[AArch64] Add a basic pattern for FACGE and FACGT

[dmgreen]

Summary

These instructions take the absolute of two values and perform a FCMGE/FCMGT between them. This patch adds some basic patterns for them.

[bipmis]

LGTM for the Vector Change.
Should this also be handled for the scalar equivalent as below

%abs1.i = tail call float @llvm.fabs.f32(float %a)
%abs1.i2 = tail call float @llvm.fabs.f32(float %b)
%cmp = fcmp oge float %abs1.i, %abs1.i2
%sext = sext i1 %cmp to i32
ret i32 %sext

[dmgreen]

Yeah I had seen the scalar instruction. Scalar usually uses fcmp instructions that set flags though, they don't set lanes to all-ones like vector instructions. We could use the scalar vacgt/vacge for the pattern you describe (so long as the result is moved from the vpr to a gpr), but I'm not sure that would come up a lot and should probably at least be handled as a separate patch.

[bipmis]

LGTM

llvm/lib/Target/AArch64/AArch64InstrInfo.td

def AArch64uaddlp   : PatFrags<(ops node:$src),
                                 (int_aarch64_neon_uaddlp node:$src)]>;
 def AArch64saddlp   : PatFrags<(ops node:$src),
                                [(AArch64saddlp_n node:$src),
                                 (int_aarch64_neon_saddlp node:$src)]>;
 def AArch64faddp     : PatFrags<(ops node:$Rn, node:$Rm),
                                 [(AArch64addp_n node:$Rn, node:$Rm),
                                  (int_aarch64_neon_faddp node:$Rn, node:$Rm)]>;
 def AArch64roundingvlshr : ComplexPattern<vAny, 2, "SelectRoundingVLShr", [AArch64vlshr]>;
+def AArch64facge     : PatFrags<(ops node:$Rn, node:$Rm),
+                                [(AArch64fcmge (fabs node:$Rn), (fabs node:$Rm)),
+                                 (int_aarch64_neon_facge node:$Rn, node:$Rm)]>;
+def AArch64facgt     : PatFrags<(ops node:$Rn, node:$Rm),
+                                [(AArch64fcmgt (fabs node:$Rn), (fabs node:$Rm)),
+                                 (int_aarch64_neon_facgt node:$Rn, node:$Rm)]>;
 
 def SDT_AArch64SETTAG : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisPtrTy<1>]>;
 def AArch64stg : SDNode<"AArch64ISD::STG", SDT_AArch64SETTAG, [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
 def AArch64stzg : SDNode<"AArch64ISD::STZG", SDT_AArch64SETTAG, [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
 def AArch64st2g : SDNode<"AArch64ISD::ST2G", SDT_AArch64SETTAG, [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
 def AArch64stz2g : SDNode<"AArch64ISD::STZ2G", SDT_AArch64SETTAG, [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
 
 def SDT_AArch64unpk : SDTypeProfile<1, 1, [

 let Predicates = [HasNEON] in {
 foreach VT = [ v2f32, v4f32, v2f64 ] in
 def : Pat<(fabs (fsub VT:$Rn, VT:$Rm)), (!cast<Instruction>("FABD"#VT) VT:$Rn, VT:$Rm)>;
 }
 let Predicates = [HasNEON, HasFullFP16] in {
 foreach VT = [ v4f16, v8f16 ] in
 def : Pat<(fabs (fsub VT:$Rn, VT:$Rm)), (!cast<Instruction>("FABD"#VT) VT:$Rn, VT:$Rm)>;
 }
-defm FACGE   : SIMDThreeSameVectorFPCmp<1,0,0b101,"facge",int_aarch64_neon_facge>;
-defm FACGT   : SIMDThreeSameVectorFPCmp<1,1,0b101,"facgt",int_aarch64_neon_facgt>;
+defm FACGE   : SIMDThreeSameVectorFPCmp<1,0,0b101,"facge",AArch64facge>;
+defm FACGT   : SIMDThreeSameVectorFPCmp<1,1,0b101,"facgt",AArch64facgt>;
 defm FADDP   : SIMDThreeSameVectorFP<1,0,0b010,"faddp", AArch64faddp>;
 defm FADD    : SIMDThreeSameVectorFP<0,0,0b010,"fadd", any_fadd>;
 defm FCMEQ   : SIMDThreeSameVectorFPCmp<0, 0, 0b100, "fcmeq", AArch64fcmeq>;
 defm FCMGE   : SIMDThreeSameVectorFPCmp<1, 0, 0b100, "fcmge", AArch64fcmge>;
 defm FCMGT   : SIMDThreeSameVectorFPCmp<1, 1, 0b100, "fcmgt", AArch64fcmgt>;
 defm FDIV    : SIMDThreeSameVectorFP<1,0,0b111,"fdiv", any_fdiv>;
 defm FMAXNMP : SIMDThreeSameVectorFP<1,0,0b000,"fmaxnmp", int_aarch64_neon_fmaxnmp>;
 defm FMAXNM  : SIMDThreeSameVectorFP<0,0,0b000,"fmaxnm", any_fmaxnum>;

llvm/test/CodeGen/AArch64/vacg.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=aarch64-none-eabi -mattr=+fullfp16 | FileCheck %s
 
 
 define <4 x i32> @gt_v4f32(<4 x float> %a, <4 x float> %b) {
 ; CHECK-LABEL: gt_v4f32:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    fabs v0.4s, v0.4s
-; CHECK-NEXT:    fabs v1.4s, v1.4s
-; CHECK-NEXT:    fcmgt v0.4s, v0.4s, v1.4s
+; CHECK-NEXT:    facgt v0.4s, v0.4s, v1.4s
 ; CHECK-NEXT:    ret
 entry:
   %vabs1.i = tail call <4 x float> @llvm.fabs.v4f32(<4 x float> %a)
   %vabs1.i2 = tail call <4 x float> @llvm.fabs.v4f32(<4 x float> %b)
   %cmp = fcmp ogt <4 x float> %vabs1.i, %vabs1.i2
   %sext = sext <4 x i1> %cmp to <4 x i32>
   ret <4 x i32> %sext
 }
 
 define <4 x i32> @ge_v4f32(<4 x float> %a, <4 x float> %b) {
 ; CHECK-LABEL: ge_v4f32:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    fabs v0.4s, v0.4s
-; CHECK-NEXT:    fabs v1.4s, v1.4s
-; CHECK-NEXT:    fcmge v0.4s, v0.4s, v1.4s
+; CHECK-NEXT:    facge v0.4s, v0.4s, v1.4s
 ; CHECK-NEXT:    ret
 entry:
   %vabs1.i = tail call <4 x float> @llvm.fabs.v4f32(<4 x float> %a)
   %vabs1.i2 = tail call <4 x float> @llvm.fabs.v4f32(<4 x float> %b)
   %cmp = fcmp oge <4 x float> %vabs1.i, %vabs1.i2
   %sext = sext <4 x i1> %cmp to <4 x i32>
   ret <4 x i32> %sext
 }
 
 define <4 x i32> @lt_v4f32(<4 x float> %a, <4 x float> %b) {
 ; CHECK-LABEL: lt_v4f32:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    fabs v0.4s, v0.4s
-; CHECK-NEXT:    fabs v1.4s, v1.4s
-; CHECK-NEXT:    fcmgt v0.4s, v1.4s, v0.4s
+; CHECK-NEXT:    facgt v0.4s, v1.4s, v0.4s
 ; CHECK-NEXT:    ret
 entry:
   %vabs1.i = tail call <4 x float> @llvm.fabs.v4f32(<4 x float> %a)
   %vabs1.i2 = tail call <4 x float> @llvm.fabs.v4f32(<4 x float> %b)
   %cmp = fcmp olt <4 x float> %vabs1.i, %vabs1.i2
   %sext = sext <4 x i1> %cmp to <4 x i32>
   ret <4 x i32> %sext
 }
 
 define <4 x i32> @le_v4f32(<4 x float> %a, <4 x float> %b) {
 ; CHECK-LABEL: le_v4f32:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    fabs v0.4s, v0.4s
-; CHECK-NEXT:    fabs v1.4s, v1.4s
-; CHECK-NEXT:    fcmge v0.4s, v1.4s, v0.4s
+; CHECK-NEXT:    facge v0.4s, v1.4s, v0.4s
 ; CHECK-NEXT:    ret
 entry:
   %vabs1.i = tail call <4 x float> @llvm.fabs.v4f32(<4 x float> %a)
   %vabs1.i2 = tail call <4 x float> @llvm.fabs.v4f32(<4 x float> %b)
   %cmp = fcmp ole <4 x float> %vabs1.i, %vabs1.i2
   %sext = sext <4 x i1> %cmp to <4 x i32>
   ret <4 x i32> %sext
 }
 
 define <2 x i32> @gt_v2f32(<2 x float> %a, <2 x float> %b) {
 ; CHECK-LABEL: gt_v2f32:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    fabs v0.2s, v0.2s
-; CHECK-NEXT:    fabs v1.2s, v1.2s
-; CHECK-NEXT:    fcmgt v0.2s, v0.2s, v1.2s
+; CHECK-NEXT:    facgt v0.2s, v0.2s, v1.2s
 ; CHECK-NEXT:    ret
 entry:
   %vabs1.i = tail call <2 x float> @llvm.fabs.v2f32(<2 x float> %a)
   %vabs1.i2 = tail call <2 x float> @llvm.fabs.v2f32(<2 x float> %b)
   %cmp = fcmp ogt <2 x float> %vabs1.i, %vabs1.i2
   %sext = sext <2 x i1> %cmp to <2 x i32>
   ret <2 x i32> %sext
 }
 
 define <2 x i32> @ge_v2f32(<2 x float> %a, <2 x float> %b) {
 ; CHECK-LABEL: ge_v2f32:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    fabs v0.2s, v0.2s
-; CHECK-NEXT:    fabs v1.2s, v1.2s
-; CHECK-NEXT:    fcmge v0.2s, v0.2s, v1.2s
+; CHECK-NEXT:    facge v0.2s, v0.2s, v1.2s
 ; CHECK-NEXT:    ret
 entry:
   %vabs1.i = tail call <2 x float> @llvm.fabs.v2f32(<2 x float> %a)
   %vabs1.i2 = tail call <2 x float> @llvm.fabs.v2f32(<2 x float> %b)
   %cmp = fcmp oge <2 x float> %vabs1.i, %vabs1.i2
   %sext = sext <2 x i1> %cmp to <2 x i32>
   ret <2 x i32> %sext
 }
 
 define <4 x i16> @gt_v4f16(<4 x half> %a, <4 x half> %b) {
 ; CHECK-LABEL: gt_v4f16:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    fabs v0.4h, v0.4h
-; CHECK-NEXT:    fabs v1.4h, v1.4h
-; CHECK-NEXT:    fcmgt v0.4h, v0.4h, v1.4h
+; CHECK-NEXT:    facgt v0.4h, v0.4h, v1.4h
 ; CHECK-NEXT:    ret
 entry:
   %vabs1.i = tail call <4 x half> @llvm.fabs.v4f16(<4 x half> %a)
   %vabs1.i2 = tail call <4 x half> @llvm.fabs.v4f16(<4 x half> %b)
   %cmp = fcmp ogt <4 x half> %vabs1.i, %vabs1.i2
   %sext = sext <4 x i1> %cmp to <4 x i16>
   ret <4 x i16> %sext
 }
 
 define <4 x i16> @ge_v4f16(<4 x half> %a, <4 x half> %b) {
 ; CHECK-LABEL: ge_v4f16:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    fabs v0.4h, v0.4h
-; CHECK-NEXT:    fabs v1.4h, v1.4h
-; CHECK-NEXT:    fcmge v0.4h, v0.4h, v1.4h
+; CHECK-NEXT:    facge v0.4h, v0.4h, v1.4h
 ; CHECK-NEXT:    ret
 entry:
   %vabs1.i = tail call <4 x half> @llvm.fabs.v4f16(<4 x half> %a)
   %vabs1.i2 = tail call <4 x half> @llvm.fabs.v4f16(<4 x half> %b)
   %cmp = fcmp oge <4 x half> %vabs1.i, %vabs1.i2
   %sext = sext <4 x i1> %cmp to <4 x i16>
   ret <4 x i16> %sext
 }
 
 define <8 x i16> @gt_v8f16(<8 x half> %a, <8 x half> %b) {
 ; CHECK-LABEL: gt_v8f16:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    fabs v0.8h, v0.8h
-; CHECK-NEXT:    fabs v1.8h, v1.8h
-; CHECK-NEXT:    fcmgt v0.8h, v0.8h, v1.8h
+; CHECK-NEXT:    facgt v0.8h, v0.8h, v1.8h
 ; CHECK-NEXT:    ret
 entry:
   %vabs1.i = tail call <8 x half> @llvm.fabs.v8f16(<8 x half> %a)
   %vabs1.i2 = tail call <8 x half> @llvm.fabs.v8f16(<8 x half> %b)
   %cmp = fcmp ogt <8 x half> %vabs1.i, %vabs1.i2
   %sext = sext <8 x i1> %cmp to <8 x i16>
   ret <8 x i16> %sext
 }
 
 define <8 x i16> @ge_v8f16(<8 x half> %a, <8 x half> %b) {
 ; CHECK-LABEL: ge_v8f16:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    fabs v0.8h, v0.8h
-; CHECK-NEXT:    fabs v1.8h, v1.8h
-; CHECK-NEXT:    fcmge v0.8h, v0.8h, v1.8h
+; CHECK-NEXT:    facge v0.8h, v0.8h, v1.8h
 ; CHECK-NEXT:    ret
 entry:
   %vabs1.i = tail call <8 x half> @llvm.fabs.v8f16(<8 x half> %a)
   %vabs1.i2 = tail call <8 x half> @llvm.fabs.v8f16(<8 x half> %b)
   %cmp = fcmp oge <8 x half> %vabs1.i, %vabs1.i2
   %sext = sext <8 x i1> %cmp to <8 x i16>
   ret <8 x i16> %sext
 }
 
 define <2 x i64> @gt_v2f64(<2 x double> %a, <2 x double> %b) {
 ; CHECK-LABEL: gt_v2f64:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    fabs v0.2d, v0.2d
-; CHECK-NEXT:    fabs v1.2d, v1.2d
-; CHECK-NEXT:    fcmgt v0.2d, v0.2d, v1.2d
+; CHECK-NEXT:    facgt v0.2d, v0.2d, v1.2d
 ; CHECK-NEXT:    ret
 entry:
   %vabs1.i = tail call <2 x double> @llvm.fabs.v2f64(<2 x double> %a)
   %vabs1.i2 = tail call <2 x double> @llvm.fabs.v2f64(<2 x double> %b)
   %cmp = fcmp ogt <2 x double> %vabs1.i, %vabs1.i2
   %sext = sext <2 x i1> %cmp to <2 x i64>
   ret <2 x i64> %sext
 }
 
 define <2 x i64> @ge_v2f64(<2 x double> %a, <2 x double> %b) {
 ; CHECK-LABEL: ge_v2f64:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    fabs v0.2d, v0.2d
-; CHECK-NEXT:    fabs v1.2d, v1.2d
-; CHECK-NEXT:    fcmge v0.2d, v0.2d, v1.2d
+; CHECK-NEXT:    facge v0.2d, v0.2d, v1.2d
 ; CHECK-NEXT:    ret
 entry:
   %vabs1.i = tail call <2 x double> @llvm.fabs.v2f64(<2 x double> %a)
   %vabs1.i2 = tail call <2 x double> @llvm.fabs.v2f64(<2 x double> %b)
   %cmp = fcmp oge <2 x double> %vabs1.i, %vabs1.i2
   %sext = sext <2 x i1> %cmp to <2 x i64>
   ret <2 x i64> %sext
 }
 
 declare <8 x half> @llvm.fabs.v8f16(<8 x half>)
 declare <4 x half> @llvm.fabs.v4f16(<4 x half>)
 declare <4 x float> @llvm.fabs.v4f32(<4 x float>)
 declare <2 x float> @llvm.fabs.v2f32(<2 x float>)
 declare <2 x double> @llvm.fabs.v2f64(<2 x double>)