[AMDGPU][GlobalISel] Add codegen support for S_INDIRECT_REG_WRITE_MOVREL_B32_V[9|10|11|12]

[foad]

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-insert-vector-elt.mir

178

How would these tests fail without your patch?

[matejam]

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-insert-vector-elt.mir

178

The compiler wouldn't select S_INDIRECT_REG_WRITE_MOVREL_B32_V9, but would select S_INDIRECT_REG_WRITE_MOVREL_B32_V16 instead.

[foad]

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-insert-vector-elt.mir

178

Then maybe precommit the tests (no review required) and rebase?

[matejam]

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-insert-vector-elt.mir

178

The reason of the MIR test failure is because of the machine verifier, without it the test passes.
"Expected a SReg_512 register, but got a SGPR_288/SGPR_320/SGPR_352/SGPR_388 register."

[foad]

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-insert-vector-elt.mir

178

Ack.

[arsenm]

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-insert-vector-elt.mir

312

are the vector cases tested for the same sizes?

[foad]

Committed in 48f6964bcbfba25e79c301b0175be327cff586d9

Mateja if you use arc diff to create the patch it will automatically add a Differential Revision: line to your commit message, and then the review will be closed automatically when you push the commit.

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

static unsigned getIndirectSGPRWriteMovRelPseudo32(unsigned VecSize) {
   if (VecSize <= 96) // 12 bytes
     return AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V3;
   if (VecSize <= 128) // 16 bytes
     return AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V4;
   if (VecSize <= 160) // 20 bytes
     return AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V5;
   if (VecSize <= 256) // 32 bytes
     return AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V8;
+  if (VecSize <= 288) // 36 bytes
+    return AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V9;
+  if (VecSize <= 320) // 40 bytes
+    return AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V10;
+  if (VecSize <= 352) // 44 bytes
+    return AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V11;
+  if (VecSize <= 384) // 48 bytes
+    return AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V12;
   if (VecSize <= 512) // 64 bytes
     return AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V16;
   if (VecSize <= 1024) // 128 bytes
     return AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V32;
 
   llvm_unreachable("unsupported size for IndirectRegWrite pseudos");
 }
 
bool SIInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
   case AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V16:
   case AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V32:
   case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V1:
   case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V2:
   case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V3:
   case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V4:
   case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V5:
   case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V8:
+  case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V9:
+  case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V10:
+  case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V11:
+  case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V12:
   case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V16:
   case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V32:
   case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B64_V1:
   case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B64_V2:
   case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B64_V4:
   case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B64_V8:
   case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B64_V16: {
     const TargetRegisterClass *EltRC = getOpRegClass(MI, 2);

llvm/lib/Target/AMDGPU/SIInstructions.td

 def V_INDIRECT_REG_WRITE_MOVREL_B32_V32 : V_INDIRECT_REG_WRITE_MOVREL_B32_pseudo<VReg_1024>;
 
 def S_INDIRECT_REG_WRITE_MOVREL_B32_V1 : S_INDIRECT_REG_WRITE_MOVREL_B32_pseudo<SReg_32>;
 def S_INDIRECT_REG_WRITE_MOVREL_B32_V2 : S_INDIRECT_REG_WRITE_MOVREL_B32_pseudo<SReg_64>;
 def S_INDIRECT_REG_WRITE_MOVREL_B32_V3 : S_INDIRECT_REG_WRITE_MOVREL_B32_pseudo<SReg_96>;
 def S_INDIRECT_REG_WRITE_MOVREL_B32_V4 : S_INDIRECT_REG_WRITE_MOVREL_B32_pseudo<SReg_128>;
 def S_INDIRECT_REG_WRITE_MOVREL_B32_V5 : S_INDIRECT_REG_WRITE_MOVREL_B32_pseudo<SReg_160>;
 def S_INDIRECT_REG_WRITE_MOVREL_B32_V8 : S_INDIRECT_REG_WRITE_MOVREL_B32_pseudo<SReg_256>;
+def S_INDIRECT_REG_WRITE_MOVREL_B32_V9 : S_INDIRECT_REG_WRITE_MOVREL_B32_pseudo<SReg_288>;
+def S_INDIRECT_REG_WRITE_MOVREL_B32_V10 : S_INDIRECT_REG_WRITE_MOVREL_B32_pseudo<SReg_320>;
+def S_INDIRECT_REG_WRITE_MOVREL_B32_V11 : S_INDIRECT_REG_WRITE_MOVREL_B32_pseudo<SReg_352>;
+def S_INDIRECT_REG_WRITE_MOVREL_B32_V12 : S_INDIRECT_REG_WRITE_MOVREL_B32_pseudo<SReg_384>;
 def S_INDIRECT_REG_WRITE_MOVREL_B32_V16 : S_INDIRECT_REG_WRITE_MOVREL_B32_pseudo<SReg_512>;
 def S_INDIRECT_REG_WRITE_MOVREL_B32_V32 : S_INDIRECT_REG_WRITE_MOVREL_B32_pseudo<SReg_1024>;
 
 def S_INDIRECT_REG_WRITE_MOVREL_B64_V1 : S_INDIRECT_REG_WRITE_MOVREL_B64_pseudo<SReg_64>;
 def S_INDIRECT_REG_WRITE_MOVREL_B64_V2 : S_INDIRECT_REG_WRITE_MOVREL_B64_pseudo<SReg_128>;
 def S_INDIRECT_REG_WRITE_MOVREL_B64_V4 : S_INDIRECT_REG_WRITE_MOVREL_B64_pseudo<SReg_256>;
 def S_INDIRECT_REG_WRITE_MOVREL_B64_V8 : S_INDIRECT_REG_WRITE_MOVREL_B64_pseudo<SReg_512>;
 def S_INDIRECT_REG_WRITE_MOVREL_B64_V16 : S_INDIRECT_REG_WRITE_MOVREL_B64_pseudo<SReg_1024>;

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-insert-vector-elt.mir

bb.0:
     %0:sgpr(<8 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
     %1:sgpr(s32) = COPY $sgpr8
     %2:sgpr(s32) = COPY $sgpr9
     %3:sgpr(<8 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
     S_ENDPGM 0, implicit %3
 ...
 
 ---
+name: insert_vector_elt_s_s32_v9s32
+legalized: true
+regBankSelected: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8, $sgpr9, $sgpr10
+
+    ; MOVREL-LABEL: name: insert_vector_elt_s_s32_v9s32
+    ; MOVREL: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8, $sgpr9, $sgpr10
+    ; MOVREL-NEXT: {{  $}}
+    ; MOVREL-NEXT: [[COPY:%[0-9]+]]:sgpr_288 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8
+    ; MOVREL-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr9
+    ; MOVREL-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr10
+    ; MOVREL-NEXT: $m0 = COPY [[COPY2]]
+    ; MOVREL-NEXT: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V9_:%[0-9]+]]:sgpr_288 = S_INDIRECT_REG_WRITE_MOVREL_B32_V9 [[COPY]], [[COPY1]], 3, implicit $m0
+    ; MOVREL-NEXT: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V9_]]
+    ; GPRIDX-LABEL: name: insert_vector_elt_s_s32_v9s32
+    ; GPRIDX: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8, $sgpr9, $sgpr10
+    ; GPRIDX-NEXT: {{  $}}
+    ; GPRIDX-NEXT: [[COPY:%[0-9]+]]:sgpr_288 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8
+    ; GPRIDX-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr9
+    ; GPRIDX-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr10
+    ; GPRIDX-NEXT: $m0 = COPY [[COPY2]]
+    ; GPRIDX-NEXT: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V9_:%[0-9]+]]:sgpr_288 = S_INDIRECT_REG_WRITE_MOVREL_B32_V9 [[COPY]], [[COPY1]], 3, implicit $m0
+    ; GPRIDX-NEXT: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V9_]]
+    %0:sgpr(<9 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8
+    %1:sgpr(s32) = COPY $sgpr9
+    %2:sgpr(s32) = COPY $sgpr10
+    %3:sgpr(<9 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
+    S_ENDPGM 0, implicit %3
+...
+
+---
+name: insert_vector_elt_s_s32_v10s32
+legalized: true
+regBankSelected: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9, $sgpr10, $sgpr11
+
+    ; MOVREL-LABEL: name: insert_vector_elt_s_s32_v10s32
+    ; MOVREL: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9, $sgpr10, $sgpr11
+    ; MOVREL-NEXT: {{  $}}
+    ; MOVREL-NEXT: [[COPY:%[0-9]+]]:sgpr_320 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9
+    ; MOVREL-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr10
+    ; MOVREL-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr11
+    ; MOVREL-NEXT: $m0 = COPY [[COPY2]]
+    ; MOVREL-NEXT: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V10_:%[0-9]+]]:sgpr_320 = S_INDIRECT_REG_WRITE_MOVREL_B32_V10 [[COPY]], [[COPY1]], 3, implicit $m0
+    ; MOVREL-NEXT: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V10_]]
+    ; GPRIDX-LABEL: name: insert_vector_elt_s_s32_v10s32
+    ; GPRIDX: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9, $sgpr10, $sgpr11
+    ; GPRIDX-NEXT: {{  $}}
+    ; GPRIDX-NEXT: [[COPY:%[0-9]+]]:sgpr_320 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9
+    ; GPRIDX-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr10
+    ; GPRIDX-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr11
+    ; GPRIDX-NEXT: $m0 = COPY [[COPY2]]
+    ; GPRIDX-NEXT: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V10_:%[0-9]+]]:sgpr_320 = S_INDIRECT_REG_WRITE_MOVREL_B32_V10 [[COPY]], [[COPY1]], 3, implicit $m0
+    ; GPRIDX-NEXT: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V10_]]
+    %0:sgpr(<10 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9
+    %1:sgpr(s32) = COPY $sgpr10
+    %2:sgpr(s32) = COPY $sgpr11
+    %3:sgpr(<10 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
+    S_ENDPGM 0, implicit %3
+...
+
+---
+name: insert_vector_elt_s_s32_v11s32
+legalized: true
+regBankSelected: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10, $sgpr11, $sgpr12
+
+    ; MOVREL-LABEL: name: insert_vector_elt_s_s32_v11s32
+    ; MOVREL: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10, $sgpr11, $sgpr12
+    ; MOVREL-NEXT: {{  $}}
+    ; MOVREL-NEXT: [[COPY:%[0-9]+]]:sgpr_352 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10
+    ; MOVREL-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr11
+    ; MOVREL-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr12
+    ; MOVREL-NEXT: $m0 = COPY [[COPY2]]
+    ; MOVREL-NEXT: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V11_:%[0-9]+]]:sgpr_352 = S_INDIRECT_REG_WRITE_MOVREL_B32_V11 [[COPY]], [[COPY1]], 3, implicit $m0
+    ; MOVREL-NEXT: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V11_]]
+    ; GPRIDX-LABEL: name: insert_vector_elt_s_s32_v11s32
+    ; GPRIDX: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10, $sgpr11, $sgpr12
+    ; GPRIDX-NEXT: {{  $}}
+    ; GPRIDX-NEXT: [[COPY:%[0-9]+]]:sgpr_352 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10
+    ; GPRIDX-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr11
+    ; GPRIDX-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr12
+    ; GPRIDX-NEXT: $m0 = COPY [[COPY2]]
+    ; GPRIDX-NEXT: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V11_:%[0-9]+]]:sgpr_352 = S_INDIRECT_REG_WRITE_MOVREL_B32_V11 [[COPY]], [[COPY1]], 3, implicit $m0
+    ; GPRIDX-NEXT: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V11_]]
+    %0:sgpr(<11 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10
+    %1:sgpr(s32) = COPY $sgpr11
+    %2:sgpr(s32) = COPY $sgpr12
+    %3:sgpr(<11 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
+    S_ENDPGM 0, implicit %3
+...
+
+---
+name: insert_vector_elt_s_s32_v12s32
+legalized: true
+regBankSelected: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11, $sgpr12, $sgpr13
+
+    ; MOVREL-LABEL: name: insert_vector_elt_s_s32_v12s32
+    ; MOVREL: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11, $sgpr12, $sgpr13
+    ; MOVREL-NEXT: {{  $}}
+    ; MOVREL-NEXT: [[COPY:%[0-9]+]]:sgpr_384 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11
+    ; MOVREL-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr12
+    ; MOVREL-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr13
+    ; MOVREL-NEXT: $m0 = COPY [[COPY2]]
+    ; MOVREL-NEXT: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V12_:%[0-9]+]]:sgpr_384 = S_INDIRECT_REG_WRITE_MOVREL_B32_V12 [[COPY]], [[COPY1]], 3, implicit $m0
+    ; MOVREL-NEXT: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V12_]]
+    ; GPRIDX-LABEL: name: insert_vector_elt_s_s32_v12s32
+    ; GPRIDX: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11, $sgpr12, $sgpr13
+    ; GPRIDX-NEXT: {{  $}}
+    ; GPRIDX-NEXT: [[COPY:%[0-9]+]]:sgpr_384 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11
+    ; GPRIDX-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr12
+    ; GPRIDX-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr13
+    ; GPRIDX-NEXT: $m0 = COPY [[COPY2]]
+    ; GPRIDX-NEXT: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V12_:%[0-9]+]]:sgpr_384 = S_INDIRECT_REG_WRITE_MOVREL_B32_V12 [[COPY]], [[COPY1]], 3, implicit $m0
+    ; GPRIDX-NEXT: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V12_]]
+    %0:sgpr(<12 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11
+    %1:sgpr(s32) = COPY $sgpr12
+    %2:sgpr(s32) = COPY $sgpr13
+    %3:sgpr(<12 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
+    S_ENDPGM 0, implicit %3
+...
+
+---
 name: insert_vector_elt_s_s32_v16s32
 legalized: true
 regBankSelected: true
 
 body: |
   bb.0:
     liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15, $sgpr16, $sgpr17