Fix placement of ampersand operator [Discarded]

llvm/lib/CodeGen/AssignmentTrackingAnalysis.cpp

while (!Worklist.empty() || !Pending.empty()) {
       }
       Worklist.swap(Pending);
       // At this point, pending must be empty, since it was just the empty
       // worklist
       assert(Pending.empty() && "Pending should be empty");
     }
 
     // Insert new location defs.
-    for (auto& Pair : BBInsertBeforeMap) {
+    for (auto &Pair : BBInsertBeforeMap) {
       InsertMap &Map = Pair.second;
-      for (auto& Pair : Map) {
+      for (auto &Pair : Map) {
         Instruction *InsertBefore = Pair.first;
         assert(InsertBefore && "should never be null");
         auto FragMemLocs = Pair.second;
         auto &Ctx = Fn.getContext();
 
-        for (auto& FragMemLoc : FragMemLocs) {
+        for (auto &FragMemLoc : FragMemLocs) {
           DIExpression *Expr = DIExpression::get(Ctx, std::nullopt);
           Expr = *DIExpression::createFragmentExpression(
               Expr, FragMemLoc.OffsetInBits, FragMemLoc.SizeInBits);
           Expr = DIExpression::prepend(Expr, DIExpression::DerefAfter,
                                        FragMemLoc.OffsetInBits / 8);
           DebugVariable Var(Aggregates[FragMemLoc.Var].first, Expr,
                             FragMemLoc.DL.getInlinedAt());
           FnVarLocs->addVarLoc(InsertBefore, Var, Expr, FragMemLoc.DL,

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

for (SDValue CurVec = InVec; CurVec;) {
       // update the shuffle mask (and second operand if we started with unary
       // shuffle) and create a new legal shuffle.
       if (CurVec.getOpcode() == ISD::VECTOR_SHUFFLE && CurVec.hasOneUse()) {
         auto *SVN = cast<ShuffleVectorSDNode>(CurVec);
         SDValue LHS = SVN->getOperand(0);
         SDValue RHS = SVN->getOperand(1);
         SmallVector<int, 16> Mask(SVN->getMask());
         bool Merged = true;
-        for (auto const& I : enumerate(Ops)) {
+        for (auto const &I : enumerate(Ops)) {
           SDValue &Op = I.value();
           if (Op) {
             SmallVector<int, 16> NewMask;
             if (!mergeEltWithShuffle(LHS, RHS, Mask, NewMask, Op, I.index())) {
               Merged = false;
               break;
             }
             Mask = std::move(NewMask);
if (!Factor)
     return SDValue();
 
   SDLoc DL(N);
   SDValue ZeroOp = DAG.getConstant(0, DL, NewScalarIntVT);
 
   // Recreate the BUILD_VECTOR, with elements now being Factor times smaller.
   SmallVector<SDValue, 16> NewOps;
   NewOps.reserve(NewIntVT.getVectorNumElements());
-  for (auto const& I : enumerate(N->ops())) {
+  for (auto const &I : enumerate(N->ops())) {
     SDValue Op = I.value();
     assert(!Op.isUndef() && "FIXME: after allowing UNDEF's, handle them here.");
     unsigned SrcOpIdx = I.index();
     if (KnownZeroOps[SrcOpIdx]) {
       NewOps.append(*Factor, ZeroOp);
       continue;
     }
     Op = DAG.getBitcast(OpIntVT, Op);

llvm/utils/TableGen/InstrInfoEmitter.cpp

private:
   std::vector<std::string> GetOperandInfo(const CodeGenInstruction &Inst);
 };
 
 } // end anonymous namespace
 
 static void PrintDefList(const std::vector<Record *> &Uses, unsigned Num,
                          raw_ostream &OS) {
   OS << "static const MCPhysReg ImplicitList" << Num << "[] = { ";
-  for (auto const& [Idx, U] : enumerate(Uses))
+  for (auto const & [Idx, U] : enumerate(Uses))
     OS << (Idx ? ", " : "") << getQualifiedName(U);
   OS << " };\n";
 }
 
 //===----------------------------------------------------------------------===//
 // Operand Info Emission.
 //===----------------------------------------------------------------------===//