[PowerPC] Enable canCombineStoreAndExtract target hook

[tingwang]

Summary

PowerPC can do store(extract-element) in one instruction. Enable this hook first, and then combiner may explore this kind of opportunities.

[shchenz]

Thank you. Implementing this function for PPC makes sense to me.

Should we add an opt test since the function is only called in an IR pass? And maybe also good to show the final assembly change with a llc test. See example when the function was introduced in ARM target https://reviews.llvm.org/D5921.

[tingwang]

Address comment: add test case to show the change.

[nemanjai]

For the most part, the code produced for vector-promotion.ll is worse as we're forcing the operations into the vector space rather than doing it in scalar registers. Perhaps we should return false from this query if the input vector is the result of a load and the only user is the extract instruction. This would of course require that we change the interface of the query to take the extract instruction rather than the type.
The idea is that if we are loading the vector, extracting an element, performing an operation and then storing, we won't really load the vector but will load only the single element. Promoting the operation will force us to load the vector which is counter productive.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

1632

Why an integer type? stxsd[x]/stfiwx/stxsiwx don't really care about whether the input vector is integer or floating point.

[tingwang]

Pattern change not good.

llvm/lib/Target/PowerPC/PPCISelLowering.h

public:
     bool isCheapToSpeculateCttz(Type *Ty) const override {
       return true;
     }
 
     bool isCheapToSpeculateCtlz(Type *Ty) const override {
       return true;
     }
 
+    bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
+                                   unsigned &Cost) const override;
+
     bool isCtlzFast() const override {
       return true;
     }
 
     bool isEqualityCmpFoldedWithSignedCmp() const override {
       return false;
     }
 

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

 bool PPCTargetLowering::hasSPE() const {
   return Subtarget.hasSPE();
 }
 
 bool PPCTargetLowering::preferIncOfAddToSubOfNot(EVT VT) const {
   return VT.isScalarInteger();
 }
 
+bool PPCTargetLowering::canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
+                                                  unsigned &Cost) const {
+  if (!Subtarget.isPPC64() || !Subtarget.hasVSX())
+    return false;
+  // Expect extract one constant-index element from integer vector.
+  if (!isa<ConstantInt>(Idx))
+    return false;
+  auto *VTy = dyn_cast<VectorType>(VectorTy);
+  if (!VTy || !VTy->getScalarType()->isIntegerTy())
+    return false;
+  // The element index defines the region that can be stored without conversion.
+  // It depends on store width and endianness.
+  unsigned BitWidth = VTy->getScalarSizeInBits();
+  unsigned ElemIdx;
+  if (BitWidth == 32 && Subtarget.hasP8Vector()) {
+    ElemIdx = Subtarget.isLittleEndian() ? 2 : 1;
+  } else if (BitWidth == 64) {
+    ElemIdx = Subtarget.isLittleEndian() ? 1 : 0;
+  } else
+    return false;
+  // Accept the combine only if the element index matches the index from extract
+  // operation.
+  if (cast<ConstantInt>(Idx)->getZExtValue() == ElemIdx) {
+    Cost = 1;
+    return true;
+  }
+  return false;
+}
+
 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
   switch ((PPCISD::NodeType)Opcode) {
   case PPCISD::FIRST_NUMBER:    break;
   case PPCISD::FSEL:            return "PPCISD::FSEL";
   case PPCISD::XSMAXC:          return "PPCISD::XSMAXC";
   case PPCISD::XSMINC:          return "PPCISD::XSMINC";
   case PPCISD::FCFID:           return "PPCISD::FCFID";
   case PPCISD::FCFIDU:          return "PPCISD::FCFIDU";

llvm/test/CodeGen/PowerPC/p10-fi-elim.ll

 ; CHECK-LABEL: test_FI_elim:
 ; CHECK:       # %bb.0: # %bb
 ; CHECK-NEXT:    mflr r0
 ; CHECK-NEXT:    std r0, 16(r1)
 ; CHECK-NEXT:    stdu r1, -80(r1)
 ; CHECK-NEXT:    .cfi_def_cfa_offset 80
 ; CHECK-NEXT:    .cfi_offset lr, 16
 ; CHECK-NEXT:    lxv v2, 0(r3)
+; CHECK-NEXT:    lbz r7, 2(r7)
 ; CHECK-NEXT:    mr r9, r6
 ; CHECK-NEXT:    mr r6, r5
-; CHECK-NEXT:    li r12, -127
-; CHECK-NEXT:    li r0, 4
-; CHECK-NEXT:    stb r12, 0(r3)
-; CHECK-NEXT:    li r2, 1
-; CHECK-NEXT:    std r0, 0(r3)
-; CHECK-NEXT:    stw r2, 0(r3)
-; CHECK-NEXT:    li r11, 3
-; CHECK-NEXT:    stb r11, 0(0)
-; CHECK-NEXT:    mfvsrd r5, v2
-; CHECK-NEXT:    vaddudm v3, v2, v2
+; CHECK-NEXT:    li r5, 3
+; CHECK-NEXT:    li r10, -127
+; CHECK-NEXT:    li r11, 4
+; CHECK-NEXT:    stb r5, 0(0)
+; CHECK-NEXT:    li r12, 1
+; CHECK-NEXT:    stb r10, 0(r3)
+; CHECK-NEXT:    std r11, 0(r3)
+; CHECK-NEXT:    stw r12, 0(r3)
+; CHECK-NEXT:    vnegd v3, v2
+; CHECK-NEXT:    vaddudm v4, v2, v2
 ; CHECK-NEXT:    pstxv v2, 64(r1), 0
-; CHECK-NEXT:    neg r5, r5
-; CHECK-NEXT:    mfvsrd r10, v3
-; CHECK-NEXT:    std r5, 0(r3)
-; CHECK-NEXT:    lbz r5, 2(r7)
+; CHECK-NEXT:    stxsd v3, 0(r3)
+; CHECK-NEXT:    stb r5, 0(r3)
+; CHECK-NEXT:    rlwinm r5, r7, 0, 27, 27
 ; CHECK-NEXT:    mr r7, r9
-; CHECK-NEXT:    stb r11, 0(r3)
-; CHECK-NEXT:    stb r12, 0(r3)
-; CHECK-NEXT:    std r2, 0(r3)
-; CHECK-NEXT:    neg r10, r10
-; CHECK-NEXT:    rlwinm r5, r5, 0, 27, 27
+; CHECK-NEXT:    stb r10, 0(r3)
+; CHECK-NEXT:    std r12, 0(r3)
+; CHECK-NEXT:    vnegd v2, v4
 ; CHECK-NEXT:    stb r5, 0(0)
 ; CHECK-NEXT:    lbz r5, 2(r8)
 ; CHECK-NEXT:    rlwinm r5, r5, 0, 27, 27
 ; CHECK-NEXT:    stb r5, 0(r3)
 ; CHECK-NEXT:    li r5, 2
-; CHECK-NEXT:    std r0, 0(r3)
+; CHECK-NEXT:    std r11, 0(r3)
 ; CHECK-NEXT:    stw r5, 0(r3)
 ; CHECK-NEXT:    mr r5, r4
-; CHECK-NEXT:    std r10, 0(r3)
+; CHECK-NEXT:    stxsd v2, 0(r3)
 ; CHECK-NEXT:    bl foo@notoc
 ; CHECK-NEXT:    extsw r3, r3
 ; CHECK-NEXT:    addi r1, r1, 80
 ; CHECK-NEXT:    ld r0, 16(r1)
 ; CHECK-NEXT:    mtlr r0
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test_FI_elim: