[AArch64] Add asm aliases for MOV, LDR, STR with predicate-as-counter

[CarolineConcatto]

Summary

In the 2022-12 release of the A64 ISA it was updated that the assembler must
also accept predicate-as-counter register names for the source predicate
register and the destination predicate register for:

• *MOV: Move predicate (unpredicated)*
• *LDR (predicate): Load predicate register*
• *STR (predicate): Store predicate register*

[sdesmalen]

llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

2207

nit: please remove newline

[sdesmalen]

Sorry for the quick turn-around here, but I just realise that we probably want to guard these aliases with HasSVE2p1_or_HasSME2, because without those features the concept of a predicate-as-counter does not exist. I see that we haven't done this for pfalse either.

[CarolineConcatto]

• Allow the alias to be used only when sve2.1 or sme2 are enabled.

[CarolineConcatto]

• Remove extra space

[sdesmalen]

llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

3847

nit: Could you add a comment here saying that these are aliases for existing (SVE) instructions for which predicate-as-counter can be accepted as an operand to the instruction?

llvm/test/MC/AArch64/SVE/ldr_alias.s

1 ↗

(On Diff #506538)

Is it worth combining these tests into a single predicate-as-counter-aliases.s test?

llvm/test/MC/AArch64/SVE/orr.s

156

nit: unrelated whitespace change?

[CarolineConcatto]

-Paste all the tests for the predicate-as-counter in one file

llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

 } // End HasBF16, HasSVEorSME
 
 let Predicates = [HasSVEorSME] in {
   // InstAliases
   def : InstAlias<"mov $Zd, $Zn",
                   (ORR_ZZZ ZPR64:$Zd, ZPR64:$Zn, ZPR64:$Zn), 1>;
   def : InstAlias<"mov $Pd, $Pg/m, $Pn",
                   (SEL_PPPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPR8:$Pd), 1>;
+
   def : InstAlias<"mov $Pd, $Pn",
                   (ORR_PPzPP PPR8:$Pd, PPR8:$Pn, PPR8:$Pn, PPR8:$Pn), 1>;
+  def : InstAlias<"mov $Pd, $Pn",
+                  (ORR_PPzPP PNR8:$Pd, PNR8:$Pn, PNR8:$Pn, PNR8:$Pn), 0>;
+
   def : InstAlias<"mov $Pd, $Pg/z, $Pn",
                   (AND_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPR8:$Pn), 1>;
 
   def : InstAlias<"movs $Pd, $Pn",
                   (ORRS_PPzPP PPR8:$Pd, PPR8:$Pn, PPR8:$Pn, PPR8:$Pn), 1>;
   def : InstAlias<"movs $Pd, $Pg/z, $Pn",
                   (ANDS_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPR8:$Pn), 1>;
 

 defm WHILEGE_CXX  : sve2p1_int_while_rr_pn<"whilege", 0b000>;
 defm WHILEGT_CXX  : sve2p1_int_while_rr_pn<"whilegt", 0b001>;
 defm WHILELT_CXX  : sve2p1_int_while_rr_pn<"whilelt", 0b010>;
 defm WHILELE_CXX  : sve2p1_int_while_rr_pn<"whilele", 0b011>;
 defm WHILEHS_CXX  : sve2p1_int_while_rr_pn<"whilehs", 0b100>;
 defm WHILEHI_CXX  : sve2p1_int_while_rr_pn<"whilehi", 0b101>;
 defm WHILELO_CXX  : sve2p1_int_while_rr_pn<"whilelo", 0b110>;
 defm WHILELS_CXX  : sve2p1_int_while_rr_pn<"whilels", 0b111>;
 } // End HasSVE2p1_or_HasSME2
 
 //===----------------------------------------------------------------------===//
 // SVE2.1 non-widening BFloat16 to BFloat16 instructions
 //===----------------------------------------------------------------------===//
 
 let Predicates = [HasSVE2p1_or_HasSME2p1, HasB16B16] in {
 def BFADD_ZZZ : sve_fp_3op_u_zd<0b00, 0b000, "bfadd", ZPR16>;
 def BFSUB_ZZZ : sve_fp_3op_u_zd<0b00, 0b001, "bfsub", ZPR16>;

llvm/lib/Target/AArch64/SVEInstrFormats.td

: I<(outs), (ins PPRAny:$Pt, GPR64sp:$Rn, simm9:$imm9),
   let mayStore = 1;
 }
 
 multiclass sve_mem_p_spill<string asm> {
   def NAME : sve_mem_p_spill<asm>;
 
   def : InstAlias<asm # "\t$Pt, [$Rn]",
                   (!cast<Instruction>(NAME) PPRAny:$Pt, GPR64sp:$Rn, 0), 1>;
+
+  def : InstAlias<asm # "\t$Pt, [$Rn, $imm9, mul vl]",
+                  (!cast<Instruction>(NAME) PNRAny:$Pt, GPR64sp:$Rn, simm9:$imm9), 0>;
+
+  def : InstAlias<asm # "\t$Pt, [$Rn]",
+                  (!cast<Instruction>(NAME) PNRAny:$Pt, GPR64sp:$Rn, 0), 0>;
 }
 
 //===----------------------------------------------------------------------===//
 // SVE Permute - Predicates Group
 //===----------------------------------------------------------------------===//
 
 class sve_int_perm_bin_perm_pp<bits<3> opc, bits<2> sz8_64, string asm,
                                PPRRegOp pprty, SDPatternOperator op>
: I<(outs PPRAny:$Pt), (ins GPR64sp:$Rn, simm9:$imm9),
   let mayLoad = 1;
 }
 
 multiclass sve_mem_p_fill<string asm> {
   def NAME : sve_mem_p_fill<asm>;
 
   def : InstAlias<asm # "\t$Pt, [$Rn]",
                   (!cast<Instruction>(NAME) PPRAny:$Pt, GPR64sp:$Rn, 0), 1>;
+
+  def : InstAlias<asm # "\t$Pt, [$Rn, $imm9, mul vl]",
+                  (!cast<Instruction>(NAME) PNRAny:$Pt, GPR64sp:$Rn, simm9:$imm9), 0>;
+
+  def : InstAlias<asm # "\t$Pt, [$Rn]",
+                  (!cast<Instruction>(NAME) PNRAny:$Pt, GPR64sp:$Rn, 0), 0>;
 }
 
 class sve2_mem_gldnt_vs_base<bits<5> opc, dag iops, string asm,
                              RegisterOperand VecList>
 : I<(outs VecList:$Zt), iops,
   asm, "\t$Zt, $Pg/z, [$Zn, $Rm]",
   "",
   []>, Sched<[]> {

llvm/test/MC/AArch64/SVE/ldr.s

 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: 85a001a7 <unknown>
 
 ldr     p5, [x10, #255, mul vl]
 // CHECK-INST: ldr     p5, [x10, #255, mul vl]
 // CHECK-ENCODING: [0x45,0x1d,0x9f,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: 859f1d45 <unknown>
+
+ldr     pn0, [x0]
+// CHECK-INST: ldr     p0, [x0]
+// CHECK-ENCODING: [0x00,0x00,0x80,0x85]
+// CHECK-ERROR: instruction requires: sve or sme
+// CHECK-UNKNOWN: 85800000 <unknown>
+
+ldr     pn5, [x10, #255, mul vl]
+// CHECK-INST: ldr     p5, [x10, #255, mul vl]
+// CHECK-ENCODING: [0x45,0x1d,0x9f,0x85]
+// CHECK-ERROR: instruction requires: sve or sme
+// CHECK-UNKNOWN: 859f1d45 <unknown>

llvm/test/MC/AArch64/SVE/orr.s

 // CHECK-UNKNOWN: 046831b7 <unknown>
 
 orr     z23.b, z13.b, z8.b  // should not use mov-alias
 // CHECK-INST: orr     z23.d, z13.d, z8.d
 // CHECK-ENCODING: [0xb7,0x31,0x68,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: 046831b7 <unknown>
 
-
+mov     pn0.b, pn0.b
+// CHECK-INST: mov     p0.b, p0.b
+// CHECK-ENCODING: [0x00,0x40,0x80,0x25]
+// CHECK-ERROR: instruction requires: sve or sme
+// CHECK-UNKNOWN: 25804000 <unknown>
 // --------------------------------------------------------------------------//
 // Test compatibility with MOVPRFX instruction.
 
 movprfx z4.d, p7/z, z6.d
 // CHECK-INST: movprfx  z4.d, p7/z, z6.d
 // CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: 04d03cc4 <unknown>

llvm/test/MC/AArch64/SVE/str.s

 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: e5a003ef <unknown>
 
 str     p5, [x10, #255, mul vl]
 // CHECK-INST: str     p5, [x10, #255, mul vl]
 // CHECK-ENCODING: [0x45,0x1d,0x9f,0xe5]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: e59f1d45 <unknown>
+
+str     pn0, [x0]
+// CHECK-INST: str     p0, [x0]
+// CHECK-ENCODING: [0x00,0x00,0x80,0xe5]
+// CHECK-ERROR: instruction requires: sve or sme
+// CHECK-UNKNOWN: e5800000 <unknown>
+
+str     pn5, [x10, #255, mul vl]
+// CHECK-INST: str     p5, [x10, #255, mul vl]
+// CHECK-ENCODING: [0x45,0x1d,0x9f,0xe5]
+// CHECK-ERROR: instruction requires: sve or sme
+// CHECK-UNKNOWN: e59f1d45 <unknown>