[AArch64] Add asm aliases for MOV, LDR, STR with predicate-as-counter

[CarolineConcatto]

Summary

In the 2022-12 release of the A64 ISA it was updated that the assembler must
also accept predicate-as-counter register names for the source predicate
register and the destination predicate register for:

• *MOV: Move predicate (unpredicated)*
• *LDR (predicate): Load predicate register*
• *STR (predicate): Store predicate register*

[sdesmalen]

llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

2211

nit: please remove newline

[sdesmalen]

Sorry for the quick turn-around here, but I just realise that we probably want to guard these aliases with HasSVE2p1_or_HasSME2, because without those features the concept of a predicate-as-counter does not exist. I see that we haven't done this for pfalse either.

[CarolineConcatto]

• Allow the alias to be used only when sve2.1 or sme2 are enabled.

[CarolineConcatto]

• Remove extra space

[sdesmalen]

llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

3847

nit: Could you add a comment here saying that these are aliases for existing (SVE) instructions for which predicate-as-counter can be accepted as an operand to the instruction?

llvm/test/MC/AArch64/SVE/ldr_alias.s

1 ↗

(On Diff #506538)

Is it worth combining these tests into a single predicate-as-counter-aliases.s test?

llvm/test/MC/AArch64/SVE/orr.s

156 ↗

(On Diff #506538)

nit: unrelated whitespace change?

[CarolineConcatto]

-Paste all the tests for the predicate-as-counter in one file

llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

 } // End HasBF16, HasSVEorSME
 
 let Predicates = [HasSVEorSME] in {
   // InstAliases
   def : InstAlias<"mov $Zd, $Zn",
                   (ORR_ZZZ ZPR64:$Zd, ZPR64:$Zn, ZPR64:$Zn), 1>;
   def : InstAlias<"mov $Pd, $Pg/m, $Pn",
                   (SEL_PPPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPR8:$Pd), 1>;
   def : InstAlias<"mov $Pd, $Pn",
                   (ORR_PPzPP PPR8:$Pd, PPR8:$Pn, PPR8:$Pn, PPR8:$Pn), 1>;
   def : InstAlias<"mov $Pd, $Pg/z, $Pn",
                   (AND_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPR8:$Pn), 1>;
 
   def : InstAlias<"movs $Pd, $Pn",
                   (ORRS_PPzPP PPR8:$Pd, PPR8:$Pn, PPR8:$Pn, PPR8:$Pn), 1>;
   def : InstAlias<"movs $Pd, $Pg/z, $Pn",
                   (ANDS_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPR8:$Pn), 1>;

 defm WHILEGE_CXX  : sve2p1_int_while_rr_pn<"whilege", 0b000>;
 defm WHILEGT_CXX  : sve2p1_int_while_rr_pn<"whilegt", 0b001>;
 defm WHILELT_CXX  : sve2p1_int_while_rr_pn<"whilelt", 0b010>;
 defm WHILELE_CXX  : sve2p1_int_while_rr_pn<"whilele", 0b011>;
 defm WHILEHS_CXX  : sve2p1_int_while_rr_pn<"whilehs", 0b100>;
 defm WHILEHI_CXX  : sve2p1_int_while_rr_pn<"whilehi", 0b101>;
 defm WHILELO_CXX  : sve2p1_int_while_rr_pn<"whilelo", 0b110>;
 defm WHILELS_CXX  : sve2p1_int_while_rr_pn<"whilels", 0b111>;
+
+
+// Aliases for existing SVE instructions for which predicate-as-counter are
+// accepted as an operand to the instruction
+def : InstAlias<"ldr $Pt, [$Rn, $imm9, mul vl]",
+               (LDR_PXI PNRAny:$Pt, GPR64sp:$Rn, simm9:$imm9), 0>;
+def : InstAlias<"ldr $Pt, [$Rn]",
+               (LDR_PXI PNRAny:$Pt, GPR64sp:$Rn, 0), 0>;
+
+def : InstAlias<"str $Pt, [$Rn, $imm9, mul vl]",
+               (STR_PXI PNRAny:$Pt, GPR64sp:$Rn, simm9:$imm9), 0>;
+def : InstAlias<"str $Pt, [$Rn]",
+               (STR_PXI PNRAny:$Pt, GPR64sp:$Rn, 0), 0>;
+
+def : InstAlias<"mov $Pd, $Pn",
+               (ORR_PPzPP PNR8:$Pd, PNR8:$Pn, PNR8:$Pn, PNR8:$Pn), 0>;
+
+def : InstAlias<"pfalse\t$Pd", (PFALSE PNR8:$Pd), 0>;
+
 } // End HasSVE2p1_or_HasSME2
 
 //===----------------------------------------------------------------------===//
 // SVE2.1 non-widening BFloat16 to BFloat16 instructions
 //===----------------------------------------------------------------------===//
 
 let Predicates = [HasSVE2p1_or_HasSME2p1, HasB16B16] in {
 def BFADD_ZZZ : sve_fp_3op_u_zd<0b00, 0b000, "bfadd", ZPR16>;

llvm/lib/Target/AArch64/SVEInstrFormats.td

: I<(outs PPR8:$Pd), (ins),
 
   let hasSideEffects = 0;
   let isReMaterializable = 1;
 }
 
 multiclass sve_int_pfalse<bits<6> opc, string asm> {
   def NAME : sve_int_pfalse<opc, asm>;
 
-  def : InstAlias<"pfalse\t$Pd", (!cast<Instruction>(NAME) PNR8:$Pd), 0>;
-
   def : Pat<(nxv16i1 immAllZerosV), (!cast<Instruction>(NAME))>;
   def : Pat<(nxv8i1 immAllZerosV), (!cast<Instruction>(NAME))>;
   def : Pat<(nxv4i1 immAllZerosV), (!cast<Instruction>(NAME))>;
   def : Pat<(nxv2i1 immAllZerosV), (!cast<Instruction>(NAME))>;
   def : Pat<(nxv1i1 immAllZerosV), (!cast<Instruction>(NAME))>;
 }
 
 class sve_int_ptest<bits<6> opc, string asm, SDPatternOperator op>

llvm/test/MC/AArch64/SVE/pfalse.s

 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
 // RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s \
 // RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:   | llvm-objdump -d --mattr=-sve - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
 pfalse p15.b
 // CHECK-INST: pfalse p15.b
 // CHECK-ENCODING: [0x0f,0xe4,0x18,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
 // CHECK-UNKNOWN: 2518e40f <unknown>
-
-pfalse pn15.b
-// CHECK-INST: pfalse  p15.b
-// CHECK-ENCODING: [0x0f,0xe4,0x18,0x25]
-// CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 2518e40f <unknown>

llvm/test/MC/AArch64/SVE/predicate-as-counter-aliases.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p1 < %s \
+// RUN:        | llvm-objdump --no-print-imm-hex -d --mattr=+sve2p1 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p1 < %s \
+// RUN:   | llvm-objdump --no-print-imm-hex -d --mattr=-sve - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+
+ldr     pn0, [x0]
+// CHECK-INST: ldr     p0, [x0]
+// CHECK-ENCODING: [0x00,0x00,0x80,0x85]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 85800000 <unknown>
+
+ldr     pn5, [x10, #255, mul vl]
+// CHECK-INST: ldr     p5, [x10, #255, mul vl]
+// CHECK-ENCODING: [0x45,0x1d,0x9f,0x85]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 859f1d45 <unknown>
+
+
+str     pn0, [x0]
+// CHECK-INST: str     p0, [x0]
+// CHECK-ENCODING: [0x00,0x00,0x80,0xe5]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: e5800000 <unknown>
+
+str     pn5, [x10, #255, mul vl]
+// CHECK-INST: str     p5, [x10, #255, mul vl]
+// CHECK-ENCODING: [0x45,0x1d,0x9f,0xe5]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: e59f1d45 <unknown>
+
+
+mov     pn0.b, pn0.b
+// CHECK-INST: mov     p0.b, p0.b
+// CHECK-ENCODING: [0x00,0x40,0x80,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 25804000 <unknown>
+
+
+pfalse pn15.b
+// CHECK-INST: pfalse  p15.b
+// CHECK-ENCODING: [0x0f,0xe4,0x18,0x25]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 2518e40f <unknown>