[AArch64] Add hex comments to mov-imm spellings in the InstPrinter

[jroelofs]

llvm/test/CodeGen/AArch64/movw-consts.ll

157

Would it be better if the comment's bitwidth matched the register's bitwidth?

[paquette]

llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp

317

static_cast is more greppable

[Gerolf]

The cases you changed *LGTM* (really good to me!! :-)) I did not check that all cases are covered, but this shouldn't hold up the merge.

[paquette]

LGTM

[paquette]

llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp

316

this could be factored out into a function?

llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp

if ((Opcode == AArch64::MOVKXi || Opcode == AArch64::MOVKWi) &&
     O << "\tmovk\t";
     printRegName(O, MI->getOperand(0).getReg());
     O << ", " << markup("<imm:") << "#";
     MI->getOperand(2).getExpr()->print(O, &MAI);
     O << markup(">");
     return;
   }
 
+  auto PrintMovImm = [&](uint64_t Value, int RegWidth) {
+    int64_t SExtVal = SignExtend64(Value, RegWidth);
+    O << "\tmov\t";
+    printRegName(O, MI->getOperand(0).getReg());
+    O << ", " << markup("<imm:") << "#"
+      << formatImm(SExtVal) << markup(">");
+    if (CommentStream) {
+      // Do the opposite to that used for instruction operands.
+      if (getPrintImmHex())
+        *CommentStream << '=' << formatDec(SExtVal) << '\n';
+      else {
+        uint64_t Mask = maskTrailingOnes<uint64_t>(RegWidth);
+        *CommentStream << '=' << formatHex(SExtVal & Mask) << '\n';
+      }
+    }
+  };
+
   // MOVZ, MOVN and "ORR wzr, #imm" instructions are aliases for MOV, but their
   // domains overlap so they need to be prioritized. The chain is "MOVZ lsl #0 >
   // MOVZ lsl #N > MOVN lsl #0 > MOVN lsl #N > ORR". The highest instruction
   // that can represent the move is the MOV alias, and the rest get printed
   // normally.
   if ((Opcode == AArch64::MOVZXi || Opcode == AArch64::MOVZWi) &&
       MI->getOperand(1).isImm() && MI->getOperand(2).isImm()) {
     int RegWidth = Opcode == AArch64::MOVZXi ? 64 : 32;
     int Shift = MI->getOperand(2).getImm();
     uint64_t Value = (uint64_t)MI->getOperand(1).getImm() << Shift;
 
     if (AArch64_AM::isMOVZMovAlias(Value, Shift,
                                    Opcode == AArch64::MOVZXi ? 64 : 32)) {
-      O << "\tmov\t";
-      printRegName(O, MI->getOperand(0).getReg());
-      O << ", " << markup("<imm:") << "#"
-        << formatImm(SignExtend64(Value, RegWidth)) << markup(">");
+      PrintMovImm(Value, RegWidth);
       return;
     }
   }
 
   if ((Opcode == AArch64::MOVNXi || Opcode == AArch64::MOVNWi) &&
       MI->getOperand(1).isImm() && MI->getOperand(2).isImm()) {
     int RegWidth = Opcode == AArch64::MOVNXi ? 64 : 32;
     int Shift = MI->getOperand(2).getImm();
     uint64_t Value = ~((uint64_t)MI->getOperand(1).getImm() << Shift);
     if (RegWidth == 32)
       Value = Value & 0xffffffff;
 
     if (AArch64_AM::isMOVNMovAlias(Value, Shift, RegWidth)) {
-      O << "\tmov\t";
-      printRegName(O, MI->getOperand(0).getReg());
-      O << ", " << markup("<imm:") << "#"
-        << formatImm(SignExtend64(Value, RegWidth)) << markup(">");
+      PrintMovImm(Value, RegWidth);
       return;
     }
   }
 
   if ((Opcode == AArch64::ORRXri || Opcode == AArch64::ORRWri) &&
       (MI->getOperand(1).getReg() == AArch64::XZR ||
        MI->getOperand(1).getReg() == AArch64::WZR) &&
       MI->getOperand(2).isImm()) {
     int RegWidth = Opcode == AArch64::ORRXri ? 64 : 32;
     uint64_t Value = AArch64_AM::decodeLogicalImmediate(
         MI->getOperand(2).getImm(), RegWidth);
     if (!AArch64_AM::isAnyMOVWMovAlias(Value, RegWidth)) {
-      O << "\tmov\t";
-      printRegName(O, MI->getOperand(0).getReg());
-      O << ", " << markup("<imm:") << "#"
-        << formatImm(SignExtend64(Value, RegWidth)) << markup(">");
+      PrintMovImm(Value, RegWidth);
       return;
     }
   }
 
   if (Opcode == AArch64::SPACE) {
     O << '\t' << MAI.getCommentString() << " SPACE "
       << MI->getOperand(1).getImm();
     printAnnotation(O, Annot);

llvm/test/CodeGen/AArch64/movw-consts.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -o - %s -mtriple=arm64-apple-ios7.0 | FileCheck %s
 
 define i64 @test0() {
 ; CHECK-LABEL: test0:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    mov x0, xzr
 ; CHECK-NEXT:    ret
 ; Not produced by move wide instructions, but good to make sure we can return 0 anyway:
   ret i64 0
 }
 
 define i64 @test1() {
 ; CHECK-LABEL: test1:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    mov w0, #1
+; CHECK-NEXT:    mov w0, #1 ; =0x1
 ; CHECK-NEXT:    ret
   ret i64 1
 }
 
 define i64 @test2() {
 ; CHECK-LABEL: test2:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    mov w0, #65535
+; CHECK-NEXT:    mov w0, #65535 ; =0xffff
 ; CHECK-NEXT:    ret
   ret i64 65535
 }
 
 define i64 @test3() {
 ; CHECK-LABEL: test3:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    mov w0, #65536
+; CHECK-NEXT:    mov w0, #65536 ; =0x10000
 ; CHECK-NEXT:    ret
   ret i64 65536
 }
 
 define i64 @test4() {
 ; CHECK-LABEL: test4:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    mov w0, #-65536
+; CHECK-NEXT:    mov w0, #-65536 ; =0xffff0000
 ; CHECK-NEXT:    ret
   ret i64 4294901760
 }
 
 define i64 @test5() {
 ; CHECK-LABEL: test5:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    mov x0, #4294967296
+; CHECK-NEXT:    mov x0, #4294967296 ; =0x100000000
 ; CHECK-NEXT:    ret
   ret i64 4294967296
 }
 
 define i64 @test6() {
 ; CHECK-LABEL: test6:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    mov x0, #281470681743360
+; CHECK-NEXT:    mov x0, #281470681743360 ; =0xffff00000000
 ; CHECK-NEXT:    ret
   ret i64 281470681743360
 }
 
 define i64 @test7() {
 ; CHECK-LABEL: test7:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    mov x0, #281474976710656
+; CHECK-NEXT:    mov x0, #281474976710656 ; =0x1000000000000
 ; CHECK-NEXT:    ret
   ret i64 281474976710656
 }
 
 ; A 32-bit MOVN can generate some 64-bit patterns that a 64-bit one
 ; couldn't. Useful even for i64
 define i64 @test8() {
 ; CHECK-LABEL: test8:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    mov w0, #-60876
+; CHECK-NEXT:    mov w0, #-60876 ; =0xffff1234
 ; CHECK-NEXT:    ret
   ret i64 4294906420
 }
 
 define i64 @test9() {
 ; CHECK-LABEL: test9:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    mov x0, #-1
+; CHECK-NEXT:    mov x0, #-1 ; =0xffffffffffffffff
 ; CHECK-NEXT:    ret
   ret i64 -1
 }
 
 define i64 @test10() {
 ; CHECK-LABEL: test10:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    mov x0, #-3989504001
+; CHECK-NEXT:    mov x0, #-3989504001 ; =0xffffffff1234ffff
 ; CHECK-NEXT:    ret
   ret i64 18446744069720047615
 }
 
 ; For reasonably legitimate reasons returning an i32 results in the
 ; selection of an i64 constant, so we need a different idiom to test that selection
 @var32 = global i32 0
 
 define void @test11() {
 ; CHECK-LABEL: test11:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    adrp x8, _var32@PAGE
 ; CHECK-NEXT:    str wzr, [x8, _var32@PAGEOFF]
 ; CHECK-NEXT:    ret
   store i32 0, ptr @var32
   ret void
 }
 
 define void @test12() {
 ; CHECK-LABEL: test12:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    adrp x8, _var32@PAGE
-; CHECK-NEXT:    mov w9, #1
+; CHECK-NEXT:    mov w9, #1 ; =0x1
 ; CHECK-NEXT:    str w9, [x8, _var32@PAGEOFF]
 ; CHECK-NEXT:    ret
   store i32 1, ptr @var32
   ret void
 }
 
 define void @test13() {
 ; CHECK-LABEL: test13:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    adrp x8, _var32@PAGE
-; CHECK-NEXT:    mov w9, #65535
+; CHECK-NEXT:    mov w9, #65535 ; =0xffff
 ; CHECK-NEXT:    str w9, [x8, _var32@PAGEOFF]
 ; CHECK-NEXT:    ret
   store i32 65535, ptr @var32
   ret void
 }
 
 define void @test14() {
 ; CHECK-LABEL: test14:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    adrp x8, _var32@PAGE
-; CHECK-NEXT:    mov w9, #65536
+; CHECK-NEXT:    mov w9, #65536 ; =0x10000
 ; CHECK-NEXT:    str w9, [x8, _var32@PAGEOFF]
 ; CHECK-NEXT:    ret
   store i32 65536, ptr @var32
   ret void
 }
 
 define void @test15() {
 ; CHECK-LABEL: test15:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    adrp x8, _var32@PAGE
-; CHECK-NEXT:    mov w9, #-65536
+; CHECK-NEXT:    mov w9, #-65536 ; =0xffff0000
 ; CHECK-NEXT:    str w9, [x8, _var32@PAGEOFF]
 ; CHECK-NEXT:    ret
   store i32 4294901760, ptr @var32
   ret void
 }
 
 define void @test16() {
 ; CHECK-LABEL: test16:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    adrp x8, _var32@PAGE
-; CHECK-NEXT:    mov w9, #-1
+; CHECK-NEXT:    mov w9, #-1 ; =0xffffffff
 ; CHECK-NEXT:    str w9, [x8, _var32@PAGEOFF]
 ; CHECK-NEXT:    ret
   store i32 -1, ptr @var32
   ret void
 }
 
 define i64 @test17() {
 ; CHECK-LABEL: test17:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    mov x0, #-3
+; CHECK-NEXT:    mov x0, #-3 ; =0xfffffffffffffffd
 ; CHECK-NEXT:    ret
 
   ; Mustn't MOVN w0 here.
   ret i64 -3
 }