[X86][MC] Emit instructions into SmallVector

[aengelke]

Summary

Depends on D145791

Storing instruction bytes directly in a SmallVector instead of a
raw_ostream yields better encoding performance (in some applications,
the improvment is ~1% of the complete back-end time).

[RKSimon]

It'd be very useful to know why replacing raw_svector_ostream (which is really just a SmallVectorImpl<char> wrapper itself) is so much slower than using SmallVector directly

[aengelke]

It essentially boils down to having function calls for every written byte, which adds up. I haven't tested with (Thin)LTO yet, but a quick glance at the disassembly of a Fedora-built LLVM (which uses ThinLTO) seems to indicate that such function calls are not eliminated.

[MaskRay]

I have an analysis of the code path: https://reviews.llvm.org/D145791#4185609
There are some if conditions, virtual function calls, SmallVector range append overhead which cannot be eliminated.

[Amir]

Please also take care of BOLT call sites.

[aengelke]

No changes, just to trigger rebuild from updated D145791.

[aengelke]

Formatting fixes

[aengelke]

@Amir The BOLT problems were already addressed with an updated version of D145791; this patch should not affect any BOLT uses. Tests also pass now.

[Amir]

No objections now, and MaskRay has approved it so feel free to land

llvm/include/llvm/MC/MCCodeEmitter.h

 public:
   MCCodeEmitter(const MCCodeEmitter &) = delete;
   MCCodeEmitter &operator=(const MCCodeEmitter &) = delete;
   virtual ~MCCodeEmitter();
 
   /// Lifetime management
   virtual void reset() {}
 
-  /// Emit the prefixes of given instruction on the output stream.
+  /// Append the prefixes of given instruction to the code buffer.
   ///
   /// \param Inst a single low-level machine instruction.
-  /// \param OS output stream.
-  virtual void emitPrefix(const MCInst &Inst, raw_ostream &OS,
+  /// \param CB code buffer
+  virtual void emitPrefix(const MCInst &Inst, SmallVectorImpl<char> &CB,
                           const MCSubtargetInfo &STI) const {}
   /// EncodeInstruction - Encode the given \p Inst to bytes and append to \p CB.
   virtual void encodeInstruction(const MCInst &Inst, SmallVectorImpl<char> &CB,
                                  SmallVectorImpl<MCFixup> &Fixups,
                                  const MCSubtargetInfo &STI) const;
 };
 
 } // end namespace llvm
 
 #endif // LLVM_MC_MCCODEEMITTER_H

llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp

bool X86AsmBackend::padInstructionViaPrefix(MCRelaxableFragment &RF,
 
   const unsigned OldSize = RF.getContents().size();
   if (OldSize == 15)
     return false;
 
   const unsigned MaxPossiblePad = std::min(15 - OldSize, RemainingSize);
   const unsigned RemainingPrefixSize = [&]() -> unsigned {
     SmallString<15> Code;
-    raw_svector_ostream VecOS(Code);
-    Emitter.emitPrefix(RF.getInst(), VecOS, STI);
+    Emitter.emitPrefix(RF.getInst(), Code, STI);
     assert(Code.size() < 15 && "The number of prefixes must be less than 15.");
 
     // TODO: It turns out we need a decent amount of plumbing for the target
     // specific bits to determine number of prefixes its safe to add.  Various
     // targets (older chips mostly, but also Atom family) encounter decoder
     // stalls with too many prefixes.  For testing purposes, we set the value
     // externally for the moment.
     unsigned ExistingPrefixSize = Code.size();

llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp

 #include "llvm/MC/MCInst.h"
 #include "llvm/MC/MCInstrDesc.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/MC/MCSymbol.h"
 #include "llvm/Support/Casting.h"
 #include "llvm/Support/ErrorHandling.h"
-#include "llvm/Support/raw_ostream.h"
 #include <cassert>
 #include <cstdint>
 #include <cstdlib>
 
 using namespace llvm;
 
 #define DEBUG_TYPE "mccodeemitter"
 
 namespace {
 
 enum PrefixKind { None, REX, XOP, VEX2, VEX3, EVEX };
 
-static void emitByte(uint8_t C, raw_ostream &OS) { OS << static_cast<char>(C); }
+static void emitByte(uint8_t C, SmallVectorImpl<char> &CB) { CB.push_back(C); }
 
 class X86OpcodePrefixHelper {
   // REX (1 byte)
   // +-----+ +------+
   // | 40H | | WRXB |
   // +-----+ +------+
 
   // XOP (3-byte)
case EVEX:
       break;
     case VEX2:
       Kind = (W | X | B | (VEX_5M != 1)) ? VEX3 : VEX2;
       break;
     }
     return Kind;
   }
 
-  void emit(raw_ostream &OS) const {
+  void emit(SmallVectorImpl<char> &CB) const {
     uint8_t FirstPayload =
         ((~R) & 0x1) << 7 | ((~X) & 0x1) << 6 | ((~B) & 0x1) << 5;
     uint8_t LastPayload = ((~VEX_4V) & 0xf) << 3 | VEX_L << 2 | VEX_PP;
     switch (Kind) {
     case None:
       return;
     case REX:
-      emitByte(0x40 | W << 3 | R << 2 | X << 1 | B, OS);
+      emitByte(0x40 | W << 3 | R << 2 | X << 1 | B, CB);
       return;
     case VEX2:
-      emitByte(0xC5, OS);
-      emitByte(((~R) & 1) << 7 | LastPayload, OS);
+      emitByte(0xC5, CB);
+      emitByte(((~R) & 1) << 7 | LastPayload, CB);
       return;
     case VEX3:
     case XOP:
-      emitByte(Kind == VEX3 ? 0xC4 : 0x8F, OS);
-      emitByte(FirstPayload | VEX_5M, OS);
-      emitByte(W << 7 | LastPayload, OS);
+      emitByte(Kind == VEX3 ? 0xC4 : 0x8F, CB);
+      emitByte(FirstPayload | VEX_5M, CB);
+      emitByte(W << 7 | LastPayload, CB);
       return;
     case EVEX:
       assert(VEX_5M && !(VEX_5M & 0x8) && "invalid mmm fields for EVEX!");
-      emitByte(0x62, OS);
-      emitByte(FirstPayload | ((~EVEX_R2) & 0x1) << 4 | VEX_5M, OS);
-      emitByte(W << 7 | ((~VEX_4V) & 0xf) << 3 | 1 << 2 | VEX_PP, OS);
+      emitByte(0x62, CB);
+      emitByte(FirstPayload | ((~EVEX_R2) & 0x1) << 4 | VEX_5M, CB);
+      emitByte(W << 7 | ((~VEX_4V) & 0xf) << 3 | 1 << 2 | VEX_PP, CB);
       emitByte(EVEX_z << 7 | EVEX_L2 << 6 | VEX_L << 5 | EVEX_b << 4 |
                    ((~EVEX_V2) & 0x1) << 3 | EVEX_aaa,
-               OS);
+               CB);
       return;
     }
   }
 };
 
 class X86MCCodeEmitter : public MCCodeEmitter {
   const MCInstrInfo &MCII;
   MCContext &Ctx;
 
 public:
   X86MCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx)
       : MCII(mcii), Ctx(ctx) {}
   X86MCCodeEmitter(const X86MCCodeEmitter &) = delete;
   X86MCCodeEmitter &operator=(const X86MCCodeEmitter &) = delete;
   ~X86MCCodeEmitter() override = default;
 
-  void emitPrefix(const MCInst &MI, raw_ostream &OS,
+  void emitPrefix(const MCInst &MI, SmallVectorImpl<char> &CB,
                   const MCSubtargetInfo &STI) const override;
 
-  void encodeInstruction(const MCInst &MI, raw_ostream &OS,
+  void encodeInstruction(const MCInst &MI, SmallVectorImpl<char> &CB,
                          SmallVectorImpl<MCFixup> &Fixups,
                          const MCSubtargetInfo &STI) const override;
 
 private:
   unsigned getX86RegNum(const MCOperand &MO) const;
 
   unsigned getX86RegEncoding(const MCInst &MI, unsigned OpNum) const;
 
   void emitImmediate(const MCOperand &Disp, SMLoc Loc, unsigned ImmSize,
-                     MCFixupKind FixupKind, uint64_t StartByte, raw_ostream &OS,
+                     MCFixupKind FixupKind, uint64_t StartByte,
+                     SmallVectorImpl<char> &CB,
                      SmallVectorImpl<MCFixup> &Fixups, int ImmOffset = 0) const;
 
   void emitRegModRMByte(const MCOperand &ModRMReg, unsigned RegOpcodeFld,
-                        raw_ostream &OS) const;
+                        SmallVectorImpl<char> &CB) const;
 
   void emitSIBByte(unsigned SS, unsigned Index, unsigned Base,
-                   raw_ostream &OS) const;
+                   SmallVectorImpl<char> &CB) const;
 
   void emitMemModRMByte(const MCInst &MI, unsigned Op, unsigned RegOpcodeField,
                         uint64_t TSFlags, PrefixKind Kind, uint64_t StartByte,
-                        raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups,
+                        SmallVectorImpl<char> &CB,
+                        SmallVectorImpl<MCFixup> &Fixups,
                         const MCSubtargetInfo &STI,
                         bool ForceSIB = false) const;
 
   PrefixKind emitPrefixImpl(unsigned &CurOp, const MCInst &MI,
-                            const MCSubtargetInfo &STI, raw_ostream &OS) const;
+                            const MCSubtargetInfo &STI,
+                            SmallVectorImpl<char> &CB) const;
 
   PrefixKind emitVEXOpcodePrefix(int MemOperand, const MCInst &MI,
-                                 raw_ostream &OS) const;
+                                 SmallVectorImpl<char> &CB) const;
 
   void emitSegmentOverridePrefix(unsigned SegOperand, const MCInst &MI,
-                                 raw_ostream &OS) const;
+                                 SmallVectorImpl<char> &CB) const;
 
   PrefixKind emitOpcodePrefix(int MemOperand, const MCInst &MI,
                               const MCSubtargetInfo &STI,
-                              raw_ostream &OS) const;
+                              SmallVectorImpl<char> &CB) const;
 
   PrefixKind emitREXPrefix(int MemOperand, const MCInst &MI,
-                           const MCSubtargetInfo &STI, raw_ostream &OS) const;
+                           const MCSubtargetInfo &STI,
+                           SmallVectorImpl<char> &CB) const;
 };
 
 } // end anonymous namespace
 
 static uint8_t modRMByte(unsigned Mod, unsigned RegOpcode, unsigned RM) {
   assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
   return RM | (RegOpcode << 3) | (Mod << 6);
 }
 
-static void emitConstant(uint64_t Val, unsigned Size, raw_ostream &OS) {
+static void emitConstant(uint64_t Val, unsigned Size,
+                         SmallVectorImpl<char> &CB) {
   // Output the constant in little endian byte order.
   for (unsigned i = 0; i != Size; ++i) {
-    emitByte(Val & 255, OS);
+    emitByte(Val & 255, CB);
     Val >>= 8;
   }
 }
 
 /// Determine if this immediate can fit in a disp8 or a compressed disp8 for
 /// EVEX instructions. \p will be set to the value to pass to the ImmOffset
 /// parameter of emitImmediate.
 static bool isDispOrCDisp8(uint64_t TSFlags, int Value, int &ImmOffset) {

 
 unsigned X86MCCodeEmitter::getX86RegEncoding(const MCInst &MI,
                                              unsigned OpNum) const {
   return Ctx.getRegisterInfo()->getEncodingValue(MI.getOperand(OpNum).getReg());
 }
 
 void X86MCCodeEmitter::emitImmediate(const MCOperand &DispOp, SMLoc Loc,
                                      unsigned Size, MCFixupKind FixupKind,
-                                     uint64_t StartByte, raw_ostream &OS,
+                                     uint64_t StartByte,
+                                     SmallVectorImpl<char> &CB,
                                      SmallVectorImpl<MCFixup> &Fixups,
                                      int ImmOffset) const {
   const MCExpr *Expr = nullptr;
   if (DispOp.isImm()) {
     // If this is a simple integer displacement that doesn't require a
     // relocation, emit it now.
     if (FixupKind != FK_PCRel_1 && FixupKind != FK_PCRel_2 &&
         FixupKind != FK_PCRel_4) {
-      emitConstant(DispOp.getImm() + ImmOffset, Size, OS);
+      emitConstant(DispOp.getImm() + ImmOffset, Size, CB);
       return;
     }
     Expr = MCConstantExpr::create(DispOp.getImm(), Ctx);
   } else {
     Expr = DispOp.getExpr();
   }
 
   // If we have an immoffset, add it to the expression.
   if ((FixupKind == FK_Data_4 || FixupKind == FK_Data_8 ||
        FixupKind == MCFixupKind(X86::reloc_signed_4byte))) {
     GlobalOffsetTableExprKind Kind = startsWithGlobalOffsetTable(Expr);
     if (Kind != GOT_None) {
       assert(ImmOffset == 0);
 
       if (Size == 8) {
         FixupKind = MCFixupKind(X86::reloc_global_offset_table8);
       } else {
         assert(Size == 4);
         FixupKind = MCFixupKind(X86::reloc_global_offset_table);
       }
 
       if (Kind == GOT_Normal)
-        ImmOffset = static_cast<int>(OS.tell() - StartByte);
+        ImmOffset = static_cast<int>(CB.size() - StartByte);
     } else if (Expr->getKind() == MCExpr::SymbolRef) {
       if (hasSecRelSymbolRef(Expr)) {
         FixupKind = MCFixupKind(FK_SecRel_4);
       }
     } else if (Expr->getKind() == MCExpr::Binary) {
       const MCBinaryExpr *Bin = static_cast<const MCBinaryExpr *>(Expr);
       if (hasSecRelSymbolRef(Bin->getLHS()) ||
           hasSecRelSymbolRef(Bin->getRHS())) {
void X86MCCodeEmitter::emitImmediate(const MCOperand &DispOp, SMLoc Loc,
   if (FixupKind == FK_PCRel_1)
     ImmOffset -= 1;
 
   if (ImmOffset)
     Expr = MCBinaryExpr::createAdd(Expr, MCConstantExpr::create(ImmOffset, Ctx),
                                    Ctx);
 
   // Emit a symbolic constant as a fixup and 4 zeros.
-  Fixups.push_back(MCFixup::create(static_cast<uint32_t>(OS.tell() - StartByte),
+  Fixups.push_back(MCFixup::create(static_cast<uint32_t>(CB.size() - StartByte),
                                    Expr, FixupKind, Loc));
-  emitConstant(0, Size, OS);
+  emitConstant(0, Size, CB);
 }
 
 void X86MCCodeEmitter::emitRegModRMByte(const MCOperand &ModRMReg,
                                         unsigned RegOpcodeFld,
-                                        raw_ostream &OS) const {
-  emitByte(modRMByte(3, RegOpcodeFld, getX86RegNum(ModRMReg)), OS);
+                                        SmallVectorImpl<char> &CB) const {
+  emitByte(modRMByte(3, RegOpcodeFld, getX86RegNum(ModRMReg)), CB);
 }
 
 void X86MCCodeEmitter::emitSIBByte(unsigned SS, unsigned Index, unsigned Base,
-                                   raw_ostream &OS) const {
+                                   SmallVectorImpl<char> &CB) const {
   // SIB byte is in the same format as the modRMByte.
-  emitByte(modRMByte(SS, Index, Base), OS);
+  emitByte(modRMByte(SS, Index, Base), CB);
 }
 
-void X86MCCodeEmitter::emitMemModRMByte(const MCInst &MI, unsigned Op,
-                                        unsigned RegOpcodeField,
-                                        uint64_t TSFlags, PrefixKind Kind,
-                                        uint64_t StartByte, raw_ostream &OS,
-                                        SmallVectorImpl<MCFixup> &Fixups,
-                                        const MCSubtargetInfo &STI,
-                                        bool ForceSIB) const {
+void X86MCCodeEmitter::emitMemModRMByte(
+    const MCInst &MI, unsigned Op, unsigned RegOpcodeField, uint64_t TSFlags,
+    PrefixKind Kind, uint64_t StartByte, SmallVectorImpl<char> &CB,
+    SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI,
   const MCOperand &Disp = MI.getOperand(Op + X86::AddrDisp);
   const MCOperand &Base = MI.getOperand(Op + X86::AddrBaseReg);
   const MCOperand &Scale = MI.getOperand(Op + X86::AddrScaleAmt);
   const MCOperand &IndexReg = MI.getOperand(Op + X86::AddrIndexReg);
   unsigned BaseReg = Base.getReg();
 
   // Handle %rip relative addressing.
   if (BaseReg == X86::RIP ||
       BaseReg == X86::EIP) { // [disp32+rIP] in X86-64 mode
     assert(STI.hasFeature(X86::Is64Bit) &&
            "Rip-relative addressing requires 64-bit mode");
     assert(IndexReg.getReg() == 0 && !ForceSIB &&
            "Invalid rip-relative address");
-    emitByte(modRMByte(0, RegOpcodeField, 5), OS);
+    emitByte(modRMByte(0, RegOpcodeField, 5), CB);
 
     unsigned Opcode = MI.getOpcode();
     unsigned FixupKind = [&]() {
       // Enable relaxed relocation only for a MCSymbolRefExpr.  We cannot use a
       // relaxed relocation if an offset is present (e.g. x@GOTPCREL+4).
       if (!(Disp.isExpr() && isa<MCSymbolRefExpr>(Disp.getExpr())))
         return X86::reloc_riprel_4byte;
 
if (BaseReg == X86::RIP ||
     // the size of the immediate field. If we have this case, add it into the
     // expression to emit.
     // Note: rip-relative addressing using immediate displacement values should
     // not be adjusted, assuming it was the user's intent.
     int ImmSize = !Disp.isImm() && X86II::hasImm(TSFlags)
                       ? X86II::getSizeOfImm(TSFlags)
                       : 0;
 
-    emitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(FixupKind), StartByte, OS,
+    emitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(FixupKind), StartByte, CB,
                   Fixups, -ImmSize);
     return;
   }
 
   unsigned BaseRegNo = BaseReg ? getX86RegNum(Base) : -1U;
 
   // 16-bit addressing forms of the ModR/M byte have a different encoding for
   // the R/M field and are far more limited in which registers can be used.
if (BaseReg) {
           RMfield = (RMfield & 1) | ((7 - IndexReg16) << 1);
         else
           RMfield = (IndexReg16 & 1) | ((7 - RMfield) << 1);
       }
 
       if (Disp.isImm() && isInt<8>(Disp.getImm())) {
         if (Disp.getImm() == 0 && RMfield != 6) {
           // There is no displacement; just the register.
-          emitByte(modRMByte(0, RegOpcodeField, RMfield), OS);
+          emitByte(modRMByte(0, RegOpcodeField, RMfield), CB);
           return;
         }
         // Use the [REG]+disp8 form, including for [BP] which cannot be encoded.
-        emitByte(modRMByte(1, RegOpcodeField, RMfield), OS);
-        emitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, StartByte, OS, Fixups);
+        emitByte(modRMByte(1, RegOpcodeField, RMfield), CB);
+        emitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, StartByte, CB, Fixups);
         return;
       }
       // This is the [REG]+disp16 case.
-      emitByte(modRMByte(2, RegOpcodeField, RMfield), OS);
+      emitByte(modRMByte(2, RegOpcodeField, RMfield), CB);
     } else {
       assert(IndexReg.getReg() == 0 && "Unexpected index register!");
       // There is no BaseReg; this is the plain [disp16] case.
-      emitByte(modRMByte(0, RegOpcodeField, 6), OS);
+      emitByte(modRMByte(0, RegOpcodeField, 6), CB);
     }
 
     // Emit 16-bit displacement for plain disp16 or [REG]+disp16 cases.
-    emitImmediate(Disp, MI.getLoc(), 2, FK_Data_2, StartByte, OS, Fixups);
+    emitImmediate(Disp, MI.getLoc(), 2, FK_Data_2, StartByte, CB, Fixups);
     return;
   }
 
   // Check for presence of {disp8} or {disp32} pseudo prefixes.
   bool UseDisp8 = MI.getFlags() & X86::IP_USE_DISP8;
   bool UseDisp32 = MI.getFlags() & X86::IP_USE_DISP32;
 
   // We only allow no displacement if no pseudo prefix is present.
if (// The SIB byte must be used if there is an index register or the
       // encode to an R/M value of 4, which indicates that a SIB byte is
       // present.
       BaseRegNo != N86::ESP &&
       // If there is no base register and we're in 64-bit mode, we need a SIB
       // byte to emit an addr that is just 'disp32' (the non-RIP relative form).
       (!STI.hasFeature(X86::Is64Bit) || BaseReg != 0)) {
 
     if (BaseReg == 0) { // [disp32]     in X86-32 mode
-      emitByte(modRMByte(0, RegOpcodeField, 5), OS);
-      emitImmediate(Disp, MI.getLoc(), 4, FK_Data_4, StartByte, OS, Fixups);
+      emitByte(modRMByte(0, RegOpcodeField, 5), CB);
+      emitImmediate(Disp, MI.getLoc(), 4, FK_Data_4, StartByte, CB, Fixups);
       return;
     }
 
     // If the base is not EBP/ESP/R12/R13 and there is no displacement, use
     // simple indirect register encoding, this handles addresses like [EAX].
     // The encoding for [EBP] or[R13] with no displacement means [disp32] so we
     // handle it by emitting a displacement of 0 later.
     if (BaseRegNo != N86::EBP) {
       if (Disp.isImm() && Disp.getImm() == 0 && AllowNoDisp) {
-        emitByte(modRMByte(0, RegOpcodeField, BaseRegNo), OS);
+        emitByte(modRMByte(0, RegOpcodeField, BaseRegNo), CB);
         return;
       }
 
       // If the displacement is @tlscall, treat it as a zero.
       if (Disp.isExpr()) {
         auto *Sym = dyn_cast<MCSymbolRefExpr>(Disp.getExpr());
         if (Sym && Sym->getKind() == MCSymbolRefExpr::VK_TLSCALL) {
           // This is exclusively used by call *a@tlscall(base). The relocation
           // (R_386_TLSCALL or R_X86_64_TLSCALL) applies to the beginning.
           Fixups.push_back(MCFixup::create(0, Sym, FK_NONE, MI.getLoc()));
-          emitByte(modRMByte(0, RegOpcodeField, BaseRegNo), OS);
+          emitByte(modRMByte(0, RegOpcodeField, BaseRegNo), CB);
           return;
         }
       }
     }
 
     // Otherwise, if the displacement fits in a byte, encode as [REG+disp8].
     // Including a compressed disp8 for EVEX instructions that support it.
     // This also handles the 0 displacement for [EBP] or [R13]. We can't use
     // disp8 if the {disp32} pseudo prefix is present.
     if (Disp.isImm() && AllowDisp8) {
       int ImmOffset = 0;
       if (isDispOrCDisp8(TSFlags, Disp.getImm(), ImmOffset)) {
-        emitByte(modRMByte(1, RegOpcodeField, BaseRegNo), OS);
-        emitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, StartByte, OS, Fixups,
+        emitByte(modRMByte(1, RegOpcodeField, BaseRegNo), CB);
+        emitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, StartByte, CB, Fixups,
                       ImmOffset);
         return;
       }
     }
 
     // Otherwise, emit the most general non-SIB encoding: [REG+disp32].
     // Displacement may be 0 for [EBP] or [R13] case if {disp32} pseudo prefix
     // prevented using disp8 above.
-    emitByte(modRMByte(2, RegOpcodeField, BaseRegNo), OS);
+    emitByte(modRMByte(2, RegOpcodeField, BaseRegNo), CB);
     unsigned Opcode = MI.getOpcode();
     unsigned FixupKind = Opcode == X86::MOV32rm ? X86::reloc_signed_4byte_relax
                                                 : X86::reloc_signed_4byte;
-    emitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(FixupKind), StartByte, OS,
+    emitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(FixupKind), StartByte, CB,
                   Fixups);
     return;
   }
 
   // We need a SIB byte, so start by outputting the ModR/M byte first
   assert(IndexReg.getReg() != X86::ESP && IndexReg.getReg() != X86::RSP &&
          "Cannot use ESP as index reg!");
 
   bool ForceDisp32 = false;
   bool ForceDisp8 = false;
   int ImmOffset = 0;
   if (BaseReg == 0) {
     // If there is no base register, we emit the special case SIB byte with
     // MOD=0, BASE=5, to JUST get the index, scale, and displacement.
     BaseRegNo = 5;
-    emitByte(modRMByte(0, RegOpcodeField, 4), OS);
+    emitByte(modRMByte(0, RegOpcodeField, 4), CB);
     ForceDisp32 = true;
   } else if (Disp.isImm() && Disp.getImm() == 0 && AllowNoDisp &&
              // Base reg can't be EBP/RBP/R13 as that would end up with '5' as
              // the base field, but that is the magic [*] nomenclature that
              // indicates no base when mod=0. For these cases we'll emit a 0
              // displacement instead.
              BaseRegNo != N86::EBP) {
     // Emit no displacement ModR/M byte
-    emitByte(modRMByte(0, RegOpcodeField, 4), OS);
+    emitByte(modRMByte(0, RegOpcodeField, 4), CB);
   } else if (Disp.isImm() && AllowDisp8 &&
              isDispOrCDisp8(TSFlags, Disp.getImm(), ImmOffset)) {
     // Displacement fits in a byte or matches an EVEX compressed disp8, use
     // disp8 encoding. This also handles EBP/R13 base with 0 displacement unless
     // {disp32} pseudo prefix was used.
-    emitByte(modRMByte(1, RegOpcodeField, 4), OS);
+    emitByte(modRMByte(1, RegOpcodeField, 4), CB);
     ForceDisp8 = true;
   } else {
     // Otherwise, emit the normal disp32 encoding.
-    emitByte(modRMByte(2, RegOpcodeField, 4), OS);
+    emitByte(modRMByte(2, RegOpcodeField, 4), CB);
     ForceDisp32 = true;
   }
 
   // Calculate what the SS field value should be...
   static const unsigned SSTable[] = {~0U, 0, 1, ~0U, 2, ~0U, ~0U, ~0U, 3};
   unsigned SS = SSTable[Scale.getImm()];
 
   unsigned IndexRegNo = IndexReg.getReg() ? getX86RegNum(IndexReg) : 4;
 
-  emitSIBByte(SS, IndexRegNo, BaseRegNo, OS);
+  emitSIBByte(SS, IndexRegNo, BaseRegNo, CB);
 
   // Do we need to output a displacement?
   if (ForceDisp8)
-    emitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, StartByte, OS, Fixups,
+    emitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, StartByte, CB, Fixups,
                   ImmOffset);
   else if (ForceDisp32)
     emitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(X86::reloc_signed_4byte),
-                  StartByte, OS, Fixups);
+                  StartByte, CB, Fixups);
 }
 
 /// Emit all instruction prefixes.
 ///
 /// \returns one of the REX, XOP, VEX2, VEX3, EVEX if any of them is used,
 /// otherwise returns None.
 PrefixKind X86MCCodeEmitter::emitPrefixImpl(unsigned &CurOp, const MCInst &MI,
                                             const MCSubtargetInfo &STI,
-                                            raw_ostream &OS) const {
+                                            SmallVectorImpl<char> &CB) const {
   uint64_t TSFlags = MCII.get(MI.getOpcode()).TSFlags;
   // Determine where the memory operand starts, if present.
   int MemoryOperand = X86II::getMemoryOperandNo(TSFlags);
   // Emit segment override opcode prefix as needed.
   if (MemoryOperand != -1) {
     MemoryOperand += CurOp;
-    emitSegmentOverridePrefix(MemoryOperand + X86::AddrSegmentReg, MI, OS);
+    emitSegmentOverridePrefix(MemoryOperand + X86::AddrSegmentReg, MI, CB);
   }
 
   // Emit the repeat opcode prefix as needed.
   unsigned Flags = MI.getFlags();
   if (TSFlags & X86II::REP || Flags & X86::IP_HAS_REPEAT)
-    emitByte(0xF3, OS);
+    emitByte(0xF3, CB);
   if (Flags & X86::IP_HAS_REPEAT_NE)
-    emitByte(0xF2, OS);
+    emitByte(0xF2, CB);
 
   // Emit the address size opcode prefix as needed.
   if (X86_MC::needsAddressSizeOverride(MI, STI, MemoryOperand, TSFlags) ||
       Flags & X86::IP_HAS_AD_SIZE)
-    emitByte(0x67, OS);
+    emitByte(0x67, CB);
 
   uint64_t Form = TSFlags & X86II::FormMask;
   switch (Form) {
   default:
     break;
   case X86II::RawFrmDstSrc: {
     // Emit segment override opcode prefix as needed (not for %ds).
     if (MI.getOperand(2).getReg() != X86::DS)
-      emitSegmentOverridePrefix(2, MI, OS);
+      emitSegmentOverridePrefix(2, MI, CB);
     CurOp += 3; // Consume operands.
     break;
   }
   case X86II::RawFrmSrc: {
     // Emit segment override opcode prefix as needed (not for %ds).
     if (MI.getOperand(1).getReg() != X86::DS)
-      emitSegmentOverridePrefix(1, MI, OS);
+      emitSegmentOverridePrefix(1, MI, CB);
     CurOp += 2; // Consume operands.
     break;
   }
   case X86II::RawFrmDst: {
     ++CurOp; // Consume operand.
     break;
   }
   case X86II::RawFrmMemOffs: {
     // Emit segment override opcode prefix as needed.
-    emitSegmentOverridePrefix(1, MI, OS);
+    emitSegmentOverridePrefix(1, MI, CB);
     break;
   }
   }
 
   // REX prefix is optional, but if used must be immediately before the opcode
   // Encoding type for this instruction.
   return (TSFlags & X86II::EncodingMask)
-             ? emitVEXOpcodePrefix(MemoryOperand, MI, OS)
-             : emitOpcodePrefix(MemoryOperand, MI, STI, OS);
+             ? emitVEXOpcodePrefix(MemoryOperand, MI, CB)
+             : emitOpcodePrefix(MemoryOperand, MI, STI, CB);
 }
 
 // AVX instructions are encoded using an encoding scheme that combines
 // prefix bytes, opcode extension field, operand encoding fields, and vector
 // length encoding capability into a new prefix, referred to as VEX.
 
 // The majority of the AVX-512 family of instructions (operating on
 // 512/256/128-bit vector register operands) are encoded using a new prefix
 // (called EVEX).
 
 // XOP is a revised subset of what was originally intended as SSE5. It was
 // changed to be similar but not overlapping with AVX.
 
 /// Emit XOP, VEX2, VEX3 or EVEX prefix.
 /// \returns the used prefix.
-PrefixKind X86MCCodeEmitter::emitVEXOpcodePrefix(int MemOperand,
-                                                 const MCInst &MI,
-                                                 raw_ostream &OS) const {
+PrefixKind
+X86MCCodeEmitter::emitVEXOpcodePrefix(int MemOperand, const MCInst &MI,
+                                      SmallVectorImpl<char> &CB) const {
   const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
   uint64_t TSFlags = Desc.TSFlags;
 
   assert(!(TSFlags & X86II::LOCK) && "Can't have LOCK VEX.");
 
   X86OpcodePrefixHelper Prefix(*Ctx.getRegisterInfo());
   switch (TSFlags & X86II::EncodingMask) {
   default:
case X86II::MRM7r: {
     break;
   }
   }
   if (EncodeRC) {
     Prefix.setL(EVEX_rc & 0x1);
     Prefix.setL2(EVEX_rc & 0x2);
   }
   PrefixKind Kind = Prefix.determineOptimalKind();
-  Prefix.emit(OS);
+  Prefix.emit(CB);
   return Kind;
 }
 
 /// Emit REX prefix which specifies
 ///   1) 64-bit instructions,
 ///   2) non-default operand size, and
 ///   3) use of X86-64 extended registers.
 ///
 /// \returns the used prefix (REX or None).
 PrefixKind X86MCCodeEmitter::emitREXPrefix(int MemOperand, const MCInst &MI,
                                            const MCSubtargetInfo &STI,
-                                           raw_ostream &OS) const {
+                                           SmallVectorImpl<char> &CB) const {
   if (!STI.hasFeature(X86::Is64Bit))
     return None;
   X86OpcodePrefixHelper Prefix(*Ctx.getRegisterInfo());
   const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
   uint64_t TSFlags = Desc.TSFlags;
   Prefix.setW(TSFlags & X86II::REX_W);
   unsigned NumOps = MI.getNumOperands();
   bool UsesHighByteReg = false;
#endif
   case X86II::MRM7r:
     Prefix.setB(MI, CurOp++);
     break;
   }
   PrefixKind Kind = Prefix.determineOptimalKind();
   if (Kind && UsesHighByteReg)
     report_fatal_error(
         "Cannot encode high byte register in REX-prefixed instruction");
-  Prefix.emit(OS);
+  Prefix.emit(CB);
   return Kind;
 }
 
 /// Emit segment override opcode prefix as needed.
-void X86MCCodeEmitter::emitSegmentOverridePrefix(unsigned SegOperand,
-                                                 const MCInst &MI,
-                                                 raw_ostream &OS) const {
+void X86MCCodeEmitter::emitSegmentOverridePrefix(
+    unsigned SegOperand, const MCInst &MI, SmallVectorImpl<char> &CB) const {
   // Check for explicit segment override on memory operand.
   if (unsigned Reg = MI.getOperand(SegOperand).getReg())
-    emitByte(X86::getSegmentOverridePrefixForReg(Reg), OS);
+    emitByte(X86::getSegmentOverridePrefixForReg(Reg), CB);
 }
 
 /// Emit all instruction prefixes prior to the opcode.
 ///
 /// \param MemOperand the operand # of the start of a memory operand if present.
 /// If not present, it is -1.
 ///
 /// \returns the used prefix (REX or None).
 PrefixKind X86MCCodeEmitter::emitOpcodePrefix(int MemOperand, const MCInst &MI,
                                               const MCSubtargetInfo &STI,
-                                        raw_ostream &OS) const {
+                                              SmallVectorImpl<char> &CB) const {
   const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
   uint64_t TSFlags = Desc.TSFlags;
 
   // Emit the operand size opcode prefix as needed.
   if ((TSFlags & X86II::OpSizeMask) ==
       (STI.hasFeature(X86::Is16Bit) ? X86II::OpSize32 : X86II::OpSize16))
-    emitByte(0x66, OS);
+    emitByte(0x66, CB);
 
   // Emit the LOCK opcode prefix.
   if (TSFlags & X86II::LOCK || MI.getFlags() & X86::IP_HAS_LOCK)
-    emitByte(0xF0, OS);
+    emitByte(0xF0, CB);
 
   // Emit the NOTRACK opcode prefix.
   if (TSFlags & X86II::NOTRACK || MI.getFlags() & X86::IP_HAS_NOTRACK)
-    emitByte(0x3E, OS);
+    emitByte(0x3E, CB);
 
   switch (TSFlags & X86II::OpPrefixMask) {
   case X86II::PD: // 66
-    emitByte(0x66, OS);
+    emitByte(0x66, CB);
     break;
   case X86II::XS: // F3
-    emitByte(0xF3, OS);
+    emitByte(0xF3, CB);
     break;
   case X86II::XD: // F2
-    emitByte(0xF2, OS);
+    emitByte(0xF2, CB);
     break;
   }
 
   // Handle REX prefix.
   assert((STI.hasFeature(X86::Is64Bit) || !(TSFlags & X86II::REX_W)) &&
          "REX.W requires 64bit mode.");
-  PrefixKind Kind = emitREXPrefix(MemOperand, MI, STI, OS);
+  PrefixKind Kind = emitREXPrefix(MemOperand, MI, STI, CB);
 
   // 0x0F escape code must be emitted just before the opcode.
   switch (TSFlags & X86II::OpMapMask) {
   case X86II::TB:        // Two-byte opcode map
   case X86II::T8:        // 0F 38
   case X86II::TA:        // 0F 3A
   case X86II::ThreeDNow: // 0F 0F, second 0F emitted by caller.
-    emitByte(0x0F, OS);
+    emitByte(0x0F, CB);
     break;
   }
 
   switch (TSFlags & X86II::OpMapMask) {
   case X86II::T8: // 0F 38
-    emitByte(0x38, OS);
+    emitByte(0x38, CB);
     break;
   case X86II::TA: // 0F 3A
-    emitByte(0x3A, OS);
+    emitByte(0x3A, CB);
     break;
   }
 
   return Kind;
 }
 
-void X86MCCodeEmitter::emitPrefix(const MCInst &MI, raw_ostream &OS,
+void X86MCCodeEmitter::emitPrefix(const MCInst &MI, SmallVectorImpl<char> &CB,
                                   const MCSubtargetInfo &STI) const {
   unsigned Opcode = MI.getOpcode();
   const MCInstrDesc &Desc = MCII.get(Opcode);
   uint64_t TSFlags = Desc.TSFlags;
 
   // Pseudo instructions don't get encoded.
   if (X86II::isPseudo(TSFlags))
     return;
 
   unsigned CurOp = X86II::getOperandBias(Desc);
 
-  emitPrefixImpl(CurOp, MI, STI, OS);
+  emitPrefixImpl(CurOp, MI, STI, CB);
 }
 
-void X86MCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
+void X86MCCodeEmitter::encodeInstruction(const MCInst &MI,
+                                         SmallVectorImpl<char> &CB,
                                          SmallVectorImpl<MCFixup> &Fixups,
                                          const MCSubtargetInfo &STI) const {
   unsigned Opcode = MI.getOpcode();
   const MCInstrDesc &Desc = MCII.get(Opcode);
   uint64_t TSFlags = Desc.TSFlags;
 
   // Pseudo instructions don't get encoded.
   if (X86II::isPseudo(TSFlags))
     return;
 
   unsigned NumOps = Desc.getNumOperands();
   unsigned CurOp = X86II::getOperandBias(Desc);
 
-  uint64_t StartByte = OS.tell();
+  uint64_t StartByte = CB.size();
 
-  PrefixKind Kind = emitPrefixImpl(CurOp, MI, STI, OS);
+  PrefixKind Kind = emitPrefixImpl(CurOp, MI, STI, CB);
 
   // It uses the VEX.VVVV field?
   bool HasVEX_4V = TSFlags & X86II::VEX_4V;
   bool HasVEX_I8Reg = (TSFlags & X86II::ImmMask) == X86II::Imm8Reg;
 
   // It uses the EVEX.aaa field?
   bool HasEVEX_K = TSFlags & X86II::EVEX_K;
   bool HasEVEX_RC = TSFlags & X86II::EVEX_RC;
default:
     errs() << "FORM: " << Form << "\n";
     llvm_unreachable("Unknown FormMask value in X86MCCodeEmitter!");
   case X86II::Pseudo:
     llvm_unreachable("Pseudo instruction shouldn't be emitted");
   case X86II::RawFrmDstSrc:
   case X86II::RawFrmSrc:
   case X86II::RawFrmDst:
   case X86II::PrefixByte:
-    emitByte(BaseOpcode, OS);
+    emitByte(BaseOpcode, CB);
     break;
   case X86II::AddCCFrm: {
     // This will be added to the opcode in the fallthrough.
     OpcodeOffset = MI.getOperand(NumOps - 1).getImm();
     assert(OpcodeOffset < 16 && "Unexpected opcode offset!");
     --NumOps; // Drop the operand from the end.
     [[fallthrough]];
   case X86II::RawFrm:
-    emitByte(BaseOpcode + OpcodeOffset, OS);
+    emitByte(BaseOpcode + OpcodeOffset, CB);
 
     if (!STI.hasFeature(X86::Is64Bit) || !isPCRel32Branch(MI, MCII))
       break;
 
     const MCOperand &Op = MI.getOperand(CurOp++);
     emitImmediate(Op, MI.getLoc(), X86II::getSizeOfImm(TSFlags),
-                  MCFixupKind(X86::reloc_branch_4byte_pcrel), StartByte, OS,
+                  MCFixupKind(X86::reloc_branch_4byte_pcrel), StartByte, CB,
                   Fixups);
     break;
   }
   case X86II::RawFrmMemOffs:
-    emitByte(BaseOpcode, OS);
+    emitByte(BaseOpcode, CB);
     emitImmediate(MI.getOperand(CurOp++), MI.getLoc(),
                   X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
-                  StartByte, OS, Fixups);
+                  StartByte, CB, Fixups);
     ++CurOp; // skip segment operand
     break;
   case X86II::RawFrmImm8:
-    emitByte(BaseOpcode, OS);
+    emitByte(BaseOpcode, CB);
     emitImmediate(MI.getOperand(CurOp++), MI.getLoc(),
                   X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
-                  StartByte, OS, Fixups);
+                  StartByte, CB, Fixups);
     emitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 1, FK_Data_1, StartByte,
-                  OS, Fixups);
+                  CB, Fixups);
     break;
   case X86II::RawFrmImm16:
-    emitByte(BaseOpcode, OS);
+    emitByte(BaseOpcode, CB);
     emitImmediate(MI.getOperand(CurOp++), MI.getLoc(),
                   X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
-                  StartByte, OS, Fixups);
+                  StartByte, CB, Fixups);
     emitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 2, FK_Data_2, StartByte,
-                  OS, Fixups);
+                  CB, Fixups);
     break;
 
   case X86II::AddRegFrm:
-    emitByte(BaseOpcode + getX86RegNum(MI.getOperand(CurOp++)), OS);
+    emitByte(BaseOpcode + getX86RegNum(MI.getOperand(CurOp++)), CB);
     break;
 
   case X86II::MRMDestReg: {
-    emitByte(BaseOpcode, OS);
+    emitByte(BaseOpcode, CB);
     unsigned SrcRegNum = CurOp + 1;
 
     if (HasEVEX_K) // Skip writemask
       ++SrcRegNum;
 
     if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
       ++SrcRegNum;
 
     emitRegModRMByte(MI.getOperand(CurOp),
-                     getX86RegNum(MI.getOperand(SrcRegNum)), OS);
+                     getX86RegNum(MI.getOperand(SrcRegNum)), CB);
     CurOp = SrcRegNum + 1;
     break;
   }
   case X86II::MRMDestMem4VOp3CC: {
     unsigned CC = MI.getOperand(8).getImm();
-    emitByte(BaseOpcode + CC, OS);
+    emitByte(BaseOpcode + CC, CB);
     unsigned SrcRegNum = CurOp + X86::AddrNumOperands;
     emitMemModRMByte(MI, CurOp + 1, getX86RegNum(MI.getOperand(0)), TSFlags,
-                     Kind, StartByte, OS, Fixups, STI, false);
+                     Kind, StartByte, CB, Fixups, STI, false);
     CurOp = SrcRegNum + 3; // skip reg, VEX_V4 and CC
     break;
   }
   case X86II::MRMDestMemFSIB:
   case X86II::MRMDestMem: {
-    emitByte(BaseOpcode, OS);
+    emitByte(BaseOpcode, CB);
     unsigned SrcRegNum = CurOp + X86::AddrNumOperands;
 
     if (HasEVEX_K) // Skip writemask
       ++SrcRegNum;
 
     if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
       ++SrcRegNum;
 
     bool ForceSIB = (Form == X86II::MRMDestMemFSIB);
     emitMemModRMByte(MI, CurOp, getX86RegNum(MI.getOperand(SrcRegNum)), TSFlags,
-                     Kind, StartByte, OS, Fixups, STI, ForceSIB);
+                     Kind, StartByte, CB, Fixups, STI, ForceSIB);
     CurOp = SrcRegNum + 1;
     break;
   }
   case X86II::MRMSrcReg: {
-    emitByte(BaseOpcode, OS);
+    emitByte(BaseOpcode, CB);
     unsigned SrcRegNum = CurOp + 1;
 
     if (HasEVEX_K) // Skip writemask
       ++SrcRegNum;
 
     if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
       ++SrcRegNum;
 
     emitRegModRMByte(MI.getOperand(SrcRegNum),
-                     getX86RegNum(MI.getOperand(CurOp)), OS);
+                     getX86RegNum(MI.getOperand(CurOp)), CB);
     CurOp = SrcRegNum + 1;
     if (HasVEX_I8Reg)
       I8RegNum = getX86RegEncoding(MI, CurOp++);
     // do not count the rounding control operand
     if (HasEVEX_RC)
       --NumOps;
     break;
   }
   case X86II::MRMSrcReg4VOp3: {
-    emitByte(BaseOpcode, OS);
+    emitByte(BaseOpcode, CB);
     unsigned SrcRegNum = CurOp + 1;
 
     emitRegModRMByte(MI.getOperand(SrcRegNum),
-                     getX86RegNum(MI.getOperand(CurOp)), OS);
+                     getX86RegNum(MI.getOperand(CurOp)), CB);
     CurOp = SrcRegNum + 1;
     ++CurOp; // Encoded in VEX.VVVV
     break;
   }
   case X86II::MRMSrcRegOp4: {
-    emitByte(BaseOpcode, OS);
+    emitByte(BaseOpcode, CB);
     unsigned SrcRegNum = CurOp + 1;
 
     // Skip 1st src (which is encoded in VEX_VVVV)
     ++SrcRegNum;
 
     // Capture 2nd src (which is encoded in Imm[7:4])
     assert(HasVEX_I8Reg && "MRMSrcRegOp4 should imply VEX_I8Reg");
     I8RegNum = getX86RegEncoding(MI, SrcRegNum++);
 
     emitRegModRMByte(MI.getOperand(SrcRegNum),
-                     getX86RegNum(MI.getOperand(CurOp)), OS);
+                     getX86RegNum(MI.getOperand(CurOp)), CB);
     CurOp = SrcRegNum + 1;
     break;
   }
   case X86II::MRMSrcRegCC: {
     unsigned FirstOp = CurOp++;
     unsigned SecondOp = CurOp++;
 
     unsigned CC = MI.getOperand(CurOp++).getImm();
-    emitByte(BaseOpcode + CC, OS);
+    emitByte(BaseOpcode + CC, CB);
 
     emitRegModRMByte(MI.getOperand(SecondOp),
-                     getX86RegNum(MI.getOperand(FirstOp)), OS);
+                     getX86RegNum(MI.getOperand(FirstOp)), CB);
     break;
   }
   case X86II::MRMSrcMemFSIB:
   case X86II::MRMSrcMem: {
     unsigned FirstMemOp = CurOp + 1;
 
     if (HasEVEX_K) // Skip writemask
       ++FirstMemOp;
 
     if (HasVEX_4V)
       ++FirstMemOp; // Skip the register source (which is encoded in VEX_VVVV).
 
-    emitByte(BaseOpcode, OS);
+    emitByte(BaseOpcode, CB);
 
     bool ForceSIB = (Form == X86II::MRMSrcMemFSIB);
     emitMemModRMByte(MI, FirstMemOp, getX86RegNum(MI.getOperand(CurOp)),
-                     TSFlags, Kind, StartByte, OS, Fixups, STI, ForceSIB);
+                     TSFlags, Kind, StartByte, CB, Fixups, STI, ForceSIB);
     CurOp = FirstMemOp + X86::AddrNumOperands;
     if (HasVEX_I8Reg)
       I8RegNum = getX86RegEncoding(MI, CurOp++);
     break;
   }
   case X86II::MRMSrcMem4VOp3: {
     unsigned FirstMemOp = CurOp + 1;
 
-    emitByte(BaseOpcode, OS);
+    emitByte(BaseOpcode, CB);
 
     emitMemModRMByte(MI, FirstMemOp, getX86RegNum(MI.getOperand(CurOp)),
-                     TSFlags, Kind, StartByte, OS, Fixups, STI);
+                     TSFlags, Kind, StartByte, CB, Fixups, STI);
     CurOp = FirstMemOp + X86::AddrNumOperands;
     ++CurOp; // Encoded in VEX.VVVV.
     break;
   }
   case X86II::MRMSrcMemOp4: {
     unsigned FirstMemOp = CurOp + 1;
 
     ++FirstMemOp; // Skip the register source (which is encoded in VEX_VVVV).
 
     // Capture second register source (encoded in Imm[7:4])
     assert(HasVEX_I8Reg && "MRMSrcRegOp4 should imply VEX_I8Reg");
     I8RegNum = getX86RegEncoding(MI, FirstMemOp++);
 
-    emitByte(BaseOpcode, OS);
+    emitByte(BaseOpcode, CB);
 
     emitMemModRMByte(MI, FirstMemOp, getX86RegNum(MI.getOperand(CurOp)),
-                     TSFlags, Kind, StartByte, OS, Fixups, STI);
+                     TSFlags, Kind, StartByte, CB, Fixups, STI);
     CurOp = FirstMemOp + X86::AddrNumOperands;
     break;
   }
   case X86II::MRMSrcMemCC: {
     unsigned RegOp = CurOp++;
     unsigned FirstMemOp = CurOp;
     CurOp = FirstMemOp + X86::AddrNumOperands;
 
     unsigned CC = MI.getOperand(CurOp++).getImm();
-    emitByte(BaseOpcode + CC, OS);
+    emitByte(BaseOpcode + CC, CB);
 
     emitMemModRMByte(MI, FirstMemOp, getX86RegNum(MI.getOperand(RegOp)),
-                     TSFlags, Kind, StartByte, OS, Fixups, STI);
+                     TSFlags, Kind, StartByte, CB, Fixups, STI);
     break;
   }
 
   case X86II::MRMXrCC: {
     unsigned RegOp = CurOp++;
 
     unsigned CC = MI.getOperand(CurOp++).getImm();
-    emitByte(BaseOpcode + CC, OS);
-    emitRegModRMByte(MI.getOperand(RegOp), 0, OS);
+    emitByte(BaseOpcode + CC, CB);
+    emitRegModRMByte(MI.getOperand(RegOp), 0, CB);
     break;
   }
 
   case X86II::MRMXr:
   case X86II::MRM0r:
   case X86II::MRM1r:
   case X86II::MRM2r:
   case X86II::MRM3r:
   case X86II::MRM4r:
   case X86II::MRM5r:
   case X86II::MRM6r:
   case X86II::MRM7r:
     if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV).
       ++CurOp;
     if (HasEVEX_K) // Skip writemask
       ++CurOp;
-    emitByte(BaseOpcode, OS);
+    emitByte(BaseOpcode, CB);
     emitRegModRMByte(MI.getOperand(CurOp++),
-                     (Form == X86II::MRMXr) ? 0 : Form - X86II::MRM0r, OS);
+                     (Form == X86II::MRMXr) ? 0 : Form - X86II::MRM0r, CB);
     break;
   case X86II::MRMr0:
-    emitByte(BaseOpcode, OS);
-    emitByte(modRMByte(3, getX86RegNum(MI.getOperand(CurOp++)),0), OS);
+    emitByte(BaseOpcode, CB);
+    emitByte(modRMByte(3, getX86RegNum(MI.getOperand(CurOp++)), 0), CB);
     break;
 
   case X86II::MRMXmCC: {
     unsigned FirstMemOp = CurOp;
     CurOp = FirstMemOp + X86::AddrNumOperands;
 
     unsigned CC = MI.getOperand(CurOp++).getImm();
-    emitByte(BaseOpcode + CC, OS);
+    emitByte(BaseOpcode + CC, CB);
 
-    emitMemModRMByte(MI, FirstMemOp, 0, TSFlags, Kind, StartByte, OS, Fixups,
+    emitMemModRMByte(MI, FirstMemOp, 0, TSFlags, Kind, StartByte, CB, Fixups,
                      STI);
     break;
   }
 
   case X86II::MRMXm:
   case X86II::MRM0m:
   case X86II::MRM1m:
   case X86II::MRM2m:
   case X86II::MRM3m:
   case X86II::MRM4m:
   case X86II::MRM5m:
   case X86II::MRM6m:
   case X86II::MRM7m:
     if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV).
       ++CurOp;
     if (HasEVEX_K) // Skip writemask
       ++CurOp;
-    emitByte(BaseOpcode, OS);
+    emitByte(BaseOpcode, CB);
     emitMemModRMByte(MI, CurOp,
                      (Form == X86II::MRMXm) ? 0 : Form - X86II::MRM0m, TSFlags,
-                     Kind, StartByte, OS, Fixups, STI);
+                     Kind, StartByte, CB, Fixups, STI);
     CurOp += X86::AddrNumOperands;
     break;
 
   case X86II::MRM0X:
   case X86II::MRM1X:
   case X86II::MRM2X:
   case X86II::MRM3X:
   case X86II::MRM4X:
   case X86II::MRM5X:
   case X86II::MRM6X:
   case X86II::MRM7X:
-    emitByte(BaseOpcode, OS);
-    emitByte(0xC0 + ((Form - X86II::MRM0X) << 3), OS);
+    emitByte(BaseOpcode, CB);
+    emitByte(0xC0 + ((Form - X86II::MRM0X) << 3), CB);
     break;
 
   case X86II::MRM_C0:
   case X86II::MRM_C1:
   case X86II::MRM_C2:
   case X86II::MRM_C3:
   case X86II::MRM_C4:
   case X86II::MRM_C5:
void X86MCCodeEmitter::encodeInstruction(const MCInst &MI,
   case X86II::MRM_F8:
   case X86II::MRM_F9:
   case X86II::MRM_FA:
   case X86II::MRM_FB:
   case X86II::MRM_FC:
   case X86II::MRM_FD:
   case X86II::MRM_FE:
   case X86II::MRM_FF:
-    emitByte(BaseOpcode, OS);
-    emitByte(0xC0 + Form - X86II::MRM_C0, OS);
+    emitByte(BaseOpcode, CB);
+    emitByte(0xC0 + Form - X86II::MRM_C0, CB);
     break;
   }
 
   if (HasVEX_I8Reg) {
     // The last source register of a 4 operand instruction in AVX is encoded
     // in bits[7:4] of a immediate byte.
     assert(I8RegNum < 16 && "Register encoding out of range");
     I8RegNum <<= 4;
     if (CurOp != NumOps) {
       unsigned Val = MI.getOperand(CurOp++).getImm();
       assert(Val < 16 && "Immediate operand value out of range");
       I8RegNum |= Val;
     }
     emitImmediate(MCOperand::createImm(I8RegNum), MI.getLoc(), 1, FK_Data_1,
-                  StartByte, OS, Fixups);
+                  StartByte, CB, Fixups);
   } else {
     // If there is a remaining operand, it must be a trailing immediate. Emit it
     // according to the right size for the instruction. Some instructions
     // (SSE4a extrq and insertq) have two trailing immediates.
     while (CurOp != NumOps && NumOps - CurOp <= 2) {
       emitImmediate(MI.getOperand(CurOp++), MI.getLoc(),
                     X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
-                    StartByte, OS, Fixups);
+                    StartByte, CB, Fixups);
     }
   }
 
   if ((TSFlags & X86II::OpMapMask) == X86II::ThreeDNow)
-    emitByte(X86II::getBaseOpcodeFor(TSFlags), OS);
+    emitByte(X86II::getBaseOpcodeFor(TSFlags), CB);
 
-  assert(OS.tell() - StartByte <= 15 &&
+  assert(CB.size() - StartByte <= 15 &&
          "The size of instruction must be no longer than 15.");
 #ifndef NDEBUG
   // FIXME: Verify.
   if (/*!Desc.isVariadic() &&*/ CurOp != NumOps) {
     errs() << "Cannot encode all operands of: ";
     MI.dump();
     errs() << '\n';
     abort();
   }
 #endif
 }
 
 MCCodeEmitter *llvm::createX86MCCodeEmitter(const MCInstrInfo &MCII,
                                             MCContext &Ctx) {
   return new X86MCCodeEmitter(MCII, Ctx);
 }