[RISCV][NFC] Break ReadVRGatherVV into ReadVRGatherVV_data and ReadVRGatherVV_index to separate the reads for VRGatherVV

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfoV.td

947–948

These instructions are so different that we should fully split the Reads between the 3 instructions.

We need ReadVRGatherVX_data_UpperBound and ReadVRGatherVI_data_UpperBound.

And ReadVRGatherVX_UpperBound needs to renamed to ReadVRGatherVX_index_UpperBound.

[craig.topper]

Reverse ping

[nitinjohnraj]

ReadVRGatherVX -> ReadVRGather_(data|index), ReadVRGatherVI -> ReadVRGatherVI_data

[craig.topper]

LGTM

llvm/lib/Target/RISCV/RISCVInstrInfoV.td

 multiclass VSLD1_FV_F<string opcodestr, bits<6> funct6, string vw = "v"> {
   def F : VALUVF<funct6, OPFVF, opcodestr # "." # vw # "f">,
           Sched<[WriteVFSlide1F_UpperBound, ReadVFSlideV_UpperBound,
                  ReadVFSlideF_UpperBound, ReadVMask]>;
 }
 
 multiclass VGTR_IV_V_X_I<string opcodestr, bits<6> funct6, Operand optype = simm5, string vw = "v"> {
   def V  : VALUVV<funct6, OPIVV, opcodestr # "." # vw # "v">,
-           Sched<[WriteVRGatherVV_UpperBound, ReadVRGatherVV_UpperBound,
-                  ReadVRGatherVV_UpperBound, ReadVMask]>;
+           Sched<[WriteVRGatherVV_UpperBound, ReadVRGatherVV_data_UpperBound,
+                  ReadVRGatherVV_index_UpperBound, ReadVMask]>;
   def X  : VALUVX<funct6, OPIVX, opcodestr # "." # vw # "x">,
-           Sched<[WriteVRGatherVX_UpperBound, ReadVRGatherVV_UpperBound,
-                  ReadVRGatherVX_UpperBound, ReadVMask]>;
+           Sched<[WriteVRGatherVX_UpperBound, ReadVRGatherVX_data_UpperBound,
+                  ReadVRGatherVX_index_UpperBound, ReadVMask]>;
   def I  : VALUVI<funct6, opcodestr # "." # vw # "i", optype>,
-           Sched<[WriteVRGatherVI_UpperBound, ReadVRGatherVV_UpperBound,
+           Sched<[WriteVRGatherVI_UpperBound, ReadVRGatherVI_data_UpperBound,
                   ReadVMask]>;
 }
 
 multiclass VCPR_MV_Mask<string opcodestr, bits<6> funct6, string vm = "v"> {
   def M  : VALUVVNoVm<funct6, OPMVV, opcodestr # "." # vm # "m">,
            Sched<[WriteVCompressV_UpperBound, ReadVCompressV_UpperBound,
                   ReadVCompressV_UpperBound]>;
 }

 defm VFSLIDE1DOWN_V : VSLD1_FV_F<"vfslide1down", 0b001111>;
 } // Predicates = [HasVInstructionsAnyF]
 
 let Predicates = [HasVInstructions] in {
 // Vector Register Gather Instruction
 let Constraints = "@earlyclobber $vd", RVVConstraint = Vrgather in {
 defm VRGATHER_V : VGTR_IV_V_X_I<"vrgather", 0b001100, uimm5>;
 def VRGATHEREI16_VV : VALUVV<0b001110, OPIVV, "vrgatherei16.vv">,
-                      Sched<[WriteVRGatherVV_UpperBound, ReadVRGatherVV_UpperBound,
-                             ReadVRGatherVV_UpperBound]>;
+                      Sched<[WriteVRGatherVV_UpperBound, ReadVRGatherVV_data_UpperBound,
+                             ReadVRGatherVV_index_UpperBound]>;
 } // Constraints = "@earlyclobber $vd", RVVConstraint = Vrgather
 
 // Vector Compress Instruction
 let Constraints = "@earlyclobber $vd", RVVConstraint = Vcompress in {
 defm VCOMPRESS_V : VCPR_MV_Mask<"vcompress", 0b010111>;
 } // Constraints = "@earlyclobber $vd", RVVConstraint = Vcompress
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0,

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

 multiclass VPseudoBinaryFV_VV<LMULInfo m, string Constraint = ""> {
   defm _VV : VPseudoBinary<m.vrclass, m.vrclass, m.vrclass, m, Constraint>;
 }
 
 multiclass VPseudoVGTR_VV_EEW<int eew, string Constraint = ""> {
   foreach m = MxList in {
     defvar mx = m.MX;
     defvar WriteVRGatherVV_MX = !cast<SchedWrite>("WriteVRGatherVV_" # mx);
-    defvar ReadVRGatherVV_MX = !cast<SchedRead>("ReadVRGatherVV_" # mx);
+    defvar ReadVRGatherVV_data_MX = !cast<SchedRead>("ReadVRGatherVV_data_" # mx);
+    defvar ReadVRGatherVV_index_MX = !cast<SchedRead>("ReadVRGatherVV_index_" # mx);
 
     foreach sew = EEWList in {
       defvar octuple_lmul = m.octuple;
       // emul = lmul * eew / sew
       defvar octuple_emul = !srl(!mul(octuple_lmul, eew), log2<sew>.val);
       if !and(!ge(octuple_emul, 1), !le(octuple_emul, 64)) then {
         defvar emulMX = octuple_to_str<octuple_emul>.ret;
         defvar emul = !cast<LMULInfo>("V_" # emulMX);
         defm _VV : VPseudoBinaryEmul<m.vrclass, m.vrclass, emul.vrclass, m, emul, Constraint>,
-                   Sched<[WriteVRGatherVV_MX, ReadVRGatherVV_MX,
-                          ReadVRGatherVV_MX]>;
+                   Sched<[WriteVRGatherVV_MX, ReadVRGatherVV_data_MX,
+                          ReadVRGatherVV_index_MX]>;
       }
     }
   }
 }
 
 multiclass VPseudoBinaryV_VX<LMULInfo m, string Constraint = ""> {
   defm "_VX" : VPseudoBinary<m.vrclass, m.vrclass, GPR, m, Constraint>;
 }

 }
 
 multiclass VPseudoVGTR_VV_VX_VI<Operand ImmType = simm5, string Constraint = ""> {
   foreach m = MxList in {
     defvar mx = m.MX;
     defvar WriteVRGatherVV_MX = !cast<SchedWrite>("WriteVRGatherVV_" # mx);
     defvar WriteVRGatherVX_MX = !cast<SchedWrite>("WriteVRGatherVX_" # mx);
     defvar WriteVRGatherVI_MX = !cast<SchedWrite>("WriteVRGatherVI_" # mx);
-    defvar ReadVRGatherVV_MX = !cast<SchedRead>("ReadVRGatherVV_" # mx);
-    defvar ReadVRGatherVX_MX = !cast<SchedRead>("ReadVRGatherVX_" # mx);
+    defvar ReadVRGatherVV_data_MX = !cast<SchedRead>("ReadVRGatherVV_data_" # mx);
+    defvar ReadVRGatherVV_index_MX = !cast<SchedRead>("ReadVRGatherVV_index_" # mx);
+    defvar ReadVRGatherVX_data_MX = !cast<SchedRead>("ReadVRGatherVX_data_" # mx);
+    defvar ReadVRGatherVX_index_MX = !cast<SchedRead>("ReadVRGatherVX_index_" # mx);
+    defvar ReadVRGatherVI_data_MX = !cast<SchedRead>("ReadVRGatherVI_data_" # mx);
 
     defm "" : VPseudoBinaryV_VV<m, Constraint>,
-              Sched<[WriteVRGatherVV_MX, ReadVRGatherVV_MX,
-                     ReadVRGatherVV_MX, ReadVMask]>;
+              Sched<[WriteVRGatherVV_MX, ReadVRGatherVV_data_MX,
+                     ReadVRGatherVV_index_MX, ReadVMask]>;
     defm "" : VPseudoBinaryV_VX<m, Constraint>,
-              Sched<[WriteVRGatherVX_MX, ReadVRGatherVV_MX,
-                     ReadVRGatherVX_MX, ReadVMask]>;
+              Sched<[WriteVRGatherVX_MX, ReadVRGatherVX_data_MX,
+                     ReadVRGatherVX_index_MX, ReadVMask]>;
     defm "" : VPseudoBinaryV_VI<ImmType, m, Constraint>,
-              Sched<[WriteVRGatherVI_MX, ReadVRGatherVV_MX, ReadVMask]>;
+              Sched<[WriteVRGatherVI_MX, ReadVRGatherVI_data_MX, ReadVMask]>;
   }
 }
 
 multiclass VPseudoVSALU_VV_VX_VI<Operand ImmType = simm5, string Constraint = ""> {
   foreach m = MxList in {
     defvar mx = m.MX;
     defvar WriteVSALUV_MX = !cast<SchedWrite>("WriteVSALUV_" # mx);
     defvar WriteVSALUX_MX = !cast<SchedWrite>("WriteVSALUX_" # mx);

llvm/lib/Target/RISCV/RISCVScheduleV.td

 defm "" : LMULSchedReads<"ReadVFMovFV">;
 defm "" : LMULSchedReads<"ReadVFMovFX">;
 // 16.3. Vector Slide Instructions
 defm "" : LMULSchedReads<"ReadVISlideV">;
 defm "" : LMULSchedReads<"ReadVISlideX">;
 defm "" : LMULSchedReads<"ReadVFSlideV">;
 defm "" : LMULSchedReads<"ReadVFSlideF">;
 // 16.4. Vector Register Gather Instructions
-defm "" : LMULSchedReads<"ReadVRGatherVV">;
-defm "" : LMULSchedReads<"ReadVRGatherVX">;
+defm "" : LMULSchedReads<"ReadVRGatherVV_data">;
+defm "" : LMULSchedReads<"ReadVRGatherVV_index">;
+defm "" : LMULSchedReads<"ReadVRGatherVX_data">;
+defm "" : LMULSchedReads<"ReadVRGatherVX_index">;
+defm "" : LMULSchedReads<"ReadVRGatherVI_data">;
 // 16.5. Vector Compress Instruction
 defm "" : LMULSchedReads<"ReadVCompressV">;
 // 16.6. Whole Vector Register Move
 // These are already LMUL aware
 def ReadVMov1V        : SchedRead;
 def ReadVMov2V        : SchedRead;
 def ReadVMov4V        : SchedRead;
 def ReadVMov8V        : SchedRead;

 defm "" : LMULReadAdvance<"ReadVIMovXX", 0>;
 defm "" : LMULReadAdvance<"ReadVFMovVF", 0>;
 defm "" : LMULReadAdvance<"ReadVFMovFV", 0>;
 defm "" : LMULReadAdvance<"ReadVFMovFX", 0>;
 defm "" : LMULReadAdvance<"ReadVISlideV", 0>;
 defm "" : LMULReadAdvance<"ReadVISlideX", 0>;
 defm "" : LMULReadAdvance<"ReadVFSlideV", 0>;
 defm "" : LMULReadAdvance<"ReadVFSlideF", 0>;
-defm "" : LMULReadAdvance<"ReadVRGatherVV", 0>;
-defm "" : LMULReadAdvance<"ReadVRGatherVX", 0>;
+defm "" : LMULReadAdvance<"ReadVRGatherVV_data", 0>;
+defm "" : LMULReadAdvance<"ReadVRGatherVV_index", 0>;
+defm "" : LMULReadAdvance<"ReadVRGatherVX_data", 0>;
+defm "" : LMULReadAdvance<"ReadVRGatherVX_index", 0>;
+defm "" : LMULReadAdvance<"ReadVRGatherVI_data", 0>;
 defm "" : LMULReadAdvance<"ReadVCompressV", 0>;
 // These are already LMUL aware
 def : ReadAdvance<ReadVMov1V, 0>;
 def : ReadAdvance<ReadVMov2V, 0>;
 def : ReadAdvance<ReadVMov4V, 0>;
 def : ReadAdvance<ReadVMov8V, 0>;
 
 // Others
 def : ReadAdvance<ReadVMask, 0>;
 
 } // Unsupported
 } // UnsupportedSchedV