[ControlHeightReduction] Don't combine a "poison" branch

[kazu]

Summary

Without this patch, the control height reduction pass would combine a
"poison" branch with an earlier well-defined branch, turning the
earlier branch into a "poison" branch also.

This patch fixes the problem by rejecting "poison" conditional
branches.

[davidxl]

lgtm

[nikic]

The value may be poison even if it's not literally poison. The problem seems to be that the condition gets swapped. CHR generates select i1 poison, i1 %arg, i1 false rather than the correct select i1 %arg, i1 poison, i1 false. Either that swapping should not occur (if it's not important to what CHR is doing) or the condition needs to be frozen.

[davidxl]

In D145008#4160793, @nikic wrote:

The value may be poison even if it's not literally poison. The problem seems to be that the condition gets swapped. CHR generates select i1 poison, i1 %arg, i1 false rather than the correct select i1 %arg, i1 poison, i1 false. Either that swapping should not occur (if it's not important to what CHR is doing) or the condition needs to be frozen.

Correct -- kazu@ brought it up before sending the patch as well -- is there existing interface to query for propagated poison?

The swap is triggered because of the profile data says it is profitable -- while it is itself a bug to deal with, it is independent to this fix.

[nikic]

In D145008#4162106, @davidxl wrote:

In D145008#4160793, @nikic wrote:

The value may be poison even if it's not literally poison. The problem seems to be that the condition gets swapped. CHR generates select i1 poison, i1 %arg, i1 false rather than the correct select i1 %arg, i1 poison, i1 false. Either that swapping should not occur (if it's not important to what CHR is doing) or the condition needs to be frozen.

Correct -- kazu@ brought it up before sending the patch as well -- is there existing interface to query for propagated poison?

There is isGuaranteedNotToBeUndefOrPoison(), but here you want to use freeze as a fallback.

The swap is triggered because of the profile data says it is profitable -- while it is itself a bug to deal with, it is independent to this fix.

How can the swap be profitable when flattening control flow into a select? Shouldn't it be independent of order at that point?

[kazu]

In D145008#4162517, @nikic wrote:

In D145008#4162106, @davidxl wrote:

In D145008#4160793, @nikic wrote:

The value may be poison even if it's not literally poison. The problem seems to be that the condition gets swapped. CHR generates select i1 poison, i1 %arg, i1 false rather than the correct select i1 %arg, i1 poison, i1 false. Either that swapping should not occur (if it's not important to what CHR is doing) or the condition needs to be frozen.

Correct -- kazu@ brought it up before sending the patch as well -- is there existing interface to query for propagated poison?

There is isGuaranteedNotToBeUndefOrPoison(), but here you want to use freeze as a fallback.

Do you mean something like this in pseudo code?

if (isGuaranteedNotToBeUndefOrPoison(Cond))
  Use Cond As is;
else
  Use freeze to prevent the potential poison from propagating further;

[nikic]

In D145008#4162691, @kazu wrote:

In D145008#4162517, @nikic wrote:

In D145008#4162106, @davidxl wrote:

In D145008#4160793, @nikic wrote:

The value may be poison even if it's not literally poison. The problem seems to be that the condition gets swapped. CHR generates select i1 poison, i1 %arg, i1 false rather than the correct select i1 %arg, i1 poison, i1 false. Either that swapping should not occur (if it's not important to what CHR is doing) or the condition needs to be frozen.

Correct -- kazu@ brought it up before sending the patch as well -- is there existing interface to query for propagated poison?

There is isGuaranteedNotToBeUndefOrPoison(), but here you want to use freeze as a fallback.

Do you mean something like this in pseudo code?

if (isGuaranteedNotToBeUndefOrPoison(Cond))
  Use Cond As is;
else
  Use freeze to prevent the potential poison from propagating further;

Yes, see the existing code in addToMergedCondition() for handling branch to select conversion. It needs to be extended for the branch case if the conditions are swapped.

[davidxl]

In D145008#4162517, @nikic wrote:

In D145008#4162106, @davidxl wrote:

In D145008#4160793, @nikic wrote:

The value may be poison even if it's not literally poison. The problem seems to be that the condition gets swapped. CHR generates select i1 poison, i1 %arg, i1 false rather than the correct select i1 %arg, i1 poison, i1 false. Either that swapping should not occur (if it's not important to what CHR is doing) or the condition needs to be frozen.

Correct -- kazu@ brought it up before sending the patch as well -- is there existing interface to query for propagated poison?

There is isGuaranteedNotToBeUndefOrPoison(), but here you want to use freeze as a fallback.

The swap is triggered because of the profile data says it is profitable -- while it is itself a bug to deal with, it is independent to this fix.

How can the swap be profitable when flattening control flow into a select? Shouldn't it be independent of order at that point?

It looks like there is a hidden profit analysis issue to be fixed, shown in the modified test below. The first branch does not have profile data attached, but CHR still decides to swap the order of the combined branch (from BB3 and BB5) with it.
@n = dso_local local_unnamed_addr global i32 0, align 4

define void @chr_poison(i1 %arg, i1 %arg2, i1 %arg3) !prof !29 {

br i1 %arg2, label %bb3, label %bb2

bb2:

store i32 2, ptr @n, align 4
ret void

bb3:

store i32 3, ptr @n, align 4
br i1 %arg3, label %bb5, label %bb4, !prof !30

bb4:

store i32 4, ptr @n, align 4
br label %bb5

bb5:

store i32 5, ptr @n, align 4
br i1 %arg, label %bb2, label %bb6, !prof !31

bb6:

store i32 6, ptr @n, align 4
br label %bb2

bb7:

store i32 7, ptr @n, align 4
br label %bb5

}

!llvm.module.flags = !{!0}

!0 = !{i32 1, !"ProfileSummary", !1}
!1 = !{!2, !3, !4, !5, !6, !7, !8, !9, !10, !11}
!2 = !{!"ProfileFormat", !"SampleProfile"}
!3 = !{!"TotalCount", i64 2625732223}
!4 = !{!"MaxCount", i64 6099111}
!5 = !{!"MaxInternalCount", i64 0}
!6 = !{!"MaxFunctionCount", i64 8812263}
!7 = !{!"NumCounts", i64 1399554}
!8 = !{!"NumFunctions", i64 14940}
!9 = !{!"IsPartialProfile", i64 0}
!10 = !{!"PartialProfileRatio", double 0.000000e+00}
!11 = !{!"DetailedSummary", !12}
!12 = !{!13, !14, !15, !16, !17, !18, !19, !20, !21, !22, !23, !24, !25, !26, !27, !28}
!13 = !{i32 10000, i64 6099103, i32 8}
!14 = !{i32 100000, i64 6083920, i32 44}
!15 = !{i32 200000, i64 5615450, i32 92}
!16 = !{i32 300000, i64 658615, i32 301}
!17 = !{i32 400000, i64 276706, i32 1049}
!18 = !{i32 500000, i64 224143, i32 2110}
!19 = !{i32 600000, i64 155027, i32 3480}
!20 = !{i32 700000, i64 62158, i32 6258}
!21 = !{i32 800000, i64 29875, i32 12602}
!22 = !{i32 900000, i64 5684, i32 34979}
!23 = !{i32 950000, i64 1439, i32 81728}
!24 = !{i32 990000, i64 319, i32 227620}
!25 = !{i32 999000, i64 34, i32 416158}
!26 = !{i32 999900, i64 4, i32 603970}
!27 = !{i32 999990, i64 1, i32 750171}
!28 = !{i32 999999, i64 1, i32 750171}
!29 = !{!"function_entry_count", i64 3204}
!30 = !{!"branch_weights", i32 2126980204, i32 20503444}
!31 = !{!"branch_weights", i32 997, i32 2}

[kazu]

In D145008#4162710, @nikic wrote:

In D145008#4162691, @kazu wrote:

In D145008#4162517, @nikic wrote:

In D145008#4162106, @davidxl wrote:

In D145008#4160793, @nikic wrote:

The value may be poison even if it's not literally poison. The problem seems to be that the condition gets swapped. CHR generates select i1 poison, i1 %arg, i1 false rather than the correct select i1 %arg, i1 poison, i1 false. Either that swapping should not occur (if it's not important to what CHR is doing) or the condition needs to be frozen.

Correct -- kazu@ brought it up before sending the patch as well -- is there existing interface to query for propagated poison?

There is isGuaranteedNotToBeUndefOrPoison(), but here you want to use freeze as a fallback.

Do you mean something like this in pseudo code?

if (isGuaranteedNotToBeUndefOrPoison(Cond))
  Use Cond As is;
else
  Use freeze to prevent the potential poison from propagating further;

Yes, see the existing code in addToMergedCondition() for handling branch to select conversion. It needs to be extended for the branch case if the conditions are swapped.

OK. Now, what if Cond is guaranteed to be a poison? Should we still transform the code?

[nikic]

In D145008#4162887, @kazu wrote:

OK. Now, what if Cond is guaranteed to be a poison? Should we still transform the code?

I'd say "Yes", in the sense that we should not go out of our way to handle this special case. We should only make sure that the transform is correct.

A branch on poison should really not reach this code and get optimized away to unreachable earlier -- the reason it isn't is that this would take some annoying test updates, see D140892.

[kazu]

Freeze potentially poisonous conditions.

[kazu]

In D145008#4163051, @nikic wrote:

A branch on poison should really not reach this code and get optimized away to unreachable earlier -- the reason it isn't is that this would take some annoying test updates, see D140892.

I was actually getting br i1 poison prior to b374423304a8d91d590d0ce5ab1b381296d6dfb2, which moved the CHR pass to module optimization pipeline.

I just updated the patch here. Please take a look. Thanks!

[nikic]

llvm/lib/Transforms/Instrumentation/ControlHeightReduction.cpp

1966

Is it possible to detect the case where a swap occurred, or is this too complicated?

[kazu]

llvm/lib/Transforms/Instrumentation/ControlHeightReduction.cpp

1966

What do you mean by a swap? Are you referring to a case where we should generate:

select i1 %arg, i1 poison, i1 false

instead of

select i1 poison, i1 %arg, i1 false

(modulo freeze)?

If so, yes, it's possible but complicated. One way goes something like this. When we call addToMergedCondition to add poison to the condition chain, we could defer that and then add poison at the end of the condition chain. But then I am not sure what we are really achieving. Also, special-casing poison here goes against your earlier comment that we don't want to go out of our way to handle poison. I am inclined to keeping things simple with freeze.

[kazu]

Please take a look. Thanks!

[nikic]

LGTM. I looked into this a bit more, and CHR is not just reordering the checks, but also hoisting them across other conditions. It should be possible to limit when freeze is applied, but the conditions for doing this aren't obvious to me, so I'm fine with landing this in the meantime.

llvm/test/Transforms/PGOProfile/chr-poison.ll

101

Please reduce unnecessary metadata.

llvm/lib/Transforms/Instrumentation/ControlHeightReduction.cpp

if (!IsTrueBiased) {
     // branch, negate the icmp predicate and swap the branch targets and avoid
     // inserting an Xor to negate Cond.
     auto *ICmp = dyn_cast<ICmpInst>(Cond);
     if (!ICmp ||
         !negateICmpIfUsedByBranchOrSelectOnly(ICmp, BranchOrSelect, Scope))
       Cond = IRB.CreateXor(ConstantInt::getTrue(F.getContext()), Cond);
   }
 
-  // Select conditions can be poison, while branching on poison is immediate
-  // undefined behavior. As such, we need to freeze potentially poisonous
-  // conditions derived from selects.
-  if (isa<SelectInst>(BranchOrSelect) &&
-      !isGuaranteedNotToBeUndefOrPoison(Cond))
+  // Freeze potentially poisonous conditions.
+  if (!isGuaranteedNotToBeUndefOrPoison(Cond))
     Cond = IRB.CreateFreeze(Cond);
 
   // Use logical and to avoid propagating poison from later conditions.
   MergedCondition = IRB.CreateLogicalAnd(MergedCondition, Cond);
 }
 
 void CHR::transformScopes(SmallVectorImpl<CHRScope *> &CHRScopes) {
   unsigned I = 0;

llvm/test/Transforms/PGOProfile/chr-poison.ll

+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -passes='require<profile-summary>,function(chr)' -S | FileCheck %s
+
+; Make sure we freeze poison.
+define void @chr_poison(i1 %arg) !prof !15 {
+; CHECK-LABEL: @chr_poison(
+; CHECK-NEXT:    [[TMP1:%.*]] = freeze i1 poison
+; CHECK-NEXT:    [[TMP2:%.*]] = select i1 true, i1 [[TMP1]], i1 false
+; CHECK-NEXT:    [[TMP3:%.*]] = freeze i1 [[ARG:%.*]]
+; CHECK-NEXT:    [[TMP4:%.*]] = select i1 [[TMP2]], i1 [[TMP3]], i1 false
+; CHECK-NEXT:    br i1 [[TMP4]], label [[DOTSPLIT:%.*]], label [[DOTSPLIT_NONCHR:%.*]], !prof [[PROF30:![0-9]+]]
+; CHECK:       .split:
+; CHECK-NEXT:    br i1 false, label [[BB3:%.*]], label [[BB4:%.*]]
+; CHECK:       bb3:
+; CHECK-NEXT:    [[SEL:%.*]] = select i1 false, ptr null, ptr null
+; CHECK-NEXT:    br label [[BB6:%.*]]
+; CHECK:       bb4:
+; CHECK-NEXT:    br i1 true, label [[BB6]], label [[BB5:%.*]], !prof [[PROF31:![0-9]+]]
+; CHECK:       bb5:
+; CHECK-NEXT:    br label [[BB6]]
+; CHECK:       bb6:
+; CHECK-NEXT:    br i1 false, label [[BB9:%.*]], label [[BB7:%.*]]
+; CHECK:       bb7:
+; CHECK-NEXT:    br i1 true, label [[BB9]], label [[BB8:%.*]], !prof [[PROF32:![0-9]+]]
+; CHECK:       bb8:
+; CHECK-NEXT:    br label [[BB9]]
+; CHECK:       .split.nonchr:
+; CHECK-NEXT:    br i1 false, label [[BB3_NONCHR:%.*]], label [[BB4_NONCHR:%.*]]
+; CHECK:       bb3.nonchr:
+; CHECK-NEXT:    [[SEL_NONCHR:%.*]] = select i1 false, ptr null, ptr null
+; CHECK-NEXT:    br label [[BB6_NONCHR:%.*]]
+; CHECK:       bb4.nonchr:
+; CHECK-NEXT:    br i1 poison, label [[BB6_NONCHR]], label [[BB5_NONCHR:%.*]], !prof [[PROF31]]
+; CHECK:       bb5.nonchr:
+; CHECK-NEXT:    br label [[BB6_NONCHR]]
+; CHECK:       bb6.nonchr:
+; CHECK-NEXT:    br i1 false, label [[BB9]], label [[BB7_NONCHR:%.*]]
+; CHECK:       bb7.nonchr:
+; CHECK-NEXT:    br i1 [[ARG]], label [[BB9]], label [[BB8_NONCHR:%.*]], !prof [[PROF32]]
+; CHECK:       bb8.nonchr:
+; CHECK-NEXT:    br label [[BB9]]
+; CHECK:       bb9:
+; CHECK-NEXT:    ret void
+;
+  br i1 false, label %bb3, label %bb4
+
+bb3:
+  %sel = select i1 false, ptr null, ptr null
+  br label %bb6
+
+bb4:
+  br i1 poison, label %bb6, label %bb5, !prof !16
+
+bb5:
+  br label %bb6
+
+bb6:
+  br i1 false, label %bb9, label %bb7
+
+bb7:
+  br i1 %arg, label %bb9, label %bb8, !prof !17
+
+bb8:
+  br label %bb9
+
+bb9:
+  ret void
+}
+
+!llvm.module.flags = !{!0}
+
+!0 = !{i32 1, !"ProfileSummary", !1}
+!1 = !{!2, !3, !4, !5, !6, !7, !8, !9, !10, !11}
+!2 = !{!"ProfileFormat", !"SampleProfile"}
+!3 = !{!"TotalCount", i64 2625732223}
+!4 = !{!"MaxCount", i64 6099111}
+!5 = !{!"MaxInternalCount", i64 0}
+!6 = !{!"MaxFunctionCount", i64 1000000}
+!7 = !{!"NumCounts", i64 1000000}
+!8 = !{!"NumFunctions", i64 14940}
+!9 = !{!"IsPartialProfile", i64 0}
+!10 = !{!"PartialProfileRatio", double 0.000000e+00}
+!11 = !{!"DetailedSummary", !12}
+!12 = !{!13, !14}
+!13 = !{i32 100000, i64 6083920, i32 44}
+!14 = !{i32 999999, i64 1, i32 1000000}
+!15 = !{!"function_entry_count", i64 1000}
+!16 = !{!"branch_weights", i32 1, i32 0}
+!17 = !{!"branch_weights", i32 1, i32 0}

llvm/test/Transforms/PGOProfile/chr.ll

 ;     foo()
 ;   if ((t0 & 2) != 0)
 ;     foo()
 ; }
 define void @test_chr_1(ptr %i) !prof !14 {
 ; CHECK-LABEL: @test_chr_1(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP0:%.*]] = load i32, ptr [[I:%.*]], align 4
-; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[TMP0]], 3
+; CHECK-NEXT:    [[DOTFR1:%.*]] = freeze i32 [[TMP0]]
+; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[DOTFR1]], 3
 ; CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 3
 ; CHECK-NEXT:    br i1 [[TMP2]], label [[BB0:%.*]], label [[ENTRY_SPLIT_NONCHR:%.*]], !prof [[PROF15:![0-9]+]]
 ; CHECK:       bb0:
 ; CHECK-NEXT:    call void @foo()
 ; CHECK-NEXT:    call void @foo()
 ; CHECK-NEXT:    br label [[BB3:%.*]]
 ; CHECK:       entry.split.nonchr:
-; CHECK-NEXT:    [[TMP3:%.*]] = and i32 [[TMP0]], 1
+; CHECK-NEXT:    [[TMP3:%.*]] = and i32 [[DOTFR1]], 1
 ; CHECK-NEXT:    [[DOTNOT:%.*]] = icmp eq i32 [[TMP3]], 0
 ; CHECK-NEXT:    br i1 [[DOTNOT]], label [[BB1_NONCHR:%.*]], label [[BB0_NONCHR:%.*]], !prof [[PROF16:![0-9]+]]
 ; CHECK:       bb0.nonchr:
 ; CHECK-NEXT:    call void @foo()
 ; CHECK-NEXT:    br label [[BB1_NONCHR]]
 ; CHECK:       bb1.nonchr:
-; CHECK-NEXT:    [[TMP4:%.*]] = and i32 [[TMP0]], 2
+; CHECK-NEXT:    [[TMP4:%.*]] = and i32 [[DOTFR1]], 2
 ; CHECK-NEXT:    [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0
 ; CHECK-NEXT:    br i1 [[TMP5]], label [[BB3]], label [[BB2_NONCHR:%.*]], !prof [[PROF16]]
 ; CHECK:       bb2.nonchr:
 ; CHECK-NEXT:    call void @foo()
 ; CHECK-NEXT:    br label [[BB3]]
 ; CHECK:       bb3:
 ; CHECK-NEXT:    ret void
 ;

 ;     bar()
 ;   if ((t0 & 4) != 0)
 ;     foo()
 ; }
 define void @test_chr_1_1(ptr %i) !prof !14 {
 ; CHECK-LABEL: @test_chr_1_1(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP0:%.*]] = load i32, ptr [[I:%.*]], align 4
-; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[TMP0]], 7
+; CHECK-NEXT:    [[DOTFR1:%.*]] = freeze i32 [[TMP0]]
+; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[DOTFR1]], 7
 ; CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 7
 ; CHECK-NEXT:    br i1 [[TMP2]], label [[BB0:%.*]], label [[ENTRY_SPLIT_NONCHR:%.*]], !prof [[PROF15]]
 ; CHECK:       bb0:
 ; CHECK-NEXT:    call void @foo()
 ; CHECK-NEXT:    call void @foo()
 ; CHECK-NEXT:    br label [[BB5:%.*]]
 ; CHECK:       entry.split.nonchr:
-; CHECK-NEXT:    [[TMP3:%.*]] = and i32 [[TMP0]], 1
+; CHECK-NEXT:    [[TMP3:%.*]] = and i32 [[DOTFR1]], 1
 ; CHECK-NEXT:    [[DOTNOT:%.*]] = icmp eq i32 [[TMP3]], 0
 ; CHECK-NEXT:    br i1 [[DOTNOT]], label [[BB1_NONCHR:%.*]], label [[BB0_NONCHR:%.*]], !prof [[PROF16]]
 ; CHECK:       bb0.nonchr:
 ; CHECK-NEXT:    call void @foo()
 ; CHECK-NEXT:    br label [[BB1_NONCHR]]
 ; CHECK:       bb1.nonchr:
-; CHECK-NEXT:    [[TMP4:%.*]] = and i32 [[TMP0]], 2
+; CHECK-NEXT:    [[TMP4:%.*]] = and i32 [[DOTFR1]], 2
 ; CHECK-NEXT:    [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0
 ; CHECK-NEXT:    br i1 [[TMP5]], label [[BB2_NONCHR:%.*]], label [[BB3_NONCHR:%.*]], !prof [[PROF16]]
 ; CHECK:       bb2.nonchr:
 ; CHECK-NEXT:    call void @bar()
 ; CHECK-NEXT:    br label [[BB3_NONCHR]]
 ; CHECK:       bb3.nonchr:
-; CHECK-NEXT:    [[TMP6:%.*]] = and i32 [[TMP0]], 4
+; CHECK-NEXT:    [[TMP6:%.*]] = and i32 [[DOTFR1]], 4
 ; CHECK-NEXT:    [[TMP7:%.*]] = icmp eq i32 [[TMP6]], 0
 ; CHECK-NEXT:    br i1 [[TMP7]], label [[BB5]], label [[BB4_NONCHR:%.*]], !prof [[PROF16]]
 ; CHECK:       bb4.nonchr:
 ; CHECK-NEXT:    call void @foo()
 ; CHECK-NEXT:    br label [[BB5]]
 ; CHECK:       bb5:
 ; CHECK-NEXT:    ret void
 ;

 ;     foo()
 ;   if ((t0 & 2) != 0)
 ;     foo()
 ; }
 define void @test_chr_2(ptr %i) !prof !14 {
 ; CHECK-LABEL: @test_chr_2(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP0:%.*]] = load i32, ptr [[I:%.*]], align 4
-; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[TMP0]], 3
+; CHECK-NEXT:    [[DOTFR1:%.*]] = freeze i32 [[TMP0]]
+; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[DOTFR1]], 3
 ; CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 3
 ; CHECK-NEXT:    br i1 [[TMP2]], label [[BB1:%.*]], label [[ENTRY_SPLIT_NONCHR:%.*]], !prof [[PROF15]]
 ; CHECK:       bb1:
 ; CHECK-NEXT:    call void @foo()
 ; CHECK-NEXT:    call void @foo()
 ; CHECK-NEXT:    br label [[BB4:%.*]]
 ; CHECK:       entry.split.nonchr:
-; CHECK-NEXT:    [[TMP3:%.*]] = and i32 [[TMP0]], 255
+; CHECK-NEXT:    [[TMP3:%.*]] = and i32 [[DOTFR1]], 255
 ; CHECK-NEXT:    [[DOTNOT:%.*]] = icmp eq i32 [[TMP3]], 0
 ; CHECK-NEXT:    br i1 [[DOTNOT]], label [[BB4]], label [[BB0_NONCHR:%.*]], !prof [[PROF16]]
 ; CHECK:       bb0.nonchr:
-; CHECK-NEXT:    [[TMP4:%.*]] = and i32 [[TMP0]], 1
+; CHECK-NEXT:    [[TMP4:%.*]] = and i32 [[DOTFR1]], 1
 ; CHECK-NEXT:    [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0
 ; CHECK-NEXT:    br i1 [[TMP5]], label [[BB2_NONCHR:%.*]], label [[BB1_NONCHR:%.*]], !prof [[PROF16]]
 ; CHECK:       bb2.nonchr:
-; CHECK-NEXT:    [[TMP6:%.*]] = and i32 [[TMP0]], 2
+; CHECK-NEXT:    [[TMP6:%.*]] = and i32 [[DOTFR1]], 2
 ; CHECK-NEXT:    [[TMP7:%.*]] = icmp eq i32 [[TMP6]], 0
 ; CHECK-NEXT:    br i1 [[TMP7]], label [[BB4]], label [[BB3_NONCHR:%.*]], !prof [[PROF16]]
 ; CHECK:       bb3.nonchr:
 ; CHECK-NEXT:    call void @foo()
 ; CHECK-NEXT:    br label [[BB4]]
 ; CHECK:       bb1.nonchr:
 ; CHECK-NEXT:    call void @foo()
 ; CHECK-NEXT:    br label [[BB2_NONCHR]]

 ;     foo()
 ;   if ((t2 & 8) != 0)
 ;     foo()
 ; }
 define void @test_chr_3(ptr %i) !prof !14 {
 ; CHECK-LABEL: @test_chr_3(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP0:%.*]] = load i32, ptr [[I:%.*]], align 4
-; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[TMP0]], 3
+; CHECK-NEXT:    [[DOTFR1:%.*]] = freeze i32 [[TMP0]]
+; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[DOTFR1]], 3
 ; CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 3
 ; CHECK-NEXT:    br i1 [[TMP2]], label [[BB0:%.*]], label [[ENTRY_SPLIT_NONCHR:%.*]], !prof [[PROF15]]
 ; CHECK:       bb0:
 ; CHECK-NEXT:    call void @foo()
 ; CHECK-NEXT:    call void @foo()
 ; CHECK-NEXT:    br label [[BB3:%.*]]
 ; CHECK:       entry.split.nonchr:
-; CHECK-NEXT:    [[TMP3:%.*]] = and i32 [[TMP0]], 1
+; CHECK-NEXT:    [[TMP3:%.*]] = and i32 [[DOTFR1]], 1
 ; CHECK-NEXT:    [[DOTNOT:%.*]] = icmp eq i32 [[TMP3]], 0
 ; CHECK-NEXT:    br i1 [[DOTNOT]], label [[BB1_NONCHR:%.*]], label [[BB0_NONCHR:%.*]], !prof [[PROF16]]
 ; CHECK:       bb0.nonchr:
 ; CHECK-NEXT:    call void @foo()
 ; CHECK-NEXT:    br label [[BB1_NONCHR]]
 ; CHECK:       bb1.nonchr:
-; CHECK-NEXT:    [[TMP4:%.*]] = and i32 [[TMP0]], 2
+; CHECK-NEXT:    [[TMP4:%.*]] = and i32 [[DOTFR1]], 2
 ; CHECK-NEXT:    [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0
 ; CHECK-NEXT:    br i1 [[TMP5]], label [[BB3]], label [[BB2_NONCHR:%.*]], !prof [[PROF16]]
 ; CHECK:       bb2.nonchr:
 ; CHECK-NEXT:    call void @foo()
 ; CHECK-NEXT:    br label [[BB3]]
 ; CHECK:       bb3:
 ; CHECK-NEXT:    [[TMP6:%.*]] = load i32, ptr [[I]], align 4
-; CHECK-NEXT:    [[TMP7:%.*]] = and i32 [[TMP6]], 12
+; CHECK-NEXT:    [[DOTFR2:%.*]] = freeze i32 [[TMP6]]
+; CHECK-NEXT:    [[TMP7:%.*]] = and i32 [[DOTFR2]], 12
 ; CHECK-NEXT:    [[TMP8:%.*]] = icmp eq i32 [[TMP7]], 12
 ; CHECK-NEXT:    br i1 [[TMP8]], label [[BB4:%.*]], label [[BB3_SPLIT_NONCHR:%.*]], !prof [[PROF15]]
 ; CHECK:       bb4:
 ; CHECK-NEXT:    call void @foo()
 ; CHECK-NEXT:    call void @foo()
 ; CHECK-NEXT:    br label [[BB7:%.*]]
 ; CHECK:       bb3.split.nonchr:
-; CHECK-NEXT:    [[TMP9:%.*]] = and i32 [[TMP6]], 4
-; CHECK-NEXT:    [[DOTNOT1:%.*]] = icmp eq i32 [[TMP9]], 0
-; CHECK-NEXT:    br i1 [[DOTNOT1]], label [[BB5_NONCHR:%.*]], label [[BB4_NONCHR:%.*]], !prof [[PROF16]]
+; CHECK-NEXT:    [[TMP9:%.*]] = and i32 [[DOTFR2]], 4
+; CHECK-NEXT:    [[DOTNOT3:%.*]] = icmp eq i32 [[TMP9]], 0
+; CHECK-NEXT:    br i1 [[DOTNOT3]], label [[BB5_NONCHR:%.*]], label [[BB4_NONCHR:%.*]], !prof [[PROF16]]
 ; CHECK:       bb4.nonchr:
 ; CHECK-NEXT:    call void @foo()
 ; CHECK-NEXT:    br label [[BB5_NONCHR]]
 ; CHECK:       bb5.nonchr:
-; CHECK-NEXT:    [[TMP10:%.*]] = and i32 [[TMP6]], 8
+; CHECK-NEXT:    [[TMP10:%.*]] = and i32 [[DOTFR2]], 8
 ; CHECK-NEXT:    [[TMP11:%.*]] = icmp eq i32 [[TMP10]], 0
 ; CHECK-NEXT:    br i1 [[TMP11]], label [[BB7]], label [[BB6_NONCHR:%.*]], !prof [[PROF16]]
 ; CHECK:       bb6.nonchr:
 ; CHECK-NEXT:    call void @foo()
 ; CHECK-NEXT:    br label [[BB7]]
 ; CHECK:       bb7:
 ; CHECK-NEXT:    ret void
 ;

 ;     sum3 = sum + 44
 ;     sum = (t0 & 8) ? sum3 : (sum3 + 44)
 ;   }
 ; }
 ; return sum
 define i32 @test_chr_5_1(ptr %i, i32 %sum0) !prof !14 {
 ; CHECK-LABEL: @test_chr_5_1(
 ; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[SUM0_FR:%.*]] = freeze i32 [[SUM0:%.*]]
 ; CHECK-NEXT:    [[TMP0:%.*]] = load i32, ptr [[I:%.*]], align 4
 ; CHECK-NEXT:    [[DOTFR1:%.*]] = freeze i32 [[TMP0]]
-; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[SUM0:%.*]], 4
+; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[SUM0_FR]], 4
 ; CHECK-NEXT:    [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0
 ; CHECK-NEXT:    [[TMP3:%.*]] = and i32 [[DOTFR1]], 11
 ; CHECK-NEXT:    [[TMP4:%.*]] = icmp eq i32 [[TMP3]], 11
-; CHECK-NEXT:    [[TMP5:%.*]] = select i1 [[TMP4]], i1 [[TMP2]], i1 false
+; CHECK-NEXT:    [[TMP5:%.*]] = and i1 [[TMP4]], [[TMP2]]
 ; CHECK-NEXT:    br i1 [[TMP5]], label [[BB0:%.*]], label [[ENTRY_SPLIT_NONCHR:%.*]], !prof [[PROF15]]
 ; CHECK:       bb0:
-; CHECK-NEXT:    [[TMP6:%.*]] = add i32 [[SUM0]], 85
-; CHECK-NEXT:    [[TMP7:%.*]] = add i32 [[SUM0]], 173
+; CHECK-NEXT:    [[TMP6:%.*]] = add i32 [[SUM0_FR]], 85
+; CHECK-NEXT:    [[TMP7:%.*]] = add i32 [[SUM0_FR]], 173
 ; CHECK-NEXT:    br label [[BB3:%.*]]
 ; CHECK:       entry.split.nonchr:
 ; CHECK-NEXT:    [[TMP8:%.*]] = and i32 [[DOTFR1]], 255
 ; CHECK-NEXT:    [[DOTNOT:%.*]] = icmp eq i32 [[TMP8]], 0
 ; CHECK-NEXT:    br i1 [[DOTNOT]], label [[BB3]], label [[BB0_NONCHR:%.*]], !prof [[PROF16]]
 ; CHECK:       bb0.nonchr:
 ; CHECK-NEXT:    [[TMP9:%.*]] = and i32 [[DOTFR1]], 1
 ; CHECK-NEXT:    [[TMP10:%.*]] = icmp eq i32 [[TMP9]], 0
-; CHECK-NEXT:    [[TMP11:%.*]] = add i32 [[SUM0]], 42
-; CHECK-NEXT:    [[SUM1_NONCHR:%.*]] = select i1 [[TMP10]], i32 [[SUM0]], i32 [[TMP11]], !prof [[PROF16]]
+; CHECK-NEXT:    [[TMP11:%.*]] = add i32 [[SUM0_FR]], 42
+; CHECK-NEXT:    [[SUM1_NONCHR:%.*]] = select i1 [[TMP10]], i32 [[SUM0_FR]], i32 [[TMP11]], !prof [[PROF16]]
 ; CHECK-NEXT:    [[TMP12:%.*]] = and i32 [[DOTFR1]], 2
 ; CHECK-NEXT:    [[TMP13:%.*]] = icmp eq i32 [[TMP12]], 0
 ; CHECK-NEXT:    [[TMP14:%.*]] = add i32 [[SUM1_NONCHR]], 43
 ; CHECK-NEXT:    [[SUM2_NONCHR:%.*]] = select i1 [[TMP13]], i32 [[SUM1_NONCHR]], i32 [[TMP14]], !prof [[PROF16]]
-; CHECK-NEXT:    [[TMP15:%.*]] = and i32 [[SUM0]], 4
+; CHECK-NEXT:    [[TMP15:%.*]] = and i32 [[SUM0_FR]], 4
 ; CHECK-NEXT:    [[TMP16:%.*]] = icmp eq i32 [[TMP15]], 0
 ; CHECK-NEXT:    [[TMP17:%.*]] = and i32 [[DOTFR1]], 8
 ; CHECK-NEXT:    [[TMP18:%.*]] = icmp eq i32 [[TMP17]], 0
 ; CHECK-NEXT:    [[SUM4_NONCHR_V:%.*]] = select i1 [[TMP18]], i32 44, i32 88
 ; CHECK-NEXT:    [[SUM4_NONCHR:%.*]] = add i32 [[SUM2_NONCHR]], [[SUM4_NONCHR_V]]
 ; CHECK-NEXT:    [[SUM5_NONCHR:%.*]] = select i1 [[TMP16]], i32 [[SUM2_NONCHR]], i32 [[SUM4_NONCHR]], !prof [[PROF16]]
 ; CHECK-NEXT:    br label [[BB3]]
 ; CHECK:       bb3:
-; CHECK-NEXT:    [[SUM6:%.*]] = phi i32 [ [[TMP7]], [[BB0]] ], [ [[SUM0]], [[ENTRY_SPLIT_NONCHR]] ], [ [[SUM5_NONCHR]], [[BB0_NONCHR]] ]
+; CHECK-NEXT:    [[SUM6:%.*]] = phi i32 [ [[TMP7]], [[BB0]] ], [ [[SUM0_FR]], [[ENTRY_SPLIT_NONCHR]] ], [ [[SUM5_NONCHR]], [[BB0_NONCHR]] ]
 ; CHECK-NEXT:    ret i32 [[SUM6]]
 ;
 entry:
   %0 = load i32, ptr %i
   %1 = and i32 %0, 255
   %2 = icmp eq i32 %1, 0
   br i1 %2, label %bb3, label %bb0, !prof !15
 

 ; }
 ; return sum
 define i32 @test_chr_6(ptr %i, ptr %j, i32 %sum0) !prof !14 {
 ; CHECK-LABEL: @test_chr_6(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[I0:%.*]] = load i32, ptr [[I:%.*]], align 4
 ; CHECK-NEXT:    [[I0_FR:%.*]] = freeze i32 [[I0]]
 ; CHECK-NEXT:    [[J0:%.*]] = load i32, ptr [[J:%.*]], align 4
-; CHECK-NEXT:    [[V9:%.*]] = and i32 [[J0]], 4
+; CHECK-NEXT:    [[J0_FR:%.*]] = freeze i32 [[J0]]
+; CHECK-NEXT:    [[V9:%.*]] = and i32 [[J0_FR]], 4
 ; CHECK-NEXT:    [[V10:%.*]] = icmp ne i32 [[V9]], 0
 ; CHECK-NEXT:    [[TMP0:%.*]] = and i32 [[I0_FR]], 10
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp eq i32 [[TMP0]], 10
-; CHECK-NEXT:    [[TMP2:%.*]] = select i1 [[TMP1]], i1 [[V10]], i1 false
+; CHECK-NEXT:    [[TMP2:%.*]] = and i1 [[TMP1]], [[V10]]
 ; CHECK-NEXT:    br i1 [[TMP2]], label [[BB0:%.*]], label [[ENTRY_SPLIT_NONCHR:%.*]], !prof [[PROF15]]
 ; CHECK:       bb0:
 ; CHECK-NEXT:    [[V8:%.*]] = add i32 [[SUM0:%.*]], 43
 ; CHECK-NEXT:    [[V13:%.*]] = add i32 [[SUM0]], 131
 ; CHECK-NEXT:    br label [[BB3:%.*]]
 ; CHECK:       entry.split.nonchr:
 ; CHECK-NEXT:    [[V1:%.*]] = and i32 [[I0_FR]], 255
 ; CHECK-NEXT:    [[V2_NOT:%.*]] = icmp eq i32 [[V1]], 0
 ; CHECK-NEXT:    br i1 [[V2_NOT]], label [[BB3]], label [[BB0_NONCHR:%.*]], !prof [[PROF16]]
 ; CHECK:       bb0.nonchr:
 ; CHECK-NEXT:    [[V3_NONCHR:%.*]] = and i32 [[I0_FR]], 2
 ; CHECK-NEXT:    [[V4_NONCHR:%.*]] = icmp eq i32 [[V3_NONCHR]], 0
 ; CHECK-NEXT:    [[V8_NONCHR:%.*]] = add i32 [[SUM0]], 43
 ; CHECK-NEXT:    [[SUM2_NONCHR:%.*]] = select i1 [[V4_NONCHR]], i32 [[SUM0]], i32 [[V8_NONCHR]], !prof [[PROF16]]
-; CHECK-NEXT:    [[V9_NONCHR:%.*]] = and i32 [[J0]], 4
+; CHECK-NEXT:    [[V9_NONCHR:%.*]] = and i32 [[J0_FR]], 4
 ; CHECK-NEXT:    [[V10_NONCHR:%.*]] = icmp eq i32 [[V9_NONCHR]], 0
 ; CHECK-NEXT:    [[V11_NONCHR:%.*]] = and i32 [[I0_FR]], 8
 ; CHECK-NEXT:    [[V12_NONCHR:%.*]] = icmp eq i32 [[V11_NONCHR]], 0
 ; CHECK-NEXT:    [[SUM4_NONCHR_V:%.*]] = select i1 [[V12_NONCHR]], i32 44, i32 88
 ; CHECK-NEXT:    [[SUM4_NONCHR:%.*]] = add i32 [[SUM2_NONCHR]], [[SUM4_NONCHR_V]]
 ; CHECK-NEXT:    [[SUM5_NONCHR:%.*]] = select i1 [[V10_NONCHR]], i32 [[SUM2_NONCHR]], i32 [[SUM4_NONCHR]], !prof [[PROF16]]
 ; CHECK-NEXT:    br label [[BB3]]
 ; CHECK:       bb3:

 ; }
 ; return sum
 define i32 @test_chr_7_1(ptr %i, ptr %j, i32 %sum0) !prof !14 {
 ; CHECK-LABEL: @test_chr_7_1(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[I0:%.*]] = load i32, ptr [[I:%.*]], align 4
 ; CHECK-NEXT:    call void @foo()
 ; CHECK-NEXT:    [[J0:%.*]] = load i32, ptr [[J:%.*]], align 4
-; CHECK-NEXT:    [[TMP0:%.*]] = and i32 [[J0]], 12
+; CHECK-NEXT:    [[J0_FR:%.*]] = freeze i32 [[J0]]
+; CHECK-NEXT:    [[TMP0:%.*]] = and i32 [[J0_FR]], 12
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp eq i32 [[TMP0]], 12
 ; CHECK-NEXT:    br i1 [[TMP1]], label [[BB0:%.*]], label [[ENTRY_SPLIT_NONCHR:%.*]], !prof [[PROF15]]
 ; CHECK:       bb0:
 ; CHECK-NEXT:    call void @foo()
 ; CHECK-NEXT:    call void @foo()
 ; CHECK-NEXT:    br label [[BB3:%.*]]
 ; CHECK:       entry.split.nonchr:
-; CHECK-NEXT:    [[V9:%.*]] = and i32 [[J0]], 4
+; CHECK-NEXT:    [[V9:%.*]] = and i32 [[J0_FR]], 4
 ; CHECK-NEXT:    [[V10_NOT:%.*]] = icmp eq i32 [[V9]], 0
 ; CHECK-NEXT:    br i1 [[V10_NOT]], label [[BB1_NONCHR:%.*]], label [[BB0_NONCHR:%.*]], !prof [[PROF16]]
 ; CHECK:       bb0.nonchr:
 ; CHECK-NEXT:    call void @foo()
 ; CHECK-NEXT:    br label [[BB1_NONCHR]]
 ; CHECK:       bb1.nonchr:
-; CHECK-NEXT:    [[V11_NONCHR:%.*]] = and i32 [[J0]], 8
+; CHECK-NEXT:    [[V11_NONCHR:%.*]] = and i32 [[J0_FR]], 8
 ; CHECK-NEXT:    [[V12_NONCHR:%.*]] = icmp eq i32 [[V11_NONCHR]], 0
 ; CHECK-NEXT:    br i1 [[V12_NONCHR]], label [[BB3]], label [[BB2_NONCHR:%.*]], !prof [[PROF16]]
 ; CHECK:       bb2.nonchr:
 ; CHECK-NEXT:    call void @foo()
 ; CHECK-NEXT:    br label [[BB3]]
 ; CHECK:       bb3:
 ; CHECK-NEXT:    [[V3:%.*]] = and i32 [[I0]], 2
 ; CHECK-NEXT:    [[V4:%.*]] = icmp eq i32 [[V3]], 0

 ;   }
 ; }
 ; // There's a phi for t here.
 ; return t
 define i32 @test_chr_9(ptr %i, ptr %j) !prof !14 {
 ; CHECK-LABEL: @test_chr_9(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP0:%.*]] = load i32, ptr [[I:%.*]], align 4
-; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[TMP0]], 3
+; CHECK-NEXT:    [[DOTFR1:%.*]] = freeze i32 [[TMP0]]
+; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[DOTFR1]], 3
 ; CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 3
 ; CHECK-NEXT:    br i1 [[TMP2]], label [[BB0:%.*]], label [[ENTRY_SPLIT_NONCHR:%.*]], !prof [[PROF15]]
 ; CHECK:       bb0:
 ; CHECK-NEXT:    call void @foo()
 ; CHECK-NEXT:    [[TMP3:%.*]] = load i32, ptr [[J:%.*]], align 4
 ; CHECK-NEXT:    call void @foo()
 ; CHECK-NEXT:    br label [[BB3:%.*]]
 ; CHECK:       entry.split.nonchr:
-; CHECK-NEXT:    [[TMP4:%.*]] = and i32 [[TMP0]], 1
+; CHECK-NEXT:    [[TMP4:%.*]] = and i32 [[DOTFR1]], 1
 ; CHECK-NEXT:    [[DOTNOT:%.*]] = icmp eq i32 [[TMP4]], 0
 ; CHECK-NEXT:    br i1 [[DOTNOT]], label [[BB1_NONCHR:%.*]], label [[BB0_NONCHR:%.*]], !prof [[PROF16]]
 ; CHECK:       bb0.nonchr:
 ; CHECK-NEXT:    call void @foo()
 ; CHECK-NEXT:    br label [[BB1_NONCHR]]
 ; CHECK:       bb1.nonchr:
-; CHECK-NEXT:    [[TMP5:%.*]] = and i32 [[TMP0]], 2
+; CHECK-NEXT:    [[TMP5:%.*]] = and i32 [[DOTFR1]], 2
 ; CHECK-NEXT:    [[TMP6:%.*]] = icmp eq i32 [[TMP5]], 0
 ; CHECK-NEXT:    br i1 [[TMP6]], label [[BB3]], label [[BB2_NONCHR:%.*]], !prof [[PROF16]]
 ; CHECK:       bb2.nonchr:
 ; CHECK-NEXT:    [[TMP7:%.*]] = load i32, ptr [[J]], align 4
 ; CHECK-NEXT:    call void @foo()
 ; CHECK-NEXT:    br label [[BB3]]
 ; CHECK:       bb3:
-; CHECK-NEXT:    [[TMP8:%.*]] = phi i32 [ [[TMP3]], [[BB0]] ], [ [[TMP0]], [[BB1_NONCHR]] ], [ [[TMP7]], [[BB2_NONCHR]] ]
+; CHECK-NEXT:    [[TMP8:%.*]] = phi i32 [ [[TMP3]], [[BB0]] ], [ [[DOTFR1]], [[BB1_NONCHR]] ], [ [[TMP7]], [[BB2_NONCHR]] ]
 ; CHECK-NEXT:    ret i32 [[TMP8]]
 ;
 entry:
   %0 = load i32, ptr %i
   %1 = and i32 %0, 1
   %2 = icmp eq i32 %1, 0
   br i1 %2, label %bb1, label %bb0, !prof !15
 

 ;   }
 ; }
 ; // A new phi for t1 is inserted here.
 ; return (t1 * 42) - (t1 - 99)
 define i32 @test_chr_10(ptr %i, ptr %j) !prof !14 {
 ; CHECK-LABEL: @test_chr_10(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP0:%.*]] = load i32, ptr [[I:%.*]], align 4
-; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[TMP0]], 3
+; CHECK-NEXT:    [[DOTFR1:%.*]] = freeze i32 [[TMP0]]
+; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[DOTFR1]], 3
 ; CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 3
 ; CHECK-NEXT:    br i1 [[TMP2]], label [[BB0:%.*]], label [[ENTRY_SPLIT_NONCHR:%.*]], !prof [[PROF15]]
 ; CHECK:       bb0:
 ; CHECK-NEXT:    call void @foo()
 ; CHECK-NEXT:    [[TMP3:%.*]] = load i32, ptr [[J:%.*]], align 4
 ; CHECK-NEXT:    call void @foo()
 ; CHECK-NEXT:    br label [[BB3:%.*]]
 ; CHECK:       entry.split.nonchr:
-; CHECK-NEXT:    [[TMP4:%.*]] = and i32 [[TMP0]], 1
+; CHECK-NEXT:    [[TMP4:%.*]] = and i32 [[DOTFR1]], 1
 ; CHECK-NEXT:    [[DOTNOT:%.*]] = icmp eq i32 [[TMP4]], 0
 ; CHECK-NEXT:    br i1 [[DOTNOT]], label [[BB1_NONCHR:%.*]], label [[BB0_NONCHR:%.*]], !prof [[PROF16]]
 ; CHECK:       bb0.nonchr:
 ; CHECK-NEXT:    call void @foo()
 ; CHECK-NEXT:    br label [[BB1_NONCHR]]
 ; CHECK:       bb1.nonchr:
 ; CHECK-NEXT:    [[TMP5:%.*]] = load i32, ptr [[J]], align 4
-; CHECK-NEXT:    [[TMP6:%.*]] = and i32 [[TMP0]], 2
+; CHECK-NEXT:    [[TMP6:%.*]] = and i32 [[DOTFR1]], 2
 ; CHECK-NEXT:    [[TMP7:%.*]] = icmp eq i32 [[TMP6]], 0
 ; CHECK-NEXT:    br i1 [[TMP7]], label [[BB3]], label [[BB2_NONCHR:%.*]], !prof [[PROF16]]
 ; CHECK:       bb2.nonchr:
 ; CHECK-NEXT:    call void @foo()
 ; CHECK-NEXT:    br label [[BB3]]
 ; CHECK:       bb3:
 ; CHECK-NEXT:    [[TMP8:%.*]] = phi i32 [ [[TMP3]], [[BB0]] ], [ [[TMP5]], [[BB2_NONCHR]] ], [ [[TMP5]], [[BB1_NONCHR]] ]
 ; CHECK-NEXT:    [[TMP9:%.*]] = mul i32 [[TMP8]], 42

 ;     foo()
 ;   if ((1.0 / t0) * t0 < 1) // Likely true
 ;     foo()
 ; }
 define void @test_chr_11(ptr %i, i32 %x) !prof !14 {
 ; CHECK-LABEL: @test_chr_11(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP0:%.*]] = load i32, ptr [[I:%.*]], align 4
-; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[TMP0]], 1
+; CHECK-NEXT:    [[DOTFR1:%.*]] = freeze i32 [[TMP0]]
+; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[DOTFR1]], 1
 ; CHECK-NEXT:    [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0
-; CHECK-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP0]] to double
+; CHECK-NEXT:    [[CONV:%.*]] = sitofp i32 [[DOTFR1]] to double
 ; CHECK-NEXT:    [[DIV:%.*]] = fdiv double 1.000000e+00, [[CONV]]
 ; CHECK-NEXT:    [[MUL16:%.*]] = fmul double [[DIV]], [[CONV]]
 ; CHECK-NEXT:    [[CONV717:%.*]] = fptosi double [[MUL16]] to i32
-; CHECK-NEXT:    [[CMP18:%.*]] = icmp sgt i32 [[CONV717]], 0
-; CHECK-NEXT:    [[TMP3:%.*]] = select i1 [[TMP2]], i1 [[CMP18]], i1 false
+; CHECK-NEXT:    [[CONV717_FR:%.*]] = freeze i32 [[CONV717]]
+; CHECK-NEXT:    [[CMP18:%.*]] = icmp sgt i32 [[CONV717_FR]], 0
+; CHECK-NEXT:    [[TMP3:%.*]] = and i1 [[TMP2]], [[CMP18]]
 ; CHECK-NEXT:    br i1 [[TMP3]], label [[BB0:%.*]], label [[ENTRY_SPLIT_NONCHR:%.*]], !prof [[PROF15]]
 ; CHECK:       bb0:
 ; CHECK-NEXT:    call void @foo()
 ; CHECK-NEXT:    call void @foo()
 ; CHECK-NEXT:    br label [[BB3:%.*]]
 ; CHECK:       entry.split.nonchr:
 ; CHECK-NEXT:    br i1 [[TMP2]], label [[BB0_NONCHR:%.*]], label [[BB1_NONCHR:%.*]], !prof [[PROF18:![0-9]+]]
 ; CHECK:       bb0.nonchr:
 ; CHECK-NEXT:    call void @foo()
 ; CHECK-NEXT:    br label [[BB1_NONCHR]]
 ; CHECK:       bb1.nonchr:
-; CHECK-NEXT:    [[CONV_NONCHR:%.*]] = sitofp i32 [[TMP0]] to double
+; CHECK-NEXT:    [[CONV_NONCHR:%.*]] = sitofp i32 [[DOTFR1]] to double
 ; CHECK-NEXT:    [[DIV_NONCHR:%.*]] = fdiv double 1.000000e+00, [[CONV_NONCHR]]
 ; CHECK-NEXT:    [[MUL16_NONCHR:%.*]] = fmul double [[DIV_NONCHR]], [[CONV_NONCHR]]
 ; CHECK-NEXT:    [[CONV717_NONCHR:%.*]] = fptosi double [[MUL16_NONCHR]] to i32
 ; CHECK-NEXT:    [[CMP18_NONCHR:%.*]] = icmp slt i32 [[CONV717_NONCHR]], 1
 ; CHECK-NEXT:    br i1 [[CMP18_NONCHR]], label [[BB3]], label [[BB2_NONCHR:%.*]], !prof [[PROF16]]
 ; CHECK:       bb2.nonchr:
 ; CHECK-NEXT:    call void @foo()
 ; CHECK-NEXT:    br label [[BB3]]
bb3:
   ret void
 }
 
 ; Selects + unrelated br only
 define i32 @test_chr_12(ptr %i, i32 %sum0) !prof !14 {
 ; CHECK-LABEL: @test_chr_12(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP0:%.*]] = load i32, ptr [[I:%.*]], align 4
-; CHECK-NEXT:    [[DOTFR1:%.*]] = freeze i32 [[TMP0]]
-; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[DOTFR1]], 255
+; CHECK-NEXT:    [[DOTFR2:%.*]] = freeze i32 [[TMP0]]
+; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[DOTFR2]], 255
 ; CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 0
 ; CHECK-NEXT:    br i1 [[TMP2]], label [[BB3:%.*]], label [[BB0:%.*]], !prof [[PROF16]]
 ; CHECK:       bb0:
-; CHECK-NEXT:    [[TMP3:%.*]] = and i32 [[DOTFR1]], 1
+; CHECK-NEXT:    [[TMP3:%.*]] = and i32 [[DOTFR2]], 1
 ; CHECK-NEXT:    [[TMP4:%.*]] = icmp eq i32 [[TMP3]], 0
 ; CHECK-NEXT:    [[TMP5:%.*]] = add i32 [[SUM0:%.*]], 42
 ; CHECK-NEXT:    [[SUM1:%.*]] = select i1 [[TMP4]], i32 [[SUM0]], i32 [[TMP5]], !prof [[PROF16]]
-; CHECK-NEXT:    [[TMP6:%.*]] = and i32 [[DOTFR1]], 2
+; CHECK-NEXT:    [[TMP6:%.*]] = and i32 [[DOTFR2]], 2
 ; CHECK-NEXT:    [[TMP7:%.*]] = icmp eq i32 [[TMP6]], 0
 ; CHECK-NEXT:    [[TMP8:%.*]] = add i32 [[SUM1]], 43
 ; CHECK-NEXT:    [[SUM2:%.*]] = select i1 [[TMP7]], i32 [[SUM1]], i32 [[TMP8]], !prof [[PROF16]]
 ; CHECK-NEXT:    [[TMP9:%.*]] = load i32, ptr [[I]], align 4
-; CHECK-NEXT:    [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
-; CHECK-NEXT:    [[TMP11:%.*]] = and i32 [[DOTFR1]], 8
+; CHECK-NEXT:    [[DOTFR:%.*]] = freeze i32 [[TMP9]]
+; CHECK-NEXT:    [[TMP10:%.*]] = icmp ne i32 [[DOTFR]], 0
+; CHECK-NEXT:    [[TMP11:%.*]] = and i32 [[DOTFR2]], 8
 ; CHECK-NEXT:    [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
 ; CHECK-NEXT:    [[TMP13:%.*]] = and i1 [[TMP10]], [[TMP12]]
 ; CHECK-NEXT:    br i1 [[TMP13]], label [[BB1:%.*]], label [[BB0_SPLIT_NONCHR:%.*]], !prof [[PROF15]]
 ; CHECK:       bb1:
 ; CHECK-NEXT:    [[TMP14:%.*]] = add i32 [[SUM2]], 88
 ; CHECK-NEXT:    br label [[BB3]]
 ; CHECK:       bb0.split.nonchr:
 ; CHECK-NEXT:    br i1 [[TMP10]], label [[BB1_NONCHR:%.*]], label [[BB3]], !prof [[PROF18]]
 ; CHECK:       bb1.nonchr:
-; CHECK-NEXT:    [[TMP15:%.*]] = and i32 [[DOTFR1]], 8
+; CHECK-NEXT:    [[TMP15:%.*]] = and i32 [[DOTFR2]], 8
 ; CHECK-NEXT:    [[TMP16:%.*]] = icmp eq i32 [[TMP15]], 0
 ; CHECK-NEXT:    [[SUM4_NONCHR_V:%.*]] = select i1 [[TMP16]], i32 44, i32 88, !prof [[PROF16]]
 ; CHECK-NEXT:    [[SUM4_NONCHR:%.*]] = add i32 [[SUM2]], [[SUM4_NONCHR_V]]
 ; CHECK-NEXT:    br label [[BB3]]
 ; CHECK:       bb3:
 ; CHECK-NEXT:    [[SUM6:%.*]] = phi i32 [ [[SUM0]], [[ENTRY:%.*]] ], [ [[TMP14]], [[BB1]] ], [ [[SUM2]], [[BB0_SPLIT_NONCHR]] ], [ [[SUM4_NONCHR]], [[BB1_NONCHR]] ]
 ; CHECK-NEXT:    ret i32 [[SUM6]]
 ;

 ;     foo()
 ; }
 ; return i0 + sum3
 define i32 @test_chr_14(ptr %i, ptr %j, i32 %sum0, i1 %pred, i32 %z) !prof !14 {
 ; CHECK-LABEL: @test_chr_14(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[Z_FR:%.*]] = freeze i32 [[Z:%.*]]
 ; CHECK-NEXT:    [[I0:%.*]] = load i32, ptr [[I:%.*]], align 4
-; CHECK-NEXT:    [[V1:%.*]] = icmp eq i32 [[Z_FR]], 1
-; CHECK-NEXT:    br i1 [[V1]], label [[BB1:%.*]], label [[ENTRY_SPLIT_NONCHR:%.*]], !prof [[PROF15]]
+; CHECK-NEXT:    [[V1_NOT:%.*]] = icmp eq i32 [[Z_FR]], 1
+; CHECK-NEXT:    br i1 [[V1_NOT]], label [[BB1:%.*]], label [[ENTRY_SPLIT_NONCHR:%.*]], !prof [[PROF15]]
 ; CHECK:       entry.split.nonchr:
+; CHECK-NEXT:    [[PRED_FR:%.*]] = freeze i1 [[PRED:%.*]]
 ; CHECK-NEXT:    [[V0:%.*]] = icmp eq i32 [[Z_FR]], 0
-; CHECK-NEXT:    [[V3_NONCHR:%.*]] = and i1 [[V0]], [[PRED:%.*]]
+; CHECK-NEXT:    [[V3_NONCHR:%.*]] = and i1 [[V0]], [[PRED_FR]]
 ; CHECK-NEXT:    br i1 [[V3_NONCHR]], label [[BB0_NONCHR:%.*]], label [[BB1]], !prof [[PROF16]]
 ; CHECK:       bb0.nonchr:
 ; CHECK-NEXT:    call void @foo()
 ; CHECK-NEXT:    br label [[BB1]]
 ; CHECK:       bb1:
 ; CHECK-NEXT:    [[J0:%.*]] = load i32, ptr [[J:%.*]], align 4
 ; CHECK-NEXT:    [[V6:%.*]] = and i32 [[I0]], 2
 ; CHECK-NEXT:    [[V4:%.*]] = icmp ne i32 [[V6]], [[J0]]

 ; t7 = phi v40, v40_nc
 ; v42 = phi v41, v41_nc
 ; v43 = v42 + t7
 ; return v43
 define i32 @test_chr_16(ptr %i) !prof !14 {
 ; CHECK-LABEL: @test_chr_16(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP0:%.*]] = load i32, ptr [[I:%.*]], align 4
-; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[TMP0]], 3
+; CHECK-NEXT:    [[DOTFR1:%.*]] = freeze i32 [[TMP0]]
+; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[DOTFR1]], 3
 ; CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 3
 ; CHECK-NEXT:    br i1 [[TMP2]], label [[BB0:%.*]], label [[ENTRY_SPLIT_NONCHR:%.*]], !prof [[PROF15]]
 ; CHECK:       bb0:
 ; CHECK-NEXT:    call void @foo()
-; CHECK-NEXT:    [[V40:%.*]] = add i32 [[TMP0]], 44
-; CHECK-NEXT:    [[V41:%.*]] = add i32 [[TMP0]], 99
+; CHECK-NEXT:    [[V40:%.*]] = add i32 [[DOTFR1]], 44
+; CHECK-NEXT:    [[V41:%.*]] = add i32 [[DOTFR1]], 99
 ; CHECK-NEXT:    call void @foo()
 ; CHECK-NEXT:    br label [[BB3:%.*]]
 ; CHECK:       entry.split.nonchr:
-; CHECK-NEXT:    [[TMP3:%.*]] = and i32 [[TMP0]], 1
+; CHECK-NEXT:    [[TMP3:%.*]] = and i32 [[DOTFR1]], 1
 ; CHECK-NEXT:    [[DOTNOT:%.*]] = icmp eq i32 [[TMP3]], 0
 ; CHECK-NEXT:    br i1 [[DOTNOT]], label [[BB1_NONCHR:%.*]], label [[BB0_NONCHR:%.*]], !prof [[PROF16]]
 ; CHECK:       bb0.nonchr:
 ; CHECK-NEXT:    call void @foo()
 ; CHECK-NEXT:    br label [[BB1_NONCHR]]
 ; CHECK:       bb1.nonchr:
-; CHECK-NEXT:    [[V40_NONCHR:%.*]] = add i32 [[TMP0]], 44
-; CHECK-NEXT:    [[TMP4:%.*]] = and i32 [[TMP0]], 2
+; CHECK-NEXT:    [[V40_NONCHR:%.*]] = add i32 [[DOTFR1]], 44
+; CHECK-NEXT:    [[TMP4:%.*]] = and i32 [[DOTFR1]], 2
 ; CHECK-NEXT:    [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0
 ; CHECK-NEXT:    br i1 [[TMP5]], label [[BB3]], label [[BB2_NONCHR:%.*]], !prof [[PROF16]]
 ; CHECK:       bb2.nonchr:
-; CHECK-NEXT:    [[V41_NONCHR:%.*]] = add i32 [[TMP0]], 99
+; CHECK-NEXT:    [[V41_NONCHR:%.*]] = add i32 [[DOTFR1]], 99
 ; CHECK-NEXT:    call void @foo()
 ; CHECK-NEXT:    br label [[BB3]]
 ; CHECK:       bb3:
 ; CHECK-NEXT:    [[TMP6:%.*]] = phi i32 [ [[V40]], [[BB0]] ], [ [[V40_NONCHR]], [[BB2_NONCHR]] ], [ [[V40_NONCHR]], [[BB1_NONCHR]] ]
 ; CHECK-NEXT:    [[V42:%.*]] = phi i32 [ [[V41]], [[BB0]] ], [ [[V41_NONCHR]], [[BB2_NONCHR]] ], [ [[V40_NONCHR]], [[BB1_NONCHR]] ]
 ; CHECK-NEXT:    [[V43:%.*]] = add i32 [[V42]], [[TMP6]]
 ; CHECK-NEXT:    ret i32 [[V43]]
 ;

 ;     foo();
 ;   if (!cmp.i)
 ;     foo();
 ;  }
 ;  return 45;
 define i32 @test_chr_21(i64 %i, i64 %k, i64 %j) !prof !14 {
 ; CHECK-LABEL: @test_chr_21(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[CMP0:%.*]] = icmp ne i64 [[J:%.*]], [[K:%.*]]
-; CHECK-NEXT:    [[CMP3:%.*]] = icmp ne i64 [[J]], [[I:%.*]]
-; CHECK-NEXT:    [[CMP_I:%.*]] = icmp ne i64 [[I]], 86
-; CHECK-NEXT:    [[TMP0:%.*]] = select i1 [[CMP0]], i1 [[CMP3]], i1 false
-; CHECK-NEXT:    [[TMP1:%.*]] = select i1 [[TMP0]], i1 [[CMP_I]], i1 false
+; CHECK-NEXT:    [[J_FR:%.*]] = freeze i64 [[J:%.*]]
+; CHECK-NEXT:    [[I_FR:%.*]] = freeze i64 [[I:%.*]]
+; CHECK-NEXT:    [[K_FR:%.*]] = freeze i64 [[K:%.*]]
+; CHECK-NEXT:    [[CMP0:%.*]] = icmp ne i64 [[J_FR]], [[K_FR]]
+; CHECK-NEXT:    [[CMP3:%.*]] = icmp ne i64 [[I_FR]], [[J_FR]]
+; CHECK-NEXT:    [[CMP_I:%.*]] = icmp ne i64 [[I_FR]], 86
+; CHECK-NEXT:    [[TMP0:%.*]] = and i1 [[CMP0]], [[CMP3]]
+; CHECK-NEXT:    [[TMP1:%.*]] = and i1 [[TMP0]], [[CMP_I]]
 ; CHECK-NEXT:    br i1 [[TMP1]], label [[BB1:%.*]], label [[ENTRY_SPLIT_NONCHR:%.*]], !prof [[PROF15]]
 ; CHECK:       bb1:
-; CHECK-NEXT:    [[CMP2:%.*]] = icmp ne i64 [[I]], 2
-; CHECK-NEXT:    switch i64 [[I]], label [[BB2:%.*]] [
+; CHECK-NEXT:    [[CMP2:%.*]] = icmp ne i64 [[I_FR]], 2
+; CHECK-NEXT:    switch i64 [[I_FR]], label [[BB2:%.*]] [
 ; CHECK-NEXT:    i64 2, label [[BB3_NONCHR2:%.*]]
 ; CHECK-NEXT:    i64 86, label [[BB2_NONCHR1:%.*]]
 ; CHECK-NEXT:    ], !prof [[PROF19:![0-9]+]]
 ; CHECK:       bb2:
 ; CHECK-NEXT:    call void @foo()
 ; CHECK-NEXT:    call void @foo()
 ; CHECK-NEXT:    br label [[BB7:%.*]]
 ; CHECK:       bb2.nonchr1:
 ; CHECK-NEXT:    call void @foo()
 ; CHECK-NEXT:    br label [[BB3_NONCHR2]]
 ; CHECK:       bb3.nonchr2:
 ; CHECK-NEXT:    br i1 [[CMP_I]], label [[BB4_NONCHR3:%.*]], label [[BB7]], !prof [[PROF18]]
 ; CHECK:       bb4.nonchr3:
 ; CHECK-NEXT:    call void @foo()
 ; CHECK-NEXT:    br label [[BB7]]
 ; CHECK:       bb7:
 ; CHECK-NEXT:    call void @foo()
 ; CHECK-NEXT:    call void @foo()
 ; CHECK-NEXT:    br label [[BB10:%.*]]
 ; CHECK:       entry.split.nonchr:
 ; CHECK-NEXT:    br i1 [[CMP0]], label [[BB1_NONCHR:%.*]], label [[BB10]], !prof [[PROF18]]
 ; CHECK:       bb1.nonchr:
-; CHECK-NEXT:    [[CMP2_NONCHR:%.*]] = icmp eq i64 [[I]], 2
+; CHECK-NEXT:    [[CMP2_NONCHR:%.*]] = icmp eq i64 [[I_FR]], 2
 ; CHECK-NEXT:    br i1 [[CMP2_NONCHR]], label [[BB3_NONCHR:%.*]], label [[BB2_NONCHR:%.*]], !prof [[PROF16]]
 ; CHECK:       bb3.nonchr:
-; CHECK-NEXT:    [[CMP_I_NONCHR:%.*]] = icmp eq i64 [[I]], 86
+; CHECK-NEXT:    [[CMP_I_NONCHR:%.*]] = icmp eq i64 [[I_FR]], 86
 ; CHECK-NEXT:    br i1 [[CMP_I_NONCHR]], label [[BB6_NONCHR:%.*]], label [[BB4_NONCHR:%.*]], !prof [[PROF16]]
 ; CHECK:       bb6.nonchr:
-; CHECK-NEXT:    [[CMP3_NONCHR:%.*]] = icmp eq i64 [[J]], [[I]]
+; CHECK-NEXT:    [[CMP3_NONCHR:%.*]] = icmp eq i64 [[J_FR]], [[I_FR]]
 ; CHECK-NEXT:    br i1 [[CMP3_NONCHR]], label [[BB8_NONCHR:%.*]], label [[BB7_NONCHR:%.*]], !prof [[PROF16]]
 ; CHECK:       bb8.nonchr:
 ; CHECK-NEXT:    br i1 [[CMP_I_NONCHR]], label [[BB10]], label [[BB9_NONCHR:%.*]], !prof [[PROF16]]
 ; CHECK:       bb9.nonchr:
 ; CHECK-NEXT:    call void @foo()
 ; CHECK-NEXT:    br label [[BB10]]
 ; CHECK:       bb7.nonchr:
 ; CHECK-NEXT:    call void @foo()

 
 ; Test a case with a really long use-def chains. This test checks that it's not
 ; really slow and doesn't appear to be hanging. This is different from
 ; test_chr_22 in that it has nested control structures (multiple scopes) and
 ; covers additional code.
 define i64 @test_chr_23(i64 %v0) !prof !14 {
 ; CHECK-LABEL: @test_chr_23(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[TMP0:%.*]] = mul i64 [[V0:%.*]], 50
+; CHECK-NEXT:    [[V0_FR:%.*]] = freeze i64 [[V0:%.*]]
+; CHECK-NEXT:    [[TMP0:%.*]] = mul i64 [[V0_FR]], 50
 ; CHECK-NEXT:    [[V10_NOT:%.*]] = icmp eq i64 [[TMP0]], -50
 ; CHECK-NEXT:    ret i64 99
 ;
 entry:
   %v1 = add i64 %v0, 3
   %v2 = add i64 %v1, %v1
   %v3 = add i64 %v2, %v1
   %v4 = add i64 %v2, %v3

 
 ; Test that chr will still optimize the first 2 regions,
 ; but will skip the last one due to basic blocks have address taken.
 @gototable2 = weak_odr dso_local local_unnamed_addr constant [2 x ptr] [ptr blockaddress(@test_chr_with_bbs_address_taken2, %bb5), ptr blockaddress(@test_chr_with_bbs_address_taken2, %bb5)]
 define void @test_chr_with_bbs_address_taken2(ptr %i) !prof !14 {
 ; CHECK-LABEL: @test_chr_with_bbs_address_taken2(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP0:%.*]] = load i32, ptr [[I:%.*]], align 4
-; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[TMP0]], 3
+; CHECK-NEXT:    [[DOTFR1:%.*]] = freeze i32 [[TMP0]]
+; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[DOTFR1]], 3
 ; CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 3
 ; CHECK-NEXT:    br i1 [[TMP2]], label [[BB0:%.*]], label [[ENTRY_SPLIT_NONCHR:%.*]], !prof [[PROF15]]
 ; CHECK:       bb0:
 ; CHECK-NEXT:    call void @foo()
 ; CHECK-NEXT:    call void @foo()
 ; CHECK-NEXT:    br label [[BB6:%.*]]
 ; CHECK:       entry.split.nonchr:
-; CHECK-NEXT:    [[TMP3:%.*]] = and i32 [[TMP0]], 1
+; CHECK-NEXT:    [[TMP3:%.*]] = and i32 [[DOTFR1]], 1
 ; CHECK-NEXT:    [[DOTNOT:%.*]] = icmp eq i32 [[TMP3]], 0
 ; CHECK-NEXT:    br i1 [[DOTNOT]], label [[BB1_NONCHR:%.*]], label [[BB0_NONCHR:%.*]], !prof [[PROF16]]
 ; CHECK:       bb0.nonchr:
 ; CHECK-NEXT:    call void @foo()
 ; CHECK-NEXT:    br label [[BB1_NONCHR]]
 ; CHECK:       bb1.nonchr:
-; CHECK-NEXT:    [[TMP4:%.*]] = and i32 [[TMP0]], 2
+; CHECK-NEXT:    [[TMP4:%.*]] = and i32 [[DOTFR1]], 2
 ; CHECK-NEXT:    [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0
 ; CHECK-NEXT:    br i1 [[TMP5]], label [[BB6]], label [[BB2_NONCHR:%.*]], !prof [[PROF16]]
 ; CHECK:       bb2.nonchr:
 ; CHECK-NEXT:    call void @foo()
 ; CHECK-NEXT:    br label [[BB6]]
 ; CHECK:       bb6:
 ; CHECK-NEXT:    ret void
 ;

llvm/test/Transforms/PGOProfile/chr_coro.ll

 
 @f.resumers = private constant [3 x ptr] [ptr @f.resume, ptr @f.destroy, ptr @f.cleanup]
 
 ; Test that chr will skip block containing llvm.coro.id.
 define ptr @test_chr_with_coro_id(ptr %i) !prof !14 {
 ; CHECK-LABEL: @test_chr_with_coro_id(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP0:%.*]] = load i32, ptr [[I:%.*]], align 4
-; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[TMP0]], 3
+; CHECK-NEXT:    [[DOTFR1:%.*]] = freeze i32 [[TMP0]]
+; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[DOTFR1]], 3
 ; CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 3
-; CHECK-NEXT:    br i1 [[TMP2]], label %[[BB0:.*]], label %[[ENTRY_SPLIT_NONCHR:.*]], !prof !15
-; CHECK:       [[BB0]]:
+; CHECK-NEXT:    br i1 [[TMP2]], label [[BB0:%.*]], label [[ENTRY_SPLIT_NONCHR:%.*]], !prof [[PROF15:![0-9]+]]
+; CHECK:       bb0:
 ; CHECK-NEXT:    call void @foo()
-; CHECK-NEXT:    br label %[[BB_CORO_ID:.*]]
+; CHECK-NEXT:    br label [[BB_CORO_ID:%.*]]
+; CHECK:       entry.split.nonchr:
+; CHECK-NEXT:    [[TMP3:%.*]] = and i32 [[DOTFR1]], 1
+; CHECK-NEXT:    [[DOTNOT:%.*]] = icmp eq i32 [[TMP3]], 0
+; CHECK-NEXT:    br i1 [[DOTNOT]], label [[BB1_NONCHR:%.*]], label [[BB0_NONCHR:%.*]], !prof [[PROF16:![0-9]+]]
+; CHECK:       bb0.nonchr:
+; CHECK-NEXT:    call void @foo()
+; CHECK-NEXT:    br label [[BB1_NONCHR]]
 ; CHECK:       bb1.nonchr:
-; CHECK-NEXT:    [[TMP4:%.*]] = and i32 [[TMP0]], 2
+; CHECK-NEXT:    [[TMP4:%.*]] = and i32 [[DOTFR1]], 2
 ; CHECK-NEXT:    [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0
-; CHECK-NEXT:    br i1 [[TMP5]], label %[[BB2_NONCHR:.*]], label %[[BB_CORO_ID]], !prof !16
-; CHECK:       [[BB2_NONCHR]]:
+; CHECK-NEXT:    br i1 [[TMP5]], label [[BB2_NONCHR:%.*]], label [[BB_CORO_ID]], !prof [[PROF16]]
+; CHECK:       bb2.nonchr:
 ; CHECK-NEXT:    call void @foo()
-; CHECK-NEXT:    br label %[[BB_CORO_ID]]
-; CHECK:       [[BB_CORO_ID]]:
-; CHECK-NEXT:    [[ID:%.*]] = call token @llvm.coro.id
+; CHECK-NEXT:    br label [[BB_CORO_ID]]
+; CHECK:       bb.coro.id:
+; CHECK-NEXT:    [[ID:%.*]] = call token @llvm.coro.id(i32 0, ptr null, ptr null, ptr nonnull @f.resumers)
 ; CHECK-NEXT:    [[NEED_DYN_ALLOC:%.*]] = call i1 @llvm.coro.alloc(token [[ID]])
-; CHECK-NEXT:    br i1 [[NEED_DYN_ALLOC]], label %[[BB_CORO_DYN_ALLOC:.*]], label %[[BB_CORO_BEGIN:.*]]
-; CHECK:       [[BB_CORO_BEGIN]]:
-; CHECK-NEXT:    [[PHI:%.*]] = phi ptr [ null, %[[BB_CORO_ID]] ], [ %alloc, %[[BB_CORO_DYN_ALLOC]] ]
+; CHECK-NEXT:    br i1 [[NEED_DYN_ALLOC]], label [[BB_CORO_DYN_ALLOC:%.*]], label [[BB_CORO_BEGIN:%.*]]
+; CHECK:       bb.coro.dyn.alloc:
+; CHECK-NEXT:    [[ALLOC:%.*]] = call ptr @malloc(i32 24)
+; CHECK-NEXT:    br label [[BB_CORO_BEGIN]]
+; CHECK:       bb.coro.begin:
+; CHECK-NEXT:    [[PHI:%.*]] = phi ptr [ null, [[BB_CORO_ID]] ], [ [[ALLOC]], [[BB_CORO_DYN_ALLOC]] ]
 ; CHECK-NEXT:    [[HDL:%.*]] = call noalias nonnull ptr @llvm.coro.begin(token [[ID]], ptr [[PHI]])
+; CHECK-NEXT:    ret ptr [[HDL]]
 ;
 entry:
   %0 = load i32, ptr %i
   %1 = and i32 %0, 1
   %2 = icmp eq i32 %1, 0
   br i1 %2, label %bb1, label %bb0, !prof !15
 
 bb0: