This is an archive of the discontinued LLVM Phabricator instance.

Differential D140892

[Local] Fold branch on undef to unreachable
Needs ReviewPublic

Authored by nikic on Jan 3 2023, 5:56 AM.
This revision needs review, but there are no reviewers specified.

Details

Reviewers
None
Summary

Branch on undef is UB, so we should fold it to unreachable.

I've cleaned up badly reduced transform tests that were affected by this, but there's still a lot of codegen tests that need to be updated:

LLVM :: CodeGen/AArch64/arm64-bitfield-extract.ll
LLVM :: CodeGen/AArch64/arm64-call-tailcalls.ll
LLVM :: CodeGen/AArch64/arm64-collect-loh.ll
LLVM :: CodeGen/AArch64/arm64-shrink-wrapping.ll
LLVM :: CodeGen/AArch64/arm64-storebytesmerge.ll
LLVM :: CodeGen/AArch64/madd-combiner.ll
LLVM :: CodeGen/AArch64/optimize-cond-branch.ll
LLVM :: CodeGen/AArch64/tail-call-unused-zext.ll
LLVM :: CodeGen/AArch64/tailcall-ssp-split-debug.ll
LLVM :: CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
LLVM :: CodeGen/AMDGPU/cgp-bitfield-extract.ll
LLVM :: CodeGen/AMDGPU/combine-add-zext-xor.ll
LLVM :: CodeGen/AMDGPU/dagcomb-shuffle-vecextend-non2.ll
LLVM :: CodeGen/AMDGPU/early-if-convert.ll
LLVM :: CodeGen/AMDGPU/extract-subvector-16bit.ll
LLVM :: CodeGen/AMDGPU/extract-subvector.ll
LLVM :: CodeGen/AMDGPU/i1-copy-implicit-def.ll
LLVM :: CodeGen/AMDGPU/i1-copy-phi.ll
LLVM :: CodeGen/AMDGPU/implicit-def-muse.ll
LLVM :: CodeGen/AMDGPU/infinite-loop.ll
LLVM :: CodeGen/AMDGPU/inline-asm.ll
LLVM :: CodeGen/AMDGPU/ipra-return-address-save-restore.ll
LLVM :: CodeGen/AMDGPU/mfma-cd-select.ll
LLVM :: CodeGen/AMDGPU/noclobber-barrier.ll
LLVM :: CodeGen/AMDGPU/si-annotate-cf-noloop.ll
LLVM :: CodeGen/AMDGPU/si-annotate-cf-unreachable.ll
LLVM :: CodeGen/AMDGPU/simplifydemandedbits-recursion.ll
LLVM :: CodeGen/AMDGPU/sink-image-sample.ll
LLVM :: CodeGen/AMDGPU/skip-if-dead.ll
LLVM :: CodeGen/AMDGPU/smrd.ll
LLVM :: CodeGen/AMDGPU/split-smrd.ll
LLVM :: CodeGen/AMDGPU/subreg-coalescer-crash.ll
LLVM :: CodeGen/AMDGPU/switch-default-block-unreachable.ll
LLVM :: CodeGen/AMDGPU/undefined-subreg-liverange.ll
LLVM :: CodeGen/AMDGPU/uniform-cfg.ll
LLVM :: CodeGen/AMDGPU/v1024.ll
LLVM :: CodeGen/AMDGPU/vgpr-liverange-ir.ll
LLVM :: CodeGen/ARM/2009-11-02-NegativeLane.ll
LLVM :: CodeGen/ARM/2011-02-07-AntidepClobber.ll
LLVM :: CodeGen/ARM/2013-07-29-vector-or-combine.ll
LLVM :: CodeGen/ARM/analyze-branch-bkpt.ll
LLVM :: CodeGen/ARM/arm-shrink-wrapping.ll
LLVM :: CodeGen/ARM/call-tc.ll
LLVM :: CodeGen/ARM/crash-greedy.ll
LLVM :: CodeGen/ARM/debug-info-qreg.ll
LLVM :: CodeGen/ARM/fcmp-xo.ll
LLVM :: CodeGen/ARM/i1.ll
LLVM :: CodeGen/ARM/ifcvt-branch-weight-bug.ll
LLVM :: CodeGen/ARM/ifcvt10.ll
LLVM :: CodeGen/ARM/machine-sink-multidef.ll
LLVM :: CodeGen/ARM/reg_sequence.ll
LLVM :: CodeGen/ARM/v8m.base-jumptable_alignment.ll
LLVM :: CodeGen/ARM/vector-DAGCombine.ll
LLVM :: CodeGen/AVR/pre-schedule.ll
LLVM :: CodeGen/Hexagon/addrmode-keepdeadphis.ll
LLVM :: CodeGen/Hexagon/always-ext.ll
LLVM :: CodeGen/Hexagon/autohvx/isel-bitcast-vsplat.ll
LLVM :: CodeGen/Hexagon/autohvx/isel-const-splat-imm.ll
LLVM :: CodeGen/Hexagon/autohvx/vector-align-only-phi-use.ll
LLVM :: CodeGen/Hexagon/avoid-predspill-calleesaved.ll
LLVM :: CodeGen/Hexagon/bit-bitsplit-regclass.ll
LLVM :: CodeGen/Hexagon/bit-visit-flowq.ll
LLVM :: CodeGen/Hexagon/branchfolder-keep-impdef.ll
LLVM :: CodeGen/Hexagon/callR_noreturn.ll
LLVM :: CodeGen/Hexagon/cfgopt-fall-through.ll
LLVM :: CodeGen/Hexagon/early-if-vecpred.ll
LLVM :: CodeGen/Hexagon/frame-offset-overflow.ll
LLVM :: CodeGen/Hexagon/hvx-bitcast-v64i1.ll
LLVM :: CodeGen/Hexagon/ignore-terminal-mbb.ll
LLVM :: CodeGen/Hexagon/isel-setcc-i1.ll
LLVM :: CodeGen/Hexagon/isel-simplify-crash.ll
LLVM :: CodeGen/Hexagon/newvalueSameReg.ll
LLVM :: CodeGen/Hexagon/newvaluejump-kill.ll
LLVM :: CodeGen/Hexagon/packetize-impdef-1.ll
LLVM :: CodeGen/Hexagon/rdf-cover-use.ll
LLVM :: CodeGen/Hexagon/rdf-extra-livein.ll
LLVM :: CodeGen/Hexagon/rdf-ignore-undef.ll
LLVM :: CodeGen/Hexagon/rdf-multiple-phis-up.ll
LLVM :: CodeGen/Hexagon/rdf-phi-shadows.ll
LLVM :: CodeGen/Hexagon/redundant-branching2.ll
LLVM :: CodeGen/Hexagon/reg-scavengebug-2.ll
LLVM :: CodeGen/Hexagon/stack-align-reset.ll
LLVM :: CodeGen/Hexagon/store-vector-pred.ll
LLVM :: CodeGen/Hexagon/swp-carried-1.ll
LLVM :: CodeGen/Hexagon/swp-dep-neg-offset.ll
LLVM :: CodeGen/Hexagon/swp-epilog-phi12.ll
LLVM :: CodeGen/Hexagon/swp-epilog-phi13.ll
LLVM :: CodeGen/Hexagon/swp-epilog-phi9.ll
LLVM :: CodeGen/Hexagon/swp-maxstart.ll
LLVM :: CodeGen/Hexagon/swp-phi-dep.ll
LLVM :: CodeGen/Hexagon/swp-phi-start.ll
LLVM :: CodeGen/Hexagon/swp-prolog-phi.ll
LLVM :: CodeGen/Hexagon/swp-tfri.ll
LLVM :: CodeGen/Hexagon/tail-dup-subreg-map.ll
LLVM :: CodeGen/Hexagon/v6-unaligned-spill.ll
LLVM :: CodeGen/Hexagon/v60-cur.ll
LLVM :: CodeGen/Hexagon/vassign-to-combine.ll
LLVM :: CodeGen/Hexagon/vect/vsplat-v8i8.ll
LLVM :: CodeGen/Hexagon/vect/zext-v4i1.ll
LLVM :: CodeGen/MIR/X86/unreachable_block.ll
LLVM :: CodeGen/MSP430/umulo-16.ll
LLVM :: CodeGen/Mips/prevent-hoisting.ll
LLVM :: CodeGen/PowerPC/aantidep-inline-asm-use.ll
LLVM :: CodeGen/PowerPC/aix-vsx-splatimm.ll
LLVM :: CodeGen/PowerPC/bdzlr.ll
LLVM :: CodeGen/PowerPC/build-vector-to-ld-chain.ll
LLVM :: CodeGen/PowerPC/ctr-cleanup.ll
LLVM :: CodeGen/PowerPC/ctrloop-large-ec.ll
LLVM :: CodeGen/PowerPC/early-ret2.ll
LLVM :: CodeGen/PowerPC/expand-foldable-isel.ll
LLVM :: CodeGen/PowerPC/extra-toc-reg-deps.ll
LLVM :: CodeGen/PowerPC/ifcvt-forked-bug-2016-08-08.ll
LLVM :: CodeGen/PowerPC/lbzux.ll
LLVM :: CodeGen/PowerPC/licm-remat.ll
LLVM :: CodeGen/PowerPC/mma-phi-accs.ll
LLVM :: CodeGen/PowerPC/negctr.ll
LLVM :: CodeGen/PowerPC/optimize-andiso.ll
LLVM :: CodeGen/PowerPC/p10-spill-crun.ll
LLVM :: CodeGen/PowerPC/post-ra-ec.ll
LLVM :: CodeGen/PowerPC/ppc-shrink-wrapping.ll
LLVM :: CodeGen/PowerPC/pr24636.ll
LLVM :: CodeGen/PowerPC/pr25157-peephole.ll
LLVM :: CodeGen/PowerPC/pr25157.ll
LLVM :: CodeGen/PowerPC/pr43527.ll
LLVM :: CodeGen/PowerPC/pr48519.ll
LLVM :: CodeGen/PowerPC/pr49509.ll
LLVM :: CodeGen/PowerPC/redundant-copy-after-tail-dup.ll
LLVM :: CodeGen/PowerPC/rlwimi-and.ll
LLVM :: CodeGen/PowerPC/sdag-ppcf128.ll
LLVM :: CodeGen/PowerPC/sink-side-effect.ll
LLVM :: CodeGen/PowerPC/sms-iterator.ll
LLVM :: CodeGen/PowerPC/spill_p9_setb.ll
LLVM :: CodeGen/PowerPC/stwu-sched.ll
LLVM :: CodeGen/PowerPC/stwux.ll
LLVM :: CodeGen/PowerPC/subreg-postra.ll
LLVM :: CodeGen/PowerPC/test-and-cmp-folding.ll
LLVM :: CodeGen/PowerPC/vsx-fma-mutate-trivial-copy.ll
LLVM :: CodeGen/PowerPC/vsx-fma-mutate-undef.ll
LLVM :: CodeGen/PowerPC/vsx-self-copy.ll
LLVM :: CodeGen/PowerPC/vsx-spill-norwstore.ll
LLVM :: CodeGen/PowerPC/xray-ret-is-terminator.ll
LLVM :: CodeGen/PowerPC/xvcmpeqdp-v2f64.ll
LLVM :: CodeGen/SPARC/missinglabel.ll
LLVM :: CodeGen/SystemZ/codegenprepare-sink-and-for-tm.ll
LLVM :: CodeGen/SystemZ/elim-frame-index-VR.ll
LLVM :: CodeGen/SystemZ/ipra.ll
LLVM :: CodeGen/SystemZ/loop-03.ll
LLVM :: CodeGen/SystemZ/signbits.ll
LLVM :: CodeGen/SystemZ/stackmap.ll
LLVM :: CodeGen/SystemZ/store-replicated-vals.ll
LLVM :: CodeGen/SystemZ/subregliveness-03.ll
LLVM :: CodeGen/SystemZ/subregliveness-05.ll
LLVM :: CodeGen/Thumb/consthoist-imm8-costs-1.ll
LLVM :: CodeGen/Thumb2/2009-08-01-WrongLDRBOpc.ll
LLVM :: CodeGen/Thumb2/2009-08-06-SpDecBug.ll
LLVM :: CodeGen/Thumb2/2010-06-21-TailMergeBug.ll
LLVM :: CodeGen/Thumb2/2010-11-22-EpilogueBug.ll
LLVM :: CodeGen/Thumb2/2011-06-07-TwoAddrEarlyClobber.ll
LLVM :: CodeGen/Thumb2/ifcvt-rescan-bug-2016-08-22.ll
LLVM :: CodeGen/Thumb2/machine-licm.ll
LLVM :: CodeGen/Thumb2/mve-phireg.ll
LLVM :: CodeGen/Thumb2/pr52817.ll
LLVM :: CodeGen/Thumb2/thumb2-ifcvt2.ll
LLVM :: CodeGen/Thumb2/v8_IT_5.ll
LLVM :: CodeGen/WebAssembly/cfg-stackify-eh.ll
LLVM :: CodeGen/WebAssembly/cfg-stackify.ll
LLVM :: CodeGen/WebAssembly/function-addr-offset.ll
LLVM :: CodeGen/WebAssembly/implicit-def.ll
LLVM :: CodeGen/X86/2011-02-21-VirtRegRewriter-KillSubReg.ll
LLVM :: CodeGen/X86/2011-04-13-SchedCmpJmp.ll
LLVM :: CodeGen/X86/2011-09-14-valcoalesce.ll
LLVM :: CodeGen/X86/2012-07-15-broadcastfold.ll
LLVM :: CodeGen/X86/AMX/amx-ldtilecfg-insert.ll
LLVM :: CodeGen/X86/AMX/amx-lower-tile-copy.ll
LLVM :: CodeGen/X86/AMX/amx-spill-merge.ll
LLVM :: CodeGen/X86/StackColoring.ll
LLVM :: CodeGen/X86/atomic-bit-test.ll
LLVM :: CodeGen/X86/avx-cmp.ll
LLVM :: CodeGen/X86/avx-load-store.ll
LLVM :: CodeGen/X86/avx-splat.ll
LLVM :: CodeGen/X86/avx2-vbroadcast.ll
LLVM :: CodeGen/X86/avx512-i1test.ll
LLVM :: CodeGen/X86/block-placement.ll
LLVM :: CodeGen/X86/callbr-asm-blockplacement.ll
LLVM :: CodeGen/X86/coalesce-esp.ll
LLVM :: CodeGen/X86/codegen-prepare-cast.ll
LLVM :: CodeGen/X86/hoist-spill.ll
LLVM :: CodeGen/X86/jump_sign.ll
LLVM :: CodeGen/X86/licm-symbol.ll
LLVM :: CodeGen/X86/machine-cse.ll
LLVM :: CodeGen/X86/machine-trace-metrics-crash.ll
LLVM :: CodeGen/X86/mbp-false-cfg-break.ll
LLVM :: CodeGen/X86/merge-vector-stores-scale-idx-crash.ll
LLVM :: CodeGen/X86/misched-new.ll
LLVM :: CodeGen/X86/postra-licm.ll
LLVM :: CodeGen/X86/pr38795.ll
LLVM :: CodeGen/X86/pr49451.ll
LLVM :: CodeGen/X86/pr50254.ll
LLVM :: CodeGen/X86/pr57673.ll
LLVM :: CodeGen/X86/ragreedy-hoist-spill.ll
LLVM :: CodeGen/X86/regalloc-spill-at-ehpad.ll
LLVM :: CodeGen/X86/shift-combine.ll
LLVM :: CodeGen/X86/shuffle-combine-crash.ll
LLVM :: CodeGen/X86/stackmap.ll
LLVM :: CodeGen/X86/statepoint-cmp-sunk-past-statepoint.ll
LLVM :: CodeGen/X86/statepoint-ra.ll
LLVM :: CodeGen/X86/swifterror.ll
LLVM :: CodeGen/X86/switch.ll
LLVM :: CodeGen/X86/tail-dup-merge-loop-headers.ll
LLVM :: CodeGen/X86/tail-merge-unreachable.ll
LLVM :: CodeGen/X86/tailcall-cgp-dup.ll
LLVM :: CodeGen/X86/taildup-crash.ll
LLVM :: CodeGen/X86/vaargs-prolog-insert.ll
LLVM :: CodeGen/X86/vector-shuffle-combining-avx512bwvl.ll
LLVM :: CodeGen/X86/x86-shrink-wrapping.ll
LLVM :: CodeGen/X86/zext-extract_subreg.ll
LLVM :: DebugInfo/X86/dbg-value-terminator.ll

Diff Detail

Unit TestsFailed

TimeTest
110 msx64 debian > LLVM.CodeGen/AArch64::arm64-bitfield-extract.ll
60 msx64 debian > LLVM.CodeGen/AArch64::arm64-call-tailcalls.ll
100 msx64 debian > LLVM.CodeGen/AArch64::arm64-collect-loh.ll
120 msx64 debian > LLVM.CodeGen/AArch64::arm64-shrink-wrapping.ll
50 msx64 debian > LLVM.CodeGen/AArch64::arm64-storebytesmerge.ll
View Full Test Results (217 Failed)

Event Timeline

nikic created this revision.Jan 3 2023, 5:56 AM
Herald added a project: Restricted Project. · View Herald TranscriptJan 3 2023, 5:56 AM
Herald added subscribers: kosarev, mstorsjo, rogfer01 and 14 others. · View Herald Transcript
nikic requested review of this revision.Jan 3 2023, 5:56 AM
Herald added a project: Restricted Project. · View Herald TranscriptJan 3 2023, 5:56 AM
Herald added subscribers: llvm-commits, vkmr, aheejin. · View Herald Transcript
Harbormaster completed remote builds in B205455: Diff 485976.Jan 3 2023, 6:57 AM
nikic mentioned this in D145008: [ControlHeightReduction] Don't combine a "poison" branch.Mar 1 2023, 2:13 PM

Revision Contents

PathSize
llvm/
lib/
Transforms/
Utils/
6 lines
test/
Transforms/
SimplifyCFG/
28 lines

Diff 485976

llvm/lib/Transforms/Utils/Local.cpp

Show First 20 Lines • Show All 175 Lines • ▼ Show 20 Lines if (auto *Cond = dyn_cast<ConstantInt>(BI->getCondition())) {
LLVMContext::MD_annotation}); LLVMContext::MD_annotation});
BI->eraseFromParent(); BI->eraseFromParent();
if (DTU) if (DTU)
DTU->applyUpdates({{DominatorTree::Delete, BB, OldDest}}); DTU->applyUpdates({{DominatorTree::Delete, BB, OldDest}});
return true; return true;
} }
if (isa<UndefValue>(BI->getCondition())) {
// Branch on undef is undefined behavior.
changeToUnreachable(BI, /*PreserveLCSSA*/ false, DTU);
return true;
}
return false; return false;
} }
if (auto *SI = dyn_cast<SwitchInst>(T)) { if (auto *SI = dyn_cast<SwitchInst>(T)) {
// If we are switching on a constant, we can convert the switch to an // If we are switching on a constant, we can convert the switch to an
// unconditional branch. // unconditional branch.
auto *CI = dyn_cast<ConstantInt>(SI->getCondition()); auto *CI = dyn_cast<ConstantInt>(SI->getCondition());
BasicBlock *DefaultDest = SI->getDefaultDest(); BasicBlock *DefaultDest = SI->getDefaultDest();
▲ Show 20 Lines • Show All 3,324 Lines • Show Last 20 Lines

llvm/test/Transforms/SimplifyCFG/branch-on-undef.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -S -passes=simplifycfg -simplifycfg-require-and-preserve-domtree < %s | FileCheck %s ; RUN: opt -S -passes=simplifycfg -simplifycfg-require-and-preserve-domtree < %s | FileCheck %s
declare void @foo(i32) declare void @foo(i32)
define void @br_undef_simple() { define void @br_undef_simple() {
; CHECK-LABEL: @br_undef_simple( ; CHECK-LABEL: @br_undef_simple(
; CHECK-NEXT: call void @foo(i32 0) ; CHECK-NEXT: call void @foo(i32 0)
; CHECK-NEXT: br i1 undef, label [[IF:%.*]], label [[ELSE:%.*]] ; CHECK-NEXT: unreachable
; CHECK: common.ret:
; CHECK-NEXT: ret void
; CHECK: if:
; CHECK-NEXT: call void @foo(i32 1)
; CHECK-NEXT: br label [[COMMON_RET:%.*]]
; CHECK: else:
; CHECK-NEXT: call void @foo(i32 2)
; CHECK-NEXT: br label [[COMMON_RET]]
; ;
call void @foo(i32 0) call void @foo(i32 0)
br i1 undef, label %if, label %else br i1 undef, label %if, label %else
if: if:
call void @foo(i32 1) call void @foo(i32 1)
ret void ret void
else: else:
call void @foo(i32 2) call void @foo(i32 2)
ret void ret void
} }
define void @br_poison_simple() { define void @br_poison_simple() {
; CHECK-LABEL: @br_poison_simple( ; CHECK-LABEL: @br_poison_simple(
; CHECK-NEXT: call void @foo(i32 0) ; CHECK-NEXT: call void @foo(i32 0)
; CHECK-NEXT: br i1 poison, label [[IF:%.*]], label [[ELSE:%.*]] ; CHECK-NEXT: unreachable
; CHECK: common.ret:
; CHECK-NEXT: ret void
; CHECK: if:
; CHECK-NEXT: call void @foo(i32 1)
; CHECK-NEXT: br label [[COMMON_RET:%.*]]
; CHECK: else:
; CHECK-NEXT: call void @foo(i32 2)
; CHECK-NEXT: br label [[COMMON_RET]]
; ;
call void @foo(i32 0) call void @foo(i32 0)
br i1 poison, label %if, label %else br i1 poison, label %if, label %else
if: if:
call void @foo(i32 1) call void @foo(i32 1)
ret void ret void
else: else:
call void @foo(i32 2) call void @foo(i32 2)
ret void ret void
} }
define void @br_poison_succs_used(i32 %v) { define void @br_poison_succs_used(i32 %v) {
; CHECK-LABEL: @br_poison_succs_used( ; CHECK-LABEL: @br_poison_succs_used(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: switch i32 [[V:%.*]], label [[BR:%.*]] [ ; CHECK-NEXT: switch i32 [[V:%.*]], label [[BR:%.*]] [
; CHECK-NEXT: i32 1, label [[IF:%.*]] ; CHECK-NEXT: i32 1, label [[IF:%.*]]
; CHECK-NEXT: i32 2, label [[ELSE:%.*]] ; CHECK-NEXT: i32 2, label [[ELSE:%.*]]
; CHECK-NEXT: ] ; CHECK-NEXT: ]
; CHECK: br: ; CHECK: br:
; CHECK-NEXT: call void @foo(i32 0) ; CHECK-NEXT: call void @foo(i32 0)
; CHECK-NEXT: br i1 poison, label [[IF]], label [[ELSE]] ; CHECK-NEXT: unreachable
; CHECK: common.ret: ; CHECK: common.ret:
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; CHECK: if: ; CHECK: if:
; CHECK-NEXT: [[PHI1:%.*]] = phi i32 [ 1, [[BR]] ], [ 2, [[ENTRY:%.*]] ] ; CHECK-NEXT: call void @foo(i32 2)
; CHECK-NEXT: call void @foo(i32 [[PHI1]])
; CHECK-NEXT: br label [[COMMON_RET:%.*]] ; CHECK-NEXT: br label [[COMMON_RET:%.*]]
; CHECK: else: ; CHECK: else:
; CHECK-NEXT: [[PHI2:%.*]] = phi i32 [ 3, [[BR]] ], [ 4, [[ENTRY]] ] ; CHECK-NEXT: call void @foo(i32 4)
; CHECK-NEXT: call void @foo(i32 [[PHI2]])
; CHECK-NEXT: br label [[COMMON_RET]] ; CHECK-NEXT: br label [[COMMON_RET]]
; ;
entry: entry:
switch i32 %v, label %br [ switch i32 %v, label %br [
i32 1, label %if i32 1, label %if
i32 2, label %else i32 2, label %else
] ]
Show All 14 Lines