Reorder stack up-adjustment and register copies

[Baltoli]

Summary

Context

This diff reorders the stack up-adjustment and return value copying phases of
machine-ir generation on Aarch64. Doing so prevents a bug observed for fastcc
calls with >8 arguments, where the up-adjustment required from making that call
is placed in the wrong place relative to spill and reloading code.

See: https://github.com/llvm/llvm-project/issues/60972 for full issue reproduction and context.

Changes

The code change is small and consists only of moving one stanza of code-generation to occur earlier than another; no change is made to the substance of that code. Doing so entails a change to several GISel tests for AArch64; I verified by hand that all of these were simple reorderings and that no changes to instruction bodies were required to get the tests to pass.

 Review

This is my first patch to LLVM of any kind and I'm sure that I will probably have missed something in the process. Some questions I have:

• Where is best to add a regression test for the issue I linked to above?
• Are there other related places I should have changed similar code, that my test didn't trigger?

If the approach or changes made in this PR are manifestly wrong, please feel free to reject them quickly! Thanks for your time spent addressing this diff.

[Baltoli]

The failing unit tests here don't look (from my naive perspective) like they relate to the changes I've made, but I'm happy to be corrected if they are.

[aemerson]

Thanks for the fix. Could you also add a test specific to the bug you're seeing as well? The test case from the GitHub issue is fine.

[Baltoli]

Add regression test from https://github.com/llvm/llvm-project/issues/60972

[Baltoli]

Add regression test to original changes

[Baltoli]

@aemerson I've pulled in the original code from my Github issue and generated a test case from it using the LLC test update script; please let me know if I should be doing anything differently. I have inspected the new test case and verified that the generated code is as expected (i.e. the stack-up adjustment follows the call, and does not get between the spill and reload).

I have also tested this on the (maximal) original example identified in our language, and the patch allows the relevant code to execute successfully. Our interpreter makes extensive use of fastcc / tail called code which further reassures me that these codegen changes are OK.

Thanks for your review!

[aemerson]

Thanks, LGTM.

[Baltoli]

Thanks very much @aemerson - I don't have commit access so someone will need to do that for me.

llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp

bool AArch64CallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
   MIB.addRegMask(Mask);
 
   if (TRI->isAnyArgRegReserved(MF))
     TRI->emitReservedArgRegCallError(MF);
 
   // Now we can add the actual call instruction to the correct basic block.
   MIRBuilder.insertInstr(MIB);
 
+  uint64_t CalleePopBytes =
+      doesCalleeRestoreStack(Info.CallConv,
+                             MF.getTarget().Options.GuaranteedTailCallOpt)
+          ? alignTo(Assigner.StackOffset, 16)
+          : 0;
+
+  CallSeqStart.addImm(Assigner.StackOffset).addImm(0);
+  MIRBuilder.buildInstr(AArch64::ADJCALLSTACKUP)
+      .addImm(Assigner.StackOffset)
+      .addImm(CalleePopBytes);
+
   // If Callee is a reg, since it is used by a target specific
   // instruction, it must have a register class matching the
   // constraint of that instruction.
   if (MIB->getOperand(CalleeOpNo).isReg())
     constrainOperandRegClass(MF, *TRI, MRI, *Subtarget.getInstrInfo(),
                              *Subtarget.getRegBankInfo(), *MIB, MIB->getDesc(),
                              MIB->getOperand(CalleeOpNo), CalleeOpNo);
 
if (!determineAndHandleAssignments(
       return false;
   }
 
   if (Info.SwiftErrorVReg) {
     MIB.addDef(AArch64::X21, RegState::Implicit);
     MIRBuilder.buildCopy(Info.SwiftErrorVReg, Register(AArch64::X21));
   }
 
-  uint64_t CalleePopBytes =
-      doesCalleeRestoreStack(Info.CallConv,
-                             MF.getTarget().Options.GuaranteedTailCallOpt)
-          ? alignTo(Assigner.StackOffset, 16)
-          : 0;
-
-  CallSeqStart.addImm(Assigner.StackOffset).addImm(0);
-  MIRBuilder.buildInstr(AArch64::ADJCALLSTACKUP)
-      .addImm(Assigner.StackOffset)
-      .addImm(CalleePopBytes);
-
   if (!Info.CanLowerReturn) {
     insertSRetLoads(MIRBuilder, Info.OrigRet.Ty, Info.OrigRet.Regs,
                     Info.DemoteRegister, Info.DemoteStackIndex);
   }
   return true;
 }
 
 bool AArch64CallLowering::isTypeIsValidForThisReturn(EVT Ty) const {
   return Ty.getSizeInBits() == 64;
 }

llvm/test/CodeGen/AArch64/GlobalISel/arm64-callingconv-ios.ll

define i32 @i8i16caller() nounwind readnone {
   ; CHECK-NEXT:   [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[C3]](s8)
   ; CHECK-NEXT:   $w3 = COPY [[SEXT]](s32)
   ; CHECK-NEXT:   [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[C4]](s16)
   ; CHECK-NEXT:   $w4 = COPY [[SEXT1]](s32)
   ; CHECK-NEXT:   $x5 = COPY [[C5]](s64)
   ; CHECK-NEXT:   $x6 = COPY [[C6]](s64)
   ; CHECK-NEXT:   $x7 = COPY [[C7]](s64)
   ; CHECK-NEXT:   BL @i8i16callee, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2, implicit $w3, implicit $w4, implicit $x5, implicit $x6, implicit $x7, implicit-def $x0
-  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(s64) = COPY $x0
   ; CHECK-NEXT:   ADJCALLSTACKUP 6, 0, implicit-def $sp, implicit $sp
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(s64) = COPY $x0
   ; CHECK-NEXT:   [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
   ; CHECK-NEXT:   $w0 = COPY [[TRUNC]](s32)
   ; CHECK-NEXT:   RET_ReallyLR implicit $w0
 entry:
   %call = tail call i64 @i8i16callee(i64 0, i64 1, i64 2, i8 signext 3, i16 signext 4, i64 5, i64 6, i64 7, i8 97, i16  98, i8  99, i8  100)
   %conv = trunc i64 %call to i32
   ret i32 %conv
 }
 

llvm/test/CodeGen/AArch64/GlobalISel/arm64-callingconv.ll

define i32 @i8i16caller() nounwind readnone {
   ; CHECK-NEXT:   [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[C3]](s8)
   ; CHECK-NEXT:   $w3 = COPY [[SEXT]](s32)
   ; CHECK-NEXT:   [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[C4]](s16)
   ; CHECK-NEXT:   $w4 = COPY [[SEXT1]](s32)
   ; CHECK-NEXT:   $x5 = COPY [[C5]](s64)
   ; CHECK-NEXT:   $x6 = COPY [[C6]](s64)
   ; CHECK-NEXT:   $x7 = COPY [[C7]](s64)
   ; CHECK-NEXT:   BL @i8i16callee, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2, implicit $w3, implicit $w4, implicit $x5, implicit $x6, implicit $x7, implicit-def $x0
-  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(s64) = COPY $x0
   ; CHECK-NEXT:   ADJCALLSTACKUP 32, 0, implicit-def $sp, implicit $sp
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(s64) = COPY $x0
   ; CHECK-NEXT:   [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
   ; CHECK-NEXT:   $w0 = COPY [[TRUNC]](s32)
   ; CHECK-NEXT:   RET_ReallyLR implicit $w0
 entry:
   %call = tail call i64 @i8i16callee(i64 0, i64 1, i64 2, i8 signext 3, i16 signext 4, i64 5, i64 6, i64 7, i8 97, i16  98, i8  99, i8  100)
   %conv = trunc i64 %call to i32
   ret i32 %conv
 }

llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-switch.ll

define void @jt_multiple_jump_tables(ptr %arg, i32 %arg1, ptr %arg2) {
   ; CHECK-NEXT:   [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[GV]], [[MUL]](s64)
   ; CHECK-NEXT:   [[C112:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
   ; CHECK-NEXT:   [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD]], [[C112]](s64)
   ; CHECK-NEXT:   [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[PTR_ADD1]](p0) :: (load (p0) from %ir.tmp59)
   ; CHECK-NEXT:   ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
   ; CHECK-NEXT:   $x0 = COPY [[COPY]](p0)
   ; CHECK-NEXT:   $x1 = COPY [[LOAD]](p0)
   ; CHECK-NEXT:   BL @wibble, csr_aarch64_aapcs_thisreturn, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1
-  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:_(p0) = COPY [[COPY]](p0)
   ; CHECK-NEXT:   ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:_(p0) = COPY [[COPY]](p0)
   ; CHECK-NEXT:   G_BR %bb.59
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.57.bb62:
   ; CHECK-NEXT:   ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
   ; CHECK-NEXT:   $x0 = COPY [[COPY]](p0)
   ; CHECK-NEXT:   $x1 = COPY [[COPY2]](p0)
   ; CHECK-NEXT:   BL @wibble, csr_aarch64_aapcs_thisreturn, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1
-  ; CHECK-NEXT:   [[COPY4:%[0-9]+]]:_(p0) = COPY [[COPY]](p0)
   ; CHECK-NEXT:   ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+  ; CHECK-NEXT:   [[COPY4:%[0-9]+]]:_(p0) = COPY [[COPY]](p0)
   ; CHECK-NEXT:   G_BR %bb.59
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.58.bb64:
   ; CHECK-NEXT:   ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
   ; CHECK-NEXT:   $w0 = COPY [[COPY1]](s32)
   ; CHECK-NEXT:   $x1 = COPY [[FRAME_INDEX]](p0)
   ; CHECK-NEXT:   BL @baz, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $w0, implicit $x1
   ; CHECK-NEXT:   ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
   ; CHECK-NEXT:   ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
   ; CHECK-NEXT:   $x0 = COPY [[COPY]](p0)
   ; CHECK-NEXT:   $x1 = COPY [[FRAME_INDEX]](p0)
   ; CHECK-NEXT:   BL @wibble, csr_aarch64_aapcs_thisreturn, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1
-  ; CHECK-NEXT:   [[COPY5:%[0-9]+]]:_(p0) = COPY [[COPY]](p0)
   ; CHECK-NEXT:   ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+  ; CHECK-NEXT:   [[COPY5:%[0-9]+]]:_(p0) = COPY [[COPY]](p0)
   ; CHECK-NEXT:   G_BR %bb.59
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.59.bb68:
   ; CHECK-NEXT:   RET_ReallyLR
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.60.bb69:
   ; CHECK-NEXT:   [[ICMP55:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY2]](p0), [[C55]]
   ; CHECK-NEXT:   G_BRCOND [[ICMP55]](s1), %bb.58
define ptr @test_range_phi_switch_cycle() {
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.4.bb3:
   ; CHECK-NEXT:   G_BR %bb.2
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.5.bb4:
   ; CHECK-NEXT:   ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
   ; CHECK-NEXT:   $w0 = COPY [[PHI]](s32)
   ; CHECK-NEXT:   BL @ham, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $w0, implicit-def $x0
-  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(p0) = COPY $x0
   ; CHECK-NEXT:   ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(p0) = COPY $x0
 bb:
   br label %bb1
 
 bb1:                                              ; preds = %bb3, %bb2, %bb1, %bb
   %tmp = phi i32 [undef, %bb ], [ 4, %bb2 ], [ 3, %bb3 ], [ 1, %bb1]
   switch i32 undef, label %bb4 [
     i32 305, label %bb1
     i32 497, label %bb3

llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-signext.ll

define i32 @caller_signext_i1() {
   ; CHECK-LABEL: name: caller_signext_i1
   ; CHECK: bb.1 (%ir-block.0):
   ; CHECK-NEXT:   [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
   ; CHECK-NEXT:   ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
   ; CHECK-NEXT:   [[SEXT:%[0-9]+]]:_(s8) = G_SEXT [[C]](s1)
   ; CHECK-NEXT:   [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[SEXT]](s8)
   ; CHECK-NEXT:   $w0 = COPY [[SEXT1]](s32)
   ; CHECK-NEXT:   BL @callee_signext_i1, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $w0, implicit-def $w0
-  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY $w0
   ; CHECK-NEXT:   ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY $w0
   ; CHECK-NEXT:   $w0 = COPY [[COPY]](s32)
   ; CHECK-NEXT:   RET_ReallyLR implicit $w0
   %r = call i32 @callee_signext_i1(i1 signext true)
   ret i32 %r
 }
 
 define signext i1 @ret_signext_i1() {
   ; CHECK-LABEL: name: ret_signext_i1
   ; CHECK: bb.1 (%ir-block.0):
   ; CHECK-NEXT:   [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
   ; CHECK-NEXT:   [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[C]](s1)
   ; CHECK-NEXT:   $w0 = COPY [[SEXT]](s32)
   ; CHECK-NEXT:   RET_ReallyLR implicit $w0
   ret i1 true
 }

llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-vectors.ll

 declare <3 x float> @bar(float)
 define void @test_return_v3f32() {
   ; CHECK-LABEL: name: test_return_v3f32
   ; CHECK: bb.1 (%ir-block.0):
   ; CHECK-NEXT:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
   ; CHECK-NEXT:   ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
   ; CHECK-NEXT:   $s0 = COPY [[DEF]](s32)
   ; CHECK-NEXT:   BL @bar, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $q0
+  ; CHECK-NEXT:   ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
   ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
   ; CHECK-NEXT:   [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY]](<2 x s64>)
   ; CHECK-NEXT:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BITCAST]](<4 x s32>)
   ; CHECK-NEXT:   [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[UV2]](s32)
-  ; CHECK-NEXT:   ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
   ; CHECK-NEXT:   RET_ReallyLR
   %call = call <3 x float> @bar(float undef)
   ret void
 }
 
 declare void @foo(<3 x i32>)
 define void @test_v3i32_arg() {
   ; CHECK-LABEL: name: test_v3i32_arg

llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-zeroext.ll

define i32 @caller_zeroext_i1() {
   ; CHECK-LABEL: name: caller_zeroext_i1
   ; CHECK: bb.1 (%ir-block.0):
   ; CHECK-NEXT:   [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
   ; CHECK-NEXT:   ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
   ; CHECK-NEXT:   [[ZEXT:%[0-9]+]]:_(s8) = G_ZEXT [[C]](s1)
   ; CHECK-NEXT:   [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[ZEXT]](s8)
   ; CHECK-NEXT:   $w0 = COPY [[ZEXT1]](s32)
   ; CHECK-NEXT:   BL @callee_zeroext_i1, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $w0, implicit-def $w0
-  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY $w0
   ; CHECK-NEXT:   ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY $w0
   ; CHECK-NEXT:   $w0 = COPY [[COPY]](s32)
   ; CHECK-NEXT:   RET_ReallyLR implicit $w0
   %r = call i32 @callee_zeroext_i1(i1 zeroext true)
   ret i32 %r
 }
 
 define zeroext i1 @ret_zeroext_i1() {
   ; CHECK-LABEL: name: ret_zeroext_i1
   ; CHECK: bb.1 (%ir-block.0):
   ; CHECK-NEXT:   [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
   ; CHECK-NEXT:   [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[C]](s1)
   ; CHECK-NEXT:   $w0 = COPY [[ZEXT]](s32)
   ; CHECK-NEXT:   RET_ReallyLR implicit $w0
   ret i1 true
 }

llvm/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call.ll

define i32 @test_too_big_stack() {
   ; DARWIN-NEXT:   $x1 = COPY [[DEF]](s64)
   ; DARWIN-NEXT:   $x2 = COPY [[DEF]](s64)
   ; DARWIN-NEXT:   $x3 = COPY [[DEF]](s64)
   ; DARWIN-NEXT:   $x4 = COPY [[DEF]](s64)
   ; DARWIN-NEXT:   $x5 = COPY [[DEF]](s64)
   ; DARWIN-NEXT:   $x6 = COPY [[DEF]](s64)
   ; DARWIN-NEXT:   $x7 = COPY [[DEF]](s64)
   ; DARWIN-NEXT:   BL @too_big_stack, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x7, implicit-def $w0
-  ; DARWIN-NEXT:   [[COPY1:%[0-9]+]]:_(s32) = COPY $w0
   ; DARWIN-NEXT:   ADJCALLSTACKUP 4, 0, implicit-def $sp, implicit $sp
+  ; DARWIN-NEXT:   [[COPY1:%[0-9]+]]:_(s32) = COPY $w0
   ; DARWIN-NEXT:   $w0 = COPY [[COPY1]](s32)
   ; DARWIN-NEXT:   RET_ReallyLR implicit $w0
   ; WINDOWS-LABEL: name: test_too_big_stack
   ; WINDOWS: bb.1.entry:
   ; WINDOWS-NEXT:   [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
   ; WINDOWS-NEXT:   [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 8
   ; WINDOWS-NEXT:   [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 9
   ; WINDOWS-NEXT:   ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
   ; WINDOWS-NEXT:   [[COPY:%[0-9]+]]:_(p0) = COPY $sp
   ; WINDOWS-NEXT:   [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
   ; WINDOWS-NEXT:   [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C2]](s64)
   ; WINDOWS-NEXT:   G_STORE [[C]](s8), [[PTR_ADD]](p0) :: (store (s8) into stack)
   ; WINDOWS-NEXT:   [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
   ; WINDOWS-NEXT:   [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C3]](s64)
   ; WINDOWS-NEXT:   G_STORE [[C1]](s16), [[PTR_ADD1]](p0) :: (store (s16) into stack + 8, align 1)
   ; WINDOWS-NEXT:   $x0 = COPY [[DEF]](s64)
   ; WINDOWS-NEXT:   $x1 = COPY [[DEF]](s64)
   ; WINDOWS-NEXT:   $x2 = COPY [[DEF]](s64)
   ; WINDOWS-NEXT:   $x3 = COPY [[DEF]](s64)
   ; WINDOWS-NEXT:   $x4 = COPY [[DEF]](s64)
   ; WINDOWS-NEXT:   $x5 = COPY [[DEF]](s64)
   ; WINDOWS-NEXT:   $x6 = COPY [[DEF]](s64)
   ; WINDOWS-NEXT:   $x7 = COPY [[DEF]](s64)
   ; WINDOWS-NEXT:   BL @too_big_stack, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x7, implicit-def $w0
-  ; WINDOWS-NEXT:   [[COPY1:%[0-9]+]]:_(s32) = COPY $w0
   ; WINDOWS-NEXT:   ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+  ; WINDOWS-NEXT:   [[COPY1:%[0-9]+]]:_(s32) = COPY $w0
   ; WINDOWS-NEXT:   $w0 = COPY [[COPY1]](s32)
   ; WINDOWS-NEXT:   RET_ReallyLR implicit $w0
 entry:
   %call = tail call i32 @too_big_stack(i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i8 8, i16 9)
   ret i32 %call
 }
 
 ; Right now, we don't want to tail call callees with nonvoid return types, since

 define hidden swiftcc i64 @swiftself_indirect_tail(ptr swiftself %arg) {
   ; DARWIN-LABEL: name: swiftself_indirect_tail
   ; DARWIN: bb.1 (%ir-block.0):
   ; DARWIN-NEXT:   liveins: $x20
   ; DARWIN-NEXT: {{  $}}
   ; DARWIN-NEXT:   [[COPY:%[0-9]+]]:_(p0) = COPY $x20
   ; DARWIN-NEXT:   ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
   ; DARWIN-NEXT:   BL @pluto, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit-def $x0
-  ; DARWIN-NEXT:   [[COPY1:%[0-9]+]]:tcgpr64(p0) = COPY $x0
   ; DARWIN-NEXT:   ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+  ; DARWIN-NEXT:   [[COPY1:%[0-9]+]]:tcgpr64(p0) = COPY $x0
   ; DARWIN-NEXT:   $x20 = COPY [[COPY]](p0)
   ; DARWIN-NEXT:   TCRETURNri [[COPY1]](p0), 0, csr_darwin_aarch64_aapcs, implicit $sp, implicit $x20
   ; WINDOWS-LABEL: name: swiftself_indirect_tail
   ; WINDOWS: bb.1 (%ir-block.0):
   ; WINDOWS-NEXT:   liveins: $x20
   ; WINDOWS-NEXT: {{  $}}
   ; WINDOWS-NEXT:   [[COPY:%[0-9]+]]:_(p0) = COPY $x20
   ; WINDOWS-NEXT:   ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
   ; WINDOWS-NEXT:   BL @pluto, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit-def $x0
-  ; WINDOWS-NEXT:   [[COPY1:%[0-9]+]]:tcgpr64(p0) = COPY $x0
   ; WINDOWS-NEXT:   ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+  ; WINDOWS-NEXT:   [[COPY1:%[0-9]+]]:tcgpr64(p0) = COPY $x0
   ; WINDOWS-NEXT:   $x20 = COPY [[COPY]](p0)
   ; WINDOWS-NEXT:   TCRETURNri [[COPY1]](p0), 0, csr_aarch64_aapcs, implicit $sp, implicit $x20
   %tmp = call ptr @pluto()
   %tmp2 = tail call swiftcc i64 %tmp(ptr swiftself %arg)
   ret i64 %tmp2
 }
 
 ; Verify that we can tail call musttail callees.

llvm/test/CodeGen/AArch64/GlobalISel/call-translator.ll

 ; This should notice that the return value from has_zext_return is zero
 ; extended.
 declare zeroext i16 @has_zext_return()
 define i32 @test_zext_return_from_callee() {
   ; CHECK-LABEL: name: test_zext_return_from_callee
   ; CHECK: bb.1 (%ir-block.0):
   ; CHECK-NEXT:   ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
   ; CHECK-NEXT:   BL @has_zext_return, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit-def $w0
+  ; CHECK-NEXT:   ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
   ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY $w0
   ; CHECK-NEXT:   [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY]], 16
   ; CHECK-NEXT:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[ASSERT_ZEXT]](s32)
-  ; CHECK-NEXT:   ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
   ; CHECK-NEXT:   [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s16)
   ; CHECK-NEXT:   $w0 = COPY [[ZEXT]](s32)
   ; CHECK-NEXT:   RET_ReallyLR implicit $w0
   %val = call i16 @has_zext_return()
   %ext = zext i16 %val to i32
   ret i32 %ext
 }
 
 ; Same as above, but with zeroext explicitly on the call. Should produce the
 ; same codegen.
 define i32 @test_zext_return_from_callee2() {
   ; CHECK-LABEL: name: test_zext_return_from_callee2
   ; CHECK: bb.1 (%ir-block.0):
   ; CHECK-NEXT:   ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
   ; CHECK-NEXT:   BL @has_zext_return, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit-def $w0
+  ; CHECK-NEXT:   ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
   ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY $w0
   ; CHECK-NEXT:   [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY]], 16
   ; CHECK-NEXT:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[ASSERT_ZEXT]](s32)
-  ; CHECK-NEXT:   ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
   ; CHECK-NEXT:   [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s16)
   ; CHECK-NEXT:   $w0 = COPY [[ZEXT]](s32)
   ; CHECK-NEXT:   RET_ReallyLR implicit $w0
   %val = call zeroext i16 @has_zext_return()
   %ext = zext i16 %val to i32
   ret i32 %ext
 }
 
 ; This should notice that the return value from has_sext_return is sign
 ; extended.
 declare signext i16 @has_sext_return()
 define i32 @test_sext_return_from_callee() {
   ; CHECK-LABEL: name: test_sext_return_from_callee
   ; CHECK: bb.1 (%ir-block.0):
   ; CHECK-NEXT:   ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
   ; CHECK-NEXT:   BL @has_sext_return, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit-def $w0
+  ; CHECK-NEXT:   ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
   ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY $w0
   ; CHECK-NEXT:   [[ASSERT_SEXT:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[COPY]], 16
   ; CHECK-NEXT:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[ASSERT_SEXT]](s32)
-  ; CHECK-NEXT:   ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
   ; CHECK-NEXT:   [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[TRUNC]](s16)
   ; CHECK-NEXT:   $w0 = COPY [[SEXT]](s32)
   ; CHECK-NEXT:   RET_ReallyLR implicit $w0
   %val = call i16 @has_sext_return()
   %ext = sext i16 %val to i32
   ret i32 %ext
 }
 
 ; Same as above, but with signext explicitly on the call. Should produce the
 ; same codegen.
 define i32 @test_sext_return_from_callee2() {
   ; CHECK-LABEL: name: test_sext_return_from_callee2
   ; CHECK: bb.1 (%ir-block.0):
   ; CHECK-NEXT:   ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
   ; CHECK-NEXT:   BL @has_sext_return, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit-def $w0
+  ; CHECK-NEXT:   ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
   ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY $w0
   ; CHECK-NEXT:   [[ASSERT_SEXT:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[COPY]], 16
   ; CHECK-NEXT:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[ASSERT_SEXT]](s32)
-  ; CHECK-NEXT:   ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
   ; CHECK-NEXT:   [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[TRUNC]](s16)
   ; CHECK-NEXT:   $w0 = COPY [[SEXT]](s32)
   ; CHECK-NEXT:   RET_ReallyLR implicit $w0
   %val = call signext i16 @has_sext_return()
   %ext = sext i16 %val to i32
   ret i32 %ext
 }

llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-exceptions.ll

define { ptr, i32 } @bar() personality ptr @__gxx_personality_v0 {
   ; CHECK-NEXT:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
   ; CHECK-NEXT:   [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF
   ; CHECK-NEXT:   [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
   ; CHECK-NEXT:   G_INVOKE_REGION_START
   ; CHECK-NEXT:   EH_LABEL <mcsymbol >
   ; CHECK-NEXT:   ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
   ; CHECK-NEXT:   $w0 = COPY [[C]](s32)
   ; CHECK-NEXT:   BL @foo, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $w0, implicit-def $w0
-  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY $w0
   ; CHECK-NEXT:   ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY $w0
   ; CHECK-NEXT:   EH_LABEL <mcsymbol >
   ; CHECK-NEXT:   G_BR %bb.3
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.2.broken (landing-pad):
   ; CHECK-NEXT:   liveins: $x0, $x1
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   EH_LABEL <mcsymbol >
   ; CHECK-NEXT:   [[DEF2:%[0-9]+]]:_(s128) = G_IMPLICIT_DEF

llvm/test/CodeGen/AArch64/GlobalISel/legalize-cos.mir

bb.0:
     liveins: $d0
     ; CHECK-LABEL: name:            test_v4f16.cos
     ; CHECK: [[V1:%[0-9]+]]:_(s16), [[V2:%[0-9]+]]:_(s16), [[V3:%[0-9]+]]:_(s16), [[V4:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES %{{[0-9]+}}(<4 x s16>)
 
     ; CHECK-DAG: [[V1_S32:%[0-9]+]]:_(s32) = G_FPEXT [[V1]](s16)
     ; CHECK-NEXT: ADJCALLSTACKDOWN
     ; CHECK-NEXT: $s0 = COPY [[V1_S32]](s32)
     ; CHECK-NEXT: BL &cosf
-    ; CHECK-NEXT: [[ELT1_S32:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK-NEXT: ADJCALLSTACKUP
+    ; CHECK-NEXT: [[ELT1_S32:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK-NEXT: [[ELT1:%[0-9]+]]:_(s16) = G_FPTRUNC [[ELT1_S32]](s32)
 
     ; CHECK-DAG: [[V2_S32:%[0-9]+]]:_(s32) = G_FPEXT [[V2]](s16)
     ; CHECK-NEXT: ADJCALLSTACKDOWN
     ; CHECK-NEXT: $s0 = COPY [[V2_S32]](s32)
     ; CHECK-NEXT: BL &cosf
-    ; CHECK-NEXT: [[ELT2_S32:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK-NEXT: ADJCALLSTACKUP
+    ; CHECK-NEXT: [[ELT2_S32:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK-NEXT: [[ELT2:%[0-9]+]]:_(s16) = G_FPTRUNC [[ELT2_S32]](s32)
 
     ; CHECK-DAG: [[V3_S32:%[0-9]+]]:_(s32) = G_FPEXT [[V3]](s16)
     ; CHECK-NEXT: ADJCALLSTACKDOWN
     ; CHECK-NEXT: $s0 = COPY [[V3_S32]](s32)
     ; CHECK-NEXT: BL &cosf
-    ; CHECK-NEXT: [[ELT3_S32:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK-NEXT: ADJCALLSTACKUP
+    ; CHECK-NEXT: [[ELT3_S32:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK-NEXT: [[ELT3:%[0-9]+]]:_(s16) = G_FPTRUNC [[ELT3_S32]](s32)
 
     ; CHECK-DAG: [[V4_S32:%[0-9]+]]:_(s32) = G_FPEXT [[V4]](s16)
     ; CHECK-NEXT: ADJCALLSTACKDOWN
     ; CHECK-NEXT: $s0 = COPY [[V4_S32]](s32)
     ; CHECK-NEXT: BL &cosf
-    ; CHECK-NEXT: [[ELT4_S32:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK-NEXT: ADJCALLSTACKUP
+    ; CHECK-NEXT: [[ELT4_S32:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK-NEXT: [[ELT4:%[0-9]+]]:_(s16) = G_FPTRUNC [[ELT4_S32]](s32)
 
     ; CHECK-DAG: %{{[0-9]+}}:_(<4 x s16>) = G_BUILD_VECTOR [[ELT1]](s16), [[ELT2]](s16), [[ELT3]](s16), [[ELT4]](s16)
 
     %0:_(<4 x s16>) = COPY $d0
     %1:_(<4 x s16>) = G_FCOS %0
     $d0 = COPY %1(<4 x s16>)
     RET_ReallyLR implicit $d0

 body:             |
   bb.0:
     liveins: $h0
     ; CHECK-LABEL: name:            test_cos_half
     ; CHECK: [[REG1:%[0-9]+]]:_(s32) = G_FPEXT %0(s16)
     ; CHECK-NEXT: ADJCALLSTACKDOWN
     ; CHECK-NEXT: $s0 = COPY [[REG1]](s32)
     ; CHECK-NEXT: BL &cosf
-    ; CHECK-NEXT: [[REG2:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK-NEXT: ADJCALLSTACKUP
+    ; CHECK-NEXT: [[REG2:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK-NEXT: [[RES:%[0-9]+]]:_(s16) = G_FPTRUNC [[REG2]](s32)
 
     %0:_(s16) = COPY $h0
     %1:_(s16) = G_FCOS %0
     $h0 = COPY %1(s16)
     RET_ReallyLR implicit $h0

llvm/test/CodeGen/AArch64/GlobalISel/legalize-exp.mir

bb.0:
     liveins: $d0
     ; CHECK-LABEL: name:            test_v4f16.exp
     ; CHECK: [[V1:%[0-9]+]]:_(s16), [[V2:%[0-9]+]]:_(s16), [[V3:%[0-9]+]]:_(s16), [[V4:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES %{{[0-9]+}}(<4 x s16>)
 
     ; CHECK-DAG: [[V1_S32:%[0-9]+]]:_(s32) = G_FPEXT [[V1]](s16)
     ; CHECK-NEXT: ADJCALLSTACKDOWN
     ; CHECK-NEXT: $s0 = COPY [[V1_S32]](s32)
     ; CHECK-NEXT: BL &expf
-    ; CHECK-NEXT: [[ELT1_S32:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK-NEXT: ADJCALLSTACKUP
+    ; CHECK-NEXT: [[ELT1_S32:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK-NEXT: [[ELT1:%[0-9]+]]:_(s16) = G_FPTRUNC [[ELT1_S32]](s32)
 
     ; CHECK-DAG: [[V2_S32:%[0-9]+]]:_(s32) = G_FPEXT [[V2]](s16)
     ; CHECK-NEXT: ADJCALLSTACKDOWN
     ; CHECK-NEXT: $s0 = COPY [[V2_S32]](s32)
     ; CHECK-NEXT: BL &expf
-    ; CHECK-NEXT: [[ELT2_S32:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK-NEXT: ADJCALLSTACKUP
+    ; CHECK-NEXT: [[ELT2_S32:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK-NEXT: [[ELT2:%[0-9]+]]:_(s16) = G_FPTRUNC [[ELT2_S32]](s32)
 
     ; CHECK-DAG: [[V3_S32:%[0-9]+]]:_(s32) = G_FPEXT [[V3]](s16)
     ; CHECK-NEXT: ADJCALLSTACKDOWN
     ; CHECK-NEXT: $s0 = COPY [[V3_S32]](s32)
     ; CHECK-NEXT: BL &expf
-    ; CHECK-NEXT: [[ELT3_S32:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK-NEXT: ADJCALLSTACKUP
+    ; CHECK-NEXT: [[ELT3_S32:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK-NEXT: [[ELT3:%[0-9]+]]:_(s16) = G_FPTRUNC [[ELT3_S32]](s32)
 
     ; CHECK-DAG: [[V4_S32:%[0-9]+]]:_(s32) = G_FPEXT [[V4]](s16)
     ; CHECK-NEXT: ADJCALLSTACKDOWN
     ; CHECK-NEXT: $s0 = COPY [[V4_S32]](s32)
     ; CHECK-NEXT: BL &expf
-    ; CHECK-NEXT: [[ELT4_S32:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK-NEXT: ADJCALLSTACKUP
+    ; CHECK-NEXT: [[ELT4_S32:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK-NEXT: [[ELT4:%[0-9]+]]:_(s16) = G_FPTRUNC [[ELT4_S32]](s32)
 
     ; CHECK-DAG: %{{[0-9]+}}:_(<4 x s16>) = G_BUILD_VECTOR [[ELT1]](s16), [[ELT2]](s16), [[ELT3]](s16), [[ELT4]](s16)
 
     %0:_(<4 x s16>) = COPY $d0
     %1:_(<4 x s16>) = G_FEXP %0
     $d0 = COPY %1(<4 x s16>)
     RET_ReallyLR implicit $d0

 body:             |
   bb.0:
     liveins: $h0
     ; CHECK-LABEL: name:            test_exp_half
     ; CHECK: [[REG1:%[0-9]+]]:_(s32) = G_FPEXT %0(s16)
     ; CHECK-NEXT: ADJCALLSTACKDOWN
     ; CHECK-NEXT: $s0 = COPY [[REG1]](s32)
     ; CHECK-NEXT: BL &expf
-    ; CHECK-NEXT: [[REG2:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK-NEXT: ADJCALLSTACKUP
+    ; CHECK-NEXT: [[REG2:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK-NEXT: [[RES:%[0-9]+]]:_(s16) = G_FPTRUNC [[REG2]](s32)
 
     %0:_(s16) = COPY $h0
     %1:_(s16) = G_FEXP %0
     $h0 = COPY %1(s16)
     RET_ReallyLR implicit $h0

llvm/test/CodeGen/AArch64/GlobalISel/legalize-fexp2.mir

bb.0:
     ; CHECK-LABEL: name: test_v4f16.exp2
     ; CHECK: liveins: $d0
     ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
     ; CHECK: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
     ; CHECK: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[UV]](s16)
     ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
     ; CHECK: $s0 = COPY [[FPEXT]](s32)
     ; CHECK: BL &exp2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0
-    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[COPY1]](s32)
     ; CHECK: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[UV1]](s16)
     ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
     ; CHECK: $s0 = COPY [[FPEXT1]](s32)
     ; CHECK: BL &exp2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0
-    ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+    ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[COPY2]](s32)
     ; CHECK: [[FPEXT2:%[0-9]+]]:_(s32) = G_FPEXT [[UV2]](s16)
     ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
     ; CHECK: $s0 = COPY [[FPEXT2]](s32)
     ; CHECK: BL &exp2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0
-    ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+    ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK: [[FPTRUNC2:%[0-9]+]]:_(s16) = G_FPTRUNC [[COPY3]](s32)
     ; CHECK: [[FPEXT3:%[0-9]+]]:_(s32) = G_FPEXT [[UV3]](s16)
     ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
     ; CHECK: $s0 = COPY [[FPEXT3]](s32)
     ; CHECK: BL &exp2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0
-    ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+    ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK: [[FPTRUNC3:%[0-9]+]]:_(s16) = G_FPTRUNC [[COPY4]](s32)
     ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[FPTRUNC]](s16), [[FPTRUNC1]](s16), [[FPTRUNC2]](s16), [[FPTRUNC3]](s16)
     ; CHECK: $d0 = COPY [[BUILD_VECTOR]](<4 x s16>)
     ; CHECK: RET_ReallyLR implicit $d0
     %0:_(<4 x s16>) = COPY $d0
     %1:_(<4 x s16>) = G_FEXP2 %0
     $d0 = COPY %1(<4 x s16>)
     RET_ReallyLR implicit $d0
bb.0:
     ; CHECK-LABEL: name: test_v8f16.exp2
     ; CHECK: liveins: $q0
     ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
     ; CHECK: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16), [[UV4:%[0-9]+]]:_(s16), [[UV5:%[0-9]+]]:_(s16), [[UV6:%[0-9]+]]:_(s16), [[UV7:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<8 x s16>)
     ; CHECK: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[UV]](s16)
     ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
     ; CHECK: $s0 = COPY [[FPEXT]](s32)
     ; CHECK: BL &exp2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0
-    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[COPY1]](s32)
     ; CHECK: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[UV1]](s16)
     ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
     ; CHECK: $s0 = COPY [[FPEXT1]](s32)
     ; CHECK: BL &exp2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0
-    ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+    ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[COPY2]](s32)
     ; CHECK: [[FPEXT2:%[0-9]+]]:_(s32) = G_FPEXT [[UV2]](s16)
     ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
     ; CHECK: $s0 = COPY [[FPEXT2]](s32)
     ; CHECK: BL &exp2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0
-    ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+    ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK: [[FPTRUNC2:%[0-9]+]]:_(s16) = G_FPTRUNC [[COPY3]](s32)
     ; CHECK: [[FPEXT3:%[0-9]+]]:_(s32) = G_FPEXT [[UV3]](s16)
     ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
     ; CHECK: $s0 = COPY [[FPEXT3]](s32)
     ; CHECK: BL &exp2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0
-    ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+    ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK: [[FPTRUNC3:%[0-9]+]]:_(s16) = G_FPTRUNC [[COPY4]](s32)
     ; CHECK: [[FPEXT4:%[0-9]+]]:_(s32) = G_FPEXT [[UV4]](s16)
     ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
     ; CHECK: $s0 = COPY [[FPEXT4]](s32)
     ; CHECK: BL &exp2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0
-    ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+    ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK: [[FPTRUNC4:%[0-9]+]]:_(s16) = G_FPTRUNC [[COPY5]](s32)
     ; CHECK: [[FPEXT5:%[0-9]+]]:_(s32) = G_FPEXT [[UV5]](s16)
     ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
     ; CHECK: $s0 = COPY [[FPEXT5]](s32)
     ; CHECK: BL &exp2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0
-    ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+    ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK: [[FPTRUNC5:%[0-9]+]]:_(s16) = G_FPTRUNC [[COPY6]](s32)
     ; CHECK: [[FPEXT6:%[0-9]+]]:_(s32) = G_FPEXT [[UV6]](s16)
     ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
     ; CHECK: $s0 = COPY [[FPEXT6]](s32)
     ; CHECK: BL &exp2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0
-    ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+    ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK: [[FPTRUNC6:%[0-9]+]]:_(s16) = G_FPTRUNC [[COPY7]](s32)
     ; CHECK: [[FPEXT7:%[0-9]+]]:_(s32) = G_FPEXT [[UV7]](s16)
     ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
     ; CHECK: $s0 = COPY [[FPEXT7]](s32)
     ; CHECK: BL &exp2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0
-    ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+    ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK: [[FPTRUNC7:%[0-9]+]]:_(s16) = G_FPTRUNC [[COPY8]](s32)
     ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR [[FPTRUNC]](s16), [[FPTRUNC1]](s16), [[FPTRUNC2]](s16), [[FPTRUNC3]](s16), [[FPTRUNC4]](s16), [[FPTRUNC5]](s16), [[FPTRUNC6]](s16), [[FPTRUNC7]](s16)
     ; CHECK: $q0 = COPY [[BUILD_VECTOR]](<8 x s16>)
     ; CHECK: RET_ReallyLR implicit $q0
     %0:_(<8 x s16>) = COPY $q0
     %1:_(<8 x s16>) = G_FEXP2 %0
     $q0 = COPY %1(<8 x s16>)
     RET_ReallyLR implicit $q0
 
 ...
 ---
 name:            test_v2f32.exp2
 alignment:       4
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $d0
     ; CHECK-LABEL: name: test_v2f32.exp2
     ; CHECK: liveins: $d0
     ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
     ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
     ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
     ; CHECK: $s0 = COPY [[UV]](s32)
     ; CHECK: BL &exp2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0
-    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
     ; CHECK: $s0 = COPY [[UV1]](s32)
     ; CHECK: BL &exp2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0
-    ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+    ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32)
     ; CHECK: $d0 = COPY [[BUILD_VECTOR]](<2 x s32>)
     ; CHECK: RET_ReallyLR implicit $d0
     %0:_(<2 x s32>) = COPY $d0
     %1:_(<2 x s32>) = G_FEXP2 %0
     $d0 = COPY %1(<2 x s32>)
     RET_ReallyLR implicit $d0
 
 ...
 ---
 name:            test_v4f32.exp2
 alignment:       4
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $q0
     ; CHECK-LABEL: name: test_v4f32.exp2
     ; CHECK: liveins: $q0
     ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
     ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<4 x s32>)
     ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
     ; CHECK: $s0 = COPY [[UV]](s32)
     ; CHECK: BL &exp2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0
-    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
     ; CHECK: $s0 = COPY [[UV1]](s32)
     ; CHECK: BL &exp2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0
-    ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+    ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
     ; CHECK: $s0 = COPY [[UV2]](s32)
     ; CHECK: BL &exp2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0
-    ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+    ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
     ; CHECK: $s0 = COPY [[UV3]](s32)
     ; CHECK: BL &exp2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0
-    ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+    ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32)
     ; CHECK: $q0 = COPY [[BUILD_VECTOR]](<4 x s32>)
     ; CHECK: RET_ReallyLR implicit $q0
     %0:_(<4 x s32>) = COPY $q0
     %1:_(<4 x s32>) = G_FEXP2 %0
     $q0 = COPY %1(<4 x s32>)
     RET_ReallyLR implicit $q0
 
 ...
 ---
 name:            test_v2f64.exp2
 alignment:       4
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $q0
     ; CHECK-LABEL: name: test_v2f64.exp2
     ; CHECK: liveins: $q0
     ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
     ; CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
     ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
     ; CHECK: $d0 = COPY [[UV]](s64)
     ; CHECK: BL &exp2, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $d0, implicit-def $d0
-    ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $d0
     ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $d0
     ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
     ; CHECK: $d0 = COPY [[UV1]](s64)
     ; CHECK: BL &exp2, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $d0, implicit-def $d0
-    ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $d0
     ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+    ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $d0
     ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[COPY1]](s64), [[COPY2]](s64)
     ; CHECK: $q0 = COPY [[BUILD_VECTOR]](<2 x s64>)
     ; CHECK: RET_ReallyLR implicit $q0
     %0:_(<2 x s64>) = COPY $q0
     %1:_(<2 x s64>) = G_FEXP2 %0
     $q0 = COPY %1(<2 x s64>)
     RET_ReallyLR implicit $q0
 
 ...
 ---
 name:            test_exp2_half
 alignment:       4
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $h0
     ; CHECK-LABEL: name: test_exp2_half
     ; CHECK: liveins: $h0
     ; CHECK: [[COPY:%[0-9]+]]:_(s16) = COPY $h0
     ; CHECK: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[COPY]](s16)
     ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
     ; CHECK: $s0 = COPY [[FPEXT]](s32)
     ; CHECK: BL &exp2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0
-    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[COPY1]](s32)
     ; CHECK: $h0 = COPY [[FPTRUNC]](s16)
     ; CHECK: RET_ReallyLR implicit $h0
     %0:_(s16) = COPY $h0
     %1:_(s16) = G_FEXP2 %0
     $h0 = COPY %1(s16)
     RET_ReallyLR implicit $h0

llvm/test/CodeGen/AArch64/GlobalISel/legalize-fmaxnum.mir

bb.0:
     liveins: $q0, $q1
     ; FP16-LABEL: name: s128_libcall
     ; FP16: %a:_(s128) = COPY $q0
     ; FP16: %b:_(s128) = COPY $q1
     ; FP16: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
     ; FP16: $q0 = COPY %a(s128)
     ; FP16: $q1 = COPY %b(s128)
     ; FP16: BL &fmaxl, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $q0, implicit $q1, implicit-def $q0
-    ; FP16: %maxnum:_(s128) = COPY $q0
     ; FP16: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+    ; FP16: %maxnum:_(s128) = COPY $q0
     ; FP16: $q0 = COPY %maxnum(s128)
     ; FP16: RET_ReallyLR implicit $q0
     ; NO-FP16-LABEL: name: s128_libcall
     ; NO-FP16: %a:_(s128) = COPY $q0
     ; NO-FP16: %b:_(s128) = COPY $q1
     ; NO-FP16: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
     ; NO-FP16: $q0 = COPY %a(s128)
     ; NO-FP16: $q1 = COPY %b(s128)
     ; NO-FP16: BL &fmaxl, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $q0, implicit $q1, implicit-def $q0
-    ; NO-FP16: %maxnum:_(s128) = COPY $q0
     ; NO-FP16: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+    ; NO-FP16: %maxnum:_(s128) = COPY $q0
     ; NO-FP16: $q0 = COPY %maxnum(s128)
     ; NO-FP16: RET_ReallyLR implicit $q0
     %a:_(s128) = COPY $q0
     %b:_(s128) = COPY $q1
     %maxnum:_(s128) = G_FMAXNUM %a, %b
     $q0 = COPY %maxnum(s128)
     RET_ReallyLR implicit $q0

llvm/test/CodeGen/AArch64/GlobalISel/legalize-fminnum.mir

bb.0:
     liveins: $q0, $q1
     ; FP16-LABEL: name: s128_libcall
     ; FP16: %a:_(s128) = COPY $q0
     ; FP16: %b:_(s128) = COPY $q1
     ; FP16: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
     ; FP16: $q0 = COPY %a(s128)
     ; FP16: $q1 = COPY %b(s128)
     ; FP16: BL &fminl, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $q0, implicit $q1, implicit-def $q0
-    ; FP16: %minnum:_(s128) = COPY $q0
     ; FP16: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+    ; FP16: %minnum:_(s128) = COPY $q0
     ; FP16: $q0 = COPY %minnum(s128)
     ; FP16: RET_ReallyLR implicit $q0
     ; NO-FP16-LABEL: name: s128_libcall
     ; NO-FP16: %a:_(s128) = COPY $q0
     ; NO-FP16: %b:_(s128) = COPY $q1
     ; NO-FP16: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
     ; NO-FP16: $q0 = COPY %a(s128)
     ; NO-FP16: $q1 = COPY %b(s128)
     ; NO-FP16: BL &fminl, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $q0, implicit $q1, implicit-def $q0
-    ; NO-FP16: %minnum:_(s128) = COPY $q0
     ; NO-FP16: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+    ; NO-FP16: %minnum:_(s128) = COPY $q0
     ; NO-FP16: $q0 = COPY %minnum(s128)
     ; NO-FP16: RET_ReallyLR implicit $q0
     %a:_(s128) = COPY $q0
     %b:_(s128) = COPY $q1
     %minnum:_(s128) = G_FMINNUM %a, %b
     $q0 = COPY %minnum(s128)
     RET_ReallyLR implicit $q0

llvm/test/CodeGen/AArch64/GlobalISel/legalize-log.mir

bb.0:
     liveins: $d0
     ; CHECK-LABEL: name:            test_v4f16.log
     ; CHECK: [[V1:%[0-9]+]]:_(s16), [[V2:%[0-9]+]]:_(s16), [[V3:%[0-9]+]]:_(s16), [[V4:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES %{{[0-9]+}}(<4 x s16>)
 
     ; CHECK-DAG: [[V1_S32:%[0-9]+]]:_(s32) = G_FPEXT [[V1]](s16)
     ; CHECK-NEXT: ADJCALLSTACKDOWN
     ; CHECK-NEXT: $s0 = COPY [[V1_S32]](s32)
     ; CHECK-NEXT: BL &logf
-    ; CHECK-NEXT: [[ELT1_S32:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK-NEXT: ADJCALLSTACKUP
+    ; CHECK-NEXT: [[ELT1_S32:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK-NEXT: [[ELT1:%[0-9]+]]:_(s16) = G_FPTRUNC [[ELT1_S32]](s32)
 
     ; CHECK-DAG: [[V2_S32:%[0-9]+]]:_(s32) = G_FPEXT [[V2]](s16)
     ; CHECK-NEXT: ADJCALLSTACKDOWN
     ; CHECK-NEXT: $s0 = COPY [[V2_S32]](s32)
     ; CHECK-NEXT: BL &logf
-    ; CHECK-NEXT: [[ELT2_S32:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK-NEXT: ADJCALLSTACKUP
+    ; CHECK-NEXT: [[ELT2_S32:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK-NEXT: [[ELT2:%[0-9]+]]:_(s16) = G_FPTRUNC [[ELT2_S32]](s32)
 
     ; CHECK-DAG: [[V3_S32:%[0-9]+]]:_(s32) = G_FPEXT [[V3]](s16)
     ; CHECK-NEXT: ADJCALLSTACKDOWN
     ; CHECK-NEXT: $s0 = COPY [[V3_S32]](s32)
     ; CHECK-NEXT: BL &logf
-    ; CHECK-NEXT: [[ELT3_S32:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK-NEXT: ADJCALLSTACKUP
+    ; CHECK-NEXT: [[ELT3_S32:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK-NEXT: [[ELT3:%[0-9]+]]:_(s16) = G_FPTRUNC [[ELT3_S32]](s32)
 
     ; CHECK-DAG: [[V4_S32:%[0-9]+]]:_(s32) = G_FPEXT [[V4]](s16)
     ; CHECK-NEXT: ADJCALLSTACKDOWN
     ; CHECK-NEXT: $s0 = COPY [[V4_S32]](s32)
     ; CHECK-NEXT: BL &logf
-    ; CHECK-NEXT: [[ELT4_S32:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK-NEXT: ADJCALLSTACKUP
+    ; CHECK-NEXT: [[ELT4_S32:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK-NEXT: [[ELT4:%[0-9]+]]:_(s16) = G_FPTRUNC [[ELT4_S32]](s32)
 
     ; CHECK-DAG: %{{[0-9]+}}:_(<4 x s16>) = G_BUILD_VECTOR [[ELT1]](s16), [[ELT2]](s16), [[ELT3]](s16), [[ELT4]](s16)
 
     %0:_(<4 x s16>) = COPY $d0
     %1:_(<4 x s16>) = G_FLOG %0
     $d0 = COPY %1(<4 x s16>)
     RET_ReallyLR implicit $d0

 body:             |
   bb.0:
     liveins: $h0
     ; CHECK-LABEL: name:            test_log_half
     ; CHECK: [[REG1:%[0-9]+]]:_(s32) = G_FPEXT %0(s16)
     ; CHECK-NEXT: ADJCALLSTACKDOWN
     ; CHECK-NEXT: $s0 = COPY [[REG1]](s32)
     ; CHECK-NEXT: BL &logf
-    ; CHECK-NEXT: [[REG2:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK-NEXT: ADJCALLSTACKUP
+    ; CHECK-NEXT: [[REG2:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK-NEXT: [[RES:%[0-9]+]]:_(s16) = G_FPTRUNC [[REG2]](s32)
 
     %0:_(s16) = COPY $h0
     %1:_(s16) = G_FLOG %0
     $h0 = COPY %1(s16)
     RET_ReallyLR implicit $h0

llvm/test/CodeGen/AArch64/GlobalISel/legalize-log10.mir

bb.0:
     liveins: $d0
     ; CHECK-LABEL: name:            test_v4f16.log10
     ; CHECK: [[V1:%[0-9]+]]:_(s16), [[V2:%[0-9]+]]:_(s16), [[V3:%[0-9]+]]:_(s16), [[V4:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES %{{[0-9]+}}(<4 x s16>)
 
     ; CHECK-DAG: [[V1_S32:%[0-9]+]]:_(s32) = G_FPEXT [[V1]](s16)
     ; CHECK-NEXT: ADJCALLSTACKDOWN
     ; CHECK-NEXT: $s0 = COPY [[V1_S32]](s32)
     ; CHECK-NEXT: BL &log10
-    ; CHECK-NEXT: [[ELT1_S32:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK-NEXT: ADJCALLSTACKUP
+    ; CHECK-NEXT: [[ELT1_S32:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK-NEXT: [[ELT1:%[0-9]+]]:_(s16) = G_FPTRUNC [[ELT1_S32]](s32)
 
     ; CHECK-DAG: [[V2_S32:%[0-9]+]]:_(s32) = G_FPEXT [[V2]](s16)
     ; CHECK-NEXT: ADJCALLSTACKDOWN
     ; CHECK-NEXT: $s0 = COPY [[V2_S32]](s32)
     ; CHECK-NEXT: BL &log10
-    ; CHECK-NEXT: [[ELT2_S32:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK-NEXT: ADJCALLSTACKUP
+    ; CHECK-NEXT: [[ELT2_S32:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK-NEXT: [[ELT2:%[0-9]+]]:_(s16) = G_FPTRUNC [[ELT2_S32]](s32)
 
     ; CHECK-DAG: [[V3_S32:%[0-9]+]]:_(s32) = G_FPEXT [[V3]](s16)
     ; CHECK-NEXT: ADJCALLSTACKDOWN
     ; CHECK-NEXT: $s0 = COPY [[V3_S32]](s32)
     ; CHECK-NEXT: BL &log10
-    ; CHECK-NEXT: [[ELT3_S32:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK-NEXT: ADJCALLSTACKUP
+    ; CHECK-NEXT: [[ELT3_S32:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK-NEXT: [[ELT3:%[0-9]+]]:_(s16) = G_FPTRUNC [[ELT3_S32]](s32)
 
     ; CHECK-DAG: [[V4_S32:%[0-9]+]]:_(s32) = G_FPEXT [[V4]](s16)
     ; CHECK-NEXT: ADJCALLSTACKDOWN
     ; CHECK-NEXT: $s0 = COPY [[V4_S32]](s32)
     ; CHECK-NEXT: BL &log10
-    ; CHECK-NEXT: [[ELT4_S32:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK-NEXT: ADJCALLSTACKUP
+    ; CHECK-NEXT: [[ELT4_S32:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK-NEXT: [[ELT4:%[0-9]+]]:_(s16) = G_FPTRUNC [[ELT4_S32]](s32)
 
     ; CHECK-DAG: %{{[0-9]+}}:_(<4 x s16>) = G_BUILD_VECTOR [[ELT1]](s16), [[ELT2]](s16), [[ELT3]](s16), [[ELT4]](s16)
 
     %0:_(<4 x s16>) = COPY $d0
     %1:_(<4 x s16>) = G_FLOG10 %0
     $d0 = COPY %1(<4 x s16>)
     RET_ReallyLR implicit $d0

 body:             |
   bb.0:
     liveins: $h0
     ; CHECK-LABEL: name:            test_log10_half
     ; CHECK: [[REG1:%[0-9]+]]:_(s32) = G_FPEXT %0(s16)
     ; CHECK-NEXT: ADJCALLSTACKDOWN
     ; CHECK-NEXT: $s0 = COPY [[REG1]](s32)
     ; CHECK-NEXT: BL &log10
-    ; CHECK-NEXT: [[REG2:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK-NEXT: ADJCALLSTACKUP
+    ; CHECK-NEXT: [[REG2:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK-NEXT: [[RES:%[0-9]+]]:_(s16) = G_FPTRUNC [[REG2]](s32)
 
     %0:_(s16) = COPY $h0
     %1:_(s16) = G_FLOG10 %0
     $h0 = COPY %1(s16)
     RET_ReallyLR implicit $h0

llvm/test/CodeGen/AArch64/GlobalISel/legalize-log2.mir

bb.0:
     liveins: $d0
     ; CHECK-LABEL: name:            test_v4f16.log2
     ; CHECK: [[V1:%[0-9]+]]:_(s16), [[V2:%[0-9]+]]:_(s16), [[V3:%[0-9]+]]:_(s16), [[V4:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES %{{[0-9]+}}(<4 x s16>)
 
     ; CHECK-DAG: [[V1_S32:%[0-9]+]]:_(s32) = G_FPEXT [[V1]](s16)
     ; CHECK-NEXT: ADJCALLSTACKDOWN
     ; CHECK-NEXT: $s0 = COPY [[V1_S32]](s32)
     ; CHECK-NEXT: BL &log2
-    ; CHECK-NEXT: [[ELT1_S32:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK-NEXT: ADJCALLSTACKUP
+    ; CHECK-NEXT: [[ELT1_S32:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK-NEXT: [[ELT1:%[0-9]+]]:_(s16) = G_FPTRUNC [[ELT1_S32]](s32)
 
     ; CHECK-DAG: [[V2_S32:%[0-9]+]]:_(s32) = G_FPEXT [[V2]](s16)
     ; CHECK-NEXT: ADJCALLSTACKDOWN
     ; CHECK-NEXT: $s0 = COPY [[V2_S32]](s32)
     ; CHECK-NEXT: BL &log2
-    ; CHECK-NEXT: [[ELT2_S32:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK-NEXT: ADJCALLSTACKUP
+    ; CHECK-NEXT: [[ELT2_S32:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK-NEXT: [[ELT2:%[0-9]+]]:_(s16) = G_FPTRUNC [[ELT2_S32]](s32)
 
     ; CHECK-DAG: [[V3_S32:%[0-9]+]]:_(s32) = G_FPEXT [[V3]](s16)
     ; CHECK-NEXT: ADJCALLSTACKDOWN
     ; CHECK-NEXT: $s0 = COPY [[V3_S32]](s32)
     ; CHECK-NEXT: BL &log2
-    ; CHECK-NEXT: [[ELT3_S32:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK-NEXT: ADJCALLSTACKUP
+    ; CHECK-NEXT: [[ELT3_S32:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK-NEXT: [[ELT3:%[0-9]+]]:_(s16) = G_FPTRUNC [[ELT3_S32]](s32)
 
     ; CHECK-DAG: [[V4_S32:%[0-9]+]]:_(s32) = G_FPEXT [[V4]](s16)
     ; CHECK-NEXT: ADJCALLSTACKDOWN
     ; CHECK-NEXT: $s0 = COPY [[V4_S32]](s32)
     ; CHECK-NEXT: BL &log2
-    ; CHECK-NEXT: [[ELT4_S32:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK-NEXT: ADJCALLSTACKUP
+    ; CHECK-NEXT: [[ELT4_S32:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK-NEXT: [[ELT4:%[0-9]+]]:_(s16) = G_FPTRUNC [[ELT4_S32]](s32)
 
     ; CHECK-DAG: %{{[0-9]+}}:_(<4 x s16>) = G_BUILD_VECTOR [[ELT1]](s16), [[ELT2]](s16), [[ELT3]](s16), [[ELT4]](s16)
 
     %0:_(<4 x s16>) = COPY $d0
     %1:_(<4 x s16>) = G_FLOG2 %0
     $d0 = COPY %1(<4 x s16>)
     RET_ReallyLR implicit $d0

 body:             |
   bb.0:
     liveins: $h0
     ; CHECK-LABEL: name:            test_log2_half
     ; CHECK: [[REG1:%[0-9]+]]:_(s32) = G_FPEXT %0(s16)
     ; CHECK-NEXT: ADJCALLSTACKDOWN
     ; CHECK-NEXT: $s0 = COPY [[REG1]](s32)
     ; CHECK-NEXT: BL &log2
-    ; CHECK-NEXT: [[REG2:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK-NEXT: ADJCALLSTACKUP
+    ; CHECK-NEXT: [[REG2:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK-NEXT: [[RES:%[0-9]+]]:_(s16) = G_FPTRUNC [[REG2]](s32)
 
     %0:_(s16) = COPY $h0
     %1:_(s16) = G_FLOG2 %0
     $h0 = COPY %1(s16)
     RET_ReallyLR implicit $h0

llvm/test/CodeGen/AArch64/GlobalISel/legalize-pow.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=aarch64-- -run-pass=legalizer %s -o - | FileCheck %s
 ---
 name:            test_pow
 body:             |
   bb.0.entry:
     ; CHECK-LABEL: name: test_pow
     ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $d0
     ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $d1
     ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $s2
     ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $s3
     ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
     ; CHECK: $d0 = COPY [[COPY]](s64)
     ; CHECK: $d1 = COPY [[COPY1]](s64)
     ; CHECK: BL &pow, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $d0, implicit $d1, implicit-def $d0
-    ; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY $d0
     ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+    ; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY $d0
     ; CHECK: $x0 = COPY [[COPY4]](s64)
     ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
     ; CHECK: $s0 = COPY [[COPY2]](s32)
     ; CHECK: $s1 = COPY [[COPY3]](s32)
     ; CHECK: BL &powf, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit $s1, implicit-def $s0
-    ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+    ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK: $w0 = COPY [[COPY5]](s32)
     %0:_(s64) = COPY $d0
     %1:_(s64) = COPY $d1
     %2:_(s32) = COPY $s2
     %3:_(s32) = COPY $s3
     %4:_(s64) = G_FPOW %0, %1
     $x0 = COPY %4(s64)
     %5:_(s32) = G_FPOW %2, %3
bb.0:
     ; CHECK: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
     ; CHECK: [[UV4:%[0-9]+]]:_(s16), [[UV5:%[0-9]+]]:_(s16), [[UV6:%[0-9]+]]:_(s16), [[UV7:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY1]](<4 x s16>)
     ; CHECK: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[UV]](s16)
     ; CHECK: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[UV4]](s16)
     ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
     ; CHECK: $s0 = COPY [[FPEXT]](s32)
     ; CHECK: $s1 = COPY [[FPEXT1]](s32)
     ; CHECK: BL &powf, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit $s1, implicit-def $s0
-    ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+    ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[COPY2]](s32)
     ; CHECK: [[FPEXT2:%[0-9]+]]:_(s32) = G_FPEXT [[UV1]](s16)
     ; CHECK: [[FPEXT3:%[0-9]+]]:_(s32) = G_FPEXT [[UV5]](s16)
     ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
     ; CHECK: $s0 = COPY [[FPEXT2]](s32)
     ; CHECK: $s1 = COPY [[FPEXT3]](s32)
     ; CHECK: BL &powf, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit $s1, implicit-def $s0
-    ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+    ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[COPY3]](s32)
     ; CHECK: [[FPEXT4:%[0-9]+]]:_(s32) = G_FPEXT [[UV2]](s16)
     ; CHECK: [[FPEXT5:%[0-9]+]]:_(s32) = G_FPEXT [[UV6]](s16)
     ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
     ; CHECK: $s0 = COPY [[FPEXT4]](s32)
     ; CHECK: $s1 = COPY [[FPEXT5]](s32)
     ; CHECK: BL &powf, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit $s1, implicit-def $s0
-    ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+    ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK: [[FPTRUNC2:%[0-9]+]]:_(s16) = G_FPTRUNC [[COPY4]](s32)
     ; CHECK: [[FPEXT6:%[0-9]+]]:_(s32) = G_FPEXT [[UV3]](s16)
     ; CHECK: [[FPEXT7:%[0-9]+]]:_(s32) = G_FPEXT [[UV7]](s16)
     ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
     ; CHECK: $s0 = COPY [[FPEXT6]](s32)
     ; CHECK: $s1 = COPY [[FPEXT7]](s32)
     ; CHECK: BL &powf, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit $s1, implicit-def $s0
-    ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+    ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK: [[FPTRUNC3:%[0-9]+]]:_(s16) = G_FPTRUNC [[COPY5]](s32)
     ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[FPTRUNC]](s16), [[FPTRUNC1]](s16), [[FPTRUNC2]](s16), [[FPTRUNC3]](s16)
     ; CHECK: $d0 = COPY [[BUILD_VECTOR]](<4 x s16>)
     ; CHECK: RET_ReallyLR implicit $d0
     %0:_(<4 x s16>) = COPY $d0
     %1:_(<4 x s16>) = COPY $d1
     %2:_(<4 x s16>) = G_FPOW %0, %1
     $d0 = COPY %2(<4 x s16>)
bb.0:
     ; CHECK: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16), [[UV4:%[0-9]+]]:_(s16), [[UV5:%[0-9]+]]:_(s16), [[UV6:%[0-9]+]]:_(s16), [[UV7:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<8 x s16>)
     ; CHECK: [[UV8:%[0-9]+]]:_(s16), [[UV9:%[0-9]+]]:_(s16), [[UV10:%[0-9]+]]:_(s16), [[UV11:%[0-9]+]]:_(s16), [[UV12:%[0-9]+]]:_(s16), [[UV13:%[0-9]+]]:_(s16), [[UV14:%[0-9]+]]:_(s16), [[UV15:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY1]](<8 x s16>)
     ; CHECK: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[UV]](s16)
     ; CHECK: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[UV8]](s16)
     ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
     ; CHECK: $s0 = COPY [[FPEXT]](s32)
     ; CHECK: $s1 = COPY [[FPEXT1]](s32)
     ; CHECK: BL &powf, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit $s1, implicit-def $s0
-    ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+    ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[COPY2]](s32)
     ; CHECK: [[FPEXT2:%[0-9]+]]:_(s32) = G_FPEXT [[UV1]](s16)
     ; CHECK: [[FPEXT3:%[0-9]+]]:_(s32) = G_FPEXT [[UV9]](s16)
     ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
     ; CHECK: $s0 = COPY [[FPEXT2]](s32)
     ; CHECK: $s1 = COPY [[FPEXT3]](s32)
     ; CHECK: BL &powf, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit $s1, implicit-def $s0
-    ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+    ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[COPY3]](s32)
     ; CHECK: [[FPEXT4:%[0-9]+]]:_(s32) = G_FPEXT [[UV2]](s16)
     ; CHECK: [[FPEXT5:%[0-9]+]]:_(s32) = G_FPEXT [[UV10]](s16)
     ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
     ; CHECK: $s0 = COPY [[FPEXT4]](s32)
     ; CHECK: $s1 = COPY [[FPEXT5]](s32)
     ; CHECK: BL &powf, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit $s1, implicit-def $s0
-    ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+    ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK: [[FPTRUNC2:%[0-9]+]]:_(s16) = G_FPTRUNC [[COPY4]](s32)
     ; CHECK: [[FPEXT6:%[0-9]+]]:_(s32) = G_FPEXT [[UV3]](s16)
     ; CHECK: [[FPEXT7:%[0-9]+]]:_(s32) = G_FPEXT [[UV11]](s16)
     ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
     ; CHECK: $s0 = COPY [[FPEXT6]](s32)
     ; CHECK: $s1 = COPY [[FPEXT7]](s32)
     ; CHECK: BL &powf, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit $s1, implicit-def $s0
-    ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+    ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK: [[FPTRUNC3:%[0-9]+]]:_(s16) = G_FPTRUNC [[COPY5]](s32)
     ; CHECK: [[FPEXT8:%[0-9]+]]:_(s32) = G_FPEXT [[UV4]](s16)
     ; CHECK: [[FPEXT9:%[0-9]+]]:_(s32) = G_FPEXT [[UV12]](s16)
     ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
     ; CHECK: $s0 = COPY [[FPEXT8]](s32)
     ; CHECK: $s1 = COPY [[FPEXT9]](s32)
     ; CHECK: BL &powf, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit $s1, implicit-def $s0
-    ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+    ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK: [[FPTRUNC4:%[0-9]+]]:_(s16) = G_FPTRUNC [[COPY6]](s32)
     ; CHECK: [[FPEXT10:%[0-9]+]]:_(s32) = G_FPEXT [[UV5]](s16)
     ; CHECK: [[FPEXT11:%[0-9]+]]:_(s32) = G_FPEXT [[UV13]](s16)
     ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
     ; CHECK: $s0 = COPY [[FPEXT10]](s32)
     ; CHECK: $s1 = COPY [[FPEXT11]](s32)
     ; CHECK: BL &powf, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit $s1, implicit-def $s0
-    ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+    ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK: [[FPTRUNC5:%[0-9]+]]:_(s16) = G_FPTRUNC [[COPY7]](s32)
     ; CHECK: [[FPEXT12:%[0-9]+]]:_(s32) = G_FPEXT [[UV6]](s16)
     ; CHECK: [[FPEXT13:%[0-9]+]]:_(s32) = G_FPEXT [[UV14]](s16)
     ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
     ; CHECK: $s0 = COPY [[FPEXT12]](s32)
     ; CHECK: $s1 = COPY [[FPEXT13]](s32)
     ; CHECK: BL &powf, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit $s1, implicit-def $s0
-    ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+    ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK: [[FPTRUNC6:%[0-9]+]]:_(s16) = G_FPTRUNC [[COPY8]](s32)
     ; CHECK: [[FPEXT14:%[0-9]+]]:_(s32) = G_FPEXT [[UV7]](s16)
     ; CHECK: [[FPEXT15:%[0-9]+]]:_(s32) = G_FPEXT [[UV15]](s16)
     ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
     ; CHECK: $s0 = COPY [[FPEXT14]](s32)
     ; CHECK: $s1 = COPY [[FPEXT15]](s32)
     ; CHECK: BL &powf, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit $s1, implicit-def $s0
-    ; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+    ; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK: [[FPTRUNC7:%[0-9]+]]:_(s16) = G_FPTRUNC [[COPY9]](s32)
     ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR [[FPTRUNC]](s16), [[FPTRUNC1]](s16), [[FPTRUNC2]](s16), [[FPTRUNC3]](s16), [[FPTRUNC4]](s16), [[FPTRUNC5]](s16), [[FPTRUNC6]](s16), [[FPTRUNC7]](s16)
     ; CHECK: $q0 = COPY [[BUILD_VECTOR]](<8 x s16>)
     ; CHECK: RET_ReallyLR implicit $q0
     %0:_(<8 x s16>) = COPY $q0
     %1:_(<8 x s16>) = COPY $q1
     %2:_(<8 x s16>) = G_FPOW %0, %1
     $q0 = COPY %2(<8 x s16>)
bb.0:
     ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
     ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
     ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
     ; CHECK: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
     ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
     ; CHECK: $s0 = COPY [[UV]](s32)
     ; CHECK: $s1 = COPY [[UV2]](s32)
     ; CHECK: BL &powf, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit $s1, implicit-def $s0
-    ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+    ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
     ; CHECK: $s0 = COPY [[UV1]](s32)
     ; CHECK: $s1 = COPY [[UV3]](s32)
     ; CHECK: BL &powf, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit $s1, implicit-def $s0
-    ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+    ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY3]](s32)
     ; CHECK: $d0 = COPY [[BUILD_VECTOR]](<2 x s32>)
     ; CHECK: RET_ReallyLR implicit $d0
     %0:_(<2 x s32>) = COPY $d0
     %1:_(<2 x s32>) = COPY $d1
     %2:_(<2 x s32>) = G_FPOW %0, %1
     $d0 = COPY %2(<2 x s32>)
     RET_ReallyLR implicit $d0
bb.0:
     ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
     ; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
     ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<4 x s32>)
     ; CHECK: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<4 x s32>)
     ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
     ; CHECK: $s0 = COPY [[UV]](s32)
     ; CHECK: $s1 = COPY [[UV4]](s32)
     ; CHECK: BL &powf, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit $s1, implicit-def $s0
-    ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+    ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
     ; CHECK: $s0 = COPY [[UV1]](s32)
     ; CHECK: $s1 = COPY [[UV5]](s32)
     ; CHECK: BL &powf, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit $s1, implicit-def $s0
-    ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+    ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
     ; CHECK: $s0 = COPY [[UV2]](s32)
     ; CHECK: $s1 = COPY [[UV6]](s32)
     ; CHECK: BL &powf, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit $s1, implicit-def $s0
-    ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+    ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
     ; CHECK: $s0 = COPY [[UV3]](s32)
     ; CHECK: $s1 = COPY [[UV7]](s32)
     ; CHECK: BL &powf, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit $s1, implicit-def $s0
-    ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+    ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32)
     ; CHECK: $q0 = COPY [[BUILD_VECTOR]](<4 x s32>)
     ; CHECK: RET_ReallyLR implicit $q0
     %0:_(<4 x s32>) = COPY $q0
     %1:_(<4 x s32>) = COPY $q1
     %2:_(<4 x s32>) = G_FPOW %0, %1
     $q0 = COPY %2(<4 x s32>)
     RET_ReallyLR implicit $q0
bb.0:
     ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
     ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
     ; CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
     ; CHECK: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY1]](<2 x s64>)
     ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
     ; CHECK: $d0 = COPY [[UV]](s64)
     ; CHECK: $d1 = COPY [[UV2]](s64)
     ; CHECK: BL &pow, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $d0, implicit $d1, implicit-def $d0
-    ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $d0
     ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+    ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $d0
     ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
     ; CHECK: $d0 = COPY [[UV1]](s64)
     ; CHECK: $d1 = COPY [[UV3]](s64)
     ; CHECK: BL &pow, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $d0, implicit $d1, implicit-def $d0
-    ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY $d0
     ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+    ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY $d0
     ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[COPY2]](s64), [[COPY3]](s64)
     ; CHECK: $q0 = COPY [[BUILD_VECTOR]](<2 x s64>)
     ; CHECK: RET_ReallyLR implicit $q0
     %0:_(<2 x s64>) = COPY $q0
     %1:_(<2 x s64>) = COPY $q1
     %2:_(<2 x s64>) = G_FPOW %0, %1
     $q0 = COPY %2(<2 x s64>)
     RET_ReallyLR implicit $q0

llvm/test/CodeGen/AArch64/GlobalISel/legalize-rem.mir

body:             |
   bb.0.entry:
     ; CHECK-LABEL: name: test_frem
     ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
     ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
     ; CHECK-NEXT: $d0 = COPY [[COPY]](s64)
     ; CHECK-NEXT: $d1 = COPY [[COPY1]](s64)
     ; CHECK-NEXT: BL &fmod, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $d0, implicit $d1, implicit-def $d0
-    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $d0
     ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $d0
     ; CHECK-NEXT: $x0 = COPY [[COPY2]](s64)
     ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
     ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
     ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
     ; CHECK-NEXT: $s0 = COPY [[TRUNC]](s32)
     ; CHECK-NEXT: $s1 = COPY [[TRUNC1]](s32)
     ; CHECK-NEXT: BL &fmodf, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit $s1, implicit-def $s0
-    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK-NEXT: $w0 = COPY [[COPY3]](s32)
     %0:_(s64) = COPY $x0
     %1:_(s64) = COPY $x1
     %2:_(s64) = G_FREM %0, %1
     $x0 = COPY %2(s64)
     %3:_(s32) = G_TRUNC %0(s64)
     %4:_(s32) = G_TRUNC %1(s64)
     %5:_(s32) = G_FREM %3, %4

llvm/test/CodeGen/AArch64/GlobalISel/legalize-s128-div.mir

bb.1 (%ir-block.0):
     ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
     ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[LOAD]](s128)
     ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[LOAD1]](s128)
     ; CHECK-NEXT: $x0 = COPY [[UV]](s64)
     ; CHECK-NEXT: $x1 = COPY [[UV1]](s64)
     ; CHECK-NEXT: $x2 = COPY [[UV2]](s64)
     ; CHECK-NEXT: $x3 = COPY [[UV3]](s64)
     ; CHECK-NEXT: BL &__udivti3, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2, implicit $x3, implicit-def $x0, implicit-def $x1
+    ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
     ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x0
     ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x1
     ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY2]](s64), [[COPY3]](s64)
-    ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
     ; CHECK-NEXT: G_STORE [[MV]](s128), [[COPY]](p0) :: (store (s128) into %ir.v1ptr)
     ; CHECK-NEXT: RET_ReallyLR
     %0:_(p0) = COPY $x0
     %1:_(p0) = COPY $x1
     %2:_(s128) = G_LOAD %0(p0) :: (load (s128) from %ir.v1ptr)
     %3:_(s128) = G_LOAD %1(p0) :: (load (s128) from %ir.v2ptr)
     %4:_(s128) = G_UDIV %2, %3
     G_STORE %4(s128), %0(p0) :: (store (s128) into %ir.v1ptr)
bb.1 (%ir-block.0):
     ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
     ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[LOAD]](s128)
     ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[LOAD1]](s128)
     ; CHECK-NEXT: $x0 = COPY [[UV]](s64)
     ; CHECK-NEXT: $x1 = COPY [[UV1]](s64)
     ; CHECK-NEXT: $x2 = COPY [[UV2]](s64)
     ; CHECK-NEXT: $x3 = COPY [[UV3]](s64)
     ; CHECK-NEXT: BL &__divti3, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2, implicit $x3, implicit-def $x0, implicit-def $x1
+    ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
     ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x0
     ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x1
     ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY2]](s64), [[COPY3]](s64)
-    ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
     ; CHECK-NEXT: G_STORE [[MV]](s128), [[COPY]](p0) :: (store (s128) into %ir.v1ptr)
     ; CHECK-NEXT: RET_ReallyLR
     %0:_(p0) = COPY $x0
     %1:_(p0) = COPY $x1
     %2:_(s128) = G_LOAD %0(p0) :: (load (s128) from %ir.v1ptr)
     %3:_(s128) = G_LOAD %1(p0) :: (load (s128) from %ir.v2ptr)
     %4:_(s128) = G_SDIV %2, %3
     G_STORE %4(s128), %0(p0) :: (store (s128) into %ir.v1ptr)
     RET_ReallyLR
 
 ...

llvm/test/CodeGen/AArch64/GlobalISel/legalize-sin.mir

bb.0:
     liveins: $d0
     ; CHECK-LABEL: name:            test_v4f16.sin
     ; CHECK: [[V1:%[0-9]+]]:_(s16), [[V2:%[0-9]+]]:_(s16), [[V3:%[0-9]+]]:_(s16), [[V4:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES %{{[0-9]+}}(<4 x s16>)
 
     ; CHECK-DAG: [[V1_S32:%[0-9]+]]:_(s32) = G_FPEXT [[V1]](s16)
     ; CHECK-NEXT: ADJCALLSTACKDOWN
     ; CHECK-NEXT: $s0 = COPY [[V1_S32]](s32)
     ; CHECK-NEXT: BL &sinf
-    ; CHECK-NEXT: [[ELT1_S32:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK-NEXT: ADJCALLSTACKUP
+    ; CHECK-NEXT: [[ELT1_S32:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK-NEXT: [[ELT1:%[0-9]+]]:_(s16) = G_FPTRUNC [[ELT1_S32]](s32)
 
     ; CHECK-DAG: [[V2_S32:%[0-9]+]]:_(s32) = G_FPEXT [[V2]](s16)
     ; CHECK-NEXT: ADJCALLSTACKDOWN
     ; CHECK-NEXT: $s0 = COPY [[V2_S32]](s32)
     ; CHECK-NEXT: BL &sinf
-    ; CHECK-NEXT: [[ELT2_S32:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK-NEXT: ADJCALLSTACKUP
+    ; CHECK-NEXT: [[ELT2_S32:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK-NEXT: [[ELT2:%[0-9]+]]:_(s16) = G_FPTRUNC [[ELT2_S32]](s32)
 
     ; CHECK-DAG: [[V3_S32:%[0-9]+]]:_(s32) = G_FPEXT [[V3]](s16)
     ; CHECK-NEXT: ADJCALLSTACKDOWN
     ; CHECK-NEXT: $s0 = COPY [[V3_S32]](s32)
     ; CHECK-NEXT: BL &sinf
-    ; CHECK-NEXT: [[ELT3_S32:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK-NEXT: ADJCALLSTACKUP
+    ; CHECK-NEXT: [[ELT3_S32:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK-NEXT: [[ELT3:%[0-9]+]]:_(s16) = G_FPTRUNC [[ELT3_S32]](s32)
 
     ; CHECK-DAG: [[V4_S32:%[0-9]+]]:_(s32) = G_FPEXT [[V4]](s16)
     ; CHECK-NEXT: ADJCALLSTACKDOWN
     ; CHECK-NEXT: $s0 = COPY [[V4_S32]](s32)
     ; CHECK-NEXT: BL &sinf
-    ; CHECK-NEXT: [[ELT4_S32:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK-NEXT: ADJCALLSTACKUP
+    ; CHECK-NEXT: [[ELT4_S32:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK-NEXT: [[ELT4:%[0-9]+]]:_(s16) = G_FPTRUNC [[ELT4_S32]](s32)
 
     ; CHECK-DAG: %{{[0-9]+}}:_(<4 x s16>) = G_BUILD_VECTOR [[ELT1]](s16), [[ELT2]](s16), [[ELT3]](s16), [[ELT4]](s16)
 
     %0:_(<4 x s16>) = COPY $d0
     %1:_(<4 x s16>) = G_FSIN %0
     $d0 = COPY %1(<4 x s16>)
     RET_ReallyLR implicit $d0

 body:             |
   bb.0:
     liveins: $h0
     ; CHECK-LABEL: name:            test_sin_half
     ; CHECK: [[REG1:%[0-9]+]]:_(s32) = G_FPEXT %0(s16)
     ; CHECK-NEXT: ADJCALLSTACKDOWN
     ; CHECK-NEXT: $s0 = COPY [[REG1]](s32)
     ; CHECK-NEXT: BL &sinf
-    ; CHECK-NEXT: [[REG2:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK-NEXT: ADJCALLSTACKUP
+    ; CHECK-NEXT: [[REG2:%[0-9]+]]:_(s32) = COPY $s0
     ; CHECK-NEXT: [[RES:%[0-9]+]]:_(s16) = G_FPTRUNC [[REG2]](s32)
 
     %0:_(s16) = COPY $h0
     %1:_(s16) = G_FSIN %0
     $h0 = COPY %1(s16)
     RET_ReallyLR implicit $h0

llvm/test/CodeGen/AArch64/aarch64-fastcc-stackup.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=aarch64-none-linux -O0 -tailcallopt < %s | FileCheck %s
+
+define void @bar() {
+; CHECK-LABEL: bar:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ret
+  ret void
+}
+
+define fastcc i64 @foo(i64 %0, i64 %1, i64 %2, i64 %3, i64 %4, i64 %5, i64 %6, i64 %7, i64 %8) {
+; CHECK-LABEL: foo:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    add sp, sp, #16
+; CHECK-NEXT:    ret
+  ret i64 %0
+}
+
+; https://github.com/llvm/llvm-project/issues/60972
+define fastcc i64 @baz() {
+; CHECK-LABEL: baz:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    sub sp, sp, #32
+; CHECK-NEXT:    .cfi_def_cfa_offset 32
+; CHECK-NEXT:    str x30, [sp, #16] // 8-byte Folded Spill
+; CHECK-NEXT:    .cfi_offset w30, -16
+; CHECK-NEXT:    mov x8, sp
+; CHECK-NEXT:    mov x7, xzr
+; CHECK-NEXT:    str xzr, [x8]
+; CHECK-NEXT:    mov x0, x7
+; CHECK-NEXT:    mov x1, x7
+; CHECK-NEXT:    mov x2, x7
+; CHECK-NEXT:    mov x3, x7
+; CHECK-NEXT:    mov x4, x7
+; CHECK-NEXT:    mov x5, x7
+; CHECK-NEXT:    mov x6, x7
+; CHECK-NEXT:    bl foo
+; CHECK-NEXT:    sub sp, sp, #16
+; CHECK-NEXT:    str x0, [sp, #8] // 8-byte Folded Spill
+; CHECK-NEXT:    bl bar
+; CHECK-NEXT:    ldr x0, [sp, #8] // 8-byte Folded Reload
+; CHECK-NEXT:    ldr x30, [sp, #16] // 8-byte Folded Reload
+; CHECK-NEXT:    add sp, sp, #32
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call fastcc i64 @foo(i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0)
+  call void @bar()
+  ret i64 %0
+}

llvm/test/CodeGen/AArch64/arm64-this-return.ll

define ptr @C_ctor_base(ptr returned %this, i32 %x) {
   ; GISEL-MIR-LABEL: name: C_ctor_base
   ; GISEL-MIR: bb.1.entry:
   ; GISEL-MIR:   liveins: $w1, $x0
   ; GISEL-MIR:   [[COPY:%[0-9]+]]:_(p0) = COPY $x0
   ; GISEL-MIR:   [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
   ; GISEL-MIR:   ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
   ; GISEL-MIR:   $x0 = COPY [[COPY]](p0)
   ; GISEL-MIR:   BL @A_ctor_base, csr_aarch64_aapcs_thisreturn, implicit-def $lr, implicit $sp, implicit $x0
-  ; GISEL-MIR:   [[COPY2:%[0-9]+]]:_(p0) = COPY [[COPY]](p0)
   ; GISEL-MIR:   ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+  ; GISEL-MIR:   [[COPY2:%[0-9]+]]:_(p0) = COPY [[COPY]](p0)
   ; GISEL-MIR:   $x0 = COPY [[COPY]](p0)
   ; GISEL-MIR:   $w1 = COPY [[COPY1]](s32)
   ; GISEL-MIR:   TCRETURNdi @B_ctor_base, 0, csr_aarch64_aapcs, implicit $sp, implicit $x0, implicit $w1
 entry:
 ; CHECK-LABEL: C_ctor_base:
 ; CHECK-NOT: mov {{x[0-9]+}}, x0
 ; CHECK: bl {{_?A_ctor_base}}
 ; CHECK-NOT: mov x0, {{x[0-9]+}}
 ; CHECK: b {{_?B_ctor_base}}
   %call = tail call ptr @A_ctor_base(ptr returned %this)
   %call2 = tail call ptr @B_ctor_base(ptr returned %this, i32 %x)
   ret ptr %this
 }
 
 define ptr @C_ctor_base_nothisret(ptr %this, i32 %x) {
   ; GISEL-MIR-LABEL: name: C_ctor_base_nothisret
   ; GISEL-MIR: bb.1.entry:
   ; GISEL-MIR:   liveins: $w1, $x0
   ; GISEL-MIR:   [[COPY:%[0-9]+]]:_(p0) = COPY $x0
   ; GISEL-MIR:   [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
   ; GISEL-MIR:   ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
   ; GISEL-MIR:   $x0 = COPY [[COPY]](p0)
   ; GISEL-MIR:   BL @A_ctor_base_nothisret, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit-def $x0
-  ; GISEL-MIR:   [[COPY2:%[0-9]+]]:_(p0) = COPY $x0
   ; GISEL-MIR:   ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+  ; GISEL-MIR:   [[COPY2:%[0-9]+]]:_(p0) = COPY $x0
   ; GISEL-MIR:   ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
   ; GISEL-MIR:   $x0 = COPY [[COPY]](p0)
   ; GISEL-MIR:   $w1 = COPY [[COPY1]](s32)
   ; GISEL-MIR:   BL @B_ctor_base_nothisret, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $w1, implicit-def $x0
-  ; GISEL-MIR:   [[COPY3:%[0-9]+]]:_(p0) = COPY $x0
   ; GISEL-MIR:   ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+  ; GISEL-MIR:   [[COPY3:%[0-9]+]]:_(p0) = COPY $x0
   ; GISEL-MIR:   $x0 = COPY [[COPY]](p0)
   ; GISEL-MIR:   RET_ReallyLR implicit $x0
 entry:
 ; CHECK-LABEL: C_ctor_base_nothisret:
 ; CHECK: mov [[SAVETHIS:x[0-9]+]], x0
 ; CHECK: bl {{_?A_ctor_base_nothisret}}
 ; CHECK: mov x0, [[SAVETHIS]]
 ; CHECK-NOT: b {{_?B_ctor_base_nothisret}}
define ptr @C_ctor_complete_nothisret(ptr %this, i32 %x) {
   ; GISEL-MIR: bb.1.entry:
   ; GISEL-MIR:   liveins: $w1, $x0
   ; GISEL-MIR:   [[COPY:%[0-9]+]]:_(p0) = COPY $x0
   ; GISEL-MIR:   [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
   ; GISEL-MIR:   ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
   ; GISEL-MIR:   $x0 = COPY [[COPY]](p0)
   ; GISEL-MIR:   $w1 = COPY [[COPY1]](s32)
   ; GISEL-MIR:   BL @C_ctor_base_nothisret, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $w1, implicit-def $x0
-  ; GISEL-MIR:   [[COPY2:%[0-9]+]]:_(p0) = COPY $x0
   ; GISEL-MIR:   ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+  ; GISEL-MIR:   [[COPY2:%[0-9]+]]:_(p0) = COPY $x0
   ; GISEL-MIR:   $x0 = COPY [[COPY]](p0)
   ; GISEL-MIR:   RET_ReallyLR implicit $x0
 entry:
 ; CHECK-LABEL: C_ctor_complete_nothisret:
 ; CHECK-NOT: b {{_?C_ctor_base_nothisret}}
   %call = tail call ptr @C_ctor_base_nothisret(ptr %this, i32 %x)
   ret ptr %this
 }
 
 define ptr @D_ctor_base(ptr %this, i32 %x) {
   ; GISEL-MIR-LABEL: name: D_ctor_base
   ; GISEL-MIR: bb.1.entry:
   ; GISEL-MIR:   liveins: $w1, $x0
   ; GISEL-MIR:   [[COPY:%[0-9]+]]:_(p0) = COPY $x0
   ; GISEL-MIR:   [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
   ; GISEL-MIR:   ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
   ; GISEL-MIR:   $x0 = COPY [[COPY]](p0)
   ; GISEL-MIR:   $w1 = COPY [[COPY1]](s32)
   ; GISEL-MIR:   BL @B_ctor_complete, csr_aarch64_aapcs_thisreturn, implicit-def $lr, implicit $sp, implicit $x0, implicit $w1
-  ; GISEL-MIR:   [[COPY2:%[0-9]+]]:_(p0) = COPY [[COPY]](p0)
   ; GISEL-MIR:   ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+  ; GISEL-MIR:   [[COPY2:%[0-9]+]]:_(p0) = COPY [[COPY]](p0)
   ; GISEL-MIR:   $x0 = COPY [[COPY]](p0)
   ; GISEL-MIR:   $w1 = COPY [[COPY1]](s32)
   ; GISEL-MIR:   TCRETURNdi @B_ctor_complete, 0, csr_aarch64_aapcs, implicit $sp, implicit $x0, implicit $w1
 entry:
 ; CHECK-LABEL: D_ctor_base:
 ; CHECK-NOT: mov {{x[0-9]+}}, x0
 ; CHECK: bl {{_?B_ctor_complete}}
 ; CHECK-NOT: mov x0, {{x[0-9]+}}
 ; CHECK: b {{_?B_ctor_complete}}
   %call = tail call ptr @B_ctor_complete(ptr returned %this, i32 %x)
   %call2 = tail call ptr @B_ctor_complete(ptr returned %this, i32 %x)
   ret ptr %this
 }
 
 define ptr @E_ctor_base(ptr %this, i32 %x) {
   ; GISEL-MIR-LABEL: name: E_ctor_base
   ; GISEL-MIR: bb.1.entry:
   ; GISEL-MIR:   liveins: $w1, $x0
   ; GISEL-MIR:   [[COPY:%[0-9]+]]:_(p0) = COPY $x0
   ; GISEL-MIR:   [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
   ; GISEL-MIR:   ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
   ; GISEL-MIR:   $x0 = COPY [[COPY]](p0)
   ; GISEL-MIR:   $w1 = COPY [[COPY1]](s32)
   ; GISEL-MIR:   BL @B_ctor_complete, csr_aarch64_aapcs_thisreturn, implicit-def $lr, implicit $sp, implicit $x0, implicit $w1
-  ; GISEL-MIR:   [[COPY2:%[0-9]+]]:_(p0) = COPY [[COPY]](p0)
   ; GISEL-MIR:   ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+  ; GISEL-MIR:   [[COPY2:%[0-9]+]]:_(p0) = COPY [[COPY]](p0)
   ; GISEL-MIR:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
   ; GISEL-MIR:   [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64)
   ; GISEL-MIR:   ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
   ; GISEL-MIR:   $x0 = COPY [[PTR_ADD]](p0)
   ; GISEL-MIR:   $w1 = COPY [[COPY1]](s32)
   ; GISEL-MIR:   BL @B_ctor_complete, csr_aarch64_aapcs_thisreturn, implicit-def $lr, implicit $sp, implicit $x0, implicit $w1
-  ; GISEL-MIR:   [[COPY3:%[0-9]+]]:_(p0) = COPY [[PTR_ADD]](p0)
   ; GISEL-MIR:   ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+  ; GISEL-MIR:   [[COPY3:%[0-9]+]]:_(p0) = COPY [[PTR_ADD]](p0)
   ; GISEL-MIR:   $x0 = COPY [[COPY]](p0)
   ; GISEL-MIR:   RET_ReallyLR implicit $x0
 entry:
 ; CHECK-LABEL: E_ctor_base:
 ; CHECK-NOT: b {{_?B_ctor_complete}}
   %call = tail call ptr @B_ctor_complete(ptr returned %this, i32 %x)
   %b2 = getelementptr inbounds %struct.E, ptr %this, i32 0, i32 1
   %call2 = tail call ptr @B_ctor_complete(ptr returned %b2, i32 %x)
   ret ptr %this
 }