[BOLT][X86][NFC] Simplify the code of X86MCPlusBuilder::getAliasSized

[skan]

Fix build fail

[skan]

Try to fix build fail

[skan]

Try to fix runfail

[Amir]

Nice, thank you for reducing it!

[skan]

BTW, I'd like to ask if there any OS requirement for the bolt build @Amir ? I followed the instructions in https://code.ornl.gov/llvm-doe/llvm-project/-/tree/doe/bolt, but could not build bolt on RHEL9. Lots of "can not find header files errors".

[Amir]

In D144551#4146291, @skan wrote:

BTW, I'd like to ask if there any OS requirement for the bolt build @Amir ? I followed the instructions in https://code.ornl.gov/llvm-doe/llvm-project/-/tree/doe/bolt, but could not build bolt on RHEL9. Lots of "can not find header files errors".

No, RHEL should do. I'm able to build on CentOS8 using default host toolchain. Please open a bug and we'll look closer.

bolt/lib/Target/X86/X86MCPlusBuilder.cpp

void getClassicGPRegs(BitVector &Regs) const override {
     Regs |= getAliases(X86::RCX);
   }
 
   void getRepRegs(BitVector &Regs) const override {
     Regs |= getAliases(X86::RCX);
   }
 
   MCPhysReg getAliasSized(MCPhysReg Reg, uint8_t Size) const override {
-    switch (Reg) {
-    case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: case X86::AH:
-      switch (Size) {
-      case 8: return X86::RAX;       case 4: return X86::EAX;
-      case 2: return X86::AX;        case 1: return X86::AL;
-      default: llvm_unreachable("Unexpected size");
-      }
-    case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: case X86::BH:
-      switch (Size) {
-      case 8: return X86::RBX;       case 4: return X86::EBX;
-      case 2: return X86::BX;        case 1: return X86::BL;
-      default: llvm_unreachable("Unexpected size");
-      }
-    case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: case X86::DH:
-      switch (Size) {
-      case 8: return X86::RDX;       case 4: return X86::EDX;
-      case 2: return X86::DX;        case 1: return X86::DL;
-      default: llvm_unreachable("Unexpected size");
-      }
-    case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL:
-      switch (Size) {
-      case 8: return X86::RDI;       case 4: return X86::EDI;
-      case 2: return X86::DI;        case 1: return X86::DIL;
-      default: llvm_unreachable("Unexpected size");
-      }
-    case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL:
-      switch (Size) {
-      case 8: return X86::RSI;       case 4: return X86::ESI;
-      case 2: return X86::SI;        case 1: return X86::SIL;
-      default: llvm_unreachable("Unexpected size");
-      }
-    case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: case X86::CH:
-      switch (Size) {
-      case 8: return X86::RCX;       case 4: return X86::ECX;
-      case 2: return X86::CX;        case 1: return X86::CL;
-      default: llvm_unreachable("Unexpected size");
-      }
-    case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL:
-      switch (Size) {
-      case 8: return X86::RSP;       case 4: return X86::ESP;
-      case 2: return X86::SP;        case 1: return X86::SPL;
-      default: llvm_unreachable("Unexpected size");
-      }
-    case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL:
-      switch (Size) {
-      case 8: return X86::RBP;       case 4: return X86::EBP;
-      case 2: return X86::BP;        case 1: return X86::BPL;
-      default: llvm_unreachable("Unexpected size");
-      }
-  case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
-      switch (Size) {
-      case 8: return X86::R8;        case 4: return X86::R8D;
-      case 2: return X86::R8W;       case 1: return X86::R8B;
-      default: llvm_unreachable("Unexpected size");
-      }
-    case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
-      switch (Size) {
-      case 8: return X86::R9;        case 4: return X86::R9D;
-      case 2: return X86::R9W;       case 1: return X86::R9B;
-      default: llvm_unreachable("Unexpected size");
-      }
-    case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
-      switch (Size) {
-      case 8: return X86::R10;        case 4: return X86::R10D;
-      case 2: return X86::R10W;       case 1: return X86::R10B;
-      default: llvm_unreachable("Unexpected size");
-      }
-    case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
-      switch (Size) {
-      case 8: return X86::R11;        case 4: return X86::R11D;
-      case 2: return X86::R11W;       case 1: return X86::R11B;
-      default: llvm_unreachable("Unexpected size");
-      }
-    case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
-      switch (Size) {
-      case 8: return X86::R12;        case 4: return X86::R12D;
-      case 2: return X86::R12W;       case 1: return X86::R12B;
-      default: llvm_unreachable("Unexpected size");
-      }
-    case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
-      switch (Size) {
-      case 8: return X86::R13;        case 4: return X86::R13D;
-      case 2: return X86::R13W;       case 1: return X86::R13B;
-      default: llvm_unreachable("Unexpected size");
-      }
-    case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
-      switch (Size) {
-      case 8: return X86::R14;        case 4: return X86::R14D;
-      case 2: return X86::R14W;       case 1: return X86::R14B;
-      default: llvm_unreachable("Unexpected size");
-      }
-    case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
-      switch (Size) {
-      case 8: return X86::R15;        case 4: return X86::R15D;
-      case 2: return X86::R15W;       case 1: return X86::R15B;
-      default: llvm_unreachable("Unexpected size");
-      }
-    default:
-      dbgs() << Reg << " (get alias sized)\n";
-      llvm_unreachable("Unexpected reg number");
-      break;
-    }
+    Reg = getX86SubSuperRegister(Reg, Size * 8);
+    assert((Reg != X86::NoRegister) && "Invalid register");
+    return Reg;
   }
 
   bool isUpper8BitReg(MCPhysReg Reg) const override {
     switch (Reg) {
     case X86::AH:
     case X86::BH:
     case X86::CH:
     case X86::DH: