[AArch64] Always lower fp16 zero to FMOVH0

[dmgreen]

Summary

We can always use FMOVH0 to lower fp16 zero, even without fullfp16. We can either expand it to movi d0, #0 or fmov s0, wzr, which will both clear all the bits of the register.

[samtebbs]

LGTM

[SjoerdMeijer]

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

9774–9775

Nit: perhaps fix this broken sentence while we are at it.

But yeah, also LGTM.

llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp

if (STI->hasZeroCycleZeroingFP() && !STI->hasZeroCycleZeroingFPWorkaround() &&
     MOVI.addOperand(MCOperand::createReg(DestReg));
     MOVI.addOperand(MCOperand::createImm(0));
     EmitToStreamer(*OutStreamer, MOVI);
   } else {
     MCInst FMov;
     switch (MI.getOpcode()) {
     default: llvm_unreachable("Unexpected opcode");
     case AArch64::FMOVH0:
-      FMov.setOpcode(AArch64::FMOVWHr);
+      FMov.setOpcode(STI->hasFullFP16() ? AArch64::FMOVWHr : AArch64::FMOVWSr);
+      if (!STI->hasFullFP16())
+        DestReg = (AArch64::S0 + (DestReg - AArch64::H0));
       FMov.addOperand(MCOperand::createReg(DestReg));
       FMov.addOperand(MCOperand::createReg(AArch64::WZR));
       break;
     case AArch64::FMOVS0:
       FMov.setOpcode(AArch64::FMOVWSr);
       FMov.addOperand(MCOperand::createReg(DestReg));
       FMov.addOperand(MCOperand::createReg(AArch64::WZR));
       break;

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

bool AArch64TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
   bool IsLegal = false;
   // We can materialize #0.0 as fmov $Rd, XZR for 64-bit, 32-bit cases, and
   // 16-bit case when target has full fp16 support.
   // FIXME: We should be able to handle f128 as well with a clever lowering.
   const APInt ImmInt = Imm.bitcastToAPInt();
   if (VT == MVT::f64)
     IsLegal = AArch64_AM::getFP64Imm(ImmInt) != -1 || Imm.isPosZero();
   else if (VT == MVT::f32)
     IsLegal = AArch64_AM::getFP32Imm(ImmInt) != -1 || Imm.isPosZero();
-  else if (VT == MVT::f16 && Subtarget->hasFullFP16())
-    IsLegal = AArch64_AM::getFP16Imm(ImmInt) != -1 || Imm.isPosZero();
-  // TODO: fmov h0, w0 is also legal, however on't have an isel pattern to
-  //       generate that fmov.
+  else if (VT == MVT::f16)
+    IsLegal =
+        (Subtarget->hasFullFP16() && AArch64_AM::getFP16Imm(ImmInt) != -1) ||
+        Imm.isPosZero();
 
   // If we can not materialize in immediate field for fmov, check if the
   // value can be encoded as the immediate operand of a logical instruction.
   // The immediate value will be created with either MOVZ, MOVN, or ORR.
+  // TODO: fmov h0, w0 is also legal, however we don't have an isel pattern to
+  //       generate that fmov.
   if (!IsLegal && (VT == MVT::f64 || VT == MVT::f32)) {
     // The cost is actually exactly the same for mov+fmov vs. adrp+ldr;
     // however the mov+fmov sequence is always better because of the reduced
     // cache pressure. The timings are still the same if you consider
     // movw+movk+fmov vs. adrp+ldr (it's one instruction longer, but the
     // movw+movk is fused). So we limit up to 2 instrdduction at most.
     SmallVector<AArch64_IMM::ImmInsnModel, 4> Insn;
     AArch64_IMM::expandMOVImm(ImmInt.getZExtValue(), VT.getSizeInBits(), Insn);

llvm/lib/Target/AArch64/AArch64InstrInfo.td

 // Unscaled integer to floating point conversion instruction.
 //===----------------------------------------------------------------------===//
 
 defm FMOV : UnscaledConversion<"fmov">;
 
 // Add pseudo ops for FMOV 0 so we can mark them as isReMaterializable
 let isReMaterializable = 1, isCodeGenOnly = 1, isAsCheapAsAMove = 1 in {
 def FMOVH0 : Pseudo<(outs FPR16:$Rd), (ins), [(set f16:$Rd, (fpimm0))]>,
-    Sched<[WriteF]>, Requires<[HasFullFP16]>;
+    Sched<[WriteF]>;
 def FMOVS0 : Pseudo<(outs FPR32:$Rd), (ins), [(set f32:$Rd, (fpimm0))]>,
     Sched<[WriteF]>;
 def FMOVD0 : Pseudo<(outs FPR64:$Rd), (ins), [(set f64:$Rd, (fpimm0))]>,
     Sched<[WriteF]>;
 }
 // Similarly add aliases
 def : InstAlias<"fmov $Rd, #0.0", (FMOVWHr FPR16:$Rd, WZR), 0>,
     Requires<[HasFullFP16]>;

llvm/test/CodeGen/AArch64/arm64-fmax.ll

 }
 
 ; FIXME: It'd be nice for this to create an fmin instruction!
 define float @test_f16(half %in) {
 ; CHECK-LABEL: test_f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $h0 killed $h0 def $s0
 ; CHECK-NEXT:    fcvt s1, h0
-; CHECK-NEXT:    adrp x8, .LCPI5_0
-; CHECK-NEXT:    ldr h2, [x8, :lo12:.LCPI5_0]
+; CHECK-NEXT:    movi d2, #0000000000000000
 ; CHECK-NEXT:    fcmp s1, #0.0
 ; CHECK-NEXT:    fcsel s0, s0, s2, lt
 ; CHECK-NEXT:    fcvt s0, h0
 ; CHECK-NEXT:    ret
   %cmp = fcmp nnan ult half %in, 0.000000e+00
   %val = select i1 %cmp, half %in, half 0.000000e+00
   %longer = fpext half %val to float
   ret float %longer
 }

llvm/test/CodeGen/AArch64/arm64-zero-cycle-zeroing.ll

 declare void @bari(i32, i32)
 declare void @barl(i64, i64)
 declare void @barf(float, float)
 
 define void @t1() nounwind ssp {
 entry:
 ; ALL-LABEL: t1:
 ; ALL-NOT: fmov
-; NONEFP-DAG: ldr h0,{{.*}}
+; NONEFP-DAG: fmov s0, wzr
 ; NONEFP-DAG: fmov s1, wzr
 ; NONEFP-DAG: fmov d2, xzr
 ; NONEFP-DAG: movi{{(.16b)?}} v3{{(.2d)?}}, #0
 ; NONE16: fmov h0, wzr
 ; NONE16: fmov s1, wzr
 ; NONE16: fmov d2, xzr
 ; NONE16: movi{{(.16b)?}} v3{{(.2d)?}}, #0
-; ZEROFP-DAG: ldr h0,{{.*}}
+; ZEROFP-DAG: movi d0, #0
 ; ZEROFP-DAG: movi d1, #0
 ; ZEROFP-DAG: movi d2, #0
 ; ZEROFP-DAG: movi v3.2d, #0
 ; ZERO16: movi d0, #0
 ; ZERO16: movi d1, #0
 ; ZERO16: movi d2, #0
 ; ZERO16: movi v3.2d, #0
   tail call void @bar(half 0.000000e+00, float 0.000000e+00, double 0.000000e+00, <2 x double> <double 0.000000e+00, double 0.000000e+00>) nounwind

llvm/test/CodeGen/AArch64/f16-imm.ll

 ;
 ; CHECK-ZCZ-LABEL: Const0:
 ; CHECK-ZCZ:       // %bb.0: // %entry
 ; CHECK-ZCZ-NEXT:    movi d0, #0000000000000000
 ; CHECK-ZCZ-NEXT:    ret
 ;
 ; CHECK-NOFP16-LABEL: Const0:
 ; CHECK-NOFP16:       // %bb.0: // %entry
-; CHECK-NOFP16-NEXT:    adrp x8, .LCPI0_0
-; CHECK-NOFP16-NEXT:    ldr h0, [x8, :lo12:.LCPI0_0]
+; CHECK-NOFP16-NEXT:    movi d0, #0000000000000000
 ; CHECK-NOFP16-NEXT:    ret
 entry:
   ret half 0xH0000
 }
 
 define half @Const1() {
 ; CHECK-FP16-LABEL: Const1:
 ; CHECK-FP16:       // %bb.0: // %entry

llvm/test/CodeGen/AArch64/mattr-all.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ;; -mattr=+all is not intended to be used for code emitters. Nevertheless,
 ;; llc does not reject it. This test intends to catch behavior changes.
 ; RUN: llc -mtriple=aarch64 -mattr=+all < %s | FileCheck %s
 
 define half @bf16() nounwind {
 ; CHECK-LABEL: bf16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI0_0
-; CHECK-NEXT:    ldr h0, [x8, :lo12:.LCPI0_0]
+; CHECK-NEXT:    movi d0, #0000000000000000
 ; CHECK-NEXT:    ret
   ret half 0xH0000
 }

llvm/test/CodeGen/AArch64/vecreduce-fadd.ll

 ; FULLFP16-NEXT:    faddp h1, v1.2h
 ; FULLFP16-NEXT:    fadd h0, h1, h0
 ; FULLFP16-NEXT:    b.ne .LBB10_1
 ; FULLFP16-NEXT:  // %bb.2: // %exit
 ; FULLFP16-NEXT:    ret
 ;
 ; CHECKNOFP16-LABEL: fadd_reduction_v4f16_in_loop:
 ; CHECKNOFP16:       // %bb.0: // %entry
-; CHECKNOFP16-NEXT:    adrp x9, .LCPI10_0
+; CHECKNOFP16-NEXT:    movi d0, #0000000000000000
 ; CHECKNOFP16-NEXT:    mov x8, xzr
-; CHECKNOFP16-NEXT:    ldr h0, [x9, :lo12:.LCPI10_0]
 ; CHECKNOFP16-NEXT:  .LBB10_1: // %loop
 ; CHECKNOFP16-NEXT:    // =>This Inner Loop Header: Depth=1
 ; CHECKNOFP16-NEXT:    ldr d1, [x0, x8]
 ; CHECKNOFP16-NEXT:    fcvt s0, h0
 ; CHECKNOFP16-NEXT:    add x8, x8, #8
 ; CHECKNOFP16-NEXT:    cmp w8, #56
 ; CHECKNOFP16-NEXT:    mov h2, v1.h[1]
 ; CHECKNOFP16-NEXT:    fcvt s3, h1

 ; FULLFP16-NEXT:    faddp h1, v1.2h
 ; FULLFP16-NEXT:    fadd h0, h1, h0
 ; FULLFP16-NEXT:    b.ne .LBB11_1
 ; FULLFP16-NEXT:  // %bb.2: // %exit
 ; FULLFP16-NEXT:    ret
 ;
 ; CHECKNOFP16-LABEL: fadd_reduction_v8f16_in_loop:
 ; CHECKNOFP16:       // %bb.0: // %entry
-; CHECKNOFP16-NEXT:    adrp x9, .LCPI11_0
+; CHECKNOFP16-NEXT:    movi d0, #0000000000000000
 ; CHECKNOFP16-NEXT:    mov x8, xzr
-; CHECKNOFP16-NEXT:    ldr h0, [x9, :lo12:.LCPI11_0]
 ; CHECKNOFP16-NEXT:  .LBB11_1: // %loop
 ; CHECKNOFP16-NEXT:    // =>This Inner Loop Header: Depth=1
 ; CHECKNOFP16-NEXT:    ldr q1, [x0, x8]
 ; CHECKNOFP16-NEXT:    fcvt s0, h0
 ; CHECKNOFP16-NEXT:    add x8, x8, #8
 ; CHECKNOFP16-NEXT:    cmp w8, #56
 ; CHECKNOFP16-NEXT:    mov h2, v1.h[1]
 ; CHECKNOFP16-NEXT:    fcvt s3, h1