[mips] Expansion of LI.S and LI.D

[smaksimovic]

Summary

This patch introduces LI.S and LI.D pseudo instructions with floating point operands.

[vkalintiris]

I believe that we can achieve the same thing without introducing new floating-point operands. We could add the AsmToken::Real case in the switch cases inside parseImm() & parseOperand(). This way the generic parser would parse the floats/doubles, saving the result in a int64_t type. After that it's just a matter of re-interpreting the bits to float or double depending on the instruction that we expand, and save the new bits in in64_t again. This would allow us to utilize the backtracking from the generic matcher in the future. Of course, we wouldn't be able to print() the operands with their types. However, we only care for their value, not their types, so there's no harm done.

[dsanders]

Please provide the whole context as per http://llvm.org/docs/Phabricator.html#requesting-a-review-via-the-web-interface

In D14390#313777, @vkalintiris wrote:

I believe that we can achieve the same thing without introducing new floating-point operands. We could add the AsmToken::Real case in the switch cases inside parseImm() & parseOperand(). This way the generic parser would parse the floats/doubles, saving the result in a int64_t type. After that it's just a matter of re-interpreting the bits to float or double depending on the instruction that we expand, and save the new bits in in64_t again. This would allow us to utilize the backtracking from the generic matcher in the future. Of course, we wouldn't be able to print() the operands with their types. However, we only care for their value, not their types, so there's no harm done.

I haven't fully read the patch yet but there's some high-level things to talk about.

There's a good reason to avoid adding the new MipsOperand kinds which is that it's important that the MipsOperand kinds do not overlap. We had some really big problems with this a year or two ago and I ended up rewriting a lot of the parsing and MipsOperand handling to resolve it. This patch currently re-introduces the root cause of those problems which I'm keen to avoid doing.

The problem with overlapping MipsOperand kinds is that there's only one chance to get the operand kind correct and there's no support for backtracking. In the original problem we had two 'add.d' instructions with one accepting FGR64 registers, and the other accepting AFGR64. These two register classes use the same set of names ($f0, $f1, ...). Our matcher table contained both possibilities with the FGR64 one appearing first. What happened was, the ParserMethod for FGR64 would be called and would create three MipsOperand of kind k_Register with, for example, registers D0, D1, and D2. It would then check the feature bits and reject this match because the feature bits said that the FPU was 32-bit (and therefore D0_64, D1_64, and D2_64 were needed instead). Then it would try the AFGR64 case but because there's no backtracking, we still had the same MipsOperand's. The PredicateMethod would always return false for these because D0/D1/D2 are not members of AFGR64 and we would therefore reject this match too. Having found no match, we would then reject the input and error out. Variants of this problem affected the majority of our instruction set in one way or another.

This problem almost manifests in this patch for inputs like:

li.s $2, 1

If it weren't for the ParserMethod's (which we ought to remove, we need to keep them to a minimum because they cause the above problems), the '1' would become a MipsOperand of kind k_Immediate which would never pass the PredicateMethod.

I'd approach this in a similar way to what Vasileios is describing but more towards the way k_RegisterIndex works. I'd have a single k_Immediate operand that separately holds integer, and APFloat values as well as a bitfield indicating which types are possible. I'd then have appropriate MipsOperand::Create*Imm functions that tell it which types are possible with '1' being valid for integer, float, and double, while '1.1' would only be valid for float and double. Finally, I'd have predicate methods that test the appropriate encoding (if it's valid) and a render method for each encoding to add the appropriately converted operand to the instruction.

This is a lot easier to explain with in person and with diagrams :-). Did that make sense?

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

558

Why did you remove RegKind_FGR? Without it, you can't match things like:

mfc1 $2, $3

which is equivalent to:

mfc1 $2, $f3

lib/Target/Mips/MCTargetDesc/MipsBaseInfo.h

128–216 ↗

(On Diff #39399)

I don't understand this code. We don't have 8-bit floating point to my knowledge and li.s/li.d should be able to handle normal 32-bit and 64-bit floating point values respectively.

lib/Target/Mips/MipsInstrFPU.td

560–579

Formatting. It looks like you may have used clang-format on a tablegen file which won't work correctly.

test/MC/Mips/li.s.s

5–7 ↗

(On Diff #39399)

Hmm, it looks like we have some rounding here. I think it should be 0x3f8fcd35 but GAS emits the same output.

[obucina]

Expansion of LI.S and LI.D without introducing new floating-point operands.

[obucina]

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

556

RegKind_FGR is removed because we didn't find another way to distinguish RegKind_GPR and RegKind_FGR in
li.s $4 1.12345 and li.s $f4 1.12345, for example. Actually, for $4 in llvm is created RegKind_Numeric register, that is defined as RegKind_Numeric = RegKind_GPR | RegKind_FGR | RegKind_FCC ..., so condition isFGRAsmReg() in validateOperandClass() function (in MipsGenAsmMatcher.inc) is true for $4 and we get the expansion for RegKind_FGR instead of RegKind_GPR.

[obucina]

Previous patch did not contain test cases. Added here.

[dsanders]

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

556

RegKind_FGR is removed because we didn't find another way to distinguish RegKind_GPR and RegKind_FGR in li.s $4 1.12345 and li.s $f4 1.12345, for example.

This should work:

bool isStrictlyFGRAsmReg() { return isRegIdx() && RegIdx.Kind == RegKind_FGR && RegIdx.Index <= 31; }

This will only be true when an FGR is the only option (i.e. the source said '$f4'). You'll also need to subclass FGR32/FGR64/AFGR64 in tablegen, override the predicate method to isStrictlyFGRAsmReg, and use those new operands in the li.s/li.d pseudos.

Actually, for $4 in llvm is created RegKind_Numeric register, that is defined as RegKind_Numeric = RegKind_GPR | RegKind_FGR | RegKind_FCC ..., so condition isFGRAsmReg() in validateOperandClass() function (in MipsGenAsmMatcher.inc) is true for $4 and we get the expansion for RegKind_FGR instead of RegKind_GPR.

$4 is a RegKind_Numeric because $4 is ambiguous without additional context. It could be a A0, F4, D4, D4_64, FCC4, COP24 (register 4 in the COP2 set, we should probably add an underscore to the name), etc. depending on the mnemonic and which operand it appears in. The same is true of $f4 and RegKind_FGR to a lesser extent. It's still ambiguous which register '$f4' refers to and could be F4, D4, or D4_64 but it definitely isn't A0, COP24, etc.

The main thing here is that MipsOperand describes what the operand _might_ be rather than what it really is (we figure out what it _is_ at a later point in the assembler). With that in mind, MipsOperand::RegIdxOp::Kind is a bitfield representing all the possible interpretations of the operand by any instruction in our instruction set. There are some instructions where $4 is a floating point register, therefore RegKind_FGR must be part of RegKind_Numeric.

The ambiguity is resolved by the match table in the AsmMatcher. For each matchable, we call a particular predicate on each operand (specified in the tablegen definitions) and the first one to find that all the predicates are true is a match. When you have multiple matchables that can accept the same operands, the one that appears first in the table is chosen. I expect that LoadImmDoubleFGR appears first in your table so $4 is accepted there and LoadImmDoubleGPR never has the chance to match. We need to either make the two cases distinct (see isStrictlyFGRAsmReg() above) or control the sort order of the table.

lib/Target/Mips/MipsInstrFPU.td

602–616

These should have the appropriate FGR_32, FGR_64, and HARDFLOAT adjectives.

614

I don't think you mean FGR32Opnd here. You need FGR64Opnd for a 64-bit FPU and AFGR64Opnd for a 32-bit FPU.

[mamidzic]

Changes according to the review

[dsanders]

Hi,

I'm unlikely to be able to look at this in the near future. I've added the new Mips code-owner (Simon) to the review.

[sdardis]

In several places there is the expression 'FirstReg + 1', This is unsafe as tablegen does not order the registers in the namespace as you would expect. Instead write a helper function to compute the next register.

Currently lib/Target/Mips/MipsGenRegisterInfo.inc in the build directory, the next register after a3 is ac0, not t0.

The second issue is that the mthc0 is only available for MIPS32r2 or later. For earlier revisions, the expansion is to use two mtcs, accessing the next numerical register and treating f0 as the "next register" in the f31 case.

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

197–201

There appears to be spurious white space on the line before this prototype, please remove it when you're committing.

921

Here too.

956

Whitespace here too.

2196

Here as well.

2750–2756

Please adjust the comment to say that this is a conversion of a double in an uint64_t to a float in a uint32_t, retaining the bit pattern of a float.

2805

Indentation, this needs another space before the TOut.emitRRX(Mips::LWC1, ...

2830–2836

Nm.

2874–2875

Rather than using FirstReg + 1, instead write a helper function to compute the next register. It is unsafe to rely on tablegen ordering the registers in the expected manner.

Currently with FirstReg == Mips::A3, FirstReg + 1 is Mips::AC0, not Mips::T0.

lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp

714

Spurious newline.

lib/Target/Mips/MipsInstrFPU.td

606–608

This needs a HARDFLOAT predicate.

test/MC/Mips/macro-li.d.s

268

Spurious whitespace at the end of this line.

test/MC/Mips/macro-li.s.s

32

Spurious whitespace at the end of this line.

86

Spurious whitespace at the end of this line.

[sdardis]

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

197–201

It's actually whitespace, not the line I'm concerned about.

921

It's actually whitespace, not the line I'm concerned about.

[mamidzic]

Addressed review comments.

[sdardis]

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

2759

Two things:

This function also needs to handle floating point registers.

Rather than returning 0, instead call llvm_unreachable("Unknown register in assembly macro expansion!");

2919

This block has the wrong condition. This should check that the lower 32 bits are zero and the high part can be loaded with a single instruction.

2921–2926

Add a FIXME comment here noting that in the case where the constant is zero, we can load the register directly from the zero register.

2923

This condition is not required.

2927

This also needs a check for hasMips64() before checking hasMips32r2(). In the mips64 case, we use dmtc1.

2928–2929

If you've reverse engineered this from the output of gas, you've hit upon a latent gas bug.

On a MIPS32 system (or a MIPS64 system executing MIPS32 code) , writing to a 64 bit FPU register must be done in a specific order; use mtc1 to write the lower 32bits, then use mthc1 to write the upper 32 bits. mtcX instructions leave the upper 32bits *UNPREDICTABLE*.

Reverse the order of these two lines.

2931–2932

See my comment about nextReg.

Also, indentation is incorrect.

2969–2970

Rather than Mips::LDC1, this should be (IsFPU64 ? Mips::LDC164 : Mips::LDC1) to get the correct instruction.

Add a FIXME comment here noting that this expansion is incorrect for mips1, it should expand to two word loads.

test/MC/Mips/macro-li.d.s

2

Can you also a RUN line for mips32 and add appropriate tests?

[mamidzic]

Addressed the review comments.

[sdardis]

I missed something the first time around reviewing this. The usage of the .lit4 & .lit8 is conditional on the usage of the sdata section. For now, you can removed the .litX handling and just use .rodata in all cases. There's a longer explanation inline.

Thanks,
Simon

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

2726–2727

This is almost correct. GAS will assemble "li.d $f31, 2.5" into "lui $at, 0x4004; mtc $at, $f0; mtc $zero, $f31".

You'll need to expand out the check or check for that specific case.

2761

Stray space the end of the line.

2833–2839

I missed this the first time around. The usage of .lit4 & .lit8 is permitted when: a) the small data section is in use, and b) the size of the constant is within the size threshold for the small data section.

If the small data section cannot be used, the constant is located within the .rodata section.

For the moment, just change this to always use the .rodata section, and add "FIXME: Enhance this expansion to use the .lit4 & .lit8 sections where appropriate."

This avoids having to modify MipsTargetObjectFile.cpp with arguably unrelated changes.

2958–2966

See my comment about the .lit4 section.

test/MC/Mips/macro-li.d.s

306

Please put a newline at the end of the file.

[smaksimovic]

Addressed review comments.

[sdardis]

A few small things. Mostly the changes necessary are along the lines of differentiating between PIC and non-PIC. I've written them inline. The other minor change is that you should remove the stub implementation of the literal section and submit that afterwards. It will be easier to implement/review then.

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

2809–2815

Rather than going through void pointers, use BitsToDouble & co. from llvm/Support/MathExtras.h.

2850–2867

This section isn't quite right.

In the PIC case, we have to load the address of the constant via the GOT, with a R_MIPS_GOT16 relocation attached to an lw. Then load the constant with ldc with a relocation type R_MIPS_LO16 attached to it.

In the non-pic case, it's lui with a R_MIPS_HI16 relocation, then a ldc1 with a R_MIPS_LO16.

2881–2886

This is the expected behaviour for loading a 64bit value in 32bit GPRs. For 64 bit GPRs we have to load it into a single register. Test the ABI to determine if we should load into one or two registers.

2910–2936

This hunk needs to be re-arranged slightly. The first step is to generate an emit the upper portion of the constant's address for non-PIC or load the address of the the constant from the GOT. Both cases set up $at.

The second step is to build an expression that refers to the base address of the constant.

Then finally, if the ABI is N32 or N64 perform emit ld, otherwise since it's O32, emit two loads.

2950

This should be

if (isABI_N32() || isABI_N64())

as the instruction expansion is dependant on the ABI.

2980–2996

This section isn't quite right.

In the PIC case, we have to load the address of the constant via the GOT, with a R_MIPS_GOT16 relocation attached to an ld. Then load the constant with ldc with a relocation type R_MIPS_LO16 attached to it.

In the non-pic case, it's lui with a R_MIPS_HI16 relocation, then a ldc1 with a R_MIPS_LO16.

test/MC/Mips/macro-li.s

1 ↗

(On Diff #88364)

This file can be kept, it's testing a different macro.

[smaksimovic]

Made additional ABI checks when loading floats to FPRs, doubles to GPRs and doubles to FPRs.
We've mostly compared it to GCC, the caveat being that GCC generates floats using lui/ori in GPRs and then moves them to FPRs with mtc1 if necessary,
whereas we always place constants into .rodata, and have relocations accordingly.

Another difference is that despite invoking GCC without -fpic flag for n64, it generates code that has R_MIPS_GOT16 relocations.
Implemented that part to use %higher, %highest relocations to fetch the address.

[sdardis]

This needs a bit more work. The problem is that the address for the constant loads is the address of the .rodata section, not the address of the constant in the .rodata section. I've spelled out the changes required inline.

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

2781

Can you make this a private class member of MipsAsmParser instead?

It avoids having to explicitly pass STI, ATReg, IsPicEnabled.

2882–2896

See my comment about generating the addresses correctly.

2930–2942

See my comment about generating addresses correctly.

2982–2994

This two hunks need to be reversed and modified slightly.

The problem is that you're generating the symbol with the name of the ReadOnlySection. The linker will resolve this as to the start of the ReadOnlySection and rewrite the relocs to that value.

Instead, you need to create a symbol visible to this object, switch to the ReadOnlySection, then emit the symbol and data.

test/MC/Mips/macro-li.d.s

2

Small change here for both files. Can you use the label O32-N32-(NO-)PIC as required? It makes to more obvious that the check lines are for O32 and N32.

[smaksimovic]

Addressed review comments.

[sdardis]

LGTM with the fixmes added and the whitespace nit addressed.

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

2806

Sorry, I missed something here. For O32 and N32 all addresses are 32 bits. For N64 addresses are 64 bits unless -msym32 is used--in which case symbols are 32 bits.

Unfortunately, I've found something questionable in the GNU assembler which is that li.d always assumes that the address of the temporary symbol used to load the constant is always 32 bits in the non-pic case.

Can you attach two fixmes here? The first is that our assembler is technically correct but gives a different result to gas but gas is incomplete there (it has a fixme noting it doesn't work with 64-bit addresses). The second is that with -msym32 the address expansion for N64 should probably use the O32 / N32 case. It's safe to use the 64 address expansion as the symbol's value is considered sign extended.

2943–2944

FIXME: This method is too general. In principal we should compute the number of instructions required to synthesize the immediate inline compared to synthesising the address inline and relying on non .text sections. For static O32 and N32 this may yield a small benefit, for static N64 this is likely to yield a much larger benefit as we have to synthesize a 64bit address to load a 64 bit value.

test/MC/Mips/macro-li.d.s

357

Spurious whitespace at the end of this line.

[sdardis]

We'll need @dsanders 's opinion too.

[dsanders]

I haven't looked too closely at the output of the macro since I don't know what it should be but it looks like the issues I raised earlier in the review are no longer there. I just have one nit about nextReg().

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

2725

I'd recommend a comment mentioning the D0 + 1 == F1 and F1 + 1 == D1 quirks. It makes sense when you're thinking of it in the context of where it's being used but F1 + 1 == D1 in particular isn't very obvious without that context. It would be reasonable for a reader to expect F1 + 1 == F2.

[smaksimovic]

Removed whitespace, added fixmes and a comment.

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

bool loadImmediate(int64_t ImmValue, unsigned DstReg, unsigned SrcReg,
                      MCStreamer &Out, const MCSubtargetInfo *STI);
 
   bool loadAndAddSymbolAddress(const MCExpr *SymExpr, unsigned DstReg,
                                unsigned SrcReg, bool Is32BitSym, SMLoc IDLoc,
                                MCStreamer &Out, const MCSubtargetInfo *STI);
 
   bool expandLoadImm(MCInst &Inst, bool Is32BitImm, SMLoc IDLoc,
                      MCStreamer &Out, const MCSubtargetInfo *STI);
   
+  bool expandLoadImmReal(MCInst &Inst, bool IsSingle, bool IsGPR, bool Is64FPU,
+                         SMLoc IDLoc, MCStreamer &Out,
+                         const MCSubtargetInfo *STI);
+
   bool expandLoadAddress(unsigned DstReg, unsigned BaseReg,
                          const MCOperand &Offset, bool Is32BitAddress,
                          SMLoc IDLoc, MCStreamer &Out,
                          const MCSubtargetInfo *STI);
 
   bool expandUncondBranchMMPseudo(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
                                   const MCSubtargetInfo *STI);
 
bool useTraps() const {
     return getSTI().getFeatureBits()[Mips::FeatureUseTCCInDIV];
   }
 
   bool useSoftFloat() const {
     return getSTI().getFeatureBits()[Mips::FeatureSoftFloat];
   }
 
   /// Warn if RegIndex is the same as the current AT.
   void warnIfRegIndexIsAT(unsigned RegIndex, SMLoc Loc);
 
   void warnIfNoMacro(SMLoc Loc);
 
   bool isLittle() const { return IsLittleEndian; }
 
   const MCExpr *createTargetUnaryExpr(const MCExpr *E,
                                       AsmToken::TokenKind OperatorToken,
                                       MCContext &Ctx) override {
     switch(OperatorToken) {
     default:
void addGPR64AsmRegOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     Inst.addOperand(MCOperand::createReg(getGPR64Reg()));
   }
 
   void addAFGR64AsmRegOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     Inst.addOperand(MCOperand::createReg(getAFGR64Reg()));
   }
   
+  void addStrictlyAFGR64AsmRegOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 1 && "Invalid number of operands!");
+    Inst.addOperand(MCOperand::createReg(getAFGR64Reg()));
+  }
+
+  void addStrictlyFGR64AsmRegOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 1 && "Invalid number of operands!");
+    Inst.addOperand(MCOperand::createReg(getFGR64Reg()));
+  }
+
   void addFGR64AsmRegOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     Inst.addOperand(MCOperand::createReg(getFGR64Reg()));
   }
 
   void addFGR32AsmRegOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     Inst.addOperand(MCOperand::createReg(getFGR32Reg()));
     // FIXME: We ought to do this for -integrated-as without -via-file-asm too.
     // FIXME: This should propagate failure up to parseStatement.
     if (!AsmParser.useOddSPReg() && RegIdx.Index & 1)
       AsmParser.getParser().printError(
           StartLoc, "-mno-odd-spreg prohibits the use of odd FPU "
                     "registers");
   }
 
+  void addStrictlyFGR32AsmRegOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 1 && "Invalid number of operands!");
+    Inst.addOperand(MCOperand::createReg(getFGR32Reg()));
+    // FIXME: We ought to do this for -integrated-as without -via-file-asm too.
+    if (!AsmParser.useOddSPReg() && RegIdx.Index & 1)
+      AsmParser.Error(StartLoc, "-mno-odd-spreg prohibits the use of odd FPU "
+                                "registers");
+  }
+  
   void addFGRH32AsmRegOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     Inst.addOperand(MCOperand::createReg(getFGRH32Reg()));
   }
 
   void addFCCAsmRegOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     Inst.addOperand(MCOperand::createReg(getFCCReg()));
if (!(isRegIdx() && RegIdx.Kind))
       return false;
     return (RegIdx.Index == 0 || (RegIdx.Index >= 2 && RegIdx.Index <= 3) ||
       (RegIdx.Index >= 16 && RegIdx.Index <= 20));
   }
   bool isFGRAsmReg() const {
     // AFGR64 is $0-$15 but we handle this in getAFGR64()
     return isRegIdx() && RegIdx.Kind & RegKind_FGR && RegIdx.Index <= 31;
   }
+  bool isStrictlyFGRAsmReg() const {
+    // AFGR64 is $0-$15 but we handle this in getAFGR64()
+    return isRegIdx() && RegIdx.Kind == RegKind_FGR && RegIdx.Index <= 31;
+  }
   bool isHWRegsAsmReg() const {
     return isRegIdx() && RegIdx.Kind & RegKind_HWRegs && RegIdx.Index <= 31;
   }
   bool isCCRAsmReg() const {
     return isRegIdx() && RegIdx.Kind & RegKind_CCR && RegIdx.Index <= 31;
   }
   bool isFCCAsmReg() const {
     if (!(isRegIdx() && RegIdx.Kind & RegKind_FCC))
case Mips::PseudoTRUNC_W_S:
     return expandTrunc(Inst, false, false, IDLoc, Out, STI) ? MER_Fail
                                                             : MER_Success;
   case Mips::PseudoTRUNC_W_D32:
     return expandTrunc(Inst, true, false, IDLoc, Out, STI) ? MER_Fail
                                                            : MER_Success;
   case Mips::PseudoTRUNC_W_D:
     return expandTrunc(Inst, true, true, IDLoc, Out, STI) ? MER_Fail
                                                           : MER_Success;
+    
+  case Mips::LoadImmSingleGPR:
+    return expandLoadImmReal(Inst, true, true, false, IDLoc, Out, STI)
+               ? MER_Fail
+               : MER_Success;
+  case Mips::LoadImmSingleFGR:
+    return expandLoadImmReal(Inst, true, false, false, IDLoc, Out, STI)
+               ? MER_Fail
+               : MER_Success;
+  case Mips::LoadImmDoubleGPR:
+    return expandLoadImmReal(Inst, false, true, false, IDLoc, Out, STI)
+               ? MER_Fail
+               : MER_Success;
+  case Mips::LoadImmDoubleFGR:
+      return expandLoadImmReal(Inst, false, false, true, IDLoc, Out, STI)
+               ? MER_Fail
+               : MER_Success;
+  case Mips::LoadImmDoubleFGR_32:
+    return expandLoadImmReal(Inst, false, false, false, IDLoc, Out, STI)
+               ? MER_Fail
+               : MER_Success;
   case Mips::Ulh:
     return expandUlh(Inst, true, IDLoc, Out, STI) ? MER_Fail : MER_Success;
   case Mips::Ulhu:
     return expandUlh(Inst, false, IDLoc, Out, STI) ? MER_Fail : MER_Success;
   case Mips::Ulw:
     return expandUlw(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
   case Mips::NORImm:
     return expandAliasImmediate(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
if (UseSrcReg)
     TOut.emitRRR(Mips::ADDu, DstReg, TmpReg, SrcReg, IDLoc, STI);
   else
     assert(
         getContext().getRegisterInfo()->isSuperOrSubRegisterEq(DstReg, TmpReg));
 
   return false;
 }
 
+bool MipsAsmParser::expandLoadImmReal(MCInst &Inst, bool IsSingle, bool IsGPR,
+                                      bool Is64FPU, SMLoc IDLoc,
+                                      MCStreamer &Out,
+                                      const MCSubtargetInfo *STI) {
+  MipsTargetStreamer &TOut = getTargetStreamer();
+  assert(Inst.getNumOperands() == 2 && "Invalid operand count");
+  assert(Inst.getOperand(0).isReg() && Inst.getOperand(1).isImm() &&
+         "Invalid instruction operand.");
+
+  unsigned FirstReg = Inst.getOperand(0).getReg();
+  uint64_t ImmOp64 = Inst.getOperand(1).getImm();
+
+  uint64_t HiImmOp64 = (ImmOp64 & 0xffffffff00000000) >> 32;
+  // If ImmOp64 is AsmToken::Integer type (all bits set to zero in the
+  // exponent field), convert it to double (e.g. 1 to 1.0)
+  if ((HiImmOp64 & 0x7ff00000) == 0) {
+    APFloat RealVal(APFloat::IEEEdouble, ImmOp64);
+    ImmOp64 = RealVal.bitcastToAPInt().getZExtValue();
+  }
+
+  uint64_t LoImmOp64 = ImmOp64 & 0xffffffff;
+  HiImmOp64 = (ImmOp64 & 0xffffffff00000000) >> 32;
+
+  if (IsSingle) {
+    uint32_t ImmOp32;
+    // Convert double ImmOp64 into single ImmOp32
+    void *void_pt = static_cast<void *>(&ImmOp64);
+    double *double_pt = static_cast<double *>(void_pt);
+    float tmp_float = static_cast<float>(*double_pt);
+    void_pt = &tmp_float;
+    uint32_t *uint32_pt = static_cast<uint32_t *>(void_pt);
+    ImmOp32 = *uint32_pt;
+
+    if (IsGPR) {
+      if (loadImmediate(ImmOp32, FirstReg, Mips::NoRegister, true, true, IDLoc,
+                        Out, STI))
+        return true;
+      return false;
+    } else {
+      if (LoImmOp64 == 0) {
+        unsigned ATReg = getATReg(IDLoc);
+        if (!ATReg)
+          return true;
+
+        if (loadImmediate(ImmOp32, ATReg, Mips::NoRegister, true, true, IDLoc,
+                          Out, STI))
+          return true;
+        TOut.emitRR(Mips::MTC1, FirstReg, ATReg, IDLoc, STI);
+        return false;
+      }
+
+      MCSection *CS = getStreamer().getCurrentSectionOnly();
+      MCSection *Lit4Section = getContext().getELFSection(
+          ".lit4", ELF::SHT_PROGBITS,
+          ELF::SHF_ALLOC | ELF::SHF_WRITE | ELF::SHF_MIPS_GPREL);
+      getStreamer().SwitchSection(Lit4Section);
+      getStreamer().EmitIntValue(ImmOp32, 4);
+      getStreamer().SwitchSection(CS);
+
+      MCSymbolELF *Sym = getContext().getOrCreateSectionSymbol(
+          *(dyn_cast<MCSectionELF>(Lit4Section)));
+
+      const MCExpr *LitSym =
+          MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, getContext());
+
+      const MipsMCExpr *LitExpr =
+          MipsMCExpr::create(MipsMCExpr::MEK_LITERAL, LitSym, getContext());
+
+      int32_t size_data_fragment = 0;
+      MCSection::FragmentListType &FragList = Lit4Section->getFragmentList();
+      if (!FragList.empty()) {
+        MCDataFragment *DF =
+            &cast<MCDataFragment>(Lit4Section->getFragmentList().back());
+        size_data_fragment = DF->getContents().size();
+      }
+
+      const MCExpr *FixupAddr = MCBinaryExpr::createAdd(
+          LitExpr, MCConstantExpr::create(size_data_fragment - 4, getContext()),
+          getContext());
+
+     TOut.emitRRX(Mips::LWC1, FirstReg, Mips::GP,
+                   MCOperand::createExpr(FixupAddr), IDLoc, STI);
+
+      return false;
+    }
+    return false;
+  }
+
+  // if(!IsSingle)
+  if (IsGPR) {
+    unsigned ATReg = getATReg(IDLoc);
+    if (!ATReg)
+      return true;
+
+    if (LoImmOp64 == 0) {
+      if (loadImmediate(HiImmOp64, FirstReg, Mips::NoRegister, true, true,
+                        IDLoc, Out, STI))
+        return true;
+
+      if (loadImmediate(0, FirstReg + 1, Mips::NoRegister, true, true, IDLoc,
+                        Out, STI))
+        return true;
+      return false;
+    }
+
+    MCSection *CS = getStreamer().getCurrentSectionOnly();
+    MCSection *ReadOnlySection = getContext().getELFSection(
+        ".rodata", ELF::SHT_PROGBITS, ELF::SHF_ALLOC);
+    getStreamer().SwitchSection(ReadOnlySection);
+    getStreamer().EmitIntValue(HiImmOp64, 4);
+    getStreamer().EmitIntValue(LoImmOp64, 4);
+    getStreamer().SwitchSection(CS);
+
+    int32_t size_data_fragment = 0;
+    MCSection::FragmentListType &FragList = ReadOnlySection->getFragmentList();
+    if (!FragList.empty()) {
+      MCDataFragment *DF =
+          &cast<MCDataFragment>(ReadOnlySection->getFragmentList().back());
+      size_data_fragment = DF->getContents().size();
+    }
+
+    MCSymbolELF *Sym = getContext().getOrCreateSectionSymbol(
+        *(dyn_cast<MCSectionELF>(ReadOnlySection)));
+
+    const MCExpr *HiSym =
+        MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, getContext());
+
+    const MipsMCExpr *HiExpr =
+        MipsMCExpr::create(MipsMCExpr::MEK_HI, HiSym, getContext());
+
+    const MCExpr *LoSym =
+        MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, getContext());
+
+    const MipsMCExpr *LoExpr =
+        MipsMCExpr::create(MipsMCExpr::MEK_LO, LoSym, getContext());
+
+    TOut.emitRX(Mips::LUi, ATReg, MCOperand::createExpr(HiExpr), IDLoc, STI);
+
+    const MCExpr *FixupAddr = MCBinaryExpr::createAdd(
+        LoExpr, MCConstantExpr::create(size_data_fragment - 8, getContext()),
+        getContext());
+
+    TOut.emitRRX(Mips::LW, FirstReg, ATReg, MCOperand::createExpr(FixupAddr),
+                 IDLoc, STI);
+
+    FixupAddr = MCBinaryExpr::createAdd(
+        LoExpr, MCConstantExpr::create(size_data_fragment - 4, getContext()),
+        getContext());
+
+    TOut.emitRRX(Mips::LW, FirstReg + 1, ATReg,
+                 MCOperand::createExpr(FixupAddr), IDLoc, STI);
+
+    return false;
+  } else { // if(!IsGPR && !IsSingle)
+
+    if (LoImmOp64 == 0) {
+      unsigned ATReg = getATReg(IDLoc);
+      if (!ATReg)
+        return true;
+      if (!Is64FPU) {
+        if (loadImmediate(HiImmOp64, ATReg, Mips::NoRegister, true, true, IDLoc,
+                          Out, STI))
+          return true;
+
+        TOut.emitRRR(Mips::MTHC1_D32, FirstReg, FirstReg, ATReg, IDLoc, STI);
+        TOut.emitRR(Mips::MTC1, FirstReg, Mips::ZERO, IDLoc, STI);
+
+        // TOut.emitRR(Mips::MTC1, FirstReg + 1, ATReg, IDLoc, STI);
+        // TOut.emitRR(Mips::MTC1, FirstReg, Mips::ZERO, IDLoc, STI);
+        return false;
+      }
+    }
+
+    MCSection *CS = getStreamer().getCurrentSectionOnly();
+    MCSection *Lit8Section = getContext().getELFSection(
+        ".lit8", ELF::SHT_PROGBITS,
+        ELF::SHF_ALLOC | ELF::SHF_WRITE | ELF::SHF_MIPS_GPREL);
+
+    getStreamer().SwitchSection(Lit8Section);
+    getStreamer().EmitIntValue(HiImmOp64, 4);
+    getStreamer().EmitIntValue(LoImmOp64, 4);
+    getStreamer().SwitchSection(CS);
+
+    int32_t size_data_fragment = 0;
+    MCSection::FragmentListType &FragList = Lit8Section->getFragmentList();
+    if (!FragList.empty()) {
+      MCDataFragment *DF =
+          &cast<MCDataFragment>(Lit8Section->getFragmentList().back());
+      size_data_fragment = DF->getContents().size();
+    }
+
+    MCSymbolELF *Sym = getContext().getOrCreateSectionSymbol(
+        *(dyn_cast<MCSectionELF>(Lit8Section)));
+
+    const MCExpr *LitSym =
+        MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, getContext());
+
+    const MipsMCExpr *LitExpr =
+        MipsMCExpr::create(MipsMCExpr::MEK_LITERAL, LitSym, getContext());
+
+    const MCExpr *FixupAddr = MCBinaryExpr::createAdd(
+        LitExpr, MCConstantExpr::create(size_data_fragment - 8, getContext()),
+        getContext());
+
+    TOut.emitRRX(Mips::LDC1, FirstReg, Mips::GP,
+                 MCOperand::createExpr(FixupAddr), IDLoc, STI);
+  }
+  return false;
+}
+
 bool MipsAsmParser::expandUncondBranchMMPseudo(MCInst &Inst, SMLoc IDLoc,
                                                MCStreamer &Out,
                                                const MCSubtargetInfo *STI) {
   MipsTargetStreamer &TOut = getTargetStreamer();
 
   assert(getInstDesc(Inst.getOpcode()).getNumOperands() == 1 &&
          "unexpected number of operands");
 
   MCOperand Offset = Inst.getOperand(0);
   if (Offset.isExpr()) {
     Inst.clear();
     Inst.setOpcode(Mips::BEQ_MM);
     Inst.addOperand(MCOperand::createReg(Mips::ZERO));
     Inst.addOperand(MCOperand::createReg(Mips::ZERO));
     Inst.addOperand(MCOperand::createExpr(Offset.getExpr()));
   } else {
     assert(Offset.isImm() && "expected immediate operand kind");
     if (isInt<11>(Offset.getImm())) {
       // If offset fits into 11 bits then this instruction becomes microMIPS
       // 16-bit unconditional branch instruction.
       if (inMicroMipsMode())
         Inst.setOpcode(hasMips32r6() ? Mips::BC16_MMR6 : Mips::B16_MM);
     } else {
       if (!isInt<17>(Offset.getImm()))
         return Error(IDLoc, "branch target out of range");
       if (OffsetToAlignment(Offset.getImm(), 1LL << 1))
         return Error(IDLoc, "branch to misaligned address");
       Inst.clear();
       Inst.setOpcode(Mips::BEQ_MM);
       Inst.addOperand(MCOperand::createReg(Mips::ZERO));
       Inst.addOperand(MCOperand::createReg(Mips::ZERO));
       Inst.addOperand(MCOperand::createImm(Offset.getImm()));
     }
   }
   Out.EmitInstruction(Inst, *STI);
 
   // If .set reorder is active and branch instruction has a delay slot,
   // emit a NOP after it.
   const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
   if (MCID.hasDelaySlot() && AssemblerOptions.back()->isReorder())
     TOut.emitEmptyDelaySlot(true, IDLoc, STI);
 
   return false;
 }
 
 bool MipsAsmParser::expandBranchImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
                                     const MCSubtargetInfo *STI) {
   MipsTargetStreamer &TOut = getTargetStreamer();
   const MCOperand &DstRegOp = Inst.getOperand(0);
   assert(DstRegOp.isReg() && "expected register operand kind");
 
   const MCOperand &ImmOp = Inst.getOperand(1);
   assert(ImmOp.isImm() && "expected immediate operand kind");
 
   const MCOperand &MemOffsetOp = Inst.getOperand(2);
   assert((MemOffsetOp.isImm() || MemOffsetOp.isExpr()) &&
          "expected immediate or expression operand");
 
   unsigned OpCode = 0;
   switch(Inst.getOpcode()) {
     case Mips::BneImm:
       OpCode = Mips::BNE;
       break;
     case Mips::BeqImm:
       OpCode = Mips::BEQ;
       break;
     default:
       llvm_unreachable("Unknown immediate branch pseudo-instruction.");
       break;
   }

lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp

case FK_GPRel_4:
     if (isN64()) {
       unsigned Type = (unsigned)ELF::R_MIPS_NONE;
       Type = setRType((unsigned)ELF::R_MIPS_GPREL32, Type);
       Type = setRType2((unsigned)ELF::R_MIPS_64, Type);
       Type = setRType3((unsigned)ELF::R_MIPS_NONE, Type);
       return Type;
     }
     return ELF::R_MIPS_GPREL32;
+  case Mips::fixup_Mips_LITERAL:
+    return ELF::R_MIPS_LITERAL;
   case Mips::fixup_Mips_GPREL16:
     return ELF::R_MIPS_GPREL16;
   case Mips::fixup_Mips_26:
     return ELF::R_MIPS_26;
   case Mips::fixup_Mips_CALL16:
     return ELF::R_MIPS_CALL16;
   case Mips::fixup_Mips_GOT:
     return ELF::R_MIPS_GOT16;

lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp

case MipsMCExpr::MEK_GOT_PAGE:
       break;
     case MipsMCExpr::MEK_GOT_OFST:
       FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT_OFST
                                    : Mips::fixup_Mips_GOT_OFST;
       break;
     case MipsMCExpr::MEK_GPREL:
       FixupKind = Mips::fixup_Mips_GPREL16;
       break;
+
     case MipsMCExpr::MEK_LO: {
       // Check for %lo(%neg(%gp_rel(X)))
       if (MipsExpr->isGpOff()) {
         FixupKind = Mips::fixup_Mips_GPOFF_LO;
         break;
       }
       FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_LO16
                                    : Mips::fixup_Mips_LO16;
       break;
     }
+    case MipsMCExpr::MEK_LITERAL:
+      FixupKind = Mips::fixup_Mips_LITERAL;
+      break;
     case MipsMCExpr::MEK_HIGHEST:
       FixupKind = Mips::fixup_Mips_HIGHEST;
       break;
     case MipsMCExpr::MEK_HIGHER:
       FixupKind = Mips::fixup_Mips_HIGHER;
       break;
     case MipsMCExpr::MEK_HI:
       // Check for %hi(%neg(%gp_rel(X)))

lib/Target/Mips/MCTargetDesc/MipsMCExpr.h

enum MipsExprKind {
     MEK_GOT_HI16,
     MEK_GOT_LO16,
     MEK_GOT_OFST,
     MEK_GOT_PAGE,
     MEK_GPREL,
     MEK_HI,
     MEK_HIGHER,
     MEK_HIGHEST,
+    MEK_LITERAL,
     MEK_LO,
     MEK_NEG,
     MEK_PCREL_HI16,
     MEK_PCREL_LO16,
     MEK_TLSGD,
     MEK_TLSLDM,
     MEK_TPREL_HI,
     MEK_TPREL_LO,

lib/Target/Mips/MCTargetDesc/MipsMCExpr.cpp

case MEK_HI:
     OS << "%hi";
     break;
   case MEK_HIGHER:
     OS << "%higher";
     break;
   case MEK_HIGHEST:
     OS << "%highest";
     break;
+  case MEK_LITERAL:
+    OS << "%lit4";
+    break;
   case MEK_LO:
     OS << "%lo";
     break;
   case MEK_NEG:
     OS << "%neg";
     break;
   case MEK_PCREL_HI16:
     OS << "%pcrel_hi";
if (Res.isAbsolute() && Fixup == nullptr) {
     case MEK_GOT_LO16:
     case MEK_GOT_OFST:
     case MEK_GOT_PAGE:
     case MEK_GPREL:
     case MEK_PCREL_HI16:
     case MEK_PCREL_LO16:
     case MEK_TLSGD:
     case MEK_TLSLDM:
+    case MEK_LITERAL:
     case MEK_TPREL_HI:
     case MEK_TPREL_LO:
       return false;
     case MEK_LO:
     case MEK_CALL_LO16:
       AbsVal = SignExtend64<16>(AbsVal);
       break;
     case MEK_CALL_HI16:
void MipsMCExpr::fixELFSymbolsInTLSFixups(MCAssembler &Asm) const {
   case MEK_GOT_HI16:
   case MEK_GOT_LO16:
   case MEK_GOT_OFST:
   case MEK_GOT_PAGE:
   case MEK_GPREL:
   case MEK_HI:
   case MEK_HIGHER:
   case MEK_HIGHEST:
+  case MEK_LITERAL:
   case MEK_LO:
   case MEK_NEG:
   case MEK_PCREL_HI16:
   case MEK_PCREL_LO16:
   case MEK_TLSLDM:
     // If we do have nested target-specific expressions, they will be in
     // a consecutive chain.
     if (const MipsMCExpr *E = dyn_cast<const MipsMCExpr>(getSubExpr()))

lib/Target/Mips/MipsInstrFPU.td

def FCMP_S32 : MMRel, CEQS_FT<"s", FGR32, II_C_CC_S, MipsFPCmp>, CEQS_FM<16>,
                  ISA_MIPS1_NOT_32R6_64R6;
   def FCMP_D32 : MMRel, CEQS_FT<"d", AFGR64, II_C_CC_D, MipsFPCmp>, CEQS_FM<17>,
                  ISA_MIPS1_NOT_32R6_64R6, FGR_32;
 }
 let DecoderNamespace = "Mips64" in
 def FCMP_D64 : CEQS_FT<"d", FGR64, II_C_CC_D, MipsFPCmp>, CEQS_FM<17>,
                ISA_MIPS1_NOT_32R6_64R6, FGR_64;
 
 //===----------------------------------------------------------------------===//
 // Floating Point Pseudo-Instructions
 //===----------------------------------------------------------------------===//
 
 // This pseudo instr gets expanded into 2 mtc1 instrs after register
 // allocation.
 class BuildPairF64Base<RegisterOperand RO> :
   PseudoSE<(outs RO:$dst), (ins GPR32Opnd:$lo, GPR32Opnd:$hi),
            [(set RO:$dst, (MipsBuildPairF64 GPR32Opnd:$lo, GPR32Opnd:$hi))],
            II_MTC1>;
 
 def BuildPairF64 : BuildPairF64Base<AFGR64Opnd>, FGR_32, HARDFLOAT;
 def BuildPairF64_64 : BuildPairF64Base<FGR64Opnd>, FGR_64, HARDFLOAT;
 
 // This pseudo instr gets expanded into 2 mfc1 instrs after register
 // allocation.
 // if n is 0, lower part of src is extracted.
 // if n is 1, higher part of src is extracted.
 // This node has associated scheduling information as the pre RA scheduler
 // asserts otherwise.
 class ExtractElementF64Base<RegisterOperand RO> :
   PseudoSE<(outs GPR32Opnd:$dst), (ins RO:$src, i32imm:$n),
            [(set GPR32Opnd:$dst, (MipsExtractElementF64 RO:$src, imm:$n))],
            II_MFC1>;
 
 def ExtractElementF64 : ExtractElementF64Base<AFGR64Opnd>, FGR_32, HARDFLOAT;
 def ExtractElementF64_64 : ExtractElementF64Base<FGR64Opnd>, FGR_64, HARDFLOAT;
 
 def PseudoTRUNC_W_S : MipsAsmPseudoInst<(outs FGR32Opnd:$fd),
                                         (ins FGR32Opnd:$fs, GPR32Opnd:$rs),
                                         "trunc.w.s\t$fd, $fs, $rs">;
 
 def PseudoTRUNC_W_D32 : MipsAsmPseudoInst<(outs FGR32Opnd:$fd),
                                           (ins AFGR64Opnd:$fs, GPR32Opnd:$rs),
                                           "trunc.w.d\t$fd, $fs, $rs">,
                         FGR_32, HARDFLOAT;
 
 def PseudoTRUNC_W_D : MipsAsmPseudoInst<(outs FGR32Opnd:$fd),
                                         (ins FGR64Opnd:$fs, GPR32Opnd:$rs),
                                         "trunc.w.d\t$fd, $fs, $rs">,
                       FGR_64, HARDFLOAT;
 
+def LoadImmSingleGPR : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),
+                                         (ins imm64:$fpimm),
+                                         "li.s\t$rd, $fpimm">;
+
+def LoadImmSingleFGR : MipsAsmPseudoInst<(outs StrictlyFGR32Opnd:$rd),
+                                         (ins imm64:$fpimm),
+                                         "li.s\t$rd, $fpimm">;
+
+def LoadImmDoubleGPR : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),
+                                         (ins imm64:$fpimm),
+                                         "li.d\t$rd, $fpimm">;
+
+def LoadImmDoubleFGR_32 : MipsAsmPseudoInst<(outs StrictlyAFGR64Opnd:$rd),
+                                            (ins imm64:$fpimm),
+                                            "li.d\t$rd, $fpimm">,
+                          FGR_32, HARDFLOAT;
+
+def LoadImmDoubleFGR : MipsAsmPseudoInst<(outs StrictlyFGR64Opnd:$rd),
+                                         (ins imm64:$fpimm),
+                                         "li.d\t$rd, $fpimm">,
+                       FGR_64, HARDFLOAT;
+
 //===----------------------------------------------------------------------===//
 // InstAliases.
 //===----------------------------------------------------------------------===//
 def : MipsInstAlias<"bc1t $offset", (BC1T FCC0, brtarget:$offset)>,
       ISA_MIPS1_NOT_32R6_64R6, HARDFLOAT;
 def : MipsInstAlias<"bc1tl $offset", (BC1TL FCC0, brtarget:$offset)>,
       ISA_MIPS2_NOT_32R6_64R6, HARDFLOAT;
 def : MipsInstAlias<"bc1f $offset", (BC1F FCC0, brtarget:$offset)>,

lib/Target/Mips/MipsRegisterInfo.td

def CCRAsmOperand : MipsAsmRegOperand {
   let Name = "CCRAsmReg";
 }
 
 def AFGR64AsmOperand : MipsAsmRegOperand {
   let Name = "AFGR64AsmReg";
   let PredicateMethod = "isFGRAsmReg";
 }
 
+def StrictlyAFGR64AsmOperand : MipsAsmRegOperand {
+  let Name = "StrictlyAFGR64AsmReg";
+  let PredicateMethod = "isStrictlyFGRAsmReg";
+}
+
 def FGR64AsmOperand : MipsAsmRegOperand {
   let Name = "FGR64AsmReg";
   let PredicateMethod = "isFGRAsmReg";
 }
 
+def StrictlyFGR64AsmOperand : MipsAsmRegOperand {
+  let Name = "StrictlyFGR64AsmReg";
+  let PredicateMethod = "isStrictlyFGRAsmReg";
+}
+
 def FGR32AsmOperand : MipsAsmRegOperand {
   let Name = "FGR32AsmReg";
   let PredicateMethod = "isFGRAsmReg";
 }
 
+def StrictlyFGR32AsmOperand : MipsAsmRegOperand {
+  let Name = "StrictlyFGR32AsmReg";
+  let PredicateMethod = "isStrictlyFGRAsmReg";
+}
+
 def FGRH32AsmOperand : MipsAsmRegOperand {
   let Name = "FGRH32AsmReg";
   let PredicateMethod = "isFGRAsmReg";
 }
 
 def FCCRegsAsmOperand : MipsAsmRegOperand {
   let Name = "FCCAsmReg";
 }

 def HWRegsOpnd : RegisterOperand<HWRegs> {
   let ParserMatchClass = HWRegsAsmOperand;
 }
 
 def AFGR64Opnd : RegisterOperand<AFGR64> {
   let ParserMatchClass = AFGR64AsmOperand;
 }
 
+def StrictlyAFGR64Opnd : RegisterOperand<AFGR64> {
+  let ParserMatchClass = StrictlyAFGR64AsmOperand;
+}
+
 def FGR64Opnd : RegisterOperand<FGR64> {
   let ParserMatchClass = FGR64AsmOperand;
 }
 
+def StrictlyFGR64Opnd : RegisterOperand<FGR64> {
+  let ParserMatchClass = StrictlyFGR64AsmOperand;
+}
+
 def FGR32Opnd : RegisterOperand<FGR32> {
   let ParserMatchClass = FGR32AsmOperand;
 }
 
+def StrictlyFGR32Opnd : RegisterOperand<FGR32> {
+  let ParserMatchClass = StrictlyFGR32AsmOperand;
+}
+
 def FGRCCOpnd : RegisterOperand<FGRCC> {
   // The assembler doesn't use register classes so we can re-use
   // FGR32AsmOperand.
   let ParserMatchClass = FGR32AsmOperand;
 }
 
 def FGRH32Opnd : RegisterOperand<FGRH32> {
   let ParserMatchClass = FGRH32AsmOperand;

test/MC/Mips/macro-li.d.s

+# RUN: llvm-mc  %s -triple=mipsel-unknown-linux -mcpu=mips32 -show-encoding | FileCheck %s --check-prefix=CHECK-MIPS32
+# RUN: llvm-mc  %s -triple=mipsel-unknown-linux -mcpu=mips64 -show-encoding | FileCheck %s --check-prefix=CHECK-MIPS64
+
+li.d  $4, 0
+# CHECK-MIPS32:   addiu   $4, $zero, 0                # encoding: [0x00,0x00,0x04,0x24]
+# CHECK-MIPS32:   addiu   $5, $zero, 0                # encoding: [0x00,0x00,0x05,0x24]
+# CHECK-MIPS64:   addiu   $4, $zero, 0                # encoding: [0x00,0x00,0x04,0x24]
+# CHECK-MIPS64:   addiu   $5, $zero, 0                # encoding: [0x00,0x00,0x05,0x24]
+
+li.d  $4, 0.0
+# CHECK-MIPS32:   addiu   $4, $zero, 0                # encoding: [0x00,0x00,0x04,0x24]
+# CHECK-MIPS32:   addiu   $5, $zero, 0                # encoding: [0x00,0x00,0x05,0x24]
+# CHECK-MIPS64:   addiu   $4, $zero, 0                # encoding: [0x00,0x00,0x04,0x24]
+# CHECK-MIPS64:   addiu   $5, $zero, 0                # encoding: [0x00,0x00,0x05,0x24]
+
+li.d  $4, 1.12345
+# CHECK-MIPS32:   .section        .rodata,"a",@progbits
+# CHECK-MIPS32:   .4byte  1072822694
+# CHECK-MIPS32:   .4byte  3037400872
+# CHECK-MIPS32:   .text
+# CHECK-MIPS32:   lui     $1, %hi(.rodata)            # encoding: [A,A,0x01,0x3c]
+# CHECK-MIPS32:                                           #   fixup A - offset: 0, value: %hi(.rodata), kind: fixup_Mips_HI16
+# CHECK-MIPS32:   lw      $4, (%lo(.rodata))-8($1)    # encoding: [0xf8'A',0xff'A',0x24,0x8c]
+# CHECK-MIPS32:                                           #   fixup A - offset: 0, value: %lo(.rodata), kind: fixup_Mips_LO16
+# CHECK-MIPS32:   lw      $5, (%lo(.rodata))-4($1)    # encoding: [0xfc'A',0xff'A',0x25,0x8c]
+# CHECK-MIPS32:                                           #   fixup A - offset: 0, value: %lo(.rodata), kind: fixup_Mips_LO16
+# CHECK-MIPS64:   .section        .rodata,"a",@progbits
+# CHECK-MIPS64:   .4byte  1072822694
+# CHECK-MIPS64:   .4byte  3037400872
+# CHECK-MIPS64:   .text
+# CHECK-MIPS64:   lui     $1, %hi(.rodata)            # encoding: [A,A,0x01,0x3c]
+# CHECK-MIPS64:                                           #   fixup A - offset: 0, value: %hi(.rodata), kind: fixup_Mips_HI16
+# CHECK-MIPS64:   lw      $4, (%lo(.rodata))-8($1)    # encoding: [0xf8'A',0xff'A',0x24,0x8c]
+# CHECK-MIPS64:                                           #   fixup A - offset: 0, value: %lo(.rodata), kind: fixup_Mips_LO16
+# CHECK-MIPS64:   lw      $5, (%lo(.rodata))-4($1)    # encoding: [0xfc'A',0xff'A',0x25,0x8c]
+# CHECK-MIPS64:                                           #   fixup A - offset: 0, value: %lo(.rodata), kind: fixup_Mips_LO16
+
+li.d  $4, 1
+# CHECK-MIPS32:   lui     $4, 16368                   # encoding: [0xf0,0x3f,0x04,0x3c]
+# CHECK-MIPS32:   addiu   $5, $zero, 0                # encoding: [0x00,0x00,0x05,0x24]
+# CHECK-MIPS64:   lui     $4, 16368                   # encoding: [0xf0,0x3f,0x04,0x3c]
+# CHECK-MIPS64:   addiu   $5, $zero, 0                # encoding: [0x00,0x00,0x05,0x24]
+
+li.d  $4, 1.0
+# CHECK-MIPS32:   lui     $4, 16368                   # encoding: [0xf0,0x3f,0x04,0x3c]
+# CHECK-MIPS32:   addiu   $5, $zero, 0                # encoding: [0x00,0x00,0x05,0x24]
+# CHECK-MIPS64:   lui     $4, 16368                   # encoding: [0xf0,0x3f,0x04,0x3c]
+# CHECK-MIPS64:   addiu   $5, $zero, 0                # encoding: [0x00,0x00,0x05,0x24]
+
+li.d  $4, 12345678910
+# CHECK-MIPS32:   .section        .rodata,"a",@progbits
+# CHECK-MIPS32:   .4byte  1107754720
+# CHECK-MIPS32:   .4byte  3790602240
+# CHECK-MIPS32:   .text
+# CHECK-MIPS32:   lui     $1, %hi(.rodata)            # encoding: [A,A,0x01,0x3c]
+# CHECK-MIPS32:                                           #   fixup A - offset: 0, value: %hi(.rodata), kind: fixup_Mips_HI16
+# CHECK-MIPS32:   lw      $4, (%lo(.rodata))-8($1)    # encoding: [0xf8'A',0xff'A',0x24,0x8c]
+# CHECK-MIPS32:                                           #   fixup A - offset: 0, value: %lo(.rodata), kind: fixup_Mips_LO16
+# CHECK-MIPS32:   lw      $5, (%lo(.rodata))-4($1)    # encoding: [0xfc'A',0xff'A',0x25,0x8c]
+# CHECK-MIPS32:                                           #   fixup A - offset: 0, value: %lo(.rodata), kind: fixup_Mips_LO16
+# CHECK-MIPS64:   .section        .rodata,"a",@progbits
+# CHECK-MIPS64:   .4byte  1107754720
+# CHECK-MIPS64:   .4byte  3790602240
+# CHECK-MIPS64:   .text
+# CHECK-MIPS64:   lui     $1, %hi(.rodata)            # encoding: [A,A,0x01,0x3c]
+# CHECK-MIPS64:                                           #   fixup A - offset: 0, value: %hi(.rodata), kind: fixup_Mips_HI16
+# CHECK-MIPS64:   lw      $4, (%lo(.rodata))-8($1)    # encoding: [0xf8'A',0xff'A',0x24,0x8c]
+# CHECK-MIPS64:                                           #   fixup A - offset: 0, value: %lo(.rodata), kind: fixup_Mips_LO16
+# CHECK-MIPS64:   lw      $5, (%lo(.rodata))-4($1)    # encoding: [0xfc'A',0xff'A',0x25,0x8c]
+# CHECK-MIPS64:                                           #   fixup A - offset: 0, value: %lo(.rodata), kind: fixup_Mips_LO16
+
+li.d  $4, 12345678910.0
+# CHECK-MIPS32:   .section        .rodata,"a",@progbits
+# CHECK-MIPS32:   .4byte  1107754720
+# CHECK-MIPS32:   .4byte  3790602240
+# CHECK-MIPS32:   .text
+# CHECK-MIPS32:   lui     $1, %hi(.rodata)            # encoding: [A,A,0x01,0x3c]
+# CHECK-MIPS32:                                           #   fixup A - offset: 0, value: %hi(.rodata), kind: fixup_Mips_HI16
+# CHECK-MIPS32:   lw      $4, (%lo(.rodata))-8($1)    # encoding: [0xf8'A',0xff'A',0x24,0x8c]
+# CHECK-MIPS32:                                           #   fixup A - offset: 0, value: %lo(.rodata), kind: fixup_Mips_LO16
+# CHECK-MIPS32:   lw      $5, (%lo(.rodata))-4($1)    # encoding: [0xfc'A',0xff'A',0x25,0x8c]
+# CHECK-MIPS32:                                           #   fixup A - offset: 0, value: %lo(.rodata), kind: fixup_Mips_LO16
+# CHECK-MIPS64:   .section        .rodata,"a",@progbits
+# CHECK-MIPS64:   .4byte  1107754720
+# CHECK-MIPS64:   .4byte  3790602240
+# CHECK-MIPS64:   .text
+# CHECK-MIPS64:   lui     $1, %hi(.rodata)            # encoding: [A,A,0x01,0x3c]
+# CHECK-MIPS64:                                           #   fixup A - offset: 0, value: %hi(.rodata), kind: fixup_Mips_HI16
+# CHECK-MIPS64:   lw      $4, (%lo(.rodata))-8($1)    # encoding: [0xf8'A',0xff'A',0x24,0x8c]
+# CHECK-MIPS64:                                           #   fixup A - offset: 0, value: %lo(.rodata), kind: fixup_Mips_LO16
+# CHECK-MIPS64:   lw      $5, (%lo(.rodata))-4($1)    # encoding: [0xfc'A',0xff'A',0x25,0x8c]
+# CHECK-MIPS64:                                           #   fixup A - offset: 0, value: %lo(.rodata), kind: fixup_Mips_LO16
+
+li.d  $4, 0.4
+# CHECK-MIPS32:   .section        .rodata,"a",@progbits
+# CHECK-MIPS32:   .4byte  1071225241
+# CHECK-MIPS32:   .4byte  2576980378
+# CHECK-MIPS32:   .text
+# CHECK-MIPS32:   lui     $1, %hi(.rodata)            # encoding: [A,A,0x01,0x3c]
+# CHECK-MIPS32:                                           #   fixup A - offset: 0, value: %hi(.rodata), kind: fixup_Mips_HI16
+# CHECK-MIPS32:   lw      $4, (%lo(.rodata))-8($1)    # encoding: [0xf8'A',0xff'A',0x24,0x8c]
+# CHECK-MIPS32:                                           #   fixup A - offset: 0, value: %lo(.rodata), kind: fixup_Mips_LO16
+# CHECK-MIPS32:   lw      $5, (%lo(.rodata))-4($1)    # encoding: [0xfc'A',0xff'A',0x25,0x8c]
+# CHECK-MIPS32:                                           #   fixup A - offset: 0, value: %lo(.rodata), kind: fixup_Mips_LO16
+# CHECK-MIPS64:   .section        .rodata,"a",@progbits
+# CHECK-MIPS64:   .4byte  1071225241
+# CHECK-MIPS64:   .4byte  2576980378
+# CHECK-MIPS64:   .text
+# CHECK-MIPS64:   lui     $1, %hi(.rodata)            # encoding: [A,A,0x01,0x3c]
+# CHECK-MIPS64:                                           #   fixup A - offset: 0, value: %hi(.rodata), kind: fixup_Mips_HI16
+# CHECK-MIPS64:   lw      $4, (%lo(.rodata))-8($1)    # encoding: [0xf8'A',0xff'A',0x24,0x8c]
+# CHECK-MIPS64:                                           #   fixup A - offset: 0, value: %lo(.rodata), kind: fixup_Mips_LO16
+# CHECK-MIPS64:   lw      $5, (%lo(.rodata))-4($1)    # encoding: [0xfc'A',0xff'A',0x25,0x8c]
+# CHECK-MIPS64:                                           #   fixup A - offset: 0, value: %lo(.rodata), kind: fixup_Mips_LO16
+
+li.d  $4, 1.5 
+# CHECK-MIPS32:   lui     $4, 16376                   # encoding: [0xf8,0x3f,0x04,0x3c]
+# CHECK-MIPS32:   addiu   $5, $zero, 0                # encoding: [0x00,0x00,0x05,0x24]
+# CHECK-MIPS64:   lui     $4, 16376                   # encoding: [0xf8,0x3f,0x04,0x3c]
+# CHECK-MIPS64:   addiu   $5, $zero, 0                # encoding: [0x00,0x00,0x05,0x24]
+
+li.d  $4, 12345678910.12345678910
+# CHECK-MIPS32:   .section        .rodata,"a",@progbits
+# CHECK-MIPS32:   .4byte  1107754720
+# CHECK-MIPS32:   .4byte  3790666967
+# CHECK-MIPS32:   .text
+# CHECK-MIPS32:   lui     $1, %hi(.rodata)            # encoding: [A,A,0x01,0x3c]
+# CHECK-MIPS32:                                           #   fixup A - offset: 0, value: %hi(.rodata), kind: fixup_Mips_HI16
+# CHECK-MIPS32:   lw      $4, (%lo(.rodata))-8($1)    # encoding: [0xf8'A',0xff'A',0x24,0x8c]
+# CHECK-MIPS32:                                           #   fixup A - offset: 0, value: %lo(.rodata), kind: fixup_Mips_LO16
+# CHECK-MIPS32:   lw      $5, (%lo(.rodata))-4($1)    # encoding: [0xfc'A',0xff'A',0x25,0x8c]
+# CHECK-MIPS32:                                           #   fixup A - offset: 0, value: %lo(.rodata), kind: fixup_Mips_LO16
+# CHECK-MIPS64:   .section        .rodata,"a",@progbits
+# CHECK-MIPS64:   .4byte  1107754720
+# CHECK-MIPS64:   .4byte  3790666967
+# CHECK-MIPS64:   .text
+# CHECK-MIPS64:   lui     $1, %hi(.rodata)            # encoding: [A,A,0x01,0x3c]
+# CHECK-MIPS64:                                           #   fixup A - offset: 0, value: %hi(.rodata), kind: fixup_Mips_HI16
+# CHECK-MIPS64:   lw      $4, (%lo(.rodata))-8($1)    # encoding: [0xf8'A',0xff'A',0x24,0x8c]
+# CHECK-MIPS64:                                           #   fixup A - offset: 0, value: %lo(.rodata), kind: fixup_Mips_LO16
+# CHECK-MIPS64:   lw      $5, (%lo(.rodata))-4($1)    # encoding: [0xfc'A',0xff'A',0x25,0x8c]
+# CHECK-MIPS64:                                           #   fixup A - offset: 0, value: %lo(.rodata), kind: fixup_Mips_LO16
+
+li.d  $4, 12345678910123456789.12345678910
+# CHECK-MIPS32:   .section        .rodata,"a",@progbits
+# CHECK-MIPS32:   .4byte  1139108501
+# CHECK-MIPS32:   .4byte  836738583
+# CHECK-MIPS32:   .text
+# CHECK-MIPS32:   lui     $1, %hi(.rodata)            # encoding: [A,A,0x01,0x3c]
+# CHECK-MIPS32:                                           #   fixup A - offset: 0, value: %hi(.rodata), kind: fixup_Mips_HI16
+# CHECK-MIPS32:   lw      $4, (%lo(.rodata))-8($1)    # encoding: [0xf8'A',0xff'A',0x24,0x8c]
+# CHECK-MIPS32:                                           #   fixup A - offset: 0, value: %lo(.rodata), kind: fixup_Mips_LO16
+# CHECK-MIPS32:   lw      $5, (%lo(.rodata))-4($1)    # encoding: [0xfc'A',0xff'A',0x25,0x8c]
+# CHECK-MIPS32:                                           #   fixup A - offset: 0, value: %lo(.rodata), kind: fixup_Mips_LO16
+# CHECK-MIPS64:   .section        .rodata,"a",@progbits
+# CHECK-MIPS64:   .4byte  1139108501
+# CHECK-MIPS64:   .4byte  836738583
+# CHECK-MIPS64:   .text
+# CHECK-MIPS64:   lui     $1, %hi(.rodata)            # encoding: [A,A,0x01,0x3c]
+# CHECK-MIPS64:                                           #   fixup A - offset: 0, value: %hi(.rodata), kind: fixup_Mips_HI16
+# CHECK-MIPS64:   lw      $4, (%lo(.rodata))-8($1)    # encoding: [0xf8'A',0xff'A',0x24,0x8c]
+# CHECK-MIPS64:                                           #   fixup A - offset: 0, value: %lo(.rodata), kind: fixup_Mips_LO16
+# CHECK-MIPS64:   lw      $5, (%lo(.rodata))-4($1)    # encoding: [0xfc'A',0xff'A',0x25,0x8c]
+# CHECK-MIPS64:                                           #   fixup A - offset: 0, value: %lo(.rodata), kind: fixup_Mips_LO16
+
+li.d  $f4, 0
+# CHECK-MIPS32:   addiu   $1, $zero, 0                # encoding: [0x00,0x00,0x01,0x24]
+# CHECK-MIPS32:   mthc1   $1, $f4                     # encoding: [0x00,0x20,0xe1,0x44]
+# CHECK-MIPS32:   mtc1    $zero, $f4                  # encoding: [0x00,0x20,0x80,0x44]
+# CHECK-MIPS64:   .section        .lit8,"aw",@progbits
+# CHECK-MIPS64:   .4byte  0
+# CHECK-MIPS64:   .4byte  0
+# CHECK-MIPS64:   .text
+# CHECK-MIPS64:   ldc1    $f4, (%lit4(.lit8))-8($gp)  # encoding: [0xf8'A',0xff'A',0x84,0xd7]
+# CHECK-MIPS64:                                           #   fixup A - offset: 0, value: %lit4(.lit8), kind: fixup_Mips_LITERAL
+
+
+li.d  $f4, 0.0
+# CHECK-MIPS32:   addiu   $1, $zero, 0                # encoding: [0x00,0x00,0x01,0x24]
+# CHECK-MIPS32:   mthc1   $1, $f4                     # encoding: [0x00,0x20,0xe1,0x44]
+# CHECK-MIPS32:   mtc1    $zero, $f4                  # encoding: [0x00,0x20,0x80,0x44]
+# CHECK-MIPS64:   .section        .lit8,"aw",@progbits
+# CHECK-MIPS64:   .4byte  0
+# CHECK-MIPS64:   .4byte  0
+# CHECK-MIPS64:   .text
+# CHECK-MIPS64:   ldc1    $f4, (%lit4(.lit8))-8($gp)  # encoding: [0xf8'A',0xff'A',0x84,0xd7]
+# CHECK-MIPS64:                                           #   fixup A - offset: 0, value: %lit4(.lit8), kind: fixup_Mips_LITERAL
+
+
+li.d  $f4, 1.12345
+# CHECK-MIPS32:   .section        .lit8,"aw",@progbits
+# CHECK-MIPS32:   .4byte  1072822694
+# CHECK-MIPS32:   .4byte  3037400872
+# CHECK-MIPS32:   .text
+# CHECK-MIPS32:   ldc1    $f4, (%lit4(.lit8))-8($gp)  # encoding: [0xf8'A',0xff'A',0x84,0xd7]
+# CHECK-MIPS32:                                           #   fixup A - offset: 0, value: %lit4(.lit8), kind: fixup_Mips_LITERAL
+# CHECK-MIPS64:   .section        .lit8,"aw",@progbits
+# CHECK-MIPS64:   .4byte  1072822694
+# CHECK-MIPS64:   .4byte  3037400872
+# CHECK-MIPS64:   .text
+# CHECK-MIPS64:   ldc1    $f4, (%lit4(.lit8))-8($gp)  # encoding: [0xf8'A',0xff'A',0x84,0xd7]
+# CHECK-MIPS64:                                           #   fixup A - offset: 0, value: %lit4(.lit8), kind: fixup_Mips_LITERAL
+
+li.d  $f4, 1
+# CHECK-MIPS32:   lui     $1, 16368                   # encoding: [0xf0,0x3f,0x01,0x3c]
+# CHECK-MIPS32:   mthc1   $1, $f4                     # encoding: [0x00,0x20,0xe1,0x44]
+# CHECK-MIPS32:   mtc1    $zero, $f4                  # encoding: [0x00,0x20,0x80,0x44]
+# CHECK-MIPS64:   .section        .lit8,"aw",@progbits
+# CHECK-MIPS64:   .4byte  1072693248
+# CHECK-MIPS64:   .4byte  0
+# CHECK-MIPS64:   .text
+# CHECK-MIPS64:   ldc1    $f4, (%lit4(.lit8))-8($gp)  # encoding: [0xf8'A',0xff'A',0x84,0xd7]
+# CHECK-MIPS64:                                           #   fixup A - offset: 0, value: %lit4(.lit8), kind: fixup_Mips_LITERAL
+
+li.d  $f4, 1.0
+# CHECK-MIPS32:    lui     $1, 16368                  # encoding: [0xf0,0x3f,0x01,0x3c]
+# CHECK-MIPS32:   mthc1   $1, $f4                     # encoding: [0x00,0x20,0xe1,0x44]
+# CHECK-MIPS32:   mtc1    $zero, $f4                  # encoding: [0x00,0x20,0x80,0x44]
+# CHECK-MIPS64:   .section        .lit8,"aw",@progbits
+# CHECK-MIPS64:   .4byte  1072693248
+# CHECK-MIPS64:   .4byte  0
+# CHECK-MIPS64:   .text
+# CHECK-MIPS64:   ldc1    $f4, (%lit4(.lit8))-8($gp)  # encoding: [0xf8'A',0xff'A',0x84,0xd7]
+# CHECK-MIPS64:                                           #   fixup A - offset: 0, value: %lit4(.lit8), kind: fixup_Mips_LITERAL
+
+li.d  $f4, 12345678910
+# CHECK-MIPS32:   .section        .lit8,"aw",@progbits
+# CHECK-MIPS32:   .4byte  1107754720
+# CHECK-MIPS32:   .4byte  3790602240
+# CHECK-MIPS32:   .text
+# CHECK-MIPS32:   ldc1    $f4, (%lit4(.lit8))-8($gp)  # encoding: [0xf8'A',0xff'A',0x84,0xd7]
+# CHECK-MIPS32:                                           #   fixup A - offset: 0, value: %lit4(.lit8), kind: fixup_Mips_LITERAL
+# CHECK-MIPS64:   .section        .lit8,"aw",@progbits
+# CHECK-MIPS64:   .4byte  1107754720
+# CHECK-MIPS64:   .4byte  3790602240
+# CHECK-MIPS64:   .text
+# CHECK-MIPS64:   ldc1    $f4, (%lit4(.lit8))-8($gp)  # encoding: [0xf8'A',0xff'A',0x84,0xd7]
+# CHECK-MIPS64:                                           #   fixup A - offset: 0, value: %lit4(.lit8), kind: fixup_Mips_LITERAL
+
+li.d  $f4, 12345678910.0
+# CHECK-MIPS32:   .section        .lit8,"aw",@progbits
+# CHECK-MIPS32:   .4byte  1107754720
+# CHECK-MIPS32:   .4byte  3790602240
+# CHECK-MIPS32:   .text
+# CHECK-MIPS32:   ldc1    $f4, (%lit4(.lit8))-8($gp)  # encoding: [0xf8'A',0xff'A',0x84,0xd7]
+# CHECK-MIPS32:                                           #   fixup A - offset: 0, value: %lit4(.lit8), kind: fixup_Mips_LITERAL
+# CHECK-MIPS64:   .section        .lit8,"aw",@progbits
+# CHECK-MIPS64:   .4byte  1107754720
+# CHECK-MIPS64:   .4byte  3790602240
+# CHECK-MIPS64:   .text
+# CHECK-MIPS64:   ldc1    $f4, (%lit4(.lit8))-8($gp)  # encoding: [0xf8'A',0xff'A',0x84,0xd7]
+# CHECK-MIPS64:                                           #   fixup A - offset: 0, value: %lit4(.lit8), kind: fixup_Mips_LITERAL
+
+li.d  $f4, 0.4
+# CHECK-MIPS32:   .section        .lit8,"aw",@progbits
+# CHECK-MIPS32:   .4byte  1071225241
+# CHECK-MIPS32:   .4byte  2576980378
+# CHECK-MIPS32:   .text
+# CHECK-MIPS32:   ldc1    $f4, (%lit4(.lit8))-8($gp)  # encoding: [0xf8'A',0xff'A',0x84,0xd7]
+# CHECK-MIPS32:                                           #   fixup A - offset: 0, value: %lit4(.lit8), kind: fixup_Mips_LITERAL
+# CHECK-MIPS64:   .section        .lit8,"aw",@progbits
+# CHECK-MIPS64:   .4byte  1071225241
+# CHECK-MIPS64:   .4byte  2576980378
+# CHECK-MIPS64:   .text
+# CHECK-MIPS64:   ldc1    $f4, (%lit4(.lit8))-8($gp)  # encoding: [0xf8'A',0xff'A',0x84,0xd7]
+# CHECK-MIPS64:                                           #   fixup A - offset: 0, value: %lit4(.lit8), kind: fixup_Mips_LITERAL
+
+li.d  $f4, 1.5 
+# CHECK-MIPS32:   lui     $1, 16376                   # encoding: [0xf8,0x3f,0x01,0x3c]
+# CHECK-MIPS32:   mthc1   $1, $f4                     # encoding: [0x00,0x20,0xe1,0x44]
+# CHECK-MIPS32:   mtc1    $zero, $f4                  # encoding: [0x00,0x20,0x80,0x44]
+# CHECK-MIPS64:   .section        .lit8,"aw",@progbits
+# CHECK-MIPS64:   .4byte  1073217536
+# CHECK-MIPS64:   .4byte  0
+# CHECK-MIPS64:   .text
+# CHECK-MIPS64:   ldc1    $f4, (%lit4(.lit8))-8($gp)  # encoding: [0xf8'A',0xff'A',0x84,0xd7]
+# CHECK-MIPS64:                                           #   fixup A - offset: 0, value: %lit4(.lit8), kind: fixup_Mips_LITERAL
+
+li.d  $f4, 12345678910.12345678910
+# CHECK-MIPS32:   .section        .lit8,"aw",@progbits
+# CHECK-MIPS32:   .4byte  1107754720
+# CHECK-MIPS32:   .4byte  3790666967
+# CHECK-MIPS32:   .text
+# CHECK-MIPS32:   ldc1    $f4, (%lit4(.lit8))-8($gp)  # encoding: [0xf8'A',0xff'A',0x84,0xd7]
+# CHECK-MIPS32:                                           #   fixup A - offset: 0, value: %lit4(.lit8), kind: fixup_Mips_LITERAL
+# CHECK-MIPS64:   .section        .lit8,"aw",@progbits
+# CHECK-MIPS64:   .4byte  1107754720
+# CHECK-MIPS64:   .4byte  3790666967
+# CHECK-MIPS64:   .text
+# CHECK-MIPS64:   ldc1    $f4, (%lit4(.lit8))-8($gp)  # encoding: [0xf8'A',0xff'A',0x84,0xd7]
+# CHECK-MIPS64:                                           #   fixup A - offset: 0, value: %lit4(.lit8), kind: fixup_Mips_LITERAL
+
+li.d  $f4, 12345678910123456789.12345678910
+# CHECK-MIPS32:   .section        .lit8,"aw",@progbits
+# CHECK-MIPS32:   .4byte  1139108501
+# CHECK-MIPS32:   .4byte  836738583
+# CHECK-MIPS32:   .text
+# CHECK-MIPS32:   ldc1    $f4, (%lit4(.lit8))-8($gp)  # encoding: [0xf8'A',0xff'A',0x84,0xd7]
+# CHECK-MIPS32:                                           #   fixup A - offset: 0, value: %lit4(.lit8), kind: fixup_Mips_LITERAL
+# CHECK-MIPS64:    .section        .lit8,"aw",@progbits
+# CHECK-MIPS64:   .4byte  1139108501
+# CHECK-MIPS64:   .4byte  836738583
+# CHECK-MIPS64:   .text
+# CHECK-MIPS64:   ldc1    $f4, (%lit4(.lit8))-8($gp)  # encoding: [0xf8'A',0xff'A',0x84,0xd7]
+# CHECK-MIPS64:                                           #   fixup A - offset: 0, value: %lit4(.lit8), kind: fixup_Mips_LITERAL

test/MC/Mips/macro-li.s.s

+# RUN: llvm-mc  %s -triple=mipsel-unknown-linux -mcpu=mips32 -show-encoding | FileCheck %s
+# RUN: llvm-mc  %s -triple=mipsel-unknown-linux -mcpu=mips64 -show-encoding | FileCheck %s
+
+li.s  $4, 0
+# CHECK:   addiu   $4, $zero, 0                # encoding: [0x00,0x00,0x04,0x24]
+
+li.s  $4, 0.0
+# CHECK:   addiu   $4, $zero, 0                # encoding: [0x00,0x00,0x04,0x24]
+
+li.s  $4, 1.12345
+# CHECK:   lui     $4, 16271                   # encoding: [0x8f,0x3f,0x04,0x3c]
+# CHECK:   ori     $4, $4, 52534               # encoding: [0x36,0xcd,0x84,0x34]
+
+li.s  $4, 1
+# CHECK:   lui     $4, 16256                   # encoding: [0x80,0x3f,0x04,0x3c]
+
+li.s  $4, 1.0
+# CHECK:   lui     $4, 16256                   # encoding: [0x80,0x3f,0x04,0x3c]
+
+li.s  $4, 12345678910
+# CHECK:   lui     $4, 20535                   # encoding: [0x37,0x50,0x04,0x3c]
+# CHECK:   ori     $4, $4, 63239               # encoding: [0x07,0xf7,0x84,0x34]
+
+li.s  $4, 12345678910.0
+# CHECK:   lui     $4, 20535                   # encoding: [0x37,0x50,0x04,0x3c]
+# CHECK:   ori     $4, $4, 63239               # encoding: [0x07,0xf7,0x84,0x34]
+
+li.s  $4, 0.4
+# CHECK:   lui     $4, 16076                   # encoding: [0xcc,0x3e,0x04,0x3c]
+# CHECK:   ori     $4, $4, 52429               # encoding: [0xcd,0xcc,0x84,0x34]
+
+li.s  $4, 1.5 
+# CHECK:   lui     $4, 16320                   # encoding: [0xc0,0x3f,0x04,0x3c]
+
+li.s  $4, 12345678910.12345678910
+# CHECK:   lui     $4, 20535                   # encoding: [0x37,0x50,0x04,0x3c]
+# CHECK:   ori     $4, $4, 63239               # encoding: [0x07,0xf7,0x84,0x34]
+
+li.s  $4, 12345678910123456789.12345678910
+# CHECK:   lui     $4, 24363                   # encoding: [0x2b,0x5f,0x04,0x3c]
+# CHECK:   ori     $4, $4, 21674               # encoding: [0xaa,0x54,0x84,0x34]
+
+li.s  $f4, 0
+# CHECK:   addiu   $1, $zero, 0                # encoding: [0x00,0x00,0x01,0x24]
+# CHECK:   mtc1    $1, $f4                     # encoding: [0x00,0x20,0x81,0x44]
+
+li.s  $f4, 0.0
+# CHECK:   addiu   $1, $zero, 0                # encoding: [0x00,0x00,0x01,0x24]
+# CHECK:   mtc1    $1, $f4                     # encoding: [0x00,0x20,0x81,0x44]
+
+li.s  $f4, 1.12345
+# CHECK:   .section        .lit4,"aw",@progbits
+# CHECK:   .4byte  1066388790
+# CHECK:   .text
+# CHECK:   lwc1    $f4, (%lit4(.lit4))-4($gp)  # encoding: [0xfc'A',0xff'A',0x84,0xc7]
+# CHECK:                                           #   fixup A - offset: 0, value: %lit4(.lit4), kind: fixup_Mips_LITERAL
+li.s  $f4, 1
+# CHECK:   lui     $1, 16256                   # encoding: [0x80,0x3f,0x01,0x3c]
+# CHECK:   mtc1    $1, $f4                     # encoding: [0x00,0x20,0x81,0x44]
+
+li.s  $f4, 1.0
+# CHECK:   lui     $1, 16256                   # encoding: [0x80,0x3f,0x01,0x3c]
+# CHECK:   mtc1    $1, $f4                     # encoding: [0x00,0x20,0x81,0x44]
+
+li.s  $f4, 12345678910
+# CHECK:   .section        .lit4,"aw",@progbits
+# CHECK:   .4byte  1345844999
+# CHECK:   .text
+# CHECK:   lwc1    $f4, (%lit4(.lit4))-4($gp)  # encoding: [0xfc'A',0xff'A',0x84,0xc7]
+# CHECK:                                           #   fixup A - offset: 0, value: %lit4(.lit4), kind: fixup_Mips_LITERAL
+
+li.s  $f4, 12345678910.0
+# CHECK:   .section        .lit4,"aw",@progbits
+# CHECK:   .4byte  1345844999
+# CHECK:   .text
+# CHECK:   lwc1    $f4, (%lit4(.lit4))-4($gp)  # encoding: [0xfc'A',0xff'A',0x84,0xc7]
+# CHECK:                                           #   fixup A - offset: 0, value: %lit4(.lit4), kind: fixup_Mips_LITERAL
+
+li.s  $f4, 0.4
+# CHECK:   .section        .lit4,"aw",@progbits
+# CHECK:   .4byte  1053609165
+# CHECK:   .text
+# CHECK:   lwc1    $f4, (%lit4(.lit4))-4($gp)  # encoding: [0xfc'A',0xff'A',0x84,0xc7]
+# CHECK:                                           #   fixup A - offset: 0, value: %lit4(.lit4), kind: fixup_Mips_LITERAL
+
+li.s  $f4, 1.5 
+# CHECK:   lui     $1, 16320                   # encoding: [0xc0,0x3f,0x01,0x3c]
+# CHECK:   mtc1    $1, $f4                     # encoding: [0x00,0x20,0x81,0x44]
+
+li.s  $f4, 12345678910.12345678910
+# CHECK:   .section        .lit4,"aw",@progbits
+# CHECK:   .4byte  1345844999
+# CHECK:   .text
+# CHECK:   lwc1    $f4, (%lit4(.lit4))-4($gp)  # encoding: [0xfc'A',0xff'A',0x84,0xc7]
+# CHECK:                                           #   fixup A - offset: 0, value: %lit4(.lit4), kind: fixup_Mips_LITERAL
+
+li.s  $f4, 12345678910123456789.12345678910
+# CHECK:   .section        .lit4,"aw",@progbits
+# CHECK:   .4byte  1596675242
+# CHECK:   .text
+# CHECK:   lwc1    $f4, (%lit4(.lit4))-4($gp)  # encoding: [0xfc'A',0xff'A',0x84,0xc7]
+# CHECK:                                           #   fixup A - offset: 0, value: %lit4(.lit4), kind: fixup_Mips_LITERAL