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- Jun 17 2015, 10:38 AM (397 w, 3 d)
Apr 18 2016
Previous patch did not contain test cases. Added here.
Apr 13 2016
Expansion of LI.S and LI.D without introducing new floating-point operands.
Apr 12 2016
Changes in accordance to last review (if replaced with ternary operator).
Apr 6 2016
Vasilis, patch is rebased. Please be faster with reviewing so that outdating does not happens again.
Rebased.
Mar 30 2016
Adding 64bit constants to ddiv[u] test cases.
We fixed indentation and we added predicates to the MipsInstAlias's.
This led to changes in the macro-div-bad.s, macro-divu-bad.s, macro-ddiv-bad.s and macro-ddivu-bad.s test cases.
Mar 23 2016
Mar 22 2016
According to feedback - using ternary operators.
According to feedback - split long line, redundant tests removed.
Mar 15 2016
Ping, dependant on D16888 and 16889
Adding 64bit constants to test cases.
Macro definitions updated to simm32, imm64
Tests reorganized.
Ping... We need review on this, since it is prerequisite for http://reviews.llvm.org/D16889
Mar 8 2016
Aditional tests added.
Mar 7 2016
Can You please be more precise what exactly You are expecting to be changed?
Feb 26 2016
Patch reduced to contain only changes for adding REM macro.
Patch reduced to contain only changes for adding immediate operand for DIV macro.
Feb 25 2016
Ping
Feb 24 2016
Review changes applied. Added additional test for case when destination register is zero register.
Feb 11 2016
This patch is split into three separate patches, and is now abandoned. Related patches:
Changes according to last feedback
Feb 10 2016
We couldn't extend test/MC/Mips/macro-la.s because some tests in it failed in pic mode. For example, 'la $5, symbol+8' gives: 'LLVM ERROR: unsupported reloc value'. Also, istruction la in the case 'la $5, 1f' does not expand properly because symbol 1 is defined at the end of the test file, so condition 'Sym->isInSection()' fails because of one pass structure of assembler.
Feb 9 2016
Added DMUL macro for non CnMips. Please, take a look at the predicates of DMULMacro, and confirm are they OK.
Old file accidentally left in the patch - removed.
Changes according to the comments
Feb 5 2016
Feb 4 2016
Feb 2 2016
In original test example there is one more instruction
Jan 28 2016
Jan 26 2016
New diff contains suggested changes
Jan 22 2016
I am continuing here http://reviews.llvm.org/D15745
Jan 19 2016
Dec 24 2015
Dec 23 2015
Continued here http://reviews.llvm.org/D15745
Nov 17 2015
New diff contains adaptations to the latest source code, using emit* functions for generating instructions.
Nov 5 2015
Nov 2 2015
New diff contains nit corrections, usage of TmpReg as suggested, and necessary changes to be applicable to latest source code.
Oct 19 2015
New diff contains nit fixes
Sep 16 2015
Sep 14 2015
Nit corrections
Sep 11 2015
New diff contains changes necessary to make patch applicable. Predicates are removed from few pseudo instructions in order to enable including PredicateControl into MipsAsmPseudoInst inheritance hierarchy. Some tests are disabled.
The same problem appeared with latest changes from http://reviews.llvm.org/D11675
Sep 8 2015
New diff contains nit fixes and changes needed to apply and properly build this fix.
New diff contains nit fixes and changes needed to apply and properly build this fix.
My bad, its:
The problem expands, because now another instruction prevents adding PredicateControl to MIspAsmPseudoInst.
Sep 7 2015
OK. I agree this is a good way to go. Then, the final corrections for this patch would be to remove AsmToken::Identifier case, remove ISA_MIPS1_NOT_32R6_64R6 from ULHU/ULW, and change tests appropriately.
Hi,
I believe you already have a conditional LGTM for this patch (for diff 28228) and that the quoted text above contains the only remaining issue. It was asking that you remove the AsmToken::Identifier code (because it introduces another way to parse labels which is already handled elsewhere) and fix the wrong-error issue it was intended to fix in a later patch that deals with other cases too.
Sep 4 2015
New diff contain changes that are needed to apply patch to latest version of source code.
Jul 8 2015
Nit corrections + context
New diff contains expansions for ROL, ROR, DROL, DROR, for all cpus and test cases.
Jul 2 2015
Jun 30 2015
New diff contains ROL/ROR expansion for all 32rN and 64rN platforms, where these instructions are aliasses for ROTR and ROTRV.
Jun 24 2015
PredicateControl moved from CondBranchPseudo to the MipsAsmPseudoInst
Jun 23 2015
Daniel, my task was the expansion of these macros, by mips bugzilla report 723.
New diff contains formatting fixes and renamed variables where suggested.
New diff includes formatting fixes, test cases for error on using BL instructions on r6, and a fix for other test cases in test files test/MC/Mips/mips??r6/invalid.s, which were not executing.
Jun 22 2015
Jun 19 2015
New diff contains fix for error reporting when branch likely instructions are used on mips32r6/mips64r6.