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Differential D143757

[AMDGPU] Enable predicated copy right from instruction selection
AbandonedPublic

Authored by cdevadas on Feb 10 2023, 9:26 AM.

Details

Reviewers
arsenm
rampitec
Summary

This patch would enable the predicated copy opcode by default
for AMDGPU right from the instruction selection. At certain
point after regalloc, they will be fixed. When for SGPR copies
they become regular COPY opcodes, for all vector copies, the
implicit exec use will be added still retaining the PRED_COPY
opcode. Based on the register class involved, later copyPhysReg
called during expand post-RA pseudos will lower all forms of
copy opcodes into respective target instructions.

Diff Detail

Large Diff

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Diff 496523

llvm/lib/Target/AMDGPU/AMDGPU.h

llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.cpp

llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.cpp

llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp

llvm/lib/Target/AMDGPU/CMakeLists.txt

llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp

llvm/lib/Target/AMDGPU/GCNPreRAOptimizations.cpp

llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp

llvm/lib/Target/AMDGPU/SIFixVGPRCopies.cpp

llvm/lib/Target/AMDGPU/SIFoldOperands.cpp

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

llvm/lib/Target/AMDGPU/SIInstrInfo.h

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp

llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp

llvm/lib/Target/AMDGPU/SISimplifyPredicatedCopies.cpp

llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp

llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-extract.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-zext.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f32-no-rtn.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f32-rtn.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f64.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.v2f16-no-rtn.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.v2f16-rtn.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/bug-legalization-artifact-combiner-dead-def.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/dereferenceable-declaration.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/dropped_debug_info_assert.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/dummy-target.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/flat-atomic-fadd.f32.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/flat-atomic-fadd.f64.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/flat-atomic-fadd.v2f16.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f32-no-rtn.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f32-rtn.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f64.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.v2f16-no-rtn.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.v2f16-rtn.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/global-value.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/inline-asm-mismatched-size.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-abs.mir

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llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-fadd-local.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-fadd-region.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-xchg-local.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-xchg-region.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-bitcast.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-bitreverse.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-brcond.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-bswap.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-build-vector-trunc.v2s16.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-build-vector.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-concat-vectors.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-constant.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ctlz-zero-undef.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ctpop.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-cttz-zero-undef.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-extract-vector-elt.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-extract.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fabs.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s16.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s32.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s64.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcanonicalize.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fceil.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fceil.s16.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.s16.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fconstant.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fexp2.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ffloor.s16.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ffloor.s32.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ffloor.s64.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fma.s32.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmad.s32.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.s16.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.v2s16.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.s16.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.v2s16.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.s16.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.v2s16.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.s16.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.v2s16.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmul.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmul.v2s16.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fneg.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptosi.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptoui.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fract.f64.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-frame-index.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-freeze.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-frint.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-frint.s16.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fshr.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-i1-copy.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-icmp.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-icmp.s16.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-icmp.s64.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-insert-vector-elt.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-insert.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-intrinsic-trunc.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-intrinsic-trunc.s16.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-inttoptr.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-flat.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-global.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-local.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-constant.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-flat.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global-saddr.mir

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llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global.s96.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-local-128.mir

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llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-add3.mir

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