[RISCV] Refactor RISCVDisassembler::getInstruction to remove repeated code. NFC

[craig.topper]

Summary

For 4 byte instructions we were always setting size to 4 eventually. Same
for 2 byte instructions. So do it as soon as we know the from the opcode.

Add a return to the end of the 4 byte code so we don't have to have an else
around the 2 byte code.

[reames]

LGTM

llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

450

whitespace change

[craig.topper]

llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

450

It was intentional. The 2 byte code had a blank line after Insn. I was making them consistent.

llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
   DecodeStatus Result;
 
   // It's a 32 bit instruction if bit 0 and 1 are 1.
   if ((Bytes[0] & 0x3) == 0x3) {
     if (Bytes.size() < 4) {
       Size = 0;
       return MCDisassembler::Fail;
     }
+    Size = 4;
+
     Insn = support::endian::read32le(Bytes.data());
+
     if (STI.getFeatureBits()[RISCV::FeatureStdExtZdinx] &&
         !STI.getFeatureBits()[RISCV::Feature64Bit]) {
       LLVM_DEBUG(dbgs() << "Trying RV32Zdinx table (Double in Integer and"
                            "rv32)\n");
       Result = decodeInstruction(DecoderTableRV32Zdinx32, MI, Insn, Address,
                                  this, STI);
-      if (Result != MCDisassembler::Fail) {
-        Size = 4;
+      if (Result != MCDisassembler::Fail)
         return Result;
-      }
-    }
-
     if (STI.getFeatureBits()[RISCV::FeatureStdExtZfinx]) {
       LLVM_DEBUG(dbgs() << "Trying RVZfinx table (Float in Integer):\n");
       Result = decodeInstruction(DecoderTableRVZfinx32, MI, Insn, Address, this,
                                  STI);
-      if (Result != MCDisassembler::Fail) {
-        Size = 4;
+      if (Result != MCDisassembler::Fail)
         return Result;
-      }
-    }
     if (STI.getFeatureBits()[RISCV::FeatureVendorXVentanaCondOps]) {
       LLVM_DEBUG(dbgs() << "Trying Ventana custom opcode table:\n");
       Result = decodeInstruction(DecoderTableVentana32, MI, Insn, Address, this,
                                  STI);
-      if (Result != MCDisassembler::Fail) {
-        Size = 4;
+      if (Result != MCDisassembler::Fail)
         return Result;
-      }
-    }
     if (STI.getFeatureBits()[RISCV::FeatureVendorXTHeadVdot]) {
       LLVM_DEBUG(dbgs() << "Trying XTHeadVdot custom opcode table:\n");
       Result =
           decodeInstruction(DecoderTableTHeadV32, MI, Insn, Address, this, STI);
-      if (Result != MCDisassembler::Fail) {
-        Size = 4;
+      if (Result != MCDisassembler::Fail)
         return Result;
-      }
-    }
 
     LLVM_DEBUG(dbgs() << "Trying RISCV32 table :\n");
-    Result = decodeInstruction(DecoderTable32, MI, Insn, Address, this, STI);
-    Size = 4;
-  } else {
-    if (Bytes.size() < 2) {
-      Size = 0;
-      return MCDisassembler::Fail;
-    }
-    Insn = support::endian::read16le(Bytes.data());
+    return decodeInstruction(DecoderTable32, MI, Insn, Address, this, STI);
+  }
+
+  Size = 2;
+
 
-    if (!STI.getFeatureBits()[RISCV::Feature64Bit]) {
-      LLVM_DEBUG(
-          dbgs() << "Trying RISCV32Only_16 table (16-bit Instruction):\n");
-      // Calling the auto-generated decoder function.
-      Result = decodeInstruction(DecoderTableRISCV32Only_16, MI, Insn, Address,
-                                 this, STI);
-      if (Result != MCDisassembler::Fail) {
-        Size = 2;
-        return Result;
-      }
-    }
+    if (Result != MCDisassembler::Fail)
 
-    LLVM_DEBUG(dbgs() << "Trying RISCV_C table (16-bit Instruction):\n");
-    // Calling the auto-generated decoder function.
-    Result = decodeInstruction(DecoderTable16, MI, Insn, Address, this, STI);
-    Size = 2;
-  }
-
-  return Result;
+  return decodeInstruction(DecoderTable16, MI, Insn, Address, this, STI);
 }