[mlir][vector] Clarify vector.contract promotion behavior

[antiagainst]

Summary

This commit updates vector.contract documentation to clarify
the promotion behavior if operands and the result have different
bitwidths. It also adds a check to disable signed/unsigned integer
types and only allow signless integers.

[dcaballe]

mlir/include/mlir/Dialect/Vector/IR/VectorOps.td

116

Could we have an f16, f16 -> f32?

[ThomasRaoux]

mlir/include/mlir/Dialect/Vector/IR/VectorOps.td

116

Yes I don't think the promotion behavior is specific to integer. What is specific to integers is whether we do signed or zero extend.

[antiagainst]

Address comments

mlir/include/mlir/Dialect/Vector/IR/VectorOps.td

116

Good catch. Reworded accordingly.

[antiagainst]

Grammar

[antiagainst]

Address comments

[ThomasRaoux]

Thanks!

mlir/include/mlir/Dialect/Vector/IR/VectorOps.td

def Vector_ContractionOp :
   let description = [{
     Computes the sum of products of vector elements along contracting
     dimension pairs from 2 vectors of rank M and N respectively, adds this
     intermediate result to the accumulator argument of rank K, and returns a
     vector result of rank K (where K = num_lhs_free_dims + num_rhs_free_dims +
     num_batch_dims (see dimension type descriptions below)). For K = 0 (no
     free or batch dimensions), the accumulator and output are a scalar.
 
+    If operands and the result have types of different bitwidths, operands are
+    promoted to have the same bitwidth as the result before performing the
+    contraction. For integer types, only signless integer types are supported,
+    and the promotion happens via sign extension.
+
     Optional vector mask arguments (produced by CreateMaskOp or ConstantMaskOp)
     specify the dynamic dimension sizes of valid data within the lhs/rhs vector
     arguments.
 
     An iterator type attribute list must be specified, where each element of
     the list represents an iterator with one of the following types:
 
     *   "reduction": reduction dimensions are present in the lhs and rhs

mlir/lib/Dialect/Vector/IR/VectorOps.cpp

if (resVectorType != expected || accVectorType != expected)
       return op.emitOpError(
                  "invalid accumulator/result vector shape, expected: ")
              << expected;
   }
   return success();
 }
 
 LogicalResult ContractionOp::verify() {
-  auto lhsType = getLhsType();
-  auto rhsType = getRhsType();
-  auto accType = getAccType();
-  auto resType = getResultType();
+  VectorType lhsType = getLhsType();
+  VectorType rhsType = getRhsType();
+  Type accType = getAccType();
+  Type resType = getResultType();
+
+  if (lhsType.getElementType().isa<IntegerType>()) {
+    if (!lhsType.getElementType().isSignlessInteger())
+      return emitOpError("only supports signless integer types");
+  }
 
   // Verify that an indexing map was specified for each vector operand.
   if (getIndexingMapsArray().size() != 3)
     return emitOpError("expected an indexing map for each vector operand");
 
   // Verify that each index map has 'numIterators' inputs, no symbols, and
   // that the number of map outputs equals the rank of its associated
   // vector operand.

mlir/test/Dialect/Vector/invalid.mlir

 }
 
 // -----
 
 func.func @vector_scalable_extract_unaligned(%vec: vector<[16]xf32>) {
   // expected-error@+1 {{op failed to verify that position is a multiple of the result length.}}
   %0 = vector.scalable.extract %vec[5] : vector<4xf32> from vector<[16]xf32>
 }
+
+// -----
+
+func.func @integer_vector_contract(%arg0: vector<16x32xsi8>, %arg1: vector<32x16xsi8>, %arg2: vector<16x16xsi32>) -> vector<16x16xsi32> {
+  // expected-error@+1 {{op only supports signless integer types}}
+  %0 = vector.contract {
+    indexing_maps = [affine_map<(d0, d1, d2) -> (d0, d2)>, affine_map<(d0, d1, d2) -> (d2, d1)>, affine_map<(d0, d1, d2) -> (d0, d1)>],
+    iterator_types = ["parallel", "parallel", "reduction"], kind = #vector.kind<add>
+  } %arg0, %arg1, %arg2 : vector<16x32xsi8>, vector<32x16xsi8> into vector<16x16xsi32>
+  return %0: vector<16x16xsi32>
+}