[mlir][vector] Clarify vector.contract promotion behavior

[antiagainst]

Summary

This commit updates vector.contract documentation to clarify
the promotion behavior if operands and the result have different
bitwidths. It also adds a check to disable signed/unsigned integer
types and only allow signless integers.

[dcaballe]

mlir/include/mlir/Dialect/Vector/IR/VectorOps.td

116

Could we have an f16, f16 -> f32?

[ThomasRaoux]

mlir/include/mlir/Dialect/Vector/IR/VectorOps.td

116

Yes I don't think the promotion behavior is specific to integer. What is specific to integers is whether we do signed or zero extend.

[antiagainst]

Address comments

mlir/include/mlir/Dialect/Vector/IR/VectorOps.td

116

Good catch. Reworded accordingly.

[antiagainst]

Grammar

[antiagainst]

Address comments

[ThomasRaoux]

Thanks!

mlir/include/mlir/Dialect/Vector/IR/VectorOps.td

def Vector_ContractionOp :
   let description = [{
     Computes the sum of products of vector elements along contracting
     dimension pairs from 2 vectors of rank M and N respectively, adds this
     intermediate result to the accumulator argument of rank K, and returns a
     vector result of rank K (where K = num_lhs_free_dims + num_rhs_free_dims +
     num_batch_dims (see dimension type descriptions below)). For K = 0 (no
     free or batch dimensions), the accumulator and output are a scalar.
 
+    If operands and results are integer types of different bitwidths, operands
+    are promoted to have the same bitwidth as the result before performing the
+    contraction.
+
     Optional vector mask arguments (produced by CreateMaskOp or ConstantMaskOp)
     specify the dynamic dimension sizes of valid data within the lhs/rhs vector
     arguments.
 
     An iterator type attribute list must be specified, where each element of
     the list represents an iterator with one of the following types:
 
     *   "reduction": reduction dimensions are present in the lhs and rhs