[SPARC] Lower BR_CC to BPr on 64-bit target whenever possible

[koakuma]

Summary

On 64-bit target, when doing i64 BR_CC where one of the comparison operands is a constant zero, try to fold the compare and BPcc into a BPr instruction.

For all integers, EQ and NE comparison are available, additionally for signed integers, GT, GE, LT, and LE is also available.

Depends on D142458 & D144012.

[koakuma]

llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp

45

Not really sure if this is the proper way to do it, but I've found that without the left shift, the integrated assembler would misplace the two upper bits of BPr branch displacements.
Comments?

[koakuma]

Ping?

[arsenm]

llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp

45

I know nothing about this, but it seems like it should be split into a separate patch

[koakuma]

llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp

45

I'm afraid I couldn't split this, since the misplacement of the upper two bits would result in all backwards BPr branches being miscompiled.

[koakuma]

Ping again?

[arsenm]

llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp

45

But this does something maybe wrong as-is. This should be separately testable with a pure MC test (e.g. llvm/test/MC/AMDGPU/offsetbug_once.s)

[koakuma]

Split the encoding fix into D144012.

[koakuma]

Sorry, just noticed that this was being merged, but can we postpone/revert it at least until D144012 is also merged, @brad?
Without it, backwards branches might be miscompiled when using IAS...

[brad]

In D142461#4186922, @koakuma wrote:

Sorry, just noticed that this was being merged, but can we postpone/revert it at least until D144012 is also merged, @brad?

Just D142461?

[koakuma]

In D142461#4187043, @brad wrote:

Just D142461?

Yes, just this one (D142461). Thanks a lot!

[koakuma]

@brad, now that D144012 has been merged, this should be okay to merge too.

[brad]

In D142461#4322261, @koakuma wrote:

@brad, now that D144012 has been merged, this should be okay to merge too.

This was not reverted. It's already in the tree.

llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp

static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
 
   case Sparc::fixup_sparc_br22:
     return (Value >> 2) & 0x3fffff;
 
   case Sparc::fixup_sparc_br19:
     return (Value >> 2) & 0x7ffff;
 
   case Sparc::fixup_sparc_br16_2:
-    return (Value >> 2) & 0xc000;
+    return ((Value >> 2) & 0xc000) << 6;
 
   case Sparc::fixup_sparc_br16_14:
     return (Value >> 2) & 0x3fff;
 
   case Sparc::fixup_sparc_hix22:
     return (~Value >> 10) & 0x3fffff;
 
   case Sparc::fixup_sparc_pc22:

llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.cpp

case SP::FMOVQ_FCC: case SP::V9FMOVQ_FCC:
     // Make sure CC is a fp conditional flag.
     CC = (CC < SPCC::FCC_BEGIN) ? (CC + SPCC::FCC_BEGIN) : CC;
     break;
   case SP::CBCOND:
   case SP::CBCONDA:
     // Make sure CC is a cp conditional flag.
     CC = (CC < SPCC::CPCC_BEGIN) ? (CC + SPCC::CPCC_BEGIN) : CC;
     break;
+  case SP::BPR:
+  case SP::BPRA:
+  case SP::BPRNT:
+  case SP::BPRANT:
   case SP::MOVRri:
   case SP::MOVRrr:
   case SP::FMOVRS:
   case SP::FMOVRD:
   case SP::FMOVRQ:
     // Make sure CC is a register conditional flag.
     CC = (CC < SPCC::REG_BEGIN) ? (CC + SPCC::REG_BEGIN) : CC;
     break;

llvm/lib/Target/Sparc/SparcISelLowering.h

enum NodeType : unsigned {
     CMPICC,    // Compare two GPR operands, set icc+xcc.
     CMPFCC,    // Compare two FP operands, set fcc.
     CMPFCC_V9, // Compare two FP operands, set fcc (v9 variant).
     BRICC,     // Branch to dest on icc condition
     BPICC,    // Branch to dest on icc condition, with prediction (64-bit only).
     BPXCC,    // Branch to dest on xcc condition, with prediction (64-bit only).
     BRFCC,    // Branch to dest on fcc condition
     BRFCC_V9, // Branch to dest on fcc condition (v9 variant).
+    BR_REG,   // Branch to dest using the comparison of a register with zero.
     SELECT_ICC, // Select between two values using the current ICC flags.
     SELECT_XCC, // Select between two values using the current XCC flags.
     SELECT_FCC, // Select between two values using the current FCC flags.
     SELECT_REG, // Select between two values using the comparison of a register
                 // with zero.
 
     Hi,
     Lo, // Hi/Lo operations, typically on a global address.

llvm/lib/Target/Sparc/SparcISelLowering.cpp

const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const {
   case SPISD::BRICC:           return "SPISD::BRICC";
   case SPISD::BPICC:
     return "SPISD::BPICC";
   case SPISD::BPXCC:
     return "SPISD::BPXCC";
   case SPISD::BRFCC:           return "SPISD::BRFCC";
   case SPISD::BRFCC_V9:
     return "SPISD::BRFCC_V9";
+  case SPISD::BR_REG:
+    return "SPISD::BR_REG";
   case SPISD::SELECT_ICC:      return "SPISD::SELECT_ICC";
   case SPISD::SELECT_XCC:      return "SPISD::SELECT_XCC";
   case SPISD::SELECT_FCC:      return "SPISD::SELECT_FCC";
   case SPISD::SELECT_REG:
     return "SPISD::SELECT_REG";
   case SPISD::Hi:              return "SPISD::Hi";
   case SPISD::Lo:              return "SPISD::Lo";
   case SPISD::FTOI:            return "SPISD::FTOI";
return TLI.LowerF128Op(Op, DAG,
                          TLI.getLibcallName(OpVT == MVT::i32
                                             ? RTLIB::UINTTOFP_I32_F128
                                             : RTLIB::UINTTOFP_I64_F128),
                          1);
 }
 
 static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG,
                           const SparcTargetLowering &TLI, bool hasHardQuad,
-                          bool isV9) {
+                          bool isV9, bool is64Bit) {
   SDValue Chain = Op.getOperand(0);
   ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
   SDValue LHS = Op.getOperand(2);
   SDValue RHS = Op.getOperand(3);
   SDValue Dest = Op.getOperand(4);
   SDLoc dl(Op);
   unsigned Opc, SPCC = ~0U;
 
   // If this is a br_cc of a "setcc", and if the setcc got lowered into
   // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
   LookThroughSetCC(LHS, RHS, CC, SPCC);
   assert(LHS.getValueType() == RHS.getValueType());
 
   // Get the condition flag.
   SDValue CompareFlag;
   if (LHS.getValueType().isInteger()) {
+    // On V9 processors running in 64-bit mode, if CC compares two `i64`s
+    // and the RHS is zero we might be able to use a specialized branch.
+    const ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS);
+    if (is64Bit && isV9 && LHS.getValueType() == MVT::i64 && RHSC &&
+        RHSC->isZero() && !ISD::isUnsignedIntSetCC(CC))
+      return DAG.getNode(SPISD::BR_REG, dl, MVT::Other, Chain, Dest,
+                         DAG.getConstant(intCondCCodeToRcond(CC), dl, MVT::i32),
+                         LHS);
+
     CompareFlag = DAG.getNode(SPISD::CMPICC, dl, MVT::Glue, LHS, RHS);
     if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
     if (isV9)
       // 32-bit compares use the icc flags, 64-bit uses the xcc flags.
       Opc = LHS.getValueType() == MVT::i32 ? SPISD::BPICC : SPISD::BPXCC;
     else
       // Non-v9 targets don't have xcc.
       Opc = SPISD::BRICC;
case ISD::FP_TO_SINT:         return LowerFP_TO_SINT(Op, DAG, *this,
                                                        hasHardQuad);
   case ISD::SINT_TO_FP:         return LowerSINT_TO_FP(Op, DAG, *this,
                                                        hasHardQuad);
   case ISD::FP_TO_UINT:         return LowerFP_TO_UINT(Op, DAG, *this,
                                                        hasHardQuad);
   case ISD::UINT_TO_FP:         return LowerUINT_TO_FP(Op, DAG, *this,
                                                        hasHardQuad);
   case ISD::BR_CC:
-    return LowerBR_CC(Op, DAG, *this, hasHardQuad, isV9);
+    return LowerBR_CC(Op, DAG, *this, hasHardQuad, isV9, is64Bit);
   case ISD::SELECT_CC:
     return LowerSELECT_CC(Op, DAG, *this, hasHardQuad, isV9, is64Bit);
   case ISD::VASTART:            return LowerVASTART(Op, DAG, *this);
   case ISD::VAARG:              return LowerVAARG(Op, DAG);
   case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG,
                                                                Subtarget);
 
   case ISD::LOAD:               return LowerLOAD(Op, DAG);

llvm/lib/Target/Sparc/SparcInstr64Bit.td

def FMOVQ_XCC : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd),
                       "fmovq$cond %xcc, $rs2, $rd",
                       [(set f128:$rd,
                        (SPselectxcc f128:$rs2, f128:$f, imm:$cond))]>;
 } // opf_cc
 } // Uses, Constraints
 
 // Branch On integer register with Prediction (BPr).
 let isBranch = 1, isTerminator = 1, hasDelaySlot = 1 in
-multiclass BranchOnReg<bits<3> cond, string OpcStr> {
-  def napt : F2_4<cond, 0, 1, (outs), (ins I64Regs:$rs1, bprtarget16:$imm16),
-             !strconcat(OpcStr, " $rs1, $imm16"), []>;
-  def apt  : F2_4<cond, 1, 1, (outs), (ins I64Regs:$rs1, bprtarget16:$imm16),
-             !strconcat(OpcStr, ",a $rs1, $imm16"), []>;
-  def napn  : F2_4<cond, 0, 0, (outs), (ins I64Regs:$rs1, bprtarget16:$imm16),
-             !strconcat(OpcStr, ",pn $rs1, $imm16"), []>;
-  def apn : F2_4<cond, 1, 0, (outs), (ins I64Regs:$rs1, bprtarget16:$imm16),
-             !strconcat(OpcStr, ",a,pn $rs1, $imm16"), []>;
+multiclass BranchOnReg<list<dag> CCPattern> {
+  def R    : F2_4<0, 1, (outs), (ins bprtarget16:$imm16, RegCCOp:$rcond, I64Regs:$rs1),
+             "br$rcond $rs1, $imm16", CCPattern>;
+  def RA   : F2_4<1, 1, (outs), (ins bprtarget16:$imm16, RegCCOp:$rcond, I64Regs:$rs1),
+             "br$rcond,a $rs1, $imm16", []>;
+  def RNT  : F2_4<0, 0, (outs), (ins bprtarget16:$imm16, RegCCOp:$rcond, I64Regs:$rs1),
+             "br$rcond,pn $rs1, $imm16", []>;
+  def RANT : F2_4<1, 0, (outs), (ins bprtarget16:$imm16, RegCCOp:$rcond, I64Regs:$rs1),
+             "br$rcond,a,pn $rs1, $imm16", []>;
 }
 
 multiclass bpr_alias<string OpcStr, Instruction NAPT, Instruction APT> {
   def : InstAlias<!strconcat(OpcStr, ",pt $rs1, $imm16"),
                   (NAPT I64Regs:$rs1, bprtarget16:$imm16), 0>;
   def : InstAlias<!strconcat(OpcStr, ",a,pt $rs1, $imm16"),
                   (APT I64Regs:$rs1, bprtarget16:$imm16), 0>;
 }
 
-defm BPZ   : BranchOnReg<0b001, "brz">;
-defm BPLEZ : BranchOnReg<0b010, "brlez">;
-defm BPLZ  : BranchOnReg<0b011, "brlz">;
-defm BPNZ  : BranchOnReg<0b101, "brnz">;
-defm BPGZ  : BranchOnReg<0b110, "brgz">;
-defm BPGEZ : BranchOnReg<0b111, "brgez">;
-
-defm : bpr_alias<"brz",   BPZnapt,   BPZapt  >;
-defm : bpr_alias<"brlez", BPLEZnapt, BPLEZapt>;
-defm : bpr_alias<"brlz",  BPLZnapt,  BPLZapt >;
-defm : bpr_alias<"brnz",  BPNZnapt,  BPNZapt >;
-defm : bpr_alias<"brgz",  BPGZnapt,  BPGZapt >;
-defm : bpr_alias<"brgez", BPGEZnapt, BPGEZapt>;
+let Predicates = [Is64Bit] in
+  defm BP : BranchOnReg<[(SPbrreg bb:$imm16, imm:$rcond, i64:$rs1)]>;
 
 // Move integer register on register condition (MOVr).
 let Predicates = [Is64Bit], Constraints = "$f = $rd" in {
   def MOVRrr : F4_4r<0b101111, 0b00000, (outs IntRegs:$rd),
                    (ins I64Regs:$rs1, IntRegs:$rs2, IntRegs:$f, RegCCOp:$rcond),
                    "movr$rcond $rs1, $rs2, $rd",
                    [(set i32:$rd, (SPselectreg i32:$rs2, i32:$f, imm:$rcond, i64:$rs1))]>;
 

llvm/lib/Target/Sparc/SparcInstrAliases.td

multiclass cp_cond_alias<string cond, int condVal> {
 
   // cb<cond>,a $imm
   def : InstAlias<!strconcat(!strconcat("cb", cond), ",a $imm"),
                   (CBCONDA brtarget:$imm, condVal), 0>;
 }
 
 // Instruction aliases for register conditional branches and moves.
 multiclass reg_cond_alias<string rcond, int condVal> {
+  // br<rcond> $rs1, $imm
+  def : InstAlias<!strconcat(!strconcat("br", rcond), " $rs1, $imm"),
+                  (BPR bprtarget16:$imm, condVal, I64Regs:$rs1)>,
+                  Requires<[Is64Bit]>;
+
+  // br<rcond>,pt $rs1, $imm
+  def : InstAlias<!strconcat(!strconcat("br", rcond), ",pt $rs1, $imm"),
+                  (BPR bprtarget16:$imm, condVal, I64Regs:$rs1)>,
+                  Requires<[Is64Bit]>;
+
+  // br<rcond>,pn $rs1, $imm
+  def : InstAlias<!strconcat(!strconcat("br", rcond), ",pn $rs1, $imm"),
+                  (BPRNT bprtarget16:$imm, condVal, I64Regs:$rs1)>,
+                  Requires<[Is64Bit]>;
+
+  // br<rcond>,a $rs1, $imm
+  def : InstAlias<!strconcat(!strconcat("br", rcond), ",a $rs1, $imm"),
+                  (BPRA bprtarget16:$imm, condVal, I64Regs:$rs1)>,
+                  Requires<[Is64Bit]>;
+
+  // br<rcond>,a,pt $rs1, $imm
+  def : InstAlias<!strconcat(!strconcat("br", rcond), ",a,pt $rs1, $imm"),
+                  (BPRA bprtarget16:$imm, condVal, I64Regs:$rs1)>,
+                  Requires<[Is64Bit]>;
+
+  // br<rcond>,a,pn $rs1, $imm
+  def : InstAlias<!strconcat(!strconcat("br", rcond), ",a,pn $rs1, $imm"),
+                  (BPRANT bprtarget16:$imm, condVal, I64Regs:$rs1)>,
+                  Requires<[Is64Bit]>;
+
   defm : regcond_mov_alias<rcond, condVal,
                             MOVRrr, MOVRri,
                             FMOVRS, FMOVRD, FMOVRQ>,
                             Requires<[Is64Bit]>;
 }
 
 defm : int_cond_alias<"a",    0b1000>;
 defm : int_cond_alias<"n",    0b0000>;

llvm/lib/Target/Sparc/SparcInstrFormats.td

class F2_3<bits<3> op2Val, bit annul, bit pred,
   let Inst{29}    = annul;
   let Inst{28-25} = cond;
   let Inst{24-22} = op2Val;
   let Inst{21-20} = cc;
   let Inst{19}    = pred;
   let Inst{18-0}  = imm19;
 }
 
-class F2_4<bits<3> cond, bit annul, bit pred, dag outs, dag ins,
+class F2_4<bit annul, bit pred, dag outs, dag ins,
            string asmstr, list<dag> pattern, InstrItinClass itin = NoItinerary>
    : InstSP<outs, ins, asmstr, pattern, itin> {
   bits<16> imm16;
   bits<5>  rs1;
+  bits<3>  rcond;
 
   let op          = 0;    // op = 0
 
   let Inst{29}    = annul;
   let Inst{28}    = 0;
-  let Inst{27-25} = cond;
+  let Inst{27-25} = rcond;
   let Inst{24-22} = 0b011;
   let Inst{21-20} = imm16{15-14};
   let Inst{19}    = pred;
   let Inst{18-14} = rs1;
   let Inst{13-0}  = imm16{13-0};
 }
 
 

llvm/lib/Target/Sparc/SparcInstrInfo.cpp

 
 #define GET_INSTRINFO_CTOR_DTOR
 #include "SparcGenInstrInfo.inc"
 
 static cl::opt<unsigned> BPccDisplacementBits(
     "sparc-bpcc-offset-bits", cl::Hidden, cl::init(19),
     cl::desc("Restrict range of BPcc/FBPfcc instructions (DEBUG)"));
 
+static cl::opt<unsigned>
+    BPrDisplacementBits("sparc-bpr-offset-bits", cl::Hidden, cl::init(16),
+                        cl::desc("Restrict range of BPr instructions (DEBUG)"));
+
 // Pin the vtable to this file.
 void SparcInstrInfo::anchor() {}
 
 SparcInstrInfo::SparcInstrInfo(SparcSubtarget &ST)
     : SparcGenInstrInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP), RI(),
       Subtarget(ST) {}
 
 /// isLoadFromStackSlot - If the specified machine instruction is a direct
return Opc == SP::BCOND || Opc == SP::BPICC || Opc == SP::BPICCA ||
          Opc == SP::BPICCNT || Opc == SP::BPICCANT;
 }
 
 static bool isI64CondBranchOpcode(int Opc) {
   return Opc == SP::BPXCC || Opc == SP::BPXCCA || Opc == SP::BPXCCNT ||
          Opc == SP::BPXCCANT;
 }
 
+static bool isRegCondBranchOpcode(int Opc) {
+  return Opc == SP::BPR || Opc == SP::BPRA || Opc == SP::BPRNT ||
+         Opc == SP::BPRANT;
+}
+
 static bool isFCondBranchOpcode(int Opc) {
   return Opc == SP::FBCOND || Opc == SP::FBCONDA || Opc == SP::FBCOND_V9 ||
          Opc == SP::FBCONDA_V9;
 }
 
 static bool isCondBranchOpcode(int Opc) {
   return isI32CondBranchOpcode(Opc) || isI64CondBranchOpcode(Opc) ||
-         isFCondBranchOpcode(Opc);
+         isRegCondBranchOpcode(Opc) || isFCondBranchOpcode(Opc);
 }
 
 static bool isIndirectBranchOpcode(int Opc) {
   return Opc == SP::BINDrr || Opc == SP::BINDri;
 }
 
 static void parseCondBranch(MachineInstr *LastInst, MachineBasicBlock *&Target,
                             SmallVectorImpl<MachineOperand> &Cond) {
   unsigned Opc = LastInst->getOpcode();
   int64_t CC = LastInst->getOperand(1).getImm();
 
   // Push the branch opcode into Cond too so later in insertBranch
   // it can use the information to emit the correct SPARC branch opcode.
   Cond.push_back(MachineOperand::CreateImm(Opc));
   Cond.push_back(MachineOperand::CreateImm(CC));
 
+  // Branch on register contents need another argument to indicate
+  // the register it branches on.
+  if (isRegCondBranchOpcode(Opc)) {
+      Register Reg = LastInst->getOperand(2).getReg();
+      Cond.push_back(MachineOperand::CreateReg(Reg, false));
+  }
+
   Target = LastInst->getOperand(0).getMBB();
 }
 
 MachineBasicBlock *
 SparcInstrInfo::getBranchDestBlock(const MachineInstr &MI) const {
   switch (MI.getOpcode()) {
   default:
       llvm_unreachable("unexpected opcode!");
SparcInstrInfo::getBranchDestBlock(const MachineInstr &MI) const {
   case SP::BPXCCNT:
   case SP::BPXCCANT:
   case SP::BPFCC:
   case SP::BPFCCA:
   case SP::BPFCCNT:
   case SP::BPFCCANT:
   case SP::FBCOND_V9:
   case SP::FBCONDA_V9:
+  case SP::BPR:
+  case SP::BPRA:
+  case SP::BPRNT:
+  case SP::BPRANT:
       return MI.getOperand(0).getMBB();
   }
 }
 
 bool SparcInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
                                    MachineBasicBlock *&TBB,
                                    MachineBasicBlock *&FBB,
                                    SmallVectorImpl<MachineOperand> &Cond,

 
 unsigned SparcInstrInfo::insertBranch(MachineBasicBlock &MBB,
                                       MachineBasicBlock *TBB,
                                       MachineBasicBlock *FBB,
                                       ArrayRef<MachineOperand> Cond,
                                       const DebugLoc &DL,
                                       int *BytesAdded) const {
   assert(TBB && "insertBranch must not be told to insert a fallthrough");
-  assert((Cond.size() <= 2) &&
-         "Sparc branch conditions should have at most two components!");
+  assert((Cond.size() <= 3) &&
+         "Sparc branch conditions should have at most three components!");
 
   if (Cond.empty()) {
     assert(!FBB && "Unconditional branch with multiple successors!");
     BuildMI(&MBB, DL, get(SP::BA)).addMBB(TBB);
     if (BytesAdded)
       *BytesAdded = 8;
     return 1;
   }
 
   // Conditional branch
   unsigned Opc = Cond[0].getImm();
   unsigned CC = Cond[1].getImm();
+  if (isRegCondBranchOpcode(Opc)) {
+    Register Reg = Cond[2].getReg();
+    BuildMI(&MBB, DL, get(Opc)).addMBB(TBB).addImm(CC).addReg(Reg);
+  } else {
     BuildMI(&MBB, DL, get(Opc)).addMBB(TBB).addImm(CC);
+  }
 
   if (!FBB) {
     if (BytesAdded)
       *BytesAdded = 8;
     return 1;
   }
 
   BuildMI(&MBB, DL, get(SP::BA)).addMBB(FBB);
unsigned SparcInstrInfo::removeBranch(MachineBasicBlock &MBB,
 
   if (BytesRemoved)
     *BytesRemoved = Removed;
   return Count;
 }
 
 bool SparcInstrInfo::reverseBranchCondition(
     SmallVectorImpl<MachineOperand> &Cond) const {
-  assert(Cond.size() <= 2);
+  assert(Cond.size() <= 3);
   SPCC::CondCodes CC = static_cast<SPCC::CondCodes>(Cond[1].getImm());
   Cond[1].setImm(GetOppositeBranchCondition(CC));
   return false;
 }
 
 bool SparcInstrInfo::isBranchOffsetInRange(unsigned BranchOpc,
                                            int64_t Offset) const {
   assert((Offset & 0b11) == 0 && "Malformed branch offset");
bool SparcInstrInfo::isBranchOffsetInRange(unsigned BranchOpc,
   case SP::BPXCCANT:
   case SP::BPFCC:
   case SP::BPFCCA:
   case SP::BPFCCNT:
   case SP::BPFCCANT:
   case SP::FBCOND_V9:
   case SP::FBCONDA_V9:
     return isIntN(BPccDisplacementBits, Offset >> 2);
+
+  case SP::BPR:
+  case SP::BPRA:
+  case SP::BPRNT:
+  case SP::BPRANT:
+    return isIntN(BPrDisplacementBits, Offset >> 2);
   }
 
   llvm_unreachable("Unknown branch instruction!");
 }
 
 void SparcInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
                                  MachineBasicBlock::iterator I,
                                  const DebugLoc &DL, MCRegister DestReg,

llvm/lib/Target/Sparc/SparcInstrInfo.td

 }
 
 def SDTSPcmpicc :
 SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;
 def SDTSPcmpfcc :
 SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisSameAs<0, 1>]>;
 def SDTSPbrcc :
 SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
+def SDTSPbrreg :
+SDTypeProfile<0, 3, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>, SDTCisVT<2, i64>]>;
 def SDTSPselectcc :
 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>]>;
 def SDTSPselectreg :
 SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>, SDTCisVT<4, i64>]>;
 def SDTSPFTOI :
 SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>;
 def SDTSPITOF :
 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>;

 def SPcmpicc : SDNode<"SPISD::CMPICC", SDTSPcmpicc, [SDNPOutGlue]>;
 def SPcmpfcc : SDNode<"SPISD::CMPFCC", SDTSPcmpfcc, [SDNPOutGlue]>;
 def SPcmpfccv9 : SDNode<"SPISD::CMPFCC_V9", SDTSPcmpfcc, [SDNPOutGlue]>;
 def SPbricc : SDNode<"SPISD::BRICC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
 def SPbpicc : SDNode<"SPISD::BPICC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
 def SPbpxcc : SDNode<"SPISD::BPXCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
 def SPbrfcc : SDNode<"SPISD::BRFCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
 def SPbrfccv9 : SDNode<"SPISD::BRFCC_V9", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
+def SPbrreg : SDNode<"SPISD::BR_REG", SDTSPbrreg, [SDNPHasChain, SDNPInGlue]>;
 
 def SPhi    : SDNode<"SPISD::Hi", SDTIntUnaryOp>;
 def SPlo    : SDNode<"SPISD::Lo", SDTIntUnaryOp>;
 
 def SPftoi  : SDNode<"SPISD::FTOI", SDTSPFTOI>;
 def SPitof  : SDNode<"SPISD::ITOF", SDTSPITOF>;
 def SPftox  : SDNode<"SPISD::FTOX", SDTSPFTOX>;
 def SPxtof  : SDNode<"SPISD::XTOF", SDTSPXTOF>;

llvm/test/CodeGen/SPARC/branches-relax.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=sparc64 -sparc-bpcc-offset-bits=4 | FileCheck --check-prefix=SPARC64 %s
+; RUN: llc < %s -mtriple=sparc64 -sparc-bpcc-offset-bits=4 -sparc-bpr-offset-bits=4 | FileCheck --check-prefix=SPARC64 %s
 
 define i32 @branch_relax_int(i32 %in) {
 ; SPARC64-LABEL: branch_relax_int:
 ; SPARC64:         .cfi_startproc
 ; SPARC64-NEXT:  ! %bb.0:
 ; SPARC64-NEXT:    save %sp, -128, %sp
 ; SPARC64-NEXT:    .cfi_def_cfa_register %fp
 ; SPARC64-NEXT:    .cfi_window_save
true:
   call void asm sideeffect "nop\0A\09nop\0A\09nop\0A\09nop\0A\09nop\0A\09nop\0A\09nop\0A\09nop", ""()
   ret i32 4
 
 false:
   call void asm sideeffect "nop\0A\09nop\0A\09nop\0A\09nop\0A\09nop\0A\09nop\0A\09nop\0A\09nop", ""()
   ret i32 0
 }
 
+define i64 @branch_relax_reg(i64 %in) {
+; SPARC64-LABEL: branch_relax_reg:
+; SPARC64:         .cfi_startproc
+; SPARC64-NEXT:  ! %bb.0:
+; SPARC64-NEXT:    save %sp, -128, %sp
+; SPARC64-NEXT:    .cfi_def_cfa_register %fp
+; SPARC64-NEXT:    .cfi_window_save
+; SPARC64-NEXT:    .cfi_register %o7, %i7
+; SPARC64-NEXT:    brnz %i0, .LBB1_1
+; SPARC64-NEXT:    nop
+; SPARC64-NEXT:    ba .LBB1_2
+; SPARC64-NEXT:    nop
+; SPARC64-NEXT:  .LBB1_1: ! %false
+; SPARC64-NEXT:    !APP
+; SPARC64-NEXT:    nop
+; SPARC64-NEXT:    nop
+; SPARC64-NEXT:    nop
+; SPARC64-NEXT:    nop
+; SPARC64-NEXT:    nop
+; SPARC64-NEXT:    nop
+; SPARC64-NEXT:    nop
+; SPARC64-NEXT:    nop
+; SPARC64-NEXT:    !NO_APP
+; SPARC64-NEXT:    ret
+; SPARC64-NEXT:    restore %g0, %g0, %o0
+; SPARC64-NEXT:  .LBB1_2: ! %true
+; SPARC64-NEXT:    mov 4, %i0
+; SPARC64-NEXT:    !APP
+; SPARC64-NEXT:    nop
+; SPARC64-NEXT:    nop
+; SPARC64-NEXT:    nop
+; SPARC64-NEXT:    nop
+; SPARC64-NEXT:    nop
+; SPARC64-NEXT:    nop
+; SPARC64-NEXT:    nop
+; SPARC64-NEXT:    nop
+; SPARC64-NEXT:    !NO_APP
+; SPARC64-NEXT:    ret
+; SPARC64-NEXT:    restore
+  %tst = icmp eq i64 %in, 0
+  br i1 %tst, label %true, label %false
+
+true:
+  call void asm sideeffect "nop\0A\09nop\0A\09nop\0A\09nop\0A\09nop\0A\09nop\0A\09nop\0A\09nop", ""()
+  ret i64 4
+
+false:
+  call void asm sideeffect "nop\0A\09nop\0A\09nop\0A\09nop\0A\09nop\0A\09nop\0A\09nop\0A\09nop", ""()
+  ret i64 0
+}
+
 define float @branch_relax_float(float %in) {
 ; SPARC64-LABEL: branch_relax_float:
 ; SPARC64:         .cfi_startproc
 ; SPARC64-NEXT:  ! %bb.0:
 ; SPARC64-NEXT:    save %sp, -128, %sp
 ; SPARC64-NEXT:    .cfi_def_cfa_register %fp
 ; SPARC64-NEXT:    .cfi_window_save
 ; SPARC64-NEXT:    .cfi_register %o7, %i7
-; SPARC64-NEXT:    sethi %h44(.LCPI1_0), %i0
-; SPARC64-NEXT:    add %i0, %m44(.LCPI1_0), %i0
+; SPARC64-NEXT:    sethi %h44(.LCPI2_0), %i0
+; SPARC64-NEXT:    add %i0, %m44(.LCPI2_0), %i0
 ; SPARC64-NEXT:    sllx %i0, 12, %i0
-; SPARC64-NEXT:    ld [%i0+%l44(.LCPI1_0)], %f0
+; SPARC64-NEXT:    ld [%i0+%l44(.LCPI2_0)], %f0
 ; SPARC64-NEXT:    fcmps %fcc0, %f1, %f0
-; SPARC64-NEXT:    fbe %fcc0, .LBB1_1
+; SPARC64-NEXT:    fbe %fcc0, .LBB2_1
 ; SPARC64-NEXT:    nop
-; SPARC64-NEXT:    ba .LBB1_2
+; SPARC64-NEXT:    ba .LBB2_2
 ; SPARC64-NEXT:    nop
-; SPARC64-NEXT:  .LBB1_1: ! %true
-; SPARC64-NEXT:    sethi %h44(.LCPI1_1), %i0
-; SPARC64-NEXT:    add %i0, %m44(.LCPI1_1), %i0
+; SPARC64-NEXT:  .LBB2_1: ! %true
+; SPARC64-NEXT:    sethi %h44(.LCPI2_1), %i0
+; SPARC64-NEXT:    add %i0, %m44(.LCPI2_1), %i0
 ; SPARC64-NEXT:    sllx %i0, 12, %i0
-; SPARC64-NEXT:    ld [%i0+%l44(.LCPI1_1)], %f0
+; SPARC64-NEXT:    ld [%i0+%l44(.LCPI2_1)], %f0
 ; SPARC64-NEXT:    !APP
 ; SPARC64-NEXT:    nop
 ; SPARC64-NEXT:    nop
 ; SPARC64-NEXT:    nop
 ; SPARC64-NEXT:    nop
 ; SPARC64-NEXT:    nop
 ; SPARC64-NEXT:    nop
 ; SPARC64-NEXT:    nop
 ; SPARC64-NEXT:    nop
 ; SPARC64-NEXT:    !NO_APP
 ; SPARC64-NEXT:    ret
 ; SPARC64-NEXT:    restore
-; SPARC64-NEXT:  .LBB1_2: ! %false
+; SPARC64-NEXT:  .LBB2_2: ! %false
 ; SPARC64-NEXT:    !APP
 ; SPARC64-NEXT:    nop
 ; SPARC64-NEXT:    nop
 ; SPARC64-NEXT:    nop
 ; SPARC64-NEXT:    nop
 ; SPARC64-NEXT:    nop
 ; SPARC64-NEXT:    nop
 ; SPARC64-NEXT:    nop

llvm/test/CodeGen/SPARC/branches-v9.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=sparcv9 -disable-sparc-leaf-proc | FileCheck %s
 
-;; 1. When emitting code for v9, branches should always explicitly specify
+;; 1. When emitting code for v9, CCR branches should always explicitly specify
 ;;    %icc or %xcc.
-;; 2. There should never be a `ba` that jumps into two instructions immediately
+;; 2. Branches on the result of a 64-bit compare with constant zero should be
+;;    lowered into an instruction in the BPr class (§A.3 in V9 spec).
+;; 3. There should never be a `ba` that jumps into two instructions immediately
 ;;    following it.
 
-define void @i(i32 signext %sel) {
-; CHECK-LABEL: i:
+define void @bricc(i32 signext %sel) {
+; CHECK-LABEL: bricc:
 ; CHECK:         .cfi_startproc
 ; CHECK-NEXT:  ! %bb.0: ! %entry
 ; CHECK-NEXT:    save %sp, -176, %sp
 ; CHECK-NEXT:    .cfi_def_cfa_register %fp
 ; CHECK-NEXT:    .cfi_window_save
 ; CHECK-NEXT:    .cfi_register %o7, %i7
 ; CHECK-NEXT:    cmp %i0, 0
 ; CHECK-NEXT:    be %icc, .LBB0_2
tbb:
   call void @f1()
   br label %end
 
 end:
   call void @f3()
   ret void
 }
 
-define void @l(i64 %sel) {
-; CHECK-LABEL: l:
+define void @brxcc(i64 %sel) {
+; CHECK-LABEL: brxcc:
 ; CHECK:         .cfi_startproc
 ; CHECK-NEXT:  ! %bb.0: ! %entry
 ; CHECK-NEXT:    save %sp, -176, %sp
 ; CHECK-NEXT:    .cfi_def_cfa_register %fp
 ; CHECK-NEXT:    .cfi_window_save
 ; CHECK-NEXT:    .cfi_register %o7, %i7
-; CHECK-NEXT:    cmp %i0, 0
-; CHECK-NEXT:    be %xcc, .LBB1_2
+; CHECK-NEXT:    cmp %i0, 1
+; CHECK-NEXT:    bne %xcc, .LBB1_2
+; CHECK-NEXT:    nop
+; CHECK-NEXT:  ! %bb.1: ! %tbb
+; CHECK-NEXT:    call f1
+; CHECK-NEXT:    nop
+; CHECK-NEXT:    ba .LBB1_3
+; CHECK-NEXT:    nop
+; CHECK-NEXT:  .LBB1_2: ! %fbb
+; CHECK-NEXT:    call f2
+; CHECK-NEXT:    nop
+; CHECK-NEXT:  .LBB1_3: ! %end
+; CHECK-NEXT:    call f3
+; CHECK-NEXT:    nop
+; CHECK-NEXT:    ret
+; CHECK-NEXT:    restore
+entry:
+  ;; Using 1 here because compares with zero
+  ;; will be lowered into a `brz`, not `be`.
+  %cond = icmp eq i64 %sel, 1
+  br i1 %cond, label %tbb, label %fbb
+
+fbb:
+  call void @f2()
+  br label %end
+
+tbb:
+  call void @f1()
+  br label %end
+
+end:
+  call void @f3()
+  ret void
+}
+
+define void @brreg(i64 %sel) {
+; CHECK-LABEL: brreg:
+; CHECK:         .cfi_startproc
+; CHECK-NEXT:  ! %bb.0: ! %entry
+; CHECK-NEXT:    save %sp, -176, %sp
+; CHECK-NEXT:    .cfi_def_cfa_register %fp
+; CHECK-NEXT:    .cfi_window_save
+; CHECK-NEXT:    .cfi_register %o7, %i7
+; CHECK-NEXT:    brz %i0, .LBB2_2
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:  ! %bb.1: ! %fbb
 ; CHECK-NEXT:    call f2
 ; CHECK-NEXT:    nop
-; CHECK-NEXT:    ba .LBB1_3
+; CHECK-NEXT:    ba .LBB2_3
 ; CHECK-NEXT:    nop
-; CHECK-NEXT:  .LBB1_2: ! %tbb
+; CHECK-NEXT:  .LBB2_2: ! %tbb
 ; CHECK-NEXT:    call f1
 ; CHECK-NEXT:    nop
-; CHECK-NEXT:  .LBB1_3: ! %end
+; CHECK-NEXT:  .LBB2_3: ! %end
 ; CHECK-NEXT:    call f3
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    ret
 ; CHECK-NEXT:    restore
 entry:
   %cond = icmp eq i64 %sel, 0
   br i1 %cond, label %tbb, label %fbb
 

llvm/test/CodeGen/SPARC/missinglabel.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -verify-machineinstrs | FileCheck %s
 
 target datalayout = "E-m:e-i64:64-n32:64-S128"
 target triple = "sparc64-unknown-linux-gnu"
 
 define void @f(i64 %a0) align 2 {
 ; CHECK-LABEL: f:
 ; CHECK:         .cfi_startproc
 ; CHECK-NEXT:  ! %bb.0: ! %entry
-; CHECK-NEXT:    cmp %o0, 0
-; CHECK-NEXT:    be %xcc, .LBB0_2
+; CHECK-NEXT:    brz %o0, .LBB0_2
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:  ! %bb.1: ! %cond.false
 ; CHECK-NEXT:  .LBB0_2: ! %targetblock
 ; CHECK-NEXT:    cmp %g0, 0
 ; CHECK-NEXT:    bne %icc, .LBB0_4
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:  ! %bb.3: ! %cond.false.i83
 ; CHECK-NEXT:  .LBB0_4: ! %exit.i85