[PowerPC] Replace PPCISD::VABSD cases with generic ISD::ABDU(X,Y) node

[RKSimon]

Summary

A move towards using the generic ISD::ABDU nodes on more backends

Also support ISD::ABDS for v4i32 types using the existing signbit flip trick

PowerPC has a select(icmp_ugt(x,y),sub(x,y),sub(y,x)) -> abdu(x,y) that I intend to move to DAGCombiner in a future patch.

I don't think the PPCISD::VABSD(X,Y,1) v4i32 combine was legal (at least alive2 didn't think so) - so I've removed it.

[nemanjai]

Thanks for updating this. I am just curious, do the combines you removed just end up getting combined to a VSELECT?

[RKSimon]

In D142313#4075615, @nemanjai wrote:

Thanks for updating this. I am just curious, do the combines you removed just end up getting combined to a VSELECT?

@dmgreen added them to DAGCombiner as part of adding the generic abds/abdu nodes

What should be done with the PPCISD::VABSD nodes? They can only be used for the PPCISD::VABSD(X, 1) case now - should they be simplified/renamed?

[RKSimon]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

17671

I'm wondering if this is actually correct? If there had been SIGN_EXTEND/SIGN_EXTEND_VECTOR_INREG equivalent nodes to the previous ABDU pattern then this would be ABSD.

https://alive2.llvm.org/ce/z/k8wpeF

[RKSimon]

Adds support for ISD::ABDS for v4i32 types using the existing signbit flip trick and remove the PPCISD::VABSD node type entirely

I've tentatively removed the "(abs (sub a, b) --> (vabsd a b 1))" fold as afaict its not correct: https://alive2.llvm.org/ce/z/jc2hLU

[RKSimon]

ping?

[RKSimon]

ping2?

llvm/test/CodeGen/PowerPC/ppc64-P9-vabsd.ll

1249 ↗

(On Diff #492800)

if we replace this with sub nsw then the fold is legal

[nemanjai]

LGTM. Thanks for cleaning this up and sorry about the delay in reviewing it.

llvm/test/CodeGen/PowerPC/ppc64-P9-vabsd.ll

1249 ↗

(On Diff #492800)

I suppose the test case then becomes equivalent to sub_absv_32() other than the use of the vmaxsw intrinsic. I think we can just add the flag so the test case shows the desired code-gen.

[lkail]

Hi @RKSimon

The ABS(SUB(X,Y)) -> PPCISD::VABSD(X,Y,1) v4i32 combine wasn't legal (https://alive2.llvm.org/ce/z/jc2hLU) - so I've removed it, having already added the legal sub nsw tests equivalent.

For case where X and Y are both zero extended from other values, the original transformation looks still correct. See https://alive2.llvm.org/ce/z/LWaEEg.