Revert "[AArch64][v8.3A] Avoid inserting implicit landing pads (PACI*SP)"

[eugenis]

Summary

Linux kernel sets SCTRL_EL1.BT0 and BT1 to 1 unconditionally, which
makes PACIASP equivalent to BTI C + PACIA LR,SP.

Use the shorter instruction sequence by default.

I'm not aware of anyone who needs the opposite. They are welcome to
revert to the current behavior under a subtarget feature or an
environment check.

This reverts commit 571c8c5263a79293aaadae07b11feb36726eaf53.

[danielkiss]

Thanks for the patch. LGTM.

llvm/lib/Target/AArch64/AArch64FrameLowering.cpp

void AArch64FrameLowering::emitPrologue(MachineFunction &MF,
   DebugLoc DL;
 
   const auto &MFnI = *MF.getInfo<AArch64FunctionInfo>();
   if (needsShadowCallStackPrologueEpilogue(MF))
     emitShadowCallStackPrologue(*TII, MF, MBB, MBBI, DL, NeedsWinCFI,
                                 MFnI.needsDwarfUnwindInfo(MF));
 
   if (MFnI.shouldSignReturnAddress(MF)) {
-    unsigned PACI;
     if (MFnI.shouldSignWithBKey()) {
       BuildMI(MBB, MBBI, DL, TII->get(AArch64::EMITBKEY))
           .setMIFlag(MachineInstr::FrameSetup);
-      // No SEH opcode for this one; it doesn't materialize into an
-      // instruction on Windows.
-      PACI = Subtarget.hasPAuth() ? AArch64::PACIB : AArch64::PACIBSP;
-    } else {
-      PACI = Subtarget.hasPAuth() ? AArch64::PACIA : AArch64::PACIASP;
-    }
+    }
+
+    BuildMI(MBB, MBBI, DL,
+            TII->get(MFnI.shouldSignWithBKey() ? AArch64::PACIBSP
+                                               : AArch64::PACIASP))
+        .setMIFlag(MachineInstr::FrameSetup);
 
-    auto MI = BuildMI(MBB, MBBI, DL, TII->get(PACI));
-    if (Subtarget.hasPAuth())
-      MI.addReg(AArch64::LR, RegState::Define)
-          .addReg(AArch64::LR)
-          .addReg(AArch64::SP, RegState::InternalRead);
-    MI.setMIFlag(MachineInstr::FrameSetup);
     if (EmitCFI) {
       unsigned CFIIndex =
           MF.addFrameInst(MCCFIInstruction::createNegateRAState(nullptr));
       BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
           .addCFIIndex(CFIIndex)
           .setMIFlags(MachineInstr::FrameSetup);
     } else if (NeedsWinCFI) {
       HasWinCFI = true;

llvm/lib/Target/AArch64/AArch64InstrInfo.cpp

for (MachineInstr &MI : MBB) {
     // checked if this instruction was legal to outline.
     int64_t NewImm = (Offset + 16) / (int64_t)Scale.getFixedValue();
     StackOffsetOperand.setImm(NewImm);
   }
 }
 
 static void signOutlinedFunction(MachineFunction &MF, MachineBasicBlock &MBB,
                                  bool ShouldSignReturnAddr,
-                                 bool ShouldSignReturnAddrWithAKey) {
+                                 bool ShouldSignReturnAddrWithBKey) {
   if (ShouldSignReturnAddr) {
     MachineBasicBlock::iterator MBBPAC = MBB.begin();
     MachineBasicBlock::iterator MBBAUT = MBB.getFirstTerminator();
     const AArch64Subtarget &Subtarget = MF.getSubtarget<AArch64Subtarget>();
     const TargetInstrInfo *TII = Subtarget.getInstrInfo();
     DebugLoc DL;
 
     if (MBBAUT != MBB.end())
       DL = MBBAUT->getDebugLoc();
 
     // At the very beginning of the basic block we insert the following
     // depending on the key type
     //
     // a_key:                   b_key:
     //    PACIASP                   EMITBKEY
     //    CFI_INSTRUCTION           PACIBSP
     //                              CFI_INSTRUCTION
-    unsigned PACI;
-    if (ShouldSignReturnAddrWithAKey) {
-      PACI = Subtarget.hasPAuth() ? AArch64::PACIA : AArch64::PACIASP;
-    } else {
+    if (ShouldSignReturnAddrWithBKey) {
       BuildMI(MBB, MBBPAC, DebugLoc(), TII->get(AArch64::EMITBKEY))
           .setMIFlag(MachineInstr::FrameSetup);
-      PACI = Subtarget.hasPAuth() ? AArch64::PACIB : AArch64::PACIBSP;
     }
 
-    auto MI = BuildMI(MBB, MBBPAC, DebugLoc(), TII->get(PACI));
-    if (Subtarget.hasPAuth())
-      MI.addReg(AArch64::LR, RegState::Define)
-          .addReg(AArch64::LR)
-          .addReg(AArch64::SP, RegState::InternalRead);
-    MI.setMIFlag(MachineInstr::FrameSetup);
+    BuildMI(MBB, MBBPAC, DebugLoc(),
+            TII->get(ShouldSignReturnAddrWithBKey ? AArch64::PACIBSP
+                                                  : AArch64::PACIASP))
+        .setMIFlag(MachineInstr::FrameSetup);
 
     if (MF.getInfo<AArch64FunctionInfo>()->needsDwarfUnwindInfo(MF)) {
       unsigned CFIIndex =
           MF.addFrameInst(MCCFIInstruction::createNegateRAState(nullptr));
       BuildMI(MBB, MBBPAC, DebugLoc(), TII->get(AArch64::CFI_INSTRUCTION))
           .addCFIIndex(CFIIndex)
           .setMIFlags(MachineInstr::FrameSetup);
     }
 
     // If v8.3a features are available we can replace a RET instruction by
     // RETAA or RETAB and omit the AUT instructions. In this case the
     // DW_CFA_AARCH64_negate_ra_state can't be emitted.
     if (Subtarget.hasPAuth() && MBBAUT != MBB.end() &&
         MBBAUT->getOpcode() == AArch64::RET) {
       BuildMI(MBB, MBBAUT, DL,
-              TII->get(ShouldSignReturnAddrWithAKey ? AArch64::RETAA
-                                                    : AArch64::RETAB))
+              TII->get(ShouldSignReturnAddrWithBKey ? AArch64::RETAB
+                                                    : AArch64::RETAA))
           .copyImplicitOps(*MBBAUT);
       MBB.erase(MBBAUT);
     } else {
       BuildMI(MBB, MBBAUT, DL,
-              TII->get(ShouldSignReturnAddrWithAKey ? AArch64::AUTIASP
-                                                    : AArch64::AUTIBSP))
+              TII->get(ShouldSignReturnAddrWithBKey ? AArch64::AUTIBSP
+                                                    : AArch64::AUTIASP))
           .setMIFlag(MachineInstr::FrameDestroy);
       unsigned CFIIndexAuth =
           MF.addFrameInst(MCCFIInstruction::createNegateRAState(nullptr));
       BuildMI(MBB, MBBAUT, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
           .addCFIIndex(CFIIndexAuth)
           .setMIFlags(MachineInstr::FrameDestroy);
     }
   }
void AArch64InstrInfo::buildOutlinedFrame(
 
   // If a bunch of candidates reach this point they must agree on their return
   // address signing. It is therefore enough to just consider the signing
   // behaviour of one of them
   const auto &MFI = *OF.Candidates.front().getMF()->getInfo<AArch64FunctionInfo>();
   bool ShouldSignReturnAddr = MFI.shouldSignReturnAddress(!IsLeafFunction);
 
   // a_key is the default
-  bool ShouldSignReturnAddrWithAKey = !MFI.shouldSignWithBKey();
+  bool ShouldSignReturnAddrWithBKey = MFI.shouldSignWithBKey();
 
   // If this is a tail call outlined function, then there's already a return.
   if (OF.FrameConstructionID == MachineOutlinerTailCall ||
       OF.FrameConstructionID == MachineOutlinerThunk) {
     signOutlinedFunction(MF, MBB, ShouldSignReturnAddr,
-                         ShouldSignReturnAddrWithAKey);
+                         ShouldSignReturnAddrWithBKey);
     return;
   }
 
   // It's not a tail call, so we have to insert the return ourselves.
 
   // LR has to be a live in so that we can return to it.
   if (!MBB.isLiveIn(AArch64::LR))
     MBB.addLiveIn(AArch64::LR);
 
   MachineInstr *ret = BuildMI(MF, DebugLoc(), get(AArch64::RET))
                           .addReg(AArch64::LR);
   MBB.insert(MBB.end(), ret);
 
   signOutlinedFunction(MF, MBB, ShouldSignReturnAddr,
-                       ShouldSignReturnAddrWithAKey);
+                       ShouldSignReturnAddrWithBKey);
 
   FI->setOutliningStyle("Function");
 
   // Did we have to modify the stack by saving the link register?
   if (OF.FrameConstructionID != MachineOutlinerDefault)
     return;
 
   // We modified the stack.

llvm/test/CodeGen/AArch64/aarch64-signedreturnaddress.ll

 ; RUN: llc < %s -mtriple=arm64-eabi -asm-verbose=false -mattr=v8.2a | FileCheck %s
 ; RUN: llc < %s -mtriple=arm64-eabi -asm-verbose=false -mattr=v8.3a | FileCheck %s --check-prefix=CHECKV83
 
-; Armv8.3-A Pointer Authetication requires a special instruction to strip the
+; Armv8.3-A Pointer Authetication requires a special intsruction to strip the
 ; pointer authentication code from the pointer.
 ; The XPACLRI instruction assembles to a hint-space instruction before Armv8.3-A
 ; therefore this instruction can be safely used for any pre Armv8.3-A architectures.
 ; On Armv8.3-A and onwards XPACI is available so use that instead.
 
 define ptr @ra0() nounwind readnone {
 entry:
 ; CHECK-LABEL: ra0:

 ; CHECK-LABEL: ra1:
 ; CHECK:          hint    #25
 ; CHECK-NEXT:     str     x30, [sp, #-16]!
 ; CHECK-NEXT:     hint    #7
 ; CHECK-NEXT:     mov     x0, x30
 ; CHECK-NEXT:     ldr     x30, [sp], #16
 ; CHECK-NEXT:     hint    #29
 ; CHECK-NEXT:     ret
-; CHECKV83:       pacia   x30, sp
+; CHECKV83:       paciasp
 ; CHECKV83-NEXT:  str     x30, [sp, #-16]!
 ; CHECKV83-NEXT:  xpaci   x30
 ; CHECKV83-NEXT:  mov     x0, x30
 ; CHECKV83-NEXT:  ldr     x30, [sp], #16
 ; CHECKV83-NEXT:  retaa
   %0 = tail call ptr @llvm.returnaddress(i32 0)
   ret ptr %0
 }
 
 attributes #0 = { "sign-return-address"="all" }
 
 declare ptr @llvm.returnaddress(i32) nounwind readnone

llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-sp-mod.ll

 ; RUN: llc -mtriple aarch64-arm-none-eabi -enable-machine-outliner \
 ; RUN:  -verify-machineinstrs %s -o - | FileCheck %s
 
 @v = common dso_local global ptr null, align 8
 
 ; CHECK-LABEL:  foo:                                    // @foo
 ; CHECK-NEXT:   // %bb.0:                               // %entry
-; CHECK-NEXT:       pacia x30, sp
+; CHECK-NEXT:       paciasp
 ; CHECK-NOT:        OUTLINED_FUNCTION_
 ; CHECK:            retaa
 define dso_local void @foo(i32 %x) #0 {
 entry:
   %0 = zext i32 %x to i64
   %vla = alloca i32, i64 %0, align 4
   store volatile ptr %vla, ptr @v, align 8
   store volatile ptr %vla, ptr @v, align 8
   store volatile ptr %vla, ptr @v, align 8
   store volatile ptr %vla, ptr @v, align 8
   store volatile ptr %vla, ptr @v, align 8
   store volatile ptr %vla, ptr @v, align 8
   ret void
 }
 
 ; CHECK-LABEL:  bar:                                    // @bar
 ; CHECK-NEXT:   // %bb.0:                               // %entry
-; CHECK-NEXT:       pacia x30, sp
+; CHECK-NEXT:       paciasp
 ; CHECK-NOT:        OUTLINED_FUNCTION_
 ; CHECK:            retaa
 define dso_local void @bar(i32 %x) #0 {
 entry:
   %0 = zext i32 %x to i64
   %vla = alloca i32, i64 %0, align 4
   store volatile ptr null, ptr @v, align 8
   store volatile ptr %vla, ptr @v, align 8

llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-subtarget.ll

 ; RUN: llc -verify-machineinstrs -enable-machine-outliner -mtriple \
 ; RUN: aarch64-arm-linux-gnu %s -o - | FileCheck %s
 
 ; Check that functions that should sign their return addresses don't get
 ; outlined if not all of the function either support v8.3a features or all of
 ; the functions don't!!
 
 define void @a() #0 {
 ; CHECK-LABEL:      a:                                     // @a
 ; CHECK:            // %bb.0:
 ; CHECK-NEXT:               .cfi_b_key_frame
-; CHECK-NEXT:               pacib x30, sp
+; CHECK-NEXT:               pacibsp
 ; CHECK-NEXT:               .cfi_negate_ra_state
 ; CHECK-NOT:                OUTLINED_FUNCTION_
   %1 = alloca i32, align 4
   %2 = alloca i32, align 4
   %3 = alloca i32, align 4
   %4 = alloca i32, align 4
   %5 = alloca i32, align 4
   %6 = alloca i32, align 4
   store i32 1, ptr %1, align 4
   store i32 2, ptr %2, align 4
   store i32 3, ptr %3, align 4
   store i32 4, ptr %4, align 4
   store i32 5, ptr %5, align 4
   store i32 6, ptr %6, align 4
 ; CHECK:                  retab
 ; CHECK-NOT:              auti[a,b]sp
   ret void
 }
 
 define void @b() #0 {
 ; CHECK-LABEL:      b:                                     // @b
 ; CHECK:            // %bb.0:
 ; CHECK-NEXT:               .cfi_b_key_frame
-; CHECK-NEXT:               pacib x30, sp
+; CHECK-NEXT:               pacibsp
 ; CHECK-NEXT:               .cfi_negate_ra_state
 ; CHECK-NOT:                OUTLINED_FUNCTION_
   %1 = alloca i32, align 4
   %2 = alloca i32, align 4
   %3 = alloca i32, align 4
   %4 = alloca i32, align 4
   %5 = alloca i32, align 4
   %6 = alloca i32, align 4

llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-v8-3.ll

 ; RUN: llc -verify-machineinstrs -enable-machine-outliner -mtriple \
 ; RUN: aarch64-arm-linux-gnu %s -o - | FileCheck %s
 
 ; Check that outlined functions use the dedicated RETAA/RETAB instructions
 ; to sign their return address if available.
 
 define void @a() #0 {
 ; CHECK-LABEL:      a:                                     // @a
 ; CHECK:            // %bb.0:
-; CHECK-NEXT:               pacib x30, sp
+; CHECK-NEXT:               pacibsp
 ; CHECK:                    bl [[OUTLINED_FUNC:OUTLINED_FUNCTION_[0-9]+]]
   %1 = alloca i32, align 4
   %2 = alloca i32, align 4
   %3 = alloca i32, align 4
   %4 = alloca i32, align 4
   %5 = alloca i32, align 4
   %6 = alloca i32, align 4
   store i32 1, ptr %1, align 4
   store i32 2, ptr %2, align 4
   store i32 3, ptr %3, align 4
   store i32 4, ptr %4, align 4
   store i32 5, ptr %5, align 4
   store i32 6, ptr %6, align 4
 ; CHECK:                  retab
-; CHECK-NOT:              auti
+; CHECK-NOT:              auti[a,b]sp
   ret void
 }
 
 define void @b() #0 {
 ; CHECK-LABEL:      b:                                     // @b
 ; CHECK:            // %bb.0:
-; CHECK-NEXT:               pacib x30, sp
+; CHECK-NEXT:               pacibsp
 ; CHECK:                    bl OUTLINED_FUNC
   %1 = alloca i32, align 4
   %2 = alloca i32, align 4
   %3 = alloca i32, align 4
   %4 = alloca i32, align 4
   %5 = alloca i32, align 4
   %6 = alloca i32, align 4
   store i32 1, ptr %1, align 4
   store i32 2, ptr %2, align 4
   store i32 3, ptr %3, align 4
   store i32 4, ptr %4, align 4
   store i32 5, ptr %5, align 4
   store i32 6, ptr %6, align 4
 ; CHECK:                  retab
-; CHECK-NOT:              auti
+; CHECK-NOT:              auti[a,b]sp
   ret void
 }
 
 define void @c() #0 {
 ; CHECK-LABEL:      c:                                     // @c
 ; CHECK:            // %bb.0:
-; CHECK-NEXT:               pacib x30, sp
+; CHECK-NEXT:               pacibsp
 ; CHECK:                    bl OUTLINED_FUNC
   %1 = alloca i32, align 4
   %2 = alloca i32, align 4
   %3 = alloca i32, align 4
   %4 = alloca i32, align 4
   %5 = alloca i32, align 4
   %6 = alloca i32, align 4
   store i32 1, ptr %1, align 4
   store i32 2, ptr %2, align 4
   store i32 3, ptr %3, align 4
   store i32 4, ptr %4, align 4
   store i32 5, ptr %5, align 4
   store i32 6, ptr %6, align 4
 ; CHECK:                  retab
-; CHECK-NOT:              auti
+; CHECK-NOT:              auti[a,b]sp
   ret void
 }
 
 attributes #0 = { "sign-return-address"="all"
                   "sign-return-address-key"="b_key"
                   "target-features"="+v8.3a"
                   nounwind }
 
 ; CHECK:            OUTLINED_FUNC
 ; CHECK:            // %bb.0:
-; CHECK-NEXT:               pacib x30, sp
+; CHECK-NEXT:               pacibsp
 ; CHECK:                    retab
 ; CHECK-NOT:                auti[a,b]sp

llvm/test/CodeGen/AArch64/pacbti-llvm-generated-funcs-2.ll

 ;; RUN: llc --mattr=+v8.3a %s -o - | FileCheck %s
 target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
 target triple = "aarch64-unknown-linux"
 
 @__llvm_gcov_ctr = internal global [1 x i64] zeroinitializer
 @0 = private unnamed_addr constant [7 x i8] c"m.gcda\00", align 1
 @llvm.global_ctors = appending global [1 x { i32, ptr, ptr }] [{ i32, ptr, ptr } { i32 0, ptr @__llvm_gcov_init, ptr null }]
 
 define dso_local i32 @f() local_unnamed_addr #0 {
 entry:
   ret i32 0
 }
 ;; CHECK-LABEL: f:
-;; CHECK: pacib x30, sp
+;; CHECK: pacibsp
 
 declare void @llvm_gcda_start_file(ptr, i32, i32) local_unnamed_addr
 
 declare void @llvm_gcda_emit_function(i32, i32, i32) local_unnamed_addr
 
 declare void @llvm_gcda_emit_arcs(i32, ptr) local_unnamed_addr
 
 declare void @llvm_gcda_summary_info() local_unnamed_addr
 
 declare void @llvm_gcda_end_file() local_unnamed_addr
 
 define internal void @__llvm_gcov_writeout() unnamed_addr #1 {
 entry:
   tail call void @llvm_gcda_start_file(ptr @0, i32 875575338, i32 0)
   tail call void @llvm_gcda_emit_function(i32 0, i32 0, i32 0)
   tail call void @llvm_gcda_emit_arcs(i32 1, ptr @__llvm_gcov_ctr)
   tail call void @llvm_gcda_summary_info()
   tail call void @llvm_gcda_end_file()
   ret void
 }
 ;; CHECK-LABEL: __llvm_gcov_writeout:
 ;; CHECK:       .cfi_b_key_frame
-;; CHECK-NEXT:  pacib x30, sp
+;; CHECK-NEXT:  pacibsp
 ;; CHECK-NEXT: .cfi_negate_ra_state
 
 define internal void @__llvm_gcov_reset() unnamed_addr #2 {
 entry:
   store i64 0, ptr @__llvm_gcov_ctr, align 8
   ret void
 }
 ;; CHECK-LABEL: __llvm_gcov_reset:
-;; CHECK:       pacib x30, sp
+;; CHECK:       pacibsp
 
 declare void @llvm_gcov_init(ptr, ptr) local_unnamed_addr
 
 define internal void @__llvm_gcov_init() unnamed_addr #1 {
 entry:
   tail call void @llvm_gcov_init(ptr nonnull @__llvm_gcov_writeout, ptr nonnull @__llvm_gcov_reset)
   ret void
 }
 ;; CHECK-LABEL: __llvm_gcov_init:
 ;; CHECK:      .cfi_b_key_frame
-;; CHECK-NEXT:  pacib x30, sp
+;; CHECK-NEXT:  pacibsp
 ;; CHECK-NEXT: .cfi_negate_ra_state
 
 attributes #0 = { norecurse nounwind readnone "sign-return-address"="all" "sign-return-address-key"="b_key" }
 attributes #1 = { noinline }
 attributes #2 = { nofree noinline norecurse nounwind writeonly }
 
 !llvm.module.flags = !{!0, !1, !2, !3, !4, !5}
 
 !0 = !{i32 2, !"Debug Info Version", i32 3}
 !1 = !{i32 1, !"wchar_size", i32 4}
 !2 = !{i32 8, !"branch-target-enforcement", i32 0}
 !3 = !{i32 8, !"sign-return-address", i32 1}
 !4 = !{i32 8, !"sign-return-address-all", i32 1}
 !5 = !{i32 8, !"sign-return-address-with-bkey", i32 1}

llvm/test/CodeGen/AArch64/pacbti-module-attrs.ll

 
 define i32 @f2(i32 %x) #2 {
 entry:
   %call = tail call i32 @g(i32 %x) #5
   %add = add nsw i32 %call, 1
   ret i32 %add
 }
 ;; CHECK-LABEL: f2:
-;; CHECK:       pacia x30, sp
+;; CHECK:       paciasp
 ;; CHECK:       retaa
 
 define i32 @f3(i32 %x) #3 {
 entry:
   %call = tail call i32 @g(i32 %x) #5
   %add = add nsw i32 %call, 1
   ret i32 %add
 }
 ;; CHECK-LABEL: f3:
-;; CHECK:       pacib x30, sp
+;; CHECK:       pacibsp
 ;; CHECK:       retab
 
 define i32 @f4(i32 %x) #4 {
 entry:
   ret i32 1
 }
 ;; CHECK-LABEL: f4:
-;; CHECK:       pacia x30, sp
+;; CHECK:       paciasp
 ;; CHECK:       retaa
 
 define i32 @f5(i32 %x) #5 {
 entry:
   %call = tail call i32 @g(i32 %x) #5
   %add = add nsw i32 %call, 1
   ret i32 %add
 }
 ;; CHECK-LABEL: f5:
-;; CHECK:       pacia x30, sp
+;; CHECK:       paciasp
 ;; CHECK:       retaa
 
 attributes #0 = { nounwind "branch-target-enforcement"="false" "sign-return-address"="none" }
 attributes #1 = { nounwind "branch-target-enforcement"="true"  "sign-return-address"="none" }
 attributes #2 = { nounwind "branch-target-enforcement"="false" "sign-return-address"="non-leaf" "sign-return-address-key"="a_key" }
 attributes #3 = { nounwind "branch-target-enforcement"="false" "sign-return-address"="non-leaf" "sign-return-address-key"="b_key" }
 attributes #4 = { nounwind "branch-target-enforcement"="false" "sign-return-address"="all" "sign-return-address-key"="a_key" }
 attributes #5 = { nounwind }
 
 !llvm.module.flags = !{!0, !1, !2, !3, !4}
 
 !0 = !{i32 1, !"wchar_size", i32 4}
 !1 = !{i32 8, !"branch-target-enforcement", i32 1}
 !2 = !{i32 8, !"sign-return-address", i32 1}
 !3 = !{i32 8, !"sign-return-address-all", i32 0}
 !4 = !{i32 8, !"sign-return-address-with-bkey", i32 0}

llvm/test/CodeGen/AArch64/sign-return-address-cfi-negate-ra-state.ll

 ; RUN: llc -mtriple=aarch64-none-eabi < %s | FileCheck --check-prefixes CHECK,CHECK-V8A %s
 ; RUN: llc -mtriple=aarch64-none-eabi -mattr=v8.3a < %s | FileCheck --check-prefixes CHECK,CHECK-V83A %s
 ; RUN: llc -mtriple=aarch64-none-eabi -filetype=obj -o - <%s | llvm-dwarfdump -v - | FileCheck --check-prefix=CHECK-DUMP %s
 
 @.str = private unnamed_addr constant [15 x i8] c"some exception\00", align 1
 @_ZTIPKc = external dso_local constant ptr
 
 ; CHECK: @_Z3fooi
 ; CHECK-V8A: hint #25
-; CHECK-V83A: pacia x30, sp
+; CHECK-V83A: paciasp
 ; CHECK-NEXT: .cfi_negate_ra_state
 ; CHECK-NOT: .cfi_negate_ra_state
 define dso_local i32 @_Z3fooi(i32 %x) #0 {
 entry:
   %retval = alloca i32, align 4
   %x.addr = alloca i32, align 4
   store i32 %x, ptr %x.addr, align 4
   %exception = call ptr @__cxa_allocate_exception(i64 8) #1

llvm/test/CodeGen/AArch64/sign-return-address.ll

 }
 
 ; CHECK-LABEL: @leaf_sign_all
 ; CHECK:       hint #25
 ; CHECK-NEXT:  .cfi_negate_ra_state
 ; CHECK:       hint #29
 ; CHECK-NEXT:  .cfi_negate_ra_state
 ; CHECK:       ret
-; CHECK-V83A:  pacia x30, sp
+; CHECK-V83A:  paciasp
 ; CHECK-V83A:  retaa
 define i32 @leaf_sign_all(i32 %x) "sign-return-address"="all" {
   ret i32 %x
 }
 
 ; CHECK:             @leaf_clobbers_lr
 ; CHECK:             hint #25
 ; CHECK-NEXT:        .cfi_negate_ra_state
-; CHECK-V83A:        pacia x30, sp
+; CHECK-V83A:        paciasp
 ; CHECK, CHECK-V83A: str x30, [sp, #-16]!
 ; CHECK, CHECK-V83A: ldr x30, [sp], #16
 ; CHECK:             hint #29
 ; CHECK-NEXT:        .cfi_negate_ra_state
 ; CHECK:             ret
 ; CHECK-V32A-NEXT:   retaa
 define i64 @leaf_clobbers_lr(i64 %x) "sign-return-address"="non-leaf"  {
   call void asm sideeffect "mov x30, $0", "r,~{lr}"(i64 %x) #1
   ret i64 %x
 }
 
 declare i32 @foo(i32)
 
 ; CHECK:      @non_leaf_sign_all
 ; CHECK:      hint #25
 ; CHECK-NEXT: .cfi_negate_ra_state
 ; CHECK:      hint #29
 ; CHECK-NEXT: .cfi_negate_ra_state
 ; CHECK:      ret
-; CHECK-V83A: pacia x30, sp
+; CHECK-V83A: paciasp
 ; CHECK-V83A: retaa
 define i32 @non_leaf_sign_all(i32 %x) "sign-return-address"="all" {
   %call = call i32 @foo(i32 %x)
   ret i32 %call
 }
 
 ; CHECK:             @non_leaf_sign_non_leaf
 ; CHECK:             hint #25
 ; CHECK-NEXT:        .cfi_negate_ra_state
-; CHECK-V83A:        pacia x30, sp
+; CHECK-V83A:        paciasp
 ; CHECK, CHECK-V83A: str x30, [sp, #-16]!
 ; CHECK, CHECK-V83A: ldr x30, [sp], #16
 ; CHECK:             hint #29
 ; CHECK-NEXT:        .cfi_negate_ra_state
 ; CHECK:             ret
 ; CHECK-V83A:        retaa
 define i32 @non_leaf_sign_non_leaf(i32 %x) "sign-return-address"="non-leaf"  {
   %call = call i32 @foo(i32 %x)
   ret i32 %call
 }
 
 ; CHECK-LABEL: @non_leaf_scs
 ; CHECK-NOT:   retaa
 define i32 @non_leaf_scs(i32 %x) "sign-return-address"="non-leaf" shadowcallstack "target-features"="+v8.3a,+reserve-x18"  {
   %call = call i32 @foo(i32 %x)
   ret i32 %call
 }
 
 ; CHECK-LABEL: @leaf_sign_all_v83
-; CHECK:        pacia x30, sp
+; CHECK: paciasp
 ; CHECK-NEXT:  .cfi_negate_ra_state
-; CHECK-NOT:   ret
-; CHECK:       retaa
-; CHECK-NOT:   ret
+; CHECK-NOT: ret
+; CHECK: retaa
+; CHECK-NOT: ret
 define i32 @leaf_sign_all_v83(i32 %x) "sign-return-address"="all" "target-features"="+v8.3a" {
   ret i32 %x
 }
 
 declare fastcc i64 @bar(i64)
 
 ; CHECK-LABEL:       @spill_lr_and_tail_call
 ; CHECK:             hint #25
 ; CHECK-NEXT:        .cfi_negate_ra_state
-; CHECK-V83A:        pacia x30, sp
+; CHECK-V83A:        paciasp
 ; CHECK-V83A-NEXT:  .cfi_negate_ra_state
 ; CHECK, CHECK-V83A: str x30, [sp, #-16]!
 ; CHECK, CHECK-V83A: ldr x30, [sp], #16
 ; CHECK-V83A:        autiasp
 ; CHECK:             hint #29
 ; CHECK-NEXT:        .cfi_negate_ra_state
 ; CHECK:             b bar
 define fastcc void @spill_lr_and_tail_call(i64 %x) "sign-return-address"="all" {
   call void asm sideeffect "mov x30, $0", "r,~{lr}"(i64 %x) #1
   tail call fastcc i64 @bar(i64 %x)
   ret void
 }
 
 ; CHECK-LABEL: @leaf_sign_all_a_key
-; CHECK:            hint #25
+; CHECK:       hint #25
 ; CHECK-NEXT:       .cfi_negate_ra_state
-; CHECK:            hint #29
+; CHECK:       hint #29
 ; CHECK-NEXT:       .cfi_negate_ra_state
-; CHECK-V83A:       pacia x30, sp
-; CHECK-V83A-NEXT:  .cfi_negate_ra_state
-; CHECK-V83A:       retaa
+; CHECK-V83A:  paciasp
+; CHECK-V83A:  retaa
 define i32 @leaf_sign_all_a_key(i32 %x) "sign-return-address"="all" "sign-return-address-key"="a_key" {
   ret i32 %x
 }
 
 ; CHECK-LABEL: @leaf_sign_all_b_key
-; CHECK:            hint #27
+; CHECK:       hint #27
 ; CHECK-NEXT:       .cfi_negate_ra_state
-; CHECK:            hint #31
+; CHECK:       hint #31
 ; CHECK-NEXT:       .cfi_negate_ra_state
-; CHECK-V83A:       pacib x30, sp
-; CHECK-V83A-NEXT:  .cfi_negate_ra_state
-; CHECK-V83A:       retab
+; CHECK-V83A:  pacibsp
+; CHECK-V83A:  retab
 define i32 @leaf_sign_all_b_key(i32 %x) "sign-return-address"="all" "sign-return-address-key"="b_key" {
   ret i32 %x
 }
 
 ; CHECK-LABEL: @leaf_sign_all_v83_b_key
-; CHECK:       pacib x30, sp
+; CHECK: pacibsp
 ; CHECK-NEXT:  .cfi_negate_ra_state
-; CHECK-NOT:   ret
-; CHECK:       retab
-; CHECK-NOT:   ret
+; CHECK-NOT: ret
+; CHECK: retab
+; CHECK-NOT: ret
 define i32 @leaf_sign_all_v83_b_key(i32 %x) "sign-return-address"="all" "target-features"="+v8.3a" "sign-return-address-key"="b_key" {
   ret i32 %x
 }
 
 ; CHECK-LABEL: @leaf_sign_all_a_key_bti
-; CHECK-NOT:        hint #34
-; CHECK:            hint #25
+; CHECK-NOT:   hint #34
+; CHECK:       hint #25
 ; CHECK-NEXT:       .cfi_negate_ra_state
-; CHECK:            hint #29
+; CHECK:       hint #29
 ; CHECK-NEXT:       .cfi_negate_ra_state
-; CHECK-V83A:       pacia x30, sp
-; CHECK-V83A-NEXT:  .cfi_negate_ra_state
-; CHECK-V83A:       retaa
+; CHECK-V83A:  paciasp
+; CHECK-V83A:  retaa
 define i32 @leaf_sign_all_a_key_bti(i32 %x) "sign-return-address"="all" "sign-return-address-key"="a_key" "branch-target-enforcement"="true"{
   ret i32 %x
 }
 
 ; CHECK-LABEL: @leaf_sign_all_b_key_bti
-; CHECK-NOT:        hint #34
-; CHECK:            hint #27
+; CHECK-NOT:   hint #34
+; CHECK:       hint #27
 ; CHECK-NEXT:       .cfi_negate_ra_state
-; CHECK:            hint #31
+; CHECK:       hint #31
 ; CHECK-NEXT:       .cfi_negate_ra_state
-; CHECK-V83A:       pacib x30, sp
-; CHECK-V83A-NEXT:  .cfi_negate_ra_state
-; CHECK-V83A:       retab
+; CHECK-V83A:  pacibsp
+; CHECK-V83A:  retab
 define i32 @leaf_sign_all_b_key_bti(i32 %x) "sign-return-address"="all" "sign-return-address-key"="b_key" "branch-target-enforcement"="true"{
   ret i32 %x
 }
 
 ; CHECK-LABEL: @leaf_sign_all_v83_b_key_bti
-; CHECK:       pacib x30, sp
+; CHECK-NOT:   hint #34
+; CHECK: pacibsp
 ; CHECK-NEXT:  .cfi_negate_ra_state
-; CHECK-NOT:   ret
-; CHECK:       retab
-; CHECK-NOT:   ret
+; CHECK-NOT: ret
+; CHECK: retab
+; CHECK-NOT: ret
 define i32 @leaf_sign_all_v83_b_key_bti(i32 %x) "sign-return-address"="all" "target-features"="+v8.3a" "sign-return-address-key"="b_key" "branch-target-enforcement"="true" {
   ret i32 %x
 }

llvm/test/CodeGen/AArch64/wineh-pac.ll

 ; CHECK-NEXT: .seh_endproc
 
 ;; For func2, check that the potentially folded autibsp+ret -> retab
 ;; is handled correctly - currently we inhibit producing retab here.
 
 ; CHECK-LABEL: func2:
 ; CHECK-NEXT: .seh_proc func2
 ; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: pacib x30, sp
+; CHECK-NEXT: pacibsp
 ; CHECK-NEXT: .seh_pac_sign_lr
 ; CHECK-NEXT: str x19, [sp, #-16]!
 ; CHECK-NEXT: .seh_save_reg_x x19, 16
 ; CHECK-NEXT: str x30, [sp, #8]
 ; CHECK-NEXT: .seh_save_reg x30, 8
 ; CHECK-NEXT: .seh_endprologue
 
 ; CHECK:      .seh_startepilogue