[LLDB][RISCV] Add RVV registers enums

[Emmmer]

Summary

RVV stands for "RISC-V V Extension", which adds 32 vector registers, and seven unprivileged CSRs (vstart, vxsat, vxrm, vcsr, vtype, vl, vlenb) to a base scalar RISC-V ISA.

The base vector extension is intended to provide general support for data-parallel execution within the 32-bit instruction encoding space, with later vector extensions supporting richer functionality for certain domains.

[DavidSpickett]

Are we going to end up with instruction emulation for RVV also? I think we'll really need another riscv specific reviewer if so. @rogfer01 Do you know anyone who could help with that?

This patch LGTM, I'm assuming it matches the relevant DWARF specs.

lldb/source/Utility/RISCV_DWARF_Registers.h

117

These previous entries were just placeholders I assume?

[Emmmer]

lldb/source/Utility/RISCV_DWARF_Registers.h

117

Yes, I want them to be named consistently with other registers, that is dwarf_<purpose>_<regnum>

[kito-cheng]

LGTM for the dwarf number part.

lldb/source/Plugins/Process/Utility/lldb-riscv-register-enums.h

enum {
   fpr_fs10_riscv = fpr_f26_riscv,
   fpr_fs11_riscv = fpr_f27_riscv,
   fpr_ft8_riscv = fpr_f28_riscv,
   fpr_ft9_riscv = fpr_f29_riscv,
   fpr_ft10_riscv = fpr_f30_riscv,
   fpr_ft11_riscv = fpr_f31_riscv,
   fpr_last_riscv = fpr_fcsr_riscv,
 
+  vpr_first_riscv = 66,
+  vpr_v0_riscv = vpr_first_riscv,
+  vpr_v1_riscv,
+  vpr_v2_riscv,
+  vpr_v3_riscv,
+  vpr_v4_riscv,
+  vpr_v5_riscv,
+  vpr_v6_riscv,
+  vpr_v7_riscv,
+  vpr_v8_riscv,
+  vpr_v9_riscv,
+  vpr_v10_riscv,
+  vpr_v11_riscv,
+  vpr_v12_riscv,
+  vpr_v13_riscv,
+  vpr_v14_riscv,
+  vpr_v15_riscv,
+  vpr_v16_riscv,
+  vpr_v17_riscv,
+  vpr_v18_riscv,
+  vpr_v19_riscv,
+  vpr_v20_riscv,
+  vpr_v21_riscv,
+  vpr_v22_riscv,
+  vpr_v23_riscv,
+  vpr_v24_riscv,
+  vpr_v25_riscv,
+  vpr_v26_riscv,
+  vpr_v27_riscv,
+  vpr_v28_riscv,
+  vpr_v29_riscv,
+  vpr_v30_riscv,
+  vpr_v31_riscv,
+  vpr_last_riscv = vpr_v31_riscv,
+
   k_num_registers_riscv
 };
 
 #endif // LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_LLDB_RISCV_REGISTER_ENUMS_H

lldb/source/Utility/RISCV_DWARF_Registers.h

enum {
   dwarf_fpr_f28,
   dwarf_fpr_f29,
   dwarf_fpr_f30,
   dwarf_fpr_f31 = 63,
 
   // alternate frame return column
   dwarf_alt_fr_col = 64,
 
-  dwarf_v0 = 96,
-  dwarf_v1,
-  dwarf_v2,
-  dwarf_v3,
-  dwarf_v4,
-  dwarf_v5,
-  dwarf_v6,
-  dwarf_v7,
-  dwarf_v8,
-  dwarf_v9,
-  dwarf_v10,
-  dwarf_v11,
-  dwarf_v12,
-  dwarf_v13,
-  dwarf_v14,
-  dwarf_v15,
-  dwarf_v16,
-  dwarf_v17,
-  dwarf_v18,
-  dwarf_v19,
-  dwarf_v20,
-  dwarf_v21,
-  dwarf_v22,
-  dwarf_v23,
-  dwarf_v24,
-  dwarf_v25,
-  dwarf_v26,
-  dwarf_v27,
-  dwarf_v28,
-  dwarf_v29,
-  dwarf_v30,
-  dwarf_v31 = 127,
+  dwarf_vpr_v0 = 96,
+  dwarf_vpr_v1,
+  dwarf_vpr_v2,
+  dwarf_vpr_v3,
+  dwarf_vpr_v4,
+  dwarf_vpr_v5,
+  dwarf_vpr_v6,
+  dwarf_vpr_v7,
+  dwarf_vpr_v8,
+  dwarf_vpr_v9,
+  dwarf_vpr_v10,
+  dwarf_vpr_v11,
+  dwarf_vpr_v12,
+  dwarf_vpr_v13,
+  dwarf_vpr_v14,
+  dwarf_vpr_v15,
+  dwarf_vpr_v16,
+  dwarf_vpr_v17,
+  dwarf_vpr_v18,
+  dwarf_vpr_v19,
+  dwarf_vpr_v20,
+  dwarf_vpr_v21,
+  dwarf_vpr_v22,
+  dwarf_vpr_v23,
+  dwarf_vpr_v24,
+  dwarf_vpr_v25,
+  dwarf_vpr_v26,
+  dwarf_vpr_v27,
+  dwarf_vpr_v28,
+  dwarf_vpr_v29,
+  dwarf_vpr_v30,
+  dwarf_vpr_v31 = 127,
   dwarf_first_csr = 4096,
   dwarf_fpr_fcsr = dwarf_first_csr + 0x003,
+  // The vector extension adds seven unprivileged CSRs
+  // (vstart, vxsat, vxrm, vcsr, vtype, vl, vlenb)
+  // to a base scalar RISC-V ISA.
+  dwarf_vpr_vstart = dwarf_first_csr + 0x008,
+  dwarf_vpr_vxsat = dwarf_first_csr + 0x009,
+  dwarf_vpr_vxrm = dwarf_first_csr + 0x00A,
+  dwarf_vpr_vcsr = dwarf_first_csr + 0x00F,
+  dwarf_vpr_vl = dwarf_first_csr + 0xC20,
+  dwarf_vpr_vtype = dwarf_first_csr + 0xC21,
+  dwarf_vpr_vlenb = dwarf_first_csr + 0xC22,
   dwarf_last_csr = 8191,
 
   // register ABI name
   dwarf_gpr_zero = dwarf_gpr_x0,
   dwarf_gpr_ra = dwarf_gpr_x1,
   dwarf_gpr_sp = dwarf_gpr_x2,
   dwarf_gpr_gp = dwarf_gpr_x3,
   dwarf_gpr_tp = dwarf_gpr_x4,