[X86] Add register definitions for cfi directives

[abrachet]

Summary

Add {e,r}flags, {g,f}s.base registers so they can be referenced in cfi
directives,. They are not otherwise useable in any instructions,
but can be implicitly pushed to the stack like with pushf for
{e,r}flags.

[mcgrathr]

llvm/lib/Target/X86/X86RegisterInfo.td

315

Should this use DwarfRegAlias?

[abrachet]

llvm/lib/Target/X86/X86RegisterInfo.td

315

Sure should

[pengfei]

IIUC, they can be used only under privileged mode. Is there a real case that compiler will emit these directives?

[mcgrathr]

Assembler syntax exists for humans who write assembly, not just for compilers.
Compilers do not emit CFI that refers to these registers.

[mcgrathr]

The lack of these registers is a regression in LLVM's assembler compared to the GNU assembler.

[pengfei]

You are right. Clang can compile assembly file and should be able to parse these directives too. LGTM, thanks!

llvm/lib/Target/X86/X86RegisterInfo.td

 
 // Status flags register.
 //
 // Note that some flags that are commonly thought of as part of the status
 // flags register are modeled separately. Typically this is due to instructions
 // reading and updating those flags independently of all the others. We don't
 // want to create false dependencies between these instructions and so we use
 // a separate register to model them.
-def EFLAGS : X86Reg<"flags", 0>;
+def EFLAGS : X86Reg<"flags", 0>, DwarfRegNum<[49, 9, 9]>;
+def _EFLAGS : X86Reg<"eflags", 0>, DwarfRegAlias<EFLAGS>;
+def RFLAGS : X86Reg<"rflags", 0>, DwarfRegNum<[49, -2, -2]>;
 
 // The direction flag.
 def DF : X86Reg<"dirflag", 0>;
 
 
 // Segment registers
 def CS : X86Reg<"cs", 1>;
 def DS : X86Reg<"ds", 3>;
 def SS : X86Reg<"ss", 2>;
 def ES : X86Reg<"es", 0>;
 def FS : X86Reg<"fs", 4>;
 def GS : X86Reg<"gs", 5>;
 
+def FS_BASE : X86Reg<"fs.base", 0>, DwarfRegNum<[58, -2, -2]>;
+def GS_BASE : X86Reg<"gs.base", 0>, DwarfRegNum<[59, -2, -2]>;
+
 // Debug registers
 def DR0  : X86Reg<"dr0",   0>;
 def DR1  : X86Reg<"dr1",   1>;
 def DR2  : X86Reg<"dr2",   2>;
 def DR3  : X86Reg<"dr3",   3>;
 def DR4  : X86Reg<"dr4",   4>;
 def DR5  : X86Reg<"dr5",   5>;
 def DR6  : X86Reg<"dr6",   6>;

llvm/test/CodeGen/X86/ipra-reg-usage.ll

 ; RUN: llc -enable-ipra -print-regusage -o /dev/null 2>&1 < %s | FileCheck %s
 
 target triple = "x86_64-unknown-unknown"
 declare void @bar1()
 define preserve_allcc void @foo()#0 {
-; CHECK: foo Clobbered Registers: $cs $df $ds $eflags $eip $eiz $es $esp $fpcw $fpsw $fs $gs $hip $hsp $ip $mxcsr $rip $riz $rsp $sp $sph $spl $ss $ssp $tmmcfg $cr0 $cr1 $cr2 $cr3 $cr4 $cr5 $cr6 $cr7 $cr8 $cr9 $cr10 $cr11 $cr12 $cr13 $cr14 $cr15 $dr0 $dr1 $dr2 $dr3 $dr4 $dr5 $dr6 $dr7 $dr8 $dr9 $dr10 $dr11 $dr12 $dr13 $dr14 $dr15 $fp0 $fp1 $fp2 $fp3 $fp4 $fp5 $fp6 $fp7 $k0 $k1 $k2 $k3 $k4 $k5 $k6 $k7 $mm0 $mm1 $mm2 $mm3 $mm4 $mm5 $mm6 $mm7 $r11 $st0 $st1 $st2 $st3 $st4 $st5 $st6 $st7 $tmm0 $tmm1 $tmm2 $tmm3 $tmm4 $tmm5 $tmm6 $tmm7 $xmm16 $xmm17 $xmm18 $xmm19 $xmm20 $xmm21 $xmm22 $xmm23 $xmm24 $xmm25 $xmm26 $xmm27 $xmm28 $xmm29 $xmm30 $xmm31 $ymm0 $ymm1 $ymm2 $ymm3 $ymm4 $ymm5 $ymm6 $ymm7 $ymm8 $ymm9 $ymm10 $ymm11 $ymm12 $ymm13 $ymm14 $ymm15 $ymm16 $ymm17 $ymm18 $ymm19 $ymm20 $ymm21 $ymm22 $ymm23 $ymm24 $ymm25 $ymm26 $ymm27 $ymm28 $ymm29 $ymm30 $ymm31 $zmm0 $zmm1 $zmm2 $zmm3 $zmm4 $zmm5 $zmm6 $zmm7 $zmm8 $zmm9 $zmm10 $zmm11 $zmm12 $zmm13 $zmm14 $zmm15 $zmm16 $zmm17 $zmm18 $zmm19 $zmm20 $zmm21 $zmm22 $zmm23 $zmm24 $zmm25 $zmm26 $zmm27 $zmm28 $zmm29 $zmm30 $zmm31 $r11b $r11bh $r11d $r11w $r11wh $k0_k1 $k2_k3 $k4_k5 $k6_k7
+; CHECK: foo Clobbered Registers: $cs $df $ds $eflags $eip $eiz $es $esp $fpcw $fpsw $fs $fs_base $gs $gs_base $hip $hsp $ip $mxcsr $rflags $rip $riz $rsp $sp $sph $spl $ss $ssp $tmmcfg $_eflags $cr0 $cr1 $cr2 $cr3 $cr4 $cr5 $cr6 $cr7 $cr8 $cr9 $cr10 $cr11 $cr12 $cr13 $cr14 $cr15 $dr0 $dr1 $dr2 $dr3 $dr4 $dr5 $dr6 $dr7 $dr8 $dr9 $dr10 $dr11 $dr12 $dr13 $dr14 $dr15 $fp0 $fp1 $fp2 $fp3 $fp4 $fp5 $fp6 $fp7 $k0 $k1 $k2 $k3 $k4 $k5 $k6 $k7 $mm0 $mm1 $mm2 $mm3 $mm4 $mm5 $mm6 $mm7 $r11 $st0 $st1 $st2 $st3 $st4 $st5 $st6 $st7 $tmm0 $tmm1 $tmm2 $tmm3 $tmm4 $tmm5 $tmm6 $tmm7 $xmm16 $xmm17 $xmm18 $xmm19 $xmm20 $xmm21 $xmm22 $xmm23 $xmm24 $xmm25 $xmm26 $xmm27 $xmm28 $xmm29 $xmm30 $xmm31 $ymm0 $ymm1 $ymm2 $ymm3 $ymm4 $ymm5 $ymm6 $ymm7 $ymm8 $ymm9 $ymm10 $ymm11 $ymm12 $ymm13 $ymm14 $ymm15 $ymm16 $ymm17 $ymm18 $ymm19 $ymm20 $ymm21 $ymm22 $ymm23 $ymm24 $ymm25 $ymm26 $ymm27 $ymm28 $ymm29 $ymm30 $ymm31 $zmm0 $zmm1 $zmm2 $zmm3 $zmm4 $zmm5 $zmm6 $zmm7 $zmm8 $zmm9 $zmm10 $zmm11 $zmm12 $zmm13 $zmm14 $zmm15 $zmm16 $zmm17 $zmm18 $zmm19 $zmm20 $zmm21 $zmm22 $zmm23 $zmm24 $zmm25 $zmm26 $zmm27 $zmm28 $zmm29 $zmm30 $zmm31 $r11b $r11bh $r11d $r11w $r11wh $k0_k1 $k2_k3 $k4_k5 $k6_k7
   call void @bar1()
   call void @bar2()
   ret void
 }
 declare void @bar2()
 
 @llvm.used = appending global [1 x ptr] [ptr @foo]
 
 attributes #0 = {nounwind}

llvm/test/MC/ELF/cfi-offset.s

-// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -S --sr --sd - | FileCheck %s
+// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o %t
+// RUN: llvm-readobj -S --sr --sd %t | FileCheck %s
+// RUN: llvm-objdump --dwarf=frames %t | FileCheck %s --check-prefix=FRAMES
 
 f:
-  .cfi_startproc
+    .cfi_startproc
         nop
-  .cfi_offset %rbp, -16
+    .cfi_offset %rbp, -24
+    .cfi_offset %rflags, -16
+    .cfi_offset %gs.base, -8
+    .cfi_offset %fs.base, 0
         nop
-  .cfi_endproc
+    .cfi_endproc
 
 // CHECK:        Section {
 // CHECK:          Name: .eh_frame
 // CHECK-NEXT:     Type: SHT_X86_64_UNWIND
 // CHECK-NEXT:     Flags [
 // CHECK-NEXT:       SHF_ALLOC
 // CHECK-NEXT:     ]
 // CHECK-NEXT:     Address: 0x0
 // CHECK-NEXT:     Offset: 0x48
-// CHECK-NEXT:     Size: 48
+// CHECK-NEXT:     Size: 56
 // CHECK-NEXT:     Link: 0
 // CHECK-NEXT:     Info: 0
 // CHECK-NEXT:     AddressAlignment: 8
 // CHECK-NEXT:     EntrySize: 0
 // CHECK-NEXT:     Relocations [
 // CHECK-NEXT:     ]
 // CHECK-NEXT:     SectionData (
 // CHECK-NEXT:       0000: 14000000 00000000 017A5200 01781001
-// CHECK-NEXT:       0010: 1B0C0708 90010000 14000000 1C000000
-// CHECK-NEXT:       0020: 00000000 02000000 00418602 00000000
+// CHECK-NEXT:       0010: 1B0C0708 90010000 1C000000 1C000000
+// CHECK-NEXT:       0020: 00000000 02000000 00418603 B102BB01
+// CHECK-NEXT:       0030: BA000000 00000000
 // CHECK-NEXT:     )
 // CHECK-NEXT:   }
 
 // CHECK:        Section {
 // CHECK:          Name: .rela.eh_frame
 // CHECK-NEXT:     Type: SHT_RELA
 // CHECK-NEXT:     Flags [
 // CHECK-NEXT:       SHF_INFO_LINK
 // CHECK-NEXT:     ]
 // CHECK-NEXT:     Address: 0x0
 // CHECK-NEXT:     Offset:
 // CHECK-NEXT:     Size: 24
 // CHECK-NEXT:     Link:
 // CHECK-NEXT:     Info:
 // CHECK-NEXT:     AddressAlignment: 8
 // CHECK-NEXT:     EntrySize: 24
 // CHECK-NEXT:     Relocations [
 // CHECK-NEXT:       0x20 R_X86_64_PC32 .text 0x0
 // CHECK-NEXT:     ]
 // CHECK:        }
+
+// FRAMES:      DW_CFA_offset: reg6 -24
+// FRAMES-NEXT: DW_CFA_offset: reg49 -16
+// FRAMES-NEXT: DW_CFA_offset: reg59 -8
+// FRAMES-NEXT: DW_CFA_offset: reg58 0