[ARM] Use MCInstrInfo::get in ARMDisassembler instead of reinventing it

[foad]

llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp

133

This is the pattern used by AArch64 and other disassemblers I looked at.

1638

It is slightly ugly having to down-cast here but I assume it is safe.

[simon_tatham]

llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp

1638

It happens in several other places already in this file, and in similar situations in quite a few other backends, so I agree that looks safe.

llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp

 #include "MCTargetDesc/ARMMCTargetDesc.h"
 #include "TargetInfo/ARMTargetInfo.h"
 #include "Utils/ARMBaseInfo.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCDecoderOps.h"
 #include "llvm/MC/MCDisassembler/MCDisassembler.h"
 #include "llvm/MC/MCInst.h"
 #include "llvm/MC/MCInstrDesc.h"
+#include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/MC/SubtargetFeature.h"
 #include "llvm/MC/TargetRegistry.h"
 #include "llvm/Support/Compiler.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/MathExtras.h"
 #include "llvm/Support/raw_ostream.h"
 #include <algorithm>
class VPTStatus
 
     private:
       SmallVector<unsigned char, 4> VPTStates;
   };
 
 /// ARM disassembler for all ARM platforms.
 class ARMDisassembler : public MCDisassembler {
 public:
-  ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
-    MCDisassembler(STI, Ctx) {
+  std::unique_ptr<const MCInstrInfo> MCII;
+
+  ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
+                  const MCInstrInfo *MCII)
+      : MCDisassembler(STI, Ctx), MCII(MCII) {
     InstructionEndianness = STI.getFeatureBits()[ARM::ModeBigEndianInstructions]
                                 ? llvm::support::big
                                 : llvm::support::little;
   }
 
   ~ARMDisassembler() override = default;
 
   DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
private:
 
   DecodeStatus getThumbInstruction(MCInst &Instr, uint64_t &Size,
                                    ArrayRef<uint8_t> Bytes, uint64_t Address,
                                    raw_ostream &CStream) const;
 
   mutable ITStatus ITBlock;
   mutable VPTStatus VPTBlock;
 
+  void AddThumb1SBit(MCInst &MI, bool InITBlock) const;
+  bool isVectorPredicable(const MCInst &MI) const;
   DecodeStatus AddThumbPredicate(MCInst&) const;
   void UpdateThumbVFPPredicate(DecodeStatus &, MCInst&) const;
 
   llvm::support::endianness InstructionEndianness;
 };
 
 } // end anonymous namespace
 
static DecodeStatus DecodeT2AddSubSPImm(MCInst &Inst, unsigned Insn,
                                         uint64_t Address,
                                         const MCDisassembler *Decoder);
 
 #include "ARMGenDisassemblerTables.inc"
 
 static MCDisassembler *createARMDisassembler(const Target &T,
                                              const MCSubtargetInfo &STI,
                                              MCContext &Ctx) {
-  return new ARMDisassembler(STI, Ctx);
+  return new ARMDisassembler(STI, Ctx, T.createMCInstrInfo());
 }
 
 // Post-decoding checks
 static DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size,
                                             uint64_t Address, raw_ostream &CS,
                                             uint32_t Insn,
                                             DecodeStatus Result) {
   switch (MI.getOpcode()) {
if (Result != MCDisassembler::Fail) {
     Size = 4;
     return checkDecodedInstruction(MI, Size, Address, CS, Insn, Result);
   }
 
   Size = 4;
   return MCDisassembler::Fail;
 }
 
-namespace llvm {
-
-extern const MCInstrDesc ARMInsts[];
-
-} // end namespace llvm
-
 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
 /// immediate Value in the MCInst.  The immediate Value has had any PC
 /// adjustment made by the caller.  If the instruction is a branch instruction
 /// then isBranch is true, else false.  If the getOpInfo() function was set as
 /// part of the setupForSymbolicDisassembly() call then that function is called
 /// to get any symbolic information at the Address for this instruction.  If
 /// that returns non-zero then the symbolic information it returns is used to
 /// create an MCExpr and that is added as an operand to the MCInst.  If
static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value,
   const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
   Dis->tryAddingPcLoadReferenceComment(Value, Address);
 }
 
 // Thumb1 instructions don't have explicit S bits.  Rather, they
 // implicitly set CPSR.  Since it's not represented in the encoding, the
 // auto-generated decoder won't inject the CPSR operand.  We need to fix
 // that as a post-pass.
-static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
-  const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
-  unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
+void ARMDisassembler::AddThumb1SBit(MCInst &MI, bool InITBlock) const {
+  const MCInstrDesc &MCID = MCII->get(MI.getOpcode());
   MCInst::iterator I = MI.begin();
-  for (unsigned i = 0; i < NumOps; ++i, ++I) {
+  for (unsigned i = 0; i < MCID.NumOperands; ++i, ++I) {
     if (I == MI.end()) break;
-    if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
-      if (i > 0 && OpInfo[i-1].isPredicate()) continue;
+    if (MCID.OpInfo[i].isOptionalDef() &&
+        MCID.OpInfo[i].RegClass == ARM::CCRRegClassID) {
+      if (i > 0 && MCID.OpInfo[i - 1].isPredicate())
+        continue;
       MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
       return;
     }
   }
 
   MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
 }
 
-static bool isVectorPredicable(unsigned Opcode) {
-  const MCOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
-  unsigned short NumOps = ARMInsts[Opcode].NumOperands;
-  for (unsigned i = 0; i < NumOps; ++i) {
-    if (ARM::isVpred(OpInfo[i].OperandType))
+bool ARMDisassembler::isVectorPredicable(const MCInst &MI) const {
+  const MCInstrDesc &MCID = MCII->get(MI.getOpcode());
+  for (unsigned i = 0; i < MCID.NumOperands; ++i) {
+    if (ARM::isVpred(MCID.OpInfo[i].OperandType))
       return true;
   }
   return false;
 }
 
 // Most Thumb instructions don't have explicit predicates in the
 // encoding, but rather get their predicates from IT context.  We need
 // to fix up the predicate operands using this context information as a
case ARM::t2TBH:
         S = SoftFail;
       break;
     default:
       break;
   }
 
   // Warn on non-VPT predicable instruction in a VPT block and a VPT
   // predicable instruction in an IT block
-  if ((!isVectorPredicable(MI.getOpcode()) && VPTBlock.instrInVPTBlock()) ||
-       (isVectorPredicable(MI.getOpcode()) && ITBlock.instrInITBlock()))
+  if ((!isVectorPredicable(MI) && VPTBlock.instrInVPTBlock()) ||
+      (isVectorPredicable(MI) && ITBlock.instrInITBlock()))
     S = SoftFail;
 
   // If we're in an IT/VPT block, base the predicate on that.  Otherwise,
   // assume a predicate of AL.
   unsigned CC = ARMCC::AL;
   unsigned VCC = ARMVCC::None;
   if (ITBlock.instrInITBlock()) {
     CC = ITBlock.getITCC();
     ITBlock.advanceITState();
   } else if (VPTBlock.instrInVPTBlock()) {
     VCC = VPTBlock.getVPTPred();
     VPTBlock.advanceVPTState();
   }
 
-  const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
-  unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
+  const MCInstrDesc &MCID = MCII->get(MI.getOpcode());
 
   MCInst::iterator CCI = MI.begin();
-  for (unsigned i = 0; i < NumOps; ++i, ++CCI) {
-    if (OpInfo[i].isPredicate() || CCI == MI.end()) break;
+  for (unsigned i = 0; i < MCID.NumOperands; ++i, ++CCI) {
+    if (MCID.OpInfo[i].isPredicate() || CCI == MI.end())
+      break;
   }
 
-  if (ARMInsts[MI.getOpcode()].isPredicable()) {
+  if (MCID.isPredicable()) {
     CCI = MI.insert(CCI, MCOperand::createImm(CC));
     ++CCI;
     if (CC == ARMCC::AL)
       MI.insert(CCI, MCOperand::createReg(0));
     else
       MI.insert(CCI, MCOperand::createReg(ARM::CPSR));
   } else if (CC != ARMCC::AL) {
     Check(S, SoftFail);
   }
 
   MCInst::iterator VCCI = MI.begin();
   unsigned VCCPos;
-  for (VCCPos = 0; VCCPos < NumOps; ++VCCPos, ++VCCI) {
-    if (ARM::isVpred(OpInfo[VCCPos].OperandType) || VCCI == MI.end()) break;
+  for (VCCPos = 0; VCCPos < MCID.NumOperands; ++VCCPos, ++VCCI) {
+    if (ARM::isVpred(MCID.OpInfo[VCCPos].OperandType) || VCCI == MI.end())
+      break;
   }
 
-  if (isVectorPredicable(MI.getOpcode())) {
+  if (isVectorPredicable(MI)) {
     VCCI = MI.insert(VCCI, MCOperand::createImm(VCC));
     ++VCCI;
     if (VCC == ARMVCC::None)
       VCCI = MI.insert(VCCI, MCOperand::createReg(0));
     else
       VCCI = MI.insert(VCCI, MCOperand::createReg(ARM::P0));
     ++VCCI;
     VCCI = MI.insert(VCCI, MCOperand::createReg(0));
     ++VCCI;
-    if (OpInfo[VCCPos].OperandType == ARM::OPERAND_VPRED_R) {
-      int TiedOp = ARMInsts[MI.getOpcode()].getOperandConstraint(
-        VCCPos + 3, MCOI::TIED_TO);
+    if (MCID.OpInfo[VCCPos].OperandType == ARM::OPERAND_VPRED_R) {
+      int TiedOp = MCID.getOperandConstraint(VCCPos + 3, MCOI::TIED_TO);
       assert(TiedOp >= 0 &&
              "Inactive register in vpred_r is not tied to an output!");
       // Copy the operand to ensure it's not invalidated when MI grows.
       MI.insert(VCCI, MCOperand(MI.getOperand(TiedOp)));
     }
   } else if (VCC != ARMVCC::None) {
     Check(S, SoftFail);
   }
if (CC == 0xF)
     CC = ARMCC::AL;
   if (ITBlock.instrInITBlock())
     ITBlock.advanceITState();
   else if (VPTBlock.instrInVPTBlock()) {
     CC = VPTBlock.getVPTPred();
     VPTBlock.advanceVPTState();
   }
 
-  const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
+  const MCInstrDesc &MCID = MCII->get(MI.getOpcode());
+  const MCOperandInfo *OpInfo = MCID.OpInfo;
   MCInst::iterator I = MI.begin();
-  unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
+  unsigned short NumOps = MCID.NumOperands;
   for (unsigned i = 0; i < NumOps; ++i, ++I) {
     if (OpInfo[i].isPredicate() ) {
-      if (CC != ARMCC::AL && !ARMInsts[MI.getOpcode()].isPredicable())
+      if (CC != ARMCC::AL && !MCID.isPredicable())
         Check(S, SoftFail);
       I->setImm(CC);
       ++I;
       if (CC == ARMCC::AL)
         I->setReg(0);
       else
         I->setReg(ARM::CPSR);
       return;

 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
                                            uint64_t Address,
                                            const MCDisassembler *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
   if (Val == 0xF) return MCDisassembler::Fail;
   // AL predicate is not allowed on Thumb1 branches.
   if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
     return MCDisassembler::Fail;
-  if (Val != ARMCC::AL && !ARMInsts[Inst.getOpcode()].isPredicable())
+  const MCInstrInfo *MCII =
+      static_cast<const ARMDisassembler *>(Decoder)->MCII.get();
+  if (Val != ARMCC::AL && !MCII->get(Inst.getOpcode()).isPredicable())
     Check(S, MCDisassembler::SoftFail);
   Inst.addOperand(MCOperand::createImm(Val));
   if (Val == ARMCC::AL) {
     Inst.addOperand(MCOperand::createReg(0));
   } else
     Inst.addOperand(MCOperand::createReg(ARM::CPSR));
   return S;
 }