[AArch64] Only enable `foldCSELOfCSEl` DAG combine when x != y

[bcl5980]

Summary

https://alive2.llvm.org/ce/z/Uy_x_b

Fix: https://github.com/llvm/llvm-project/issues/59902

[dmgreen]

LGTM Thanks

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

20024

These could be combined into the "Where x and y are constants" line.

20055–20058

This comment could be formatted to flow better.

llvm/test/CodeGen/AArch64/pr59902.ll

5

this -> This

[bcl5980]

address comments.

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

unsigned BitWidth = CTTZ.getOpcode() == ISD::TRUNCATE
                           ? CTTZ.getOperand(0).getValueSizeInBits()
                           : CTTZ.getValueSizeInBits();
   SDValue BitWidthMinusOne =
       DAG.getConstant(BitWidth - 1, SDLoc(N), CTTZ.getValueType());
   return DAG.getNode(ISD::AND, SDLoc(N), CTTZ.getValueType(), CTTZ,
                      BitWidthMinusOne);
 }
 
 // (CSEL l r EQ (CMP (CSEL x y cc2 cond) x)) => (CSEL l r cc2 cond)
 // (CSEL l r EQ (CMP (CSEL x y cc2 cond) y)) => (CSEL l r !cc2 cond)
-// Where x and y are constants
+// Where x and y are constants and x != y
 
 // (CSEL l r NE (CMP (CSEL x y cc2 cond) x)) => (CSEL l r !cc2 cond)
 // (CSEL l r NE (CMP (CSEL x y cc2 cond) y)) => (CSEL l r cc2 cond)
-// Where x and y are constants
+// Where x and y are constants and x != y
 static SDValue foldCSELOfCSEL(SDNode *Op, SelectionDAG &DAG) {
   SDValue L = Op->getOperand(0);
   SDValue R = Op->getOperand(1);
   AArch64CC::CondCode OpCC =
       static_cast<AArch64CC::CondCode>(Op->getConstantOperandVal(2));
 
   SDValue OpCmp = Op->getOperand(3);
   if (!isCMP(OpCmp))
     return SDValue();
 
   SDValue CmpLHS = OpCmp.getOperand(0);
   SDValue CmpRHS = OpCmp.getOperand(1);
 
   if (CmpRHS.getOpcode() == AArch64ISD::CSEL)
     std::swap(CmpLHS, CmpRHS);
   else if (CmpLHS.getOpcode() != AArch64ISD::CSEL)
     return SDValue();
 
   SDValue X = CmpLHS->getOperand(0);
   SDValue Y = CmpLHS->getOperand(1);
-  if (!isa<ConstantSDNode>(X) || !isa<ConstantSDNode>(Y)) {
+  if (!isa<ConstantSDNode>(X) || !isa<ConstantSDNode>(Y) || X == Y) {
     return SDValue();
   }
 
+  // If one of the constant is opaque constant, x,y sdnode is still different
+  // but the real value maybe the same. So check APInt here to make sure the
+  // code is correct.
+  ConstantSDNode *CX = cast<ConstantSDNode>(X);
+  ConstantSDNode *CY = cast<ConstantSDNode>(Y);
+  if (CX->getAPIntValue() == CY->getAPIntValue())
+    return SDValue();
+
   AArch64CC::CondCode CC =
       static_cast<AArch64CC::CondCode>(CmpLHS->getConstantOperandVal(2));
   SDValue Cond = CmpLHS->getOperand(3);
 
   if (CmpRHS == Y)
     CC = AArch64CC::getInvertedCondCode(CC);
   else if (CmpRHS != X)
     return SDValue();

llvm/test/CodeGen/AArch64/pr59902.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
+
+; This used to miscompile because foldCSELOfCSEL function
+; doesn't check const x != y
+define i1 @test() {
+; CHECK-LABEL: test:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov x8, #9007199254740990
+; CHECK-NEXT:    movk x8, #65503, lsl #16
+; CHECK-NEXT:    movk x8, #65407, lsl #32
+; CHECK-NEXT:    cmp x8, x8
+; CHECK-NEXT:    csel x9, x8, x8, gt
+; CHECK-NEXT:    cmp x9, x8
+; CHECK-NEXT:    cset w0, eq
+; CHECK-NEXT:    ret
+  %1 = select i1 false, i64 0, i64 9006649496829950
+  %2 = call i64 @llvm.smax.i64(i64 %1, i64 9006649496829950)
+  %3 = icmp eq i64 %2, 9006649496829950
+  ret i1 %3
+}
+
+declare i64 @llvm.smax.i64(i64, i64)