AMDGPU/GlobalISel: Make regbankselect of implicit_def consistent with constants

[foad]

llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-implicit-def.mir

135–137

Patch looks reasonable but I don't understand why it has this effect.

[arsenm]

llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-implicit-def.mir

135–137

Previously the widen to s32 was applied to the select input, now it's being applied to the implicit_def's output too, so you get both. We currently don't try to fold out intermediate states

[Pierre-vh]

LGTM (not sure if @foad has any concerns)?

llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-implicit-def.mir

135–137

This will be folded by the next combine run before instruction select right?

[foad]

In D141128#4047083, @Pierre-vh wrote:

LGTM (not sure if @foad has any concerns)?

No objection from me!

[arsenm]

371884865393141b0216b6479260b6feef5915ee

llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-implicit-def.mir

135–137

Hopefully, but regbank combine hasn't seen much work

llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

AMDGPURegisterBankInfo::getInstrAlternativeMappings(
     const MachineInstr &MI) const {
 
   const MachineFunction &MF = *MI.getParent()->getParent();
   const MachineRegisterInfo &MRI = MF.getRegInfo();
 
 
   InstructionMappings AltMappings;
   switch (MI.getOpcode()) {
-  case TargetOpcode::G_CONSTANT: {
+  case TargetOpcode::G_CONSTANT:
+  case TargetOpcode::G_IMPLICIT_DEF: {
     unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);
     if (Size == 1) {
       static const OpRegBankEntry<1> Table[3] = {
         { { AMDGPU::VGPRRegBankID }, 1 },
         { { AMDGPU::SGPRRegBankID }, 1 },
         { { AMDGPU::VCCRegBankID }, 1 }
       };
 

 }
 
 void AMDGPURegisterBankInfo::applyMappingImpl(
     const OperandsMapper &OpdMapper) const {
   MachineInstr &MI = OpdMapper.getMI();
   unsigned Opc = MI.getOpcode();
   MachineRegisterInfo &MRI = OpdMapper.getMRI();
   switch (Opc) {
-  case AMDGPU::G_CONSTANT: {
+  case AMDGPU::G_CONSTANT:
+  case AMDGPU::G_IMPLICIT_DEF: {
     Register DstReg = MI.getOperand(0).getReg();
     LLT DstTy = MRI.getType(DstReg);
     if (DstTy != LLT::scalar(1))
       break;
 
     const RegisterBank *DstBank =
         OpdMapper.getInstrMapping().getOperandMapping(0).BreakDown[0].RegBank;
     if (DstBank == &AMDGPU::VCCRegBank)
       break;
     SmallVector<Register, 1> DefRegs(OpdMapper.getVRegs(0));
     if (DefRegs.empty())
       DefRegs.push_back(DstReg);
 
     MachineIRBuilder B(MI);
     B.setInsertPt(*MI.getParent(), ++MI.getIterator());
 
     Register NewDstReg = MRI.createGenericVirtualRegister(LLT::scalar(32));
     LLVMContext &Ctx = B.getMF().getFunction().getContext();
 
     MI.getOperand(0).setReg(NewDstReg);
+
+    if (Opc != AMDGPU::G_IMPLICIT_DEF) {
       MI.getOperand(1).setCImm(
           ConstantInt::get(IntegerType::getInt32Ty(Ctx),
                            MI.getOperand(1).getCImm()->getZExtValue()));
+    }
+
     MRI.setRegBank(NewDstReg, *DstBank);
     B.buildTrunc(DefRegs[0], NewDstReg);
     return;
   }
   case AMDGPU::G_PHI: {
     Register DstReg = MI.getOperand(0).getReg();
     LLT DstTy = MRI.getType(DstReg);
     if (DstTy != LLT::scalar(1))

llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-implicit-def.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s
-# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck -check-prefixes=CHECK,FAST %s
+# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck -check-prefixes=CHECK,GREEDY %s
 
 ---
 name: test_implicit_def_s32_vgpr_use
 legalized:       true
 body: |
   bb.0:
     liveins: $vgpr0_vgpr1
 

 body: |
   bb.0:
     liveins: $sgpr8, $sgpr9
     ; CHECK-LABEL: name: test_implicit_def_s1_sgpr_use
     ; CHECK: liveins: $sgpr8, $sgpr9
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr8
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr9
-    ; CHECK-NEXT: [[DEF:%[0-9]+]]:sgpr(s1) = G_IMPLICIT_DEF
-    ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[DEF]](s1)
+    ; CHECK-NEXT: [[DEF:%[0-9]+]]:sgpr(s32) = G_IMPLICIT_DEF
+    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[DEF]](s32)
+    ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)
     ; CHECK-NEXT: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ZEXT]](s32), [[COPY]], [[COPY1]]
     ; CHECK-NEXT: S_ENDPGM 0, implicit [[SELECT]](s32)
     %0:_(s32) = COPY $sgpr8
     %1:_(s32) = COPY $sgpr9
     %2:_(s1) = G_IMPLICIT_DEF
     %3:_(s32) = G_SELECT %2, %0, %1
     S_ENDPGM 0, implicit %3
 
 ...
 
 ---
 name: test_implicit_def_s1_vcc_use
 legalized:       true
 body: |
   bb.0:
     liveins: $vgpr0, $vgpr1
     ; CHECK-LABEL: name: test_implicit_def_s1_vcc_use
     ; CHECK: liveins: $vgpr0, $vgpr1
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
-    ; CHECK-NEXT: [[DEF:%[0-9]+]]:sgpr(s1) = G_IMPLICIT_DEF
-    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[DEF]](s1)
+    ; CHECK-NEXT: [[DEF:%[0-9]+]]:sgpr(s32) = G_IMPLICIT_DEF
+    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[DEF]](s32)
+    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
     ; CHECK-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY2]](s1), [[COPY]], [[COPY1]]
     ; CHECK-NEXT: S_ENDPGM 0, implicit [[SELECT]](s32)
     %0:_(s32) = COPY $vgpr0
     %1:_(s32) = COPY $vgpr1
     %2:_(s1) = G_IMPLICIT_DEF
     %3:_(s32) = G_SELECT %2, %0, %1
     S_ENDPGM 0, implicit %3
 
 ...
 
 ---
 name: test_implicit_def_s1_explicit_vcc_use_0
 legalized:       true
 body: |
   bb.0:
     liveins: $vgpr0, $vgpr1
-    ; CHECK-LABEL: name: test_implicit_def_s1_explicit_vcc_use_0
-    ; CHECK: liveins: $vgpr0, $vgpr1
-    ; CHECK-NEXT: {{  $}}
-    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
-    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
-    ; CHECK-NEXT: [[DEF:%[0-9]+]]:sgpr(s1) = G_IMPLICIT_DEF
-    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[DEF]](s1)
-    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY2]](s1), [[COPY]], [[COPY1]]
-    ; CHECK-NEXT: S_ENDPGM 0, implicit [[SELECT]](s32)
+    ; FAST-LABEL: name: test_implicit_def_s1_explicit_vcc_use_0
+    ; FAST: liveins: $vgpr0, $vgpr1
+    ; FAST-NEXT: {{  $}}
+    ; FAST-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+    ; FAST-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
+    ; FAST-NEXT: [[DEF:%[0-9]+]]:sgpr(s32) = G_IMPLICIT_DEF
+    ; FAST-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[DEF]](s32)
+    ; FAST-NEXT: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
+    ; FAST-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY2]](s1), [[COPY]], [[COPY1]]
+    ; FAST-NEXT: S_ENDPGM 0, implicit [[SELECT]](s32)
+    ; GREEDY-LABEL: name: test_implicit_def_s1_explicit_vcc_use_0
+    ; GREEDY: liveins: $vgpr0, $vgpr1
+    ; GREEDY-NEXT: {{  $}}
+    ; GREEDY-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+    ; GREEDY-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
+    ; GREEDY-NEXT: [[DEF:%[0-9]+]]:vcc(s1) = G_IMPLICIT_DEF
+    ; GREEDY-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[DEF]](s1), [[COPY]], [[COPY1]]
+    ; GREEDY-NEXT: S_ENDPGM 0, implicit [[SELECT]](s32)
     %0:_(s32) = COPY $vgpr0
     %1:_(s32) = COPY $vgpr1
     %2:vcc(s1) = G_IMPLICIT_DEF
     %3:_(s32) = G_SELECT %2, %0, %1
     S_ENDPGM 0, implicit %3
 
 ...
 
 ---
 name: test_implicit_def_s1_explicit_vcc_use_1
 legalized:       true
 body: |
   bb.0:
-    ; CHECK-LABEL: name: test_implicit_def_s1_explicit_vcc_use_1
-    ; CHECK: [[DEF:%[0-9]+]]:sgpr(s1) = G_IMPLICIT_DEF
-    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vcc(s1) = COPY [[DEF]](s1)
-    ; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY]](s1)
+    ; FAST-LABEL: name: test_implicit_def_s1_explicit_vcc_use_1
+    ; FAST: [[DEF:%[0-9]+]]:sgpr(s32) = G_IMPLICIT_DEF
+    ; FAST-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[DEF]](s32)
+    ; FAST-NEXT: [[COPY:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
+    ; FAST-NEXT: S_ENDPGM 0, implicit [[COPY]](s1)
+    ; GREEDY-LABEL: name: test_implicit_def_s1_explicit_vcc_use_1
+    ; GREEDY: [[DEF:%[0-9]+]]:vcc(s1) = G_IMPLICIT_DEF
+    ; GREEDY-NEXT: S_ENDPGM 0, implicit [[DEF]](s1)
     %2:vcc(s1) = G_IMPLICIT_DEF
     S_ENDPGM 0, implicit %2
 
 ...