[RISCV] Add more XVentanaCondOps patterns.

[craig.topper]

Summary

Add patterns with seteq/setne conditions.

We don't have instructions for seteq/setne except for comparing
with zero and need to emit an ADDI or XOR before a seqz/snez to
compare other values.

The select ISD node takes a 0/1 value for the condition, but the
VT_MASKC(N) instructions check all XLen bits for zero or non-zero.
We can use this to avoid the seqz/snez in many cases.

This is pretty ridiculous number of patterns. I wonder if we could
use some ComplexPatterns to merge them, but I'd like to do that as
a follow up and focus on correctness of the result in this patch.

[craig.topper]

Rebase

[craig.topper]

Ping

[reames]

LGTM

llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td

 
 let Predicates = [IsRV64, HasVendorXVentanaCondOps] in {
 // Directly use MASKC/MASKCN in case of any of the operands being 0.
 def : Pat<(select GPR:$rc, GPR:$rs1, (i64 0)),
           (VT_MASKC $rs1, $rc)>;
 def : Pat<(select GPR:$rc, (i64 0), GPR:$rs1),
           (VT_MASKCN $rs1, $rc)>;
 
+def : Pat<(select (i64 (setne GPR:$rc, (i64 0))), GPR:$rs1, (i64 0)),
+          (VT_MASKC GPR:$rs1, GPR:$rc)>;
+def : Pat<(select (i64 (seteq GPR:$rc, (i64 0))), GPR:$rs1, (i64 0)),
+          (VT_MASKCN GPR:$rs1, GPR:$rc)>;
+def : Pat<(select (i64 (setne GPR:$rc, (i64 0))), (i64 0), GPR:$rs1),
+          (VT_MASKCN GPR:$rs1, GPR:$rc)>;
+def : Pat<(select (i64 (seteq GPR:$rc, (i64 0))), (i64 0), GPR:$rs1),
+          (VT_MASKC GPR:$rs1, GPR:$rc)>;
+
+def : Pat<(select (i64 (setne GPR:$x, simm12_plus1:$y)), GPR:$rs1, (i64 0)),
+          (VT_MASKC GPR:$rs1, (ADDI GPR:$x, (NegImm simm12_plus1:$y)))>;
+def : Pat<(select (i64 (seteq GPR:$x, simm12_plus1:$y)), GPR:$rs1, (i64 0)),
+          (VT_MASKCN GPR:$rs1, (ADDI GPR:$x, (NegImm simm12_plus1:$y)))>;
+def : Pat<(select (i64 (setne GPR:$x, simm12_plus1:$y)), (i64 0), GPR:$rs1),
+          (VT_MASKCN GPR:$rs1, (ADDI GPR:$x, (NegImm simm12_plus1:$y)))>;
+def : Pat<(select (i64 (seteq GPR:$x, simm12_plus1:$y)), (i64 0), GPR:$rs1),
+          (VT_MASKC GPR:$rs1, (ADDI GPR:$x, (NegImm simm12_plus1:$y)))>;
+
+def : Pat<(select (i64 (setne GPR:$x, (i64 -2048))), GPR:$rs1, (i64 0)),
+          (VT_MASKC GPR:$rs1, (XORI GPR:$x, -2048))>;
+def : Pat<(select (i64 (seteq GPR:$x, (i64 -2048))), GPR:$rs1, (i64 0)),
+          (VT_MASKCN GPR:$rs1, (XORI GPR:$x, -2048))>;
+def : Pat<(select (i64 (setne GPR:$x, (i64 -2048))), (i64 0), GPR:$rs1),
+          (VT_MASKCN GPR:$rs1, (XORI GPR:$x, -2048))>;
+def : Pat<(select (i64 (seteq GPR:$x, (i64 -2048))), (i64 0), GPR:$rs1),
+          (VT_MASKC GPR:$rs1, (XORI GPR:$x, -2048))>;
+
+def : Pat<(select (i64 (setne GPR:$x, GPR:$y)), GPR:$rs1, (i64 0)),
+          (VT_MASKC GPR:$rs1, (XOR GPR:$x, GPR:$y))>;
+def : Pat<(select (i64 (seteq GPR:$x, GPR:$y)), GPR:$rs1, (i64 0)),
+          (VT_MASKCN GPR:$rs1, (XOR GPR:$x, GPR:$y))>;
+def : Pat<(select (i64 (setne GPR:$x, GPR:$y)), (i64 0), GPR:$rs1),
+          (VT_MASKCN GPR:$rs1, (XOR GPR:$x, GPR:$y))>;
+def : Pat<(select (i64 (seteq GPR:$x, GPR:$y)), (i64 0), GPR:$rs1),
+          (VT_MASKC GPR:$rs1, (XOR GPR:$x, GPR:$y))>;
+
 // Conditional AND operation patterns.
 def : Pat<(i64 (select GPR:$rc, (and GPR:$rs1, GPR:$rs2), GPR:$rs1)),
           (OR (AND $rs1, $rs2), (VT_MASKCN $rs1, $rc))>;
 def : Pat<(i64 (select GPR:$rc, GPR:$rs1, (and GPR:$rs1, GPR:$rs2))),
           (OR (AND $rs1, $rs2), (VT_MASKC $rs1, $rc))>;
 
 // Basic select pattern that selects between 2 registers.
 def : Pat<(i64 (select GPR:$rc, GPR:$rs1, GPR:$rs2)),
           (OR (VT_MASKC $rs1, $rc), (VT_MASKCN $rs2, $rc))>;
+
+def : Pat<(i64 (select (i64 (setne GPR:$rc, (i64 0))), GPR:$rs1, GPR:$rs2)),
+          (OR (VT_MASKC GPR:$rs1, GPR:$rc), (VT_MASKCN GPR:$rs2, GPR:$rc))>;
+def : Pat<(i64 (select (i64 (seteq GPR:$rc, (i64 0))), GPR:$rs2, GPR:$rs1)),
+          (OR (VT_MASKC GPR:$rs1, GPR:$rc), (VT_MASKCN GPR:$rs2, GPR:$rc))>;
+
+def : Pat<(i64 (select (i64 (setne GPR:$x, simm12_plus1:$y)), GPR:$rs1, GPR:$rs2)),
+          (OR (VT_MASKC GPR:$rs1, (ADDI GPR:$x, (NegImm simm12_plus1:$y))),
+              (VT_MASKCN GPR:$rs2, (ADDI GPR:$x, (NegImm simm12_plus1:$y))))>;
+def : Pat<(i64 (select (i64 (seteq GPR:$x, simm12_plus1:$y)), GPR:$rs2, GPR:$rs1)),
+          (OR (VT_MASKC GPR:$rs1, (ADDI GPR:$x, (NegImm simm12_plus1:$y))),
+              (VT_MASKCN GPR:$rs2, (ADDI GPR:$x, (NegImm simm12_plus1:$y))))>;
+
+def : Pat<(i64 (select (i64 (setne GPR:$x, (i64 -2048))), GPR:$rs1, GPR:$rs2)),
+          (OR (VT_MASKC GPR:$rs1, (XORI GPR:$x, -2048)),
+              (VT_MASKCN GPR:$rs2, (XORI GPR:$x, -2048)))>;
+def : Pat<(i64 (select (i64 (seteq GPR:$x, (i64 -2048))), GPR:$rs2, GPR:$rs1)),
+          (OR (VT_MASKC GPR:$rs1, (XORI GPR:$x, -2048)),
+              (VT_MASKCN GPR:$rs2, (XORI GPR:$x, -2048)))>;
+
+def : Pat<(i64 (select (i64 (setne GPR:$x, GPR:$y)), GPR:$rs1, GPR:$rs2)),
+          (OR (VT_MASKC GPR:$rs1, (XOR GPR:$x, GPR:$y)),
+              (VT_MASKCN GPR:$rs2, (XOR GPR:$x, GPR:$y)))>;
+def : Pat<(i64 (select (i64 (seteq GPR:$x, GPR:$y)), GPR:$rs2, GPR:$rs1)),
+          (OR (VT_MASKC GPR:$rs1, (XOR GPR:$x, GPR:$y)),
+              (VT_MASKCN GPR:$rs2, (XOR GPR:$x, GPR:$y)))>;
+
 } // Predicates = [IsRV64, HasVendorXVentanaCondOps]

llvm/test/CodeGen/RISCV/select.ll

 ; NOCONDOPS-NEXT:    addiw a1, a1, -1
 ; NOCONDOPS-NEXT:    andi a1, a1, 43
 ; NOCONDOPS-NEXT:    xor a0, a0, a1
 ; NOCONDOPS-NEXT:    ret
 ;
 ; CONDOPS-LABEL: select_xor_3:
 ; CONDOPS:       # %bb.0: # %entry
 ; CONDOPS-NEXT:    andi a1, a1, 1
-; CONDOPS-NEXT:    seqz a1, a1
 ; CONDOPS-NEXT:    li a2, 43
-; CONDOPS-NEXT:    vt.maskc a1, a2, a1
+; CONDOPS-NEXT:    vt.maskcn a1, a2, a1
 ; CONDOPS-NEXT:    xor a0, a0, a1
 ; CONDOPS-NEXT:    ret
 entry:
  %and = and i8 %cond, 1
  %cmp10 = icmp eq i8 %and, 0
  %0 = xor i16 %A, 43
  %1 = select i1 %cmp10, i16 %0, i16 %A
  ret i16 %1

 ; NOCONDOPS-NEXT:    addi a2, a2, -1
 ; NOCONDOPS-NEXT:    and a1, a2, a1
 ; NOCONDOPS-NEXT:    xor a0, a0, a1
 ; NOCONDOPS-NEXT:    ret
 ;
 ; CONDOPS-LABEL: select_xor_4:
 ; CONDOPS:       # %bb.0: # %entry
 ; CONDOPS-NEXT:    andi a2, a2, 1
-; CONDOPS-NEXT:    seqz a2, a2
-; CONDOPS-NEXT:    vt.maskc a1, a1, a2
+; CONDOPS-NEXT:    vt.maskcn a1, a1, a2
 ; CONDOPS-NEXT:    xor a0, a0, a1
 ; CONDOPS-NEXT:    ret
 entry:
  %and = and i8 %cond, 1
  %cmp10 = icmp eq i8 %and, 0
  %0 = xor i32 %B, %A
  %1 = select i1 %cmp10, i32 %0, i32 %A
  ret i32 %1

 ; NOCONDOPS-NEXT:    addi a2, a2, -1
 ; NOCONDOPS-NEXT:    and a1, a2, a1
 ; NOCONDOPS-NEXT:    or a0, a0, a1
 ; NOCONDOPS-NEXT:    ret
 ;
 ; CONDOPS-LABEL: select_or_2:
 ; CONDOPS:       # %bb.0: # %entry
 ; CONDOPS-NEXT:    andi a2, a2, 1
-; CONDOPS-NEXT:    seqz a2, a2
-; CONDOPS-NEXT:    vt.maskc a1, a1, a2
+; CONDOPS-NEXT:    vt.maskcn a1, a1, a2
 ; CONDOPS-NEXT:    or a0, a0, a1
 ; CONDOPS-NEXT:    ret
 entry:
  %and = and i8 %cond, 1
  %cmp10 = icmp eq i8 %and, 0
  %0 = or i32 %B, %A
  %1 = select i1 %cmp10, i32 %0, i32 %A
  ret i32 %1

 ; NOCONDOPS-NEXT:    addi a2, a2, -1
 ; NOCONDOPS-NEXT:    and a1, a2, a1
 ; NOCONDOPS-NEXT:    or a0, a0, a1
 ; NOCONDOPS-NEXT:    ret
 ;
 ; CONDOPS-LABEL: select_or_3:
 ; CONDOPS:       # %bb.0: # %entry
 ; CONDOPS-NEXT:    andi a2, a2, 1
-; CONDOPS-NEXT:    seqz a2, a2
-; CONDOPS-NEXT:    vt.maskc a1, a1, a2
+; CONDOPS-NEXT:    vt.maskcn a1, a1, a2
 ; CONDOPS-NEXT:    or a0, a0, a1
 ; CONDOPS-NEXT:    ret
 entry:
  %and = and i32 %cond, 1
  %cmp10 = icmp eq i32 %and, 0
  %0 = or i32 %B, %A
  %1 = select i1 %cmp10, i32 %0, i32 %A
  ret i32 %1

llvm/test/CodeGen/RISCV/xventanacondops.ll

; CHECK-NEXT:    ret
   %sel = select i1 %rc, i64 %rs1, i64 %rs2
   ret i64 %sel
 }
 
 define i64 @seteq(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
 ; CHECK-LABEL: seteq:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xor a0, a0, a1
-; CHECK-NEXT:    seqz a0, a0
-; CHECK-NEXT:    vt.maskcn a1, a3, a0
-; CHECK-NEXT:    vt.maskc a0, a2, a0
+; CHECK-NEXT:    vt.maskcn a1, a2, a0
+; CHECK-NEXT:    vt.maskc a0, a3, a0
 ; CHECK-NEXT:    or a0, a0, a1
 ; CHECK-NEXT:    ret
   %rc = icmp eq i64 %a, %b
   %sel = select i1 %rc, i64 %rs1, i64 %rs2
   ret i64 %sel
 }
 
 define i64 @setne(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
 ; CHECK-LABEL: setne:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xor a0, a0, a1
-; CHECK-NEXT:    snez a0, a0
 ; CHECK-NEXT:    vt.maskcn a1, a3, a0
 ; CHECK-NEXT:    vt.maskc a0, a2, a0
 ; CHECK-NEXT:    or a0, a0, a1
 ; CHECK-NEXT:    ret
   %rc = icmp ne i64 %a, %b
   %sel = select i1 %rc, i64 %rs1, i64 %rs2
   ret i64 %sel
 }
; CHECK-NEXT:    ret
   %rc = icmp ule i64 %a, %b
   %sel = select i1 %rc, i64 %rs1, i64 %rs2
   ret i64 %sel
 }
 
 define i64 @seteq_zero(i64 %a, i64 %rs1, i64 %rs2) {
 ; CHECK-LABEL: seteq_zero:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    seqz a0, a0
-; CHECK-NEXT:    vt.maskcn a2, a2, a0
-; CHECK-NEXT:    vt.maskc a0, a1, a0
-; CHECK-NEXT:    or a0, a0, a2
+; CHECK-NEXT:    vt.maskcn a1, a1, a0
+; CHECK-NEXT:    vt.maskc a0, a2, a0
+; CHECK-NEXT:    or a0, a0, a1
 ; CHECK-NEXT:    ret
   %rc = icmp eq i64 %a, 0
   %sel = select i1 %rc, i64 %rs1, i64 %rs2
   ret i64 %sel
 }
 
 define i64 @setne_zero(i64 %a, i64 %rs1, i64 %rs2) {
 ; CHECK-LABEL: setne_zero:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    snez a0, a0
 ; CHECK-NEXT:    vt.maskcn a2, a2, a0
 ; CHECK-NEXT:    vt.maskc a0, a1, a0
 ; CHECK-NEXT:    or a0, a0, a2
 ; CHECK-NEXT:    ret
   %rc = icmp ne i64 %a, 0
   %sel = select i1 %rc, i64 %rs1, i64 %rs2
   ret i64 %sel
 }
 
 define i64 @seteq_constant(i64 %a, i64 %rs1, i64 %rs2) {
 ; CHECK-LABEL: seteq_constant:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, a0, -123
-; CHECK-NEXT:    seqz a0, a0
-; CHECK-NEXT:    vt.maskcn a2, a2, a0
-; CHECK-NEXT:    vt.maskc a0, a1, a0
-; CHECK-NEXT:    or a0, a0, a2
+; CHECK-NEXT:    vt.maskcn a1, a1, a0
+; CHECK-NEXT:    vt.maskc a0, a2, a0
+; CHECK-NEXT:    or a0, a0, a1
 ; CHECK-NEXT:    ret
   %rc = icmp eq i64 %a, 123
   %sel = select i1 %rc, i64 %rs1, i64 %rs2
   ret i64 %sel
 }
 
 define i64 @setne_constant(i64 %a, i64 %rs1, i64 %rs2) {
 ; CHECK-LABEL: setne_constant:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, a0, -456
-; CHECK-NEXT:    snez a0, a0
 ; CHECK-NEXT:    vt.maskcn a2, a2, a0
 ; CHECK-NEXT:    vt.maskc a0, a1, a0
 ; CHECK-NEXT:    or a0, a0, a2
 ; CHECK-NEXT:    ret
   %rc = icmp ne i64 %a, 456
   %sel = select i1 %rc, i64 %rs1, i64 %rs2
   ret i64 %sel
 }
 
 define i64 @seteq_neg2048(i64 %a, i64 %rs1, i64 %rs2) {
 ; CHECK-LABEL: seteq_neg2048:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xori a0, a0, -2048
-; CHECK-NEXT:    seqz a0, a0
-; CHECK-NEXT:    vt.maskcn a2, a2, a0
-; CHECK-NEXT:    vt.maskc a0, a1, a0
-; CHECK-NEXT:    or a0, a0, a2
+; CHECK-NEXT:    vt.maskcn a1, a1, a0
+; CHECK-NEXT:    vt.maskc a0, a2, a0
+; CHECK-NEXT:    or a0, a0, a1
 ; CHECK-NEXT:    ret
   %rc = icmp eq i64 %a, -2048
   %sel = select i1 %rc, i64 %rs1, i64 %rs2
   ret i64 %sel
 }
 
 define i64 @setne_neg2048(i64 %a, i64 %rs1, i64 %rs2) {
 ; CHECK-LABEL: setne_neg2048:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xori a0, a0, -2048
-; CHECK-NEXT:    snez a0, a0
 ; CHECK-NEXT:    vt.maskcn a2, a2, a0
 ; CHECK-NEXT:    vt.maskc a0, a1, a0
 ; CHECK-NEXT:    or a0, a0, a2
 ; CHECK-NEXT:    ret
   %rc = icmp ne i64 %a, -2048
   %sel = select i1 %rc, i64 %rs1, i64 %rs2
   ret i64 %sel
 }
 
 define i64 @zero1_seteq(i64 %a, i64 %b, i64 %rs1) {
 ; CHECK-LABEL: zero1_seteq:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xor a0, a0, a1
-; CHECK-NEXT:    seqz a0, a0
-; CHECK-NEXT:    vt.maskc a0, a2, a0
+; CHECK-NEXT:    vt.maskcn a0, a2, a0
 ; CHECK-NEXT:    ret
   %rc = icmp eq i64 %a, %b
   %sel = select i1 %rc, i64 %rs1, i64 0
   ret i64 %sel
 }
 
 define i64 @zero2_seteq(i64 %a, i64 %b, i64 %rs1) {
 ; CHECK-LABEL: zero2_seteq:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xor a0, a0, a1
-; CHECK-NEXT:    seqz a0, a0
-; CHECK-NEXT:    vt.maskcn a0, a2, a0
+; CHECK-NEXT:    vt.maskc a0, a2, a0
 ; CHECK-NEXT:    ret
   %rc = icmp eq i64 %a, %b
   %sel = select i1 %rc, i64 0, i64 %rs1
   ret i64 %sel
 }
 
 define i64 @zero1_setne(i64 %a, i64 %b, i64 %rs1) {
 ; CHECK-LABEL: zero1_setne:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xor a0, a0, a1
-; CHECK-NEXT:    snez a0, a0
 ; CHECK-NEXT:    vt.maskc a0, a2, a0
 ; CHECK-NEXT:    ret
   %rc = icmp ne i64 %a, %b
   %sel = select i1 %rc, i64 %rs1, i64 0
   ret i64 %sel
 }
 
 define i64 @zero2_setne(i64 %a, i64 %b, i64 %rs1) {
 ; CHECK-LABEL: zero2_setne:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xor a0, a0, a1
-; CHECK-NEXT:    snez a0, a0
 ; CHECK-NEXT:    vt.maskcn a0, a2, a0
 ; CHECK-NEXT:    ret
   %rc = icmp ne i64 %a, %b
   %sel = select i1 %rc, i64 0, i64 %rs1
   ret i64 %sel
 }
 
 define i64 @zero1_seteq_zero(i64 %a, i64 %rs1) {
 ; CHECK-LABEL: zero1_seteq_zero:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    seqz a0, a0
-; CHECK-NEXT:    vt.maskc a0, a1, a0
+; CHECK-NEXT:    vt.maskcn a0, a1, a0
 ; CHECK-NEXT:    ret
   %rc = icmp eq i64 %a, 0
   %sel = select i1 %rc, i64 %rs1, i64 0
   ret i64 %sel
 }
 
 define i64 @zero2_seteq_zero(i64 %a, i64 %rs1) {
 ; CHECK-LABEL: zero2_seteq_zero:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    seqz a0, a0
-; CHECK-NEXT:    vt.maskcn a0, a1, a0
+; CHECK-NEXT:    vt.maskc a0, a1, a0
 ; CHECK-NEXT:    ret
   %rc = icmp eq i64 %a, 0
   %sel = select i1 %rc, i64 0, i64 %rs1
   ret i64 %sel
 }
 
 define i64 @zero1_setne_zero(i64 %a, i64 %rs1) {
 ; CHECK-LABEL: zero1_setne_zero:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    snez a0, a0
 ; CHECK-NEXT:    vt.maskc a0, a1, a0
 ; CHECK-NEXT:    ret
   %rc = icmp ne i64 %a, 0
   %sel = select i1 %rc, i64 %rs1, i64 0
   ret i64 %sel
 }
 
 define i64 @zero2_setne_zero(i64 %a, i64 %rs1) {
 ; CHECK-LABEL: zero2_setne_zero:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    snez a0, a0
 ; CHECK-NEXT:    vt.maskcn a0, a1, a0
 ; CHECK-NEXT:    ret
   %rc = icmp ne i64 %a, 0
   %sel = select i1 %rc, i64 0, i64 %rs1
   ret i64 %sel
 }
 
 define i64 @zero1_seteq_constant(i64 %a, i64 %rs1) {
 ; CHECK-LABEL: zero1_seteq_constant:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, a0, 231
-; CHECK-NEXT:    seqz a0, a0
-; CHECK-NEXT:    vt.maskc a0, a1, a0
+; CHECK-NEXT:    vt.maskcn a0, a1, a0
 ; CHECK-NEXT:    ret
   %rc = icmp eq i64 %a, -231
   %sel = select i1 %rc, i64 %rs1, i64 0
   ret i64 %sel
 }
 
 define i64 @zero2_seteq_constant(i64 %a, i64 %rs1) {
 ; CHECK-LABEL: zero2_seteq_constant:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, a0, -546
-; CHECK-NEXT:    seqz a0, a0
-; CHECK-NEXT:    vt.maskcn a0, a1, a0
+; CHECK-NEXT:    vt.maskc a0, a1, a0
 ; CHECK-NEXT:    ret
   %rc = icmp eq i64 %a, 546
   %sel = select i1 %rc, i64 0, i64 %rs1
   ret i64 %sel
 }
 
 define i64 @zero1_setne_constant(i64 %a, i64 %rs1) {
 ; CHECK-LABEL: zero1_setne_constant:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, a0, -321
-; CHECK-NEXT:    snez a0, a0
 ; CHECK-NEXT:    vt.maskc a0, a1, a0
 ; CHECK-NEXT:    ret
   %rc = icmp ne i64 %a, 321
   %sel = select i1 %rc, i64 %rs1, i64 0
   ret i64 %sel
 }
 
 define i64 @zero2_setne_constant(i64 %a, i64 %rs1) {
 ; CHECK-LABEL: zero2_setne_constant:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, a0, 654
-; CHECK-NEXT:    snez a0, a0
 ; CHECK-NEXT:    vt.maskcn a0, a1, a0
 ; CHECK-NEXT:    ret
   %rc = icmp ne i64 %a, -654
   %sel = select i1 %rc, i64 0, i64 %rs1
   ret i64 %sel
 }
 
 define i64 @zero1_seteq_neg2048(i64 %a, i64 %rs1) {
 ; CHECK-LABEL: zero1_seteq_neg2048:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xori a0, a0, -2048
-; CHECK-NEXT:    seqz a0, a0
-; CHECK-NEXT:    vt.maskc a0, a1, a0
+; CHECK-NEXT:    vt.maskcn a0, a1, a0
 ; CHECK-NEXT:    ret
   %rc = icmp eq i64 %a, -2048
   %sel = select i1 %rc, i64 %rs1, i64 0
   ret i64 %sel
 }
 
 define i64 @zero2_seteq_neg2048(i64 %a, i64 %rs1) {
 ; CHECK-LABEL: zero2_seteq_neg2048:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xori a0, a0, -2048
-; CHECK-NEXT:    seqz a0, a0
-; CHECK-NEXT:    vt.maskcn a0, a1, a0
+; CHECK-NEXT:    vt.maskc a0, a1, a0
 ; CHECK-NEXT:    ret
   %rc = icmp eq i64 %a, -2048
   %sel = select i1 %rc, i64 0, i64 %rs1
   ret i64 %sel
 }
 
 define i64 @zero1_setne_neg2048(i64 %a, i64 %rs1) {
 ; CHECK-LABEL: zero1_setne_neg2048:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xori a0, a0, -2048
-; CHECK-NEXT:    snez a0, a0
 ; CHECK-NEXT:    vt.maskc a0, a1, a0
 ; CHECK-NEXT:    ret
   %rc = icmp ne i64 %a, -2048
   %sel = select i1 %rc, i64 %rs1, i64 0
   ret i64 %sel
 }
 
 define i64 @zero2_setne_neg2048(i64 %a, i64 %rs1) {
 ; CHECK-LABEL: zero2_setne_neg2048:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xori a0, a0, -2048
-; CHECK-NEXT:    snez a0, a0
 ; CHECK-NEXT:    vt.maskcn a0, a1, a0
 ; CHECK-NEXT:    ret
   %rc = icmp ne i64 %a, -2048
   %sel = select i1 %rc, i64 0, i64 %rs1
   ret i64 %sel
 }
 
 ; Test that we are able to convert the sext.w int he loop to mv.