[PowerPC] Use Power9 test data class instruction to lower IS_FPCLASS

[qiucf]

Summary

Power ISA 3.0 introduced new 'test data class' instructions (xststdc(s|d|q)p and xvtstdc(s|d)p), which accept flags for: NaN, +Infinity, -Infinity, +Zero, -Zero, +Denormal, -Denormal.

This instruction can be used to implement custom lowering for llvm.is.fpclass intrinsic, but some extra bits provided by the intrinsic are missing: +Normal, -Normal, QNaN, SNaN ('normal' means a number is not inf/nan/zero/denormal). For those, this patch uses a two-way or three-way combination to implement correct behavior:

• For flags including both +Normal/-Normal, try reverse flags to avoid them.
• For flags including either +Normal/-Normal, try the rest flags first, and use method above with sign check.
• For flags including either QNaN/SNaN, try the rest flags first, and test 'whether it's NaN' with quiet bit set/unset.

I tested all flags (2**10=1024) against one value from every class with float/double/fp128 type (3*10), and compare result with Power8, all 30720 cases pass on ppc64le. And all 20480 cases (fp128 is not supported) pass on ppc64/ppc32.

Nearly all 3072 cases see improvement, except some shown in changes of is_fpclass.ll.

[qiucf]

llvm/test/CodeGen/PowerPC/is_fpclass.ll

577

When return type is zeroext i1, this should be:

xscvdpspn 0, 1
mffprwz	3, 0
rlwinm 3, 3, 9, 23, 31
subfic 3, 3, 254
rldicl 3, 3, 1, 63

1 less instruction than new codegen.

[qiucf]

Gentle ping... Any comments?

[sepavloff]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

10958

It is better to use FPClassTest instead of unsigned.

10988

If Mask were FPClassTest, & fcAllFlags could be omitted.

10995

Should it be Mask & ~fcNormal?

11065

Should it be (Mask & fcNan) == fcNan)?

[sepavloff]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

11186

According to the LLVM coding stype (https://llvm.org/docs/CodingStandards.html#do-not-use-braced-initializer-lists-to-call-a-constructor) constructor with parentheses should be used. It also applies to some initializations below.

11205

It seems that if Mask is fcNormal (which is fcPosNormal | fcNegNormal), the OR node is not needed.

11215

Mask & ~fcNan should be enough.

[qiucf]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

11205

It's already been handled by previous condition (Mask & fcNormal) == fcNormal.

[sepavloff]

LGTM.

I am not proficient in Power ISA and rely on the results of testing mentioned in the patch summary.

[qiucf]

Hi @nemanjai @shchenz do you have any comments? I verified the behavior of new codegen again, all okay on ppc64le/ppc64/ppc32

[shchenz]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

11151

Should we check isKnownNeverNaN() or isKnownNeverZeroFloat() first before we really compute the class? (we may need to add isKnownNeverInfinity() and isKnownNeverSubnormal()). With these functions, we can handle some compile-time class. For example, the Op is a fp constant.

11207

Do we need the OR if Mask == fcPosNormal || Mask == fcNegNormal ?

11244

Will we generate an illegal type if useCRBits() is set to false?

11248

Same as above, we may not need the OR is we only test SNAN or QNAN?

[qiucf]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

11151

I think they were already handled in constant folding/earlycse before ISel. Following code still produces folded result after this patch on pwr9:

define zeroext i1 @fpclass() {
entry:
  %x = call i1 @llvm.is.fpclass.f64(double 0.0, i32 64)
  ret i1 %x
}
declare i1 @llvm.is.fpclass.f64(double, i32)

SystemZ implementation does also not include constant folding.

[shchenz]

Looks reasonable to me too. Thanks for making this improvement.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

11151

OK. Let's improve this later if we find a pattern that is created during ISEL. I agree if the pattern is created before, we should handle it in inst combine phase.

llvm/lib/Target/PowerPC/PPCISelLowering.h

     SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerVPERM(SDValue Op, SelectionDAG &DAG, ArrayRef<int> PermMask,
                        EVT VT, SDValue V1, SDValue V2) const;
     SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerBSWAP(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
+    SDValue LowerIS_FPCLASS(SDValue Op, SelectionDAG &DAG) const;
     SDValue lowerToLibCall(const char *LibCallName, SDValue Op,
                            SelectionDAG &DAG) const;
     SDValue lowerLibCallBasedOnType(const char *LibCallFloatName,
                                     const char *LibCallDoubleName, SDValue Op,
                                     SelectionDAG &DAG) const;
     bool isLowringToMASSFiniteSafe(SDValue Op) const;
     bool isLowringToMASSSafe(SDValue Op) const;
     bool isScalarMASSConversionEnabled() const;

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

       addRegisterClass(MVT::v2i64, &PPC::VRRCRegClass);
       addRegisterClass(MVT::v1i128, &PPC::VRRCRegClass);
     }
 
     if (Subtarget.hasP9Vector()) {
       setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
       setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
 
+      setOperationAction(ISD::IS_FPCLASS, MVT::f32, Custom);
+      setOperationAction(ISD::IS_FPCLASS, MVT::f64, Custom);
+      setOperationAction(ISD::IS_FPCLASS, MVT::f128, Custom);
+
       // 128 bit shifts can be accomplished via 3 instructions for SHL and
       // SRL, but not for SRA because of the instructions available:
       // VS{RL} and VS{RL}O.
       setOperationAction(ISD::SHL, MVT::v1i128, Legal);
       setOperationAction(ISD::SRL, MVT::v1i128, Legal);
       setOperationAction(ISD::SRA, MVT::v1i128, Expand);
 
       setOperationAction(ISD::FADD, MVT::f128, Legal);

     return DAG.getMemIntrinsicNode(ISD::INTRINSIC_VOID, dl, Tys, Ops, MemVT,
                                    N->getMemOperand());
   }
   default:
     llvm_unreachable("Unexpected atomic opcode");
   }
 }
 
+static SDValue getDataClassTest(SDValue Op, unsigned Mask, const SDLoc &Dl,
+                                SelectionDAG &DAG,
+                                const PPCSubtarget &Subtarget) {
+  assert(Mask <= fcAllFlags && "Invalid fp_class flags!");
+
+  enum DataClassMask {
+    DC_NAN = 1 << 6,
+    DC_NEG_INF = 1 << 4,
+    DC_POS_INF = 1 << 5,
+    DC_NEG_ZERO = 1 << 2,
+    DC_POS_ZERO = 1 << 3,
+    DC_NEG_SUBNORM = 1,
+    DC_POS_SUBNORM = 1 << 1,
+  };
+
+  EVT VT = Op.getValueType();
+
+  unsigned TestOp = VT == MVT::f128  ? PPC::XSTSTDCQP
+                    : VT == MVT::f64 ? PPC::XSTSTDCDP
+                                     : PPC::XSTSTDCSP;
+
+  if (Mask == fcAllFlags)
+    return DAG.getBoolConstant(true, Dl, MVT::i1, VT);
+  if (Mask == 0)
+    return DAG.getBoolConstant(false, Dl, MVT::i1, VT);
+
+  // When it's cheaper or necessary to test reverse flags.
+  if ((Mask & fcNormal) == fcNormal || Mask == (fcAllFlags ^ fcQNan) ||
+      Mask == (fcAllFlags ^ fcSNan)) {
+    SDValue Rev =
+        getDataClassTest(Op, (~Mask) & fcAllFlags, Dl, DAG, Subtarget);
+    return DAG.getNOT(Dl, Rev, MVT::i1);
+  }
+
+  // Power doesn't support testing whether a value is 'normal'. Test the rest
+  // first, and test if it's 'not not-normal' with expected sign.
+  if ((Mask & fcNormal) != 0) {
+    SDValue Rest = getDataClassTest(Op, Mask & (fcAllFlags ^ fcNormal), Dl, DAG,
+                                    Subtarget);
+    SDValue Rev{DAG.getMachineNode(
+                    TestOp, Dl, MVT::i32,
+                    DAG.getTargetConstant(DC_NAN | DC_NEG_INF | DC_POS_INF |
+                                              DC_NEG_ZERO | DC_POS_ZERO |
+                                              DC_NEG_SUBNORM | DC_POS_SUBNORM,
+                                          Dl, MVT::i32),
+                    Op),
+                0};
+    // Sign are stored in CR bit 0, result are in CR bit 2.
+    SDValue Sign{
+        DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, Dl, MVT::i1, Rev,
+                           DAG.getTargetConstant(PPC::sub_lt, Dl, MVT::i32)),
+        0};
+    SDValue Normal{DAG.getNOT(
+        Dl,
+        {DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, Dl, MVT::i1, Rev,
+                            DAG.getTargetConstant(PPC::sub_eq, Dl, MVT::i32)),
+         0},
+        MVT::i1)};
+    if (Mask & fcPosNormal)
+      Sign = DAG.getNOT(Dl, Sign, MVT::i1);
+    return DAG.getNode(ISD::OR, Dl, MVT::i1, Rest,
+                       DAG.getNode(ISD::AND, Dl, MVT::i1, Sign, Normal));
+  }
+
+  // The instruction doesn't differentiate between signaling or quiet NaN. Test
+  // the rest first, and test if it 'is NaN and is signaling/quiet'.
+  if ((Mask & fcNan) == fcQNan || (Mask & fcNan) == fcSNan) {
+    SDValue Rest =
+        getDataClassTest(Op, Mask & (fcAllFlags ^ fcNan), Dl, DAG, Subtarget);
+    bool IsQuiet = Mask & fcQNan;
+    SDValue NanCheck = getDataClassTest(Op, fcNan, Dl, DAG, Subtarget);
+
+    // Quietness is determined by the first bit in fraction field.
+    uint64_t QuietMask = 0;
+    SDValue HighWord;
+    if (VT == MVT::f128) {
+      HighWord = DAG.getNode(
+          ISD::EXTRACT_VECTOR_ELT, Dl, MVT::i32, DAG.getBitcast(MVT::v4i32, Op),
+          DAG.getVectorIdxConstant(Subtarget.isLittleEndian() ? 3 : 0, Dl));
+      QuietMask = 0x8000;
+    } else if (VT == MVT::f64) {
+      if (Subtarget.isPPC64()) {
+        HighWord = DAG.getNode(ISD::EXTRACT_ELEMENT, Dl, MVT::i32,
+                               DAG.getBitcast(MVT::i64, Op),
+                               DAG.getConstant(1, Dl, MVT::i32));
+      } else {
+        SDValue Vec = DAG.getBitcast(
+            MVT::v4i32, DAG.getNode(ISD::SCALAR_TO_VECTOR, Dl, MVT::v2f64, Op));
+        HighWord = DAG.getNode(
+            ISD::EXTRACT_VECTOR_ELT, Dl, MVT::i32, Vec,
+            DAG.getVectorIdxConstant(Subtarget.isLittleEndian() ? 1 : 0, Dl));
+      }
+      QuietMask = 0x80000;
+    } else if (VT == MVT::f32) {
+      HighWord = DAG.getBitcast(MVT::i32, Op);
+      QuietMask = 0x400000;
+    }
+    SDValue NanRes = DAG.getSetCC(
+        Dl, MVT::i1,
+        DAG.getNode(ISD::AND, Dl, MVT::i32, HighWord,
+                    DAG.getConstant(QuietMask, Dl, MVT::i32)),
+        DAG.getConstant(0, Dl, MVT::i32), IsQuiet ? ISD::SETNE : ISD::SETEQ);
+    return DAG.getNode(ISD::OR, Dl, MVT::i1, Rest,
+                       DAG.getNode(ISD::AND, Dl, MVT::i1, NanCheck, NanRes));
+  }
+
+  unsigned NativeMask = 0;
+  if (Mask & fcNan)
+    NativeMask |= DC_NAN;
+  if (Mask & fcNegInf)
+    NativeMask |= DC_NEG_INF;
+  if (Mask & fcPosInf)
+    NativeMask |= DC_POS_INF;
+  if (Mask & fcNegZero)
+    NativeMask |= DC_NEG_ZERO;
+  if (Mask & fcPosZero)
+    NativeMask |= DC_POS_ZERO;
+  if (Mask & fcNegSubnormal)
+    NativeMask |= DC_NEG_SUBNORM;
+  if (Mask & fcPosSubnormal)
+    NativeMask |= DC_POS_SUBNORM;
+  return SDValue(DAG.getMachineNode(
+                     TargetOpcode::EXTRACT_SUBREG, Dl, MVT::i1,
+                     {DAG.getMachineNode(
+                          TestOp, Dl, MVT::i32,
+                          DAG.getTargetConstant(NativeMask, Dl, MVT::i32), Op),
+                      0},
+                     DAG.getTargetConstant(PPC::sub_eq, Dl, MVT::i32)),
+                 0);
+}
+
+SDValue PPCTargetLowering::LowerIS_FPCLASS(SDValue Op,
+                                           SelectionDAG &DAG) const {
+  assert(Subtarget.hasP9Vector() && "Test data class requires Power9");
+  SDValue LHS = Op.getOperand(0);
+  const auto *RHS = cast<ConstantSDNode>(Op.getOperand(1));
+  SDLoc Dl(Op);
+  unsigned Category = RHS->getZExtValue();
+  return getDataClassTest(LHS, Category, Dl, DAG, Subtarget);
+}
+
 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
                                                  SelectionDAG &DAG) const {
   SDLoc dl(Op);
   // Create a stack slot that is 16-byte aligned.
   MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
   int FrameIdx = MFI.CreateStackObject(16, Align(16), false);
   EVT PtrVT = getPointerTy(DAG.getDataLayout());
   SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);

       SDValue InsVecElt =
           DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v4i32, BitcastVector,
                       BitcastLoad, Op.getOperand(2));
       return DAG.getBitcast(MVT::v4f32, InsVecElt);
     }
   }
 
   if (Subtarget.isISA3_1()) {
     if ((VT == MVT::v2i64 || VT == MVT::v2f64) && !Subtarget.isPPC64())
       return SDValue();
     // On P10, we have legal lowering for constant and variable indices for
     // all vectors.
     if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 ||
         VT == MVT::v2i64 || VT == MVT::v4f32 || VT == MVT::v2f64)
       return Op;
   }
 

 }
 
 SDValue PPCTargetLowering::LowerVectorLoad(SDValue Op,
                                            SelectionDAG &DAG) const {
   SDLoc dl(Op);
   LoadSDNode *LN = cast<LoadSDNode>(Op.getNode());
   SDValue LoadChain = LN->getChain();
   SDValue BasePtr = LN->getBasePtr();
   EVT VT = Op.getValueType();
 
   if (VT != MVT::v256i1 && VT != MVT::v512i1)
     return Op;
 
   // Type v256i1 is used for pairs and v512i1 is used for accumulators.
   // Here we create 2 or 4 v16i8 loads to load the pair or accumulator value in
   // 2 or 4 vsx registers.
   assert((VT != MVT::v512i1 || Subtarget.hasMMA()) &&
          "Type unsupported without MMA");
   assert((VT != MVT::v256i1 || Subtarget.pairedVectorMemops()) &&
          "Type unsupported without paired vector support");

   case ISD::INTRINSIC_VOID:
     return LowerINTRINSIC_VOID(Op, DAG);
   case ISD::BSWAP:
     return LowerBSWAP(Op, DAG);
   case ISD::ATOMIC_CMP_SWAP:
     return LowerATOMIC_CMP_SWAP(Op, DAG);
   case ISD::ATOMIC_STORE:
     return LowerATOMIC_LOAD_STORE(Op, DAG);
+  case ISD::IS_FPCLASS:
+    return LowerIS_FPCLASS(Op, DAG);
   }
 }
 
 void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
                                            SmallVectorImpl<SDValue>&Results,
                                            SelectionDAG &DAG) const {
   SDLoc dl(N);
   switch (N->getOpcode()) {

llvm/test/CodeGen/PowerPC/is_fpclass.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 -verify-machineinstrs -o - %s | FileCheck %s
 
 
 define i1 @isnan_float(float %x) nounwind {
 ; CHECK-LABEL: isnan_float:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    fcmpu 0, 1, 1
+; CHECK-NEXT:    xststdcsp 0, 1, 64
 ; CHECK-NEXT:    li 3, 0
 ; CHECK-NEXT:    li 4, 1
-; CHECK-NEXT:    isel 3, 4, 3, 3
+; CHECK-NEXT:    iseleq 3, 4, 3
 ; CHECK-NEXT:    blr
   %1 = call i1 @llvm.is.fpclass.f32(float %x, i32 3)  ; nan
   ret i1 %1
 }
 
 define i1 @isnan_double(double %x) nounwind {
 ; CHECK-LABEL: isnan_double:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    fcmpu 0, 1, 1
+; CHECK-NEXT:    xststdcdp 0, 1, 64
 ; CHECK-NEXT:    li 3, 0
 ; CHECK-NEXT:    li 4, 1
-; CHECK-NEXT:    isel 3, 4, 3, 3
+; CHECK-NEXT:    iseleq 3, 4, 3
 ; CHECK-NEXT:    blr
   %1 = call i1 @llvm.is.fpclass.f64(double %x, i32 3)  ; nan
   ret i1 %1
 }
 
 define i1 @isnan_ppc_fp128(ppc_fp128 %x) nounwind {
 ; CHECK-LABEL: isnan_ppc_fp128:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fcmpu 0, 1, 1
 ; CHECK-NEXT:    li 3, 0
 ; CHECK-NEXT:    li 4, 1
 ; CHECK-NEXT:    isel 3, 4, 3, 3
 ; CHECK-NEXT:    blr
   %1 = call i1 @llvm.is.fpclass.ppcf128(ppc_fp128 %x, i32 3)  ; nan
   ret i1 %1
 }
 
 define i1 @isnan_f128(fp128 %x) nounwind {
 ; CHECK-LABEL: isnan_f128:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    xscmpuqp 0, 2, 2
+; CHECK-NEXT:    xststdcqp 0, 2, 64
 ; CHECK-NEXT:    li 3, 0
 ; CHECK-NEXT:    li 4, 1
-; CHECK-NEXT:    isel 3, 4, 3, 3
+; CHECK-NEXT:    iseleq 3, 4, 3
 ; CHECK-NEXT:    blr
   %1 = call i1 @llvm.is.fpclass.f128(fp128 %x, i32 3)  ; nan
   ret i1 %1
 }
 
 define i1 @isnan_float_strictfp(float %x) strictfp nounwind {
 ; CHECK-LABEL: isnan_float_strictfp:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    xscvdpspn 0, 1
-; CHECK-NEXT:    lis 4, 32640
-; CHECK-NEXT:    mffprwz 3, 0
-; CHECK-NEXT:    clrlwi 3, 3, 1
-; CHECK-NEXT:    cmpw 3, 4
+; CHECK-NEXT:    xststdcsp 0, 1, 64
 ; CHECK-NEXT:    li 3, 0
 ; CHECK-NEXT:    li 4, 1
-; CHECK-NEXT:    iselgt 3, 4, 3
+; CHECK-NEXT:    iseleq 3, 4, 3
 ; CHECK-NEXT:    blr
   %1 = call i1 @llvm.is.fpclass.f32(float %x, i32 3)  ; nan
   ret i1 %1
 }
 
 define i1 @isnan_double_strictfp(double %x) strictfp nounwind {
 ; CHECK-LABEL: isnan_double_strictfp:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    mffprd 3, 1
-; CHECK-NEXT:    li 4, 2047
-; CHECK-NEXT:    clrldi 3, 3, 1
-; CHECK-NEXT:    rldic 4, 4, 52, 1
-; CHECK-NEXT:    cmpd 3, 4
+; CHECK-NEXT:    xststdcdp 0, 1, 64
 ; CHECK-NEXT:    li 3, 0
 ; CHECK-NEXT:    li 4, 1
-; CHECK-NEXT:    iselgt 3, 4, 3
+; CHECK-NEXT:    iseleq 3, 4, 3
 ; CHECK-NEXT:    blr
   %1 = call i1 @llvm.is.fpclass.f64(double %x, i32 3)  ; nan
   ret i1 %1
 }
 
 define i1 @isnan_ppc_fp128_strictfp(ppc_fp128 %x) strictfp nounwind {
 ; CHECK-LABEL: isnan_ppc_fp128_strictfp:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    mffprd 3, 1
 ; CHECK-NEXT:    li 4, 2047
 ; CHECK-NEXT:    clrldi 3, 3, 1
 ; CHECK-NEXT:    rldic 4, 4, 52, 1
 ; CHECK-NEXT:    cmpd 3, 4
 ; CHECK-NEXT:    li 3, 0
 ; CHECK-NEXT:    li 4, 1
 ; CHECK-NEXT:    iselgt 3, 4, 3
 ; CHECK-NEXT:    blr
   %1 = call i1 @llvm.is.fpclass.ppcf128(ppc_fp128 %x, i32 3)  ; nan
   ret i1 %1
 }
 
 define i1 @isnan_f128_strictfp(fp128 %x) strictfp nounwind {
 ; CHECK-LABEL: isnan_f128_strictfp:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    stxv 34, -16(1)
-; CHECK-NEXT:    li 5, 32767
-; CHECK-NEXT:    ld 4, -8(1)
-; CHECK-NEXT:    ld 3, -16(1)
-; CHECK-NEXT:    rldic 5, 5, 48, 1
-; CHECK-NEXT:    clrldi 4, 4, 1
-; CHECK-NEXT:    cmpld 4, 5
-; CHECK-NEXT:    cmpd 1, 4, 5
-; CHECK-NEXT:    crandc 20, 5, 2
-; CHECK-NEXT:    cmpdi 1, 3, 0
-; CHECK-NEXT:    li 3, 1
-; CHECK-NEXT:    crandc 21, 2, 6
-; CHECK-NEXT:    crnor 20, 21, 20
-; CHECK-NEXT:    isel 3, 0, 3, 20
+; CHECK-NEXT:    xststdcqp 0, 2, 64
+; CHECK-NEXT:    li 3, 0
+; CHECK-NEXT:    li 4, 1
+; CHECK-NEXT:    iseleq 3, 4, 3
 ; CHECK-NEXT:    blr
   %1 = call i1 @llvm.is.fpclass.f128(fp128 %x, i32 3)  ; nan
   ret i1 %1
 }
 
 define i1 @isinf_float(float %x) nounwind {
 ; CHECK-LABEL: isinf_float:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    xscvdpspn 0, 1
-; CHECK-NEXT:    li 4, 1
-; CHECK-NEXT:    mffprwz 3, 0
-; CHECK-NEXT:    clrlwi 3, 3, 1
-; CHECK-NEXT:    xoris 3, 3, 32640
-; CHECK-NEXT:    cmplwi 3, 0
+; CHECK-NEXT:    xststdcsp 0, 1, 48
 ; CHECK-NEXT:    li 3, 0
+; CHECK-NEXT:    li 4, 1
 ; CHECK-NEXT:    iseleq 3, 4, 3
 ; CHECK-NEXT:    blr
   %1 = call i1 @llvm.is.fpclass.f32(float %x, i32 516)  ; 0x204 = "inf"
   ret i1 %1
 }
 
 define i1 @isinf_ppc_fp128(ppc_fp128 %x) nounwind {
 ; CHECK-LABEL: isinf_ppc_fp128:

 ; CHECK-NEXT:    blr
   %1 = call i1 @llvm.is.fpclass.ppcf128(ppc_fp128 %x, i32 516)  ; 0x204 = "inf"
   ret i1 %1
 }
 
 define i1 @isinf_f128(fp128 %x) nounwind {
 ; CHECK-LABEL: isinf_f128:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    stxv 34, -16(1)
-; CHECK-NEXT:    li 5, 32767
-; CHECK-NEXT:    ld 4, -8(1)
-; CHECK-NEXT:    ld 3, -16(1)
-; CHECK-NEXT:    rldic 5, 5, 48, 1
-; CHECK-NEXT:    clrldi 4, 4, 1
-; CHECK-NEXT:    xor 4, 4, 5
-; CHECK-NEXT:    or 3, 3, 4
-; CHECK-NEXT:    cntlzd 3, 3
-; CHECK-NEXT:    rldicl 3, 3, 58, 63
+; CHECK-NEXT:    xststdcqp 0, 2, 48
+; CHECK-NEXT:    li 3, 0
+; CHECK-NEXT:    li 4, 1
+; CHECK-NEXT:    iseleq 3, 4, 3
 ; CHECK-NEXT:    blr
   %1 = call i1 @llvm.is.fpclass.f128(fp128 %x, i32 516)  ; 0x204 = "inf"
   ret i1 %1
 }
 
 define i1 @isfinite_float(float %x) nounwind {
 ; CHECK-LABEL: isfinite_float:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    xscvdpspn 0, 1
-; CHECK-NEXT:    lis 4, 32640
-; CHECK-NEXT:    mffprwz 3, 0
-; CHECK-NEXT:    clrlwi 3, 3, 1
-; CHECK-NEXT:    cmpw 3, 4
-; CHECK-NEXT:    li 3, 0
-; CHECK-NEXT:    li 4, 1
-; CHECK-NEXT:    isellt 3, 4, 3
+; CHECK-NEXT:    xststdcsp 0, 1, 112
+; CHECK-NEXT:    li 3, 1
+; CHECK-NEXT:    iseleq 3, 0, 3
 ; CHECK-NEXT:    blr
   %1 = call i1 @llvm.is.fpclass.f32(float %x, i32 504)  ; 0x1f8 = "finite"
   ret i1 %1
 }
 
 define i1 @isfinite_f128(fp128 %x) nounwind {
 ; CHECK-LABEL: isfinite_f128:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    stxv 34, -16(1)
-; CHECK-NEXT:    li 4, 32767
-; CHECK-NEXT:    ld 3, -8(1)
-; CHECK-NEXT:    rldic 4, 4, 48, 1
-; CHECK-NEXT:    clrldi 3, 3, 1
-; CHECK-NEXT:    cmpd 3, 4
-; CHECK-NEXT:    li 3, 0
-; CHECK-NEXT:    li 4, 1
-; CHECK-NEXT:    isellt 3, 4, 3
+; CHECK-NEXT:    xststdcqp 0, 2, 112
+; CHECK-NEXT:    li 3, 1
+; CHECK-NEXT:    iseleq 3, 0, 3
 ; CHECK-NEXT:    blr
   %1 = call i1 @llvm.is.fpclass.f128(fp128 %x, i32 504)  ; 0x1f8 = "finite"
   ret i1 %1
 }
 
 define i1 @isnormal_float(float %x) nounwind {
 ; CHECK-LABEL: isnormal_float:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    xscvdpspn 0, 1
-; CHECK-NEXT:    li 4, 1
-; CHECK-NEXT:    mffprwz 3, 0
-; CHECK-NEXT:    clrlwi 3, 3, 1
-; CHECK-NEXT:    addis 3, 3, -128
-; CHECK-NEXT:    srwi 3, 3, 24
-; CHECK-NEXT:    cmplwi 3, 127
-; CHECK-NEXT:    li 3, 0
-; CHECK-NEXT:    isellt 3, 4, 3
+; CHECK-NEXT:    xststdcsp 0, 1, 127
+; CHECK-NEXT:    li 3, 1
+; CHECK-NEXT:    iseleq 3, 0, 3
 ; CHECK-NEXT:    blr
   %1 = call i1 @llvm.is.fpclass.f32(float %x, i32 264)  ; 0x108 = "normal"
   ret i1 %1
 }
 
 define i1 @isnormal_f128(fp128 %x) nounwind {
 ; CHECK-LABEL: isnormal_f128:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    stxv 34, -16(1)
-; CHECK-NEXT:    li 4, -1
-; CHECK-NEXT:    ld 3, -8(1)
-; CHECK-NEXT:    rldic 4, 4, 48, 0
-; CHECK-NEXT:    clrldi 3, 3, 1
-; CHECK-NEXT:    add 3, 3, 4
-; CHECK-NEXT:    li 4, 1
-; CHECK-NEXT:    rldicl 3, 3, 15, 49
-; CHECK-NEXT:    cmpldi 3, 16383
-; CHECK-NEXT:    li 3, 0
-; CHECK-NEXT:    isellt 3, 4, 3
+; CHECK-NEXT:    xststdcqp 0, 2, 127
+; CHECK-NEXT:    li 3, 1
+; CHECK-NEXT:    iseleq 3, 0, 3
 ; CHECK-NEXT:    blr
   %1 = call i1 @llvm.is.fpclass.f128(fp128 %x, i32 264)  ; 0x108 = "normal"
   ret i1 %1
 }
 
 define i1 @issubnormal_float(float %x) nounwind {
 ; CHECK-LABEL: issubnormal_float:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    xscvdpspn 0, 1
-; CHECK-NEXT:    lis 4, 127
-; CHECK-NEXT:    ori 4, 4, 65535
-; CHECK-NEXT:    mffprwz 3, 0
-; CHECK-NEXT:    clrlwi 3, 3, 1
-; CHECK-NEXT:    addi 3, 3, -1
-; CHECK-NEXT:    cmplw 3, 4
+; CHECK-NEXT:    xststdcsp 0, 1, 3
 ; CHECK-NEXT:    li 3, 0
 ; CHECK-NEXT:    li 4, 1
-; CHECK-NEXT:    isellt 3, 4, 3
+; CHECK-NEXT:    iseleq 3, 4, 3
 ; CHECK-NEXT:    blr
   %1 = call i1 @llvm.is.fpclass.f32(float %x, i32 144)  ; 0x90 = "subnormal"
   ret i1 %1
 }
 
 define i1 @issubnormal_f128(fp128 %x) nounwind {
 ; CHECK-LABEL: issubnormal_f128:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    stxv 34, -16(1)
-; CHECK-NEXT:    li 5, -1
-; CHECK-NEXT:    ld 4, -8(1)
-; CHECK-NEXT:    ld 3, -16(1)
-; CHECK-NEXT:    rldic 5, 5, 0, 16
-; CHECK-NEXT:    clrldi 4, 4, 1
-; CHECK-NEXT:    addic 3, 3, -1
-; CHECK-NEXT:    addme 4, 4
-; CHECK-NEXT:    cmpdi 1, 3, -1
-; CHECK-NEXT:    li 3, 1
-; CHECK-NEXT:    cmpld 4, 5
-; CHECK-NEXT:    crandc 20, 0, 2
-; CHECK-NEXT:    crandc 21, 2, 6
-; CHECK-NEXT:    crnor 20, 21, 20
-; CHECK-NEXT:    isel 3, 0, 3, 20
+; CHECK-NEXT:    xststdcqp 0, 2, 3
+; CHECK-NEXT:    li 3, 0
+; CHECK-NEXT:    li 4, 1
+; CHECK-NEXT:    iseleq 3, 4, 3
 ; CHECK-NEXT:    blr
   %1 = call i1 @llvm.is.fpclass.f128(fp128 %x, i32 144)  ; 0x90 = "subnormal"
   ret i1 %1
 }
 
 define i1 @iszero_float(float %x) nounwind {
 ; CHECK-LABEL: iszero_float:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    xxlxor 0, 0, 0
+; CHECK-NEXT:    xststdcsp 0, 1, 12
 ; CHECK-NEXT:    li 3, 0
 ; CHECK-NEXT:    li 4, 1
-; CHECK-NEXT:    fcmpu 0, 1, 0
 ; CHECK-NEXT:    iseleq 3, 4, 3
 ; CHECK-NEXT:    blr
   %1 = call i1 @llvm.is.fpclass.f32(float %x, i32 96)  ; 0x60 = "zero"
   ret i1 %1
 }
 
 define i1 @iszero_f128(fp128 %x) nounwind {
 ; CHECK-LABEL: iszero_f128:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addis 3, 2, .LCPI18_0@toc@ha
-; CHECK-NEXT:    li 4, 1
-; CHECK-NEXT:    addi 3, 3, .LCPI18_0@toc@l
-; CHECK-NEXT:    lxv 35, 0(3)
+; CHECK-NEXT:    xststdcqp 0, 2, 12
 ; CHECK-NEXT:    li 3, 0
-; CHECK-NEXT:    xscmpuqp 0, 2, 3
+; CHECK-NEXT:    li 4, 1
 ; CHECK-NEXT:    iseleq 3, 4, 3
 ; CHECK-NEXT:    blr
   %1 = call i1 @llvm.is.fpclass.f128(fp128 %x, i32 96)  ; 0x60 = "zero"
   ret i1 %1
 }
 
 define i1 @issnan_float(float %x) nounwind {
 ; CHECK-LABEL: issnan_float:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xscvdpspn 0, 1
-; CHECK-NEXT:    lis 4, 32704
+; CHECK-NEXT:    xststdcsp 1, 1, 64
 ; CHECK-NEXT:    mffprwz 3, 0
-; CHECK-NEXT:    clrlwi 3, 3, 1
-; CHECK-NEXT:    cmpw 3, 4
-; CHECK-NEXT:    lis 4, 32640
-; CHECK-NEXT:    cmpw 1, 3, 4
+; CHECK-NEXT:    andis. 3, 3, 64
 ; CHECK-NEXT:    li 3, 1
-; CHECK-NEXT:    crnand 20, 5, 0
+; CHECK-NEXT:    crnand 20, 6, 2
 ; CHECK-NEXT:    isel 3, 0, 3, 20
 ; CHECK-NEXT:    blr
   %1 = call i1 @llvm.is.fpclass.f32(float %x, i32 1)
   ret i1 %1
 }
 
 define i1 @issnan_double(double %x) nounwind {
 ; CHECK-LABEL: issnan_double:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    mffprd 3, 1
-; CHECK-NEXT:    li 4, 4095
-; CHECK-NEXT:    clrldi 3, 3, 1
-; CHECK-NEXT:    rldic 4, 4, 51, 1
-; CHECK-NEXT:    cmpd 3, 4
-; CHECK-NEXT:    li 4, 2047
-; CHECK-NEXT:    rldic 4, 4, 52, 1
-; CHECK-NEXT:    cmpd 1, 3, 4
+; CHECK-NEXT:    xststdcdp 1, 1, 64
+; CHECK-NEXT:    rldicl 3, 3, 32, 32
+; CHECK-NEXT:    andis. 3, 3, 8
 ; CHECK-NEXT:    li 3, 1
-; CHECK-NEXT:    crnand 20, 5, 0
+; CHECK-NEXT:    crnand 20, 6, 2
 ; CHECK-NEXT:    isel 3, 0, 3, 20
 ; CHECK-NEXT:    blr
   %1 = call i1 @llvm.is.fpclass.f64(double %x, i32 1)
   ret i1 %1
 }
 
 define i1 @issnan_fp128(fp128 %x) nounwind {
 ; CHECK-LABEL: issnan_fp128:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    stxv 34, -16(1)
-; CHECK-NEXT:    li 5, 32767
-; CHECK-NEXT:    ld 4, -8(1)
-; CHECK-NEXT:    ld 3, -16(1)
-; CHECK-NEXT:    rldic 5, 5, 48, 1
-; CHECK-NEXT:    clrldi 4, 4, 1
-; CHECK-NEXT:    cmpld 4, 5
-; CHECK-NEXT:    cmpd 1, 4, 5
-; CHECK-NEXT:    crandc 20, 5, 2
-; CHECK-NEXT:    cmpdi 1, 3, 0
-; CHECK-NEXT:    li 3, -1
-; CHECK-NEXT:    crandc 21, 2, 6
-; CHECK-NEXT:    rldic 3, 3, 47, 1
-; CHECK-NEXT:    cror 20, 21, 20
-; CHECK-NEXT:    cmpd 4, 3
+; CHECK-NEXT:    li 3, 12
+; CHECK-NEXT:    xststdcqp 1, 2, 64
+; CHECK-NEXT:    vextuwrx 3, 3, 2
+; CHECK-NEXT:    andi. 3, 3, 32768
 ; CHECK-NEXT:    li 3, 1
-; CHECK-NEXT:    crnand 20, 20, 0
+; CHECK-NEXT:    crnand 20, 6, 2
 ; CHECK-NEXT:    isel 3, 0, 3, 20
 ; CHECK-NEXT:    blr
   %1 = call i1 @llvm.is.fpclass.f128(fp128 %x, i32 1)
   ret i1 %1
 }
 
 define i1 @issnan_ppc_fp128(ppc_fp128 %x) nounwind {
 ; CHECK-LABEL: issnan_ppc_fp128:
; CHECK-NEXT:    blr
   %1 = call i1 @llvm.is.fpclass.ppcf128(ppc_fp128 %x, i32 1)
   ret i1 %1
 }
 
 define i1 @isqnan_float(float %x) nounwind {
 ; CHECK-LABEL: isqnan_float:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xscvdpspn 0, 1
-; CHECK-NEXT:    lis 4, 32703
-; CHECK-NEXT:    ori 4, 4, 65535
+; CHECK-NEXT:    xststdcsp 1, 1, 64
 ; CHECK-NEXT:    mffprwz 3, 0
-; CHECK-NEXT:    clrlwi 3, 3, 1
-; CHECK-NEXT:    cmpw 3, 4
-; CHECK-NEXT:    li 3, 0
-; CHECK-NEXT:    li 4, 1
-; CHECK-NEXT:    iselgt 3, 4, 3
+; CHECK-NEXT:    srwi 3, 3, 22
+; CHECK-NEXT:    andi. 3, 3, 1
+; CHECK-NEXT:    li 3, 1
+; CHECK-NEXT:    crnand 20, 6, 1
+; CHECK-NEXT:    isel 3, 0, 3, 20
 ; CHECK-NEXT:    blr
   %1 = call i1 @llvm.is.fpclass.f32(float %x, i32 2)
   ret i1 %1
 }
 
 define i1 @isqnan_double(double %x) nounwind {
 ; CHECK-LABEL: isqnan_double:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    mffprd 3, 1
-; CHECK-NEXT:    li 4, -17
-; CHECK-NEXT:    clrldi 3, 3, 1
-; CHECK-NEXT:    rldicl 4, 4, 47, 1
-; CHECK-NEXT:    cmpd 3, 4
-; CHECK-NEXT:    li 3, 0
-; CHECK-NEXT:    li 4, 1
-; CHECK-NEXT:    iselgt 3, 4, 3
+; CHECK-NEXT:    xststdcdp 1, 1, 64
+; CHECK-NEXT:    rldicl 3, 3, 13, 51
+; CHECK-NEXT:    andi. 3, 3, 1
+; CHECK-NEXT:    li 3, 1
+; CHECK-NEXT:    crnand 20, 6, 1
+; CHECK-NEXT:    isel 3, 0, 3, 20
 ; CHECK-NEXT:    blr
   %1 = call i1 @llvm.is.fpclass.f64(double %x, i32 2)
   ret i1 %1
 }
 
 define i1 @isqnan_fp128(fp128 %x) nounwind {
 ; CHECK-LABEL: isqnan_fp128:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    stxv 34, -16(1)
-; CHECK-NEXT:    li 4, -2
-; CHECK-NEXT:    ld 3, -8(1)
-; CHECK-NEXT:    rldicl 4, 4, 47, 1
-; CHECK-NEXT:    clrldi 3, 3, 1
-; CHECK-NEXT:    cmpd 3, 4
-; CHECK-NEXT:    li 3, 0
-; CHECK-NEXT:    li 4, 1
-; CHECK-NEXT:    iselgt 3, 4, 3
+; CHECK-NEXT:    li 3, 12
+; CHECK-NEXT:    xststdcqp 1, 2, 64
+; CHECK-NEXT:    vextuwrx 3, 3, 2
+; CHECK-NEXT:    srwi 3, 3, 15
+; CHECK-NEXT:    andi. 3, 3, 1
+; CHECK-NEXT:    li 3, 1
+; CHECK-NEXT:    crnand 20, 6, 1
+; CHECK-NEXT:    isel 3, 0, 3, 20
 ; CHECK-NEXT:    blr
   %1 = call i1 @llvm.is.fpclass.f128(fp128 %x, i32 2)
   ret i1 %1
 }
 
 define i1 @isqnan_ppc_fp128(ppc_fp128 %x) nounwind {
 ; CHECK-LABEL: isqnan_ppc_fp128:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    mffprd 3, 1
 ; CHECK-NEXT:    li 4, -17
 ; CHECK-NEXT:    clrldi 3, 3, 1
 ; CHECK-NEXT:    rldicl 4, 4, 47, 1
 ; CHECK-NEXT:    cmpd 3, 4
 ; CHECK-NEXT:    li 3, 0
 ; CHECK-NEXT:    li 4, 1
 ; CHECK-NEXT:    iselgt 3, 4, 3
 ; CHECK-NEXT:    blr
   %1 = call i1 @llvm.is.fpclass.ppcf128(ppc_fp128 %x, i32 2)
   ret i1 %1
 }
 
 define i1 @isposzero_double(double %x) nounwind {
 ; CHECK-LABEL: isposzero_double:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    mffprd 3, 1
-; CHECK-NEXT:    cntlzd 3, 3
-; CHECK-NEXT:    rldicl 3, 3, 58, 63
+; CHECK-NEXT:    xststdcdp 0, 1, 8
+; CHECK-NEXT:    li 3, 0
+; CHECK-NEXT:    li 4, 1
+; CHECK-NEXT:    iseleq 3, 4, 3
 ; CHECK-NEXT:    blr
   %1 = call i1 @llvm.is.fpclass.f64(double %x, i32 64)
   ret i1 %1
 }
 
 define i1 @isnegzero_double(double %x) nounwind {
 ; CHECK-LABEL: isnegzero_double:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    li 4, 1
-; CHECK-NEXT:    mffprd 3, 1
-; CHECK-NEXT:    rldic 5, 4, 63, 0
-; CHECK-NEXT:    cmpd 3, 5
+; CHECK-NEXT:    xststdcdp 0, 1, 4
 ; CHECK-NEXT:    li 3, 0
+; CHECK-NEXT:    li 4, 1
 ; CHECK-NEXT:    iseleq 3, 4, 3
 ; CHECK-NEXT:    blr
   %1 = call i1 @llvm.is.fpclass.f64(double %x, i32 32)
   ret i1 %1
 }
 
 define i1 @isposnormal_double(double %x) nounwind {
 ; CHECK-LABEL: isposnormal_double:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    mffprd 3, 1
-; CHECK-NEXT:    li 5, 4095
-; CHECK-NEXT:    clrldi 4, 3, 1
-; CHECK-NEXT:    rldic 5, 5, 52, 0
-; CHECK-NEXT:    cmpdi 1, 3, -1
-; CHECK-NEXT:    li 3, 1
-; CHECK-NEXT:    add 4, 4, 5
-; CHECK-NEXT:    rldicl 4, 4, 11, 53
-; CHECK-NEXT:    cmpldi 4, 1023
-; CHECK-NEXT:    crnand 20, 0, 5
+; CHECK-NEXT:    xststdcdp 0, 1, 127
+; CHECK-NEXT:    li 3, 1
+; CHECK-NEXT:    cror 20, 0, 2
 ; CHECK-NEXT:    isel 3, 0, 3, 20
 ; CHECK-NEXT:    blr
   %1 = call i1 @llvm.is.fpclass.f64(double %x, i32 256)
   ret i1 %1
 }
 
 define i1 @isnegnormal_double(double %x) nounwind {
 ; CHECK-LABEL: isnegnormal_double:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    mffprd 3, 1
-; CHECK-NEXT:    li 5, 4095
-; CHECK-NEXT:    clrldi 4, 3, 1
-; CHECK-NEXT:    rldic 5, 5, 52, 0
-; CHECK-NEXT:    cmpdi 1, 3, 0
-; CHECK-NEXT:    li 3, 1
-; CHECK-NEXT:    add 4, 4, 5
-; CHECK-NEXT:    rldicl 4, 4, 11, 53
-; CHECK-NEXT:    cmpldi 4, 1023
-; CHECK-NEXT:    crnand 20, 0, 4
+; CHECK-NEXT:    xststdcdp 0, 1, 127
+; CHECK-NEXT:    li 3, 1
+; CHECK-NEXT:    crorc 20, 2, 0
 ; CHECK-NEXT:    isel 3, 0, 3, 20
 ; CHECK-NEXT:    blr
   %1 = call i1 @llvm.is.fpclass.f64(double %x, i32 8)
   ret i1 %1
 }
 
 define i1 @isnormal_double(double %x) nounwind {
 ; CHECK-LABEL: isnormal_double:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    mffprd 3, 1
-; CHECK-NEXT:    li 4, 4095
-; CHECK-NEXT:    clrldi 3, 3, 1
-; CHECK-NEXT:    rldic 4, 4, 52, 0
-; CHECK-NEXT:    add 3, 3, 4
-; CHECK-NEXT:    li 4, 1
-; CHECK-NEXT:    rldicl 3, 3, 11, 53
-; CHECK-NEXT:    cmpldi 3, 1023
-; CHECK-NEXT:    li 3, 0
-; CHECK-NEXT:    isellt 3, 4, 3
+; CHECK-NEXT:    xststdcdp 0, 1, 127
+; CHECK-NEXT:    li 3, 1
+; CHECK-NEXT:    iseleq 3, 0, 3
 ; CHECK-NEXT:    blr
   %1 = call i1 @llvm.is.fpclass.f64(double %x, i32 264)
   ret i1 %1
 }
 
 define i1 @isclass_00d_double(double %x) nounwind {
 ; CHECK-LABEL: isclass_00d_double:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    mffprd 3, 1
-; CHECK-NEXT:    li 5, 4095
-; CHECK-NEXT:    clrldi 4, 3, 1
-; CHECK-NEXT:    rldic 6, 5, 51, 1
-; CHECK-NEXT:    rldic 5, 5, 52, 0
-; CHECK-NEXT:    cmpd 4, 6
-; CHECK-NEXT:    li 6, 2047
-; CHECK-NEXT:    rldic 6, 6, 52, 1
-; CHECK-NEXT:    cmpd 1, 4, 6
-; CHECK-NEXT:    add 4, 4, 5
-; CHECK-NEXT:    crand 20, 5, 0
-; CHECK-NEXT:    cmpd 3, 5
-; CHECK-NEXT:    rldicl 4, 4, 11, 53
-; CHECK-NEXT:    cmpdi 1, 3, 0
-; CHECK-NEXT:    li 3, 1
-; CHECK-NEXT:    cror 20, 2, 20
-; CHECK-NEXT:    cmpldi 4, 1023
-; CHECK-NEXT:    crand 21, 0, 4
-; CHECK-NEXT:    crnor 20, 20, 21
+; CHECK-NEXT:    xststdcdp 0, 1, 127
+; CHECK-NEXT:    xststdcdp 1, 1, 64
+; CHECK-NEXT:    rldicl 3, 3, 32, 32
+; CHECK-NEXT:    crandc 20, 0, 2
+; CHECK-NEXT:    andis. 3, 3, 8
+; CHECK-NEXT:    li 3, 1
+; CHECK-NEXT:    crand 21, 6, 2
+; CHECK-NEXT:    xststdcdp 0, 1, 16
+; CHECK-NEXT:    cror 21, 2, 21
+; CHECK-NEXT:    crnor 20, 21, 20
 ; CHECK-NEXT:    isel 3, 0, 3, 20
 ; CHECK-NEXT:    blr
   %1 = call i1 @llvm.is.fpclass.f64(double %x, i32 13)
   ret i1 %1
 }
 
 define i1 @isclass_1c0_float(float %x) nounwind {
 ; CHECK-LABEL: isclass_1c0_float:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    xscvdpspn 0, 1
-; CHECK-NEXT:    li 4, 1
-; CHECK-NEXT:    mffprwz 3, 0
-; CHECK-NEXT:    srwi 3, 3, 23
-; CHECK-NEXT:    cmplwi 3, 255
-; CHECK-NEXT:    li 3, 0
-; CHECK-NEXT:    isellt 3, 4, 3
+; CHECK-NEXT:    xststdcsp 0, 1, 127
+; CHECK-NEXT:    li 3, 1
+; CHECK-NEXT:    crnor 20, 0, 2
+; CHECK-NEXT:    xststdcsp 0, 1, 10
+; CHECK-NEXT:    crnor 20, 2, 20
+; CHECK-NEXT:    isel 3, 0, 3, 20
 ; CHECK-NEXT:    blr
   %1 = call i1 @llvm.is.fpclass.f32(float %x, i32 448)
   ret i1 %1
 }
 
 declare i1 @llvm.is.fpclass.f32(float, i32)
 declare i1 @llvm.is.fpclass.f64(double, i32)
 declare i1 @llvm.is.fpclass.ppcf128(ppc_fp128, i32)
 declare i1 @llvm.is.fpclass.f128(fp128, i32)