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Differential D140103

[SPIR-V] Disable MachineLateInstrsCleanup pass
ClosedPublic

Authored by mpaszkowski on Dec 15 2022, 6:33 AM.

Details

Reviewers
iliya-diyachkov
konrad.trifunovic
zuban32
MaskRay
rengolin
jonpa
Commits
rG3a26a650821d: [SPIR-V] Disable MachineLateInstrsCleanup pass
Summary

This change:

  • Disables MachineLateInstrsCleanup pass since it does not work with virtual registers
  • Makes all LIT tests run with -O0

Diff Detail

Event Timeline

mpaszkowski created this revision.Dec 15 2022, 6:33 AM
Herald added a project: Restricted Project. · View Herald TranscriptDec 15 2022, 6:33 AM
Herald added subscribers: StephenFan, ThomasRaoux, hiraditya. · View Herald Transcript
mpaszkowski requested review of this revision.Dec 15 2022, 6:33 AM
Herald added a project: Restricted Project. · View Herald TranscriptDec 15 2022, 6:33 AM
Herald added a subscriber: llvm-commits. · View Herald Transcript
Harbormaster completed remote builds in B203337: Diff 483161.Dec 15 2022, 7:52 AM
jonpa added a comment.Dec 15 2022, 8:19 AM

Sorry - I disabled this already for NVPTX and WebAssembly for the same reason but must have missed that SPIRV does not do regalloc when no SPIRV tests at all changed.

mpaszkowski added a comment.Dec 15 2022, 8:22 AM
In D140103#3998038, @jonpa wrote:

Sorry - I disabled this already for NVPTX and WebAssembly for the same reason but must have missed that SPIRV does not do regalloc when no SPIRV tests at all changed.

No problem! SPIR-V tests did not run since the backend is experimental and not built in default CMake configuration.

iliya-diyachkov added inline comments.Dec 15 2022, 12:16 PM
llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp
129

Please remove the extra whitespace in the empty line.

iliya-diyachkov accepted this revision.Dec 15 2022, 12:43 PM

In other respects, it looks good to me.

This revision is now accepted and ready to land.Dec 15 2022, 12:43 PM
mpaszkowski updated this revision to Diff 483851.Dec 18 2022, 4:16 PM
mpaszkowski marked an inline comment as done.
Harbormaster completed remote builds in B203836: Diff 483851.Dec 18 2022, 5:10 PM
Closed by commit rG3a26a650821d: [SPIR-V] Disable MachineLateInstrsCleanup pass (authored by mpaszkowski). · Explain WhyDec 19 2022, 10:27 AM
This revision was automatically updated to reflect the committed changes.
mpaszkowski added a commit: rG3a26a650821d: [SPIR-V] Disable MachineLateInstrsCleanup pass.

Revision Contents

PathSize
llvm/
lib/
Target/
SPIRV/
1 line
test/
CodeGen/
SPIRV/
instructions/
2 lines
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Diff 484002

llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp

Show First 20 Lines • Show All 118 Lines • ▼ Show 20 Linesvoid SPIRVPassConfig::addPostRegAlloc() {
disablePass(&MachineCopyPropagationID); disablePass(&MachineCopyPropagationID);
disablePass(&PostRAMachineSinkingID); disablePass(&PostRAMachineSinkingID);
disablePass(&PostRASchedulerID); disablePass(&PostRASchedulerID);
disablePass(&FuncletLayoutID); disablePass(&FuncletLayoutID);
disablePass(&StackMapLivenessID); disablePass(&StackMapLivenessID);
disablePass(&PatchableFunctionID); disablePass(&PatchableFunctionID);
disablePass(&ShrinkWrapID); disablePass(&ShrinkWrapID);
disablePass(&LiveDebugValuesID); disablePass(&LiveDebugValuesID);
disablePass(&MachineLateInstrsCleanupID);
// Do not work with OpPhi. // Do not work with OpPhi.
iliya-diyachkovUnsubmitted
Done
ReplyInline Actions

Please remove the extra whitespace in the empty line.

iliya-diyachkov: Please remove the extra whitespace in the empty line.
disablePass(&BranchFolderPassID); disablePass(&BranchFolderPassID);
disablePass(&MachineBlockPlacementID); disablePass(&MachineBlockPlacementID);
TargetPassConfig::addPostRegAlloc(); TargetPassConfig::addPostRegAlloc();
} }
TargetTransformInfo TargetTransformInfo
SPIRVTargetMachine::getTargetTransformInfo(const Function &F) const { SPIRVTargetMachine::getTargetTransformInfo(const Function &F) const {
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llvm/test/CodeGen/SPIRV/instructions/atomic.ll

; RUN: llc -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
; CHECK-DAG: OpName [[ADD:%.*]] "test_add" ; CHECK-DAG: OpName [[ADD:%.*]] "test_add"
; CHECK-DAG: OpName [[SUB:%.*]] "test_sub" ; CHECK-DAG: OpName [[SUB:%.*]] "test_sub"
; CHECK-DAG: OpName [[MIN:%.*]] "test_min" ; CHECK-DAG: OpName [[MIN:%.*]] "test_min"
; CHECK-DAG: OpName [[MAX:%.*]] "test_max" ; CHECK-DAG: OpName [[MAX:%.*]] "test_max"
; CHECK-DAG: OpName [[UMIN:%.*]] "test_umin" ; CHECK-DAG: OpName [[UMIN:%.*]] "test_umin"
; CHECK-DAG: OpName [[UMAX:%.*]] "test_umax" ; CHECK-DAG: OpName [[UMAX:%.*]] "test_umax"
; CHECK-DAG: OpName [[AND:%.*]] "test_and" ; CHECK-DAG: OpName [[AND:%.*]] "test_and"
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llvm/test/CodeGen/SPIRV/instructions/atomic_acqrel.ll

; RUN: llc -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
; CHECK-DAG: OpName [[ADD:%.*]] "test_add" ; CHECK-DAG: OpName [[ADD:%.*]] "test_add"
; CHECK-DAG: OpName [[SUB:%.*]] "test_sub" ; CHECK-DAG: OpName [[SUB:%.*]] "test_sub"
; CHECK-DAG: OpName [[MIN:%.*]] "test_min" ; CHECK-DAG: OpName [[MIN:%.*]] "test_min"
; CHECK-DAG: OpName [[MAX:%.*]] "test_max" ; CHECK-DAG: OpName [[MAX:%.*]] "test_max"
; CHECK-DAG: OpName [[UMIN:%.*]] "test_umin" ; CHECK-DAG: OpName [[UMIN:%.*]] "test_umin"
; CHECK-DAG: OpName [[UMAX:%.*]] "test_umax" ; CHECK-DAG: OpName [[UMAX:%.*]] "test_umax"
; CHECK-DAG: OpName [[AND:%.*]] "test_and" ; CHECK-DAG: OpName [[AND:%.*]] "test_and"
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llvm/test/CodeGen/SPIRV/instructions/atomic_seq.ll

; RUN: llc -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
; CHECK-DAG: OpName [[ADD:%.*]] "test_add" ; CHECK-DAG: OpName [[ADD:%.*]] "test_add"
; CHECK-DAG: OpName [[SUB:%.*]] "test_sub" ; CHECK-DAG: OpName [[SUB:%.*]] "test_sub"
; CHECK-DAG: OpName [[MIN:%.*]] "test_min" ; CHECK-DAG: OpName [[MIN:%.*]] "test_min"
; CHECK-DAG: OpName [[MAX:%.*]] "test_max" ; CHECK-DAG: OpName [[MAX:%.*]] "test_max"
; CHECK-DAG: OpName [[UMIN:%.*]] "test_umin" ; CHECK-DAG: OpName [[UMIN:%.*]] "test_umin"
; CHECK-DAG: OpName [[UMAX:%.*]] "test_umax" ; CHECK-DAG: OpName [[UMAX:%.*]] "test_umax"
; CHECK-DAG: OpName [[AND:%.*]] "test_and" ; CHECK-DAG: OpName [[AND:%.*]] "test_and"
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llvm/test/CodeGen/SPIRV/instructions/fcmp.ll

; RUN: llc -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
; CHECK-DAG: OpName [[UEQ:%.*]] "test_ueq" ; CHECK-DAG: OpName [[UEQ:%.*]] "test_ueq"
; CHECK-DAG: OpName [[OEQ:%.*]] "test_oeq" ; CHECK-DAG: OpName [[OEQ:%.*]] "test_oeq"
; CHECK-DAG: OpName [[UNE:%.*]] "test_une" ; CHECK-DAG: OpName [[UNE:%.*]] "test_une"
; CHECK-DAG: OpName [[ONE:%.*]] "test_one" ; CHECK-DAG: OpName [[ONE:%.*]] "test_one"
; CHECK-DAG: OpName [[ULT:%.*]] "test_ult" ; CHECK-DAG: OpName [[ULT:%.*]] "test_ult"
; CHECK-DAG: OpName [[OLT:%.*]] "test_olt" ; CHECK-DAG: OpName [[OLT:%.*]] "test_olt"
; CHECK-DAG: OpName [[ULE:%.*]] "test_ule" ; CHECK-DAG: OpName [[ULE:%.*]] "test_ule"
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llvm/test/CodeGen/SPIRV/instructions/float-casts.ll

; RUN: llc -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
; CHECK-DAG: OpName [[TRUNC32_16:%.*]] "f32tof16" ; CHECK-DAG: OpName [[TRUNC32_16:%.*]] "f32tof16"
; CHECK-DAG: OpName [[EXT16_32:%.*]] "f16tof32" ; CHECK-DAG: OpName [[EXT16_32:%.*]] "f16tof32"
; CHECK-DAG: OpName [[TRUNC32_16v3:%.*]] "f32tof16v3" ; CHECK-DAG: OpName [[TRUNC32_16v3:%.*]] "f32tof16v3"
; CHECK-DAG: OpName [[EXT16_32v3:%.*]] "f16tof32v3" ; CHECK-DAG: OpName [[EXT16_32v3:%.*]] "f16tof32v3"
; CHECK-DAG: OpName [[F32toS32:%.*]] "f32tos32" ; CHECK-DAG: OpName [[F32toS32:%.*]] "f32tos32"
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llvm/test/CodeGen/SPIRV/instructions/icmp.ll

; RUN: llc -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
; CHECK-DAG: OpName [[EQ:%.*]] "test_eq" ; CHECK-DAG: OpName [[EQ:%.*]] "test_eq"
; CHECK-DAG: OpName [[NE:%.*]] "test_ne" ; CHECK-DAG: OpName [[NE:%.*]] "test_ne"
; CHECK-DAG: OpName [[ULT:%.*]] "test_ult" ; CHECK-DAG: OpName [[ULT:%.*]] "test_ult"
; CHECK-DAG: OpName [[SLT:%.*]] "test_slt" ; CHECK-DAG: OpName [[SLT:%.*]] "test_slt"
; CHECK-DAG: OpName [[ULE:%.*]] "test_ule" ; CHECK-DAG: OpName [[ULE:%.*]] "test_ule"
; CHECK-DAG: OpName [[SLE:%.*]] "test_sle" ; CHECK-DAG: OpName [[SLE:%.*]] "test_sle"
; CHECK-DAG: OpName [[UGT:%.*]] "test_ugt" ; CHECK-DAG: OpName [[UGT:%.*]] "test_ugt"
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llvm/test/CodeGen/SPIRV/instructions/integer-casts.ll

; RUN: llc -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
; CHECK-DAG: OpName [[TRUNC32_16:%.*]] "i32toi16" ; CHECK-DAG: OpName [[TRUNC32_16:%.*]] "i32toi16"
; CHECK-DAG: OpName [[TRUNC32_8:%.*]] "i32toi8" ; CHECK-DAG: OpName [[TRUNC32_8:%.*]] "i32toi8"
; CHECK-DAG: OpName [[TRUNC16_8:%.*]] "i16toi8" ; CHECK-DAG: OpName [[TRUNC16_8:%.*]] "i16toi8"
; CHECK-DAG: OpName [[SEXT8_32:%.*]] "s8tos32" ; CHECK-DAG: OpName [[SEXT8_32:%.*]] "s8tos32"
; CHECK-DAG: OpName [[SEXT8_16:%.*]] "s8tos16" ; CHECK-DAG: OpName [[SEXT8_16:%.*]] "s8tos16"
; CHECK-DAG: OpName [[SEXT16_32:%.*]] "s16tos32" ; CHECK-DAG: OpName [[SEXT16_32:%.*]] "s16tos32"
; CHECK-DAG: OpName [[ZEXT8_32:%.*]] "u8tou32" ; CHECK-DAG: OpName [[ZEXT8_32:%.*]] "u8tou32"
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llvm/test/CodeGen/SPIRV/instructions/intrinsics.ll

; RUN: llc %s -mtriple=spirv32-unknown-unknown -o - | FileCheck %s ; RUN: llc -O0 %s -mtriple=spirv32-unknown-unknown -o - | FileCheck %s
declare float @llvm.fabs.f32(float) declare float @llvm.fabs.f32(float)
declare float @llvm.rint.f32(float) declare float @llvm.rint.f32(float)
declare float @llvm.nearbyint.f32(float) declare float @llvm.nearbyint.f32(float)
declare float @llvm.floor.f32(float) declare float @llvm.floor.f32(float)
declare float @llvm.ceil.f32(float) declare float @llvm.ceil.f32(float)
declare float @llvm.round.f32(float) declare float @llvm.round.f32(float)
declare float @llvm.trunc.f32(float) declare float @llvm.trunc.f32(float)
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llvm/test/CodeGen/SPIRV/instructions/ptrcmp.ll

; RUN: llc -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
; CHECK-DAG: OpName [[EQ:%.*]] "test_eq" ; CHECK-DAG: OpName [[EQ:%.*]] "test_eq"
; CHECK-DAG: OpName [[NE:%.*]] "test_ne" ; CHECK-DAG: OpName [[NE:%.*]] "test_ne"
; CHECK-DAG: OpName [[ULT:%.*]] "test_ult" ; CHECK-DAG: OpName [[ULT:%.*]] "test_ult"
; CHECK-DAG: OpName [[SLT:%.*]] "test_slt" ; CHECK-DAG: OpName [[SLT:%.*]] "test_slt"
; CHECK-DAG: OpName [[ULE:%.*]] "test_ule" ; CHECK-DAG: OpName [[ULE:%.*]] "test_ule"
; CHECK-DAG: OpName [[SLE:%.*]] "test_sle" ; CHECK-DAG: OpName [[SLE:%.*]] "test_sle"
; CHECK-DAG: OpName [[UGT:%.*]] "test_ugt" ; CHECK-DAG: OpName [[UGT:%.*]] "test_ugt"
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llvm/test/CodeGen/SPIRV/instructions/vector-shuffle.ll

; RUN: llc -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
; CHECK-DAG: OpName [[SHFv4:%.+]] "shuffle_v4" ; CHECK-DAG: OpName [[SHFv4:%.+]] "shuffle_v4"
; CHECK-DAG: OpName [[INSv4:%.+]] "insert_v4" ; CHECK-DAG: OpName [[INSv4:%.+]] "insert_v4"
; CHECK-DAG: OpName [[EXTv4:%.+]] "extract_v4" ; CHECK-DAG: OpName [[EXTv4:%.+]] "extract_v4"
; CHECK-DAG: OpName [[INSv4C:%.+]] "insert_v4C" ; CHECK-DAG: OpName [[INSv4C:%.+]] "insert_v4C"
; CHECK-DAG: OpName [[EXTv4C:%.+]] "extract_v4C" ; CHECK-DAG: OpName [[EXTv4C:%.+]] "extract_v4C"
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