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Differential D140045

[X86] Move RDFLAGS/WRFLAGS expansion until after RA
ClosedPublic

Authored by void on Dec 14 2022, 12:14 PM.

Details

Reviewers
craig.topper
nickdesaulniers
arsenm
efriedma
pengfei
Commits
rG7d626e7cbb3a: [X86] Move RDFLAGS/WRFLAGS expansion until after RA
Summary

The register allocator may introduce reloads in the middle of reading
and writing the EFLAGS register, due to the RDFLAGS & WRFLAGS pseudos
being expanded before RA. This may cause an issue where the stack
pointer was adjusted but the stack offset for the reload wasn't
accounted for (see [1]).

To avoid this, expand these pseudos after register allocation.

[1] https://github.com/llvm/llvm-project/issues/59102

Diff Detail

Event Timeline

void created this revision.Dec 14 2022, 12:14 PM
Herald added a project: Restricted Project. · View Herald TranscriptDec 14 2022, 12:14 PM
Herald added subscribers: StephenFan, pengfei, hiraditya. · View Herald Transcript
void requested review of this revision.Dec 14 2022, 12:14 PM
Herald added a project: Restricted Project. · View Herald TranscriptDec 14 2022, 12:14 PM
Herald added subscribers: llvm-commits, wdng. · View Herald Transcript
arsenm added inline comments.Dec 14 2022, 12:23 PM
llvm/lib/Target/X86/X86InstrInfo.cpp
5074–5075

Are these not reserved?

void added a reviewer: pengfei.Dec 14 2022, 12:24 PM
void added inline comments.
llvm/lib/Target/X86/X86InstrInfo.cpp
5074–5075

Dunno. I'm going off of what the original code was doing...

nickdesaulniers accepted this revision.Dec 14 2022, 1:16 PM
nickdesaulniers added inline comments.
llvm/test/CodeGen/X86/eflags.ll
4–22 ↗(On Diff #482958)

These are already covered by llvm/test/CodeGen/X86/x86-64-flags-intrinsics.ll. Do they add anything here?

This revision is now accepted and ready to land.Dec 14 2022, 1:16 PM
efriedma added a comment.Dec 14 2022, 1:53 PM

You should be able to teach frame lowering to compute the correct offsets by fixing X86InstrInfo::getSPAdjust(). Maybe that's better than trying to avoid the use of frame indexes between the push and pop?

Harbormaster completed remote builds in B203192: Diff 482958.Dec 14 2022, 2:25 PM
pengfei added inline comments.Dec 14 2022, 9:41 PM
llvm/lib/Target/X86/X86InstrInfo.td
1384

Seems not needed.

1397

ditto.

craig.topper added inline comments.Dec 14 2022, 9:42 PM
llvm/lib/Target/X86/X86InstrInfo.td
1384

I think it's need to make expandPostRAPseudo get called.

pengfei added inline comments.Dec 14 2022, 9:49 PM
llvm/lib/Target/X86/X86InstrInfo.td
1384

It just checks isPseudo https://github.com/llvm/llvm-project/blob/main/llvm/lib/CodeGen/ExpandPostRAPseudos.cpp#L199-L203

pengfei added inline comments.Dec 14 2022, 9:51 PM
llvm/lib/Target/X86/X86InstrInfo.td
1384

I mean usesCustomInserter = 1 is not needed since the code is removed from EmitInstrWithCustomInserter.

craig.topper added inline comments.Dec 14 2022, 9:52 PM
llvm/lib/Target/X86/X86InstrInfo.td
1384

Agreed. usesCustomInserter can be removed

pengfei added inline comments.Dec 14 2022, 9:53 PM
llvm/lib/Target/X86/X86InstrInfo.cpp
5074–5075

I think this might be a problem for PostRA.

pengfei added inline comments.Dec 14 2022, 10:04 PM
llvm/lib/Target/X86/X86InstrInfo.cpp
5074–5075

Sorry, I misunderstood the question. Please ignore.

void added a comment.EditedDec 15 2022, 10:13 AM
In D140045#3996240, @efriedma wrote:

You should be able to teach frame lowering to compute the correct offsets by fixing X86InstrInfo::getSPAdjust(). Maybe that's better than trying to avoid the use of frame indexes between the push and pop?

That's the correct general fix for this issue. Though I still maintain that this is a good addition. Having reloads occurring in the middle of these two instructions isn't really beneficial.

To be clear, I'll submit a subsequent patch that corrects the offsets. :-)

llvm/lib/Target/X86/X86InstrInfo.td
1384

Ah! Okay.

void updated this revision to Diff 483260.Dec 15 2022, 11:27 AM

Update TD file and testcase. Also correct the MIBs to have the correct parameters.

Harbormaster completed remote builds in B203410: Diff 483260.Dec 15 2022, 2:33 PM
craig.topper accepted this revision.Jan 25 2023, 10:19 AM

LGTM

pengfei accepted this revision.Jan 26 2023, 2:42 AM

LGTM.

void updated this revision to Diff 493427.Jan 30 2023, 2:38 PM

Rebase.

Harbormaster completed remote builds in B210865: Diff 493427.Jan 30 2023, 3:13 PM
This revision was landed with ongoing or failed builds.Jan 30 2023, 3:32 PM
Closed by commit rG7d626e7cbb3a: [X86] Move RDFLAGS/WRFLAGS expansion until after RA (authored by void). · Explain Why
This revision was automatically updated to reflect the committed changes.
void added a commit: rG7d626e7cbb3a: [X86] Move RDFLAGS/WRFLAGS expansion until after RA.

Revision Contents

PathSize
llvm/
lib/
Target/
X86/
35 lines
39 lines
4 lines
test/
CodeGen/
X86/
164 lines

Diff 493438

llvm/lib/Target/X86/X86ISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 37,300 Lines • ▼ Show 20 LinesX86TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
case X86::CMOV_VK2: case X86::CMOV_VK2:
case X86::CMOV_VK4: case X86::CMOV_VK4:
case X86::CMOV_VK8: case X86::CMOV_VK8:
case X86::CMOV_VK16: case X86::CMOV_VK16:
case X86::CMOV_VK32: case X86::CMOV_VK32:
case X86::CMOV_VK64: case X86::CMOV_VK64:
return EmitLoweredSelect(MI, BB); return EmitLoweredSelect(MI, BB);
case X86::RDFLAGS32:
case X86::RDFLAGS64: {
unsigned PushF =
MI.getOpcode() == X86::RDFLAGS32 ? X86::PUSHF32 : X86::PUSHF64;
unsigned Pop = MI.getOpcode() == X86::RDFLAGS32 ? X86::POP32r : X86::POP64r;
MachineInstr *Push = BuildMI(*BB, MI, DL, TII->get(PushF));
// Permit reads of the EFLAGS and DF registers without them being defined.
// This intrinsic exists to read external processor state in flags, such as
// the trap flag, interrupt flag, and direction flag, none of which are
// modeled by the backend.
assert(Push->getOperand(2).getReg() == X86::EFLAGS &&
"Unexpected register in operand!");
Push->getOperand(2).setIsUndef();
assert(Push->getOperand(3).getReg() == X86::DF &&
"Unexpected register in operand!");
Push->getOperand(3).setIsUndef();
BuildMI(*BB, MI, DL, TII->get(Pop), MI.getOperand(0).getReg());
MI.eraseFromParent(); // The pseudo is gone now.
return BB;
}
case X86::WRFLAGS32:
case X86::WRFLAGS64: {
unsigned Push =
MI.getOpcode() == X86::WRFLAGS32 ? X86::PUSH32r : X86::PUSH64r;
unsigned PopF =
MI.getOpcode() == X86::WRFLAGS32 ? X86::POPF32 : X86::POPF64;
BuildMI(*BB, MI, DL, TII->get(Push)).addReg(MI.getOperand(0).getReg());
BuildMI(*BB, MI, DL, TII->get(PopF));
MI.eraseFromParent(); // The pseudo is gone now.
return BB;
}
case X86::FP32_TO_INT16_IN_MEM: case X86::FP32_TO_INT16_IN_MEM:
case X86::FP32_TO_INT32_IN_MEM: case X86::FP32_TO_INT32_IN_MEM:
case X86::FP32_TO_INT64_IN_MEM: case X86::FP32_TO_INT64_IN_MEM:
case X86::FP64_TO_INT16_IN_MEM: case X86::FP64_TO_INT16_IN_MEM:
case X86::FP64_TO_INT32_IN_MEM: case X86::FP64_TO_INT32_IN_MEM:
case X86::FP64_TO_INT64_IN_MEM: case X86::FP64_TO_INT64_IN_MEM:
case X86::FP80_TO_INT16_IN_MEM: case X86::FP80_TO_INT16_IN_MEM:
case X86::FP80_TO_INT32_IN_MEM: case X86::FP80_TO_INT32_IN_MEM:
▲ Show 20 Lines • Show All 20,458 Lines • Show Last 20 Lines

llvm/lib/Target/X86/X86InstrInfo.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 5,054 Lines • ▼ Show 20 Lines case X86::MOV32ri64: {
Register Reg = MIB.getReg(0); Register Reg = MIB.getReg(0);
Register Reg32 = RI.getSubReg(Reg, X86::sub_32bit); Register Reg32 = RI.getSubReg(Reg, X86::sub_32bit);
MI.setDesc(get(X86::MOV32ri)); MI.setDesc(get(X86::MOV32ri));
MIB->getOperand(0).setReg(Reg32); MIB->getOperand(0).setReg(Reg32);
MIB.addReg(Reg, RegState::ImplicitDefine); MIB.addReg(Reg, RegState::ImplicitDefine);
return true; return true;
} }
case X86::RDFLAGS32:
case X86::RDFLAGS64: {
unsigned Is64Bit = MI.getOpcode() == X86::RDFLAGS64;
MachineBasicBlock &MBB = *MIB->getParent();
MachineInstr *NewMI =
BuildMI(MBB, MI, MIB->getDebugLoc(),
get(Is64Bit ? X86::PUSHF64 : X86::PUSHF32))
.getInstr();
// Permit reads of the EFLAGS and DF registers without them being defined.
// This intrinsic exists to read external processor state in flags, such as
// the trap flag, interrupt flag, and direction flag, none of which are
arsenmUnsubmitted
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Are these not reserved?

arsenm: Are these not reserved?
voidAuthorUnsubmitted
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Dunno. I'm going off of what the original code was doing...

void: Dunno. I'm going off of what the original code was doing...
pengfeiUnsubmitted
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I think this might be a problem for PostRA.

pengfei: I think this might be a problem for PostRA.
pengfeiUnsubmitted
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Sorry, I misunderstood the question. Please ignore.

pengfei: Sorry, I misunderstood the question. Please ignore.
// modeled by the backend.
assert(NewMI->getOperand(2).getReg() == X86::EFLAGS &&
"Unexpected register in operand! Should be EFLAGS.");
NewMI->getOperand(2).setIsUndef();
assert(NewMI->getOperand(3).getReg() == X86::DF &&
"Unexpected register in operand! Should be DF.");
NewMI->getOperand(3).setIsUndef();
MIB->setDesc(get(Is64Bit ? X86::POP64r : X86::POP32r));
return true;
}
case X86::WRFLAGS32:
case X86::WRFLAGS64: {
unsigned Is64Bit = MI.getOpcode() == X86::WRFLAGS64;
MachineBasicBlock &MBB = *MIB->getParent();
BuildMI(MBB, MI, MIB->getDebugLoc(),
get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
.addReg(MI.getOperand(0).getReg());
BuildMI(MBB, MI, MIB->getDebugLoc(),
get(Is64Bit ? X86::POPF64 : X86::POPF32));
MI.eraseFromParent();
return true;
}
// KNL does not recognize dependency-breaking idioms for mask registers, // KNL does not recognize dependency-breaking idioms for mask registers,
// so kxnor %k1, %k1, %k2 has a RAW dependence on %k1. // so kxnor %k1, %k1, %k2 has a RAW dependence on %k1.
// Using %k0 as the undef input register is a performance heuristic based // Using %k0 as the undef input register is a performance heuristic based
// on the assumption that %k0 is used less frequently than the other mask // on the assumption that %k0 is used less frequently than the other mask
// registers, since it is not usable as a write mask. // registers, since it is not usable as a write mask.
// FIXME: A more advanced approach would be to choose the best input mask // FIXME: A more advanced approach would be to choose the best input mask
// register based on context. // register based on context.
case X86::KSET0W: return Expand2AddrKreg(MIB, get(X86::KXORWrr), X86::K0); case X86::KSET0W: return Expand2AddrKreg(MIB, get(X86::KXORWrr), X86::K0);
▲ Show 20 Lines • Show All 4,666 Lines • Show Last 20 Lines

llvm/lib/Target/X86/X86InstrInfo.td

Show First 20 Lines • Show All 1,375 Lines • ▼ Show 20 Lines
def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src", []>, def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src", []>,
OpSize16; OpSize16;
def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src", []>, def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src", []>,
OpSize32, Requires<[Not64BitMode]>; OpSize32, Requires<[Not64BitMode]>;
} // mayLoad, mayStore, SchedRW } // mayLoad, mayStore, SchedRW
} }
let mayLoad = 1, mayStore = 1, usesCustomInserter = 1, let isPseudo = 1, mayLoad = 1, mayStore = 1,
pengfeiUnsubmitted
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Seems not needed.

pengfei: Seems not needed.
craig.topperUnsubmitted
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I think it's need to make expandPostRAPseudo get called.

craig.topper: I think it's need to make expandPostRAPseudo get called.
pengfeiUnsubmitted
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It just checks isPseudo https://github.com/llvm/llvm-project/blob/main/llvm/lib/CodeGen/ExpandPostRAPseudos.cpp#L199-L203

pengfei: It just checks `isPseudo` https://github.com/llvm/llvm…
pengfeiUnsubmitted
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I mean usesCustomInserter = 1 is not needed since the code is removed from EmitInstrWithCustomInserter.

pengfei: I mean `usesCustomInserter = 1` is not needed since the code is removed from…
craig.topperUnsubmitted
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Agreed. usesCustomInserter can be removed

craig.topper: Agreed. usesCustomInserter can be removed
voidAuthorUnsubmitted
Done
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Ah! Okay.

void: Ah! Okay.
SchedRW = [WriteRMW], Defs = [ESP] in { SchedRW = [WriteRMW], Defs = [ESP] in {
let Uses = [ESP] in let Uses = [ESP] in
def RDFLAGS32 : PseudoI<(outs GR32:$dst), (ins), def RDFLAGS32 : PseudoI<(outs GR32:$dst), (ins),
[(set GR32:$dst, (int_x86_flags_read_u32))]>, [(set GR32:$dst, (int_x86_flags_read_u32))]>,
Requires<[Not64BitMode]>; Requires<[Not64BitMode]>;
let Uses = [RSP] in let Uses = [RSP] in
def RDFLAGS64 : PseudoI<(outs GR64:$dst), (ins), def RDFLAGS64 : PseudoI<(outs GR64:$dst), (ins),
[(set GR64:$dst, (int_x86_flags_read_u64))]>, [(set GR64:$dst, (int_x86_flags_read_u64))]>,
Requires<[In64BitMode]>; Requires<[In64BitMode]>;
} }
let mayLoad = 1, mayStore = 1, usesCustomInserter = 1, let isPseudo = 1, mayLoad = 1, mayStore = 1,
pengfeiUnsubmitted
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ditto.

pengfei: ditto.
SchedRW = [WriteRMW] in { SchedRW = [WriteRMW] in {
let Defs = [ESP, EFLAGS, DF], Uses = [ESP] in let Defs = [ESP, EFLAGS, DF], Uses = [ESP] in
def WRFLAGS32 : PseudoI<(outs), (ins GR32:$src), def WRFLAGS32 : PseudoI<(outs), (ins GR32:$src),
[(int_x86_flags_write_u32 GR32:$src)]>, [(int_x86_flags_write_u32 GR32:$src)]>,
Requires<[Not64BitMode]>; Requires<[Not64BitMode]>;
let Defs = [RSP, EFLAGS, DF], Uses = [RSP] in let Defs = [RSP, EFLAGS, DF], Uses = [RSP] in
def WRFLAGS64 : PseudoI<(outs), (ins GR64:$src), def WRFLAGS64 : PseudoI<(outs), (ins GR64:$src),
▲ Show 20 Lines • Show All 2,417 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/x86-64-flags-intrinsics.ll

Show First 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
; WIN64-NEXT: popfq ; WIN64-NEXT: popfq
; WIN64-NEXT: popq %rbp ; WIN64-NEXT: popq %rbp
; WIN64-NEXT: retq ; WIN64-NEXT: retq
; WIN64-NEXT: .seh_endproc ; WIN64-NEXT: .seh_endproc
entry: entry:
call void @llvm.x86.flags.write.u64(i64 %arg) call void @llvm.x86.flags.write.u64(i64 %arg)
ret void ret void
} }
define i64 @read_flags_reg_pressure() nounwind {
; CHECK-LABEL: read_flags_reg_pressure:
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rbp
; CHECK-NEXT: pushq %r15
; CHECK-NEXT: pushq %r14
; CHECK-NEXT: pushq %r13
; CHECK-NEXT: pushq %r12
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: subq $16, %rsp
; CHECK-NEXT: #APP
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: movq %rdx, (%rsp) # 8-byte Spill
; CHECK-NEXT: pushfq
; CHECK-NEXT: popq %rdx
; CHECK-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; CHECK-NEXT: movq (%rsp), %rdx # 8-byte Reload
; CHECK-NEXT: #APP
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
; CHECK-NEXT: addq $16, %rsp
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: popq %r12
; CHECK-NEXT: popq %r13
; CHECK-NEXT: popq %r14
; CHECK-NEXT: popq %r15
; CHECK-NEXT: popq %rbp
; CHECK-NEXT: retq
;
; WIN64-LABEL: read_flags_reg_pressure:
; WIN64: # %bb.0:
; WIN64-NEXT: pushq %rbp
; WIN64-NEXT: pushq %r15
; WIN64-NEXT: pushq %r14
; WIN64-NEXT: pushq %r13
; WIN64-NEXT: pushq %r12
; WIN64-NEXT: pushq %rsi
; WIN64-NEXT: pushq %rdi
; WIN64-NEXT: pushq %rbx
; WIN64-NEXT: subq $16, %rsp
; WIN64-NEXT: leaq {{[0-9]+}}(%rsp), %rbp
; WIN64-NEXT: #APP
; WIN64-NEXT: #NO_APP
; WIN64-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; WIN64-NEXT: pushfq
; WIN64-NEXT: popq %rdx
; WIN64-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; WIN64-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rdx # 8-byte Reload
; WIN64-NEXT: #APP
; WIN64-NEXT: #NO_APP
; WIN64-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
; WIN64-NEXT: addq $16, %rsp
; WIN64-NEXT: popq %rbx
; WIN64-NEXT: popq %rdi
; WIN64-NEXT: popq %rsi
; WIN64-NEXT: popq %r12
; WIN64-NEXT: popq %r13
; WIN64-NEXT: popq %r14
; WIN64-NEXT: popq %r15
; WIN64-NEXT: popq %rbp
; WIN64-NEXT: retq
%1 = tail call { i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64 } asm sideeffect "", "={ax},={bx},={cx},={dx},={si},={di},={bp},={r8},={r9},={r10},={r11},={r12},={r13},={r14},={r15},~{dirflag},~{fpsr},~{flags}"()
%2 = extractvalue { i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64 } %1, 0
%3 = extractvalue { i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64 } %1, 1
%4 = extractvalue { i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64 } %1, 2
%5 = extractvalue { i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64 } %1, 3
%6 = extractvalue { i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64 } %1, 4
%7 = extractvalue { i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64 } %1, 5
%8 = extractvalue { i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64 } %1, 6
%9 = extractvalue { i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64 } %1, 7
%10 = extractvalue { i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64 } %1, 8
%11 = extractvalue { i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64 } %1, 9
%12 = extractvalue { i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64 } %1, 10
%13 = extractvalue { i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64 } %1, 11
%14 = extractvalue { i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64 } %1, 12
%15 = extractvalue { i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64 } %1, 13
%16 = extractvalue { i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64 } %1, 14
%17 = tail call i64 @llvm.x86.flags.read.u64()
tail call void asm sideeffect "", "{ax},{bx},{cx},{dx},{si},{di},{bp},{r8},{r9},{r10},{r11},{r12},{r13},{r14},{r15},~{dirflag},~{fpsr},~{flags}"(i64 %2, i64 %3, i64 %4, i64 %5, i64 %6, i64 %7, i64 %8, i64 %9, i64 %10, i64 %11, i64 %12, i64 %13, i64 %14, i64 %15, i64 %16)
ret i64 %17
}
define void @write_flags_reg_pressure(i64 noundef %0) nounwind {
; CHECK-LABEL: write_flags_reg_pressure:
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rbp
; CHECK-NEXT: pushq %r15
; CHECK-NEXT: pushq %r14
; CHECK-NEXT: pushq %r13
; CHECK-NEXT: pushq %r12
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: subq $16, %rsp
; CHECK-NEXT: movq %rdi, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; CHECK-NEXT: #APP
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: movq %rdx, (%rsp) # 8-byte Spill
; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rdx # 8-byte Reload
; CHECK-NEXT: pushq %rdx
; CHECK-NEXT: popfq
; CHECK-NEXT: movq (%rsp), %rdx # 8-byte Reload
; CHECK-NEXT: #APP
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: addq $16, %rsp
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: popq %r12
; CHECK-NEXT: popq %r13
; CHECK-NEXT: popq %r14
; CHECK-NEXT: popq %r15
; CHECK-NEXT: popq %rbp
; CHECK-NEXT: retq
;
; WIN64-LABEL: write_flags_reg_pressure:
; WIN64: # %bb.0:
; WIN64-NEXT: pushq %rbp
; WIN64-NEXT: pushq %r15
; WIN64-NEXT: pushq %r14
; WIN64-NEXT: pushq %r13
; WIN64-NEXT: pushq %r12
; WIN64-NEXT: pushq %rsi
; WIN64-NEXT: pushq %rdi
; WIN64-NEXT: pushq %rbx
; WIN64-NEXT: subq $16, %rsp
; WIN64-NEXT: leaq {{[0-9]+}}(%rsp), %rbp
; WIN64-NEXT: movq %rcx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; WIN64-NEXT: #APP
; WIN64-NEXT: #NO_APP
; WIN64-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; WIN64-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rdx # 8-byte Reload
; WIN64-NEXT: pushq %rdx
; WIN64-NEXT: popfq
; WIN64-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rdx # 8-byte Reload
; WIN64-NEXT: #APP
; WIN64-NEXT: #NO_APP
; WIN64-NEXT: addq $16, %rsp
; WIN64-NEXT: popq %rbx
; WIN64-NEXT: popq %rdi
; WIN64-NEXT: popq %rsi
; WIN64-NEXT: popq %r12
; WIN64-NEXT: popq %r13
; WIN64-NEXT: popq %r14
; WIN64-NEXT: popq %r15
; WIN64-NEXT: popq %rbp
; WIN64-NEXT: retq
%2 = tail call { i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64 } asm sideeffect "", "={ax},={bx},={cx},={dx},={si},={di},={bp},={r8},={r9},={r10},={r11},={r12},={r13},={r14},={r15},~{dirflag},~{fpsr},~{flags}"()
%3 = extractvalue { i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64 } %2, 0
%4 = extractvalue { i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64 } %2, 1
%5 = extractvalue { i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64 } %2, 2
%6 = extractvalue { i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64 } %2, 3
%7 = extractvalue { i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64 } %2, 4
%8 = extractvalue { i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64 } %2, 5
%9 = extractvalue { i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64 } %2, 6
%10 = extractvalue { i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64 } %2, 7
%11 = extractvalue { i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64 } %2, 8
%12 = extractvalue { i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64 } %2, 9
%13 = extractvalue { i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64 } %2, 10
%14 = extractvalue { i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64 } %2, 11
%15 = extractvalue { i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64 } %2, 12
%16 = extractvalue { i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64 } %2, 13
%17 = extractvalue { i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64 } %2, 14
tail call void @llvm.x86.flags.write.u64(i64 %0)
tail call void asm sideeffect "", "{ax},{bx},{cx},{dx},{si},{di},{bp},{r8},{r9},{r10},{r11},{r12},{r13},{r14},{r15},~{dirflag},~{fpsr},~{flags}"(i64 %3, i64 %4, i64 %5, i64 %6, i64 %7, i64 %8, i64 %9, i64 %10, i64 %11, i64 %12, i64 %13, i64 %14, i64 %15, i64 %16, i64 %17)
ret void
}