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Differential D139991

[X86] combine-and.ll - add 256 and 512 bit test coverage for scalar broadcast
ClosedPublic

Authored by e-kud on Dec 13 2022, 6:55 PM.

Details

Reviewers
pengfei
RKSimon
Commits
rG80ec3f027dab: [X86] combine-and.ll - add 256 and 512 bit test coverage for scalar broadcast

Diff Detail

Event Timeline

e-kud created this revision.Dec 13 2022, 6:55 PM
Herald added a project: Restricted Project. · View Herald TranscriptDec 13 2022, 6:55 PM
Herald added a subscriber: pengfei. · View Herald Transcript
e-kud added a child revision: D138521: [X86] Support ANDNP combine through vector_shuffle.Dec 13 2022, 7:35 PM
Harbormaster completed remote builds in B202995: Diff 482687.Dec 13 2022, 8:03 PM
e-kud updated this revision to Diff 483061.Dec 14 2022, 6:40 PM

Added a test with bitcasted not.

e-kud published this revision for review.Dec 14 2022, 7:14 PM
e-kud added reviewers: pengfei, RKSimon.
Herald added a project: Restricted Project. · View Herald TranscriptDec 14 2022, 7:14 PM
Herald added a subscriber: llvm-commits. · View Herald Transcript
Harbormaster completed remote builds in B203263: Diff 483061.Dec 14 2022, 7:56 PM
RKSimon added a comment.Dec 15 2022, 12:53 AM

I added some 256/512 cases already - what coverage do these tests add?

RKSimon accepted this revision.Dec 15 2022, 1:07 AM

Ah! Its for the missing bitcast I mentioned on D138521 - LGTM cheers

This revision is now accepted and ready to land.Dec 15 2022, 1:07 AM
This revision was landed with ongoing or failed builds.Dec 21 2022, 4:31 AM
Closed by commit rG80ec3f027dab: [X86] combine-and.ll - add 256 and 512 bit test coverage for scalar broadcast (authored by e-kud, committed by pengfei). · Explain Why
This revision was automatically updated to reflect the committed changes.
pengfei added a commit: rG80ec3f027dab: [X86] combine-and.ll - add 256 and 512 bit test coverage for scalar broadcast.

Revision Contents

PathSize
llvm/
test/
CodeGen/
X86/
318 lines

Diff 483061

llvm/test/CodeGen/X86/combine-and.ll

Show First 20 Lines • Show All 480 Lines • ▼ Show 20 Lines; AVX-NEXT: retq
%3 = add <16 x i8> %2, %a1 %3 = add <16 x i8> %2, %a1
ret <16 x i8> %3 ret <16 x i8> %3
} }
; ;
; Simplify and with a broadcasted negated scalar ; Simplify and with a broadcasted negated scalar
; ;
define <8 x i64> @neg_scalar_broadcast_v8i64_arg(i64 %a0, <8 x i64> %a1) {
; SSE-LABEL: neg_scalar_broadcast_v8i64_arg:
; SSE: # %bb.0:
; SSE-NEXT: notq %rdi
; SSE-NEXT: movq %rdi, %xmm4
; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm4[0,1,0,1]
; SSE-NEXT: pand %xmm4, %xmm0
; SSE-NEXT: pand %xmm4, %xmm1
; SSE-NEXT: pand %xmm4, %xmm2
; SSE-NEXT: pand %xmm4, %xmm3
; SSE-NEXT: retq
;
; AVX1-LABEL: neg_scalar_broadcast_v8i64_arg:
; AVX1: # %bb.0:
; AVX1-NEXT: notq %rdi
; AVX1-NEXT: vmovq %rdi, %xmm2
; AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[0,1,0,1]
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm2, %ymm2
; AVX1-NEXT: vandps %ymm0, %ymm2, %ymm0
; AVX1-NEXT: vandps %ymm1, %ymm2, %ymm1
; AVX1-NEXT: retq
;
; AVX2-LABEL: neg_scalar_broadcast_v8i64_arg:
; AVX2: # %bb.0:
; AVX2-NEXT: notq %rdi
; AVX2-NEXT: vmovq %rdi, %xmm2
; AVX2-NEXT: vpbroadcastq %xmm2, %ymm2
; AVX2-NEXT: vpand %ymm0, %ymm2, %ymm0
; AVX2-NEXT: vpand %ymm1, %ymm2, %ymm1
; AVX2-NEXT: retq
;
; AVX512-LABEL: neg_scalar_broadcast_v8i64_arg:
; AVX512: # %bb.0:
; AVX512-NEXT: notq %rdi
; AVX512-NEXT: vpbroadcastq %rdi, %zmm1
; AVX512-NEXT: vpandq %zmm0, %zmm1, %zmm0
; AVX512-NEXT: retq
%1 = xor i64 %a0, -1
%2 = insertelement <8 x i64> undef, i64 %1, i64 0
%3 = shufflevector <8 x i64> %2, <8 x i64> poison, <8 x i32> zeroinitializer
%4 = and <8 x i64> %3, %a1
ret <8 x i64> %4
}
define <8 x i64> @neg_scalar_broadcast_v8i64(i64 %a0, <2 x i64> %a1) {
; SSE-LABEL: neg_scalar_broadcast_v8i64:
; SSE: # %bb.0:
; SSE-NEXT: movdqa %xmm0, %xmm2
; SSE-NEXT: notq %rdi
; SSE-NEXT: movq %rdi, %xmm0
; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm0[0,1,0,1]
; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm2[0,1,0,1]
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm2[2,3,2,3]
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm2[2,3,0,1]
; SSE-NEXT: pand %xmm4, %xmm0
; SSE-NEXT: pand %xmm4, %xmm1
; SSE-NEXT: pand %xmm4, %xmm2
; SSE-NEXT: pand %xmm4, %xmm3
; SSE-NEXT: retq
;
; AVX1-LABEL: neg_scalar_broadcast_v8i64:
; AVX1: # %bb.0:
; AVX1-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
; AVX1-NEXT: notq %rdi
; AVX1-NEXT: vmovq %rdi, %xmm1
; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,1,0,1]
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm1, %ymm1
; AVX1-NEXT: vpermilps {{.*#+}} xmm2 = xmm0[0,1,0,1]
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm2
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
; AVX1-NEXT: vpermilpd {{.*#+}} ymm0 = ymm0[1,0,3,3]
; AVX1-NEXT: vandpd %ymm1, %ymm0, %ymm0
; AVX1-NEXT: vandpd %ymm1, %ymm2, %ymm1
; AVX1-NEXT: retq
;
; AVX2-LABEL: neg_scalar_broadcast_v8i64:
; AVX2: # %bb.0:
; AVX2-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
; AVX2-NEXT: notq %rdi
; AVX2-NEXT: vmovq %rdi, %xmm1
; AVX2-NEXT: vpbroadcastq %xmm1, %ymm1
; AVX2-NEXT: vpermq {{.*#+}} ymm2 = ymm0[0,1,0,0]
; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[1,0,1,1]
; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX2-NEXT: vpand %ymm1, %ymm2, %ymm1
; AVX2-NEXT: retq
;
; AVX512-LABEL: neg_scalar_broadcast_v8i64:
; AVX512: # %bb.0:
; AVX512-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; AVX512-NEXT: notq %rdi
; AVX512-NEXT: vpbroadcastq %rdi, %zmm1
; AVX512-NEXT: vmovdqa64 {{.*#+}} zmm2 = [1,0,1,1,0,1,0,0]
; AVX512-NEXT: vpermq %zmm0, %zmm2, %zmm0
; AVX512-NEXT: vpandq %zmm1, %zmm0, %zmm0
; AVX512-NEXT: retq
%1 = xor i64 %a0, -1
%2 = insertelement <8 x i64> undef, i64 %1, i64 0
%3 = shufflevector <8 x i64> %2, <8 x i64> poison, <8 x i32> zeroinitializer
%4 = shufflevector <2 x i64> %a1, <2 x i64> poison, <8 x i32> <i32 1, i32 0, i32 1, i32 1, i32 0, i32 1, i32 0, i32 0>
%5 = and <8 x i64> %4, %3
ret <8 x i64> %5
}
define <4 x i64> @neg_scalar_broadcast_v4i64_arg(i64 %a0, <4 x i64> %a1) {
; SSE-LABEL: neg_scalar_broadcast_v4i64_arg:
; SSE: # %bb.0:
; SSE-NEXT: notq %rdi
; SSE-NEXT: movq %rdi, %xmm2
; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,1,0,1]
; SSE-NEXT: pand %xmm2, %xmm0
; SSE-NEXT: pand %xmm2, %xmm1
; SSE-NEXT: retq
;
; AVX1-LABEL: neg_scalar_broadcast_v4i64_arg:
; AVX1: # %bb.0:
; AVX1-NEXT: notq %rdi
; AVX1-NEXT: vmovq %rdi, %xmm1
; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,1,0,1]
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm1, %ymm1
; AVX1-NEXT: vandps %ymm0, %ymm1, %ymm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: neg_scalar_broadcast_v4i64_arg:
; AVX2: # %bb.0:
; AVX2-NEXT: notq %rdi
; AVX2-NEXT: vmovq %rdi, %xmm1
; AVX2-NEXT: vpbroadcastq %xmm1, %ymm1
; AVX2-NEXT: vpand %ymm0, %ymm1, %ymm0
; AVX2-NEXT: retq
;
; AVX512-LABEL: neg_scalar_broadcast_v4i64_arg:
; AVX512: # %bb.0:
; AVX512-NEXT: notq %rdi
; AVX512-NEXT: vpbroadcastq %rdi, %ymm1
; AVX512-NEXT: vpand %ymm0, %ymm1, %ymm0
; AVX512-NEXT: retq
%1 = xor i64 %a0, -1
%2 = insertelement <4 x i64> undef, i64 %1, i64 0
%3 = shufflevector <4 x i64> %2, <4 x i64> poison, <4 x i32> zeroinitializer
%4 = and <4 x i64> %3, %a1
ret <4 x i64> %4
}
define <4 x i64> @neg_scalar_broadcast_v4i64(i64 %a0, <2 x i64> %a1) {
; SSE-LABEL: neg_scalar_broadcast_v4i64:
; SSE: # %bb.0:
; SSE-NEXT: notq %rdi
; SSE-NEXT: movq %rdi, %xmm1
; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm1[0,1,0,1]
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
; SSE-NEXT: pand %xmm2, %xmm0
; SSE-NEXT: pand %xmm2, %xmm1
; SSE-NEXT: retq
;
; AVX1-LABEL: neg_scalar_broadcast_v4i64:
; AVX1: # %bb.0:
; AVX1-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
; AVX1-NEXT: notq %rdi
; AVX1-NEXT: vmovq %rdi, %xmm1
; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,1,0,1]
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm1, %ymm1
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
; AVX1-NEXT: vpermilpd {{.*#+}} ymm0 = ymm0[1,0,3,3]
; AVX1-NEXT: vandpd %ymm1, %ymm0, %ymm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: neg_scalar_broadcast_v4i64:
; AVX2: # %bb.0:
; AVX2-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
; AVX2-NEXT: notq %rdi
; AVX2-NEXT: vmovq %rdi, %xmm1
; AVX2-NEXT: vpbroadcastq %xmm1, %ymm1
; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[1,0,1,1]
; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX2-NEXT: retq
;
; AVX512-LABEL: neg_scalar_broadcast_v4i64:
; AVX512: # %bb.0:
; AVX512-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
; AVX512-NEXT: notq %rdi
; AVX512-NEXT: vpbroadcastq %rdi, %ymm1
; AVX512-NEXT: vpermq {{.*#+}} ymm0 = ymm0[1,0,1,1]
; AVX512-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX512-NEXT: retq
%1 = xor i64 %a0, -1
%2 = insertelement <4 x i64> undef, i64 %1, i64 0
%3 = shufflevector <4 x i64> %2, <4 x i64> poison, <4 x i32> zeroinitializer
%4 = shufflevector <2 x i64> %a1, <2 x i64> poison, <4 x i32> <i32 1, i32 0, i32 1, i32 1>
%5 = and <4 x i64> %4, %3
ret <4 x i64> %5
}
define <2 x i64> @neg_scalar_broadcast_v2i64(i64 %a0, <2 x i64> %a1) { define <2 x i64> @neg_scalar_broadcast_v2i64(i64 %a0, <2 x i64> %a1) {
; SSE-LABEL: neg_scalar_broadcast_v2i64: ; SSE-LABEL: neg_scalar_broadcast_v2i64:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: notq %rdi ; SSE-NEXT: notq %rdi
; SSE-NEXT: movq %rdi, %xmm1 ; SSE-NEXT: movq %rdi, %xmm1
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,1,0,1] ; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,1,0,1]
; SSE-NEXT: pand %xmm1, %xmm0 ; SSE-NEXT: pand %xmm1, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
Show All 22 Lines
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%1 = xor i64 %a0, -1 %1 = xor i64 %a0, -1
%2 = insertelement <2 x i64> undef, i64 %1, i64 0 %2 = insertelement <2 x i64> undef, i64 %1, i64 0
%3 = shufflevector <2 x i64> %2, <2 x i64> poison, <2 x i32> zeroinitializer %3 = shufflevector <2 x i64> %2, <2 x i64> poison, <2 x i32> zeroinitializer
%4 = and <2 x i64> %3, %a1 %4 = and <2 x i64> %3, %a1
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @casted_neg_scalar_broadcast_v2i64(<2 x i32> %a0, <2 x i64> %a1) {
; SSE-LABEL: casted_neg_scalar_broadcast_v2i64:
; SSE: # %bb.0:
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
; SSE-NEXT: pandn %xmm1, %xmm0
; SSE-NEXT: retq
;
; AVX1-LABEL: casted_neg_scalar_broadcast_v2i64:
; AVX1: # %bb.0:
; AVX1-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,1,0,1]
; AVX1-NEXT: vandnps %xmm1, %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: casted_neg_scalar_broadcast_v2i64:
; AVX2: # %bb.0:
; AVX2-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
; AVX2-NEXT: vandnps %xmm1, %xmm0, %xmm0
; AVX2-NEXT: retq
;
; AVX512-LABEL: casted_neg_scalar_broadcast_v2i64:
; AVX512: # %bb.0:
; AVX512-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
; AVX512-NEXT: vandnps %xmm1, %xmm0, %xmm0
; AVX512-NEXT: retq
%1 = xor <2 x i32> %a0, <i32 -1, i32 -1>
%2 = bitcast <2 x i32> %1 to i64
%3 = insertelement <2 x i64> undef, i64 %2, i64 0
%4 = shufflevector <2 x i64> %3, <2 x i64> poison, <2 x i32> zeroinitializer
%5 = and <2 x i64> %4, %a1
ret <2 x i64> %5
}
define <8 x i32> @neg_scalar_broadcast_v8i32(i32 %a0, <8 x i32> %a1) { define <8 x i32> @neg_scalar_broadcast_v8i32(i32 %a0, <8 x i32> %a1) {
; SSE-LABEL: neg_scalar_broadcast_v8i32: ; SSE-LABEL: neg_scalar_broadcast_v8i32:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: notl %edi ; SSE-NEXT: notl %edi
; SSE-NEXT: movd %edi, %xmm2 ; SSE-NEXT: movd %edi, %xmm2
; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,0,0,0] ; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,0,0,0]
; SSE-NEXT: pand %xmm2, %xmm0 ; SSE-NEXT: pand %xmm2, %xmm0
; SSE-NEXT: pand %xmm2, %xmm1 ; SSE-NEXT: pand %xmm2, %xmm1
▲ Show 20 Lines • Show All 152 Lines • ▼ Show 20 Lines
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%1 = xor i8 %a0, -1 %1 = xor i8 %a0, -1
%2 = insertelement <64 x i8> undef, i8 %1, i64 0 %2 = insertelement <64 x i8> undef, i8 %1, i64 0
%3 = shufflevector <64 x i8> %2, <64 x i8> poison, <64 x i32> zeroinitializer %3 = shufflevector <64 x i8> %2, <64 x i8> poison, <64 x i32> zeroinitializer
%4 = and <64 x i8> %3, %a1 %4 = and <64 x i8> %3, %a1
ret <64 x i8> %4 ret <64 x i8> %4
} }
define <8 x i64> @neg_scalar_broadcast_v64i8_v8i64(i8 %a0, <8 x i64> %a1) {
; SSE-LABEL: neg_scalar_broadcast_v64i8_v8i64:
; SSE: # %bb.0:
; SSE-NEXT: notb %dil
; SSE-NEXT: movzbl %dil, %eax
; SSE-NEXT: movd %eax, %xmm4
; SSE-NEXT: pxor %xmm5, %xmm5
; SSE-NEXT: pshufb %xmm5, %xmm4
; SSE-NEXT: pand %xmm4, %xmm0
; SSE-NEXT: pand %xmm4, %xmm1
; SSE-NEXT: pand %xmm4, %xmm2
; SSE-NEXT: pand %xmm4, %xmm3
; SSE-NEXT: retq
;
; AVX1-LABEL: neg_scalar_broadcast_v64i8_v8i64:
; AVX1: # %bb.0:
; AVX1-NEXT: notb %dil
; AVX1-NEXT: vmovd %edi, %xmm2
; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3
; AVX1-NEXT: vpshufb %xmm3, %xmm2, %xmm2
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm2, %ymm2
; AVX1-NEXT: vandps %ymm0, %ymm2, %ymm0
; AVX1-NEXT: vandps %ymm1, %ymm2, %ymm1
; AVX1-NEXT: retq
;
; AVX2-LABEL: neg_scalar_broadcast_v64i8_v8i64:
; AVX2: # %bb.0:
; AVX2-NEXT: notb %dil
; AVX2-NEXT: vmovd %edi, %xmm2
; AVX2-NEXT: vpbroadcastb %xmm2, %ymm2
; AVX2-NEXT: vpand %ymm0, %ymm2, %ymm0
; AVX2-NEXT: vpand %ymm1, %ymm2, %ymm1
; AVX2-NEXT: retq
;
; AVX512-LABEL: neg_scalar_broadcast_v64i8_v8i64:
; AVX512: # %bb.0:
; AVX512-NEXT: notb %dil
; AVX512-NEXT: vpbroadcastb %edi, %zmm1
; AVX512-NEXT: vpandq %zmm0, %zmm1, %zmm0
; AVX512-NEXT: retq
%1 = xor i8 %a0, -1
%2 = insertelement <64 x i8> undef, i8 %1, i64 0
%3 = shufflevector <64 x i8> %2, <64 x i8> poison, <64 x i32> zeroinitializer
%4 = bitcast <64 x i8> %3 to <8 x i64>
%5 = and <8 x i64> %4, %a1
ret <8 x i64> %5
}
define <4 x i64> @neg_scalar_broadcast_v32i8_v4i64(i8 %a0, <4 x i64> %a1) {
; SSE-LABEL: neg_scalar_broadcast_v32i8_v4i64:
; SSE: # %bb.0:
; SSE-NEXT: notb %dil
; SSE-NEXT: movzbl %dil, %eax
; SSE-NEXT: movd %eax, %xmm2
; SSE-NEXT: pxor %xmm3, %xmm3
; SSE-NEXT: pshufb %xmm3, %xmm2
; SSE-NEXT: pand %xmm2, %xmm0
; SSE-NEXT: pand %xmm2, %xmm1
; SSE-NEXT: retq
;
; AVX1-LABEL: neg_scalar_broadcast_v32i8_v4i64:
; AVX1: # %bb.0:
; AVX1-NEXT: notb %dil
; AVX1-NEXT: vmovd %edi, %xmm1
; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm1, %ymm1
; AVX1-NEXT: vandps %ymm0, %ymm1, %ymm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: neg_scalar_broadcast_v32i8_v4i64:
; AVX2: # %bb.0:
; AVX2-NEXT: notb %dil
; AVX2-NEXT: vmovd %edi, %xmm1
; AVX2-NEXT: vpbroadcastb %xmm1, %ymm1
; AVX2-NEXT: vpand %ymm0, %ymm1, %ymm0
; AVX2-NEXT: retq
;
; AVX512-LABEL: neg_scalar_broadcast_v32i8_v4i64:
; AVX512: # %bb.0:
; AVX512-NEXT: notb %dil
; AVX512-NEXT: vpbroadcastb %edi, %ymm1
; AVX512-NEXT: vpand %ymm0, %ymm1, %ymm0
; AVX512-NEXT: retq
%1 = xor i8 %a0, -1
%2 = insertelement <32 x i8> undef, i8 %1, i64 0
%3 = shufflevector <32 x i8> %2, <32 x i8> poison, <32 x i32> zeroinitializer
%4 = bitcast <32 x i8> %3 to <4 x i64>
%5 = and <4 x i64> %4, %a1
ret <4 x i64> %5
}
define <2 x i64> @neg_scalar_broadcast_v16i8_v2i64(i8 %a0, <2 x i64> %a1) { define <2 x i64> @neg_scalar_broadcast_v16i8_v2i64(i8 %a0, <2 x i64> %a1) {
; SSE-LABEL: neg_scalar_broadcast_v16i8_v2i64: ; SSE-LABEL: neg_scalar_broadcast_v16i8_v2i64:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: notb %dil ; SSE-NEXT: notb %dil
; SSE-NEXT: movzbl %dil, %eax ; SSE-NEXT: movzbl %dil, %eax
; SSE-NEXT: movd %eax, %xmm1 ; SSE-NEXT: movd %eax, %xmm1
; SSE-NEXT: pxor %xmm2, %xmm2 ; SSE-NEXT: pxor %xmm2, %xmm2
; SSE-NEXT: pshufb %xmm2, %xmm1 ; SSE-NEXT: pshufb %xmm2, %xmm1
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