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Differential D139246

[X86][ConstraintFP] Model `MXCSR` when load/store it
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Authored by pengfei on Dec 2 2022, 10:27 PM.

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Reviewers
andrew.w.kaylor
craig.topper
RKSimon
lebedev.ri
sepavloff
andreadb
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rGb1221d10dd15: [X86][ConstraintFP] Model `MXCSR` when load/store it
Summary

This patch partially fixes #59305.

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pengfei created this revision.Dec 2 2022, 10:27 PM
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Harbormaster completed remote builds in B200888: Diff 479803.Dec 2 2022, 11:08 PM
RKSimon accepted this revision.Dec 5 2022, 2:50 AM

LGTM

This revision is now accepted and ready to land.Dec 5 2022, 2:50 AM
Closed by commit rGb1221d10dd15: [X86][ConstraintFP] Model `MXCSR` when load/store it (authored by pengfei). · Explain WhyDec 7 2022, 5:48 PM
This revision was automatically updated to reflect the committed changes.
pengfei added a commit: rGb1221d10dd15: [X86][ConstraintFP] Model `MXCSR` when load/store it.

Revision Contents

PathSize
llvm/
lib/
Target/
X86/
8 lines
test/
tools/
llvm-mca/
X86/
BtVer2/
58 lines
Haswell/
74 lines

Diff 479803

llvm/lib/Target/X86/X86InstrSSE.td

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
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} // SchedRW } // SchedRW
def : Pat<(X86MFence), (MFENCE)>; def : Pat<(X86MFence), (MFENCE)>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// SSE 1 & 2 - Load/Store XCSR register // SSE 1 & 2 - Load/Store XCSR register
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
let mayLoad=1, hasSideEffects=1 in let mayLoad=1, hasSideEffects=1, Defs=[MXCSR] in
def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src), def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
"ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>, "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>,
VEX, Sched<[WriteLDMXCSR]>, VEX_WIG; VEX, Sched<[WriteLDMXCSR]>, VEX_WIG;
let mayStore=1, hasSideEffects=1 in let mayStore=1, hasSideEffects=1, Uses=[MXCSR] in
def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst), def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
"stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>, "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>,
VEX, Sched<[WriteSTMXCSR]>, VEX_WIG; VEX, Sched<[WriteSTMXCSR]>, VEX_WIG;
let mayLoad=1, hasSideEffects=1 in let mayLoad=1, hasSideEffects=1, Defs=[MXCSR] in
def LDMXCSR : I<0xAE, MRM2m, (outs), (ins i32mem:$src), def LDMXCSR : I<0xAE, MRM2m, (outs), (ins i32mem:$src),
"ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>, "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>,
PS, Sched<[WriteLDMXCSR]>; PS, Sched<[WriteLDMXCSR]>;
let mayStore=1, hasSideEffects=1 in let mayStore=1, hasSideEffects=1, Uses=[MXCSR] in
def STMXCSR : I<0xAE, MRM3m, (outs), (ins i32mem:$dst), def STMXCSR : I<0xAE, MRM3m, (outs), (ins i32mem:$dst),
"stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>, "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>,
PS, Sched<[WriteSTMXCSR]>; PS, Sched<[WriteSTMXCSR]>;
//===---------------------------------------------------------------------===// //===---------------------------------------------------------------------===//
// SSE2 - Move Aligned/Unaligned Packed Integer Instructions // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
//===---------------------------------------------------------------------===// //===---------------------------------------------------------------------===//
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llvm/test/tools/llvm-mca/X86/BtVer2/stmxcsr-ldmxcsr.s

# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -timeline -timeline-max-iterations=3 < %s | FileCheck %s # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -timeline -timeline-max-iterations=3 < %s | FileCheck %s
# Code snippet taken from PR48024. # Code snippet taken from PR48024.
stmxcsr -4(%rsp) stmxcsr -4(%rsp)
movl $-24577, %eax # imm = 0x9FFF movl $-24577, %eax # imm = 0x9FFF
andl -4(%rsp), %eax andl -4(%rsp), %eax
movl %eax, -8(%rsp) movl %eax, -8(%rsp)
ldmxcsr -8(%rsp) ldmxcsr -8(%rsp)
retq retq
# CHECK: Iterations: 100 # CHECK: Iterations: 100
# CHECK-NEXT: Instructions: 600 # CHECK-NEXT: Instructions: 600
# CHECK-NEXT: Total Cycles: 308 # CHECK-NEXT: Total Cycles: 407
# CHECK-NEXT: Total uOps: 600 # CHECK-NEXT: Total uOps: 600
# CHECK: Dispatch Width: 2 # CHECK: Dispatch Width: 2
# CHECK-NEXT: uOps Per Cycle: 1.95 # CHECK-NEXT: uOps Per Cycle: 1.47
# CHECK-NEXT: IPC: 1.95 # CHECK-NEXT: IPC: 1.47
# CHECK-NEXT: Block RThroughput: 3.0 # CHECK-NEXT: Block RThroughput: 3.0
# CHECK: Instruction Info: # CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps # CHECK-NEXT: [1]: #uOps
# CHECK-NEXT: [2]: Latency # CHECK-NEXT: [2]: Latency
# CHECK-NEXT: [3]: RThroughput # CHECK-NEXT: [3]: RThroughput
# CHECK-NEXT: [4]: MayLoad # CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore # CHECK-NEXT: [5]: MayStore
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# CHECK-NEXT: - - - - - - - - - 1.00 - - - - stmxcsr -4(%rsp) # CHECK-NEXT: - - - - - - - - - 1.00 - - - - stmxcsr -4(%rsp)
# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - movl $-24577, %eax # CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - movl $-24577, %eax
# CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - - - - - - andl -4(%rsp), %eax # CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - - - - - - andl -4(%rsp), %eax
# CHECK-NEXT: - - - - - - - - - 1.00 - - - - movl %eax, -8(%rsp) # CHECK-NEXT: - - - - - - - - - 1.00 - - - - movl %eax, -8(%rsp)
# CHECK-NEXT: - - - - - - - 1.00 - - - - - - ldmxcsr -8(%rsp) # CHECK-NEXT: - - - - - - - 1.00 - - - - - - ldmxcsr -8(%rsp)
# CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - - - - - - retq # CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - - - - - - retq
# CHECK: Timeline view: # CHECK: Timeline view:
# CHECK-NEXT: 0123456 # CHECK-NEXT: 012345678
# CHECK-NEXT: Index 0123456789 # CHECK-NEXT: Index 0123456789
# CHECK: [0,0] DeER . . .. stmxcsr -4(%rsp) # CHECK: [0,0] DeER . . . . stmxcsr -4(%rsp)
# CHECK-NEXT: [0,1] DeER . . .. movl $-24577, %eax # CHECK-NEXT: [0,1] DeER . . . . movl $-24577, %eax
# CHECK-NEXT: [0,2] .DeeeeER . .. andl -4(%rsp), %eax # CHECK-NEXT: [0,2] .DeeeeER . . . andl -4(%rsp), %eax
# CHECK-NEXT: [0,3] .D====eER . .. movl %eax, -8(%rsp) # CHECK-NEXT: [0,3] .D====eER . . . movl %eax, -8(%rsp)
# CHECK-NEXT: [0,4] . D===eeeER .. ldmxcsr -8(%rsp) # CHECK-NEXT: [0,4] . D===eeeER . . ldmxcsr -8(%rsp)
# CHECK-NEXT: [0,5] . DeeeeE--R .. retq # CHECK-NEXT: [0,5] . DeeeeE--R . . retq
# CHECK-NEXT: [1,0] . D===eE--R .. stmxcsr -4(%rsp) # CHECK-NEXT: [1,0] . D=====eER . . stmxcsr -4(%rsp)
# CHECK-NEXT: [1,1] . DeE-----R .. movl $-24577, %eax # CHECK-NEXT: [1,1] . DeE-----R . . movl $-24577, %eax
# CHECK-NEXT: [1,2] . DeeeeE--R .. andl -4(%rsp), %eax # CHECK-NEXT: [1,2] . DeeeeE--R . . andl -4(%rsp), %eax
# CHECK-NEXT: [1,3] . D====eE-R .. movl %eax, -8(%rsp) # CHECK-NEXT: [1,3] . D=====eER . . movl %eax, -8(%rsp)
# CHECK-NEXT: [1,4] . D===eeeER .. ldmxcsr -8(%rsp) # CHECK-NEXT: [1,4] . D====eeeER. . ldmxcsr -8(%rsp)
# CHECK-NEXT: [1,5] . D=eeeeE-R .. retq # CHECK-NEXT: [1,5] . D=eeeeE--R. . retq
# CHECK-NEXT: [2,0] . .D===eE--R.. stmxcsr -4(%rsp) # CHECK-NEXT: [2,0] . .D======eER . stmxcsr -4(%rsp)
# CHECK-NEXT: [2,1] . .DeE-----R.. movl $-24577, %eax # CHECK-NEXT: [2,1] . .DeE------R . movl $-24577, %eax
# CHECK-NEXT: [2,2] . . DeeeeE--R. andl -4(%rsp), %eax # CHECK-NEXT: [2,2] . . DeeeeE---R . andl -4(%rsp), %eax
# CHECK-NEXT: [2,3] . . D====eE-R. movl %eax, -8(%rsp) # CHECK-NEXT: [2,3] . . D======eER . movl %eax, -8(%rsp)
# CHECK-NEXT: [2,4] . . D===eeeER ldmxcsr -8(%rsp) # CHECK-NEXT: [2,4] . . D=====eeeER ldmxcsr -8(%rsp)
# CHECK-NEXT: [2,5] . . D=eeeeE-R retq # CHECK-NEXT: [2,5] . . DeeeeE----R retq
# CHECK: Average Wait times (based on the timeline view): # CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions # CHECK-NEXT: [0]: Executions
# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3] # CHECK: [0] [1] [2] [3]
# CHECK-NEXT: 0. 3 3.0 1.0 1.3 stmxcsr -4(%rsp) # CHECK-NEXT: 0. 3 4.7 0.3 0.0 stmxcsr -4(%rsp)
# CHECK-NEXT: 1. 3 1.0 1.0 3.3 movl $-24577, %eax # CHECK-NEXT: 1. 3 1.0 1.0 3.7 movl $-24577, %eax
# CHECK-NEXT: 2. 3 1.0 1.0 1.3 andl -4(%rsp), %eax # CHECK-NEXT: 2. 3 1.0 1.0 1.7 andl -4(%rsp), %eax
# CHECK-NEXT: 3. 3 5.0 0.0 0.7 movl %eax, -8(%rsp) # CHECK-NEXT: 3. 3 6.0 0.7 0.0 movl %eax, -8(%rsp)
# CHECK-NEXT: 4. 3 4.0 0.0 0.0 ldmxcsr -8(%rsp) # CHECK-NEXT: 4. 3 5.0 0.0 0.0 ldmxcsr -8(%rsp)
# CHECK-NEXT: 5. 3 1.7 1.7 1.3 retq # CHECK-NEXT: 5. 3 1.3 1.3 2.7 retq
# CHECK-NEXT: 3 2.6 0.8 1.3 <total> # CHECK-NEXT: 3 3.2 0.7 1.3 <total>

llvm/test/tools/llvm-mca/X86/Haswell/stmxcsr-ldmxcsr.s

# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=haswell -timeline -timeline-max-iterations=3 < %s | FileCheck %s # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=haswell -timeline -timeline-max-iterations=3 < %s | FileCheck %s
# Code snippet taken from PR48024. # Code snippet taken from PR48024.
stmxcsr -4(%rsp) stmxcsr -4(%rsp)
movl $-24577, %eax # imm = 0x9FFF movl $-24577, %eax # imm = 0x9FFF
andl -4(%rsp), %eax andl -4(%rsp), %eax
movl %eax, -8(%rsp) movl %eax, -8(%rsp)
ldmxcsr -8(%rsp) ldmxcsr -8(%rsp)
retq retq
# CHECK: Iterations: 100 # CHECK: Iterations: 100
# CHECK-NEXT: Instructions: 600 # CHECK-NEXT: Instructions: 600
# CHECK-NEXT: Total Cycles: 413 # CHECK-NEXT: Total Cycles: 809
# CHECK-NEXT: Total uOps: 1300 # CHECK-NEXT: Total uOps: 1300
# CHECK: Dispatch Width: 4 # CHECK: Dispatch Width: 4
# CHECK-NEXT: uOps Per Cycle: 3.15 # CHECK-NEXT: uOps Per Cycle: 1.61
# CHECK-NEXT: IPC: 1.45 # CHECK-NEXT: IPC: 0.74
# CHECK-NEXT: Block RThroughput: 3.3 # CHECK-NEXT: Block RThroughput: 3.3
# CHECK: Instruction Info: # CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps # CHECK-NEXT: [1]: #uOps
# CHECK-NEXT: [2]: Latency # CHECK-NEXT: [2]: Latency
# CHECK-NEXT: [3]: RThroughput # CHECK-NEXT: [3]: RThroughput
# CHECK-NEXT: [4]: MayLoad # CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore # CHECK-NEXT: [5]: MayStore
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# CHECK-NEXT: [5] - HWPort3 # CHECK-NEXT: [5] - HWPort3
# CHECK-NEXT: [6] - HWPort4 # CHECK-NEXT: [6] - HWPort4
# CHECK-NEXT: [7] - HWPort5 # CHECK-NEXT: [7] - HWPort5
# CHECK-NEXT: [8] - HWPort6 # CHECK-NEXT: [8] - HWPort6
# CHECK-NEXT: [9] - HWPort7 # CHECK-NEXT: [9] - HWPort7
# CHECK: Resource pressure per iteration: # CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9]
# CHECK-NEXT: - - 1.99 1.50 1.66 1.67 2.00 1.52 1.99 1.67 # CHECK-NEXT: - - 1.77 1.71 1.75 1.75 2.00 1.81 1.71 1.50
# CHECK: Resource pressure by instruction: # CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
# CHECK-NEXT: - - - - 0.16 - 1.00 1.00 - 0.84 stmxcsr -4(%rsp) # CHECK-NEXT: - - - - - - 1.00 1.00 - 1.00 stmxcsr -4(%rsp)
# CHECK-NEXT: - - 0.49 0.49 - - - 0.01 0.01 - movl $-24577, %eax # CHECK-NEXT: - - 0.26 0.46 - - - 0.27 0.01 - movl $-24577, %eax
# CHECK-NEXT: - - 0.49 0.02 0.49 0.51 - 0.01 0.48 - andl -4(%rsp), %eax # CHECK-NEXT: - - 0.28 0.28 0.49 0.51 - 0.07 0.37 - andl -4(%rsp), %eax
# CHECK-NEXT: - - - - 0.17 - 1.00 - - 0.83 movl %eax, -8(%rsp) # CHECK-NEXT: - - - - 0.18 0.32 1.00 - - 0.50 movl %eax, -8(%rsp)
# CHECK-NEXT: - - 1.00 0.01 0.33 0.67 - 0.49 0.50 - ldmxcsr -8(%rsp) # CHECK-NEXT: - - 1.00 0.67 0.58 0.42 - - 0.33 - ldmxcsr -8(%rsp)
# CHECK-NEXT: - - 0.01 0.98 0.51 0.49 - 0.01 1.00 - retq # CHECK-NEXT: - - 0.23 0.30 0.50 0.50 - 0.47 1.00 - retq
# CHECK: Timeline view: # CHECK: Timeline view:
# CHECK-NEXT: 0123456789 # CHECK-NEXT: 0123456789 012
# CHECK-NEXT: Index 0123456789 01234 # CHECK-NEXT: Index 0123456789 0123456789
# CHECK: [0,0] DeeER. . . . . stmxcsr -4(%rsp) # CHECK: [0,0] DeeER. . . . . . . stmxcsr -4(%rsp)
# CHECK-NEXT: [0,1] DeE-R. . . . . movl $-24577, %eax # CHECK-NEXT: [0,1] DeE-R. . . . . . . movl $-24577, %eax
# CHECK-NEXT: [0,2] .DeeeeeeER. . . . andl -4(%rsp), %eax # CHECK-NEXT: [0,2] .DeeeeeeER. . . . . . andl -4(%rsp), %eax
# CHECK-NEXT: [0,3] .D======eER . . . movl %eax, -8(%rsp) # CHECK-NEXT: [0,3] .D======eER . . . . . movl %eax, -8(%rsp)
# CHECK-NEXT: [0,4] . D=====eeeeeeeER . . ldmxcsr -8(%rsp) # CHECK-NEXT: [0,4] . D=====eeeeeeeER . . . . ldmxcsr -8(%rsp)
# CHECK-NEXT: [0,5] . DeeeeeeeE----R . . retq # CHECK-NEXT: [0,5] . DeeeeeeeE----R . . . . retq
# CHECK-NEXT: [1,0] . D====eeE----R . . stmxcsr -4(%rsp) # CHECK-NEXT: [1,0] . D==========eeER . . . . stmxcsr -4(%rsp)
# CHECK-NEXT: [1,1] . DeE---------R . . movl $-24577, %eax # CHECK-NEXT: [1,1] . DeE-----------R . . . . movl $-24577, %eax
# CHECK-NEXT: [1,2] . DeeeeeeE---R . . andl -4(%rsp), %eax # CHECK-NEXT: [1,2] . DeeeeeeE-----R . . . . andl -4(%rsp), %eax
# CHECK-NEXT: [1,3] . D======eE--R . . movl %eax, -8(%rsp) # CHECK-NEXT: [1,3] . D==========eER . . . . movl %eax, -8(%rsp)
# CHECK-NEXT: [1,4] . .D=====eeeeeeeER . ldmxcsr -8(%rsp) # CHECK-NEXT: [1,4] . .D=========eeeeeeeER. . . ldmxcsr -8(%rsp)
# CHECK-NEXT: [1,5] . . D=eeeeeeeE---R . retq # CHECK-NEXT: [1,5] . . D=eeeeeeeE-------R. . . retq
# CHECK-NEXT: [2,0] . . D====eeE----R . stmxcsr -4(%rsp) # CHECK-NEXT: [2,0] . . D==============eeER . . stmxcsr -4(%rsp)
# CHECK-NEXT: [2,1] . . DeE---------R . movl $-24577, %eax # CHECK-NEXT: [2,1] . . DeE---------------R . . movl $-24577, %eax
# CHECK-NEXT: [2,2] . . DeeeeeeE---R . andl -4(%rsp), %eax # CHECK-NEXT: [2,2] . . DeeeeeeE---------R . . andl -4(%rsp), %eax
# CHECK-NEXT: [2,3] . . D======eE--R . movl %eax, -8(%rsp) # CHECK-NEXT: [2,3] . . D==============eER . . movl %eax, -8(%rsp)
# CHECK-NEXT: [2,4] . . D=====eeeeeeeER ldmxcsr -8(%rsp) # CHECK-NEXT: [2,4] . . D=============eeeeeeeER ldmxcsr -8(%rsp)
# CHECK-NEXT: [2,5] . . .DeeeeeeeE----R retq # CHECK-NEXT: [2,5] . . .DeeeeeeeE------------R retq
# CHECK: Average Wait times (based on the timeline view): # CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions # CHECK-NEXT: [0]: Executions
# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3] # CHECK: [0] [1] [2] [3]
# CHECK-NEXT: 0. 3 3.7 1.0 2.7 stmxcsr -4(%rsp) # CHECK-NEXT: 0. 3 9.0 0.3 0.0 stmxcsr -4(%rsp)
# CHECK-NEXT: 1. 3 1.0 1.0 6.3 movl $-24577, %eax # CHECK-NEXT: 1. 3 1.0 1.0 9.0 movl $-24577, %eax
# CHECK-NEXT: 2. 3 1.0 1.0 2.0 andl -4(%rsp), %eax # CHECK-NEXT: 2. 3 1.0 1.0 4.7 andl -4(%rsp), %eax
# CHECK-NEXT: 3. 3 7.0 0.0 1.3 movl %eax, -8(%rsp) # CHECK-NEXT: 3. 3 11.0 0.7 0.0 movl %eax, -8(%rsp)
# CHECK-NEXT: 4. 3 6.0 0.0 0.0 ldmxcsr -8(%rsp) # CHECK-NEXT: 4. 3 10.0 0.0 0.0 ldmxcsr -8(%rsp)
# CHECK-NEXT: 5. 3 1.3 1.3 3.7 retq # CHECK-NEXT: 5. 3 1.3 1.3 7.7 retq
# CHECK-NEXT: 3 3.3 0.7 2.7 <total> # CHECK-NEXT: 3 5.6 0.7 3.6 <total>