[clang][CodeGen] Add noundef metadata to load instructions (preliminary 3 or 5)

[jmciver]

Summary

Add noundef attribute support for matrix and vector type loads in support of elemental or sufflevector operations.

[jmciver]

Updating D138983: [clang][CodeGen] Add noundef metadata to load instructions (preliminary 3 or 3)

The following tests have been updated:

• matrix-type-operators.c

clang/lib/CodeGen/CGExpr.cpp

if (LV.isSimple()) {
 
     // Everything needs a load.
     return RValue::get(EmitLoadOfScalar(LV, Loc));
   }
 
   if (LV.isVectorElt()) {
     llvm::LoadInst *Load = Builder.CreateLoad(LV.getVectorAddress(),
                                               LV.isVolatileQualified());
+    applyNoundefToLoadInst(CGM.getCodeGenOpts().EnableNoundefLoadAttr,
+                           LV.getType(), Load);
     return RValue::get(Builder.CreateExtractElement(Load, LV.getVectorIdx(),
                                                     "vecext"));
   }
 
   // If this is a reference to a subset of the elements of a vector, either
   // shuffle the input or extract/insert them as appropriate.
   if (LV.isExtVectorElt()) {
     return EmitLoadOfExtVectorElementLValue(LV);
   }
 
   // Global Register variables always invoke intrinsics
   if (LV.isGlobalReg())
     return EmitLoadOfGlobalRegLValue(LV);
 
   if (LV.isMatrixElt()) {
     llvm::Value *Idx = LV.getMatrixIdx();
     if (CGM.getCodeGenOpts().OptimizationLevel > 0) {
       const auto *const MatTy = LV.getType()->castAs<ConstantMatrixType>();
       llvm::MatrixBuilder MB(Builder);
       MB.CreateIndexAssumption(Idx, MatTy->getNumElementsFlattened());
     }
     llvm::LoadInst *Load =
         Builder.CreateLoad(LV.getMatrixAddress(), LV.isVolatileQualified());
+    applyNoundefToLoadInst(CGM.getCodeGenOpts().EnableNoundefLoadAttr,
+                           LV.getType(), Load);
     return RValue::get(Builder.CreateExtractElement(Load, Idx, "matrixext"));
   }
 
   assert(LV.isBitField() && "Unknown LValue type!");
   return EmitLoadOfBitfieldLValue(LV, Loc);
 }
 
 RValue CodeGenFunction::EmitLoadOfBitfieldLValue(LValue LV,
RValue CodeGenFunction::EmitLoadOfBitfieldLValue(LValue LV,
   return RValue::get(Val);
 }
 
 // If this is a reference to a subset of the elements of a vector, create an
 // appropriate shufflevector.
 RValue CodeGenFunction::EmitLoadOfExtVectorElementLValue(LValue LV) {
   llvm::Value *Vec = Builder.CreateLoad(LV.getExtVectorAddress(),
                                         LV.isVolatileQualified());
+  applyNoundefToLoadInst(CGM.getCodeGenOpts().EnableNoundefLoadAttr,
+                         LV.getType(), dyn_cast<llvm::LoadInst>(Vec));
 
   const llvm::Constant *Elts = LV.getExtVectorElts();
 
   // If the result of the expression is a non-vector type, we must be extracting
   // a single element.  Just codegen as an extractelement.
   const VectorType *ExprVT = LV.getType()->getAs<VectorType>();
   if (!ExprVT) {
     unsigned InIdx = getAccessedFieldNo(0, Elts);

clang/test/CodeGen/matrix-type-operators.c

void insert_extract(dx5x5_t a, fx3x3_t b, unsigned long j, short k) {
   // CHECK-NEXT:    store <9 x float> [[MATINS]], <9 x float>* [[MAT_ADDR]], align 4
   // CHECK-NEXT:    ret void
 
   b[2][j] = b[0][k];
 }
 
 void insert_compound_stmt(dx5x5_t a) {
   // CHECK-LABEL: define{{.*}} void @insert_compound_stmt(<25 x double> noundef %a)
-  // CHECK:        [[A:%.*]] = load <25 x double>, <25 x double>* [[A_PTR:%.*]], align 8{{$}}
+  // CHECK:        [[A:%.*]] = load <25 x double>, <25 x double>* [[A_PTR:%.*]], align 8, !noundef [[NOUNDEF:![0-9]+]]{{$}}
   // CHECK-NEXT:   [[EXT:%.*]] = extractelement <25 x double> [[A]], i64 17
   // CHECK-NEXT:   [[SUB:%.*]] = fsub double [[EXT]], 1.000000e+00
   // CHECK-NEXT:   [[A2:%.*]] = load <25 x double>, <25 x double>* [[A_PTR]], align 8{{$}}
   // CHECK-NEXT:   [[INS:%.*]] = insertelement <25 x double> [[A2]], double [[SUB]], i64 17
   // CHECK-NEXT:   store <25 x double> [[INS]], <25 x double>* [[A_PTR]], align 8
   // CHECK-NEXT:   ret void
 
   a[2][3] -= 1.0;
void insert_compound_stmt_field(struct Foo *a, float f, unsigned i, unsigned j) {
   // NOOPT-NEXT:    [[J:%.*]] = load i32, i32* %j.addr, align 4, !noundef [[NOUNDEF]]{{$}}
   // OPT-NEXT:      [[J:%.*]] = load i32, i32* %j.addr, align 4, !tbaa !{{[0-9]+}}, !noundef [[NOUNDEF]]{{$}}
   // CHECK-NEXT:    [[J_EXT:%.*]] = zext i32 [[J]] to i64
   // CHECK-NEXT:    [[IDX1:%.*]] = mul i64 [[J_EXT]], 2
   // CHECK-NEXT:    [[IDX2:%.*]] = add i64 [[IDX1]], [[I_EXT]]
   // CHECK-NEXT:    [[MAT_PTR:%.*]] = bitcast [6 x float]* %mat to <6 x float>*
   // OPT-NEXT:      [[CMP:%.*]] = icmp ult i64 [[IDX2]], 6
   // OPT-NEXT:      call void @llvm.assume(i1 [[CMP]])
-  // CHECK-NEXT:    [[MAT:%.*]] = load <6 x float>, <6 x float>* [[MAT_PTR]], align 4{{$}}
+  // CHECK-NEXT:    [[MAT:%.*]] = load <6 x float>, <6 x float>* [[MAT_PTR]], align 4, !noundef [[NOUNDEF]]{{$}}
   // CHECK-NEXT:    [[EXT:%.*]] = extractelement <6 x float> [[MAT]], i64 [[IDX2]]
   // CHECK-NEXT:    [[SUM:%.*]] = fadd float [[EXT]], {{.*}}
   // OPT-NEXT:      [[CMP:%.*]] = icmp ult i64 [[IDX2]], 6
   // OPT-NEXT:      call void @llvm.assume(i1 [[CMP]])
   // CHECK-NEXT:    [[MAT2:%.*]] = load <6 x float>, <6 x float>* [[MAT_PTR]], align 4{{$}}
   // CHECK-NEXT:    [[INS:%.*]] = insertelement <6 x float> [[MAT2]], float [[SUM]], i64 [[IDX2]]
   // CHECK-NEXT:    store <6 x float> [[INS]], <6 x float>* [[MAT_PTR]], align 4
   // CHECK-NEXT:    ret void

clang/test/CodeGen/vector-noundef.c

+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -no-opaque-pointers -flax-vector-conversions=none -ffreestanding -triple x86_64-gnu-linux -target-feature +avx512f -O0 -enable-noundef-load-analysis -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -no-opaque-pointers -flax-vector-conversions=none -ffreestanding -triple x86_64-gnu-linux -target-feature +avx512f -O0 -no-enable-noundef-load-analysis -emit-llvm -o - %s | FileCheck %s --check-prefix=DISABLE
+
+#include <immintrin.h>
+
+// CHECK-LABEL: @test_mm_mask_div_ss(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[__A_ADDR_I:%.*]] = alloca <4 x float>, align 16
+// CHECK-NEXT:    [[__B_ADDR_I:%.*]] = alloca <4 x float>, align 16
+// CHECK-NEXT:    [[__W_ADDR_I:%.*]] = alloca <4 x float>, align 16
+// CHECK-NEXT:    [[__U_ADDR_I:%.*]] = alloca i8, align 1
+// CHECK-NEXT:    [[__A_ADDR_I2:%.*]] = alloca <4 x float>, align 16
+// CHECK-NEXT:    [[__B_ADDR_I2:%.*]] = alloca <4 x float>, align 16
+// CHECK-NEXT:    [[__W_ADDR:%.*]] = alloca <4 x float>, align 16
+// CHECK-NEXT:    [[__U_ADDR:%.*]] = alloca i8, align 1
+// CHECK-NEXT:    [[__A_ADDR:%.*]] = alloca <4 x float>, align 16
+// CHECK-NEXT:    [[__B_ADDR:%.*]] = alloca <4 x float>, align 16
+// CHECK-NEXT:    store <4 x float> [[__W:%.*]], <4 x float>* [[__W_ADDR]], align 16
+// CHECK-NEXT:    store i8 [[__U:%.*]], i8* [[__U_ADDR]], align 1
+// CHECK-NEXT:    store <4 x float> [[__A:%.*]], <4 x float>* [[__A_ADDR]], align 16
+// CHECK-NEXT:    store <4 x float> [[__B:%.*]], <4 x float>* [[__B_ADDR]], align 16
+// CHECK-NEXT:    [[TMP0:%.*]] = load <4 x float>, <4 x float>* [[__W_ADDR]], align 16, !noundef [[NOUNDEF2:![0-9]+]]
+// CHECK-NEXT:    [[TMP1:%.*]] = load i8, i8* [[__U_ADDR]], align 1
+// CHECK-NEXT:    [[TMP2:%.*]] = load <4 x float>, <4 x float>* [[__A_ADDR]], align 16, !noundef [[NOUNDEF2]]
+// CHECK-NEXT:    [[TMP3:%.*]] = load <4 x float>, <4 x float>* [[__B_ADDR]], align 16, !noundef [[NOUNDEF2]]
+// CHECK-NEXT:    store <4 x float> [[TMP0]], <4 x float>* [[__W_ADDR_I]], align 16
+// CHECK-NEXT:    store i8 [[TMP1]], i8* [[__U_ADDR_I]], align 1
+// CHECK-NEXT:    store <4 x float> [[TMP2]], <4 x float>* [[__A_ADDR_I2]], align 16
+// CHECK-NEXT:    store <4 x float> [[TMP3]], <4 x float>* [[__B_ADDR_I2]], align 16
+// CHECK-NEXT:    [[TMP4:%.*]] = load <4 x float>, <4 x float>* [[__A_ADDR_I2]], align 16, !noundef [[NOUNDEF2]]
+// CHECK-NEXT:    [[TMP5:%.*]] = load <4 x float>, <4 x float>* [[__B_ADDR_I2]], align 16, !noundef [[NOUNDEF2]]
+// CHECK-NEXT:    store <4 x float> [[TMP4]], <4 x float>* [[__A_ADDR_I]], align 16
+// CHECK-NEXT:    store <4 x float> [[TMP5]], <4 x float>* [[__B_ADDR_I]], align 16
+// CHECK-NEXT:    [[TMP6:%.*]] = load <4 x float>, <4 x float>* [[__B_ADDR_I]], align 16, !noundef [[NOUNDEF2]]
+// CHECK-NEXT:    [[VECEXT_I:%.*]] = extractelement <4 x float> [[TMP6]], i32 0
+// CHECK-NEXT:    [[TMP7:%.*]] = load <4 x float>, <4 x float>* [[__A_ADDR_I]], align 16, !noundef [[NOUNDEF2]]
+// CHECK-NEXT:    [[VECEXT1_I:%.*]] = extractelement <4 x float> [[TMP7]], i32 0
+// CHECK-NEXT:    [[DIV_I:%.*]] = fdiv float [[VECEXT1_I]], [[VECEXT_I]]
+// CHECK-NEXT:    [[TMP8:%.*]] = load <4 x float>, <4 x float>* [[__A_ADDR_I]], align 16
+// CHECK-NEXT:    [[VECINS_I:%.*]] = insertelement <4 x float> [[TMP8]], float [[DIV_I]], i32 0
+// CHECK-NEXT:    store <4 x float> [[VECINS_I]], <4 x float>* [[__A_ADDR_I]], align 16
+// CHECK-NEXT:    [[TMP9:%.*]] = load <4 x float>, <4 x float>* [[__A_ADDR_I]], align 16, !noundef [[NOUNDEF2]]
+// CHECK-NEXT:    store <4 x float> [[TMP9]], <4 x float>* [[__A_ADDR_I2]], align 16
+// CHECK-NEXT:    [[TMP10:%.*]] = load i8, i8* [[__U_ADDR_I]], align 1
+// CHECK-NEXT:    [[TMP11:%.*]] = load <4 x float>, <4 x float>* [[__A_ADDR_I2]], align 16, !noundef [[NOUNDEF2]]
+// CHECK-NEXT:    [[TMP12:%.*]] = load <4 x float>, <4 x float>* [[__W_ADDR_I]], align 16, !noundef [[NOUNDEF2]]
+// CHECK-NEXT:    [[TMP13:%.*]] = extractelement <4 x float> [[TMP11]], i64 0
+// CHECK-NEXT:    [[TMP14:%.*]] = extractelement <4 x float> [[TMP12]], i64 0
+// CHECK-NEXT:    [[TMP15:%.*]] = bitcast i8 [[TMP10]] to <8 x i1>
+// CHECK-NEXT:    [[TMP16:%.*]] = extractelement <8 x i1> [[TMP15]], i64 0
+// CHECK-NEXT:    [[TMP17:%.*]] = select i1 [[TMP16]], float [[TMP13]], float [[TMP14]]
+// CHECK-NEXT:    [[TMP18:%.*]] = insertelement <4 x float> [[TMP11]], float [[TMP17]], i64 0
+// CHECK-NEXT:    ret <4 x float> [[TMP18]]
+//
+// DISABLE-LABEL: @test_mm_mask_div_ss(
+// DISABLE-NEXT:  entry:
+// DISABLE-NEXT:    [[__A_ADDR_I:%.*]] = alloca <4 x float>, align 16
+// DISABLE-NEXT:    [[__B_ADDR_I:%.*]] = alloca <4 x float>, align 16
+// DISABLE-NEXT:    [[__W_ADDR_I:%.*]] = alloca <4 x float>, align 16
+// DISABLE-NEXT:    [[__U_ADDR_I:%.*]] = alloca i8, align 1
+// DISABLE-NEXT:    [[__A_ADDR_I2:%.*]] = alloca <4 x float>, align 16
+// DISABLE-NEXT:    [[__B_ADDR_I2:%.*]] = alloca <4 x float>, align 16
+// DISABLE-NEXT:    [[__W_ADDR:%.*]] = alloca <4 x float>, align 16
+// DISABLE-NEXT:    [[__U_ADDR:%.*]] = alloca i8, align 1
+// DISABLE-NEXT:    [[__A_ADDR:%.*]] = alloca <4 x float>, align 16
+// DISABLE-NEXT:    [[__B_ADDR:%.*]] = alloca <4 x float>, align 16
+// DISABLE-NEXT:    store <4 x float> [[__W:%.*]], <4 x float>* [[__W_ADDR]], align 16
+// DISABLE-NEXT:    store i8 [[__U:%.*]], i8* [[__U_ADDR]], align 1
+// DISABLE-NEXT:    store <4 x float> [[__A:%.*]], <4 x float>* [[__A_ADDR]], align 16
+// DISABLE-NEXT:    store <4 x float> [[__B:%.*]], <4 x float>* [[__B_ADDR]], align 16
+// DISABLE-NEXT:    [[TMP0:%.*]] = load <4 x float>, <4 x float>* [[__W_ADDR]], align 16
+// DISABLE-NEXT:    [[TMP1:%.*]] = load i8, i8* [[__U_ADDR]], align 1
+// DISABLE-NEXT:    [[TMP2:%.*]] = load <4 x float>, <4 x float>* [[__A_ADDR]], align 16
+// DISABLE-NEXT:    [[TMP3:%.*]] = load <4 x float>, <4 x float>* [[__B_ADDR]], align 16
+// DISABLE-NEXT:    store <4 x float> [[TMP0]], <4 x float>* [[__W_ADDR_I]], align 16
+// DISABLE-NEXT:    store i8 [[TMP1]], i8* [[__U_ADDR_I]], align 1
+// DISABLE-NEXT:    store <4 x float> [[TMP2]], <4 x float>* [[__A_ADDR_I2]], align 16
+// DISABLE-NEXT:    store <4 x float> [[TMP3]], <4 x float>* [[__B_ADDR_I2]], align 16
+// DISABLE-NEXT:    [[TMP4:%.*]] = load <4 x float>, <4 x float>* [[__A_ADDR_I2]], align 16
+// DISABLE-NEXT:    [[TMP5:%.*]] = load <4 x float>, <4 x float>* [[__B_ADDR_I2]], align 16
+// DISABLE-NEXT:    store <4 x float> [[TMP4]], <4 x float>* [[__A_ADDR_I]], align 16
+// DISABLE-NEXT:    store <4 x float> [[TMP5]], <4 x float>* [[__B_ADDR_I]], align 16
+// DISABLE-NEXT:    [[TMP6:%.*]] = load <4 x float>, <4 x float>* [[__B_ADDR_I]], align 16
+// DISABLE-NEXT:    [[VECEXT_I:%.*]] = extractelement <4 x float> [[TMP6]], i32 0
+// DISABLE-NEXT:    [[TMP7:%.*]] = load <4 x float>, <4 x float>* [[__A_ADDR_I]], align 16
+// DISABLE-NEXT:    [[VECEXT1_I:%.*]] = extractelement <4 x float> [[TMP7]], i32 0
+// DISABLE-NEXT:    [[DIV_I:%.*]] = fdiv float [[VECEXT1_I]], [[VECEXT_I]]
+// DISABLE-NEXT:    [[TMP8:%.*]] = load <4 x float>, <4 x float>* [[__A_ADDR_I]], align 16
+// DISABLE-NEXT:    [[VECINS_I:%.*]] = insertelement <4 x float> [[TMP8]], float [[DIV_I]], i32 0
+// DISABLE-NEXT:    store <4 x float> [[VECINS_I]], <4 x float>* [[__A_ADDR_I]], align 16
+// DISABLE-NEXT:    [[TMP9:%.*]] = load <4 x float>, <4 x float>* [[__A_ADDR_I]], align 16
+// DISABLE-NEXT:    store <4 x float> [[TMP9]], <4 x float>* [[__A_ADDR_I2]], align 16
+// DISABLE-NEXT:    [[TMP10:%.*]] = load i8, i8* [[__U_ADDR_I]], align 1
+// DISABLE-NEXT:    [[TMP11:%.*]] = load <4 x float>, <4 x float>* [[__A_ADDR_I2]], align 16
+// DISABLE-NEXT:    [[TMP12:%.*]] = load <4 x float>, <4 x float>* [[__W_ADDR_I]], align 16
+// DISABLE-NEXT:    [[TMP13:%.*]] = extractelement <4 x float> [[TMP11]], i64 0
+// DISABLE-NEXT:    [[TMP14:%.*]] = extractelement <4 x float> [[TMP12]], i64 0
+// DISABLE-NEXT:    [[TMP15:%.*]] = bitcast i8 [[TMP10]] to <8 x i1>
+// DISABLE-NEXT:    [[TMP16:%.*]] = extractelement <8 x i1> [[TMP15]], i64 0
+// DISABLE-NEXT:    [[TMP17:%.*]] = select i1 [[TMP16]], float [[TMP13]], float [[TMP14]]
+// DISABLE-NEXT:    [[TMP18:%.*]] = insertelement <4 x float> [[TMP11]], float [[TMP17]], i64 0
+// DISABLE-NEXT:    ret <4 x float> [[TMP18]]
+//
+__m128 test_mm_mask_div_ss(__m128 __W, __mmask8 __U, __m128 __A, __m128 __B) {
+  return _mm_mask_div_ss(__W,__U,__A,__B);
+}

clang/test/CodeGenCXX/vector-noundef.cpp

 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // RUN: %clang_cc1 -std=c++17 -triple x86_64-gnu-linux -O0 -enable-noundef-load-analysis -emit-llvm -o - %s | FileCheck %s
 // RUN: %clang_cc1 -std=c++17 -triple x86_64-gnu-linux -O0 -no-enable-noundef-load-analysis -emit-llvm -o - %s | FileCheck %s --check-prefix=DISABLE
 
 using VecOfFourBools __attribute__((ext_vector_type(4))) = bool;
 using VecOfThreeChars __attribute__((ext_vector_type(3))) = char;
 using VecOfThreeUChars __attribute__((ext_vector_type(3))) = unsigned char;
 
+using VecOfFourFloats __attribute__((ext_vector_type(4))) = float;
+using VecOfTwoFloats __attribute__((ext_vector_type(2))) = float;
+
 // CHECK-LABEL: @_Z15getElement4BoolRDv4_b(
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
 // CHECK-NEXT:    store ptr [[A:%.*]], ptr [[A_ADDR]], align 8
 // CHECK-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
 // CHECK-NEXT:    [[LOAD_BITS:%.*]] = load i8, ptr [[TMP0]], align 1, !noundef [[NOUNDEF2:![0-9]+]]
 // CHECK-NEXT:    [[TMP1:%.*]] = bitcast i8 [[LOAD_BITS]] to <8 x i1>
 // CHECK-NEXT:    [[EXTRACTVEC:%.*]] = shufflevector <8 x i1> [[TMP1]], <8 x i1> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>

 // DISABLE-NEXT:    [[EXTRACTVEC:%.*]] = shufflevector <4 x i8> [[LOADVEC4]], <4 x i8> poison, <3 x i32> <i32 0, i32 1, i32 2>
 // DISABLE-NEXT:    [[VECEXT:%.*]] = extractelement <3 x i8> [[EXTRACTVEC]], i32 0
 // DISABLE-NEXT:    ret i8 [[VECEXT]]
 //
 char getElement3UChar(VecOfThreeUChars& a)
 {
   return a[0];
 }
+
+// CHECK-LABEL: @_Z16vectorSubsectionRDv2_fRDv4_f(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[VEC2_ADDR:%.*]] = alloca ptr, align 8
+// CHECK-NEXT:    [[VEC4_ADDR:%.*]] = alloca ptr, align 8
+// CHECK-NEXT:    store ptr [[VEC2:%.*]], ptr [[VEC2_ADDR]], align 8
+// CHECK-NEXT:    store ptr [[VEC4:%.*]], ptr [[VEC4_ADDR]], align 8
+// CHECK-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VEC4_ADDR]], align 8
+// CHECK-NEXT:    [[TMP1:%.*]] = load <4 x float>, ptr [[TMP0]], align 16, !noundef [[NOUNDEF2]]
+// CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> poison, <2 x i32> <i32 0, i32 1>
+// CHECK-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[VEC2_ADDR]], align 8
+// CHECK-NEXT:    store <2 x float> [[TMP2]], ptr [[TMP3]], align 8
+// CHECK-NEXT:    ret void
+//
+// DISABLE-LABEL: @_Z16vectorSubsectionRDv2_fRDv4_f(
+// DISABLE-NEXT:  entry:
+// DISABLE-NEXT:    [[VEC2_ADDR:%.*]] = alloca ptr, align 8
+// DISABLE-NEXT:    [[VEC4_ADDR:%.*]] = alloca ptr, align 8
+// DISABLE-NEXT:    store ptr [[VEC2:%.*]], ptr [[VEC2_ADDR]], align 8
+// DISABLE-NEXT:    store ptr [[VEC4:%.*]], ptr [[VEC4_ADDR]], align 8
+// DISABLE-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VEC4_ADDR]], align 8
+// DISABLE-NEXT:    [[TMP1:%.*]] = load <4 x float>, ptr [[TMP0]], align 16
+// DISABLE-NEXT:    [[TMP2:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> poison, <2 x i32> <i32 0, i32 1>
+// DISABLE-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[VEC2_ADDR]], align 8
+// DISABLE-NEXT:    store <2 x float> [[TMP2]], ptr [[TMP3]], align 8
+// DISABLE-NEXT:    ret void
+//
+void vectorSubsection(VecOfTwoFloats& vec2, VecOfFourFloats& vec4) {
+    vec2 = vec4.xy;
+}