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Differential D138045

[TargetLowering][RISCV][ARM][AArch64][Mips] Reduce the number of AND mask constants used by BSWAP expansion.
ClosedPublic

Authored by craig.topper on Nov 15 2022, 10:41 AM.

Details

Reviewers
RKSimon
spatel
reames
efriedma
Commits
rGf387918dd854: [TargetLowering][RISCV][ARM][AArch64][Mips] Reduce the number of AND mask…
Summary

We can reuse constants if we use SRL followed by AND and AND followed by SHL.
Similar was done to bitreverse previously.

Diff Detail

Event Timeline

craig.topper created this revision.Nov 15 2022, 10:41 AM
Herald added a project: Restricted Project. · View Herald TranscriptNov 15 2022, 10:41 AM
Herald added subscribers: sunshaoce, VincentWu, StephenFan and 32 others. · View Herald Transcript
craig.topper requested review of this revision.Nov 15 2022, 10:41 AM
Herald added a project: Restricted Project. · View Herald TranscriptNov 15 2022, 10:41 AM
Herald added subscribers: • pcwang-thead, eopXD, MaskRay. · View Herald Transcript
craig.topper added a reviewer: efriedma.Nov 15 2022, 10:41 AM
Harbormaster completed remote builds in B197795: Diff 475519.Nov 15 2022, 11:32 AM
efriedma accepted this revision.Nov 15 2022, 1:31 PM

LGTM; seems to help all the testcases, likely to be generally beneficial, and if it somehow hurts some target, that target can always override.

This revision is now accepted and ready to land.Nov 15 2022, 1:31 PM
This revision was landed with ongoing or failed builds.Nov 15 2022, 2:36 PM
Closed by commit rGf387918dd854: [TargetLowering][RISCV][ARM][AArch64][Mips] Reduce the number of AND mask… (authored by craig.topper). · Explain Why
This revision was automatically updated to reflect the committed changes.
craig.topper added a commit: rGf387918dd854: [TargetLowering][RISCV][ARM][AArch64][Mips] Reduce the number of AND mask….
craig.topper mentioned this in D137928: [VP][RISCV] Add vp.bswap and RISC-V support..Nov 15 2022, 2:36 PM

Revision Contents

PathSize
llvm/
lib/
CodeGen/
SelectionDAG/
34 lines
test/
CodeGen/
AArch64/
351 lines
ARM/
49 lines
37 lines
Mips/
36 lines
RISCV/
180 lines
22 lines
61 lines
rvv/
516 lines
402 lines
436 lines
276 lines

Diff 475584

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 8,342 Lines • ▼ Show 20 LinesSDValue TargetLowering::expandBSWAP(SDNode *N, SelectionDAG &DAG) const {
switch (VT.getSimpleVT().getScalarType().SimpleTy) { switch (VT.getSimpleVT().getScalarType().SimpleTy) {
default: default:
return SDValue(); return SDValue();
case MVT::i16: case MVT::i16:
// Use a rotate by 8. This can be further expanded if necessary. // Use a rotate by 8. This can be further expanded if necessary.
return DAG.getNode(ISD::ROTL, dl, VT, Op, DAG.getConstant(8, dl, SHVT)); return DAG.getNode(ISD::ROTL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
case MVT::i32: case MVT::i32:
Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, dl, SHVT)); Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, dl, SHVT));
Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, dl, SHVT)); Tmp3 = DAG.getNode(ISD::AND, dl, VT, Op,
DAG.getConstant(0xFF00, dl, VT));
Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Tmp3, DAG.getConstant(8, dl, SHVT));
Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, dl, SHVT)); Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, dl, SHVT));
Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3,
DAG.getConstant(0xFF0000, dl, VT));
Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, dl, VT)); Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, dl, VT));
Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, dl, SHVT));
Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3); Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1); Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2); return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
case MVT::i64: case MVT::i64:
Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, dl, SHVT)); Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, dl, SHVT));
Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, dl, SHVT)); Tmp7 = DAG.getNode(ISD::AND, dl, VT, Op,
Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, dl, SHVT)); DAG.getConstant(255ULL<<8, dl, VT));
Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, dl, SHVT)); Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Tmp7, DAG.getConstant(40, dl, SHVT));
Tmp6 = DAG.getNode(ISD::AND, dl, VT, Op,
DAG.getConstant(255ULL<<16, dl, VT));
Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Tmp6, DAG.getConstant(24, dl, SHVT));
Tmp5 = DAG.getNode(ISD::AND, dl, VT, Op,
DAG.getConstant(255ULL<<24, dl, VT));
Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Tmp5, DAG.getConstant(8, dl, SHVT));
Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, dl, SHVT)); Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, dl, SHVT));
Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, dl, SHVT));
Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, dl, SHVT));
Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7,
DAG.getConstant(255ULL<<48, dl, VT));
Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6,
DAG.getConstant(255ULL<<40, dl, VT));
Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5,
DAG.getConstant(255ULL<<32, dl, VT));
Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4,
DAG.getConstant(255ULL<<24, dl, VT)); DAG.getConstant(255ULL<<24, dl, VT));
Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, dl, SHVT));
Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3,
DAG.getConstant(255ULL<<16, dl, VT)); DAG.getConstant(255ULL<<16, dl, VT));
Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, dl, SHVT));
Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2,
DAG.getConstant(255ULL<<8 , dl, VT)); DAG.getConstant(255ULL<<8, dl, VT));
Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, dl, SHVT));
Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7); Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7);
Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5); Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5);
Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3); Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1); Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6); Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6);
Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2); Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4); return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4);
} }
▲ Show 20 Lines • Show All 1,727 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-rev.ll

Show First 20 Lines • Show All 195 Lines • ▼ Show 20 Lines
; ;
; REVB ; REVB
; ;
define <2 x i16> @bswap_v2i16(<2 x i16> %op) #0 { define <2 x i16> @bswap_v2i16(<2 x i16> %op) #0 {
; CHECK-LABEL: bswap_v2i16: ; CHECK-LABEL: bswap_v2i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI14_0 ; CHECK-NEXT: adrp x8, .LCPI14_0
; CHECK-NEXT: adrp x9, .LCPI14_1
; CHECK-NEXT: adrp x10, .LCPI14_2 ; CHECK-NEXT: adrp x10, .LCPI14_2
; CHECK-NEXT: adrp x9, .LCPI14_1
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 ; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
; CHECK-NEXT: ptrue p0.s, vl2 ; CHECK-NEXT: ptrue p0.s, vl2
; CHECK-NEXT: ldr d1, [x8, :lo12:.LCPI14_0] ; CHECK-NEXT: ldr d1, [x8, :lo12:.LCPI14_0]
; CHECK-NEXT: adrp x8, .LCPI14_3 ; CHECK-NEXT: adrp x8, .LCPI14_3
; CHECK-NEXT: ldr d3, [x10, :lo12:.LCPI14_2]
; CHECK-NEXT: movprfx z4, z0
; CHECK-NEXT: lsr z4.s, p0/m, z4.s, z1.s
; CHECK-NEXT: ldr d2, [x9, :lo12:.LCPI14_1] ; CHECK-NEXT: ldr d2, [x9, :lo12:.LCPI14_1]
; CHECK-NEXT: movprfx z5, z0 ; CHECK-NEXT: movprfx z5, z0
; CHECK-NEXT: lsr z5.s, p0/m, z5.s, z1.s ; CHECK-NEXT: lsr z5.s, p0/m, z5.s, z2.s
; CHECK-NEXT: ldr d3, [x10, :lo12:.LCPI14_2]
; CHECK-NEXT: movprfx z6, z0
; CHECK-NEXT: lsr z6.s, p0/m, z6.s, z2.s
; CHECK-NEXT: ldr d4, [x8, :lo12:.LCPI14_3]
; CHECK-NEXT: adrp x8, .LCPI14_4
; CHECK-NEXT: lslr z1.s, p0/m, z1.s, z0.s ; CHECK-NEXT: lslr z1.s, p0/m, z1.s, z0.s
; CHECK-NEXT: and z0.d, z0.d, z3.d
; CHECK-NEXT: and z3.d, z5.d, z3.d
; CHECK-NEXT: lsl z0.s, p0/m, z0.s, z2.s ; CHECK-NEXT: lsl z0.s, p0/m, z0.s, z2.s
; CHECK-NEXT: and z2.d, z6.d, z3.d ; CHECK-NEXT: ldr d2, [x8, :lo12:.LCPI14_3]
; CHECK-NEXT: and z0.d, z0.d, z4.d ; CHECK-NEXT: orr z3.d, z3.d, z4.d
; CHECK-NEXT: ldr d3, [x8, :lo12:.LCPI14_4]
; CHECK-NEXT: orr z2.d, z2.d, z5.d
; CHECK-NEXT: orr z0.d, z1.d, z0.d ; CHECK-NEXT: orr z0.d, z1.d, z0.d
; CHECK-NEXT: orr z0.d, z0.d, z2.d ; CHECK-NEXT: orr z0.d, z0.d, z3.d
; CHECK-NEXT: lsr z0.s, p0/m, z0.s, z3.s ; CHECK-NEXT: lsr z0.s, p0/m, z0.s, z2.s
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <2 x i16> @llvm.bswap.v2i16(<2 x i16> %op) %res = call <2 x i16> @llvm.bswap.v2i16(<2 x i16> %op)
ret <2 x i16> %res ret <2 x i16> %res
} }
define <4 x i16> @bswap_v4i16(<4 x i16> %op) #0 { define <4 x i16> @bswap_v4i16(<4 x i16> %op) #0 {
; CHECK-LABEL: bswap_v4i16: ; CHECK-LABEL: bswap_v4i16:
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%res = call <16 x i16> @llvm.bswap.v16i16(<16 x i16> %op) %res = call <16 x i16> @llvm.bswap.v16i16(<16 x i16> %op)
store <16 x i16> %res, <16 x i16>* %a store <16 x i16> %res, <16 x i16>* %a
ret void ret void
} }
define <2 x i32> @bswap_v2i32(<2 x i32> %op) #0 { define <2 x i32> @bswap_v2i32(<2 x i32> %op) #0 {
; CHECK-LABEL: bswap_v2i32: ; CHECK-LABEL: bswap_v2i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI18_1 ; CHECK-NEXT: adrp x8, .LCPI18_0
; CHECK-NEXT: adrp x9, .LCPI18_2 ; CHECK-NEXT: adrp x10, .LCPI18_2
; CHECK-NEXT: adrp x10, .LCPI18_0 ; CHECK-NEXT: adrp x9, .LCPI18_1
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 ; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
; CHECK-NEXT: ptrue p0.s, vl2 ; CHECK-NEXT: ptrue p0.s, vl2
; CHECK-NEXT: ldr d1, [x8, :lo12:.LCPI18_1] ; CHECK-NEXT: ldr d1, [x8, :lo12:.LCPI18_0]
; CHECK-NEXT: adrp x8, .LCPI18_3 ; CHECK-NEXT: movprfx z4, z0
; CHECK-NEXT: ldr d2, [x9, :lo12:.LCPI18_2] ; CHECK-NEXT: lsr z4.s, p0/m, z4.s, z1.s
; CHECK-NEXT: ldr d3, [x10, :lo12:.LCPI18_2]
; CHECK-NEXT: ldr d2, [x9, :lo12:.LCPI18_1]
; CHECK-NEXT: movprfx z5, z0 ; CHECK-NEXT: movprfx z5, z0
; CHECK-NEXT: lsr z5.s, p0/m, z5.s, z1.s ; CHECK-NEXT: lsr z5.s, p0/m, z5.s, z2.s
; CHECK-NEXT: ldr d3, [x10, :lo12:.LCPI18_0] ; CHECK-NEXT: and z5.d, z5.d, z3.d
; CHECK-NEXT: ldr d4, [x8, :lo12:.LCPI18_3] ; CHECK-NEXT: and z3.d, z0.d, z3.d
; CHECK-NEXT: and z2.d, z5.d, z2.d ; CHECK-NEXT: lsl z0.s, p0/m, z0.s, z1.s
; CHECK-NEXT: movprfx z5, z0 ; CHECK-NEXT: movprfx z1, z3
; CHECK-NEXT: lsr z5.s, p0/m, z5.s, z3.s ; CHECK-NEXT: lsl z1.s, p0/m, z1.s, z2.s
; CHECK-NEXT: lslr z1.s, p0/m, z1.s, z0.s ; CHECK-NEXT: orr z2.d, z5.d, z4.d
; CHECK-NEXT: lsl z0.s, p0/m, z0.s, z3.s
; CHECK-NEXT: and z1.d, z1.d, z4.d
; CHECK-NEXT: orr z2.d, z2.d, z5.d
; CHECK-NEXT: orr z0.d, z0.d, z1.d ; CHECK-NEXT: orr z0.d, z0.d, z1.d
; CHECK-NEXT: orr z0.d, z0.d, z2.d ; CHECK-NEXT: orr z0.d, z0.d, z2.d
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <2 x i32> @llvm.bswap.v2i32(<2 x i32> %op) %res = call <2 x i32> @llvm.bswap.v2i32(<2 x i32> %op)
ret <2 x i32> %res ret <2 x i32> %res
} }
define <4 x i32> @bswap_v4i32(<4 x i32> %op) #0 { define <4 x i32> @bswap_v4i32(<4 x i32> %op) #0 {
; CHECK-LABEL: bswap_v4i32: ; CHECK-LABEL: bswap_v4i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI19_1 ; CHECK-NEXT: adrp x8, .LCPI19_0
; CHECK-NEXT: adrp x9, .LCPI19_2 ; CHECK-NEXT: adrp x10, .LCPI19_2
; CHECK-NEXT: adrp x10, .LCPI19_0 ; CHECK-NEXT: adrp x9, .LCPI19_1
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 ; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
; CHECK-NEXT: ptrue p0.s, vl4 ; CHECK-NEXT: ptrue p0.s, vl4
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI19_1] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI19_0]
; CHECK-NEXT: adrp x8, .LCPI19_3 ; CHECK-NEXT: movprfx z4, z0
; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI19_2] ; CHECK-NEXT: lsr z4.s, p0/m, z4.s, z1.s
; CHECK-NEXT: ldr q3, [x10, :lo12:.LCPI19_2]
; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI19_1]
; CHECK-NEXT: movprfx z5, z0 ; CHECK-NEXT: movprfx z5, z0
; CHECK-NEXT: lsr z5.s, p0/m, z5.s, z1.s ; CHECK-NEXT: lsr z5.s, p0/m, z5.s, z2.s
; CHECK-NEXT: ldr q3, [x10, :lo12:.LCPI19_0] ; CHECK-NEXT: and z5.d, z5.d, z3.d
; CHECK-NEXT: ldr q4, [x8, :lo12:.LCPI19_3] ; CHECK-NEXT: and z3.d, z0.d, z3.d
; CHECK-NEXT: and z2.d, z5.d, z2.d ; CHECK-NEXT: lsl z0.s, p0/m, z0.s, z1.s
; CHECK-NEXT: movprfx z5, z0 ; CHECK-NEXT: movprfx z1, z3
; CHECK-NEXT: lsr z5.s, p0/m, z5.s, z3.s ; CHECK-NEXT: lsl z1.s, p0/m, z1.s, z2.s
; CHECK-NEXT: lslr z1.s, p0/m, z1.s, z0.s ; CHECK-NEXT: orr z2.d, z5.d, z4.d
; CHECK-NEXT: lsl z0.s, p0/m, z0.s, z3.s
; CHECK-NEXT: and z1.d, z1.d, z4.d
; CHECK-NEXT: orr z2.d, z2.d, z5.d
; CHECK-NEXT: orr z0.d, z0.d, z1.d ; CHECK-NEXT: orr z0.d, z0.d, z1.d
; CHECK-NEXT: orr z0.d, z0.d, z2.d ; CHECK-NEXT: orr z0.d, z0.d, z2.d
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %op) %res = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %op)
ret <4 x i32> %res ret <4 x i32> %res
} }
define void @bswap_v8i32(<8 x i32>* %a) #0 { define void @bswap_v8i32(<8 x i32>* %a) #0 {
; CHECK-LABEL: bswap_v8i32: ; CHECK-LABEL: bswap_v8i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI20_0 ; CHECK-NEXT: adrp x8, .LCPI20_0
; CHECK-NEXT: adrp x9, .LCPI20_1 ; CHECK-NEXT: adrp x9, .LCPI20_1
; CHECK-NEXT: ldp q3, q2, [x0] ; CHECK-NEXT: ldp q4, q1, [x0]
; CHECK-NEXT: ptrue p0.s, vl4 ; CHECK-NEXT: ptrue p0.s, vl4
; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI20_0] ; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI20_0]
; CHECK-NEXT: adrp x8, .LCPI20_2 ; CHECK-NEXT: adrp x8, .LCPI20_2
; CHECK-NEXT: ldr q1, [x9, :lo12:.LCPI20_1] ; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI20_1]
; CHECK-NEXT: movprfx z5, z2 ; CHECK-NEXT: movprfx z5, z1
; CHECK-NEXT: lsr z5.s, p0/m, z5.s, z0.s ; CHECK-NEXT: lsr z5.s, p0/m, z5.s, z0.s
; CHECK-NEXT: movprfx z6, z2 ; CHECK-NEXT: movprfx z6, z1
; CHECK-NEXT: lsr z6.s, p0/m, z6.s, z1.s ; CHECK-NEXT: lsr z6.s, p0/m, z6.s, z2.s
; CHECK-NEXT: movprfx z7, z2 ; CHECK-NEXT: movprfx z7, z1
; CHECK-NEXT: lsl z7.s, p0/m, z7.s, z0.s ; CHECK-NEXT: lsl z7.s, p0/m, z7.s, z0.s
; CHECK-NEXT: ldr q4, [x8, :lo12:.LCPI20_2] ; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI20_2]
; CHECK-NEXT: adrp x8, .LCPI20_3 ; CHECK-NEXT: movprfx z16, z4
; CHECK-NEXT: lsl z2.s, p0/m, z2.s, z1.s ; CHECK-NEXT: lsr z16.s, p0/m, z16.s, z2.s
; CHECK-NEXT: and z6.d, z6.d, z4.d ; CHECK-NEXT: and z1.d, z1.d, z3.d
; CHECK-NEXT: ldr q16, [x8, :lo12:.LCPI20_3] ; CHECK-NEXT: and z6.d, z6.d, z3.d
; CHECK-NEXT: and z16.d, z16.d, z3.d
; CHECK-NEXT: and z3.d, z4.d, z3.d
; CHECK-NEXT: orr z5.d, z6.d, z5.d ; CHECK-NEXT: orr z5.d, z6.d, z5.d
; CHECK-NEXT: movprfx z6, z3 ; CHECK-NEXT: movprfx z6, z4
; CHECK-NEXT: lsr z6.s, p0/m, z6.s, z1.s
; CHECK-NEXT: and z4.d, z6.d, z4.d
; CHECK-NEXT: movprfx z6, z3
; CHECK-NEXT: lsr z6.s, p0/m, z6.s, z0.s ; CHECK-NEXT: lsr z6.s, p0/m, z6.s, z0.s
; CHECK-NEXT: lslr z0.s, p0/m, z0.s, z3.s ; CHECK-NEXT: lslr z0.s, p0/m, z0.s, z4.s
; CHECK-NEXT: lslr z1.s, p0/m, z1.s, z3.s ; CHECK-NEXT: lsl z1.s, p0/m, z1.s, z2.s
; CHECK-NEXT: and z2.d, z2.d, z16.d ; CHECK-NEXT: lslr z2.s, p0/m, z2.s, z3.s
; CHECK-NEXT: and z1.d, z1.d, z16.d ; CHECK-NEXT: orr z3.d, z16.d, z6.d
; CHECK-NEXT: orr z3.d, z4.d, z6.d ; CHECK-NEXT: orr z0.d, z0.d, z2.d
; CHECK-NEXT: orr z0.d, z0.d, z1.d ; CHECK-NEXT: orr z1.d, z7.d, z1.d
; CHECK-NEXT: orr z1.d, z7.d, z2.d
; CHECK-NEXT: orr z0.d, z0.d, z3.d ; CHECK-NEXT: orr z0.d, z0.d, z3.d
; CHECK-NEXT: orr z1.d, z1.d, z5.d ; CHECK-NEXT: orr z1.d, z1.d, z5.d
; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: stp q0, q1, [x0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%op = load <8 x i32>, <8 x i32>* %a %op = load <8 x i32>, <8 x i32>* %a
%res = call <8 x i32> @llvm.bswap.v8i32(<8 x i32> %op) %res = call <8 x i32> @llvm.bswap.v8i32(<8 x i32> %op)
store <8 x i32> %res, <8 x i32>* %a store <8 x i32> %res, <8 x i32>* %a
ret void ret void
} }
define <1 x i64> @bswap_v1i64(<1 x i64> %op) #0 { define <1 x i64> @bswap_v1i64(<1 x i64> %op) #0 {
; CHECK-LABEL: bswap_v1i64: ; CHECK-LABEL: bswap_v1i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #56 ; CHECK-NEXT: mov w8, #56
; CHECK-NEXT: mov w9, #40 ; CHECK-NEXT: mov w9, #40
; CHECK-NEXT: mov w10, #65280 ; CHECK-NEXT: mov w10, #65280
; CHECK-NEXT: mov w11, #24
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 ; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
; CHECK-NEXT: ptrue p0.d, vl1 ; CHECK-NEXT: ptrue p0.d, vl1
; CHECK-NEXT: fmov d1, x8 ; CHECK-NEXT: fmov d1, x8
; CHECK-NEXT: mov w8, #24 ; CHECK-NEXT: mov w8, #16711680
; CHECK-NEXT: fmov d2, x9 ; CHECK-NEXT: fmov d2, x9
; CHECK-NEXT: mov w9, #16711680 ; CHECK-NEXT: mov w9, #8
; CHECK-NEXT: fmov d3, x10 ; CHECK-NEXT: fmov d3, x10
; CHECK-NEXT: mov w10, #8 ; CHECK-NEXT: movprfx z7, z0
; CHECK-NEXT: fmov d4, x8 ; CHECK-NEXT: lsr z7.d, p0/m, z7.d, z1.d
; CHECK-NEXT: fmov d5, x8
; CHECK-NEXT: mov w8, #-16777216 ; CHECK-NEXT: mov w8, #-16777216
; CHECK-NEXT: fmov d5, x9
; CHECK-NEXT: mov x9, #1095216660480
; CHECK-NEXT: movprfx z16, z0 ; CHECK-NEXT: movprfx z16, z0
; CHECK-NEXT: lsr z16.d, p0/m, z16.d, z2.d ; CHECK-NEXT: lsr z16.d, p0/m, z16.d, z2.d
; CHECK-NEXT: and z3.d, z16.d, z3.d ; CHECK-NEXT: fmov d4, x11
; CHECK-NEXT: fmov d7, x8 ; CHECK-NEXT: fmov d6, x9
; CHECK-NEXT: mov x8, #280375465082880 ; CHECK-NEXT: and z16.d, z16.d, z3.d
; CHECK-NEXT: fmov d17, x8
; CHECK-NEXT: orr z7.d, z16.d, z7.d
; CHECK-NEXT: movprfx z16, z0 ; CHECK-NEXT: movprfx z16, z0
; CHECK-NEXT: lsr z16.d, p0/m, z16.d, z4.d ; CHECK-NEXT: lsr z16.d, p0/m, z16.d, z4.d
; CHECK-NEXT: fmov d6, x10 ; CHECK-NEXT: movprfx z18, z0
; CHECK-NEXT: and z5.d, z16.d, z5.d ; CHECK-NEXT: lsr z18.d, p0/m, z18.d, z6.d
; CHECK-NEXT: movprfx z16, z0 ; CHECK-NEXT: and z16.d, z16.d, z5.d
; CHECK-NEXT: lsr z16.d, p0/m, z16.d, z6.d ; CHECK-NEXT: and z5.d, z0.d, z5.d
; CHECK-NEXT: fmov d18, x8 ; CHECK-NEXT: and z18.d, z18.d, z17.d
; CHECK-NEXT: mov x8, #71776119061217280 ; CHECK-NEXT: and z17.d, z0.d, z17.d
; CHECK-NEXT: and z7.d, z16.d, z7.d ; CHECK-NEXT: lslr z6.d, p0/m, z6.d, z17.d
; CHECK-NEXT: fmov d17, x9 ; CHECK-NEXT: lslr z4.d, p0/m, z4.d, z5.d
; CHECK-NEXT: orr z5.d, z7.d, z5.d ; CHECK-NEXT: and z3.d, z0.d, z3.d
; CHECK-NEXT: movprfx z16, z0
; CHECK-NEXT: lsr z16.d, p0/m, z16.d, z1.d
; CHECK-NEXT: fmov d7, x8
; CHECK-NEXT: lslr z6.d, p0/m, z6.d, z0.d
; CHECK-NEXT: lslr z4.d, p0/m, z4.d, z0.d
; CHECK-NEXT: lslr z2.d, p0/m, z2.d, z0.d
; CHECK-NEXT: and z6.d, z6.d, z17.d
; CHECK-NEXT: and z4.d, z4.d, z18.d
; CHECK-NEXT: lsl z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: lsl z0.d, p0/m, z0.d, z1.d
; CHECK-NEXT: and z1.d, z2.d, z7.d ; CHECK-NEXT: orr z16.d, z18.d, z16.d
; CHECK-NEXT: orr z3.d, z3.d, z16.d ; CHECK-NEXT: movprfx z1, z3
; CHECK-NEXT: lsl z1.d, p0/m, z1.d, z2.d
; CHECK-NEXT: orr z2.d, z4.d, z6.d ; CHECK-NEXT: orr z2.d, z4.d, z6.d
; CHECK-NEXT: orr z0.d, z0.d, z1.d ; CHECK-NEXT: orr z0.d, z0.d, z1.d
; CHECK-NEXT: orr z1.d, z5.d, z3.d ; CHECK-NEXT: orr z1.d, z16.d, z7.d
; CHECK-NEXT: orr z0.d, z0.d, z2.d ; CHECK-NEXT: orr z0.d, z0.d, z2.d
; CHECK-NEXT: orr z0.d, z0.d, z1.d ; CHECK-NEXT: orr z0.d, z0.d, z1.d
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <1 x i64> @llvm.bswap.v1i64(<1 x i64> %op) %res = call <1 x i64> @llvm.bswap.v1i64(<1 x i64> %op)
ret <1 x i64> %res ret <1 x i64> %res
} }
Show All 9 Lines
; CHECK-NEXT: adrp x8, .LCPI22_3 ; CHECK-NEXT: adrp x8, .LCPI22_3
; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI22_1] ; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI22_1]
; CHECK-NEXT: adrp x9, .LCPI22_4 ; CHECK-NEXT: adrp x9, .LCPI22_4
; CHECK-NEXT: ldr q3, [x10, :lo12:.LCPI22_2] ; CHECK-NEXT: ldr q3, [x10, :lo12:.LCPI22_2]
; CHECK-NEXT: adrp x10, .LCPI22_5 ; CHECK-NEXT: adrp x10, .LCPI22_5
; CHECK-NEXT: ldr q4, [x8, :lo12:.LCPI22_3] ; CHECK-NEXT: ldr q4, [x8, :lo12:.LCPI22_3]
; CHECK-NEXT: adrp x8, .LCPI22_6 ; CHECK-NEXT: adrp x8, .LCPI22_6
; CHECK-NEXT: ldr q5, [x9, :lo12:.LCPI22_4] ; CHECK-NEXT: ldr q5, [x9, :lo12:.LCPI22_4]
; CHECK-NEXT: adrp x9, .LCPI22_7 ; CHECK-NEXT: movprfx z7, z0
; CHECK-NEXT: lsr z7.d, p0/m, z7.d, z1.d
; CHECK-NEXT: movprfx z16, z0 ; CHECK-NEXT: movprfx z16, z0
; CHECK-NEXT: lsr z16.d, p0/m, z16.d, z2.d ; CHECK-NEXT: lsr z16.d, p0/m, z16.d, z2.d
; CHECK-NEXT: and z3.d, z16.d, z3.d
; CHECK-NEXT: ldr q7, [x8, :lo12:.LCPI22_6]
; CHECK-NEXT: adrp x8, .LCPI22_8
; CHECK-NEXT: movprfx z16, z0
; CHECK-NEXT: lsr z16.d, p0/m, z16.d, z4.d
; CHECK-NEXT: ldr q6, [x10, :lo12:.LCPI22_5] ; CHECK-NEXT: ldr q6, [x10, :lo12:.LCPI22_5]
; CHECK-NEXT: and z5.d, z16.d, z5.d ; CHECK-NEXT: ldr q17, [x8, :lo12:.LCPI22_6]
; CHECK-NEXT: movprfx z16, z0 ; CHECK-NEXT: and z16.d, z16.d, z3.d
; CHECK-NEXT: lsr z16.d, p0/m, z16.d, z6.d ; CHECK-NEXT: orr z7.d, z16.d, z7.d
; CHECK-NEXT: ldr q18, [x8, :lo12:.LCPI22_8]
; CHECK-NEXT: adrp x8, .LCPI22_9
; CHECK-NEXT: and z7.d, z16.d, z7.d
; CHECK-NEXT: ldr q17, [x9, :lo12:.LCPI22_7]
; CHECK-NEXT: orr z5.d, z7.d, z5.d
; CHECK-NEXT: movprfx z16, z0 ; CHECK-NEXT: movprfx z16, z0
; CHECK-NEXT: lsr z16.d, p0/m, z16.d, z1.d ; CHECK-NEXT: lsr z16.d, p0/m, z16.d, z4.d
; CHECK-NEXT: ldr q7, [x8, :lo12:.LCPI22_9] ; CHECK-NEXT: movprfx z18, z0
; CHECK-NEXT: lslr z6.d, p0/m, z6.d, z0.d ; CHECK-NEXT: lsr z18.d, p0/m, z18.d, z6.d
; CHECK-NEXT: lslr z4.d, p0/m, z4.d, z0.d ; CHECK-NEXT: and z16.d, z16.d, z5.d
; CHECK-NEXT: lslr z2.d, p0/m, z2.d, z0.d ; CHECK-NEXT: and z18.d, z18.d, z17.d
; CHECK-NEXT: and z6.d, z6.d, z17.d ; CHECK-NEXT: and z17.d, z0.d, z17.d
; CHECK-NEXT: and z4.d, z4.d, z18.d ; CHECK-NEXT: and z5.d, z0.d, z5.d
; CHECK-NEXT: lslr z6.d, p0/m, z6.d, z17.d
; CHECK-NEXT: lslr z4.d, p0/m, z4.d, z5.d
; CHECK-NEXT: and z3.d, z0.d, z3.d
; CHECK-NEXT: lsl z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: lsl z0.d, p0/m, z0.d, z1.d
; CHECK-NEXT: and z1.d, z2.d, z7.d ; CHECK-NEXT: orr z16.d, z18.d, z16.d
; CHECK-NEXT: orr z3.d, z3.d, z16.d ; CHECK-NEXT: movprfx z1, z3
; CHECK-NEXT: lsl z1.d, p0/m, z1.d, z2.d
; CHECK-NEXT: orr z2.d, z4.d, z6.d ; CHECK-NEXT: orr z2.d, z4.d, z6.d
; CHECK-NEXT: orr z0.d, z0.d, z1.d ; CHECK-NEXT: orr z0.d, z0.d, z1.d
; CHECK-NEXT: orr z1.d, z5.d, z3.d ; CHECK-NEXT: orr z1.d, z16.d, z7.d
; CHECK-NEXT: orr z0.d, z0.d, z2.d ; CHECK-NEXT: orr z0.d, z0.d, z2.d
; CHECK-NEXT: orr z0.d, z0.d, z1.d ; CHECK-NEXT: orr z0.d, z0.d, z1.d
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <2 x i64> @llvm.bswap.v2i64(<2 x i64> %op) %res = call <2 x i64> @llvm.bswap.v2i64(<2 x i64> %op)
ret <2 x i64> %res ret <2 x i64> %res
} }
define void @bswap_v4i64(<4 x i64>* %a) #0 { define void @bswap_v4i64(<4 x i64>* %a) #0 {
; CHECK-LABEL: bswap_v4i64: ; CHECK-LABEL: bswap_v4i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI23_0 ; CHECK-NEXT: adrp x8, .LCPI23_0
; CHECK-NEXT: adrp x9, .LCPI23_1 ; CHECK-NEXT: adrp x9, .LCPI23_1
; CHECK-NEXT: adrp x10, .LCPI23_2 ; CHECK-NEXT: adrp x10, .LCPI23_3
; CHECK-NEXT: ptrue p0.d, vl2 ; CHECK-NEXT: ptrue p0.d, vl2
; CHECK-NEXT: ldp q0, q1, [x0] ; CHECK-NEXT: ldp q1, q2, [x0]
; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI23_0] ; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI23_0]
; CHECK-NEXT: adrp x8, .LCPI23_4 ; CHECK-NEXT: adrp x8, .LCPI23_2
; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI23_1] ; CHECK-NEXT: ldr q3, [x9, :lo12:.LCPI23_1]
; CHECK-NEXT: adrp x9, .LCPI23_3 ; CHECK-NEXT: adrp x9, .LCPI23_4
; CHECK-NEXT: ldr q4, [x10, :lo12:.LCPI23_2] ; CHECK-NEXT: ldr q5, [x10, :lo12:.LCPI23_3]
; CHECK-NEXT: adrp x10, .LCPI23_5 ; CHECK-NEXT: adrp x10, .LCPI23_6
; CHECK-NEXT: ldr q7, [x8, :lo12:.LCPI23_4] ; CHECK-NEXT: ldr q4, [x8, :lo12:.LCPI23_2]
; CHECK-NEXT: adrp x8, .LCPI23_6 ; CHECK-NEXT: adrp x8, .LCPI23_5
; CHECK-NEXT: ldr q5, [x9, :lo12:.LCPI23_3] ; CHECK-NEXT: ldr q6, [x9, :lo12:.LCPI23_4]
; CHECK-NEXT: adrp x9, .LCPI23_7 ; CHECK-NEXT: movprfx z16, z2
; CHECK-NEXT: movprfx z6, z1 ; CHECK-NEXT: lsr z16.d, p0/m, z16.d, z3.d
; CHECK-NEXT: lsr z6.d, p0/m, z6.d, z2.d ; CHECK-NEXT: ldr q17, [x10, :lo12:.LCPI23_6]
; CHECK-NEXT: movprfx z17, z1 ; CHECK-NEXT: movprfx z18, z2
; CHECK-NEXT: lsr z17.d, p0/m, z17.d, z3.d ; CHECK-NEXT: lsr z18.d, p0/m, z18.d, z0.d
; CHECK-NEXT: ldr q18, [x8, :lo12:.LCPI23_6] ; CHECK-NEXT: ldr q7, [x8, :lo12:.LCPI23_5]
; CHECK-NEXT: adrp x8, .LCPI23_8 ; CHECK-NEXT: movprfx z19, z2
; CHECK-NEXT: and z6.d, z6.d, z4.d
; CHECK-NEXT: ldr q16, [x10, :lo12:.LCPI23_5]
; CHECK-NEXT: orr z6.d, z6.d, z17.d
; CHECK-NEXT: ldr q17, [x9, :lo12:.LCPI23_7]
; CHECK-NEXT: ldr q21, [x8, :lo12:.LCPI23_8]
; CHECK-NEXT: adrp x8, .LCPI23_9
; CHECK-NEXT: movprfx z19, z1
; CHECK-NEXT: lsr z19.d, p0/m, z19.d, z5.d ; CHECK-NEXT: lsr z19.d, p0/m, z19.d, z5.d
; CHECK-NEXT: movprfx z20, z1 ; CHECK-NEXT: movprfx z20, z2
; CHECK-NEXT: lsr z20.d, p0/m, z20.d, z16.d ; CHECK-NEXT: lsr z20.d, p0/m, z20.d, z7.d
; CHECK-NEXT: and z19.d, z19.d, z7.d ; CHECK-NEXT: and z16.d, z16.d, z4.d
; CHECK-NEXT: and z20.d, z20.d, z18.d ; CHECK-NEXT: and z19.d, z19.d, z6.d
; CHECK-NEXT: orr z19.d, z20.d, z19.d
; CHECK-NEXT: movprfx z20, z1
; CHECK-NEXT: lsl z20.d, p0/m, z20.d, z16.d
; CHECK-NEXT: movprfx z22, z1
; CHECK-NEXT: lsl z22.d, p0/m, z22.d, z5.d
; CHECK-NEXT: ldr q23, [x8, :lo12:.LCPI23_9]
; CHECK-NEXT: and z20.d, z20.d, z17.d ; CHECK-NEXT: and z20.d, z20.d, z17.d
; CHECK-NEXT: and z22.d, z22.d, z21.d ; CHECK-NEXT: orr z16.d, z16.d, z18.d
; CHECK-NEXT: orr z6.d, z19.d, z6.d ; CHECK-NEXT: orr z18.d, z20.d, z19.d
; CHECK-NEXT: orr z19.d, z22.d, z20.d ; CHECK-NEXT: and z19.d, z2.d, z17.d
; CHECK-NEXT: and z20.d, z2.d, z6.d
; CHECK-NEXT: lsl z19.d, p0/m, z19.d, z7.d
; CHECK-NEXT: lsl z20.d, p0/m, z20.d, z5.d
; CHECK-NEXT: orr z16.d, z18.d, z16.d
; CHECK-NEXT: orr z18.d, z20.d, z19.d
; CHECK-NEXT: movprfx z19, z2
; CHECK-NEXT: lsl z19.d, p0/m, z19.d, z0.d
; CHECK-NEXT: and z2.d, z2.d, z4.d
; CHECK-NEXT: movprfx z20, z1
; CHECK-NEXT: lsr z20.d, p0/m, z20.d, z3.d
; CHECK-NEXT: lsl z2.d, p0/m, z2.d, z3.d
; CHECK-NEXT: movprfx z21, z1
; CHECK-NEXT: lsr z21.d, p0/m, z21.d, z0.d
; CHECK-NEXT: and z20.d, z20.d, z4.d
; CHECK-NEXT: orr z2.d, z19.d, z2.d
; CHECK-NEXT: orr z19.d, z20.d, z21.d
; CHECK-NEXT: movprfx z20, z1 ; CHECK-NEXT: movprfx z20, z1
; CHECK-NEXT: lsl z20.d, p0/m, z20.d, z3.d
; CHECK-NEXT: lsl z1.d, p0/m, z1.d, z2.d
; CHECK-NEXT: movprfx z22, z0
; CHECK-NEXT: lsr z22.d, p0/m, z22.d, z2.d
; CHECK-NEXT: and z1.d, z1.d, z23.d
; CHECK-NEXT: and z4.d, z22.d, z4.d
; CHECK-NEXT: movprfx z22, z0
; CHECK-NEXT: lsr z22.d, p0/m, z22.d, z3.d
; CHECK-NEXT: orr z1.d, z20.d, z1.d
; CHECK-NEXT: orr z4.d, z4.d, z22.d
; CHECK-NEXT: movprfx z20, z0
; CHECK-NEXT: lsr z20.d, p0/m, z20.d, z5.d ; CHECK-NEXT: lsr z20.d, p0/m, z20.d, z5.d
; CHECK-NEXT: movprfx z22, z0 ; CHECK-NEXT: movprfx z21, z1
; CHECK-NEXT: lsr z22.d, p0/m, z22.d, z16.d ; CHECK-NEXT: lsr z21.d, p0/m, z21.d, z7.d
; CHECK-NEXT: lslr z16.d, p0/m, z16.d, z0.d ; CHECK-NEXT: and z20.d, z20.d, z6.d
; CHECK-NEXT: lslr z5.d, p0/m, z5.d, z0.d ; CHECK-NEXT: and z21.d, z21.d, z17.d
; CHECK-NEXT: lslr z2.d, p0/m, z2.d, z0.d ; CHECK-NEXT: and z17.d, z1.d, z17.d
; CHECK-NEXT: and z7.d, z20.d, z7.d ; CHECK-NEXT: and z6.d, z1.d, z6.d
; CHECK-NEXT: and z18.d, z22.d, z18.d ; CHECK-NEXT: lslr z7.d, p0/m, z7.d, z17.d
; CHECK-NEXT: and z16.d, z16.d, z17.d ; CHECK-NEXT: lslr z5.d, p0/m, z5.d, z6.d
; CHECK-NEXT: and z5.d, z5.d, z21.d ; CHECK-NEXT: lslr z0.d, p0/m, z0.d, z1.d
; CHECK-NEXT: lsl z0.d, p0/m, z0.d, z3.d ; CHECK-NEXT: orr z20.d, z21.d, z20.d
; CHECK-NEXT: and z2.d, z2.d, z23.d ; CHECK-NEXT: and z4.d, z1.d, z4.d
; CHECK-NEXT: orr z7.d, z18.d, z7.d ; CHECK-NEXT: movprfx z1, z4
; CHECK-NEXT: orr z3.d, z5.d, z16.d ; CHECK-NEXT: lsl z1.d, p0/m, z1.d, z3.d
; CHECK-NEXT: orr z0.d, z0.d, z2.d ; CHECK-NEXT: orr z3.d, z5.d, z7.d
; CHECK-NEXT: orr z2.d, z7.d, z4.d ; CHECK-NEXT: orr z0.d, z0.d, z1.d
; CHECK-NEXT: orr z1.d, z20.d, z19.d
; CHECK-NEXT: orr z0.d, z0.d, z3.d ; CHECK-NEXT: orr z0.d, z0.d, z3.d
; CHECK-NEXT: orr z1.d, z1.d, z19.d ; CHECK-NEXT: orr z2.d, z2.d, z18.d
; CHECK-NEXT: orr z0.d, z0.d, z2.d ; CHECK-NEXT: orr z0.d, z0.d, z1.d
; CHECK-NEXT: orr z1.d, z1.d, z6.d ; CHECK-NEXT: orr z1.d, z2.d, z16.d
; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: stp q0, q1, [x0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%op = load <4 x i64>, <4 x i64>* %a %op = load <4 x i64>, <4 x i64>* %a
%res = call <4 x i64> @llvm.bswap.v4i64(<4 x i64> %op) %res = call <4 x i64> @llvm.bswap.v4i64(<4 x i64> %op)
store <4 x i64> %res, <4 x i64>* %a store <4 x i64> %res, <4 x i64>* %a
ret void ret void
} }
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llvm/test/CodeGen/ARM/load-combine-big-endian.ll

Show First 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
; i8* p; // p is 4 byte aligned ; i8* p; // p is 4 byte aligned
; (i32) p[0] | ((i32) p[1] << 8) | ((i32) p[2] << 16) | ((i32) p[3] << 24) ; (i32) p[0] | ((i32) p[1] << 8) | ((i32) p[2] << 16) | ((i32) p[3] << 24)
define i32 @load_i32_by_i8_bswap(i32* %arg) { define i32 @load_i32_by_i8_bswap(i32* %arg) {
; BSWAP is not supported by 32 bit target ; BSWAP is not supported by 32 bit target
; CHECK-LABEL: load_i32_by_i8_bswap: ; CHECK-LABEL: load_i32_by_i8_bswap:
; CHECK: @ %bb.0: ; CHECK: @ %bb.0:
; CHECK-NEXT: ldr r0, [r0] ; CHECK-NEXT: ldr r0, [r0]
; CHECK-NEXT: mov r1, #65280 ; CHECK-NEXT: mov r1, #65280
; CHECK-NEXT: mov r2, #16711680 ; CHECK-NEXT: and r2, r0, #65280
; CHECK-NEXT: and r1, r1, r0, lsr #8 ; CHECK-NEXT: and r1, r1, r0, lsr #8
; CHECK-NEXT: and r2, r2, r0, lsl #8
; CHECK-NEXT: orr r1, r1, r0, lsr #24 ; CHECK-NEXT: orr r1, r1, r0, lsr #24
; CHECK-NEXT: orr r0, r2, r0, lsl #24 ; CHECK-NEXT: lsl r0, r0, #24
; CHECK-NEXT: orr r0, r0, r2, lsl #8
; CHECK-NEXT: orr r0, r0, r1 ; CHECK-NEXT: orr r0, r0, r1
; CHECK-NEXT: mov pc, lr ; CHECK-NEXT: mov pc, lr
; ;
; CHECK-ARMv6-LABEL: load_i32_by_i8_bswap: ; CHECK-ARMv6-LABEL: load_i32_by_i8_bswap:
; CHECK-ARMv6: @ %bb.0: ; CHECK-ARMv6: @ %bb.0:
; CHECK-ARMv6-NEXT: ldr r0, [r0] ; CHECK-ARMv6-NEXT: ldr r0, [r0]
; CHECK-ARMv6-NEXT: rev r0, r0 ; CHECK-ARMv6-NEXT: rev r0, r0
; CHECK-ARMv6-NEXT: bx lr ; CHECK-ARMv6-NEXT: bx lr
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ret i32 %tmp13 ret i32 %tmp13
} }
; i8* p; // p is 8 byte aligned ; i8* p; // p is 8 byte aligned
; (i64) p[0] | ((i64) p[1] << 8) | ((i64) p[2] << 16) | ((i64) p[3] << 24) | ((i64) p[4] << 32) | ((i64) p[5] << 40) | ((i64) p[6] << 48) | ((i64) p[7] << 56) ; (i64) p[0] | ((i64) p[1] << 8) | ((i64) p[2] << 16) | ((i64) p[3] << 24) | ((i64) p[4] << 32) | ((i64) p[5] << 40) | ((i64) p[6] << 48) | ((i64) p[7] << 56)
define i64 @load_i64_by_i8_bswap(i64* %arg) { define i64 @load_i64_by_i8_bswap(i64* %arg) {
; CHECK-LABEL: load_i64_by_i8_bswap: ; CHECK-LABEL: load_i64_by_i8_bswap:
; CHECK: @ %bb.0: ; CHECK: @ %bb.0:
; CHECK-NEXT: push {r11, lr}
; CHECK-NEXT: ldr r1, [r0] ; CHECK-NEXT: ldr r1, [r0]
; CHECK-NEXT: mov r12, #65280 ; CHECK-NEXT: mov r12, #65280
; CHECK-NEXT: ldr r0, [r0, #4] ; CHECK-NEXT: ldr r0, [r0, #4]
; CHECK-NEXT: mov lr, #16711680 ; CHECK-NEXT: and r2, r0, #65280
; CHECK-NEXT: and r3, r12, r0, lsr #8 ; CHECK-NEXT: and r3, r12, r0, lsr #8
; CHECK-NEXT: and r2, lr, r0, lsl #8
; CHECK-NEXT: orr r3, r3, r0, lsr #24 ; CHECK-NEXT: orr r3, r3, r0, lsr #24
; CHECK-NEXT: orr r0, r2, r0, lsl #24 ; CHECK-NEXT: lsl r0, r0, #24
; CHECK-NEXT: orr r0, r0, r2, lsl #8
; CHECK-NEXT: and r2, r12, r1, lsr #8 ; CHECK-NEXT: and r2, r12, r1, lsr #8
; CHECK-NEXT: orr r0, r0, r3 ; CHECK-NEXT: orr r0, r0, r3
; CHECK-NEXT: and r3, lr, r1, lsl #8 ; CHECK-NEXT: and r3, r1, #65280
; CHECK-NEXT: orr r2, r2, r1, lsr #24 ; CHECK-NEXT: orr r2, r2, r1, lsr #24
; CHECK-NEXT: orr r1, r3, r1, lsl #24 ; CHECK-NEXT: lsl r1, r1, #24
; CHECK-NEXT: orr r1, r1, r3, lsl #8
; CHECK-NEXT: orr r1, r1, r2 ; CHECK-NEXT: orr r1, r1, r2
; CHECK-NEXT: pop {r11, lr}
; CHECK-NEXT: mov pc, lr ; CHECK-NEXT: mov pc, lr
; ;
; CHECK-ARMv6-LABEL: load_i64_by_i8_bswap: ; CHECK-ARMv6-LABEL: load_i64_by_i8_bswap:
; CHECK-ARMv6: @ %bb.0: ; CHECK-ARMv6: @ %bb.0:
; CHECK-ARMv6-NEXT: ldrd r2, r3, [r0] ; CHECK-ARMv6-NEXT: ldrd r2, r3, [r0]
; CHECK-ARMv6-NEXT: rev r0, r3 ; CHECK-ARMv6-NEXT: rev r0, r3
; CHECK-ARMv6-NEXT: rev r1, r2 ; CHECK-ARMv6-NEXT: rev r1, r2
; CHECK-ARMv6-NEXT: bx lr ; CHECK-ARMv6-NEXT: bx lr
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; i8* p; // p[1] is 4 byte aligned ; i8* p; // p[1] is 4 byte aligned
; (i32) p[1] | ((i32) p[2] << 8) | ((i32) p[3] << 16) | ((i32) p[4] << 24) ; (i32) p[1] | ((i32) p[2] << 8) | ((i32) p[3] << 16) | ((i32) p[4] << 24)
define i32 @load_i32_by_i8_nonzero_offset(i32* %arg) { define i32 @load_i32_by_i8_nonzero_offset(i32* %arg) {
; CHECK-LABEL: load_i32_by_i8_nonzero_offset: ; CHECK-LABEL: load_i32_by_i8_nonzero_offset:
; CHECK: @ %bb.0: ; CHECK: @ %bb.0:
; CHECK-NEXT: ldr r0, [r0, #1] ; CHECK-NEXT: ldr r0, [r0, #1]
; CHECK-NEXT: mov r1, #65280 ; CHECK-NEXT: mov r1, #65280
; CHECK-NEXT: mov r2, #16711680 ; CHECK-NEXT: and r2, r0, #65280
; CHECK-NEXT: and r1, r1, r0, lsr #8 ; CHECK-NEXT: and r1, r1, r0, lsr #8
; CHECK-NEXT: and r2, r2, r0, lsl #8
; CHECK-NEXT: orr r1, r1, r0, lsr #24 ; CHECK-NEXT: orr r1, r1, r0, lsr #24
; CHECK-NEXT: orr r0, r2, r0, lsl #24 ; CHECK-NEXT: lsl r0, r0, #24
; CHECK-NEXT: orr r0, r0, r2, lsl #8
; CHECK-NEXT: orr r0, r0, r1 ; CHECK-NEXT: orr r0, r0, r1
; CHECK-NEXT: mov pc, lr ; CHECK-NEXT: mov pc, lr
; ;
; CHECK-ARMv6-LABEL: load_i32_by_i8_nonzero_offset: ; CHECK-ARMv6-LABEL: load_i32_by_i8_nonzero_offset:
; CHECK-ARMv6: @ %bb.0: ; CHECK-ARMv6: @ %bb.0:
; CHECK-ARMv6-NEXT: ldr r0, [r0, #1] ; CHECK-ARMv6-NEXT: ldr r0, [r0, #1]
; CHECK-ARMv6-NEXT: rev r0, r0 ; CHECK-ARMv6-NEXT: rev r0, r0
; CHECK-ARMv6-NEXT: bx lr ; CHECK-ARMv6-NEXT: bx lr
Show All 37 Lines
; i8* p; // p[-4] is 4 byte aligned ; i8* p; // p[-4] is 4 byte aligned
; (i32) p[-4] | ((i32) p[-3] << 8) | ((i32) p[-2] << 16) | ((i32) p[-1] << 24) ; (i32) p[-4] | ((i32) p[-3] << 8) | ((i32) p[-2] << 16) | ((i32) p[-1] << 24)
define i32 @load_i32_by_i8_neg_offset(i32* %arg) { define i32 @load_i32_by_i8_neg_offset(i32* %arg) {
; CHECK-LABEL: load_i32_by_i8_neg_offset: ; CHECK-LABEL: load_i32_by_i8_neg_offset:
; CHECK: @ %bb.0: ; CHECK: @ %bb.0:
; CHECK-NEXT: ldr r0, [r0, #-4] ; CHECK-NEXT: ldr r0, [r0, #-4]
; CHECK-NEXT: mov r1, #65280 ; CHECK-NEXT: mov r1, #65280
; CHECK-NEXT: mov r2, #16711680 ; CHECK-NEXT: and r2, r0, #65280
; CHECK-NEXT: and r1, r1, r0, lsr #8 ; CHECK-NEXT: and r1, r1, r0, lsr #8
; CHECK-NEXT: and r2, r2, r0, lsl #8
; CHECK-NEXT: orr r1, r1, r0, lsr #24 ; CHECK-NEXT: orr r1, r1, r0, lsr #24
; CHECK-NEXT: orr r0, r2, r0, lsl #24 ; CHECK-NEXT: lsl r0, r0, #24
; CHECK-NEXT: orr r0, r0, r2, lsl #8
; CHECK-NEXT: orr r0, r0, r1 ; CHECK-NEXT: orr r0, r0, r1
; CHECK-NEXT: mov pc, lr ; CHECK-NEXT: mov pc, lr
; ;
; CHECK-ARMv6-LABEL: load_i32_by_i8_neg_offset: ; CHECK-ARMv6-LABEL: load_i32_by_i8_neg_offset:
; CHECK-ARMv6: @ %bb.0: ; CHECK-ARMv6: @ %bb.0:
; CHECK-ARMv6-NEXT: ldr r0, [r0, #-4] ; CHECK-ARMv6-NEXT: ldr r0, [r0, #-4]
; CHECK-ARMv6-NEXT: rev r0, r0 ; CHECK-ARMv6-NEXT: rev r0, r0
; CHECK-ARMv6-NEXT: bx lr ; CHECK-ARMv6-NEXT: bx lr
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; i16* p; // p is 4 byte aligned ; i16* p; // p is 4 byte aligned
; (i32) bswap(p[0]) | (i32) bswap(p[1] << 16) ; (i32) bswap(p[0]) | (i32) bswap(p[1] << 16)
define i32 @load_i32_by_bswap_i16(i32* %arg) { define i32 @load_i32_by_bswap_i16(i32* %arg) {
; CHECK-LABEL: load_i32_by_bswap_i16: ; CHECK-LABEL: load_i32_by_bswap_i16:
; CHECK: @ %bb.0: ; CHECK: @ %bb.0:
; CHECK-NEXT: ldr r0, [r0] ; CHECK-NEXT: ldr r0, [r0]
; CHECK-NEXT: mov r1, #65280 ; CHECK-NEXT: mov r1, #65280
; CHECK-NEXT: mov r2, #16711680 ; CHECK-NEXT: and r2, r0, #65280
; CHECK-NEXT: and r1, r1, r0, lsr #8 ; CHECK-NEXT: and r1, r1, r0, lsr #8
; CHECK-NEXT: and r2, r2, r0, lsl #8
; CHECK-NEXT: orr r1, r1, r0, lsr #24 ; CHECK-NEXT: orr r1, r1, r0, lsr #24
; CHECK-NEXT: orr r0, r2, r0, lsl #24 ; CHECK-NEXT: lsl r0, r0, #24
; CHECK-NEXT: orr r0, r0, r2, lsl #8
; CHECK-NEXT: orr r0, r0, r1 ; CHECK-NEXT: orr r0, r0, r1
; CHECK-NEXT: mov pc, lr ; CHECK-NEXT: mov pc, lr
; ;
; CHECK-ARMv6-LABEL: load_i32_by_bswap_i16: ; CHECK-ARMv6-LABEL: load_i32_by_bswap_i16:
; CHECK-ARMv6: @ %bb.0: ; CHECK-ARMv6: @ %bb.0:
; CHECK-ARMv6-NEXT: ldr r0, [r0] ; CHECK-ARMv6-NEXT: ldr r0, [r0]
; CHECK-ARMv6-NEXT: rev r0, r0 ; CHECK-ARMv6-NEXT: rev r0, r0
; CHECK-ARMv6-NEXT: bx lr ; CHECK-ARMv6-NEXT: bx lr
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; i8* arg; i32 i; ; i8* arg; i32 i;
; p = arg + 12; ; p = arg + 12;
; (i32) p[i] | ((i32) p[i + 1] << 8) | ((i32) p[i + 2] << 16) | ((i32) p[i + 3] << 24) ; (i32) p[i] | ((i32) p[i + 1] << 8) | ((i32) p[i + 2] << 16) | ((i32) p[i + 3] << 24)
define i32 @load_i32_by_i8_base_offset_index(i8* %arg, i32 %i) { define i32 @load_i32_by_i8_base_offset_index(i8* %arg, i32 %i) {
; CHECK-LABEL: load_i32_by_i8_base_offset_index: ; CHECK-LABEL: load_i32_by_i8_base_offset_index:
; CHECK: @ %bb.0: ; CHECK: @ %bb.0:
; CHECK-NEXT: add r0, r0, r1 ; CHECK-NEXT: add r0, r0, r1
; CHECK-NEXT: mov r1, #65280 ; CHECK-NEXT: mov r1, #65280
; CHECK-NEXT: mov r2, #16711680
; CHECK-NEXT: ldr r0, [r0, #12] ; CHECK-NEXT: ldr r0, [r0, #12]
; CHECK-NEXT: and r2, r0, #65280
; CHECK-NEXT: and r1, r1, r0, lsr #8 ; CHECK-NEXT: and r1, r1, r0, lsr #8
; CHECK-NEXT: and r2, r2, r0, lsl #8
; CHECK-NEXT: orr r1, r1, r0, lsr #24 ; CHECK-NEXT: orr r1, r1, r0, lsr #24
; CHECK-NEXT: orr r0, r2, r0, lsl #24 ; CHECK-NEXT: lsl r0, r0, #24
; CHECK-NEXT: orr r0, r0, r2, lsl #8
; CHECK-NEXT: orr r0, r0, r1 ; CHECK-NEXT: orr r0, r0, r1
; CHECK-NEXT: mov pc, lr ; CHECK-NEXT: mov pc, lr
; ;
; CHECK-ARMv6-LABEL: load_i32_by_i8_base_offset_index: ; CHECK-ARMv6-LABEL: load_i32_by_i8_base_offset_index:
; CHECK-ARMv6: @ %bb.0: ; CHECK-ARMv6: @ %bb.0:
; CHECK-ARMv6-NEXT: add r0, r0, r1 ; CHECK-ARMv6-NEXT: add r0, r0, r1
; CHECK-ARMv6-NEXT: ldr r0, [r0, #12] ; CHECK-ARMv6-NEXT: ldr r0, [r0, #12]
; CHECK-ARMv6-NEXT: rev r0, r0 ; CHECK-ARMv6-NEXT: rev r0, r0
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; i8* arg; i32 i; ; i8* arg; i32 i;
; p = arg + 12; ; p = arg + 12;
; (i32) p[i + 1] | ((i32) p[i + 2] << 8) | ((i32) p[i + 3] << 16) | ((i32) p[i + 4] << 24) ; (i32) p[i + 1] | ((i32) p[i + 2] << 8) | ((i32) p[i + 3] << 16) | ((i32) p[i + 4] << 24)
define i32 @load_i32_by_i8_base_offset_index_2(i8* %arg, i32 %i) { define i32 @load_i32_by_i8_base_offset_index_2(i8* %arg, i32 %i) {
; CHECK-LABEL: load_i32_by_i8_base_offset_index_2: ; CHECK-LABEL: load_i32_by_i8_base_offset_index_2:
; CHECK: @ %bb.0: ; CHECK: @ %bb.0:
; CHECK-NEXT: add r0, r1, r0 ; CHECK-NEXT: add r0, r1, r0
; CHECK-NEXT: mov r1, #65280 ; CHECK-NEXT: mov r1, #65280
; CHECK-NEXT: mov r2, #16711680
; CHECK-NEXT: ldr r0, [r0, #13] ; CHECK-NEXT: ldr r0, [r0, #13]
; CHECK-NEXT: and r2, r0, #65280
; CHECK-NEXT: and r1, r1, r0, lsr #8 ; CHECK-NEXT: and r1, r1, r0, lsr #8
; CHECK-NEXT: and r2, r2, r0, lsl #8
; CHECK-NEXT: orr r1, r1, r0, lsr #24 ; CHECK-NEXT: orr r1, r1, r0, lsr #24
; CHECK-NEXT: orr r0, r2, r0, lsl #24 ; CHECK-NEXT: lsl r0, r0, #24
; CHECK-NEXT: orr r0, r0, r2, lsl #8
; CHECK-NEXT: orr r0, r0, r1 ; CHECK-NEXT: orr r0, r0, r1
; CHECK-NEXT: mov pc, lr ; CHECK-NEXT: mov pc, lr
; ;
; CHECK-ARMv6-LABEL: load_i32_by_i8_base_offset_index_2: ; CHECK-ARMv6-LABEL: load_i32_by_i8_base_offset_index_2:
; CHECK-ARMv6: @ %bb.0: ; CHECK-ARMv6: @ %bb.0:
; CHECK-ARMv6-NEXT: add r0, r1, r0 ; CHECK-ARMv6-NEXT: add r0, r1, r0
; CHECK-ARMv6-NEXT: ldr r0, [r0, #13] ; CHECK-ARMv6-NEXT: ldr r0, [r0, #13]
; CHECK-ARMv6-NEXT: rev r0, r0 ; CHECK-ARMv6-NEXT: rev r0, r0
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llvm/test/CodeGen/ARM/load-combine.ll

Show First 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; i8* p; // p is 4 byte aligned ; i8* p; // p is 4 byte aligned
; ((i32) p[0] << 24) | ((i32) p[1] << 16) | ((i32) p[2] << 8) | (i32) p[3] ; ((i32) p[0] << 24) | ((i32) p[1] << 16) | ((i32) p[2] << 8) | (i32) p[3]
define i32 @load_i32_by_i8_bswap(i32* %arg) { define i32 @load_i32_by_i8_bswap(i32* %arg) {
; BSWAP is not supported by 32 bit target ; BSWAP is not supported by 32 bit target
; CHECK-LABEL: load_i32_by_i8_bswap: ; CHECK-LABEL: load_i32_by_i8_bswap:
; CHECK: @ %bb.0: ; CHECK: @ %bb.0:
; CHECK-NEXT: ldr r0, [r0] ; CHECK-NEXT: ldr r0, [r0]
; CHECK-NEXT: mov r1, #65280 ; CHECK-NEXT: mov r1, #65280
; CHECK-NEXT: mov r2, #16711680 ; CHECK-NEXT: and r2, r0, #65280
; CHECK-NEXT: and r1, r1, r0, lsr #8 ; CHECK-NEXT: and r1, r1, r0, lsr #8
; CHECK-NEXT: and r2, r2, r0, lsl #8
; CHECK-NEXT: orr r1, r1, r0, lsr #24 ; CHECK-NEXT: orr r1, r1, r0, lsr #24
; CHECK-NEXT: orr r0, r2, r0, lsl #24 ; CHECK-NEXT: lsl r0, r0, #24
; CHECK-NEXT: orr r0, r0, r2, lsl #8
; CHECK-NEXT: orr r0, r0, r1 ; CHECK-NEXT: orr r0, r0, r1
; CHECK-NEXT: mov pc, lr ; CHECK-NEXT: mov pc, lr
; ;
; CHECK-ARMv6-LABEL: load_i32_by_i8_bswap: ; CHECK-ARMv6-LABEL: load_i32_by_i8_bswap:
; CHECK-ARMv6: @ %bb.0: ; CHECK-ARMv6: @ %bb.0:
; CHECK-ARMv6-NEXT: ldr r0, [r0] ; CHECK-ARMv6-NEXT: ldr r0, [r0]
; CHECK-ARMv6-NEXT: rev r0, r0 ; CHECK-ARMv6-NEXT: rev r0, r0
; CHECK-ARMv6-NEXT: bx lr ; CHECK-ARMv6-NEXT: bx lr
▲ Show 20 Lines • Show All 99 Lines • ▼ Show 20 Lines; CHECK-THUMBv7-NEXT: bx lr
ret i64 %tmp37 ret i64 %tmp37
} }
; i8* p; // p is 8 byte aligned ; i8* p; // p is 8 byte aligned
; ((i64) p[0] << 56) | ((i64) p[1] << 48) | ((i64) p[2] << 40) | ((i64) p[3] << 32) | ((i64) p[4] << 24) | ((i64) p[5] << 16) | ((i64) p[6] << 8) | (i64) p[7] ; ((i64) p[0] << 56) | ((i64) p[1] << 48) | ((i64) p[2] << 40) | ((i64) p[3] << 32) | ((i64) p[4] << 24) | ((i64) p[5] << 16) | ((i64) p[6] << 8) | (i64) p[7]
define i64 @load_i64_by_i8_bswap(i64* %arg) { define i64 @load_i64_by_i8_bswap(i64* %arg) {
; CHECK-LABEL: load_i64_by_i8_bswap: ; CHECK-LABEL: load_i64_by_i8_bswap:
; CHECK: @ %bb.0: ; CHECK: @ %bb.0:
; CHECK-NEXT: push {r11, lr}
; CHECK-NEXT: ldr r1, [r0] ; CHECK-NEXT: ldr r1, [r0]
; CHECK-NEXT: mov r12, #65280 ; CHECK-NEXT: mov r12, #65280
; CHECK-NEXT: ldr r0, [r0, #4] ; CHECK-NEXT: ldr r0, [r0, #4]
; CHECK-NEXT: mov lr, #16711680 ; CHECK-NEXT: and r2, r0, #65280
; CHECK-NEXT: and r3, r12, r0, lsr #8 ; CHECK-NEXT: and r3, r12, r0, lsr #8
; CHECK-NEXT: and r2, lr, r0, lsl #8
; CHECK-NEXT: orr r3, r3, r0, lsr #24 ; CHECK-NEXT: orr r3, r3, r0, lsr #24
; CHECK-NEXT: orr r0, r2, r0, lsl #24 ; CHECK-NEXT: lsl r0, r0, #24
; CHECK-NEXT: orr r0, r0, r2, lsl #8
; CHECK-NEXT: and r2, r12, r1, lsr #8 ; CHECK-NEXT: and r2, r12, r1, lsr #8
; CHECK-NEXT: orr r0, r0, r3 ; CHECK-NEXT: orr r0, r0, r3
; CHECK-NEXT: and r3, lr, r1, lsl #8 ; CHECK-NEXT: and r3, r1, #65280
; CHECK-NEXT: orr r2, r2, r1, lsr #24 ; CHECK-NEXT: orr r2, r2, r1, lsr #24
; CHECK-NEXT: orr r1, r3, r1, lsl #24 ; CHECK-NEXT: lsl r1, r1, #24
; CHECK-NEXT: orr r1, r1, r3, lsl #8
; CHECK-NEXT: orr r1, r1, r2 ; CHECK-NEXT: orr r1, r1, r2
; CHECK-NEXT: pop {r11, lr}
; CHECK-NEXT: mov pc, lr ; CHECK-NEXT: mov pc, lr
; ;
; CHECK-ARMv6-LABEL: load_i64_by_i8_bswap: ; CHECK-ARMv6-LABEL: load_i64_by_i8_bswap:
; CHECK-ARMv6: @ %bb.0: ; CHECK-ARMv6: @ %bb.0:
; CHECK-ARMv6-NEXT: ldrd r2, r3, [r0] ; CHECK-ARMv6-NEXT: ldrd r2, r3, [r0]
; CHECK-ARMv6-NEXT: rev r0, r3 ; CHECK-ARMv6-NEXT: rev r0, r3
; CHECK-ARMv6-NEXT: rev r1, r2 ; CHECK-ARMv6-NEXT: rev r1, r2
; CHECK-ARMv6-NEXT: bx lr ; CHECK-ARMv6-NEXT: bx lr
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; i8* p; // p[1] is 4 byte aligned ; i8* p; // p[1] is 4 byte aligned
; (i32) p[4] | ((i32) p[3] << 8) | ((i32) p[2] << 16) | ((i32) p[1] << 24) ; (i32) p[4] | ((i32) p[3] << 8) | ((i32) p[2] << 16) | ((i32) p[1] << 24)
define i32 @load_i32_by_i8_nonzero_offset_bswap(i32* %arg) { define i32 @load_i32_by_i8_nonzero_offset_bswap(i32* %arg) {
; CHECK-LABEL: load_i32_by_i8_nonzero_offset_bswap: ; CHECK-LABEL: load_i32_by_i8_nonzero_offset_bswap:
; CHECK: @ %bb.0: ; CHECK: @ %bb.0:
; CHECK-NEXT: ldr r0, [r0, #1] ; CHECK-NEXT: ldr r0, [r0, #1]
; CHECK-NEXT: mov r1, #65280 ; CHECK-NEXT: mov r1, #65280
; CHECK-NEXT: mov r2, #16711680 ; CHECK-NEXT: and r2, r0, #65280
; CHECK-NEXT: and r1, r1, r0, lsr #8 ; CHECK-NEXT: and r1, r1, r0, lsr #8
; CHECK-NEXT: and r2, r2, r0, lsl #8
; CHECK-NEXT: orr r1, r1, r0, lsr #24 ; CHECK-NEXT: orr r1, r1, r0, lsr #24
; CHECK-NEXT: orr r0, r2, r0, lsl #24 ; CHECK-NEXT: lsl r0, r0, #24
; CHECK-NEXT: orr r0, r0, r2, lsl #8
; CHECK-NEXT: orr r0, r0, r1 ; CHECK-NEXT: orr r0, r0, r1
; CHECK-NEXT: mov pc, lr ; CHECK-NEXT: mov pc, lr
; ;
; CHECK-ARMv6-LABEL: load_i32_by_i8_nonzero_offset_bswap: ; CHECK-ARMv6-LABEL: load_i32_by_i8_nonzero_offset_bswap:
; CHECK-ARMv6: @ %bb.0: ; CHECK-ARMv6: @ %bb.0:
; CHECK-ARMv6-NEXT: ldr r0, [r0, #1] ; CHECK-ARMv6-NEXT: ldr r0, [r0, #1]
; CHECK-ARMv6-NEXT: rev r0, r0 ; CHECK-ARMv6-NEXT: rev r0, r0
; CHECK-ARMv6-NEXT: bx lr ; CHECK-ARMv6-NEXT: bx lr
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; i8* p; // p[-4] is 4 byte aligned ; i8* p; // p[-4] is 4 byte aligned
; (i32) p[-1] | ((i32) p[-2] << 8) | ((i32) p[-3] << 16) | ((i32) p[-4] << 24) ; (i32) p[-1] | ((i32) p[-2] << 8) | ((i32) p[-3] << 16) | ((i32) p[-4] << 24)
define i32 @load_i32_by_i8_neg_offset_bswap(i32* %arg) { define i32 @load_i32_by_i8_neg_offset_bswap(i32* %arg) {
; CHECK-LABEL: load_i32_by_i8_neg_offset_bswap: ; CHECK-LABEL: load_i32_by_i8_neg_offset_bswap:
; CHECK: @ %bb.0: ; CHECK: @ %bb.0:
; CHECK-NEXT: ldr r0, [r0, #-4] ; CHECK-NEXT: ldr r0, [r0, #-4]
; CHECK-NEXT: mov r1, #65280 ; CHECK-NEXT: mov r1, #65280
; CHECK-NEXT: mov r2, #16711680 ; CHECK-NEXT: and r2, r0, #65280
; CHECK-NEXT: and r1, r1, r0, lsr #8 ; CHECK-NEXT: and r1, r1, r0, lsr #8
; CHECK-NEXT: and r2, r2, r0, lsl #8
; CHECK-NEXT: orr r1, r1, r0, lsr #24 ; CHECK-NEXT: orr r1, r1, r0, lsr #24
; CHECK-NEXT: orr r0, r2, r0, lsl #24 ; CHECK-NEXT: lsl r0, r0, #24
; CHECK-NEXT: orr r0, r0, r2, lsl #8
; CHECK-NEXT: orr r0, r0, r1 ; CHECK-NEXT: orr r0, r0, r1
; CHECK-NEXT: mov pc, lr ; CHECK-NEXT: mov pc, lr
; ;
; CHECK-ARMv6-LABEL: load_i32_by_i8_neg_offset_bswap: ; CHECK-ARMv6-LABEL: load_i32_by_i8_neg_offset_bswap:
; CHECK-ARMv6: @ %bb.0: ; CHECK-ARMv6: @ %bb.0:
; CHECK-ARMv6-NEXT: ldr r0, [r0, #-4] ; CHECK-ARMv6-NEXT: ldr r0, [r0, #-4]
; CHECK-ARMv6-NEXT: rev r0, r0 ; CHECK-ARMv6-NEXT: rev r0, r0
; CHECK-ARMv6-NEXT: bx lr ; CHECK-ARMv6-NEXT: bx lr
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; i16* p; // p is 4 byte aligned ; i16* p; // p is 4 byte aligned
; (i32) bswap(p[1]) | (i32) bswap(p[0] << 16) ; (i32) bswap(p[1]) | (i32) bswap(p[0] << 16)
define i32 @load_i32_by_bswap_i16(i32* %arg) { define i32 @load_i32_by_bswap_i16(i32* %arg) {
; CHECK-LABEL: load_i32_by_bswap_i16: ; CHECK-LABEL: load_i32_by_bswap_i16:
; CHECK: @ %bb.0: ; CHECK: @ %bb.0:
; CHECK-NEXT: ldr r0, [r0] ; CHECK-NEXT: ldr r0, [r0]
; CHECK-NEXT: mov r1, #65280 ; CHECK-NEXT: mov r1, #65280
; CHECK-NEXT: mov r2, #16711680 ; CHECK-NEXT: and r2, r0, #65280
; CHECK-NEXT: and r1, r1, r0, lsr #8 ; CHECK-NEXT: and r1, r1, r0, lsr #8
; CHECK-NEXT: and r2, r2, r0, lsl #8
; CHECK-NEXT: orr r1, r1, r0, lsr #24 ; CHECK-NEXT: orr r1, r1, r0, lsr #24
; CHECK-NEXT: orr r0, r2, r0, lsl #24 ; CHECK-NEXT: lsl r0, r0, #24
; CHECK-NEXT: orr r0, r0, r2, lsl #8
; CHECK-NEXT: orr r0, r0, r1 ; CHECK-NEXT: orr r0, r0, r1
; CHECK-NEXT: mov pc, lr ; CHECK-NEXT: mov pc, lr
; ;
; CHECK-ARMv6-LABEL: load_i32_by_bswap_i16: ; CHECK-ARMv6-LABEL: load_i32_by_bswap_i16:
; CHECK-ARMv6: @ %bb.0: ; CHECK-ARMv6: @ %bb.0:
; CHECK-ARMv6-NEXT: ldr r0, [r0] ; CHECK-ARMv6-NEXT: ldr r0, [r0]
; CHECK-ARMv6-NEXT: rev r0, r0 ; CHECK-ARMv6-NEXT: rev r0, r0
; CHECK-ARMv6-NEXT: bx lr ; CHECK-ARMv6-NEXT: bx lr
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llvm/test/CodeGen/Mips/bswap.ll

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; MM: rotr ${{[0-9]+}}, $[[R0]], 16 ; MM: rotr ${{[0-9]+}}, $[[R0]], 16
; MIPS64-LABEL: bswap32: ; MIPS64-LABEL: bswap32:
; MIPS64: wsbh $[[R0:[0-9]+]] ; MIPS64: wsbh $[[R0:[0-9]+]]
; MIPS64: rotr ${{[0-9]+}}, $[[R0]], 16 ; MIPS64: rotr ${{[0-9]+}}, $[[R0]], 16
; MIPS16-LABEL: bswap32: ; MIPS16-LABEL: bswap32:
; MIPS16-DAG: srl $[[R0:[0-9]+]], $4, 8 ; MIPS16-DAG: srl $[[R0:[0-9]+]], $4, 8
; MIPS16-DAG: li $[[R4:[0-9]+]], 65280
; MIPS16-DAG: and $[[R0]], $[[R4]]
; MIPS16-DAG: srl $[[R1:[0-9]+]], $4, 24 ; MIPS16-DAG: srl $[[R1:[0-9]+]], $4, 24
; MIPS16-DAG: sll $[[R2:[0-9]+]], $4, 8 ; MIPS16-DAG: or $[[R1]], $[[R0]]
; MIPS16-DAG: and $[[R4]], $4
; MIPS16-DAG: sll $[[R2:[0-9]+]], $[[R4]], 8
; MIPS16-DAG: sll $[[R3:[0-9]+]], $4, 24 ; MIPS16-DAG: sll $[[R3:[0-9]+]], $4, 24
; MIPS16-DAG: li $[[R4:[0-9]+]], 65280 ; MIPS16-DAG: or $[[R3]], $[[R2]]
; MIPS16-DAG: and $[[R4]], $[[R0]]
; MIPS16-DAG: or $[[R1]], $[[R4]]
; MIPS16-DAG: lw $[[R7:[0-9]+]], $CPI
; MIPS16-DAG: and $[[R7]], $[[R2]]
; MIPS16-DAG: or $[[R3]], $[[R7]]
; MIPS16-DAG: or $[[R3]], $[[R1]] ; MIPS16-DAG: or $[[R3]], $[[R1]]
%or.3 = call i32 @llvm.bswap.i32(i32 %x) %or.3 = call i32 @llvm.bswap.i32(i32 %x)
ret i32 %or.3 ret i32 %or.3
} }
define i64 @bswap64(i64 signext %x) nounwind readnone { define i64 @bswap64(i64 signext %x) nounwind readnone {
entry: entry:
; MIPS32-LABEL: bswap64: ; MIPS32-LABEL: bswap64:
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; MM: rotr ${{[0-9]+}}, $[[R0]], 16 ; MM: rotr ${{[0-9]+}}, $[[R0]], 16
; MIPS64-LABEL: bswap64: ; MIPS64-LABEL: bswap64:
; MIPS64: dsbh $[[R0:[0-9]+]] ; MIPS64: dsbh $[[R0:[0-9]+]]
; MIPS64: dshd ${{[0-9]+}}, $[[R0]] ; MIPS64: dshd ${{[0-9]+}}, $[[R0]]
; MIPS16-LABEL: bswap64: ; MIPS16-LABEL: bswap64:
; MIPS16-DAG: srl $[[R0:[0-9]+]], $5, 8 ; MIPS16-DAG: srl $[[R0:[0-9]+]], $5, 8
; MIPS16-DAG: srl $[[R1:[0-9]+]], $5, 24
; MIPS16-DAG: sll $[[R2:[0-9]+]], $5, 8
; MIPS16-DAG: sll $[[R3:[0-9]+]], $5, 24
; MIPS16-DAG: li $[[R4:[0-9]+]], 65280 ; MIPS16-DAG: li $[[R4:[0-9]+]], 65280
; MIPS16-DAG: and $[[R0]], $[[R4]] ; MIPS16-DAG: and $[[R0]], $[[R4]]
; MIPS16-DAG: srl $[[R1:[0-9]+]], $5, 24
; MIPS16-DAG: or $[[R1]], $[[R0]] ; MIPS16-DAG: or $[[R1]], $[[R0]]
; MIPS16-DAG: lw $[[R7:[0-9]+]], 1f ; MIPS16-DAG: sll $[[R3:[0-9]+]], $5, 24
; MIPS16-DAG: and $[[R2]], $[[R7]] ; MIPS16-DAG: and $5, $[[R4]]
; MIPS16-DAG: or $[[R3]], $[[R2]] ; MIPS16-DAG: sll $[[R2:[0-9]+]], $5, 8
; MIPS16-DAG: or $[[R3]], $[[R1]] ; MIPS16-DAG: or $[[R0]], $[[R3]]
; MIPS16-DAG: or $[[R0]], $[[R1]]
; MIPS16-DAG: srl $[[R0:[0-9]+]], $4, 8 ; MIPS16-DAG: srl $[[R0:[0-9]+]], $4, 8
; MIPS16-DAG: srl $[[R1:[0-9]+]], $4, 24
; MIPS16-DAG: sll $[[R2:[0-9]+]], $4, 8
; MIPS16-DAG: sll $[[R3:[0-9]+]], $4, 24
; MIPS16-DAG: and $[[R0]], $[[R4]] ; MIPS16-DAG: and $[[R0]], $[[R4]]
; MIPS16-DAG: srl $[[R1:[0-9]+]], $4, 24
; MIPS16-DAG: or $[[R1]], $[[R0]] ; MIPS16-DAG: or $[[R1]], $[[R0]]
; MIPS16-DAG: and $[[R2]], $[[R7]] ; MIPS16-DAG: and $[[R4]], $4
; MIPS16-DAG: sll $[[R2:[0-9]+]], $[[R4]], 8
; MIPS16-DAG: sll $[[R3:[0-9]+]], $4, 24
; MIPS16-DAG: or $[[R3]], $[[R2]] ; MIPS16-DAG: or $[[R3]], $[[R2]]
; MIPS16-DAG: or $[[R3]], $[[R1]] ; MIPS16-DAG: or $[[R3]], $[[R1]]
%or.7 = call i64 @llvm.bswap.i64(i64 %x) %or.7 = call i64 @llvm.bswap.i64(i64 %x)
ret i64 %or.7 ret i64 %or.7
} }
define <4 x i32> @bswapv4i32(<4 x i32> %x) nounwind readnone { define <4 x i32> @bswapv4i32(<4 x i32> %x) nounwind readnone {
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llvm/test/CodeGen/RISCV/bswap-bitreverse.ll

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define i32 @test_bswap_i32(i32 %a) nounwind { define i32 @test_bswap_i32(i32 %a) nounwind {
; RV32I-LABEL: test_bswap_i32: ; RV32I-LABEL: test_bswap_i32:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: srli a1, a0, 8 ; RV32I-NEXT: srli a1, a0, 8
; RV32I-NEXT: lui a2, 16 ; RV32I-NEXT: lui a2, 16
; RV32I-NEXT: addi a2, a2, -256 ; RV32I-NEXT: addi a2, a2, -256
; RV32I-NEXT: and a1, a1, a2 ; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: srli a2, a0, 24 ; RV32I-NEXT: srli a3, a0, 24
; RV32I-NEXT: or a1, a1, a2 ; RV32I-NEXT: or a1, a1, a3
; RV32I-NEXT: slli a2, a0, 8 ; RV32I-NEXT: and a2, a0, a2
; RV32I-NEXT: lui a3, 4080 ; RV32I-NEXT: slli a2, a2, 8
; RV32I-NEXT: and a2, a2, a3
; RV32I-NEXT: slli a0, a0, 24 ; RV32I-NEXT: slli a0, a0, 24
; RV32I-NEXT: or a0, a0, a2 ; RV32I-NEXT: or a0, a0, a2
; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: test_bswap_i32: ; RV64I-LABEL: test_bswap_i32:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: srli a1, a0, 8 ; RV64I-NEXT: srli a1, a0, 8
; RV64I-NEXT: lui a2, 16 ; RV64I-NEXT: lui a2, 16
; RV64I-NEXT: addiw a2, a2, -256 ; RV64I-NEXT: addiw a2, a2, -256
; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: srliw a2, a0, 24 ; RV64I-NEXT: srliw a3, a0, 24
; RV64I-NEXT: or a1, a1, a2 ; RV64I-NEXT: or a1, a1, a3
; RV64I-NEXT: slli a2, a0, 8 ; RV64I-NEXT: and a2, a0, a2
; RV64I-NEXT: lui a3, 4080 ; RV64I-NEXT: slli a2, a2, 8
; RV64I-NEXT: and a2, a2, a3
; RV64I-NEXT: slliw a0, a0, 24 ; RV64I-NEXT: slliw a0, a0, 24
; RV64I-NEXT: or a0, a0, a2 ; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV32ZB-LABEL: test_bswap_i32: ; RV32ZB-LABEL: test_bswap_i32:
; RV32ZB: # %bb.0: ; RV32ZB: # %bb.0:
; RV32ZB-NEXT: rev8 a0, a0 ; RV32ZB-NEXT: rev8 a0, a0
Show All 12 Lines
; RV32I-LABEL: test_bswap_i64: ; RV32I-LABEL: test_bswap_i64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: srli a2, a1, 8 ; RV32I-NEXT: srli a2, a1, 8
; RV32I-NEXT: lui a3, 16 ; RV32I-NEXT: lui a3, 16
; RV32I-NEXT: addi a3, a3, -256 ; RV32I-NEXT: addi a3, a3, -256
; RV32I-NEXT: and a2, a2, a3 ; RV32I-NEXT: and a2, a2, a3
; RV32I-NEXT: srli a4, a1, 24 ; RV32I-NEXT: srli a4, a1, 24
; RV32I-NEXT: or a2, a2, a4 ; RV32I-NEXT: or a2, a2, a4
; RV32I-NEXT: slli a4, a1, 8 ; RV32I-NEXT: and a4, a1, a3
; RV32I-NEXT: lui a5, 4080 ; RV32I-NEXT: slli a4, a4, 8
; RV32I-NEXT: and a4, a4, a5
; RV32I-NEXT: slli a1, a1, 24 ; RV32I-NEXT: slli a1, a1, 24
; RV32I-NEXT: or a1, a1, a4 ; RV32I-NEXT: or a1, a1, a4
; RV32I-NEXT: or a2, a1, a2 ; RV32I-NEXT: or a2, a1, a2
; RV32I-NEXT: srli a1, a0, 8 ; RV32I-NEXT: srli a1, a0, 8
; RV32I-NEXT: and a1, a1, a3 ; RV32I-NEXT: and a1, a1, a3
; RV32I-NEXT: srli a3, a0, 24 ; RV32I-NEXT: srli a4, a0, 24
; RV32I-NEXT: or a1, a1, a3 ; RV32I-NEXT: or a1, a1, a4
; RV32I-NEXT: slli a3, a0, 8 ; RV32I-NEXT: and a3, a0, a3
; RV32I-NEXT: and a3, a3, a5 ; RV32I-NEXT: slli a3, a3, 8
; RV32I-NEXT: slli a0, a0, 24 ; RV32I-NEXT: slli a0, a0, 24
; RV32I-NEXT: or a0, a0, a3 ; RV32I-NEXT: or a0, a0, a3
; RV32I-NEXT: or a1, a0, a1 ; RV32I-NEXT: or a1, a0, a1
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: test_bswap_i64: ; RV64I-LABEL: test_bswap_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: slli a1, a0, 24 ; RV64I-NEXT: srli a1, a0, 40
; RV64I-NEXT: li a2, 255 ; RV64I-NEXT: lui a2, 16
; RV64I-NEXT: slli a3, a2, 40 ; RV64I-NEXT: addiw a2, a2, -256
; RV64I-NEXT: and a1, a1, a3 ; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: srliw a3, a0, 24
; RV64I-NEXT: slli a3, a3, 32
; RV64I-NEXT: or a1, a1, a3
; RV64I-NEXT: slli a3, a0, 40
; RV64I-NEXT: slli a2, a2, 48
; RV64I-NEXT: and a2, a3, a2
; RV64I-NEXT: slli a3, a0, 56
; RV64I-NEXT: or a2, a3, a2
; RV64I-NEXT: or a1, a2, a1
; RV64I-NEXT: srli a2, a0, 40
; RV64I-NEXT: lui a3, 16
; RV64I-NEXT: addiw a3, a3, -256
; RV64I-NEXT: and a2, a2, a3
; RV64I-NEXT: srli a3, a0, 56 ; RV64I-NEXT: srli a3, a0, 56
; RV64I-NEXT: or a2, a2, a3 ; RV64I-NEXT: or a1, a1, a3
; RV64I-NEXT: srli a3, a0, 24 ; RV64I-NEXT: srli a3, a0, 24
; RV64I-NEXT: lui a4, 4080 ; RV64I-NEXT: lui a4, 4080
; RV64I-NEXT: and a3, a3, a4 ; RV64I-NEXT: and a3, a3, a4
; RV64I-NEXT: srli a0, a0, 8 ; RV64I-NEXT: srli a5, a0, 8
; RV64I-NEXT: srliw a0, a0, 24 ; RV64I-NEXT: srliw a5, a5, 24
; RV64I-NEXT: slli a0, a0, 24 ; RV64I-NEXT: slli a5, a5, 24
; RV64I-NEXT: or a0, a0, a3 ; RV64I-NEXT: or a3, a5, a3
; RV64I-NEXT: or a1, a3, a1
; RV64I-NEXT: and a3, a0, a4
; RV64I-NEXT: slli a3, a3, 24
; RV64I-NEXT: srliw a4, a0, 24
; RV64I-NEXT: slli a4, a4, 32
; RV64I-NEXT: or a3, a3, a4
; RV64I-NEXT: and a2, a0, a2
; RV64I-NEXT: slli a2, a2, 40
; RV64I-NEXT: slli a0, a0, 56
; RV64I-NEXT: or a0, a0, a2 ; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a0, a3
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV32ZB-LABEL: test_bswap_i64: ; RV32ZB-LABEL: test_bswap_i64:
; RV32ZB: # %bb.0: ; RV32ZB: # %bb.0:
; RV32ZB-NEXT: rev8 a2, a1 ; RV32ZB-NEXT: rev8 a2, a1
; RV32ZB-NEXT: rev8 a1, a0 ; RV32ZB-NEXT: rev8 a1, a0
; RV32ZB-NEXT: mv a0, a2 ; RV32ZB-NEXT: mv a0, a2
; RV32ZB-NEXT: ret ; RV32ZB-NEXT: ret
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define i32 @test_bitreverse_i32(i32 %a) nounwind { define i32 @test_bitreverse_i32(i32 %a) nounwind {
; RV32I-LABEL: test_bitreverse_i32: ; RV32I-LABEL: test_bitreverse_i32:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: srli a1, a0, 8 ; RV32I-NEXT: srli a1, a0, 8
; RV32I-NEXT: lui a2, 16 ; RV32I-NEXT: lui a2, 16
; RV32I-NEXT: addi a2, a2, -256 ; RV32I-NEXT: addi a2, a2, -256
; RV32I-NEXT: and a1, a1, a2 ; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: srli a2, a0, 24 ; RV32I-NEXT: srli a3, a0, 24
; RV32I-NEXT: or a1, a1, a2 ; RV32I-NEXT: or a1, a1, a3
; RV32I-NEXT: slli a2, a0, 8 ; RV32I-NEXT: and a2, a0, a2
; RV32I-NEXT: lui a3, 4080 ; RV32I-NEXT: slli a2, a2, 8
; RV32I-NEXT: and a2, a2, a3
; RV32I-NEXT: slli a0, a0, 24 ; RV32I-NEXT: slli a0, a0, 24
; RV32I-NEXT: or a0, a0, a2 ; RV32I-NEXT: or a0, a0, a2
; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: srli a1, a0, 4 ; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: lui a2, 61681 ; RV32I-NEXT: lui a2, 61681
; RV32I-NEXT: addi a2, a2, -241 ; RV32I-NEXT: addi a2, a2, -241
; RV32I-NEXT: and a1, a1, a2 ; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: and a0, a0, a2 ; RV32I-NEXT: and a0, a0, a2
Show All 16 Lines
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: test_bitreverse_i32: ; RV64I-LABEL: test_bitreverse_i32:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: srli a1, a0, 8 ; RV64I-NEXT: srli a1, a0, 8
; RV64I-NEXT: lui a2, 16 ; RV64I-NEXT: lui a2, 16
; RV64I-NEXT: addiw a2, a2, -256 ; RV64I-NEXT: addiw a2, a2, -256
; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: srliw a2, a0, 24 ; RV64I-NEXT: srliw a3, a0, 24
; RV64I-NEXT: or a1, a1, a2 ; RV64I-NEXT: or a1, a1, a3
; RV64I-NEXT: slli a2, a0, 8 ; RV64I-NEXT: and a2, a0, a2
; RV64I-NEXT: lui a3, 4080 ; RV64I-NEXT: slli a2, a2, 8
; RV64I-NEXT: and a2, a2, a3
; RV64I-NEXT: slliw a0, a0, 24 ; RV64I-NEXT: slliw a0, a0, 24
; RV64I-NEXT: or a0, a0, a2 ; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: srli a1, a0, 4 ; RV64I-NEXT: srli a1, a0, 4
; RV64I-NEXT: lui a2, 61681 ; RV64I-NEXT: lui a2, 61681
; RV64I-NEXT: addiw a2, a2, -241 ; RV64I-NEXT: addiw a2, a2, -241
; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a0, a0, a2
▲ Show 20 Lines • Show All 90 Lines • ▼ Show 20 Lines
; RV32I-LABEL: test_bitreverse_i64: ; RV32I-LABEL: test_bitreverse_i64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: srli a2, a1, 8 ; RV32I-NEXT: srli a2, a1, 8
; RV32I-NEXT: lui a3, 16 ; RV32I-NEXT: lui a3, 16
; RV32I-NEXT: addi a3, a3, -256 ; RV32I-NEXT: addi a3, a3, -256
; RV32I-NEXT: and a2, a2, a3 ; RV32I-NEXT: and a2, a2, a3
; RV32I-NEXT: srli a4, a1, 24 ; RV32I-NEXT: srli a4, a1, 24
; RV32I-NEXT: or a2, a2, a4 ; RV32I-NEXT: or a2, a2, a4
; RV32I-NEXT: slli a4, a1, 8 ; RV32I-NEXT: and a4, a1, a3
; RV32I-NEXT: lui a5, 4080 ; RV32I-NEXT: slli a4, a4, 8
; RV32I-NEXT: and a4, a4, a5
; RV32I-NEXT: slli a1, a1, 24 ; RV32I-NEXT: slli a1, a1, 24
; RV32I-NEXT: or a1, a1, a4 ; RV32I-NEXT: or a1, a1, a4
; RV32I-NEXT: or a1, a1, a2 ; RV32I-NEXT: or a1, a1, a2
; RV32I-NEXT: srli a2, a1, 4 ; RV32I-NEXT: srli a2, a1, 4
; RV32I-NEXT: lui a4, 61681 ; RV32I-NEXT: lui a4, 61681
; RV32I-NEXT: addi a4, a4, -241 ; RV32I-NEXT: addi a4, a4, -241
; RV32I-NEXT: and a2, a2, a4 ; RV32I-NEXT: and a2, a2, a4
; RV32I-NEXT: and a1, a1, a4 ; RV32I-NEXT: and a1, a1, a4
; RV32I-NEXT: slli a1, a1, 4 ; RV32I-NEXT: slli a1, a1, 4
; RV32I-NEXT: or a1, a2, a1 ; RV32I-NEXT: or a1, a2, a1
; RV32I-NEXT: srli a2, a1, 2 ; RV32I-NEXT: srli a2, a1, 2
; RV32I-NEXT: lui a6, 209715 ; RV32I-NEXT: lui a5, 209715
; RV32I-NEXT: addi a6, a6, 819 ; RV32I-NEXT: addi a5, a5, 819
; RV32I-NEXT: and a2, a2, a6 ; RV32I-NEXT: and a2, a2, a5
; RV32I-NEXT: and a1, a1, a6 ; RV32I-NEXT: and a1, a1, a5
; RV32I-NEXT: slli a1, a1, 2 ; RV32I-NEXT: slli a1, a1, 2
; RV32I-NEXT: or a1, a2, a1 ; RV32I-NEXT: or a1, a2, a1
; RV32I-NEXT: srli a2, a1, 1 ; RV32I-NEXT: srli a2, a1, 1
; RV32I-NEXT: lui a7, 349525 ; RV32I-NEXT: lui a6, 349525
; RV32I-NEXT: addi a7, a7, 1365 ; RV32I-NEXT: addi a6, a6, 1365
; RV32I-NEXT: and a2, a2, a7 ; RV32I-NEXT: and a2, a2, a6
; RV32I-NEXT: and a1, a1, a7 ; RV32I-NEXT: and a1, a1, a6
; RV32I-NEXT: slli a1, a1, 1 ; RV32I-NEXT: slli a1, a1, 1
; RV32I-NEXT: or a2, a2, a1 ; RV32I-NEXT: or a2, a2, a1
; RV32I-NEXT: srli a1, a0, 8 ; RV32I-NEXT: srli a1, a0, 8
; RV32I-NEXT: and a1, a1, a3 ; RV32I-NEXT: and a1, a1, a3
; RV32I-NEXT: srli a3, a0, 24 ; RV32I-NEXT: srli a7, a0, 24
; RV32I-NEXT: or a1, a1, a3 ; RV32I-NEXT: or a1, a1, a7
; RV32I-NEXT: slli a3, a0, 8 ; RV32I-NEXT: and a3, a0, a3
; RV32I-NEXT: and a3, a3, a5 ; RV32I-NEXT: slli a3, a3, 8
; RV32I-NEXT: slli a0, a0, 24 ; RV32I-NEXT: slli a0, a0, 24
; RV32I-NEXT: or a0, a0, a3 ; RV32I-NEXT: or a0, a0, a3
; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: srli a1, a0, 4 ; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: and a1, a1, a4 ; RV32I-NEXT: and a1, a1, a4
; RV32I-NEXT: and a0, a0, a4 ; RV32I-NEXT: and a0, a0, a4
; RV32I-NEXT: slli a0, a0, 4 ; RV32I-NEXT: slli a0, a0, 4
; RV32I-NEXT: or a0, a1, a0 ; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: srli a1, a0, 2 ; RV32I-NEXT: srli a1, a0, 2
; RV32I-NEXT: and a1, a1, a6 ; RV32I-NEXT: and a1, a1, a5
; RV32I-NEXT: and a0, a0, a6 ; RV32I-NEXT: and a0, a0, a5
; RV32I-NEXT: slli a0, a0, 2 ; RV32I-NEXT: slli a0, a0, 2
; RV32I-NEXT: or a0, a1, a0 ; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: srli a1, a0, 1 ; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: and a1, a1, a7 ; RV32I-NEXT: and a1, a1, a6
; RV32I-NEXT: and a0, a0, a7 ; RV32I-NEXT: and a0, a0, a6
; RV32I-NEXT: slli a0, a0, 1 ; RV32I-NEXT: slli a0, a0, 1
; RV32I-NEXT: or a1, a1, a0 ; RV32I-NEXT: or a1, a1, a0
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: test_bitreverse_i64: ; RV64I-LABEL: test_bitreverse_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: slli a1, a0, 24 ; RV64I-NEXT: srli a1, a0, 40
; RV64I-NEXT: li a2, 255 ; RV64I-NEXT: lui a2, 16
; RV64I-NEXT: slli a3, a2, 40 ; RV64I-NEXT: addiw a2, a2, -256
; RV64I-NEXT: and a1, a1, a3 ; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: srliw a3, a0, 24
; RV64I-NEXT: slli a3, a3, 32
; RV64I-NEXT: or a1, a1, a3
; RV64I-NEXT: slli a3, a0, 40
; RV64I-NEXT: slli a2, a2, 48
; RV64I-NEXT: and a2, a3, a2
; RV64I-NEXT: slli a3, a0, 56
; RV64I-NEXT: or a2, a3, a2
; RV64I-NEXT: or a1, a2, a1
; RV64I-NEXT: srli a2, a0, 40
; RV64I-NEXT: lui a3, 16
; RV64I-NEXT: addiw a3, a3, -256
; RV64I-NEXT: and a2, a2, a3
; RV64I-NEXT: srli a3, a0, 56 ; RV64I-NEXT: srli a3, a0, 56
; RV64I-NEXT: or a2, a2, a3 ; RV64I-NEXT: or a1, a1, a3
; RV64I-NEXT: srli a3, a0, 24 ; RV64I-NEXT: srli a3, a0, 24
; RV64I-NEXT: lui a4, 4080 ; RV64I-NEXT: lui a4, 4080
; RV64I-NEXT: and a3, a3, a4 ; RV64I-NEXT: and a3, a3, a4
; RV64I-NEXT: srli a0, a0, 8 ; RV64I-NEXT: srli a5, a0, 8
; RV64I-NEXT: srliw a0, a0, 24 ; RV64I-NEXT: srliw a5, a5, 24
; RV64I-NEXT: slli a0, a0, 24 ; RV64I-NEXT: slli a5, a5, 24
; RV64I-NEXT: or a0, a0, a3 ; RV64I-NEXT: or a3, a5, a3
; RV64I-NEXT: lui a3, %hi(.LCPI6_0) ; RV64I-NEXT: or a1, a3, a1
; RV64I-NEXT: ld a3, %lo(.LCPI6_0)(a3) ; RV64I-NEXT: and a3, a0, a4
; RV64I-NEXT: slli a3, a3, 24
; RV64I-NEXT: srliw a4, a0, 24
; RV64I-NEXT: slli a4, a4, 32
; RV64I-NEXT: or a3, a3, a4
; RV64I-NEXT: and a2, a0, a2
; RV64I-NEXT: slli a2, a2, 40
; RV64I-NEXT: slli a0, a0, 56
; RV64I-NEXT: or a0, a0, a2 ; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: lui a2, %hi(.LCPI6_0)
; RV64I-NEXT: ld a2, %lo(.LCPI6_0)(a2)
; RV64I-NEXT: or a0, a0, a3
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: srli a1, a0, 4 ; RV64I-NEXT: srli a1, a0, 4
; RV64I-NEXT: and a1, a1, a3 ; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: and a0, a0, a3 ; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: lui a2, %hi(.LCPI6_1) ; RV64I-NEXT: lui a2, %hi(.LCPI6_1)
; RV64I-NEXT: ld a2, %lo(.LCPI6_1)(a2) ; RV64I-NEXT: ld a2, %lo(.LCPI6_1)(a2)
; RV64I-NEXT: slli a0, a0, 4 ; RV64I-NEXT: slli a0, a0, 4
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: srli a1, a0, 2 ; RV64I-NEXT: srli a1, a0, 2
; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: lui a2, %hi(.LCPI6_2) ; RV64I-NEXT: lui a2, %hi(.LCPI6_2)
▲ Show 20 Lines • Show All 904 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rv32zbb.ll

Show First 20 Lines • Show All 763 Lines • ▼ Show 20 Lines
define i32 @bswap_i32(i32 %a) nounwind { define i32 @bswap_i32(i32 %a) nounwind {
; RV32I-LABEL: bswap_i32: ; RV32I-LABEL: bswap_i32:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: srli a1, a0, 8 ; RV32I-NEXT: srli a1, a0, 8
; RV32I-NEXT: lui a2, 16 ; RV32I-NEXT: lui a2, 16
; RV32I-NEXT: addi a2, a2, -256 ; RV32I-NEXT: addi a2, a2, -256
; RV32I-NEXT: and a1, a1, a2 ; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: srli a2, a0, 24 ; RV32I-NEXT: srli a3, a0, 24
; RV32I-NEXT: or a1, a1, a2 ; RV32I-NEXT: or a1, a1, a3
; RV32I-NEXT: slli a2, a0, 8 ; RV32I-NEXT: and a2, a0, a2
; RV32I-NEXT: lui a3, 4080 ; RV32I-NEXT: slli a2, a2, 8
; RV32I-NEXT: and a2, a2, a3
; RV32I-NEXT: slli a0, a0, 24 ; RV32I-NEXT: slli a0, a0, 24
; RV32I-NEXT: or a0, a0, a2 ; RV32I-NEXT: or a0, a0, a2
; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32ZBB-LABEL: bswap_i32: ; RV32ZBB-LABEL: bswap_i32:
; RV32ZBB: # %bb.0: ; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: rev8 a0, a0 ; RV32ZBB-NEXT: rev8 a0, a0
; RV32ZBB-NEXT: ret ; RV32ZBB-NEXT: ret
%1 = tail call i32 @llvm.bswap.i32(i32 %a) %1 = tail call i32 @llvm.bswap.i32(i32 %a)
ret i32 %1 ret i32 %1
} }
declare i64 @llvm.bswap.i64(i64) declare i64 @llvm.bswap.i64(i64)
define i64 @bswap_i64(i64 %a) { define i64 @bswap_i64(i64 %a) {
; RV32I-LABEL: bswap_i64: ; RV32I-LABEL: bswap_i64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: srli a2, a1, 8 ; RV32I-NEXT: srli a2, a1, 8
; RV32I-NEXT: lui a3, 16 ; RV32I-NEXT: lui a3, 16
; RV32I-NEXT: addi a3, a3, -256 ; RV32I-NEXT: addi a3, a3, -256
; RV32I-NEXT: and a2, a2, a3 ; RV32I-NEXT: and a2, a2, a3
; RV32I-NEXT: srli a4, a1, 24 ; RV32I-NEXT: srli a4, a1, 24
; RV32I-NEXT: or a2, a2, a4 ; RV32I-NEXT: or a2, a2, a4
; RV32I-NEXT: slli a4, a1, 8 ; RV32I-NEXT: and a4, a1, a3
; RV32I-NEXT: lui a5, 4080 ; RV32I-NEXT: slli a4, a4, 8
; RV32I-NEXT: and a4, a4, a5
; RV32I-NEXT: slli a1, a1, 24 ; RV32I-NEXT: slli a1, a1, 24
; RV32I-NEXT: or a1, a1, a4 ; RV32I-NEXT: or a1, a1, a4
; RV32I-NEXT: or a2, a1, a2 ; RV32I-NEXT: or a2, a1, a2
; RV32I-NEXT: srli a1, a0, 8 ; RV32I-NEXT: srli a1, a0, 8
; RV32I-NEXT: and a1, a1, a3 ; RV32I-NEXT: and a1, a1, a3
; RV32I-NEXT: srli a3, a0, 24 ; RV32I-NEXT: srli a4, a0, 24
; RV32I-NEXT: or a1, a1, a3 ; RV32I-NEXT: or a1, a1, a4
; RV32I-NEXT: slli a3, a0, 8 ; RV32I-NEXT: and a3, a0, a3
; RV32I-NEXT: and a3, a3, a5 ; RV32I-NEXT: slli a3, a3, 8
; RV32I-NEXT: slli a0, a0, 24 ; RV32I-NEXT: slli a0, a0, 24
; RV32I-NEXT: or a0, a0, a3 ; RV32I-NEXT: or a0, a0, a3
; RV32I-NEXT: or a1, a0, a1 ; RV32I-NEXT: or a1, a0, a1
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32ZBB-LABEL: bswap_i64: ; RV32ZBB-LABEL: bswap_i64:
; RV32ZBB: # %bb.0: ; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: rev8 a2, a1 ; RV32ZBB-NEXT: rev8 a2, a1
; RV32ZBB-NEXT: rev8 a1, a0 ; RV32ZBB-NEXT: rev8 a1, a0
; RV32ZBB-NEXT: mv a0, a2 ; RV32ZBB-NEXT: mv a0, a2
; RV32ZBB-NEXT: ret ; RV32ZBB-NEXT: ret
%1 = call i64 @llvm.bswap.i64(i64 %a) %1 = call i64 @llvm.bswap.i64(i64 %a)
ret i64 %1 ret i64 %1
} }

llvm/test/CodeGen/RISCV/rv64zbb.ll

Show First 20 Lines • Show All 946 Lines • ▼ Show 20 Lines
define signext i32 @bswap_i32(i32 signext %a) nounwind { define signext i32 @bswap_i32(i32 signext %a) nounwind {
; RV64I-LABEL: bswap_i32: ; RV64I-LABEL: bswap_i32:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: srli a1, a0, 8 ; RV64I-NEXT: srli a1, a0, 8
; RV64I-NEXT: lui a2, 16 ; RV64I-NEXT: lui a2, 16
; RV64I-NEXT: addiw a2, a2, -256 ; RV64I-NEXT: addiw a2, a2, -256
; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: srliw a2, a0, 24 ; RV64I-NEXT: srliw a3, a0, 24
; RV64I-NEXT: or a1, a1, a2 ; RV64I-NEXT: or a1, a1, a3
; RV64I-NEXT: slli a2, a0, 8 ; RV64I-NEXT: and a2, a0, a2
; RV64I-NEXT: lui a3, 4080 ; RV64I-NEXT: slli a2, a2, 8
; RV64I-NEXT: and a2, a2, a3
; RV64I-NEXT: slliw a0, a0, 24 ; RV64I-NEXT: slliw a0, a0, 24
; RV64I-NEXT: or a0, a0, a2 ; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64ZBB-LABEL: bswap_i32: ; RV64ZBB-LABEL: bswap_i32:
; RV64ZBB: # %bb.0: ; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: rev8 a0, a0 ; RV64ZBB-NEXT: rev8 a0, a0
; RV64ZBB-NEXT: srai a0, a0, 32 ; RV64ZBB-NEXT: srai a0, a0, 32
; RV64ZBB-NEXT: ret ; RV64ZBB-NEXT: ret
%1 = tail call i32 @llvm.bswap.i32(i32 %a) %1 = tail call i32 @llvm.bswap.i32(i32 %a)
ret i32 %1 ret i32 %1
} }
; Similar to bswap_i32 but the result is not sign extended. ; Similar to bswap_i32 but the result is not sign extended.
define void @bswap_i32_nosext(i32 signext %a, i32* %x) nounwind { define void @bswap_i32_nosext(i32 signext %a, i32* %x) nounwind {
; RV64I-LABEL: bswap_i32_nosext: ; RV64I-LABEL: bswap_i32_nosext:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: srli a2, a0, 8 ; RV64I-NEXT: srli a2, a0, 8
; RV64I-NEXT: lui a3, 16 ; RV64I-NEXT: lui a3, 16
; RV64I-NEXT: addiw a3, a3, -256 ; RV64I-NEXT: addiw a3, a3, -256
; RV64I-NEXT: and a2, a2, a3 ; RV64I-NEXT: and a2, a2, a3
; RV64I-NEXT: srliw a3, a0, 24 ; RV64I-NEXT: srliw a4, a0, 24
; RV64I-NEXT: or a2, a2, a3 ; RV64I-NEXT: or a2, a2, a4
; RV64I-NEXT: slli a3, a0, 8 ; RV64I-NEXT: and a3, a0, a3
; RV64I-NEXT: lui a4, 4080 ; RV64I-NEXT: slli a3, a3, 8
; RV64I-NEXT: and a3, a3, a4
; RV64I-NEXT: slli a0, a0, 24 ; RV64I-NEXT: slli a0, a0, 24
; RV64I-NEXT: or a0, a0, a3 ; RV64I-NEXT: or a0, a0, a3
; RV64I-NEXT: or a0, a0, a2 ; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: sw a0, 0(a1) ; RV64I-NEXT: sw a0, 0(a1)
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64ZBB-LABEL: bswap_i32_nosext: ; RV64ZBB-LABEL: bswap_i32_nosext:
; RV64ZBB: # %bb.0: ; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: rev8 a0, a0 ; RV64ZBB-NEXT: rev8 a0, a0
; RV64ZBB-NEXT: srli a0, a0, 32 ; RV64ZBB-NEXT: srli a0, a0, 32
; RV64ZBB-NEXT: sw a0, 0(a1) ; RV64ZBB-NEXT: sw a0, 0(a1)
; RV64ZBB-NEXT: ret ; RV64ZBB-NEXT: ret
%1 = tail call i32 @llvm.bswap.i32(i32 %a) %1 = tail call i32 @llvm.bswap.i32(i32 %a)
store i32 %1, i32* %x store i32 %1, i32* %x
ret void ret void
} }
declare i64 @llvm.bswap.i64(i64) declare i64 @llvm.bswap.i64(i64)
define i64 @bswap_i64(i64 %a) { define i64 @bswap_i64(i64 %a) {
; RV64I-LABEL: bswap_i64: ; RV64I-LABEL: bswap_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: slli a1, a0, 24 ; RV64I-NEXT: srli a1, a0, 40
; RV64I-NEXT: li a2, 255 ; RV64I-NEXT: lui a2, 16
; RV64I-NEXT: slli a3, a2, 40 ; RV64I-NEXT: addiw a2, a2, -256
; RV64I-NEXT: and a1, a1, a3 ; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: srliw a3, a0, 24
; RV64I-NEXT: slli a3, a3, 32
; RV64I-NEXT: or a1, a1, a3
; RV64I-NEXT: slli a3, a0, 40
; RV64I-NEXT: slli a2, a2, 48
; RV64I-NEXT: and a2, a3, a2
; RV64I-NEXT: slli a3, a0, 56
; RV64I-NEXT: or a2, a3, a2
; RV64I-NEXT: or a1, a2, a1
; RV64I-NEXT: srli a2, a0, 40
; RV64I-NEXT: lui a3, 16
; RV64I-NEXT: addiw a3, a3, -256
; RV64I-NEXT: and a2, a2, a3
; RV64I-NEXT: srli a3, a0, 56 ; RV64I-NEXT: srli a3, a0, 56
; RV64I-NEXT: or a2, a2, a3 ; RV64I-NEXT: or a1, a1, a3
; RV64I-NEXT: srli a3, a0, 24 ; RV64I-NEXT: srli a3, a0, 24
; RV64I-NEXT: lui a4, 4080 ; RV64I-NEXT: lui a4, 4080
; RV64I-NEXT: and a3, a3, a4 ; RV64I-NEXT: and a3, a3, a4
; RV64I-NEXT: srli a0, a0, 8 ; RV64I-NEXT: srli a5, a0, 8
; RV64I-NEXT: srliw a0, a0, 24 ; RV64I-NEXT: srliw a5, a5, 24
; RV64I-NEXT: slli a0, a0, 24 ; RV64I-NEXT: slli a5, a5, 24
; RV64I-NEXT: or a0, a0, a3 ; RV64I-NEXT: or a3, a5, a3
; RV64I-NEXT: or a1, a3, a1
; RV64I-NEXT: and a3, a0, a4
; RV64I-NEXT: slli a3, a3, 24
; RV64I-NEXT: srliw a4, a0, 24
; RV64I-NEXT: slli a4, a4, 32
; RV64I-NEXT: or a3, a3, a4
; RV64I-NEXT: and a2, a0, a2
; RV64I-NEXT: slli a2, a2, 40
; RV64I-NEXT: slli a0, a0, 56
; RV64I-NEXT: or a0, a0, a2 ; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a0, a3
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64ZBB-LABEL: bswap_i64: ; RV64ZBB-LABEL: bswap_i64:
; RV64ZBB: # %bb.0: ; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: rev8 a0, a0 ; RV64ZBB-NEXT: rev8 a0, a0
; RV64ZBB-NEXT: ret ; RV64ZBB-NEXT: ret
%1 = call i64 @llvm.bswap.i64(i64 %a) %1 = call i64 @llvm.bswap.i64(i64 %a)
ret i64 %1 ret i64 %1
} }

llvm/test/CodeGen/RISCV/rvv/bitreverse-sdnode.ll

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; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; RV32-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
; RV32-NEXT: vsrl.vi v9, v8, 8 ; RV32-NEXT: vsrl.vi v9, v8, 8
; RV32-NEXT: lui a0, 16 ; RV32-NEXT: lui a0, 16
; RV32-NEXT: addi a0, a0, -256 ; RV32-NEXT: addi a0, a0, -256
; RV32-NEXT: vand.vx v9, v9, a0 ; RV32-NEXT: vand.vx v9, v9, a0
; RV32-NEXT: vsrl.vi v10, v8, 24 ; RV32-NEXT: vsrl.vi v10, v8, 24
; RV32-NEXT: vor.vv v9, v9, v10 ; RV32-NEXT: vor.vv v9, v9, v10
; RV32-NEXT: vsll.vi v10, v8, 8 ; RV32-NEXT: vand.vx v10, v8, a0
; RV32-NEXT: lui a0, 4080 ; RV32-NEXT: vsll.vi v10, v10, 8
; RV32-NEXT: vand.vx v10, v10, a0
; RV32-NEXT: vsll.vi v8, v8, 24 ; RV32-NEXT: vsll.vi v8, v8, 24
; RV32-NEXT: vor.vv v8, v8, v10 ; RV32-NEXT: vor.vv v8, v8, v10
; RV32-NEXT: vor.vv v8, v8, v9 ; RV32-NEXT: vor.vv v8, v8, v9
; RV32-NEXT: vsrl.vi v9, v8, 4 ; RV32-NEXT: vsrl.vi v9, v8, 4
; RV32-NEXT: lui a0, 61681 ; RV32-NEXT: lui a0, 61681
; RV32-NEXT: addi a0, a0, -241 ; RV32-NEXT: addi a0, a0, -241
; RV32-NEXT: vand.vx v9, v9, a0 ; RV32-NEXT: vand.vx v9, v9, a0
; RV32-NEXT: vand.vx v8, v8, a0 ; RV32-NEXT: vand.vx v8, v8, a0
Show All 19 Lines
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; RV64-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
; RV64-NEXT: vsrl.vi v9, v8, 8 ; RV64-NEXT: vsrl.vi v9, v8, 8
; RV64-NEXT: lui a0, 16 ; RV64-NEXT: lui a0, 16
; RV64-NEXT: addiw a0, a0, -256 ; RV64-NEXT: addiw a0, a0, -256
; RV64-NEXT: vand.vx v9, v9, a0 ; RV64-NEXT: vand.vx v9, v9, a0
; RV64-NEXT: vsrl.vi v10, v8, 24 ; RV64-NEXT: vsrl.vi v10, v8, 24
; RV64-NEXT: vor.vv v9, v9, v10 ; RV64-NEXT: vor.vv v9, v9, v10
; RV64-NEXT: vsll.vi v10, v8, 8 ; RV64-NEXT: vand.vx v10, v8, a0
; RV64-NEXT: lui a0, 4080 ; RV64-NEXT: vsll.vi v10, v10, 8
; RV64-NEXT: vand.vx v10, v10, a0
; RV64-NEXT: vsll.vi v8, v8, 24 ; RV64-NEXT: vsll.vi v8, v8, 24
; RV64-NEXT: vor.vv v8, v8, v10 ; RV64-NEXT: vor.vv v8, v8, v10
; RV64-NEXT: vor.vv v8, v8, v9 ; RV64-NEXT: vor.vv v8, v8, v9
; RV64-NEXT: vsrl.vi v9, v8, 4 ; RV64-NEXT: vsrl.vi v9, v8, 4
; RV64-NEXT: lui a0, 61681 ; RV64-NEXT: lui a0, 61681
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v9, v9, a0 ; RV64-NEXT: vand.vx v9, v9, a0
; RV64-NEXT: vand.vx v8, v8, a0 ; RV64-NEXT: vand.vx v8, v8, a0
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; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a0, zero, e32, m1, ta, ma ; RV32-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; RV32-NEXT: vsrl.vi v9, v8, 8 ; RV32-NEXT: vsrl.vi v9, v8, 8
; RV32-NEXT: lui a0, 16 ; RV32-NEXT: lui a0, 16
; RV32-NEXT: addi a0, a0, -256 ; RV32-NEXT: addi a0, a0, -256
; RV32-NEXT: vand.vx v9, v9, a0 ; RV32-NEXT: vand.vx v9, v9, a0
; RV32-NEXT: vsrl.vi v10, v8, 24 ; RV32-NEXT: vsrl.vi v10, v8, 24
; RV32-NEXT: vor.vv v9, v9, v10 ; RV32-NEXT: vor.vv v9, v9, v10
; RV32-NEXT: vsll.vi v10, v8, 8 ; RV32-NEXT: vand.vx v10, v8, a0
; RV32-NEXT: lui a0, 4080 ; RV32-NEXT: vsll.vi v10, v10, 8
; RV32-NEXT: vand.vx v10, v10, a0
; RV32-NEXT: vsll.vi v8, v8, 24 ; RV32-NEXT: vsll.vi v8, v8, 24
; RV32-NEXT: vor.vv v8, v8, v10 ; RV32-NEXT: vor.vv v8, v8, v10
; RV32-NEXT: vor.vv v8, v8, v9 ; RV32-NEXT: vor.vv v8, v8, v9
; RV32-NEXT: vsrl.vi v9, v8, 4 ; RV32-NEXT: vsrl.vi v9, v8, 4
; RV32-NEXT: lui a0, 61681 ; RV32-NEXT: lui a0, 61681
; RV32-NEXT: addi a0, a0, -241 ; RV32-NEXT: addi a0, a0, -241
; RV32-NEXT: vand.vx v9, v9, a0 ; RV32-NEXT: vand.vx v9, v9, a0
; RV32-NEXT: vand.vx v8, v8, a0 ; RV32-NEXT: vand.vx v8, v8, a0
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; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a0, zero, e32, m1, ta, ma ; RV64-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; RV64-NEXT: vsrl.vi v9, v8, 8 ; RV64-NEXT: vsrl.vi v9, v8, 8
; RV64-NEXT: lui a0, 16 ; RV64-NEXT: lui a0, 16
; RV64-NEXT: addiw a0, a0, -256 ; RV64-NEXT: addiw a0, a0, -256
; RV64-NEXT: vand.vx v9, v9, a0 ; RV64-NEXT: vand.vx v9, v9, a0
; RV64-NEXT: vsrl.vi v10, v8, 24 ; RV64-NEXT: vsrl.vi v10, v8, 24
; RV64-NEXT: vor.vv v9, v9, v10 ; RV64-NEXT: vor.vv v9, v9, v10
; RV64-NEXT: vsll.vi v10, v8, 8 ; RV64-NEXT: vand.vx v10, v8, a0
; RV64-NEXT: lui a0, 4080 ; RV64-NEXT: vsll.vi v10, v10, 8
; RV64-NEXT: vand.vx v10, v10, a0
; RV64-NEXT: vsll.vi v8, v8, 24 ; RV64-NEXT: vsll.vi v8, v8, 24
; RV64-NEXT: vor.vv v8, v8, v10 ; RV64-NEXT: vor.vv v8, v8, v10
; RV64-NEXT: vor.vv v8, v8, v9 ; RV64-NEXT: vor.vv v8, v8, v9
; RV64-NEXT: vsrl.vi v9, v8, 4 ; RV64-NEXT: vsrl.vi v9, v8, 4
; RV64-NEXT: lui a0, 61681 ; RV64-NEXT: lui a0, 61681
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v9, v9, a0 ; RV64-NEXT: vand.vx v9, v9, a0
; RV64-NEXT: vand.vx v8, v8, a0 ; RV64-NEXT: vand.vx v8, v8, a0
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; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; RV32-NEXT: vsrl.vi v10, v8, 8 ; RV32-NEXT: vsrl.vi v10, v8, 8
; RV32-NEXT: lui a0, 16 ; RV32-NEXT: lui a0, 16
; RV32-NEXT: addi a0, a0, -256 ; RV32-NEXT: addi a0, a0, -256
; RV32-NEXT: vand.vx v10, v10, a0 ; RV32-NEXT: vand.vx v10, v10, a0
; RV32-NEXT: vsrl.vi v12, v8, 24 ; RV32-NEXT: vsrl.vi v12, v8, 24
; RV32-NEXT: vor.vv v10, v10, v12 ; RV32-NEXT: vor.vv v10, v10, v12
; RV32-NEXT: vsll.vi v12, v8, 8 ; RV32-NEXT: vand.vx v12, v8, a0
; RV32-NEXT: lui a0, 4080 ; RV32-NEXT: vsll.vi v12, v12, 8
; RV32-NEXT: vand.vx v12, v12, a0
; RV32-NEXT: vsll.vi v8, v8, 24 ; RV32-NEXT: vsll.vi v8, v8, 24
; RV32-NEXT: vor.vv v8, v8, v12 ; RV32-NEXT: vor.vv v8, v8, v12
; RV32-NEXT: vor.vv v8, v8, v10 ; RV32-NEXT: vor.vv v8, v8, v10
; RV32-NEXT: vsrl.vi v10, v8, 4 ; RV32-NEXT: vsrl.vi v10, v8, 4
; RV32-NEXT: lui a0, 61681 ; RV32-NEXT: lui a0, 61681
; RV32-NEXT: addi a0, a0, -241 ; RV32-NEXT: addi a0, a0, -241
; RV32-NEXT: vand.vx v10, v10, a0 ; RV32-NEXT: vand.vx v10, v10, a0
; RV32-NEXT: vand.vx v8, v8, a0 ; RV32-NEXT: vand.vx v8, v8, a0
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; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; RV64-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; RV64-NEXT: vsrl.vi v10, v8, 8 ; RV64-NEXT: vsrl.vi v10, v8, 8
; RV64-NEXT: lui a0, 16 ; RV64-NEXT: lui a0, 16
; RV64-NEXT: addiw a0, a0, -256 ; RV64-NEXT: addiw a0, a0, -256
; RV64-NEXT: vand.vx v10, v10, a0 ; RV64-NEXT: vand.vx v10, v10, a0
; RV64-NEXT: vsrl.vi v12, v8, 24 ; RV64-NEXT: vsrl.vi v12, v8, 24
; RV64-NEXT: vor.vv v10, v10, v12 ; RV64-NEXT: vor.vv v10, v10, v12
; RV64-NEXT: vsll.vi v12, v8, 8 ; RV64-NEXT: vand.vx v12, v8, a0
; RV64-NEXT: lui a0, 4080 ; RV64-NEXT: vsll.vi v12, v12, 8
; RV64-NEXT: vand.vx v12, v12, a0
; RV64-NEXT: vsll.vi v8, v8, 24 ; RV64-NEXT: vsll.vi v8, v8, 24
; RV64-NEXT: vor.vv v8, v8, v12 ; RV64-NEXT: vor.vv v8, v8, v12
; RV64-NEXT: vor.vv v8, v8, v10 ; RV64-NEXT: vor.vv v8, v8, v10
; RV64-NEXT: vsrl.vi v10, v8, 4 ; RV64-NEXT: vsrl.vi v10, v8, 4
; RV64-NEXT: lui a0, 61681 ; RV64-NEXT: lui a0, 61681
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v10, v10, a0 ; RV64-NEXT: vand.vx v10, v10, a0
; RV64-NEXT: vand.vx v8, v8, a0 ; RV64-NEXT: vand.vx v8, v8, a0
Show All 24 Lines
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; RV32-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; RV32-NEXT: vsrl.vi v12, v8, 8 ; RV32-NEXT: vsrl.vi v12, v8, 8
; RV32-NEXT: lui a0, 16 ; RV32-NEXT: lui a0, 16
; RV32-NEXT: addi a0, a0, -256 ; RV32-NEXT: addi a0, a0, -256
; RV32-NEXT: vand.vx v12, v12, a0 ; RV32-NEXT: vand.vx v12, v12, a0
; RV32-NEXT: vsrl.vi v16, v8, 24 ; RV32-NEXT: vsrl.vi v16, v8, 24
; RV32-NEXT: vor.vv v12, v12, v16 ; RV32-NEXT: vor.vv v12, v12, v16
; RV32-NEXT: vsll.vi v16, v8, 8 ; RV32-NEXT: vand.vx v16, v8, a0
; RV32-NEXT: lui a0, 4080 ; RV32-NEXT: vsll.vi v16, v16, 8
; RV32-NEXT: vand.vx v16, v16, a0
; RV32-NEXT: vsll.vi v8, v8, 24 ; RV32-NEXT: vsll.vi v8, v8, 24
; RV32-NEXT: vor.vv v8, v8, v16 ; RV32-NEXT: vor.vv v8, v8, v16
; RV32-NEXT: vor.vv v8, v8, v12 ; RV32-NEXT: vor.vv v8, v8, v12
; RV32-NEXT: vsrl.vi v12, v8, 4 ; RV32-NEXT: vsrl.vi v12, v8, 4
; RV32-NEXT: lui a0, 61681 ; RV32-NEXT: lui a0, 61681
; RV32-NEXT: addi a0, a0, -241 ; RV32-NEXT: addi a0, a0, -241
; RV32-NEXT: vand.vx v12, v12, a0 ; RV32-NEXT: vand.vx v12, v12, a0
; RV32-NEXT: vand.vx v8, v8, a0 ; RV32-NEXT: vand.vx v8, v8, a0
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; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; RV64-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; RV64-NEXT: vsrl.vi v12, v8, 8 ; RV64-NEXT: vsrl.vi v12, v8, 8
; RV64-NEXT: lui a0, 16 ; RV64-NEXT: lui a0, 16
; RV64-NEXT: addiw a0, a0, -256 ; RV64-NEXT: addiw a0, a0, -256
; RV64-NEXT: vand.vx v12, v12, a0 ; RV64-NEXT: vand.vx v12, v12, a0
; RV64-NEXT: vsrl.vi v16, v8, 24 ; RV64-NEXT: vsrl.vi v16, v8, 24
; RV64-NEXT: vor.vv v12, v12, v16 ; RV64-NEXT: vor.vv v12, v12, v16
; RV64-NEXT: vsll.vi v16, v8, 8 ; RV64-NEXT: vand.vx v16, v8, a0
; RV64-NEXT: lui a0, 4080 ; RV64-NEXT: vsll.vi v16, v16, 8
; RV64-NEXT: vand.vx v16, v16, a0
; RV64-NEXT: vsll.vi v8, v8, 24 ; RV64-NEXT: vsll.vi v8, v8, 24
; RV64-NEXT: vor.vv v8, v8, v16 ; RV64-NEXT: vor.vv v8, v8, v16
; RV64-NEXT: vor.vv v8, v8, v12 ; RV64-NEXT: vor.vv v8, v8, v12
; RV64-NEXT: vsrl.vi v12, v8, 4 ; RV64-NEXT: vsrl.vi v12, v8, 4
; RV64-NEXT: lui a0, 61681 ; RV64-NEXT: lui a0, 61681
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v12, v12, a0 ; RV64-NEXT: vand.vx v12, v12, a0
; RV64-NEXT: vand.vx v8, v8, a0 ; RV64-NEXT: vand.vx v8, v8, a0
Show All 24 Lines
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a0, zero, e32, m8, ta, ma ; RV32-NEXT: vsetvli a0, zero, e32, m8, ta, ma
; RV32-NEXT: vsrl.vi v16, v8, 8 ; RV32-NEXT: vsrl.vi v16, v8, 8
; RV32-NEXT: lui a0, 16 ; RV32-NEXT: lui a0, 16
; RV32-NEXT: addi a0, a0, -256 ; RV32-NEXT: addi a0, a0, -256
; RV32-NEXT: vand.vx v16, v16, a0 ; RV32-NEXT: vand.vx v16, v16, a0
; RV32-NEXT: vsrl.vi v24, v8, 24 ; RV32-NEXT: vsrl.vi v24, v8, 24
; RV32-NEXT: vor.vv v16, v16, v24 ; RV32-NEXT: vor.vv v16, v16, v24
; RV32-NEXT: vsll.vi v24, v8, 8 ; RV32-NEXT: vand.vx v24, v8, a0
; RV32-NEXT: lui a0, 4080 ; RV32-NEXT: vsll.vi v24, v24, 8
; RV32-NEXT: vand.vx v24, v24, a0
; RV32-NEXT: vsll.vi v8, v8, 24 ; RV32-NEXT: vsll.vi v8, v8, 24
; RV32-NEXT: vor.vv v8, v8, v24 ; RV32-NEXT: vor.vv v8, v8, v24
; RV32-NEXT: vor.vv v8, v8, v16 ; RV32-NEXT: vor.vv v8, v8, v16
; RV32-NEXT: vsrl.vi v16, v8, 4 ; RV32-NEXT: vsrl.vi v16, v8, 4
; RV32-NEXT: lui a0, 61681 ; RV32-NEXT: lui a0, 61681
; RV32-NEXT: addi a0, a0, -241 ; RV32-NEXT: addi a0, a0, -241
; RV32-NEXT: vand.vx v16, v16, a0 ; RV32-NEXT: vand.vx v16, v16, a0
; RV32-NEXT: vand.vx v8, v8, a0 ; RV32-NEXT: vand.vx v8, v8, a0
Show All 19 Lines
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a0, zero, e32, m8, ta, ma ; RV64-NEXT: vsetvli a0, zero, e32, m8, ta, ma
; RV64-NEXT: vsrl.vi v16, v8, 8 ; RV64-NEXT: vsrl.vi v16, v8, 8
; RV64-NEXT: lui a0, 16 ; RV64-NEXT: lui a0, 16
; RV64-NEXT: addiw a0, a0, -256 ; RV64-NEXT: addiw a0, a0, -256
; RV64-NEXT: vand.vx v16, v16, a0 ; RV64-NEXT: vand.vx v16, v16, a0
; RV64-NEXT: vsrl.vi v24, v8, 24 ; RV64-NEXT: vsrl.vi v24, v8, 24
; RV64-NEXT: vor.vv v16, v16, v24 ; RV64-NEXT: vor.vv v16, v16, v24
; RV64-NEXT: vsll.vi v24, v8, 8 ; RV64-NEXT: vand.vx v24, v8, a0
; RV64-NEXT: lui a0, 4080 ; RV64-NEXT: vsll.vi v24, v24, 8
; RV64-NEXT: vand.vx v24, v24, a0
; RV64-NEXT: vsll.vi v8, v8, 24 ; RV64-NEXT: vsll.vi v8, v8, 24
; RV64-NEXT: vor.vv v8, v8, v24 ; RV64-NEXT: vor.vv v8, v8, v24
; RV64-NEXT: vor.vv v8, v8, v16 ; RV64-NEXT: vor.vv v8, v8, v16
; RV64-NEXT: vsrl.vi v16, v8, 4 ; RV64-NEXT: vsrl.vi v16, v8, 4
; RV64-NEXT: lui a0, 61681 ; RV64-NEXT: lui a0, 61681
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: vand.vx v16, v16, a0 ; RV64-NEXT: vand.vx v16, v16, a0
; RV64-NEXT: vand.vx v8, v8, a0 ; RV64-NEXT: vand.vx v8, v8, a0
Show All 22 Lines
define <vscale x 1 x i64> @bitreverse_nxv1i64(<vscale x 1 x i64> %va) { define <vscale x 1 x i64> @bitreverse_nxv1i64(<vscale x 1 x i64> %va) {
; RV32-LABEL: bitreverse_nxv1i64: ; RV32-LABEL: bitreverse_nxv1i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw zero, 12(sp) ; RV32-NEXT: sw zero, 12(sp)
; RV32-NEXT: lui a0, 1044480 ; RV32-NEXT: lui a0, 1044480
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: lui a0, 4080 ; RV32-NEXT: lui a0, 61681
; RV32-NEXT: addi a0, a0, -241
; RV32-NEXT: sw a0, 12(sp) ; RV32-NEXT: sw a0, 12(sp)
; RV32-NEXT: sw zero, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: li a1, 255 ; RV32-NEXT: lui a0, 209715
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, a0, 819
; RV32-NEXT: lui a1, 16 ; RV32-NEXT: sw a0, 12(sp)
; RV32-NEXT: addi a1, a1, -256 ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: lui a0, 349525
; RV32-NEXT: lui a2, 61681 ; RV32-NEXT: addi a0, a0, 1365
; RV32-NEXT: addi a2, a2, -241 ; RV32-NEXT: sw a0, 12(sp)
; RV32-NEXT: sw a2, 12(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a2, 8(sp) ; RV32-NEXT: li a0, 56
; RV32-NEXT: lui a2, 209715 ; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma
; RV32-NEXT: addi a2, a2, 819 ; RV32-NEXT: vsrl.vx v9, v8, a0
; RV32-NEXT: sw a2, 12(sp) ; RV32-NEXT: li a1, 40
; RV32-NEXT: sw a2, 8(sp) ; RV32-NEXT: vsrl.vx v10, v8, a1
; RV32-NEXT: lui a2, 349525 ; RV32-NEXT: lui a2, 16
; RV32-NEXT: addi a2, a2, 1365 ; RV32-NEXT: addi a2, a2, -256
; RV32-NEXT: sw a2, 12(sp) ; RV32-NEXT: vand.vx v10, v10, a2
; RV32-NEXT: sw a2, 8(sp)
; RV32-NEXT: li a2, 56
; RV32-NEXT: vsetvli a3, zero, e64, m1, ta, ma
; RV32-NEXT: vsrl.vx v9, v8, a2
; RV32-NEXT: li a3, 40
; RV32-NEXT: vsrl.vx v10, v8, a3
; RV32-NEXT: vand.vx v10, v10, a1
; RV32-NEXT: vor.vv v9, v10, v9 ; RV32-NEXT: vor.vv v9, v10, v9
; RV32-NEXT: addi a1, sp, 8 ; RV32-NEXT: vsrl.vi v10, v8, 24
; RV32-NEXT: vlse64.v v10, (a1), zero ; RV32-NEXT: addi a3, sp, 8
; RV32-NEXT: vsrl.vi v11, v8, 24 ; RV32-NEXT: vlse64.v v11, (a3), zero
; RV32-NEXT: vand.vx v11, v11, a0 ; RV32-NEXT: lui a4, 4080
; RV32-NEXT: vand.vx v10, v10, a4
; RV32-NEXT: vsrl.vi v12, v8, 8 ; RV32-NEXT: vsrl.vi v12, v8, 8
; RV32-NEXT: vand.vv v10, v12, v10 ; RV32-NEXT: vand.vv v12, v12, v11
; RV32-NEXT: vor.vv v10, v10, v11 ; RV32-NEXT: vor.vv v10, v12, v10
; RV32-NEXT: vlse64.v v11, (a1), zero
; RV32-NEXT: vor.vv v9, v10, v9 ; RV32-NEXT: vor.vv v9, v10, v9
; RV32-NEXT: vsll.vx v10, v8, a2 ; RV32-NEXT: vsll.vx v10, v8, a0
; RV32-NEXT: vsll.vx v12, v8, a3 ; RV32-NEXT: vand.vx v12, v8, a2
; RV32-NEXT: vand.vv v11, v12, v11 ; RV32-NEXT: vsll.vx v12, v12, a1
; RV32-NEXT: vlse64.v v12, (a1), zero ; RV32-NEXT: vor.vv v10, v10, v12
; RV32-NEXT: vor.vv v10, v10, v11 ; RV32-NEXT: vand.vx v12, v8, a4
; RV32-NEXT: vlse64.v v11, (a1), zero ; RV32-NEXT: vsll.vi v12, v12, 24
; RV32-NEXT: vsll.vi v13, v8, 8
; RV32-NEXT: vand.vv v12, v13, v12
; RV32-NEXT: vsll.vi v8, v8, 24
; RV32-NEXT: vand.vv v8, v8, v11 ; RV32-NEXT: vand.vv v8, v8, v11
; RV32-NEXT: vor.vv v8, v8, v12 ; RV32-NEXT: vsll.vi v8, v8, 8
; RV32-NEXT: vlse64.v v11, (a1), zero ; RV32-NEXT: vor.vv v8, v12, v8
; RV32-NEXT: vlse64.v v11, (a3), zero
; RV32-NEXT: vor.vv v8, v10, v8 ; RV32-NEXT: vor.vv v8, v10, v8
; RV32-NEXT: vor.vv v8, v8, v9 ; RV32-NEXT: vor.vv v8, v8, v9
; RV32-NEXT: vsrl.vi v9, v8, 4 ; RV32-NEXT: vsrl.vi v9, v8, 4
; RV32-NEXT: vand.vv v9, v9, v11 ; RV32-NEXT: vand.vv v9, v9, v11
; RV32-NEXT: vand.vv v8, v8, v11 ; RV32-NEXT: vand.vv v8, v8, v11
; RV32-NEXT: vlse64.v v10, (a1), zero ; RV32-NEXT: vlse64.v v10, (a3), zero
; RV32-NEXT: vsll.vi v8, v8, 4 ; RV32-NEXT: vsll.vi v8, v8, 4
; RV32-NEXT: vor.vv v8, v9, v8 ; RV32-NEXT: vor.vv v8, v9, v8
; RV32-NEXT: vsrl.vi v9, v8, 2 ; RV32-NEXT: vsrl.vi v9, v8, 2
; RV32-NEXT: vand.vv v9, v9, v10 ; RV32-NEXT: vand.vv v9, v9, v10
; RV32-NEXT: vand.vv v8, v8, v10 ; RV32-NEXT: vand.vv v8, v8, v10
; RV32-NEXT: vlse64.v v10, (a1), zero ; RV32-NEXT: vlse64.v v10, (a3), zero
; RV32-NEXT: vsll.vi v8, v8, 2 ; RV32-NEXT: vsll.vi v8, v8, 2
; RV32-NEXT: vor.vv v8, v9, v8 ; RV32-NEXT: vor.vv v8, v9, v8
; RV32-NEXT: vsrl.vi v9, v8, 1 ; RV32-NEXT: vsrl.vi v9, v8, 1
; RV32-NEXT: vand.vv v9, v9, v10 ; RV32-NEXT: vand.vv v9, v9, v10
; RV32-NEXT: vand.vv v8, v8, v10 ; RV32-NEXT: vand.vv v8, v8, v10
; RV32-NEXT: vadd.vv v8, v8, v8 ; RV32-NEXT: vadd.vv v8, v8, v8
; RV32-NEXT: vor.vv v8, v9, v8 ; RV32-NEXT: vor.vv v8, v9, v8
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: bitreverse_nxv1i64: ; RV64-LABEL: bitreverse_nxv1i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, ma ; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, ma
; RV64-NEXT: vsrl.vx v9, v8, a0 ; RV64-NEXT: vsrl.vx v9, v8, a0
; RV64-NEXT: li a1, 40 ; RV64-NEXT: li a1, 40
; RV64-NEXT: vsrl.vx v10, v8, a1 ; RV64-NEXT: vsrl.vx v10, v8, a1
; RV64-NEXT: lui a2, 16 ; RV64-NEXT: lui a2, 16
; RV64-NEXT: addiw a2, a2, -256 ; RV64-NEXT: addiw a2, a2, -256
; RV64-NEXT: vand.vx v10, v10, a2 ; RV64-NEXT: vand.vx v10, v10, a2
; RV64-NEXT: vor.vv v9, v10, v9 ; RV64-NEXT: vor.vv v9, v10, v9
; RV64-NEXT: vsrl.vi v10, v8, 24 ; RV64-NEXT: vsrl.vi v10, v8, 24
; RV64-NEXT: lui a2, 4080 ; RV64-NEXT: lui a3, 4080
; RV64-NEXT: vand.vx v10, v10, a2 ; RV64-NEXT: vand.vx v10, v10, a3
; RV64-NEXT: vsrl.vi v11, v8, 8 ; RV64-NEXT: vsrl.vi v11, v8, 8
; RV64-NEXT: li a2, 255 ; RV64-NEXT: li a4, 255
; RV64-NEXT: slli a3, a2, 24 ; RV64-NEXT: slli a4, a4, 24
; RV64-NEXT: vand.vx v11, v11, a3 ; RV64-NEXT: vand.vx v11, v11, a4
; RV64-NEXT: vor.vv v10, v11, v10 ; RV64-NEXT: vor.vv v10, v11, v10
; RV64-NEXT: vor.vv v9, v10, v9 ; RV64-NEXT: vor.vv v9, v10, v9
; RV64-NEXT: vsll.vi v10, v8, 8 ; RV64-NEXT: vand.vx v10, v8, a3
; RV64-NEXT: slli a3, a2, 32 ; RV64-NEXT: vsll.vi v10, v10, 24
; RV64-NEXT: vand.vx v10, v10, a3 ; RV64-NEXT: vand.vx v11, v8, a4
; RV64-NEXT: vsll.vi v11, v8, 24 ; RV64-NEXT: vsll.vi v11, v11, 8
; RV64-NEXT: slli a3, a2, 40 ; RV64-NEXT: vor.vv v10, v10, v11
; RV64-NEXT: vand.vx v11, v11, a3
; RV64-NEXT: vor.vv v10, v11, v10
; RV64-NEXT: vsll.vx v11, v8, a0 ; RV64-NEXT: vsll.vx v11, v8, a0
; RV64-NEXT: vand.vx v8, v8, a2
; RV64-NEXT: vsll.vx v8, v8, a1 ; RV64-NEXT: vsll.vx v8, v8, a1
; RV64-NEXT: slli a0, a2, 48
; RV64-NEXT: vand.vx v8, v8, a0
; RV64-NEXT: vor.vv v8, v11, v8 ; RV64-NEXT: vor.vv v8, v11, v8
; RV64-NEXT: lui a0, %hi(.LCPI18_0) ; RV64-NEXT: lui a0, %hi(.LCPI18_0)
; RV64-NEXT: ld a0, %lo(.LCPI18_0)(a0) ; RV64-NEXT: ld a0, %lo(.LCPI18_0)(a0)
; RV64-NEXT: vor.vv v8, v8, v10 ; RV64-NEXT: vor.vv v8, v8, v10
; RV64-NEXT: vor.vv v8, v8, v9 ; RV64-NEXT: vor.vv v8, v8, v9
; RV64-NEXT: vsrl.vi v9, v8, 4 ; RV64-NEXT: vsrl.vi v9, v8, 4
; RV64-NEXT: vand.vx v9, v9, a0 ; RV64-NEXT: vand.vx v9, v9, a0
; RV64-NEXT: vand.vx v8, v8, a0 ; RV64-NEXT: vand.vx v8, v8, a0
Show All 22 Lines
define <vscale x 2 x i64> @bitreverse_nxv2i64(<vscale x 2 x i64> %va) { define <vscale x 2 x i64> @bitreverse_nxv2i64(<vscale x 2 x i64> %va) {
; RV32-LABEL: bitreverse_nxv2i64: ; RV32-LABEL: bitreverse_nxv2i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw zero, 12(sp) ; RV32-NEXT: sw zero, 12(sp)
; RV32-NEXT: lui a0, 1044480 ; RV32-NEXT: lui a0, 1044480
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: lui a0, 4080 ; RV32-NEXT: lui a0, 61681
; RV32-NEXT: addi a0, a0, -241
; RV32-NEXT: sw a0, 12(sp)
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: lui a0, 209715
; RV32-NEXT: addi a0, a0, 819
; RV32-NEXT: sw a0, 12(sp)
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: lui a0, 349525
; RV32-NEXT: addi a0, a0, 1365
; RV32-NEXT: sw a0, 12(sp) ; RV32-NEXT: sw a0, 12(sp)
; RV32-NEXT: sw zero, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: li a1, 255 ; RV32-NEXT: li a0, 56
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma
; RV32-NEXT: lui a1, 16 ; RV32-NEXT: vsrl.vx v10, v8, a0
; RV32-NEXT: addi a1, a1, -256 ; RV32-NEXT: li a1, 40
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: vsrl.vx v12, v8, a1
; RV32-NEXT: lui a2, 61681 ; RV32-NEXT: lui a2, 16
; RV32-NEXT: addi a2, a2, -241 ; RV32-NEXT: addi a2, a2, -256
; RV32-NEXT: sw a2, 12(sp) ; RV32-NEXT: vand.vx v12, v12, a2
; RV32-NEXT: sw a2, 8(sp)
; RV32-NEXT: lui a2, 209715
; RV32-NEXT: addi a2, a2, 819
; RV32-NEXT: sw a2, 12(sp)
; RV32-NEXT: sw a2, 8(sp)
; RV32-NEXT: lui a2, 349525
; RV32-NEXT: addi a2, a2, 1365
; RV32-NEXT: sw a2, 12(sp)
; RV32-NEXT: sw a2, 8(sp)
; RV32-NEXT: li a2, 56
; RV32-NEXT: vsetvli a3, zero, e64, m2, ta, ma
; RV32-NEXT: vsrl.vx v10, v8, a2
; RV32-NEXT: li a3, 40
; RV32-NEXT: vsrl.vx v12, v8, a3
; RV32-NEXT: vand.vx v12, v12, a1
; RV32-NEXT: vor.vv v10, v12, v10 ; RV32-NEXT: vor.vv v10, v12, v10
; RV32-NEXT: addi a1, sp, 8 ; RV32-NEXT: vsrl.vi v12, v8, 24
; RV32-NEXT: vlse64.v v12, (a1), zero ; RV32-NEXT: addi a3, sp, 8
; RV32-NEXT: vsrl.vi v14, v8, 24 ; RV32-NEXT: vlse64.v v14, (a3), zero
; RV32-NEXT: vand.vx v14, v14, a0 ; RV32-NEXT: lui a4, 4080
; RV32-NEXT: vand.vx v12, v12, a4
; RV32-NEXT: vsrl.vi v16, v8, 8 ; RV32-NEXT: vsrl.vi v16, v8, 8
; RV32-NEXT: vand.vv v12, v16, v12 ; RV32-NEXT: vand.vv v16, v16, v14
; RV32-NEXT: vor.vv v12, v12, v14 ; RV32-NEXT: vor.vv v12, v16, v12
; RV32-NEXT: vlse64.v v14, (a1), zero
; RV32-NEXT: vor.vv v10, v12, v10 ; RV32-NEXT: vor.vv v10, v12, v10
; RV32-NEXT: vsll.vx v12, v8, a2 ; RV32-NEXT: vsll.vx v12, v8, a0
; RV32-NEXT: vsll.vx v16, v8, a3 ; RV32-NEXT: vand.vx v16, v8, a2
; RV32-NEXT: vand.vv v14, v16, v14 ; RV32-NEXT: vsll.vx v16, v16, a1
; RV32-NEXT: vlse64.v v16, (a1), zero ; RV32-NEXT: vor.vv v12, v12, v16
; RV32-NEXT: vor.vv v12, v12, v14 ; RV32-NEXT: vand.vx v16, v8, a4
; RV32-NEXT: vlse64.v v14, (a1), zero ; RV32-NEXT: vsll.vi v16, v16, 24
; RV32-NEXT: vsll.vi v18, v8, 8
; RV32-NEXT: vand.vv v16, v18, v16
; RV32-NEXT: vsll.vi v8, v8, 24
; RV32-NEXT: vand.vv v8, v8, v14 ; RV32-NEXT: vand.vv v8, v8, v14
; RV32-NEXT: vor.vv v8, v8, v16 ; RV32-NEXT: vsll.vi v8, v8, 8
; RV32-NEXT: vlse64.v v14, (a1), zero ; RV32-NEXT: vor.vv v8, v16, v8
; RV32-NEXT: vlse64.v v14, (a3), zero
; RV32-NEXT: vor.vv v8, v12, v8 ; RV32-NEXT: vor.vv v8, v12, v8
; RV32-NEXT: vor.vv v8, v8, v10 ; RV32-NEXT: vor.vv v8, v8, v10
; RV32-NEXT: vsrl.vi v10, v8, 4 ; RV32-NEXT: vsrl.vi v10, v8, 4
; RV32-NEXT: vand.vv v10, v10, v14 ; RV32-NEXT: vand.vv v10, v10, v14
; RV32-NEXT: vand.vv v8, v8, v14 ; RV32-NEXT: vand.vv v8, v8, v14
; RV32-NEXT: vlse64.v v12, (a1), zero ; RV32-NEXT: vlse64.v v12, (a3), zero
; RV32-NEXT: vsll.vi v8, v8, 4 ; RV32-NEXT: vsll.vi v8, v8, 4
; RV32-NEXT: vor.vv v8, v10, v8 ; RV32-NEXT: vor.vv v8, v10, v8
; RV32-NEXT: vsrl.vi v10, v8, 2 ; RV32-NEXT: vsrl.vi v10, v8, 2
; RV32-NEXT: vand.vv v10, v10, v12 ; RV32-NEXT: vand.vv v10, v10, v12
; RV32-NEXT: vand.vv v8, v8, v12 ; RV32-NEXT: vand.vv v8, v8, v12
; RV32-NEXT: vlse64.v v12, (a1), zero ; RV32-NEXT: vlse64.v v12, (a3), zero
; RV32-NEXT: vsll.vi v8, v8, 2 ; RV32-NEXT: vsll.vi v8, v8, 2
; RV32-NEXT: vor.vv v8, v10, v8 ; RV32-NEXT: vor.vv v8, v10, v8
; RV32-NEXT: vsrl.vi v10, v8, 1 ; RV32-NEXT: vsrl.vi v10, v8, 1
; RV32-NEXT: vand.vv v10, v10, v12 ; RV32-NEXT: vand.vv v10, v10, v12
; RV32-NEXT: vand.vv v8, v8, v12 ; RV32-NEXT: vand.vv v8, v8, v12
; RV32-NEXT: vadd.vv v8, v8, v8 ; RV32-NEXT: vadd.vv v8, v8, v8
; RV32-NEXT: vor.vv v8, v10, v8 ; RV32-NEXT: vor.vv v8, v10, v8
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: bitreverse_nxv2i64: ; RV64-LABEL: bitreverse_nxv2i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, ma ; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, ma
; RV64-NEXT: vsrl.vx v10, v8, a0 ; RV64-NEXT: vsrl.vx v10, v8, a0
; RV64-NEXT: li a1, 40 ; RV64-NEXT: li a1, 40
; RV64-NEXT: vsrl.vx v12, v8, a1 ; RV64-NEXT: vsrl.vx v12, v8, a1
; RV64-NEXT: lui a2, 16 ; RV64-NEXT: lui a2, 16
; RV64-NEXT: addiw a2, a2, -256 ; RV64-NEXT: addiw a2, a2, -256
; RV64-NEXT: vand.vx v12, v12, a2 ; RV64-NEXT: vand.vx v12, v12, a2
; RV64-NEXT: vor.vv v10, v12, v10 ; RV64-NEXT: vor.vv v10, v12, v10
; RV64-NEXT: vsrl.vi v12, v8, 24 ; RV64-NEXT: vsrl.vi v12, v8, 24
; RV64-NEXT: lui a2, 4080 ; RV64-NEXT: lui a3, 4080
; RV64-NEXT: vand.vx v12, v12, a2 ; RV64-NEXT: vand.vx v12, v12, a3
; RV64-NEXT: vsrl.vi v14, v8, 8 ; RV64-NEXT: vsrl.vi v14, v8, 8
; RV64-NEXT: li a2, 255 ; RV64-NEXT: li a4, 255
; RV64-NEXT: slli a3, a2, 24 ; RV64-NEXT: slli a4, a4, 24
; RV64-NEXT: vand.vx v14, v14, a3 ; RV64-NEXT: vand.vx v14, v14, a4
; RV64-NEXT: vor.vv v12, v14, v12 ; RV64-NEXT: vor.vv v12, v14, v12
; RV64-NEXT: vor.vv v10, v12, v10 ; RV64-NEXT: vor.vv v10, v12, v10
; RV64-NEXT: vsll.vi v12, v8, 8 ; RV64-NEXT: vand.vx v12, v8, a3
; RV64-NEXT: slli a3, a2, 32 ; RV64-NEXT: vsll.vi v12, v12, 24
; RV64-NEXT: vand.vx v12, v12, a3 ; RV64-NEXT: vand.vx v14, v8, a4
; RV64-NEXT: vsll.vi v14, v8, 24 ; RV64-NEXT: vsll.vi v14, v14, 8
; RV64-NEXT: slli a3, a2, 40 ; RV64-NEXT: vor.vv v12, v12, v14
; RV64-NEXT: vand.vx v14, v14, a3
; RV64-NEXT: vor.vv v12, v14, v12
; RV64-NEXT: vsll.vx v14, v8, a0 ; RV64-NEXT: vsll.vx v14, v8, a0
; RV64-NEXT: vand.vx v8, v8, a2
; RV64-NEXT: vsll.vx v8, v8, a1 ; RV64-NEXT: vsll.vx v8, v8, a1
; RV64-NEXT: slli a0, a2, 48
; RV64-NEXT: vand.vx v8, v8, a0
; RV64-NEXT: vor.vv v8, v14, v8 ; RV64-NEXT: vor.vv v8, v14, v8
; RV64-NEXT: lui a0, %hi(.LCPI19_0) ; RV64-NEXT: lui a0, %hi(.LCPI19_0)
; RV64-NEXT: ld a0, %lo(.LCPI19_0)(a0) ; RV64-NEXT: ld a0, %lo(.LCPI19_0)(a0)
; RV64-NEXT: vor.vv v8, v8, v12 ; RV64-NEXT: vor.vv v8, v8, v12
; RV64-NEXT: vor.vv v8, v8, v10 ; RV64-NEXT: vor.vv v8, v8, v10
; RV64-NEXT: vsrl.vi v10, v8, 4 ; RV64-NEXT: vsrl.vi v10, v8, 4
; RV64-NEXT: vand.vx v10, v10, a0 ; RV64-NEXT: vand.vx v10, v10, a0
; RV64-NEXT: vand.vx v8, v8, a0 ; RV64-NEXT: vand.vx v8, v8, a0
Show All 22 Lines
define <vscale x 4 x i64> @bitreverse_nxv4i64(<vscale x 4 x i64> %va) { define <vscale x 4 x i64> @bitreverse_nxv4i64(<vscale x 4 x i64> %va) {
; RV32-LABEL: bitreverse_nxv4i64: ; RV32-LABEL: bitreverse_nxv4i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw zero, 12(sp) ; RV32-NEXT: sw zero, 12(sp)
; RV32-NEXT: lui a0, 1044480 ; RV32-NEXT: lui a0, 1044480
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: lui a0, 4080 ; RV32-NEXT: lui a0, 61681
; RV32-NEXT: addi a0, a0, -241
; RV32-NEXT: sw a0, 12(sp) ; RV32-NEXT: sw a0, 12(sp)
; RV32-NEXT: sw zero, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: li a1, 255 ; RV32-NEXT: lui a0, 209715
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, a0, 819
; RV32-NEXT: lui a1, 16 ; RV32-NEXT: sw a0, 12(sp)
; RV32-NEXT: addi a1, a1, -256 ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: lui a0, 349525
; RV32-NEXT: lui a2, 61681 ; RV32-NEXT: addi a0, a0, 1365
; RV32-NEXT: addi a2, a2, -241 ; RV32-NEXT: sw a0, 12(sp)
; RV32-NEXT: sw a2, 12(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a2, 8(sp) ; RV32-NEXT: li a0, 56
; RV32-NEXT: lui a2, 209715 ; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma
; RV32-NEXT: addi a2, a2, 819 ; RV32-NEXT: vsrl.vx v12, v8, a0
; RV32-NEXT: sw a2, 12(sp) ; RV32-NEXT: li a1, 40
; RV32-NEXT: sw a2, 8(sp) ; RV32-NEXT: vsrl.vx v16, v8, a1
; RV32-NEXT: lui a2, 349525 ; RV32-NEXT: lui a2, 16
; RV32-NEXT: addi a2, a2, 1365 ; RV32-NEXT: addi a2, a2, -256
; RV32-NEXT: sw a2, 12(sp) ; RV32-NEXT: vand.vx v16, v16, a2
; RV32-NEXT: sw a2, 8(sp)
; RV32-NEXT: li a2, 56
; RV32-NEXT: vsetvli a3, zero, e64, m4, ta, ma
; RV32-NEXT: vsrl.vx v12, v8, a2
; RV32-NEXT: li a3, 40
; RV32-NEXT: vsrl.vx v16, v8, a3
; RV32-NEXT: vand.vx v16, v16, a1
; RV32-NEXT: vor.vv v12, v16, v12 ; RV32-NEXT: vor.vv v12, v16, v12
; RV32-NEXT: addi a1, sp, 8 ; RV32-NEXT: vsrl.vi v16, v8, 24
; RV32-NEXT: vlse64.v v16, (a1), zero ; RV32-NEXT: addi a3, sp, 8
; RV32-NEXT: vsrl.vi v20, v8, 24 ; RV32-NEXT: vlse64.v v20, (a3), zero
; RV32-NEXT: vand.vx v20, v20, a0 ; RV32-NEXT: lui a4, 4080
; RV32-NEXT: vand.vx v16, v16, a4
; RV32-NEXT: vsrl.vi v24, v8, 8 ; RV32-NEXT: vsrl.vi v24, v8, 8
; RV32-NEXT: vand.vv v16, v24, v16 ; RV32-NEXT: vand.vv v24, v24, v20
; RV32-NEXT: vor.vv v16, v16, v20 ; RV32-NEXT: vor.vv v16, v24, v16
; RV32-NEXT: vlse64.v v20, (a1), zero
; RV32-NEXT: vor.vv v12, v16, v12 ; RV32-NEXT: vor.vv v12, v16, v12
; RV32-NEXT: vsll.vx v16, v8, a2 ; RV32-NEXT: vsll.vx v16, v8, a0
; RV32-NEXT: vsll.vx v24, v8, a3 ; RV32-NEXT: vand.vx v24, v8, a2
; RV32-NEXT: vand.vv v20, v24, v20 ; RV32-NEXT: vsll.vx v24, v24, a1
; RV32-NEXT: vlse64.v v24, (a1), zero ; RV32-NEXT: vor.vv v16, v16, v24
; RV32-NEXT: vor.vv v16, v16, v20 ; RV32-NEXT: vand.vx v24, v8, a4
; RV32-NEXT: vlse64.v v20, (a1), zero ; RV32-NEXT: vsll.vi v24, v24, 24
; RV32-NEXT: vsll.vi v28, v8, 8
; RV32-NEXT: vand.vv v24, v28, v24
; RV32-NEXT: vsll.vi v8, v8, 24
; RV32-NEXT: vand.vv v8, v8, v20 ; RV32-NEXT: vand.vv v8, v8, v20
; RV32-NEXT: vor.vv v8, v8, v24 ; RV32-NEXT: vsll.vi v8, v8, 8
; RV32-NEXT: vlse64.v v20, (a1), zero ; RV32-NEXT: vor.vv v8, v24, v8
; RV32-NEXT: vlse64.v v20, (a3), zero
; RV32-NEXT: vor.vv v8, v16, v8 ; RV32-NEXT: vor.vv v8, v16, v8
; RV32-NEXT: vor.vv v8, v8, v12 ; RV32-NEXT: vor.vv v8, v8, v12
; RV32-NEXT: vsrl.vi v12, v8, 4 ; RV32-NEXT: vsrl.vi v12, v8, 4
; RV32-NEXT: vand.vv v12, v12, v20 ; RV32-NEXT: vand.vv v12, v12, v20
; RV32-NEXT: vand.vv v8, v8, v20 ; RV32-NEXT: vand.vv v8, v8, v20
; RV32-NEXT: vlse64.v v16, (a1), zero ; RV32-NEXT: vlse64.v v16, (a3), zero
; RV32-NEXT: vsll.vi v8, v8, 4 ; RV32-NEXT: vsll.vi v8, v8, 4
; RV32-NEXT: vor.vv v8, v12, v8 ; RV32-NEXT: vor.vv v8, v12, v8
; RV32-NEXT: vsrl.vi v12, v8, 2 ; RV32-NEXT: vsrl.vi v12, v8, 2
; RV32-NEXT: vand.vv v12, v12, v16 ; RV32-NEXT: vand.vv v12, v12, v16
; RV32-NEXT: vand.vv v8, v8, v16 ; RV32-NEXT: vand.vv v8, v8, v16
; RV32-NEXT: vlse64.v v16, (a1), zero ; RV32-NEXT: vlse64.v v16, (a3), zero
; RV32-NEXT: vsll.vi v8, v8, 2 ; RV32-NEXT: vsll.vi v8, v8, 2
; RV32-NEXT: vor.vv v8, v12, v8 ; RV32-NEXT: vor.vv v8, v12, v8
; RV32-NEXT: vsrl.vi v12, v8, 1 ; RV32-NEXT: vsrl.vi v12, v8, 1
; RV32-NEXT: vand.vv v12, v12, v16 ; RV32-NEXT: vand.vv v12, v12, v16
; RV32-NEXT: vand.vv v8, v8, v16 ; RV32-NEXT: vand.vv v8, v8, v16
; RV32-NEXT: vadd.vv v8, v8, v8 ; RV32-NEXT: vadd.vv v8, v8, v8
; RV32-NEXT: vor.vv v8, v12, v8 ; RV32-NEXT: vor.vv v8, v12, v8
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: bitreverse_nxv4i64: ; RV64-LABEL: bitreverse_nxv4i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, ma ; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, ma
; RV64-NEXT: vsrl.vx v12, v8, a0 ; RV64-NEXT: vsrl.vx v12, v8, a0
; RV64-NEXT: li a1, 40 ; RV64-NEXT: li a1, 40
; RV64-NEXT: vsrl.vx v16, v8, a1 ; RV64-NEXT: vsrl.vx v16, v8, a1
; RV64-NEXT: lui a2, 16 ; RV64-NEXT: lui a2, 16
; RV64-NEXT: addiw a2, a2, -256 ; RV64-NEXT: addiw a2, a2, -256
; RV64-NEXT: vand.vx v16, v16, a2 ; RV64-NEXT: vand.vx v16, v16, a2
; RV64-NEXT: vor.vv v12, v16, v12 ; RV64-NEXT: vor.vv v12, v16, v12
; RV64-NEXT: vsrl.vi v16, v8, 24 ; RV64-NEXT: vsrl.vi v16, v8, 24
; RV64-NEXT: lui a2, 4080 ; RV64-NEXT: lui a3, 4080
; RV64-NEXT: vand.vx v16, v16, a2 ; RV64-NEXT: vand.vx v16, v16, a3
; RV64-NEXT: vsrl.vi v20, v8, 8 ; RV64-NEXT: vsrl.vi v20, v8, 8
; RV64-NEXT: li a2, 255 ; RV64-NEXT: li a4, 255
; RV64-NEXT: slli a3, a2, 24 ; RV64-NEXT: slli a4, a4, 24
; RV64-NEXT: vand.vx v20, v20, a3 ; RV64-NEXT: vand.vx v20, v20, a4
; RV64-NEXT: vor.vv v16, v20, v16 ; RV64-NEXT: vor.vv v16, v20, v16
; RV64-NEXT: vor.vv v12, v16, v12 ; RV64-NEXT: vor.vv v12, v16, v12
; RV64-NEXT: vsll.vi v16, v8, 8 ; RV64-NEXT: vand.vx v16, v8, a3
; RV64-NEXT: slli a3, a2, 32 ; RV64-NEXT: vsll.vi v16, v16, 24
; RV64-NEXT: vand.vx v16, v16, a3 ; RV64-NEXT: vand.vx v20, v8, a4
; RV64-NEXT: vsll.vi v20, v8, 24 ; RV64-NEXT: vsll.vi v20, v20, 8
; RV64-NEXT: slli a3, a2, 40 ; RV64-NEXT: vor.vv v16, v16, v20
; RV64-NEXT: vand.vx v20, v20, a3
; RV64-NEXT: vor.vv v16, v20, v16
; RV64-NEXT: vsll.vx v20, v8, a0 ; RV64-NEXT: vsll.vx v20, v8, a0
; RV64-NEXT: vand.vx v8, v8, a2
; RV64-NEXT: vsll.vx v8, v8, a1 ; RV64-NEXT: vsll.vx v8, v8, a1
; RV64-NEXT: slli a0, a2, 48
; RV64-NEXT: vand.vx v8, v8, a0
; RV64-NEXT: vor.vv v8, v20, v8 ; RV64-NEXT: vor.vv v8, v20, v8
; RV64-NEXT: lui a0, %hi(.LCPI20_0) ; RV64-NEXT: lui a0, %hi(.LCPI20_0)
; RV64-NEXT: ld a0, %lo(.LCPI20_0)(a0) ; RV64-NEXT: ld a0, %lo(.LCPI20_0)(a0)
; RV64-NEXT: vor.vv v8, v8, v16 ; RV64-NEXT: vor.vv v8, v8, v16
; RV64-NEXT: vor.vv v8, v8, v12 ; RV64-NEXT: vor.vv v8, v8, v12
; RV64-NEXT: vsrl.vi v12, v8, 4 ; RV64-NEXT: vsrl.vi v12, v8, 4
; RV64-NEXT: vand.vx v12, v12, a0 ; RV64-NEXT: vand.vx v12, v12, a0
; RV64-NEXT: vand.vx v8, v8, a0 ; RV64-NEXT: vand.vx v8, v8, a0
Show All 20 Lines
declare <vscale x 4 x i64> @llvm.bitreverse.nxv4i64(<vscale x 4 x i64>) declare <vscale x 4 x i64> @llvm.bitreverse.nxv4i64(<vscale x 4 x i64>)
define <vscale x 8 x i64> @bitreverse_nxv8i64(<vscale x 8 x i64> %va) { define <vscale x 8 x i64> @bitreverse_nxv8i64(<vscale x 8 x i64> %va) {
; RV32-LABEL: bitreverse_nxv8i64: ; RV32-LABEL: bitreverse_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 4 ; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: sub sp, sp, a0 ; RV32-NEXT: sub sp, sp, a0
; RV32-NEXT: sw zero, 12(sp) ; RV32-NEXT: sw zero, 12(sp)
; RV32-NEXT: lui a0, 1044480 ; RV32-NEXT: lui a0, 1044480
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: lui a0, 4080 ; RV32-NEXT: lui a0, 61681
; RV32-NEXT: addi a0, a0, -241
; RV32-NEXT: sw a0, 12(sp) ; RV32-NEXT: sw a0, 12(sp)
; RV32-NEXT: sw zero, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: li a1, 255 ; RV32-NEXT: lui a0, 209715
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, a0, 819
; RV32-NEXT: lui a1, 16 ; RV32-NEXT: sw a0, 12(sp)
; RV32-NEXT: addi a1, a1, -256 ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: lui a0, 349525
; RV32-NEXT: lui a2, 61681 ; RV32-NEXT: addi a0, a0, 1365
; RV32-NEXT: addi a2, a2, -241 ; RV32-NEXT: sw a0, 12(sp)
; RV32-NEXT: sw a2, 12(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a2, 8(sp) ; RV32-NEXT: li a0, 56
; RV32-NEXT: lui a2, 209715 ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma
; RV32-NEXT: addi a2, a2, 819 ; RV32-NEXT: vsrl.vx v16, v8, a0
; RV32-NEXT: sw a2, 12(sp) ; RV32-NEXT: li a1, 40
; RV32-NEXT: sw a2, 8(sp) ; RV32-NEXT: vsrl.vx v24, v8, a1
; RV32-NEXT: lui a2, 349525 ; RV32-NEXT: lui a2, 16
; RV32-NEXT: addi a2, a2, 1365 ; RV32-NEXT: addi a2, a2, -256
; RV32-NEXT: sw a2, 12(sp) ; RV32-NEXT: vand.vx v24, v24, a2
; RV32-NEXT: sw a2, 8(sp)
; RV32-NEXT: li a2, 56
; RV32-NEXT: vsetvli a3, zero, e64, m8, ta, ma
; RV32-NEXT: li a3, 40
; RV32-NEXT: vsrl.vx v16, v8, a3
; RV32-NEXT: vand.vx v16, v16, a1
; RV32-NEXT: addi a1, sp, 8
; RV32-NEXT: vlse64.v v24, (a1), zero
; RV32-NEXT: vsrl.vx v0, v8, a2
; RV32-NEXT: vor.vv v16, v16, v0
; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: slli a4, a4, 3
; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vs8r.v v16, (a4) # Unknown-size Folded Spill
; RV32-NEXT: vsrl.vi v0, v8, 8
; RV32-NEXT: vand.vv v24, v0, v24
; RV32-NEXT: vsrl.vi v0, v8, 24
; RV32-NEXT: vand.vx v0, v0, a0
; RV32-NEXT: vlse64.v v16, (a1), zero
; RV32-NEXT: vor.vv v24, v24, v0
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8re8.v v0, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v24, v24, v0
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill
; RV32-NEXT: vsll.vx v24, v8, a3
; RV32-NEXT: vand.vv v16, v24, v16
; RV32-NEXT: vsll.vx v24, v8, a2
; RV32-NEXT: vlse64.v v0, (a1), zero
; RV32-NEXT: vor.vv v16, v24, v16 ; RV32-NEXT: vor.vv v16, v24, v16
; RV32-NEXT: addi a0, sp, 16 ; RV32-NEXT: addi a3, sp, 16
; RV32-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v16, (a3) # Unknown-size Folded Spill
; RV32-NEXT: vlse64.v v16, (a1), zero ; RV32-NEXT: vsrl.vi v0, v8, 24
; RV32-NEXT: vsll.vi v24, v8, 8 ; RV32-NEXT: addi a3, sp, 8
; RV32-NEXT: vand.vv v24, v24, v0 ; RV32-NEXT: vlse64.v v24, (a3), zero
; RV32-NEXT: lui a4, 4080
; RV32-NEXT: vand.vx v0, v0, a4
; RV32-NEXT: vsrl.vi v16, v8, 8
; RV32-NEXT: vand.vv v16, v16, v24
; RV32-NEXT: vor.vv v16, v16, v0
; RV32-NEXT: addi a5, sp, 16
; RV32-NEXT: vl8re8.v v0, (a5) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v16, v16, v0
; RV32-NEXT: addi a5, sp, 16
; RV32-NEXT: vs8r.v v16, (a5) # Unknown-size Folded Spill
; RV32-NEXT: vand.vx v0, v8, a2
; RV32-NEXT: vsll.vx v0, v0, a1
; RV32-NEXT: vsll.vx v16, v8, a0
; RV32-NEXT: vor.vv v0, v16, v0
; RV32-NEXT: vand.vv v16, v8, v24
; RV32-NEXT: vand.vx v8, v8, a4
; RV32-NEXT: vsll.vi v8, v8, 24 ; RV32-NEXT: vsll.vi v8, v8, 24
; RV32-NEXT: vand.vv v8, v8, v16 ; RV32-NEXT: vsll.vi v16, v16, 8
; RV32-NEXT: vor.vv v8, v8, v24 ; RV32-NEXT: vor.vv v8, v8, v16
; RV32-NEXT: vlse64.v v16, (a1), zero ; RV32-NEXT: vlse64.v v16, (a3), zero
; RV32-NEXT: vor.vv v8, v0, v8
; RV32-NEXT: addi a0, sp, 16 ; RV32-NEXT: addi a0, sp, 16
; RV32-NEXT: vl8re8.v v24, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8re8.v v24, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v8, v24, v8
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8re8.v v24, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v8, v8, v24 ; RV32-NEXT: vor.vv v8, v8, v24
; RV32-NEXT: vsrl.vi v24, v8, 4 ; RV32-NEXT: vsrl.vi v24, v8, 4
; RV32-NEXT: vand.vv v24, v24, v16 ; RV32-NEXT: vand.vv v24, v24, v16
; RV32-NEXT: vand.vv v8, v8, v16 ; RV32-NEXT: vand.vv v8, v8, v16
; RV32-NEXT: vlse64.v v16, (a1), zero ; RV32-NEXT: vlse64.v v16, (a3), zero
; RV32-NEXT: vsll.vi v8, v8, 4 ; RV32-NEXT: vsll.vi v8, v8, 4
; RV32-NEXT: vor.vv v8, v24, v8 ; RV32-NEXT: vor.vv v8, v24, v8
; RV32-NEXT: vsrl.vi v24, v8, 2 ; RV32-NEXT: vsrl.vi v24, v8, 2
; RV32-NEXT: vand.vv v24, v24, v16 ; RV32-NEXT: vand.vv v24, v24, v16
; RV32-NEXT: vand.vv v8, v8, v16 ; RV32-NEXT: vand.vv v8, v8, v16
; RV32-NEXT: vlse64.v v16, (a1), zero ; RV32-NEXT: vlse64.v v16, (a3), zero
; RV32-NEXT: vsll.vi v8, v8, 2 ; RV32-NEXT: vsll.vi v8, v8, 2
; RV32-NEXT: vor.vv v8, v24, v8 ; RV32-NEXT: vor.vv v8, v24, v8
; RV32-NEXT: vsrl.vi v24, v8, 1 ; RV32-NEXT: vsrl.vi v24, v8, 1
; RV32-NEXT: vand.vv v24, v24, v16 ; RV32-NEXT: vand.vv v24, v24, v16
; RV32-NEXT: vand.vv v8, v8, v16 ; RV32-NEXT: vand.vv v8, v8, v16
; RV32-NEXT: vadd.vv v8, v8, v8 ; RV32-NEXT: vadd.vv v8, v8, v8
; RV32-NEXT: vor.vv v8, v24, v8 ; RV32-NEXT: vor.vv v8, v24, v8
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 4 ; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add sp, sp, a0 ; RV32-NEXT: add sp, sp, a0
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: bitreverse_nxv8i64: ; RV64-LABEL: bitreverse_nxv8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma
; RV64-NEXT: vsrl.vx v16, v8, a0 ; RV64-NEXT: vsrl.vx v16, v8, a0
; RV64-NEXT: li a1, 40 ; RV64-NEXT: li a1, 40
; RV64-NEXT: vsrl.vx v24, v8, a1 ; RV64-NEXT: vsrl.vx v24, v8, a1
; RV64-NEXT: lui a2, 16 ; RV64-NEXT: lui a2, 16
; RV64-NEXT: addiw a2, a2, -256 ; RV64-NEXT: addiw a2, a2, -256
; RV64-NEXT: vand.vx v24, v24, a2 ; RV64-NEXT: vand.vx v24, v24, a2
; RV64-NEXT: vor.vv v16, v24, v16 ; RV64-NEXT: vor.vv v16, v24, v16
; RV64-NEXT: vsrl.vi v24, v8, 24 ; RV64-NEXT: vsrl.vi v24, v8, 24
; RV64-NEXT: lui a2, 4080 ; RV64-NEXT: lui a3, 4080
; RV64-NEXT: vand.vx v24, v24, a2 ; RV64-NEXT: vand.vx v24, v24, a3
; RV64-NEXT: vsrl.vi v0, v8, 8 ; RV64-NEXT: vsrl.vi v0, v8, 8
; RV64-NEXT: li a2, 255 ; RV64-NEXT: li a4, 255
; RV64-NEXT: slli a3, a2, 24 ; RV64-NEXT: slli a4, a4, 24
; RV64-NEXT: vand.vx v0, v0, a3 ; RV64-NEXT: vand.vx v0, v0, a4
; RV64-NEXT: vor.vv v24, v0, v24 ; RV64-NEXT: vor.vv v24, v0, v24
; RV64-NEXT: vor.vv v16, v24, v16 ; RV64-NEXT: vor.vv v16, v24, v16
; RV64-NEXT: vsll.vi v24, v8, 8 ; RV64-NEXT: vand.vx v24, v8, a3
; RV64-NEXT: slli a3, a2, 32 ; RV64-NEXT: vsll.vi v24, v24, 24
; RV64-NEXT: vand.vx v24, v24, a3 ; RV64-NEXT: vand.vx v0, v8, a4
; RV64-NEXT: vsll.vi v0, v8, 24 ; RV64-NEXT: vsll.vi v0, v0, 8
; RV64-NEXT: slli a3, a2, 40 ; RV64-NEXT: vor.vv v24, v24, v0
; RV64-NEXT: vand.vx v0, v0, a3
; RV64-NEXT: vor.vv v24, v0, v24
; RV64-NEXT: vsll.vx v0, v8, a0 ; RV64-NEXT: vsll.vx v0, v8, a0
; RV64-NEXT: vand.vx v8, v8, a2
; RV64-NEXT: vsll.vx v8, v8, a1 ; RV64-NEXT: vsll.vx v8, v8, a1
; RV64-NEXT: slli a0, a2, 48
; RV64-NEXT: vand.vx v8, v8, a0
; RV64-NEXT: vor.vv v8, v0, v8 ; RV64-NEXT: vor.vv v8, v0, v8
; RV64-NEXT: lui a0, %hi(.LCPI21_0) ; RV64-NEXT: lui a0, %hi(.LCPI21_0)
; RV64-NEXT: ld a0, %lo(.LCPI21_0)(a0) ; RV64-NEXT: ld a0, %lo(.LCPI21_0)(a0)
; RV64-NEXT: vor.vv v8, v8, v24 ; RV64-NEXT: vor.vv v8, v8, v24
; RV64-NEXT: vor.vv v8, v8, v16 ; RV64-NEXT: vor.vv v8, v8, v16
; RV64-NEXT: vsrl.vi v16, v8, 4 ; RV64-NEXT: vsrl.vi v16, v8, 4
; RV64-NEXT: vand.vx v16, v16, a0 ; RV64-NEXT: vand.vx v16, v16, a0
; RV64-NEXT: vand.vx v8, v8, a0 ; RV64-NEXT: vand.vx v8, v8, a0
Show All 21 Lines

llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll

Show First 20 Lines • Show All 84 Lines • ▼ Show 20 Lines
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; RV32-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
; RV32-NEXT: vsrl.vi v9, v8, 8 ; RV32-NEXT: vsrl.vi v9, v8, 8
; RV32-NEXT: lui a0, 16 ; RV32-NEXT: lui a0, 16
; RV32-NEXT: addi a0, a0, -256 ; RV32-NEXT: addi a0, a0, -256
; RV32-NEXT: vand.vx v9, v9, a0 ; RV32-NEXT: vand.vx v9, v9, a0
; RV32-NEXT: vsrl.vi v10, v8, 24 ; RV32-NEXT: vsrl.vi v10, v8, 24
; RV32-NEXT: vor.vv v9, v9, v10 ; RV32-NEXT: vor.vv v9, v9, v10
; RV32-NEXT: vsll.vi v10, v8, 8 ; RV32-NEXT: vand.vx v10, v8, a0
; RV32-NEXT: lui a0, 4080 ; RV32-NEXT: vsll.vi v10, v10, 8
; RV32-NEXT: vand.vx v10, v10, a0
; RV32-NEXT: vsll.vi v8, v8, 24 ; RV32-NEXT: vsll.vi v8, v8, 24
; RV32-NEXT: vor.vv v8, v8, v10 ; RV32-NEXT: vor.vv v8, v8, v10
; RV32-NEXT: vor.vv v8, v8, v9 ; RV32-NEXT: vor.vv v8, v8, v9
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: bswap_nxv1i32: ; RV64-LABEL: bswap_nxv1i32:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; RV64-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
; RV64-NEXT: vsrl.vi v9, v8, 8 ; RV64-NEXT: vsrl.vi v9, v8, 8
; RV64-NEXT: lui a0, 16 ; RV64-NEXT: lui a0, 16
; RV64-NEXT: addiw a0, a0, -256 ; RV64-NEXT: addiw a0, a0, -256
; RV64-NEXT: vand.vx v9, v9, a0 ; RV64-NEXT: vand.vx v9, v9, a0
; RV64-NEXT: vsrl.vi v10, v8, 24 ; RV64-NEXT: vsrl.vi v10, v8, 24
; RV64-NEXT: vor.vv v9, v9, v10 ; RV64-NEXT: vor.vv v9, v9, v10
; RV64-NEXT: vsll.vi v10, v8, 8 ; RV64-NEXT: vand.vx v10, v8, a0
; RV64-NEXT: lui a0, 4080 ; RV64-NEXT: vsll.vi v10, v10, 8
; RV64-NEXT: vand.vx v10, v10, a0
; RV64-NEXT: vsll.vi v8, v8, 24 ; RV64-NEXT: vsll.vi v8, v8, 24
; RV64-NEXT: vor.vv v8, v8, v10 ; RV64-NEXT: vor.vv v8, v8, v10
; RV64-NEXT: vor.vv v8, v8, v9 ; RV64-NEXT: vor.vv v8, v8, v9
; RV64-NEXT: ret ; RV64-NEXT: ret
%a = call <vscale x 1 x i32> @llvm.bswap.nxv1i32(<vscale x 1 x i32> %va) %a = call <vscale x 1 x i32> @llvm.bswap.nxv1i32(<vscale x 1 x i32> %va)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.bswap.nxv1i32(<vscale x 1 x i32>) declare <vscale x 1 x i32> @llvm.bswap.nxv1i32(<vscale x 1 x i32>)
define <vscale x 2 x i32> @bswap_nxv2i32(<vscale x 2 x i32> %va) { define <vscale x 2 x i32> @bswap_nxv2i32(<vscale x 2 x i32> %va) {
; RV32-LABEL: bswap_nxv2i32: ; RV32-LABEL: bswap_nxv2i32:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a0, zero, e32, m1, ta, ma ; RV32-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; RV32-NEXT: vsrl.vi v9, v8, 8 ; RV32-NEXT: vsrl.vi v9, v8, 8
; RV32-NEXT: lui a0, 16 ; RV32-NEXT: lui a0, 16
; RV32-NEXT: addi a0, a0, -256 ; RV32-NEXT: addi a0, a0, -256
; RV32-NEXT: vand.vx v9, v9, a0 ; RV32-NEXT: vand.vx v9, v9, a0
; RV32-NEXT: vsrl.vi v10, v8, 24 ; RV32-NEXT: vsrl.vi v10, v8, 24
; RV32-NEXT: vor.vv v9, v9, v10 ; RV32-NEXT: vor.vv v9, v9, v10
; RV32-NEXT: vsll.vi v10, v8, 8 ; RV32-NEXT: vand.vx v10, v8, a0
; RV32-NEXT: lui a0, 4080 ; RV32-NEXT: vsll.vi v10, v10, 8
; RV32-NEXT: vand.vx v10, v10, a0
; RV32-NEXT: vsll.vi v8, v8, 24 ; RV32-NEXT: vsll.vi v8, v8, 24
; RV32-NEXT: vor.vv v8, v8, v10 ; RV32-NEXT: vor.vv v8, v8, v10
; RV32-NEXT: vor.vv v8, v8, v9 ; RV32-NEXT: vor.vv v8, v8, v9
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: bswap_nxv2i32: ; RV64-LABEL: bswap_nxv2i32:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a0, zero, e32, m1, ta, ma ; RV64-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; RV64-NEXT: vsrl.vi v9, v8, 8 ; RV64-NEXT: vsrl.vi v9, v8, 8
; RV64-NEXT: lui a0, 16 ; RV64-NEXT: lui a0, 16
; RV64-NEXT: addiw a0, a0, -256 ; RV64-NEXT: addiw a0, a0, -256
; RV64-NEXT: vand.vx v9, v9, a0 ; RV64-NEXT: vand.vx v9, v9, a0
; RV64-NEXT: vsrl.vi v10, v8, 24 ; RV64-NEXT: vsrl.vi v10, v8, 24
; RV64-NEXT: vor.vv v9, v9, v10 ; RV64-NEXT: vor.vv v9, v9, v10
; RV64-NEXT: vsll.vi v10, v8, 8 ; RV64-NEXT: vand.vx v10, v8, a0
; RV64-NEXT: lui a0, 4080 ; RV64-NEXT: vsll.vi v10, v10, 8
; RV64-NEXT: vand.vx v10, v10, a0
; RV64-NEXT: vsll.vi v8, v8, 24 ; RV64-NEXT: vsll.vi v8, v8, 24
; RV64-NEXT: vor.vv v8, v8, v10 ; RV64-NEXT: vor.vv v8, v8, v10
; RV64-NEXT: vor.vv v8, v8, v9 ; RV64-NEXT: vor.vv v8, v8, v9
; RV64-NEXT: ret ; RV64-NEXT: ret
%a = call <vscale x 2 x i32> @llvm.bswap.nxv2i32(<vscale x 2 x i32> %va) %a = call <vscale x 2 x i32> @llvm.bswap.nxv2i32(<vscale x 2 x i32> %va)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.bswap.nxv2i32(<vscale x 2 x i32>) declare <vscale x 2 x i32> @llvm.bswap.nxv2i32(<vscale x 2 x i32>)
define <vscale x 4 x i32> @bswap_nxv4i32(<vscale x 4 x i32> %va) { define <vscale x 4 x i32> @bswap_nxv4i32(<vscale x 4 x i32> %va) {
; RV32-LABEL: bswap_nxv4i32: ; RV32-LABEL: bswap_nxv4i32:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; RV32-NEXT: vsrl.vi v10, v8, 8 ; RV32-NEXT: vsrl.vi v10, v8, 8
; RV32-NEXT: lui a0, 16 ; RV32-NEXT: lui a0, 16
; RV32-NEXT: addi a0, a0, -256 ; RV32-NEXT: addi a0, a0, -256
; RV32-NEXT: vand.vx v10, v10, a0 ; RV32-NEXT: vand.vx v10, v10, a0
; RV32-NEXT: vsrl.vi v12, v8, 24 ; RV32-NEXT: vsrl.vi v12, v8, 24
; RV32-NEXT: vor.vv v10, v10, v12 ; RV32-NEXT: vor.vv v10, v10, v12
; RV32-NEXT: vsll.vi v12, v8, 8 ; RV32-NEXT: vand.vx v12, v8, a0
; RV32-NEXT: lui a0, 4080 ; RV32-NEXT: vsll.vi v12, v12, 8
; RV32-NEXT: vand.vx v12, v12, a0
; RV32-NEXT: vsll.vi v8, v8, 24 ; RV32-NEXT: vsll.vi v8, v8, 24
; RV32-NEXT: vor.vv v8, v8, v12 ; RV32-NEXT: vor.vv v8, v8, v12
; RV32-NEXT: vor.vv v8, v8, v10 ; RV32-NEXT: vor.vv v8, v8, v10
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: bswap_nxv4i32: ; RV64-LABEL: bswap_nxv4i32:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; RV64-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; RV64-NEXT: vsrl.vi v10, v8, 8 ; RV64-NEXT: vsrl.vi v10, v8, 8
; RV64-NEXT: lui a0, 16 ; RV64-NEXT: lui a0, 16
; RV64-NEXT: addiw a0, a0, -256 ; RV64-NEXT: addiw a0, a0, -256
; RV64-NEXT: vand.vx v10, v10, a0 ; RV64-NEXT: vand.vx v10, v10, a0
; RV64-NEXT: vsrl.vi v12, v8, 24 ; RV64-NEXT: vsrl.vi v12, v8, 24
; RV64-NEXT: vor.vv v10, v10, v12 ; RV64-NEXT: vor.vv v10, v10, v12
; RV64-NEXT: vsll.vi v12, v8, 8 ; RV64-NEXT: vand.vx v12, v8, a0
; RV64-NEXT: lui a0, 4080 ; RV64-NEXT: vsll.vi v12, v12, 8
; RV64-NEXT: vand.vx v12, v12, a0
; RV64-NEXT: vsll.vi v8, v8, 24 ; RV64-NEXT: vsll.vi v8, v8, 24
; RV64-NEXT: vor.vv v8, v8, v12 ; RV64-NEXT: vor.vv v8, v8, v12
; RV64-NEXT: vor.vv v8, v8, v10 ; RV64-NEXT: vor.vv v8, v8, v10
; RV64-NEXT: ret ; RV64-NEXT: ret
%a = call <vscale x 4 x i32> @llvm.bswap.nxv4i32(<vscale x 4 x i32> %va) %a = call <vscale x 4 x i32> @llvm.bswap.nxv4i32(<vscale x 4 x i32> %va)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.bswap.nxv4i32(<vscale x 4 x i32>) declare <vscale x 4 x i32> @llvm.bswap.nxv4i32(<vscale x 4 x i32>)
define <vscale x 8 x i32> @bswap_nxv8i32(<vscale x 8 x i32> %va) { define <vscale x 8 x i32> @bswap_nxv8i32(<vscale x 8 x i32> %va) {
; RV32-LABEL: bswap_nxv8i32: ; RV32-LABEL: bswap_nxv8i32:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; RV32-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; RV32-NEXT: vsrl.vi v12, v8, 8 ; RV32-NEXT: vsrl.vi v12, v8, 8
; RV32-NEXT: lui a0, 16 ; RV32-NEXT: lui a0, 16
; RV32-NEXT: addi a0, a0, -256 ; RV32-NEXT: addi a0, a0, -256
; RV32-NEXT: vand.vx v12, v12, a0 ; RV32-NEXT: vand.vx v12, v12, a0
; RV32-NEXT: vsrl.vi v16, v8, 24 ; RV32-NEXT: vsrl.vi v16, v8, 24
; RV32-NEXT: vor.vv v12, v12, v16 ; RV32-NEXT: vor.vv v12, v12, v16
; RV32-NEXT: vsll.vi v16, v8, 8 ; RV32-NEXT: vand.vx v16, v8, a0
; RV32-NEXT: lui a0, 4080 ; RV32-NEXT: vsll.vi v16, v16, 8
; RV32-NEXT: vand.vx v16, v16, a0
; RV32-NEXT: vsll.vi v8, v8, 24 ; RV32-NEXT: vsll.vi v8, v8, 24
; RV32-NEXT: vor.vv v8, v8, v16 ; RV32-NEXT: vor.vv v8, v8, v16
; RV32-NEXT: vor.vv v8, v8, v12 ; RV32-NEXT: vor.vv v8, v8, v12
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: bswap_nxv8i32: ; RV64-LABEL: bswap_nxv8i32:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; RV64-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; RV64-NEXT: vsrl.vi v12, v8, 8 ; RV64-NEXT: vsrl.vi v12, v8, 8
; RV64-NEXT: lui a0, 16 ; RV64-NEXT: lui a0, 16
; RV64-NEXT: addiw a0, a0, -256 ; RV64-NEXT: addiw a0, a0, -256
; RV64-NEXT: vand.vx v12, v12, a0 ; RV64-NEXT: vand.vx v12, v12, a0
; RV64-NEXT: vsrl.vi v16, v8, 24 ; RV64-NEXT: vsrl.vi v16, v8, 24
; RV64-NEXT: vor.vv v12, v12, v16 ; RV64-NEXT: vor.vv v12, v12, v16
; RV64-NEXT: vsll.vi v16, v8, 8 ; RV64-NEXT: vand.vx v16, v8, a0
; RV64-NEXT: lui a0, 4080 ; RV64-NEXT: vsll.vi v16, v16, 8
; RV64-NEXT: vand.vx v16, v16, a0
; RV64-NEXT: vsll.vi v8, v8, 24 ; RV64-NEXT: vsll.vi v8, v8, 24
; RV64-NEXT: vor.vv v8, v8, v16 ; RV64-NEXT: vor.vv v8, v8, v16
; RV64-NEXT: vor.vv v8, v8, v12 ; RV64-NEXT: vor.vv v8, v8, v12
; RV64-NEXT: ret ; RV64-NEXT: ret
%a = call <vscale x 8 x i32> @llvm.bswap.nxv8i32(<vscale x 8 x i32> %va) %a = call <vscale x 8 x i32> @llvm.bswap.nxv8i32(<vscale x 8 x i32> %va)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.bswap.nxv8i32(<vscale x 8 x i32>) declare <vscale x 8 x i32> @llvm.bswap.nxv8i32(<vscale x 8 x i32>)
define <vscale x 16 x i32> @bswap_nxv16i32(<vscale x 16 x i32> %va) { define <vscale x 16 x i32> @bswap_nxv16i32(<vscale x 16 x i32> %va) {
; RV32-LABEL: bswap_nxv16i32: ; RV32-LABEL: bswap_nxv16i32:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a0, zero, e32, m8, ta, ma ; RV32-NEXT: vsetvli a0, zero, e32, m8, ta, ma
; RV32-NEXT: vsrl.vi v16, v8, 8 ; RV32-NEXT: vsrl.vi v16, v8, 8
; RV32-NEXT: lui a0, 16 ; RV32-NEXT: lui a0, 16
; RV32-NEXT: addi a0, a0, -256 ; RV32-NEXT: addi a0, a0, -256
; RV32-NEXT: vand.vx v16, v16, a0 ; RV32-NEXT: vand.vx v16, v16, a0
; RV32-NEXT: vsrl.vi v24, v8, 24 ; RV32-NEXT: vsrl.vi v24, v8, 24
; RV32-NEXT: vor.vv v16, v16, v24 ; RV32-NEXT: vor.vv v16, v16, v24
; RV32-NEXT: vsll.vi v24, v8, 8 ; RV32-NEXT: vand.vx v24, v8, a0
; RV32-NEXT: lui a0, 4080 ; RV32-NEXT: vsll.vi v24, v24, 8
; RV32-NEXT: vand.vx v24, v24, a0
; RV32-NEXT: vsll.vi v8, v8, 24 ; RV32-NEXT: vsll.vi v8, v8, 24
; RV32-NEXT: vor.vv v8, v8, v24 ; RV32-NEXT: vor.vv v8, v8, v24
; RV32-NEXT: vor.vv v8, v8, v16 ; RV32-NEXT: vor.vv v8, v8, v16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: bswap_nxv16i32: ; RV64-LABEL: bswap_nxv16i32:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a0, zero, e32, m8, ta, ma ; RV64-NEXT: vsetvli a0, zero, e32, m8, ta, ma
; RV64-NEXT: vsrl.vi v16, v8, 8 ; RV64-NEXT: vsrl.vi v16, v8, 8
; RV64-NEXT: lui a0, 16 ; RV64-NEXT: lui a0, 16
; RV64-NEXT: addiw a0, a0, -256 ; RV64-NEXT: addiw a0, a0, -256
; RV64-NEXT: vand.vx v16, v16, a0 ; RV64-NEXT: vand.vx v16, v16, a0
; RV64-NEXT: vsrl.vi v24, v8, 24 ; RV64-NEXT: vsrl.vi v24, v8, 24
; RV64-NEXT: vor.vv v16, v16, v24 ; RV64-NEXT: vor.vv v16, v16, v24
; RV64-NEXT: vsll.vi v24, v8, 8 ; RV64-NEXT: vand.vx v24, v8, a0
; RV64-NEXT: lui a0, 4080 ; RV64-NEXT: vsll.vi v24, v24, 8
; RV64-NEXT: vand.vx v24, v24, a0
; RV64-NEXT: vsll.vi v8, v8, 24 ; RV64-NEXT: vsll.vi v8, v8, 24
; RV64-NEXT: vor.vv v8, v8, v24 ; RV64-NEXT: vor.vv v8, v8, v24
; RV64-NEXT: vor.vv v8, v8, v16 ; RV64-NEXT: vor.vv v8, v8, v16
; RV64-NEXT: ret ; RV64-NEXT: ret
%a = call <vscale x 16 x i32> @llvm.bswap.nxv16i32(<vscale x 16 x i32> %va) %a = call <vscale x 16 x i32> @llvm.bswap.nxv16i32(<vscale x 16 x i32> %va)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.bswap.nxv16i32(<vscale x 16 x i32>) declare <vscale x 16 x i32> @llvm.bswap.nxv16i32(<vscale x 16 x i32>)
define <vscale x 1 x i64> @bswap_nxv1i64(<vscale x 1 x i64> %va) { define <vscale x 1 x i64> @bswap_nxv1i64(<vscale x 1 x i64> %va) {
; RV32-LABEL: bswap_nxv1i64: ; RV32-LABEL: bswap_nxv1i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw zero, 12(sp) ; RV32-NEXT: sw zero, 12(sp)
; RV32-NEXT: lui a0, 1044480 ; RV32-NEXT: lui a0, 1044480
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: lui a0, 4080 ; RV32-NEXT: li a0, 56
; RV32-NEXT: sw a0, 12(sp) ; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma
; RV32-NEXT: sw zero, 8(sp) ; RV32-NEXT: vsrl.vx v9, v8, a0
; RV32-NEXT: li a1, 255 ; RV32-NEXT: li a1, 40
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: vsrl.vx v10, v8, a1
; RV32-NEXT: lui a1, 16 ; RV32-NEXT: lui a2, 16
; RV32-NEXT: addi a1, a1, -256 ; RV32-NEXT: addi a2, a2, -256
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: vand.vx v10, v10, a2
; RV32-NEXT: li a2, 56
; RV32-NEXT: vsetvli a3, zero, e64, m1, ta, ma
; RV32-NEXT: vsrl.vx v9, v8, a2
; RV32-NEXT: li a3, 40
; RV32-NEXT: vsrl.vx v10, v8, a3
; RV32-NEXT: vand.vx v10, v10, a1
; RV32-NEXT: vor.vv v9, v10, v9 ; RV32-NEXT: vor.vv v9, v10, v9
; RV32-NEXT: addi a1, sp, 8 ; RV32-NEXT: vsrl.vi v10, v8, 24
; RV32-NEXT: vlse64.v v10, (a1), zero ; RV32-NEXT: addi a3, sp, 8
; RV32-NEXT: vsrl.vi v11, v8, 24 ; RV32-NEXT: vlse64.v v11, (a3), zero
; RV32-NEXT: vand.vx v11, v11, a0 ; RV32-NEXT: lui a3, 4080
; RV32-NEXT: vand.vx v10, v10, a3
; RV32-NEXT: vsrl.vi v12, v8, 8 ; RV32-NEXT: vsrl.vi v12, v8, 8
; RV32-NEXT: vand.vv v10, v12, v10 ; RV32-NEXT: vand.vv v12, v12, v11
; RV32-NEXT: vor.vv v10, v10, v11 ; RV32-NEXT: vor.vv v10, v12, v10
; RV32-NEXT: vlse64.v v11, (a1), zero
; RV32-NEXT: vor.vv v9, v10, v9 ; RV32-NEXT: vor.vv v9, v10, v9
; RV32-NEXT: vsll.vx v10, v8, a2 ; RV32-NEXT: vsll.vx v10, v8, a0
; RV32-NEXT: vsll.vx v12, v8, a3 ; RV32-NEXT: vand.vx v12, v8, a2
; RV32-NEXT: vand.vv v11, v12, v11 ; RV32-NEXT: vsll.vx v12, v12, a1
; RV32-NEXT: vlse64.v v12, (a1), zero ; RV32-NEXT: vor.vv v10, v10, v12
; RV32-NEXT: vor.vv v10, v10, v11 ; RV32-NEXT: vand.vx v12, v8, a3
; RV32-NEXT: vlse64.v v11, (a1), zero ; RV32-NEXT: vsll.vi v12, v12, 24
; RV32-NEXT: vsll.vi v13, v8, 8
; RV32-NEXT: vand.vv v12, v13, v12
; RV32-NEXT: vsll.vi v8, v8, 24
; RV32-NEXT: vand.vv v8, v8, v11 ; RV32-NEXT: vand.vv v8, v8, v11
; RV32-NEXT: vor.vv v8, v8, v12 ; RV32-NEXT: vsll.vi v8, v8, 8
; RV32-NEXT: vor.vv v8, v12, v8
; RV32-NEXT: vor.vv v8, v10, v8 ; RV32-NEXT: vor.vv v8, v10, v8
; RV32-NEXT: vor.vv v8, v8, v9 ; RV32-NEXT: vor.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: bswap_nxv1i64: ; RV64-LABEL: bswap_nxv1i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, ma ; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, ma
; RV64-NEXT: vsrl.vx v9, v8, a0 ; RV64-NEXT: vsrl.vx v9, v8, a0
; RV64-NEXT: li a1, 40 ; RV64-NEXT: li a1, 40
; RV64-NEXT: vsrl.vx v10, v8, a1 ; RV64-NEXT: vsrl.vx v10, v8, a1
; RV64-NEXT: lui a2, 16 ; RV64-NEXT: lui a2, 16
; RV64-NEXT: addiw a2, a2, -256 ; RV64-NEXT: addiw a2, a2, -256
; RV64-NEXT: vand.vx v10, v10, a2 ; RV64-NEXT: vand.vx v10, v10, a2
; RV64-NEXT: vor.vv v9, v10, v9 ; RV64-NEXT: vor.vv v9, v10, v9
; RV64-NEXT: vsrl.vi v10, v8, 24 ; RV64-NEXT: vsrl.vi v10, v8, 24
; RV64-NEXT: lui a2, 4080 ; RV64-NEXT: lui a3, 4080
; RV64-NEXT: vand.vx v10, v10, a2 ; RV64-NEXT: vand.vx v10, v10, a3
; RV64-NEXT: vsrl.vi v11, v8, 8 ; RV64-NEXT: vsrl.vi v11, v8, 8
; RV64-NEXT: li a2, 255 ; RV64-NEXT: li a4, 255
; RV64-NEXT: slli a3, a2, 24 ; RV64-NEXT: slli a4, a4, 24
; RV64-NEXT: vand.vx v11, v11, a3 ; RV64-NEXT: vand.vx v11, v11, a4
; RV64-NEXT: vor.vv v10, v11, v10 ; RV64-NEXT: vor.vv v10, v11, v10
; RV64-NEXT: vor.vv v9, v10, v9 ; RV64-NEXT: vor.vv v9, v10, v9
; RV64-NEXT: vsll.vi v10, v8, 8 ; RV64-NEXT: vand.vx v10, v8, a3
; RV64-NEXT: slli a3, a2, 32 ; RV64-NEXT: vsll.vi v10, v10, 24
; RV64-NEXT: vand.vx v10, v10, a3 ; RV64-NEXT: vand.vx v11, v8, a4
; RV64-NEXT: vsll.vi v11, v8, 24 ; RV64-NEXT: vsll.vi v11, v11, 8
; RV64-NEXT: slli a3, a2, 40 ; RV64-NEXT: vor.vv v10, v10, v11
; RV64-NEXT: vand.vx v11, v11, a3
; RV64-NEXT: vor.vv v10, v11, v10
; RV64-NEXT: vsll.vx v11, v8, a0 ; RV64-NEXT: vsll.vx v11, v8, a0
; RV64-NEXT: vand.vx v8, v8, a2
; RV64-NEXT: vsll.vx v8, v8, a1 ; RV64-NEXT: vsll.vx v8, v8, a1
; RV64-NEXT: slli a0, a2, 48
; RV64-NEXT: vand.vx v8, v8, a0
; RV64-NEXT: vor.vv v8, v11, v8 ; RV64-NEXT: vor.vv v8, v11, v8
; RV64-NEXT: vor.vv v8, v8, v10 ; RV64-NEXT: vor.vv v8, v8, v10
; RV64-NEXT: vor.vv v8, v8, v9 ; RV64-NEXT: vor.vv v8, v8, v9
; RV64-NEXT: ret ; RV64-NEXT: ret
%a = call <vscale x 1 x i64> @llvm.bswap.nxv1i64(<vscale x 1 x i64> %va) %a = call <vscale x 1 x i64> @llvm.bswap.nxv1i64(<vscale x 1 x i64> %va)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.bswap.nxv1i64(<vscale x 1 x i64>) declare <vscale x 1 x i64> @llvm.bswap.nxv1i64(<vscale x 1 x i64>)
define <vscale x 2 x i64> @bswap_nxv2i64(<vscale x 2 x i64> %va) { define <vscale x 2 x i64> @bswap_nxv2i64(<vscale x 2 x i64> %va) {
; RV32-LABEL: bswap_nxv2i64: ; RV32-LABEL: bswap_nxv2i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw zero, 12(sp) ; RV32-NEXT: sw zero, 12(sp)
; RV32-NEXT: lui a0, 1044480 ; RV32-NEXT: lui a0, 1044480
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: lui a0, 4080 ; RV32-NEXT: li a0, 56
; RV32-NEXT: sw a0, 12(sp) ; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma
; RV32-NEXT: sw zero, 8(sp) ; RV32-NEXT: vsrl.vx v10, v8, a0
; RV32-NEXT: li a1, 255 ; RV32-NEXT: li a1, 40
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: vsrl.vx v12, v8, a1
; RV32-NEXT: lui a1, 16 ; RV32-NEXT: lui a2, 16
; RV32-NEXT: addi a1, a1, -256 ; RV32-NEXT: addi a2, a2, -256
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: vand.vx v12, v12, a2
; RV32-NEXT: li a2, 56
; RV32-NEXT: vsetvli a3, zero, e64, m2, ta, ma
; RV32-NEXT: vsrl.vx v10, v8, a2
; RV32-NEXT: li a3, 40
; RV32-NEXT: vsrl.vx v12, v8, a3
; RV32-NEXT: vand.vx v12, v12, a1
; RV32-NEXT: vor.vv v10, v12, v10 ; RV32-NEXT: vor.vv v10, v12, v10
; RV32-NEXT: addi a1, sp, 8 ; RV32-NEXT: vsrl.vi v12, v8, 24
; RV32-NEXT: vlse64.v v12, (a1), zero ; RV32-NEXT: addi a3, sp, 8
; RV32-NEXT: vsrl.vi v14, v8, 24 ; RV32-NEXT: vlse64.v v14, (a3), zero
; RV32-NEXT: vand.vx v14, v14, a0 ; RV32-NEXT: lui a3, 4080
; RV32-NEXT: vand.vx v12, v12, a3
; RV32-NEXT: vsrl.vi v16, v8, 8 ; RV32-NEXT: vsrl.vi v16, v8, 8
; RV32-NEXT: vand.vv v12, v16, v12 ; RV32-NEXT: vand.vv v16, v16, v14
; RV32-NEXT: vor.vv v12, v12, v14 ; RV32-NEXT: vor.vv v12, v16, v12
; RV32-NEXT: vlse64.v v14, (a1), zero
; RV32-NEXT: vor.vv v10, v12, v10 ; RV32-NEXT: vor.vv v10, v12, v10
; RV32-NEXT: vsll.vx v12, v8, a2 ; RV32-NEXT: vsll.vx v12, v8, a0
; RV32-NEXT: vsll.vx v16, v8, a3 ; RV32-NEXT: vand.vx v16, v8, a2
; RV32-NEXT: vand.vv v14, v16, v14 ; RV32-NEXT: vsll.vx v16, v16, a1
; RV32-NEXT: vlse64.v v16, (a1), zero ; RV32-NEXT: vor.vv v12, v12, v16
; RV32-NEXT: vor.vv v12, v12, v14 ; RV32-NEXT: vand.vx v16, v8, a3
; RV32-NEXT: vlse64.v v14, (a1), zero ; RV32-NEXT: vsll.vi v16, v16, 24
; RV32-NEXT: vsll.vi v18, v8, 8
; RV32-NEXT: vand.vv v16, v18, v16
; RV32-NEXT: vsll.vi v8, v8, 24
; RV32-NEXT: vand.vv v8, v8, v14 ; RV32-NEXT: vand.vv v8, v8, v14
; RV32-NEXT: vor.vv v8, v8, v16 ; RV32-NEXT: vsll.vi v8, v8, 8
; RV32-NEXT: vor.vv v8, v16, v8
; RV32-NEXT: vor.vv v8, v12, v8 ; RV32-NEXT: vor.vv v8, v12, v8
; RV32-NEXT: vor.vv v8, v8, v10 ; RV32-NEXT: vor.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: bswap_nxv2i64: ; RV64-LABEL: bswap_nxv2i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, ma ; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, ma
; RV64-NEXT: vsrl.vx v10, v8, a0 ; RV64-NEXT: vsrl.vx v10, v8, a0
; RV64-NEXT: li a1, 40 ; RV64-NEXT: li a1, 40
; RV64-NEXT: vsrl.vx v12, v8, a1 ; RV64-NEXT: vsrl.vx v12, v8, a1
; RV64-NEXT: lui a2, 16 ; RV64-NEXT: lui a2, 16
; RV64-NEXT: addiw a2, a2, -256 ; RV64-NEXT: addiw a2, a2, -256
; RV64-NEXT: vand.vx v12, v12, a2 ; RV64-NEXT: vand.vx v12, v12, a2
; RV64-NEXT: vor.vv v10, v12, v10 ; RV64-NEXT: vor.vv v10, v12, v10
; RV64-NEXT: vsrl.vi v12, v8, 24 ; RV64-NEXT: vsrl.vi v12, v8, 24
; RV64-NEXT: lui a2, 4080 ; RV64-NEXT: lui a3, 4080
; RV64-NEXT: vand.vx v12, v12, a2 ; RV64-NEXT: vand.vx v12, v12, a3
; RV64-NEXT: vsrl.vi v14, v8, 8 ; RV64-NEXT: vsrl.vi v14, v8, 8
; RV64-NEXT: li a2, 255 ; RV64-NEXT: li a4, 255
; RV64-NEXT: slli a3, a2, 24 ; RV64-NEXT: slli a4, a4, 24
; RV64-NEXT: vand.vx v14, v14, a3 ; RV64-NEXT: vand.vx v14, v14, a4
; RV64-NEXT: vor.vv v12, v14, v12 ; RV64-NEXT: vor.vv v12, v14, v12
; RV64-NEXT: vor.vv v10, v12, v10 ; RV64-NEXT: vor.vv v10, v12, v10
; RV64-NEXT: vsll.vi v12, v8, 8 ; RV64-NEXT: vand.vx v12, v8, a3
; RV64-NEXT: slli a3, a2, 32 ; RV64-NEXT: vsll.vi v12, v12, 24
; RV64-NEXT: vand.vx v12, v12, a3 ; RV64-NEXT: vand.vx v14, v8, a4
; RV64-NEXT: vsll.vi v14, v8, 24 ; RV64-NEXT: vsll.vi v14, v14, 8
; RV64-NEXT: slli a3, a2, 40 ; RV64-NEXT: vor.vv v12, v12, v14
; RV64-NEXT: vand.vx v14, v14, a3
; RV64-NEXT: vor.vv v12, v14, v12
; RV64-NEXT: vsll.vx v14, v8, a0 ; RV64-NEXT: vsll.vx v14, v8, a0
; RV64-NEXT: vand.vx v8, v8, a2
; RV64-NEXT: vsll.vx v8, v8, a1 ; RV64-NEXT: vsll.vx v8, v8, a1
; RV64-NEXT: slli a0, a2, 48
; RV64-NEXT: vand.vx v8, v8, a0
; RV64-NEXT: vor.vv v8, v14, v8 ; RV64-NEXT: vor.vv v8, v14, v8
; RV64-NEXT: vor.vv v8, v8, v12 ; RV64-NEXT: vor.vv v8, v8, v12
; RV64-NEXT: vor.vv v8, v8, v10 ; RV64-NEXT: vor.vv v8, v8, v10
; RV64-NEXT: ret ; RV64-NEXT: ret
%a = call <vscale x 2 x i64> @llvm.bswap.nxv2i64(<vscale x 2 x i64> %va) %a = call <vscale x 2 x i64> @llvm.bswap.nxv2i64(<vscale x 2 x i64> %va)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.bswap.nxv2i64(<vscale x 2 x i64>) declare <vscale x 2 x i64> @llvm.bswap.nxv2i64(<vscale x 2 x i64>)
define <vscale x 4 x i64> @bswap_nxv4i64(<vscale x 4 x i64> %va) { define <vscale x 4 x i64> @bswap_nxv4i64(<vscale x 4 x i64> %va) {
; RV32-LABEL: bswap_nxv4i64: ; RV32-LABEL: bswap_nxv4i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw zero, 12(sp) ; RV32-NEXT: sw zero, 12(sp)
; RV32-NEXT: lui a0, 1044480 ; RV32-NEXT: lui a0, 1044480
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: lui a0, 4080 ; RV32-NEXT: li a0, 56
; RV32-NEXT: sw a0, 12(sp) ; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma
; RV32-NEXT: sw zero, 8(sp) ; RV32-NEXT: vsrl.vx v12, v8, a0
; RV32-NEXT: li a1, 255 ; RV32-NEXT: li a1, 40
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: vsrl.vx v16, v8, a1
; RV32-NEXT: lui a1, 16 ; RV32-NEXT: lui a2, 16
; RV32-NEXT: addi a1, a1, -256 ; RV32-NEXT: addi a2, a2, -256
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: vand.vx v16, v16, a2
; RV32-NEXT: li a2, 56
; RV32-NEXT: vsetvli a3, zero, e64, m4, ta, ma
; RV32-NEXT: vsrl.vx v12, v8, a2
; RV32-NEXT: li a3, 40
; RV32-NEXT: vsrl.vx v16, v8, a3
; RV32-NEXT: vand.vx v16, v16, a1
; RV32-NEXT: vor.vv v12, v16, v12 ; RV32-NEXT: vor.vv v12, v16, v12
; RV32-NEXT: addi a1, sp, 8 ; RV32-NEXT: vsrl.vi v16, v8, 24
; RV32-NEXT: vlse64.v v16, (a1), zero ; RV32-NEXT: addi a3, sp, 8
; RV32-NEXT: vsrl.vi v20, v8, 24 ; RV32-NEXT: vlse64.v v20, (a3), zero
; RV32-NEXT: vand.vx v20, v20, a0 ; RV32-NEXT: lui a3, 4080
; RV32-NEXT: vand.vx v16, v16, a3
; RV32-NEXT: vsrl.vi v24, v8, 8 ; RV32-NEXT: vsrl.vi v24, v8, 8
; RV32-NEXT: vand.vv v16, v24, v16 ; RV32-NEXT: vand.vv v24, v24, v20
; RV32-NEXT: vor.vv v16, v16, v20 ; RV32-NEXT: vor.vv v16, v24, v16
; RV32-NEXT: vlse64.v v20, (a1), zero
; RV32-NEXT: vor.vv v12, v16, v12 ; RV32-NEXT: vor.vv v12, v16, v12
; RV32-NEXT: vsll.vx v16, v8, a2 ; RV32-NEXT: vsll.vx v16, v8, a0
; RV32-NEXT: vsll.vx v24, v8, a3 ; RV32-NEXT: vand.vx v24, v8, a2
; RV32-NEXT: vand.vv v20, v24, v20 ; RV32-NEXT: vsll.vx v24, v24, a1
; RV32-NEXT: vlse64.v v24, (a1), zero ; RV32-NEXT: vor.vv v16, v16, v24
; RV32-NEXT: vor.vv v16, v16, v20 ; RV32-NEXT: vand.vx v24, v8, a3
; RV32-NEXT: vlse64.v v20, (a1), zero ; RV32-NEXT: vsll.vi v24, v24, 24
; RV32-NEXT: vsll.vi v28, v8, 8
; RV32-NEXT: vand.vv v24, v28, v24
; RV32-NEXT: vsll.vi v8, v8, 24
; RV32-NEXT: vand.vv v8, v8, v20 ; RV32-NEXT: vand.vv v8, v8, v20
; RV32-NEXT: vor.vv v8, v8, v24 ; RV32-NEXT: vsll.vi v8, v8, 8
; RV32-NEXT: vor.vv v8, v24, v8
; RV32-NEXT: vor.vv v8, v16, v8 ; RV32-NEXT: vor.vv v8, v16, v8
; RV32-NEXT: vor.vv v8, v8, v12 ; RV32-NEXT: vor.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: bswap_nxv4i64: ; RV64-LABEL: bswap_nxv4i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, ma ; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, ma
; RV64-NEXT: vsrl.vx v12, v8, a0 ; RV64-NEXT: vsrl.vx v12, v8, a0
; RV64-NEXT: li a1, 40 ; RV64-NEXT: li a1, 40
; RV64-NEXT: vsrl.vx v16, v8, a1 ; RV64-NEXT: vsrl.vx v16, v8, a1
; RV64-NEXT: lui a2, 16 ; RV64-NEXT: lui a2, 16
; RV64-NEXT: addiw a2, a2, -256 ; RV64-NEXT: addiw a2, a2, -256
; RV64-NEXT: vand.vx v16, v16, a2 ; RV64-NEXT: vand.vx v16, v16, a2
; RV64-NEXT: vor.vv v12, v16, v12 ; RV64-NEXT: vor.vv v12, v16, v12
; RV64-NEXT: vsrl.vi v16, v8, 24 ; RV64-NEXT: vsrl.vi v16, v8, 24
; RV64-NEXT: lui a2, 4080 ; RV64-NEXT: lui a3, 4080
; RV64-NEXT: vand.vx v16, v16, a2 ; RV64-NEXT: vand.vx v16, v16, a3
; RV64-NEXT: vsrl.vi v20, v8, 8 ; RV64-NEXT: vsrl.vi v20, v8, 8
; RV64-NEXT: li a2, 255 ; RV64-NEXT: li a4, 255
; RV64-NEXT: slli a3, a2, 24 ; RV64-NEXT: slli a4, a4, 24
; RV64-NEXT: vand.vx v20, v20, a3 ; RV64-NEXT: vand.vx v20, v20, a4
; RV64-NEXT: vor.vv v16, v20, v16 ; RV64-NEXT: vor.vv v16, v20, v16
; RV64-NEXT: vor.vv v12, v16, v12 ; RV64-NEXT: vor.vv v12, v16, v12
; RV64-NEXT: vsll.vi v16, v8, 8 ; RV64-NEXT: vand.vx v16, v8, a3
; RV64-NEXT: slli a3, a2, 32 ; RV64-NEXT: vsll.vi v16, v16, 24
; RV64-NEXT: vand.vx v16, v16, a3 ; RV64-NEXT: vand.vx v20, v8, a4
; RV64-NEXT: vsll.vi v20, v8, 24 ; RV64-NEXT: vsll.vi v20, v20, 8
; RV64-NEXT: slli a3, a2, 40 ; RV64-NEXT: vor.vv v16, v16, v20
; RV64-NEXT: vand.vx v20, v20, a3
; RV64-NEXT: vor.vv v16, v20, v16
; RV64-NEXT: vsll.vx v20, v8, a0 ; RV64-NEXT: vsll.vx v20, v8, a0
; RV64-NEXT: vand.vx v8, v8, a2
; RV64-NEXT: vsll.vx v8, v8, a1 ; RV64-NEXT: vsll.vx v8, v8, a1
; RV64-NEXT: slli a0, a2, 48
; RV64-NEXT: vand.vx v8, v8, a0
; RV64-NEXT: vor.vv v8, v20, v8 ; RV64-NEXT: vor.vv v8, v20, v8
; RV64-NEXT: vor.vv v8, v8, v16 ; RV64-NEXT: vor.vv v8, v8, v16
; RV64-NEXT: vor.vv v8, v8, v12 ; RV64-NEXT: vor.vv v8, v8, v12
; RV64-NEXT: ret ; RV64-NEXT: ret
%a = call <vscale x 4 x i64> @llvm.bswap.nxv4i64(<vscale x 4 x i64> %va) %a = call <vscale x 4 x i64> @llvm.bswap.nxv4i64(<vscale x 4 x i64> %va)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.bswap.nxv4i64(<vscale x 4 x i64>) declare <vscale x 4 x i64> @llvm.bswap.nxv4i64(<vscale x 4 x i64>)
define <vscale x 8 x i64> @bswap_nxv8i64(<vscale x 8 x i64> %va) { define <vscale x 8 x i64> @bswap_nxv8i64(<vscale x 8 x i64> %va) {
; RV32-LABEL: bswap_nxv8i64: ; RV32-LABEL: bswap_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 4 ; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: sub sp, sp, a0 ; RV32-NEXT: sub sp, sp, a0
; RV32-NEXT: sw zero, 12(sp) ; RV32-NEXT: sw zero, 12(sp)
; RV32-NEXT: lui a0, 1044480 ; RV32-NEXT: lui a0, 1044480
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: lui a0, 4080 ; RV32-NEXT: li a0, 56
; RV32-NEXT: sw a0, 12(sp) ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma
; RV32-NEXT: sw zero, 8(sp) ; RV32-NEXT: vsrl.vx v16, v8, a0
; RV32-NEXT: li a1, 255 ; RV32-NEXT: li a1, 40
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: vsrl.vx v24, v8, a1
; RV32-NEXT: lui a1, 16 ; RV32-NEXT: lui a2, 16
; RV32-NEXT: addi a1, a1, -256 ; RV32-NEXT: addi a2, a2, -256
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: vand.vx v24, v24, a2
; RV32-NEXT: li a2, 56 ; RV32-NEXT: vor.vv v16, v24, v16
; RV32-NEXT: vsetvli a3, zero, e64, m8, ta, ma ; RV32-NEXT: addi a3, sp, 16
; RV32-NEXT: li a3, 40 ; RV32-NEXT: vs8r.v v16, (a3) # Unknown-size Folded Spill
; RV32-NEXT: vsrl.vx v16, v8, a3
; RV32-NEXT: vand.vx v16, v16, a1
; RV32-NEXT: addi a1, sp, 8
; RV32-NEXT: vlse64.v v24, (a1), zero
; RV32-NEXT: vsrl.vx v0, v8, a2
; RV32-NEXT: vor.vv v16, v16, v0
; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: slli a4, a4, 3
; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vs8r.v v16, (a4) # Unknown-size Folded Spill
; RV32-NEXT: vsrl.vi v0, v8, 8
; RV32-NEXT: vand.vv v24, v0, v24
; RV32-NEXT: vsrl.vi v0, v8, 24 ; RV32-NEXT: vsrl.vi v0, v8, 24
; RV32-NEXT: vand.vx v0, v0, a0 ; RV32-NEXT: addi a3, sp, 8
; RV32-NEXT: vlse64.v v16, (a1), zero ; RV32-NEXT: vlse64.v v24, (a3), zero
; RV32-NEXT: vor.vv v24, v24, v0 ; RV32-NEXT: lui a3, 4080
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: vand.vx v0, v0, a3
; RV32-NEXT: slli a0, a0, 3 ; RV32-NEXT: vsrl.vi v16, v8, 8
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8re8.v v0, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v24, v24, v0
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill
; RV32-NEXT: vsll.vx v0, v8, a3
; RV32-NEXT: vand.vv v16, v0, v16
; RV32-NEXT: vsll.vx v0, v8, a2
; RV32-NEXT: vlse64.v v24, (a1), zero
; RV32-NEXT: vor.vv v16, v0, v16
; RV32-NEXT: addi a0, sp, 16
; RV32-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
; RV32-NEXT: vlse64.v v0, (a1), zero
; RV32-NEXT: vsll.vi v16, v8, 8
; RV32-NEXT: vand.vv v16, v16, v24 ; RV32-NEXT: vand.vv v16, v16, v24
; RV32-NEXT: vor.vv v16, v16, v0
; RV32-NEXT: addi a4, sp, 16
; RV32-NEXT: vl8re8.v v0, (a4) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v16, v16, v0
; RV32-NEXT: addi a4, sp, 16
; RV32-NEXT: vs8r.v v16, (a4) # Unknown-size Folded Spill
; RV32-NEXT: vand.vx v0, v8, a2
; RV32-NEXT: vsll.vx v0, v0, a1
; RV32-NEXT: vsll.vx v16, v8, a0
; RV32-NEXT: vor.vv v16, v16, v0
; RV32-NEXT: vand.vv v24, v8, v24
; RV32-NEXT: vand.vx v8, v8, a3
; RV32-NEXT: vsll.vi v8, v8, 24 ; RV32-NEXT: vsll.vi v8, v8, 24
; RV32-NEXT: vand.vv v8, v8, v0 ; RV32-NEXT: vsll.vi v24, v24, 8
; RV32-NEXT: vor.vv v8, v8, v16 ; RV32-NEXT: vor.vv v8, v8, v24
; RV32-NEXT: addi a0, sp, 16
; RV32-NEXT: vl8re8.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v8, v16, v8 ; RV32-NEXT: vor.vv v8, v16, v8
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: addi a0, sp, 16
; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8re8.v v16, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8re8.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v8, v8, v16 ; RV32-NEXT: vor.vv v8, v8, v16
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 4 ; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add sp, sp, a0 ; RV32-NEXT: add sp, sp, a0
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: bswap_nxv8i64: ; RV64-LABEL: bswap_nxv8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: li a0, 56 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma
; RV64-NEXT: vsrl.vx v16, v8, a0 ; RV64-NEXT: vsrl.vx v16, v8, a0
; RV64-NEXT: li a1, 40 ; RV64-NEXT: li a1, 40
; RV64-NEXT: vsrl.vx v24, v8, a1 ; RV64-NEXT: vsrl.vx v24, v8, a1
; RV64-NEXT: lui a2, 16 ; RV64-NEXT: lui a2, 16
; RV64-NEXT: addiw a2, a2, -256 ; RV64-NEXT: addiw a2, a2, -256
; RV64-NEXT: vand.vx v24, v24, a2 ; RV64-NEXT: vand.vx v24, v24, a2
; RV64-NEXT: vor.vv v16, v24, v16 ; RV64-NEXT: vor.vv v16, v24, v16
; RV64-NEXT: vsrl.vi v24, v8, 24 ; RV64-NEXT: vsrl.vi v24, v8, 24
; RV64-NEXT: lui a2, 4080 ; RV64-NEXT: lui a3, 4080
; RV64-NEXT: vand.vx v24, v24, a2 ; RV64-NEXT: vand.vx v24, v24, a3
; RV64-NEXT: vsrl.vi v0, v8, 8 ; RV64-NEXT: vsrl.vi v0, v8, 8
; RV64-NEXT: li a2, 255 ; RV64-NEXT: li a4, 255
; RV64-NEXT: slli a3, a2, 24 ; RV64-NEXT: slli a4, a4, 24
; RV64-NEXT: vand.vx v0, v0, a3 ; RV64-NEXT: vand.vx v0, v0, a4
; RV64-NEXT: vor.vv v24, v0, v24 ; RV64-NEXT: vor.vv v24, v0, v24
; RV64-NEXT: vor.vv v16, v24, v16 ; RV64-NEXT: vor.vv v16, v24, v16
; RV64-NEXT: vsll.vi v24, v8, 8 ; RV64-NEXT: vand.vx v24, v8, a3
; RV64-NEXT: slli a3, a2, 32 ; RV64-NEXT: vsll.vi v24, v24, 24
; RV64-NEXT: vand.vx v24, v24, a3 ; RV64-NEXT: vand.vx v0, v8, a4
; RV64-NEXT: vsll.vi v0, v8, 24 ; RV64-NEXT: vsll.vi v0, v0, 8
; RV64-NEXT: slli a3, a2, 40 ; RV64-NEXT: vor.vv v24, v24, v0
; RV64-NEXT: vand.vx v0, v0, a3
; RV64-NEXT: vor.vv v24, v0, v24
; RV64-NEXT: vsll.vx v0, v8, a0 ; RV64-NEXT: vsll.vx v0, v8, a0
; RV64-NEXT: vand.vx v8, v8, a2
; RV64-NEXT: vsll.vx v8, v8, a1 ; RV64-NEXT: vsll.vx v8, v8, a1
; RV64-NEXT: slli a0, a2, 48
; RV64-NEXT: vand.vx v8, v8, a0
; RV64-NEXT: vor.vv v8, v0, v8 ; RV64-NEXT: vor.vv v8, v0, v8
; RV64-NEXT: vor.vv v8, v8, v24 ; RV64-NEXT: vor.vv v8, v8, v24
; RV64-NEXT: vor.vv v8, v8, v16 ; RV64-NEXT: vor.vv v8, v8, v16
; RV64-NEXT: ret ; RV64-NEXT: ret
%a = call <vscale x 8 x i64> @llvm.bswap.nxv8i64(<vscale x 8 x i64> %va) %a = call <vscale x 8 x i64> @llvm.bswap.nxv8i64(<vscale x 8 x i64> %va)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.bswap.nxv8i64(<vscale x 8 x i64>) declare <vscale x 8 x i64> @llvm.bswap.nxv8i64(<vscale x 8 x i64>)

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll

Show First 20 Lines • Show All 79 Lines • ▼ Show 20 Lines
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV32-NEXT: vle32.v v8, (a0) ; RV32-NEXT: vle32.v v8, (a0)
; RV32-NEXT: vsrl.vi v9, v8, 8 ; RV32-NEXT: vsrl.vi v9, v8, 8
; RV32-NEXT: lui a1, 16 ; RV32-NEXT: lui a1, 16
; RV32-NEXT: addi a1, a1, -256 ; RV32-NEXT: addi a1, a1, -256
; RV32-NEXT: vand.vx v9, v9, a1 ; RV32-NEXT: vand.vx v9, v9, a1
; RV32-NEXT: vsrl.vi v10, v8, 24 ; RV32-NEXT: vsrl.vi v10, v8, 24
; RV32-NEXT: vor.vv v9, v9, v10 ; RV32-NEXT: vor.vv v9, v9, v10
; RV32-NEXT: vsll.vi v10, v8, 8 ; RV32-NEXT: vand.vx v10, v8, a1
; RV32-NEXT: lui a1, 4080 ; RV32-NEXT: vsll.vi v10, v10, 8
; RV32-NEXT: vand.vx v10, v10, a1
; RV32-NEXT: vsll.vi v8, v8, 24 ; RV32-NEXT: vsll.vi v8, v8, 24
; RV32-NEXT: vor.vv v8, v8, v10 ; RV32-NEXT: vor.vv v8, v8, v10
; RV32-NEXT: vor.vv v8, v8, v9 ; RV32-NEXT: vor.vv v8, v8, v9
; RV32-NEXT: vsrl.vi v9, v8, 4 ; RV32-NEXT: vsrl.vi v9, v8, 4
; RV32-NEXT: lui a1, 61681 ; RV32-NEXT: lui a1, 61681
; RV32-NEXT: addi a1, a1, -241 ; RV32-NEXT: addi a1, a1, -241
; RV32-NEXT: vand.vx v9, v9, a1 ; RV32-NEXT: vand.vx v9, v9, a1
; RV32-NEXT: vand.vx v8, v8, a1 ; RV32-NEXT: vand.vx v8, v8, a1
Show All 21 Lines
; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV64-NEXT: vle32.v v8, (a0) ; RV64-NEXT: vle32.v v8, (a0)
; RV64-NEXT: vsrl.vi v9, v8, 8 ; RV64-NEXT: vsrl.vi v9, v8, 8
; RV64-NEXT: lui a1, 16 ; RV64-NEXT: lui a1, 16
; RV64-NEXT: addiw a1, a1, -256 ; RV64-NEXT: addiw a1, a1, -256
; RV64-NEXT: vand.vx v9, v9, a1 ; RV64-NEXT: vand.vx v9, v9, a1
; RV64-NEXT: vsrl.vi v10, v8, 24 ; RV64-NEXT: vsrl.vi v10, v8, 24
; RV64-NEXT: vor.vv v9, v9, v10 ; RV64-NEXT: vor.vv v9, v9, v10
; RV64-NEXT: vsll.vi v10, v8, 8 ; RV64-NEXT: vand.vx v10, v8, a1
; RV64-NEXT: lui a1, 4080 ; RV64-NEXT: vsll.vi v10, v10, 8
; RV64-NEXT: vand.vx v10, v10, a1
; RV64-NEXT: vsll.vi v8, v8, 24 ; RV64-NEXT: vsll.vi v8, v8, 24
; RV64-NEXT: vor.vv v8, v8, v10 ; RV64-NEXT: vor.vv v8, v8, v10
; RV64-NEXT: vor.vv v8, v8, v9 ; RV64-NEXT: vor.vv v8, v8, v9
; RV64-NEXT: vsrl.vi v9, v8, 4 ; RV64-NEXT: vsrl.vi v9, v8, 4
; RV64-NEXT: lui a1, 61681 ; RV64-NEXT: lui a1, 61681
; RV64-NEXT: addiw a1, a1, -241 ; RV64-NEXT: addiw a1, a1, -241
; RV64-NEXT: vand.vx v9, v9, a1 ; RV64-NEXT: vand.vx v9, v9, a1
; RV64-NEXT: vand.vx v8, v8, a1 ; RV64-NEXT: vand.vx v8, v8, a1
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
; RV32-NEXT: li a5, 5 ; RV32-NEXT: li a5, 5
; RV32-NEXT: vmv.s.x v0, a5 ; RV32-NEXT: vmv.s.x v0, a5
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV32-NEXT: vmv.v.i v11, 0 ; RV32-NEXT: vmv.v.i v11, 0
; RV32-NEXT: lui a5, 1044480 ; RV32-NEXT: lui a5, 1044480
; RV32-NEXT: vmerge.vxm v11, v11, a5, v0 ; RV32-NEXT: vmerge.vxm v11, v11, a5, v0
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV32-NEXT: vsrl.vi v12, v8, 8 ; RV32-NEXT: vsrl.vi v12, v8, 8
; RV32-NEXT: vand.vv v11, v12, v11 ; RV32-NEXT: vand.vv v12, v12, v11
; RV32-NEXT: vor.vv v10, v11, v10 ; RV32-NEXT: vor.vv v10, v12, v10
; RV32-NEXT: vor.vv v9, v10, v9 ; RV32-NEXT: vor.vv v9, v10, v9
; RV32-NEXT: li a5, 255 ; RV32-NEXT: vsll.vx v10, v8, a1
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; RV32-NEXT: vand.vx v12, v8, a3
; RV32-NEXT: vmv.v.x v10, a5 ; RV32-NEXT: vsll.vx v12, v12, a2
; RV32-NEXT: vmerge.vim v10, v10, 0, v0 ; RV32-NEXT: vor.vv v10, v10, v12
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; RV32-NEXT: vand.vx v12, v8, a4
; RV32-NEXT: vsll.vi v11, v8, 8 ; RV32-NEXT: vsll.vi v12, v12, 24
; RV32-NEXT: vand.vv v10, v11, v10 ; RV32-NEXT: vand.vv v8, v8, v11
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; RV32-NEXT: vsll.vi v8, v8, 8
; RV32-NEXT: vmv.v.x v11, a3 ; RV32-NEXT: vor.vv v8, v12, v8
; RV32-NEXT: vmerge.vim v11, v11, 0, v0 ; RV32-NEXT: vor.vv v8, v10, v8
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV32-NEXT: vsll.vi v12, v8, 24
; RV32-NEXT: vand.vv v11, v12, v11
; RV32-NEXT: vor.vv v10, v11, v10
; RV32-NEXT: vsll.vx v11, v8, a2
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV32-NEXT: vmv.v.x v12, a4
; RV32-NEXT: vmerge.vim v12, v12, 0, v0
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV32-NEXT: vand.vv v11, v11, v12
; RV32-NEXT: vsll.vx v8, v8, a1
; RV32-NEXT: vor.vv v8, v8, v11
; RV32-NEXT: vor.vv v8, v8, v10
; RV32-NEXT: vor.vv v8, v8, v9 ; RV32-NEXT: vor.vv v8, v8, v9
; RV32-NEXT: vsrl.vi v9, v8, 4 ; RV32-NEXT: vsrl.vi v9, v8, 4
; RV32-NEXT: lui a1, 61681 ; RV32-NEXT: lui a1, 61681
; RV32-NEXT: addi a1, a1, -241 ; RV32-NEXT: addi a1, a1, -241
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV32-NEXT: vmv.v.x v10, a1 ; RV32-NEXT: vmv.v.x v10, a1
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV32-NEXT: vand.vv v9, v9, v10 ; RV32-NEXT: vand.vv v9, v9, v10
Show All 31 Lines
; RV64-NEXT: vsrl.vx v9, v8, a1 ; RV64-NEXT: vsrl.vx v9, v8, a1
; RV64-NEXT: li a2, 40 ; RV64-NEXT: li a2, 40
; RV64-NEXT: vsrl.vx v10, v8, a2 ; RV64-NEXT: vsrl.vx v10, v8, a2
; RV64-NEXT: lui a3, 16 ; RV64-NEXT: lui a3, 16
; RV64-NEXT: addiw a3, a3, -256 ; RV64-NEXT: addiw a3, a3, -256
; RV64-NEXT: vand.vx v10, v10, a3 ; RV64-NEXT: vand.vx v10, v10, a3
; RV64-NEXT: vor.vv v9, v10, v9 ; RV64-NEXT: vor.vv v9, v10, v9
; RV64-NEXT: vsrl.vi v10, v8, 24 ; RV64-NEXT: vsrl.vi v10, v8, 24
; RV64-NEXT: lui a3, 4080 ; RV64-NEXT: lui a4, 4080
; RV64-NEXT: vand.vx v10, v10, a3 ; RV64-NEXT: vand.vx v10, v10, a4
; RV64-NEXT: vsrl.vi v11, v8, 8 ; RV64-NEXT: vsrl.vi v11, v8, 8
; RV64-NEXT: li a3, 255 ; RV64-NEXT: li a5, 255
; RV64-NEXT: slli a4, a3, 24 ; RV64-NEXT: slli a5, a5, 24
; RV64-NEXT: vand.vx v11, v11, a4 ; RV64-NEXT: vand.vx v11, v11, a5
; RV64-NEXT: vor.vv v10, v11, v10 ; RV64-NEXT: vor.vv v10, v11, v10
; RV64-NEXT: vor.vv v9, v10, v9 ; RV64-NEXT: vor.vv v9, v10, v9
; RV64-NEXT: vsll.vi v10, v8, 8 ; RV64-NEXT: vand.vx v10, v8, a5
; RV64-NEXT: slli a4, a3, 32 ; RV64-NEXT: vsll.vi v10, v10, 8
; RV64-NEXT: vand.vx v10, v10, a4 ; RV64-NEXT: vand.vx v11, v8, a4
; RV64-NEXT: vsll.vi v11, v8, 24 ; RV64-NEXT: vsll.vi v11, v11, 24
; RV64-NEXT: slli a4, a3, 40
; RV64-NEXT: vand.vx v11, v11, a4
; RV64-NEXT: vor.vv v10, v11, v10 ; RV64-NEXT: vor.vv v10, v11, v10
; RV64-NEXT: vsll.vx v11, v8, a1 ; RV64-NEXT: vsll.vx v11, v8, a1
; RV64-NEXT: vand.vx v8, v8, a3
; RV64-NEXT: vsll.vx v8, v8, a2 ; RV64-NEXT: vsll.vx v8, v8, a2
; RV64-NEXT: slli a1, a3, 48
; RV64-NEXT: vand.vx v8, v8, a1
; RV64-NEXT: vor.vv v8, v11, v8 ; RV64-NEXT: vor.vv v8, v11, v8
; RV64-NEXT: lui a1, %hi(.LCPI2_0) ; RV64-NEXT: lui a1, %hi(.LCPI2_0)
; RV64-NEXT: ld a1, %lo(.LCPI2_0)(a1) ; RV64-NEXT: ld a1, %lo(.LCPI2_0)(a1)
; RV64-NEXT: vor.vv v8, v8, v10 ; RV64-NEXT: vor.vv v8, v8, v10
; RV64-NEXT: vor.vv v8, v8, v9 ; RV64-NEXT: vor.vv v8, v8, v9
; RV64-NEXT: vsrl.vi v9, v8, 4 ; RV64-NEXT: vsrl.vi v9, v8, 4
; RV64-NEXT: vand.vx v9, v9, a1 ; RV64-NEXT: vand.vx v9, v9, a1
; RV64-NEXT: vand.vx v8, v8, a1 ; RV64-NEXT: vand.vx v8, v8, a1
▲ Show 20 Lines • Show All 203 Lines • ▼ Show 20 Lines
; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; LMULMAX2-RV32-NEXT: vle32.v v8, (a0) ; LMULMAX2-RV32-NEXT: vle32.v v8, (a0)
; LMULMAX2-RV32-NEXT: vsrl.vi v10, v8, 8 ; LMULMAX2-RV32-NEXT: vsrl.vi v10, v8, 8
; LMULMAX2-RV32-NEXT: lui a1, 16 ; LMULMAX2-RV32-NEXT: lui a1, 16
; LMULMAX2-RV32-NEXT: addi a1, a1, -256 ; LMULMAX2-RV32-NEXT: addi a1, a1, -256
; LMULMAX2-RV32-NEXT: vand.vx v10, v10, a1 ; LMULMAX2-RV32-NEXT: vand.vx v10, v10, a1
; LMULMAX2-RV32-NEXT: vsrl.vi v12, v8, 24 ; LMULMAX2-RV32-NEXT: vsrl.vi v12, v8, 24
; LMULMAX2-RV32-NEXT: vor.vv v10, v10, v12 ; LMULMAX2-RV32-NEXT: vor.vv v10, v10, v12
; LMULMAX2-RV32-NEXT: vsll.vi v12, v8, 8 ; LMULMAX2-RV32-NEXT: vand.vx v12, v8, a1
; LMULMAX2-RV32-NEXT: lui a1, 4080 ; LMULMAX2-RV32-NEXT: vsll.vi v12, v12, 8
; LMULMAX2-RV32-NEXT: vand.vx v12, v12, a1
; LMULMAX2-RV32-NEXT: vsll.vi v8, v8, 24 ; LMULMAX2-RV32-NEXT: vsll.vi v8, v8, 24
; LMULMAX2-RV32-NEXT: vor.vv v8, v8, v12 ; LMULMAX2-RV32-NEXT: vor.vv v8, v8, v12
; LMULMAX2-RV32-NEXT: vor.vv v8, v8, v10 ; LMULMAX2-RV32-NEXT: vor.vv v8, v8, v10
; LMULMAX2-RV32-NEXT: vsrl.vi v10, v8, 4 ; LMULMAX2-RV32-NEXT: vsrl.vi v10, v8, 4
; LMULMAX2-RV32-NEXT: lui a1, 61681 ; LMULMAX2-RV32-NEXT: lui a1, 61681
; LMULMAX2-RV32-NEXT: addi a1, a1, -241 ; LMULMAX2-RV32-NEXT: addi a1, a1, -241
; LMULMAX2-RV32-NEXT: vand.vx v10, v10, a1 ; LMULMAX2-RV32-NEXT: vand.vx v10, v10, a1
; LMULMAX2-RV32-NEXT: vand.vx v8, v8, a1 ; LMULMAX2-RV32-NEXT: vand.vx v8, v8, a1
Show All 21 Lines
; LMULMAX2-RV64-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; LMULMAX2-RV64-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; LMULMAX2-RV64-NEXT: vle32.v v8, (a0) ; LMULMAX2-RV64-NEXT: vle32.v v8, (a0)
; LMULMAX2-RV64-NEXT: vsrl.vi v10, v8, 8 ; LMULMAX2-RV64-NEXT: vsrl.vi v10, v8, 8
; LMULMAX2-RV64-NEXT: lui a1, 16 ; LMULMAX2-RV64-NEXT: lui a1, 16
; LMULMAX2-RV64-NEXT: addiw a1, a1, -256 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -256
; LMULMAX2-RV64-NEXT: vand.vx v10, v10, a1 ; LMULMAX2-RV64-NEXT: vand.vx v10, v10, a1
; LMULMAX2-RV64-NEXT: vsrl.vi v12, v8, 24 ; LMULMAX2-RV64-NEXT: vsrl.vi v12, v8, 24
; LMULMAX2-RV64-NEXT: vor.vv v10, v10, v12 ; LMULMAX2-RV64-NEXT: vor.vv v10, v10, v12
; LMULMAX2-RV64-NEXT: vsll.vi v12, v8, 8 ; LMULMAX2-RV64-NEXT: vand.vx v12, v8, a1
; LMULMAX2-RV64-NEXT: lui a1, 4080 ; LMULMAX2-RV64-NEXT: vsll.vi v12, v12, 8
; LMULMAX2-RV64-NEXT: vand.vx v12, v12, a1
; LMULMAX2-RV64-NEXT: vsll.vi v8, v8, 24 ; LMULMAX2-RV64-NEXT: vsll.vi v8, v8, 24
; LMULMAX2-RV64-NEXT: vor.vv v8, v8, v12 ; LMULMAX2-RV64-NEXT: vor.vv v8, v8, v12
; LMULMAX2-RV64-NEXT: vor.vv v8, v8, v10 ; LMULMAX2-RV64-NEXT: vor.vv v8, v8, v10
; LMULMAX2-RV64-NEXT: vsrl.vi v10, v8, 4 ; LMULMAX2-RV64-NEXT: vsrl.vi v10, v8, 4
; LMULMAX2-RV64-NEXT: lui a1, 61681 ; LMULMAX2-RV64-NEXT: lui a1, 61681
; LMULMAX2-RV64-NEXT: addiw a1, a1, -241 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -241
; LMULMAX2-RV64-NEXT: vand.vx v10, v10, a1 ; LMULMAX2-RV64-NEXT: vand.vx v10, v10, a1
; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a1 ; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a1
Show All 23 Lines
; LMULMAX1-RV32-NEXT: vle32.v v8, (a1) ; LMULMAX1-RV32-NEXT: vle32.v v8, (a1)
; LMULMAX1-RV32-NEXT: vle32.v v9, (a0) ; LMULMAX1-RV32-NEXT: vle32.v v9, (a0)
; LMULMAX1-RV32-NEXT: vsrl.vi v10, v8, 8 ; LMULMAX1-RV32-NEXT: vsrl.vi v10, v8, 8
; LMULMAX1-RV32-NEXT: lui a2, 16 ; LMULMAX1-RV32-NEXT: lui a2, 16
; LMULMAX1-RV32-NEXT: addi a2, a2, -256 ; LMULMAX1-RV32-NEXT: addi a2, a2, -256
; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a2 ; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a2
; LMULMAX1-RV32-NEXT: vsrl.vi v11, v8, 24 ; LMULMAX1-RV32-NEXT: vsrl.vi v11, v8, 24
; LMULMAX1-RV32-NEXT: vor.vv v10, v10, v11 ; LMULMAX1-RV32-NEXT: vor.vv v10, v10, v11
; LMULMAX1-RV32-NEXT: vsll.vi v11, v8, 8 ; LMULMAX1-RV32-NEXT: vand.vx v11, v8, a2
; LMULMAX1-RV32-NEXT: lui a3, 4080 ; LMULMAX1-RV32-NEXT: vsll.vi v11, v11, 8
; LMULMAX1-RV32-NEXT: vand.vx v11, v11, a3
; LMULMAX1-RV32-NEXT: vsll.vi v8, v8, 24 ; LMULMAX1-RV32-NEXT: vsll.vi v8, v8, 24
; LMULMAX1-RV32-NEXT: vor.vv v8, v8, v11 ; LMULMAX1-RV32-NEXT: vor.vv v8, v8, v11
; LMULMAX1-RV32-NEXT: vor.vv v8, v8, v10 ; LMULMAX1-RV32-NEXT: vor.vv v8, v8, v10
; LMULMAX1-RV32-NEXT: vsrl.vi v10, v8, 4 ; LMULMAX1-RV32-NEXT: vsrl.vi v10, v8, 4
; LMULMAX1-RV32-NEXT: lui a4, 61681 ; LMULMAX1-RV32-NEXT: lui a3, 61681
; LMULMAX1-RV32-NEXT: addi a4, a4, -241 ; LMULMAX1-RV32-NEXT: addi a3, a3, -241
; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a4 ; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a3
; LMULMAX1-RV32-NEXT: vand.vx v8, v8, a4 ; LMULMAX1-RV32-NEXT: vand.vx v8, v8, a3
; LMULMAX1-RV32-NEXT: vsll.vi v8, v8, 4 ; LMULMAX1-RV32-NEXT: vsll.vi v8, v8, 4
; LMULMAX1-RV32-NEXT: vor.vv v8, v10, v8 ; LMULMAX1-RV32-NEXT: vor.vv v8, v10, v8
; LMULMAX1-RV32-NEXT: vsrl.vi v10, v8, 2 ; LMULMAX1-RV32-NEXT: vsrl.vi v10, v8, 2
; LMULMAX1-RV32-NEXT: lui a5, 209715 ; LMULMAX1-RV32-NEXT: lui a4, 209715
; LMULMAX1-RV32-NEXT: addi a5, a5, 819 ; LMULMAX1-RV32-NEXT: addi a4, a4, 819
; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a5 ; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a4
; LMULMAX1-RV32-NEXT: vand.vx v8, v8, a5 ; LMULMAX1-RV32-NEXT: vand.vx v8, v8, a4
; LMULMAX1-RV32-NEXT: vsll.vi v8, v8, 2 ; LMULMAX1-RV32-NEXT: vsll.vi v8, v8, 2
; LMULMAX1-RV32-NEXT: vor.vv v8, v10, v8 ; LMULMAX1-RV32-NEXT: vor.vv v8, v10, v8
; LMULMAX1-RV32-NEXT: vsrl.vi v10, v8, 1 ; LMULMAX1-RV32-NEXT: vsrl.vi v10, v8, 1
; LMULMAX1-RV32-NEXT: lui a6, 349525 ; LMULMAX1-RV32-NEXT: lui a5, 349525
; LMULMAX1-RV32-NEXT: addi a6, a6, 1365 ; LMULMAX1-RV32-NEXT: addi a5, a5, 1365
; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a6 ; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a5
; LMULMAX1-RV32-NEXT: vand.vx v8, v8, a6 ; LMULMAX1-RV32-NEXT: vand.vx v8, v8, a5
; LMULMAX1-RV32-NEXT: vadd.vv v8, v8, v8 ; LMULMAX1-RV32-NEXT: vadd.vv v8, v8, v8
; LMULMAX1-RV32-NEXT: vor.vv v8, v10, v8 ; LMULMAX1-RV32-NEXT: vor.vv v8, v10, v8
; LMULMAX1-RV32-NEXT: vsrl.vi v10, v9, 8 ; LMULMAX1-RV32-NEXT: vsrl.vi v10, v9, 8
; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a2 ; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a2
; LMULMAX1-RV32-NEXT: vsrl.vi v11, v9, 24 ; LMULMAX1-RV32-NEXT: vsrl.vi v11, v9, 24
; LMULMAX1-RV32-NEXT: vor.vv v10, v10, v11 ; LMULMAX1-RV32-NEXT: vor.vv v10, v10, v11
; LMULMAX1-RV32-NEXT: vsll.vi v11, v9, 8 ; LMULMAX1-RV32-NEXT: vand.vx v11, v9, a2
; LMULMAX1-RV32-NEXT: vand.vx v11, v11, a3 ; LMULMAX1-RV32-NEXT: vsll.vi v11, v11, 8
; LMULMAX1-RV32-NEXT: vsll.vi v9, v9, 24 ; LMULMAX1-RV32-NEXT: vsll.vi v9, v9, 24
; LMULMAX1-RV32-NEXT: vor.vv v9, v9, v11 ; LMULMAX1-RV32-NEXT: vor.vv v9, v9, v11
; LMULMAX1-RV32-NEXT: vor.vv v9, v9, v10 ; LMULMAX1-RV32-NEXT: vor.vv v9, v9, v10
; LMULMAX1-RV32-NEXT: vsrl.vi v10, v9, 4 ; LMULMAX1-RV32-NEXT: vsrl.vi v10, v9, 4
; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a4 ; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a3
; LMULMAX1-RV32-NEXT: vand.vx v9, v9, a4 ; LMULMAX1-RV32-NEXT: vand.vx v9, v9, a3
; LMULMAX1-RV32-NEXT: vsll.vi v9, v9, 4 ; LMULMAX1-RV32-NEXT: vsll.vi v9, v9, 4
; LMULMAX1-RV32-NEXT: vor.vv v9, v10, v9 ; LMULMAX1-RV32-NEXT: vor.vv v9, v10, v9
; LMULMAX1-RV32-NEXT: vsrl.vi v10, v9, 2 ; LMULMAX1-RV32-NEXT: vsrl.vi v10, v9, 2
; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a5 ; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a4
; LMULMAX1-RV32-NEXT: vand.vx v9, v9, a5 ; LMULMAX1-RV32-NEXT: vand.vx v9, v9, a4
; LMULMAX1-RV32-NEXT: vsll.vi v9, v9, 2 ; LMULMAX1-RV32-NEXT: vsll.vi v9, v9, 2
; LMULMAX1-RV32-NEXT: vor.vv v9, v10, v9 ; LMULMAX1-RV32-NEXT: vor.vv v9, v10, v9
; LMULMAX1-RV32-NEXT: vsrl.vi v10, v9, 1 ; LMULMAX1-RV32-NEXT: vsrl.vi v10, v9, 1
; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a6 ; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a5
; LMULMAX1-RV32-NEXT: vand.vx v9, v9, a6 ; LMULMAX1-RV32-NEXT: vand.vx v9, v9, a5
; LMULMAX1-RV32-NEXT: vadd.vv v9, v9, v9 ; LMULMAX1-RV32-NEXT: vadd.vv v9, v9, v9
; LMULMAX1-RV32-NEXT: vor.vv v9, v10, v9 ; LMULMAX1-RV32-NEXT: vor.vv v9, v10, v9
; LMULMAX1-RV32-NEXT: vse32.v v9, (a0) ; LMULMAX1-RV32-NEXT: vse32.v v9, (a0)
; LMULMAX1-RV32-NEXT: vse32.v v8, (a1) ; LMULMAX1-RV32-NEXT: vse32.v v8, (a1)
; LMULMAX1-RV32-NEXT: ret ; LMULMAX1-RV32-NEXT: ret
; ;
; LMULMAX1-RV64-LABEL: bitreverse_v8i32: ; LMULMAX1-RV64-LABEL: bitreverse_v8i32:
; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-RV64-NEXT: addi a1, a0, 16 ; LMULMAX1-RV64-NEXT: addi a1, a0, 16
; LMULMAX1-RV64-NEXT: vle32.v v8, (a1) ; LMULMAX1-RV64-NEXT: vle32.v v8, (a1)
; LMULMAX1-RV64-NEXT: vle32.v v9, (a0) ; LMULMAX1-RV64-NEXT: vle32.v v9, (a0)
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 8 ; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 8
; LMULMAX1-RV64-NEXT: lui a2, 16 ; LMULMAX1-RV64-NEXT: lui a2, 16
; LMULMAX1-RV64-NEXT: addiw a2, a2, -256 ; LMULMAX1-RV64-NEXT: addiw a2, a2, -256
; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a2 ; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a2
; LMULMAX1-RV64-NEXT: vsrl.vi v11, v8, 24 ; LMULMAX1-RV64-NEXT: vsrl.vi v11, v8, 24
; LMULMAX1-RV64-NEXT: vor.vv v10, v10, v11 ; LMULMAX1-RV64-NEXT: vor.vv v10, v10, v11
; LMULMAX1-RV64-NEXT: vsll.vi v11, v8, 8 ; LMULMAX1-RV64-NEXT: vand.vx v11, v8, a2
; LMULMAX1-RV64-NEXT: lui a3, 4080 ; LMULMAX1-RV64-NEXT: vsll.vi v11, v11, 8
; LMULMAX1-RV64-NEXT: vand.vx v11, v11, a3
; LMULMAX1-RV64-NEXT: vsll.vi v8, v8, 24 ; LMULMAX1-RV64-NEXT: vsll.vi v8, v8, 24
; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v11 ; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v11
; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v10 ; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v10
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 4 ; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 4
; LMULMAX1-RV64-NEXT: lui a4, 61681 ; LMULMAX1-RV64-NEXT: lui a3, 61681
; LMULMAX1-RV64-NEXT: addiw a4, a4, -241 ; LMULMAX1-RV64-NEXT: addiw a3, a3, -241
; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a4 ; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a3
; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a4 ; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a3
; LMULMAX1-RV64-NEXT: vsll.vi v8, v8, 4 ; LMULMAX1-RV64-NEXT: vsll.vi v8, v8, 4
; LMULMAX1-RV64-NEXT: vor.vv v8, v10, v8 ; LMULMAX1-RV64-NEXT: vor.vv v8, v10, v8
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 2 ; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 2
; LMULMAX1-RV64-NEXT: lui a5, 209715 ; LMULMAX1-RV64-NEXT: lui a4, 209715
; LMULMAX1-RV64-NEXT: addiw a5, a5, 819 ; LMULMAX1-RV64-NEXT: addiw a4, a4, 819
; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a5 ; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a4
; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a5 ; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a4
; LMULMAX1-RV64-NEXT: vsll.vi v8, v8, 2 ; LMULMAX1-RV64-NEXT: vsll.vi v8, v8, 2
; LMULMAX1-RV64-NEXT: vor.vv v8, v10, v8 ; LMULMAX1-RV64-NEXT: vor.vv v8, v10, v8
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 1 ; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 1
; LMULMAX1-RV64-NEXT: lui a6, 349525 ; LMULMAX1-RV64-NEXT: lui a5, 349525
; LMULMAX1-RV64-NEXT: addiw a6, a6, 1365 ; LMULMAX1-RV64-NEXT: addiw a5, a5, 1365
; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a6 ; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a5
; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a6 ; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a5
; LMULMAX1-RV64-NEXT: vadd.vv v8, v8, v8 ; LMULMAX1-RV64-NEXT: vadd.vv v8, v8, v8
; LMULMAX1-RV64-NEXT: vor.vv v8, v10, v8 ; LMULMAX1-RV64-NEXT: vor.vv v8, v10, v8
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 8 ; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 8
; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a2 ; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a2
; LMULMAX1-RV64-NEXT: vsrl.vi v11, v9, 24 ; LMULMAX1-RV64-NEXT: vsrl.vi v11, v9, 24
; LMULMAX1-RV64-NEXT: vor.vv v10, v10, v11 ; LMULMAX1-RV64-NEXT: vor.vv v10, v10, v11
; LMULMAX1-RV64-NEXT: vsll.vi v11, v9, 8 ; LMULMAX1-RV64-NEXT: vand.vx v11, v9, a2
; LMULMAX1-RV64-NEXT: vand.vx v11, v11, a3 ; LMULMAX1-RV64-NEXT: vsll.vi v11, v11, 8
; LMULMAX1-RV64-NEXT: vsll.vi v9, v9, 24 ; LMULMAX1-RV64-NEXT: vsll.vi v9, v9, 24
; LMULMAX1-RV64-NEXT: vor.vv v9, v9, v11 ; LMULMAX1-RV64-NEXT: vor.vv v9, v9, v11
; LMULMAX1-RV64-NEXT: vor.vv v9, v9, v10 ; LMULMAX1-RV64-NEXT: vor.vv v9, v9, v10
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 4 ; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 4
; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a4 ; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a3
; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a4 ; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a3
; LMULMAX1-RV64-NEXT: vsll.vi v9, v9, 4 ; LMULMAX1-RV64-NEXT: vsll.vi v9, v9, 4
; LMULMAX1-RV64-NEXT: vor.vv v9, v10, v9 ; LMULMAX1-RV64-NEXT: vor.vv v9, v10, v9
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 2 ; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 2
; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a5 ; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a4
; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a5 ; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a4
; LMULMAX1-RV64-NEXT: vsll.vi v9, v9, 2 ; LMULMAX1-RV64-NEXT: vsll.vi v9, v9, 2
; LMULMAX1-RV64-NEXT: vor.vv v9, v10, v9 ; LMULMAX1-RV64-NEXT: vor.vv v9, v10, v9
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 1 ; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 1
; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a6 ; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a5
; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a6 ; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a5
; LMULMAX1-RV64-NEXT: vadd.vv v9, v9, v9 ; LMULMAX1-RV64-NEXT: vadd.vv v9, v9, v9
; LMULMAX1-RV64-NEXT: vor.vv v9, v10, v9 ; LMULMAX1-RV64-NEXT: vor.vv v9, v10, v9
; LMULMAX1-RV64-NEXT: vse32.v v9, (a0) ; LMULMAX1-RV64-NEXT: vse32.v v9, (a0)
; LMULMAX1-RV64-NEXT: vse32.v v8, (a1) ; LMULMAX1-RV64-NEXT: vse32.v v8, (a1)
; LMULMAX1-RV64-NEXT: ret ; LMULMAX1-RV64-NEXT: ret
%a = load <8 x i32>, <8 x i32>* %x %a = load <8 x i32>, <8 x i32>* %x
%b = load <8 x i32>, <8 x i32>* %y %b = load <8 x i32>, <8 x i32>* %y
%c = call <8 x i32> @llvm.bitreverse.v8i32(<8 x i32> %a) %c = call <8 x i32> @llvm.bitreverse.v8i32(<8 x i32> %a)
Show All 21 Lines
; LMULMAX2-RV32-NEXT: li a5, 85 ; LMULMAX2-RV32-NEXT: li a5, 85
; LMULMAX2-RV32-NEXT: vmv.s.x v0, a5 ; LMULMAX2-RV32-NEXT: vmv.s.x v0, a5
; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; LMULMAX2-RV32-NEXT: vmv.v.i v14, 0 ; LMULMAX2-RV32-NEXT: vmv.v.i v14, 0
; LMULMAX2-RV32-NEXT: lui a5, 1044480 ; LMULMAX2-RV32-NEXT: lui a5, 1044480
; LMULMAX2-RV32-NEXT: vmerge.vxm v14, v14, a5, v0 ; LMULMAX2-RV32-NEXT: vmerge.vxm v14, v14, a5, v0
; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; LMULMAX2-RV32-NEXT: vsrl.vi v16, v8, 8 ; LMULMAX2-RV32-NEXT: vsrl.vi v16, v8, 8
; LMULMAX2-RV32-NEXT: vand.vv v14, v16, v14 ; LMULMAX2-RV32-NEXT: vand.vv v16, v16, v14
; LMULMAX2-RV32-NEXT: vor.vv v12, v14, v12 ; LMULMAX2-RV32-NEXT: vor.vv v12, v16, v12
; LMULMAX2-RV32-NEXT: vor.vv v10, v12, v10 ; LMULMAX2-RV32-NEXT: vor.vv v10, v12, v10
; LMULMAX2-RV32-NEXT: li a5, 255 ; LMULMAX2-RV32-NEXT: vsll.vx v12, v8, a1
; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; LMULMAX2-RV32-NEXT: vand.vx v16, v8, a3
; LMULMAX2-RV32-NEXT: vmv.v.x v12, a5 ; LMULMAX2-RV32-NEXT: vsll.vx v16, v16, a2
; LMULMAX2-RV32-NEXT: vmerge.vim v12, v12, 0, v0 ; LMULMAX2-RV32-NEXT: vor.vv v12, v12, v16
; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; LMULMAX2-RV32-NEXT: vand.vx v16, v8, a4
; LMULMAX2-RV32-NEXT: vsll.vi v14, v8, 8 ; LMULMAX2-RV32-NEXT: vsll.vi v16, v16, 24
; LMULMAX2-RV32-NEXT: vand.vv v12, v14, v12 ; LMULMAX2-RV32-NEXT: vand.vv v8, v8, v14
; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; LMULMAX2-RV32-NEXT: vsll.vi v8, v8, 8
; LMULMAX2-RV32-NEXT: vmv.v.x v14, a3 ; LMULMAX2-RV32-NEXT: vor.vv v8, v16, v8
; LMULMAX2-RV32-NEXT: vmerge.vim v14, v14, 0, v0 ; LMULMAX2-RV32-NEXT: vor.vv v8, v12, v8
; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; LMULMAX2-RV32-NEXT: vsll.vi v16, v8, 24
; LMULMAX2-RV32-NEXT: vand.vv v14, v16, v14
; LMULMAX2-RV32-NEXT: vor.vv v12, v14, v12
; LMULMAX2-RV32-NEXT: vsll.vx v14, v8, a2
; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; LMULMAX2-RV32-NEXT: vmv.v.x v16, a4
; LMULMAX2-RV32-NEXT: vmerge.vim v16, v16, 0, v0
; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; LMULMAX2-RV32-NEXT: vand.vv v14, v14, v16
; LMULMAX2-RV32-NEXT: vsll.vx v8, v8, a1
; LMULMAX2-RV32-NEXT: vor.vv v8, v8, v14
; LMULMAX2-RV32-NEXT: vor.vv v8, v8, v12
; LMULMAX2-RV32-NEXT: vor.vv v8, v8, v10 ; LMULMAX2-RV32-NEXT: vor.vv v8, v8, v10
; LMULMAX2-RV32-NEXT: vsrl.vi v10, v8, 4 ; LMULMAX2-RV32-NEXT: vsrl.vi v10, v8, 4
; LMULMAX2-RV32-NEXT: lui a1, 61681 ; LMULMAX2-RV32-NEXT: lui a1, 61681
; LMULMAX2-RV32-NEXT: addi a1, a1, -241 ; LMULMAX2-RV32-NEXT: addi a1, a1, -241
; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; LMULMAX2-RV32-NEXT: vmv.v.x v12, a1 ; LMULMAX2-RV32-NEXT: vmv.v.x v12, a1
; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; LMULMAX2-RV32-NEXT: vand.vv v10, v10, v12 ; LMULMAX2-RV32-NEXT: vand.vv v10, v10, v12
Show All 31 Lines
; LMULMAX2-RV64-NEXT: vsrl.vx v10, v8, a1 ; LMULMAX2-RV64-NEXT: vsrl.vx v10, v8, a1
; LMULMAX2-RV64-NEXT: li a2, 40 ; LMULMAX2-RV64-NEXT: li a2, 40
; LMULMAX2-RV64-NEXT: vsrl.vx v12, v8, a2 ; LMULMAX2-RV64-NEXT: vsrl.vx v12, v8, a2
; LMULMAX2-RV64-NEXT: lui a3, 16 ; LMULMAX2-RV64-NEXT: lui a3, 16
; LMULMAX2-RV64-NEXT: addiw a3, a3, -256 ; LMULMAX2-RV64-NEXT: addiw a3, a3, -256
; LMULMAX2-RV64-NEXT: vand.vx v12, v12, a3 ; LMULMAX2-RV64-NEXT: vand.vx v12, v12, a3
; LMULMAX2-RV64-NEXT: vor.vv v10, v12, v10 ; LMULMAX2-RV64-NEXT: vor.vv v10, v12, v10
; LMULMAX2-RV64-NEXT: vsrl.vi v12, v8, 24 ; LMULMAX2-RV64-NEXT: vsrl.vi v12, v8, 24
; LMULMAX2-RV64-NEXT: lui a3, 4080 ; LMULMAX2-RV64-NEXT: lui a4, 4080
; LMULMAX2-RV64-NEXT: vand.vx v12, v12, a3 ; LMULMAX2-RV64-NEXT: vand.vx v12, v12, a4
; LMULMAX2-RV64-NEXT: vsrl.vi v14, v8, 8 ; LMULMAX2-RV64-NEXT: vsrl.vi v14, v8, 8
; LMULMAX2-RV64-NEXT: li a3, 255 ; LMULMAX2-RV64-NEXT: li a5, 255
; LMULMAX2-RV64-NEXT: slli a4, a3, 24 ; LMULMAX2-RV64-NEXT: slli a5, a5, 24
; LMULMAX2-RV64-NEXT: vand.vx v14, v14, a4 ; LMULMAX2-RV64-NEXT: vand.vx v14, v14, a5
; LMULMAX2-RV64-NEXT: vor.vv v12, v14, v12 ; LMULMAX2-RV64-NEXT: vor.vv v12, v14, v12
; LMULMAX2-RV64-NEXT: vor.vv v10, v12, v10 ; LMULMAX2-RV64-NEXT: vor.vv v10, v12, v10
; LMULMAX2-RV64-NEXT: vsll.vi v12, v8, 8 ; LMULMAX2-RV64-NEXT: vand.vx v12, v8, a5
; LMULMAX2-RV64-NEXT: slli a4, a3, 32 ; LMULMAX2-RV64-NEXT: vsll.vi v12, v12, 8
; LMULMAX2-RV64-NEXT: vand.vx v12, v12, a4 ; LMULMAX2-RV64-NEXT: vand.vx v14, v8, a4
; LMULMAX2-RV64-NEXT: vsll.vi v14, v8, 24 ; LMULMAX2-RV64-NEXT: vsll.vi v14, v14, 24
; LMULMAX2-RV64-NEXT: slli a4, a3, 40
; LMULMAX2-RV64-NEXT: vand.vx v14, v14, a4
; LMULMAX2-RV64-NEXT: vor.vv v12, v14, v12 ; LMULMAX2-RV64-NEXT: vor.vv v12, v14, v12
; LMULMAX2-RV64-NEXT: vsll.vx v14, v8, a1 ; LMULMAX2-RV64-NEXT: vsll.vx v14, v8, a1
; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a3
; LMULMAX2-RV64-NEXT: vsll.vx v8, v8, a2 ; LMULMAX2-RV64-NEXT: vsll.vx v8, v8, a2
; LMULMAX2-RV64-NEXT: slli a1, a3, 48
; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a1
; LMULMAX2-RV64-NEXT: vor.vv v8, v14, v8 ; LMULMAX2-RV64-NEXT: vor.vv v8, v14, v8
; LMULMAX2-RV64-NEXT: lui a1, %hi(.LCPI5_0) ; LMULMAX2-RV64-NEXT: lui a1, %hi(.LCPI5_0)
; LMULMAX2-RV64-NEXT: ld a1, %lo(.LCPI5_0)(a1) ; LMULMAX2-RV64-NEXT: ld a1, %lo(.LCPI5_0)(a1)
; LMULMAX2-RV64-NEXT: vor.vv v8, v8, v12 ; LMULMAX2-RV64-NEXT: vor.vv v8, v8, v12
; LMULMAX2-RV64-NEXT: vor.vv v8, v8, v10 ; LMULMAX2-RV64-NEXT: vor.vv v8, v8, v10
; LMULMAX2-RV64-NEXT: vsrl.vi v10, v8, 4 ; LMULMAX2-RV64-NEXT: vsrl.vi v10, v8, 4
; LMULMAX2-RV64-NEXT: vand.vx v10, v10, a1 ; LMULMAX2-RV64-NEXT: vand.vx v10, v10, a1
; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a1 ; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a1
Show All 15 Lines
; LMULMAX2-RV64-NEXT: vor.vv v8, v10, v8 ; LMULMAX2-RV64-NEXT: vor.vv v8, v10, v8
; LMULMAX2-RV64-NEXT: vse64.v v8, (a0) ; LMULMAX2-RV64-NEXT: vse64.v v8, (a0)
; LMULMAX2-RV64-NEXT: ret ; LMULMAX2-RV64-NEXT: ret
; ;
; LMULMAX1-RV32-LABEL: bitreverse_v4i64: ; LMULMAX1-RV32-LABEL: bitreverse_v4i64:
; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-RV32-NEXT: addi a1, a0, 16 ; LMULMAX1-RV32-NEXT: addi a1, a0, 16
; LMULMAX1-RV32-NEXT: vle64.v v12, (a1) ; LMULMAX1-RV32-NEXT: vle64.v v10, (a1)
; LMULMAX1-RV32-NEXT: vle64.v v8, (a0) ; LMULMAX1-RV32-NEXT: vle64.v v8, (a0)
; LMULMAX1-RV32-NEXT: li a2, 56 ; LMULMAX1-RV32-NEXT: li a2, 56
; LMULMAX1-RV32-NEXT: vsrl.vx v9, v12, a2 ; LMULMAX1-RV32-NEXT: vsrl.vx v9, v10, a2
; LMULMAX1-RV32-NEXT: li a3, 40 ; LMULMAX1-RV32-NEXT: li a3, 40
; LMULMAX1-RV32-NEXT: vsrl.vx v10, v12, a3 ; LMULMAX1-RV32-NEXT: vsrl.vx v11, v10, a3
; LMULMAX1-RV32-NEXT: lui a4, 16 ; LMULMAX1-RV32-NEXT: lui a4, 16
; LMULMAX1-RV32-NEXT: addi a4, a4, -256 ; LMULMAX1-RV32-NEXT: addi a4, a4, -256
; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a4 ; LMULMAX1-RV32-NEXT: vand.vx v11, v11, a4
; LMULMAX1-RV32-NEXT: vor.vv v10, v10, v9 ; LMULMAX1-RV32-NEXT: vor.vv v11, v11, v9
; LMULMAX1-RV32-NEXT: vsrl.vi v9, v12, 24 ; LMULMAX1-RV32-NEXT: vsrl.vi v9, v10, 24
; LMULMAX1-RV32-NEXT: lui a5, 4080 ; LMULMAX1-RV32-NEXT: lui a5, 4080
; LMULMAX1-RV32-NEXT: vand.vx v11, v9, a5 ; LMULMAX1-RV32-NEXT: vand.vx v12, v9, a5
; LMULMAX1-RV32-NEXT: li a6, 5 ; LMULMAX1-RV32-NEXT: li a6, 5
; LMULMAX1-RV32-NEXT: vmv.s.x v0, a6 ; LMULMAX1-RV32-NEXT: vmv.s.x v0, a6
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-RV32-NEXT: vmv.v.i v9, 0 ; LMULMAX1-RV32-NEXT: vmv.v.i v9, 0
; LMULMAX1-RV32-NEXT: lui a6, 1044480 ; LMULMAX1-RV32-NEXT: lui a6, 1044480
; LMULMAX1-RV32-NEXT: vmerge.vxm v9, v9, a6, v0 ; LMULMAX1-RV32-NEXT: vmerge.vxm v9, v9, a6, v0
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-RV32-NEXT: vsrl.vi v13, v12, 8 ; LMULMAX1-RV32-NEXT: vsrl.vi v13, v10, 8
; LMULMAX1-RV32-NEXT: vand.vv v13, v13, v9 ; LMULMAX1-RV32-NEXT: vand.vv v13, v13, v9
; LMULMAX1-RV32-NEXT: vor.vv v11, v13, v11 ; LMULMAX1-RV32-NEXT: vor.vv v12, v13, v12
; LMULMAX1-RV32-NEXT: vor.vv v13, v11, v10 ; LMULMAX1-RV32-NEXT: vor.vv v11, v12, v11
; LMULMAX1-RV32-NEXT: li a6, 255 ; LMULMAX1-RV32-NEXT: vsll.vx v12, v10, a2
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX1-RV32-NEXT: vand.vx v13, v10, a4
; LMULMAX1-RV32-NEXT: vmv.v.x v10, a6 ; LMULMAX1-RV32-NEXT: vsll.vx v13, v13, a3
; LMULMAX1-RV32-NEXT: vmerge.vim v10, v10, 0, v0
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-RV32-NEXT: vsll.vi v11, v12, 8
; LMULMAX1-RV32-NEXT: vand.vv v14, v11, v10
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-RV32-NEXT: vmv.v.x v11, a4
; LMULMAX1-RV32-NEXT: vmerge.vim v11, v11, 0, v0
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-RV32-NEXT: vsll.vi v15, v12, 24
; LMULMAX1-RV32-NEXT: vand.vv v15, v15, v11
; LMULMAX1-RV32-NEXT: vor.vv v14, v15, v14
; LMULMAX1-RV32-NEXT: vsll.vx v15, v12, a3
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-RV32-NEXT: vmv.v.x v16, a5
; LMULMAX1-RV32-NEXT: vmerge.vim v16, v16, 0, v0
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-RV32-NEXT: vand.vv v15, v15, v16
; LMULMAX1-RV32-NEXT: vsll.vx v12, v12, a2
; LMULMAX1-RV32-NEXT: vor.vv v12, v12, v15
; LMULMAX1-RV32-NEXT: vor.vv v12, v12, v14
; LMULMAX1-RV32-NEXT: vor.vv v12, v12, v13 ; LMULMAX1-RV32-NEXT: vor.vv v12, v12, v13
; LMULMAX1-RV32-NEXT: vsrl.vi v13, v12, 4 ; LMULMAX1-RV32-NEXT: vand.vx v13, v10, a5
; LMULMAX1-RV32-NEXT: vsll.vi v13, v13, 24
; LMULMAX1-RV32-NEXT: vand.vv v10, v10, v9
; LMULMAX1-RV32-NEXT: vsll.vi v10, v10, 8
; LMULMAX1-RV32-NEXT: vor.vv v10, v13, v10
; LMULMAX1-RV32-NEXT: vor.vv v10, v12, v10
; LMULMAX1-RV32-NEXT: vor.vv v10, v10, v11
; LMULMAX1-RV32-NEXT: vsrl.vi v11, v10, 4
; LMULMAX1-RV32-NEXT: lui a6, 61681 ; LMULMAX1-RV32-NEXT: lui a6, 61681
; LMULMAX1-RV32-NEXT: addi a6, a6, -241 ; LMULMAX1-RV32-NEXT: addi a6, a6, -241
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-RV32-NEXT: vmv.v.x v14, a6 ; LMULMAX1-RV32-NEXT: vmv.v.x v12, a6
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-RV32-NEXT: vand.vv v13, v13, v14 ; LMULMAX1-RV32-NEXT: vand.vv v11, v11, v12
; LMULMAX1-RV32-NEXT: vand.vv v12, v12, v14 ; LMULMAX1-RV32-NEXT: vand.vv v10, v10, v12
; LMULMAX1-RV32-NEXT: vsll.vi v12, v12, 4 ; LMULMAX1-RV32-NEXT: vsll.vi v10, v10, 4
; LMULMAX1-RV32-NEXT: vor.vv v12, v13, v12 ; LMULMAX1-RV32-NEXT: vor.vv v10, v11, v10
; LMULMAX1-RV32-NEXT: vsrl.vi v13, v12, 2 ; LMULMAX1-RV32-NEXT: vsrl.vi v11, v10, 2
; LMULMAX1-RV32-NEXT: lui a6, 209715 ; LMULMAX1-RV32-NEXT: lui a6, 209715
; LMULMAX1-RV32-NEXT: addi a6, a6, 819 ; LMULMAX1-RV32-NEXT: addi a6, a6, 819
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-RV32-NEXT: vmv.v.x v15, a6 ; LMULMAX1-RV32-NEXT: vmv.v.x v13, a6
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-RV32-NEXT: vand.vv v13, v13, v15 ; LMULMAX1-RV32-NEXT: vand.vv v11, v11, v13
; LMULMAX1-RV32-NEXT: vand.vv v12, v12, v15 ; LMULMAX1-RV32-NEXT: vand.vv v10, v10, v13
; LMULMAX1-RV32-NEXT: vsll.vi v12, v12, 2 ; LMULMAX1-RV32-NEXT: vsll.vi v10, v10, 2
; LMULMAX1-RV32-NEXT: vor.vv v12, v13, v12 ; LMULMAX1-RV32-NEXT: vor.vv v10, v11, v10
; LMULMAX1-RV32-NEXT: vsrl.vi v13, v12, 1 ; LMULMAX1-RV32-NEXT: vsrl.vi v11, v10, 1
; LMULMAX1-RV32-NEXT: lui a6, 349525 ; LMULMAX1-RV32-NEXT: lui a6, 349525
; LMULMAX1-RV32-NEXT: addi a6, a6, 1365 ; LMULMAX1-RV32-NEXT: addi a6, a6, 1365
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-RV32-NEXT: vmv.v.x v17, a6 ; LMULMAX1-RV32-NEXT: vmv.v.x v14, a6
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-RV32-NEXT: vand.vv v13, v13, v17 ; LMULMAX1-RV32-NEXT: vand.vv v11, v11, v14
; LMULMAX1-RV32-NEXT: vand.vv v12, v12, v17 ; LMULMAX1-RV32-NEXT: vand.vv v10, v10, v14
; LMULMAX1-RV32-NEXT: vadd.vv v12, v12, v12 ; LMULMAX1-RV32-NEXT: vadd.vv v10, v10, v10
; LMULMAX1-RV32-NEXT: vor.vv v12, v13, v12
; LMULMAX1-RV32-NEXT: vsrl.vx v13, v8, a2
; LMULMAX1-RV32-NEXT: vsrl.vx v18, v8, a3
; LMULMAX1-RV32-NEXT: vand.vx v18, v18, a4
; LMULMAX1-RV32-NEXT: vor.vv v13, v18, v13
; LMULMAX1-RV32-NEXT: vsrl.vi v18, v8, 24
; LMULMAX1-RV32-NEXT: vand.vx v18, v18, a5
; LMULMAX1-RV32-NEXT: vsrl.vi v19, v8, 8
; LMULMAX1-RV32-NEXT: vand.vv v9, v19, v9
; LMULMAX1-RV32-NEXT: vor.vv v9, v9, v18
; LMULMAX1-RV32-NEXT: vor.vv v9, v9, v13
; LMULMAX1-RV32-NEXT: vsll.vi v13, v8, 8
; LMULMAX1-RV32-NEXT: vand.vv v10, v13, v10
; LMULMAX1-RV32-NEXT: vsll.vi v13, v8, 24
; LMULMAX1-RV32-NEXT: vand.vv v11, v13, v11
; LMULMAX1-RV32-NEXT: vor.vv v10, v11, v10 ; LMULMAX1-RV32-NEXT: vor.vv v10, v11, v10
; LMULMAX1-RV32-NEXT: vsll.vx v11, v8, a3 ; LMULMAX1-RV32-NEXT: vsrl.vx v11, v8, a2
; LMULMAX1-RV32-NEXT: vand.vv v11, v11, v16 ; LMULMAX1-RV32-NEXT: vsrl.vx v15, v8, a3
; LMULMAX1-RV32-NEXT: vsll.vx v8, v8, a2 ; LMULMAX1-RV32-NEXT: vand.vx v15, v15, a4
; LMULMAX1-RV32-NEXT: vor.vv v11, v15, v11
; LMULMAX1-RV32-NEXT: vsrl.vi v15, v8, 24
; LMULMAX1-RV32-NEXT: vand.vx v15, v15, a5
; LMULMAX1-RV32-NEXT: vsrl.vi v16, v8, 8
; LMULMAX1-RV32-NEXT: vand.vv v16, v16, v9
; LMULMAX1-RV32-NEXT: vor.vv v15, v16, v15
; LMULMAX1-RV32-NEXT: vor.vv v11, v15, v11
; LMULMAX1-RV32-NEXT: vsll.vx v15, v8, a2
; LMULMAX1-RV32-NEXT: vand.vx v16, v8, a4
; LMULMAX1-RV32-NEXT: vsll.vx v16, v16, a3
; LMULMAX1-RV32-NEXT: vor.vv v15, v15, v16
; LMULMAX1-RV32-NEXT: vand.vx v16, v8, a5
; LMULMAX1-RV32-NEXT: vsll.vi v16, v16, 24
; LMULMAX1-RV32-NEXT: vand.vv v8, v8, v9
; LMULMAX1-RV32-NEXT: vsll.vi v8, v8, 8
; LMULMAX1-RV32-NEXT: vor.vv v8, v16, v8
; LMULMAX1-RV32-NEXT: vor.vv v8, v15, v8
; LMULMAX1-RV32-NEXT: vor.vv v8, v8, v11 ; LMULMAX1-RV32-NEXT: vor.vv v8, v8, v11
; LMULMAX1-RV32-NEXT: vor.vv v8, v8, v10
; LMULMAX1-RV32-NEXT: vor.vv v8, v8, v9
; LMULMAX1-RV32-NEXT: vsrl.vi v9, v8, 4 ; LMULMAX1-RV32-NEXT: vsrl.vi v9, v8, 4
; LMULMAX1-RV32-NEXT: vand.vv v9, v9, v14 ; LMULMAX1-RV32-NEXT: vand.vv v9, v9, v12
; LMULMAX1-RV32-NEXT: vand.vv v8, v8, v14 ; LMULMAX1-RV32-NEXT: vand.vv v8, v8, v12
; LMULMAX1-RV32-NEXT: vsll.vi v8, v8, 4 ; LMULMAX1-RV32-NEXT: vsll.vi v8, v8, 4
; LMULMAX1-RV32-NEXT: vor.vv v8, v9, v8 ; LMULMAX1-RV32-NEXT: vor.vv v8, v9, v8
; LMULMAX1-RV32-NEXT: vsrl.vi v9, v8, 2 ; LMULMAX1-RV32-NEXT: vsrl.vi v9, v8, 2
; LMULMAX1-RV32-NEXT: vand.vv v9, v9, v15 ; LMULMAX1-RV32-NEXT: vand.vv v9, v9, v13
; LMULMAX1-RV32-NEXT: vand.vv v8, v8, v15 ; LMULMAX1-RV32-NEXT: vand.vv v8, v8, v13
; LMULMAX1-RV32-NEXT: vsll.vi v8, v8, 2 ; LMULMAX1-RV32-NEXT: vsll.vi v8, v8, 2
; LMULMAX1-RV32-NEXT: vor.vv v8, v9, v8 ; LMULMAX1-RV32-NEXT: vor.vv v8, v9, v8
; LMULMAX1-RV32-NEXT: vsrl.vi v9, v8, 1 ; LMULMAX1-RV32-NEXT: vsrl.vi v9, v8, 1
; LMULMAX1-RV32-NEXT: vand.vv v9, v9, v17 ; LMULMAX1-RV32-NEXT: vand.vv v9, v9, v14
; LMULMAX1-RV32-NEXT: vand.vv v8, v8, v17 ; LMULMAX1-RV32-NEXT: vand.vv v8, v8, v14
; LMULMAX1-RV32-NEXT: vadd.vv v8, v8, v8 ; LMULMAX1-RV32-NEXT: vadd.vv v8, v8, v8
; LMULMAX1-RV32-NEXT: vor.vv v8, v9, v8 ; LMULMAX1-RV32-NEXT: vor.vv v8, v9, v8
; LMULMAX1-RV32-NEXT: vse64.v v8, (a0) ; LMULMAX1-RV32-NEXT: vse64.v v8, (a0)
; LMULMAX1-RV32-NEXT: vse64.v v12, (a1) ; LMULMAX1-RV32-NEXT: vse64.v v10, (a1)
; LMULMAX1-RV32-NEXT: ret ; LMULMAX1-RV32-NEXT: ret
; ;
; LMULMAX1-RV64-LABEL: bitreverse_v4i64: ; LMULMAX1-RV64-LABEL: bitreverse_v4i64:
; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-RV64-NEXT: addi a1, a0, 16 ; LMULMAX1-RV64-NEXT: addi a1, a0, 16
; LMULMAX1-RV64-NEXT: vle64.v v9, (a1) ; LMULMAX1-RV64-NEXT: vle64.v v9, (a1)
; LMULMAX1-RV64-NEXT: vle64.v v8, (a0) ; LMULMAX1-RV64-NEXT: vle64.v v8, (a0)
; LMULMAX1-RV64-NEXT: li a2, 56 ; LMULMAX1-RV64-NEXT: li a2, 56
; LMULMAX1-RV64-NEXT: vsrl.vx v10, v9, a2 ; LMULMAX1-RV64-NEXT: vsrl.vx v10, v9, a2
; LMULMAX1-RV64-NEXT: li a3, 40 ; LMULMAX1-RV64-NEXT: li a3, 40
; LMULMAX1-RV64-NEXT: vsrl.vx v11, v9, a3 ; LMULMAX1-RV64-NEXT: vsrl.vx v11, v9, a3
; LMULMAX1-RV64-NEXT: lui a4, 16 ; LMULMAX1-RV64-NEXT: lui a4, 16
; LMULMAX1-RV64-NEXT: addiw a4, a4, -256 ; LMULMAX1-RV64-NEXT: addiw a4, a4, -256
; LMULMAX1-RV64-NEXT: vand.vx v11, v11, a4 ; LMULMAX1-RV64-NEXT: vand.vx v11, v11, a4
; LMULMAX1-RV64-NEXT: vor.vv v10, v11, v10 ; LMULMAX1-RV64-NEXT: vor.vv v10, v11, v10
; LMULMAX1-RV64-NEXT: vsrl.vi v11, v9, 24 ; LMULMAX1-RV64-NEXT: vsrl.vi v11, v9, 24
; LMULMAX1-RV64-NEXT: lui a5, 4080 ; LMULMAX1-RV64-NEXT: lui a5, 4080
; LMULMAX1-RV64-NEXT: vand.vx v11, v11, a5 ; LMULMAX1-RV64-NEXT: vand.vx v11, v11, a5
; LMULMAX1-RV64-NEXT: vsrl.vi v12, v9, 8 ; LMULMAX1-RV64-NEXT: vsrl.vi v12, v9, 8
; LMULMAX1-RV64-NEXT: li a6, 255 ; LMULMAX1-RV64-NEXT: li a6, 255
; LMULMAX1-RV64-NEXT: slli a7, a6, 24 ; LMULMAX1-RV64-NEXT: slli a6, a6, 24
; LMULMAX1-RV64-NEXT: vand.vx v12, v12, a7 ; LMULMAX1-RV64-NEXT: vand.vx v12, v12, a6
; LMULMAX1-RV64-NEXT: vor.vv v11, v12, v11 ; LMULMAX1-RV64-NEXT: vor.vv v11, v12, v11
; LMULMAX1-RV64-NEXT: vor.vv v10, v11, v10 ; LMULMAX1-RV64-NEXT: vor.vv v10, v11, v10
; LMULMAX1-RV64-NEXT: vsll.vi v11, v9, 8 ; LMULMAX1-RV64-NEXT: vand.vx v11, v9, a6
; LMULMAX1-RV64-NEXT: slli t0, a6, 32 ; LMULMAX1-RV64-NEXT: vsll.vi v11, v11, 8
; LMULMAX1-RV64-NEXT: vand.vx v11, v11, t0 ; LMULMAX1-RV64-NEXT: vand.vx v12, v9, a5
; LMULMAX1-RV64-NEXT: vsll.vi v12, v9, 24 ; LMULMAX1-RV64-NEXT: vsll.vi v12, v12, 24
; LMULMAX1-RV64-NEXT: slli t1, a6, 40
; LMULMAX1-RV64-NEXT: vand.vx v12, v12, t1
; LMULMAX1-RV64-NEXT: vor.vv v11, v12, v11 ; LMULMAX1-RV64-NEXT: vor.vv v11, v12, v11
; LMULMAX1-RV64-NEXT: vsll.vx v12, v9, a2 ; LMULMAX1-RV64-NEXT: vsll.vx v12, v9, a2
; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a4
; LMULMAX1-RV64-NEXT: vsll.vx v9, v9, a3 ; LMULMAX1-RV64-NEXT: vsll.vx v9, v9, a3
; LMULMAX1-RV64-NEXT: slli a6, a6, 48
; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a6
; LMULMAX1-RV64-NEXT: vor.vv v9, v12, v9 ; LMULMAX1-RV64-NEXT: vor.vv v9, v12, v9
; LMULMAX1-RV64-NEXT: lui t2, %hi(.LCPI5_0) ; LMULMAX1-RV64-NEXT: lui a7, %hi(.LCPI5_0)
; LMULMAX1-RV64-NEXT: ld t2, %lo(.LCPI5_0)(t2) ; LMULMAX1-RV64-NEXT: ld a7, %lo(.LCPI5_0)(a7)
; LMULMAX1-RV64-NEXT: vor.vv v9, v9, v11 ; LMULMAX1-RV64-NEXT: vor.vv v9, v9, v11
; LMULMAX1-RV64-NEXT: vor.vv v9, v9, v10 ; LMULMAX1-RV64-NEXT: vor.vv v9, v9, v10
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 4 ; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 4
; LMULMAX1-RV64-NEXT: vand.vx v10, v10, t2 ; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a7
; LMULMAX1-RV64-NEXT: vand.vx v9, v9, t2 ; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a7
; LMULMAX1-RV64-NEXT: lui t3, %hi(.LCPI5_1) ; LMULMAX1-RV64-NEXT: lui t0, %hi(.LCPI5_1)
; LMULMAX1-RV64-NEXT: ld t3, %lo(.LCPI5_1)(t3) ; LMULMAX1-RV64-NEXT: ld t0, %lo(.LCPI5_1)(t0)
; LMULMAX1-RV64-NEXT: vsll.vi v9, v9, 4 ; LMULMAX1-RV64-NEXT: vsll.vi v9, v9, 4
; LMULMAX1-RV64-NEXT: vor.vv v9, v10, v9 ; LMULMAX1-RV64-NEXT: vor.vv v9, v10, v9
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 2 ; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 2
; LMULMAX1-RV64-NEXT: vand.vx v10, v10, t3 ; LMULMAX1-RV64-NEXT: vand.vx v10, v10, t0
; LMULMAX1-RV64-NEXT: vand.vx v9, v9, t3 ; LMULMAX1-RV64-NEXT: vand.vx v9, v9, t0
; LMULMAX1-RV64-NEXT: lui t4, %hi(.LCPI5_2) ; LMULMAX1-RV64-NEXT: lui t1, %hi(.LCPI5_2)
; LMULMAX1-RV64-NEXT: ld t4, %lo(.LCPI5_2)(t4) ; LMULMAX1-RV64-NEXT: ld t1, %lo(.LCPI5_2)(t1)
; LMULMAX1-RV64-NEXT: vsll.vi v9, v9, 2 ; LMULMAX1-RV64-NEXT: vsll.vi v9, v9, 2
; LMULMAX1-RV64-NEXT: vor.vv v9, v10, v9 ; LMULMAX1-RV64-NEXT: vor.vv v9, v10, v9
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 1 ; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 1
; LMULMAX1-RV64-NEXT: vand.vx v10, v10, t4 ; LMULMAX1-RV64-NEXT: vand.vx v10, v10, t1
; LMULMAX1-RV64-NEXT: vand.vx v9, v9, t4 ; LMULMAX1-RV64-NEXT: vand.vx v9, v9, t1
; LMULMAX1-RV64-NEXT: vadd.vv v9, v9, v9 ; LMULMAX1-RV64-NEXT: vadd.vv v9, v9, v9
; LMULMAX1-RV64-NEXT: vor.vv v9, v10, v9 ; LMULMAX1-RV64-NEXT: vor.vv v9, v10, v9
; LMULMAX1-RV64-NEXT: vsrl.vx v10, v8, a2 ; LMULMAX1-RV64-NEXT: vsrl.vx v10, v8, a2
; LMULMAX1-RV64-NEXT: vsrl.vx v11, v8, a3 ; LMULMAX1-RV64-NEXT: vsrl.vx v11, v8, a3
; LMULMAX1-RV64-NEXT: vand.vx v11, v11, a4 ; LMULMAX1-RV64-NEXT: vand.vx v11, v11, a4
; LMULMAX1-RV64-NEXT: vor.vv v10, v11, v10 ; LMULMAX1-RV64-NEXT: vor.vv v10, v11, v10
; LMULMAX1-RV64-NEXT: vsrl.vi v11, v8, 24 ; LMULMAX1-RV64-NEXT: vsrl.vi v11, v8, 24
; LMULMAX1-RV64-NEXT: vand.vx v11, v11, a5 ; LMULMAX1-RV64-NEXT: vand.vx v11, v11, a5
; LMULMAX1-RV64-NEXT: vsrl.vi v12, v8, 8 ; LMULMAX1-RV64-NEXT: vsrl.vi v12, v8, 8
; LMULMAX1-RV64-NEXT: vand.vx v12, v12, a7 ; LMULMAX1-RV64-NEXT: vand.vx v12, v12, a6
; LMULMAX1-RV64-NEXT: vor.vv v11, v12, v11 ; LMULMAX1-RV64-NEXT: vor.vv v11, v12, v11
; LMULMAX1-RV64-NEXT: vor.vv v10, v11, v10 ; LMULMAX1-RV64-NEXT: vor.vv v10, v11, v10
; LMULMAX1-RV64-NEXT: vsll.vi v11, v8, 8 ; LMULMAX1-RV64-NEXT: vand.vx v11, v8, a6
; LMULMAX1-RV64-NEXT: vand.vx v11, v11, t0 ; LMULMAX1-RV64-NEXT: vsll.vi v11, v11, 8
; LMULMAX1-RV64-NEXT: vsll.vi v12, v8, 24 ; LMULMAX1-RV64-NEXT: vand.vx v12, v8, a5
; LMULMAX1-RV64-NEXT: vand.vx v12, v12, t1 ; LMULMAX1-RV64-NEXT: vsll.vi v12, v12, 24
; LMULMAX1-RV64-NEXT: vor.vv v11, v12, v11 ; LMULMAX1-RV64-NEXT: vor.vv v11, v12, v11
; LMULMAX1-RV64-NEXT: vsll.vx v12, v8, a2 ; LMULMAX1-RV64-NEXT: vsll.vx v12, v8, a2
; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a4
; LMULMAX1-RV64-NEXT: vsll.vx v8, v8, a3 ; LMULMAX1-RV64-NEXT: vsll.vx v8, v8, a3
; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a6
; LMULMAX1-RV64-NEXT: vor.vv v8, v12, v8 ; LMULMAX1-RV64-NEXT: vor.vv v8, v12, v8
; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v11 ; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v11
; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v10 ; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v10
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 4 ; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 4
; LMULMAX1-RV64-NEXT: vand.vx v10, v10, t2 ; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a7
; LMULMAX1-RV64-NEXT: vand.vx v8, v8, t2 ; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a7
; LMULMAX1-RV64-NEXT: vsll.vi v8, v8, 4 ; LMULMAX1-RV64-NEXT: vsll.vi v8, v8, 4
; LMULMAX1-RV64-NEXT: vor.vv v8, v10, v8 ; LMULMAX1-RV64-NEXT: vor.vv v8, v10, v8
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 2 ; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 2
; LMULMAX1-RV64-NEXT: vand.vx v10, v10, t3 ; LMULMAX1-RV64-NEXT: vand.vx v10, v10, t0
; LMULMAX1-RV64-NEXT: vand.vx v8, v8, t3 ; LMULMAX1-RV64-NEXT: vand.vx v8, v8, t0
; LMULMAX1-RV64-NEXT: vsll.vi v8, v8, 2 ; LMULMAX1-RV64-NEXT: vsll.vi v8, v8, 2
; LMULMAX1-RV64-NEXT: vor.vv v8, v10, v8 ; LMULMAX1-RV64-NEXT: vor.vv v8, v10, v8
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 1 ; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 1
; LMULMAX1-RV64-NEXT: vand.vx v10, v10, t4 ; LMULMAX1-RV64-NEXT: vand.vx v10, v10, t1
; LMULMAX1-RV64-NEXT: vand.vx v8, v8, t4 ; LMULMAX1-RV64-NEXT: vand.vx v8, v8, t1
; LMULMAX1-RV64-NEXT: vadd.vv v8, v8, v8 ; LMULMAX1-RV64-NEXT: vadd.vv v8, v8, v8
; LMULMAX1-RV64-NEXT: vor.vv v8, v10, v8 ; LMULMAX1-RV64-NEXT: vor.vv v8, v10, v8
; LMULMAX1-RV64-NEXT: vse64.v v8, (a0) ; LMULMAX1-RV64-NEXT: vse64.v v8, (a0)
; LMULMAX1-RV64-NEXT: vse64.v v9, (a1) ; LMULMAX1-RV64-NEXT: vse64.v v9, (a1)
; LMULMAX1-RV64-NEXT: ret ; LMULMAX1-RV64-NEXT: ret
%a = load <4 x i64>, <4 x i64>* %x %a = load <4 x i64>, <4 x i64>* %x
%b = load <4 x i64>, <4 x i64>* %y %b = load <4 x i64>, <4 x i64>* %y
%c = call <4 x i64> @llvm.bitreverse.v4i64(<4 x i64> %a) %c = call <4 x i64> @llvm.bitreverse.v4i64(<4 x i64> %a)
store <4 x i64> %c, <4 x i64>* %x store <4 x i64> %c, <4 x i64>* %x
ret void ret void
} }
declare <4 x i64> @llvm.bitreverse.v4i64(<4 x i64>) declare <4 x i64> @llvm.bitreverse.v4i64(<4 x i64>)

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll

Show All 27 Lines
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV32-NEXT: vle32.v v8, (a0) ; RV32-NEXT: vle32.v v8, (a0)
; RV32-NEXT: vsrl.vi v9, v8, 8 ; RV32-NEXT: vsrl.vi v9, v8, 8
; RV32-NEXT: lui a1, 16 ; RV32-NEXT: lui a1, 16
; RV32-NEXT: addi a1, a1, -256 ; RV32-NEXT: addi a1, a1, -256
; RV32-NEXT: vand.vx v9, v9, a1 ; RV32-NEXT: vand.vx v9, v9, a1
; RV32-NEXT: vsrl.vi v10, v8, 24 ; RV32-NEXT: vsrl.vi v10, v8, 24
; RV32-NEXT: vor.vv v9, v9, v10 ; RV32-NEXT: vor.vv v9, v9, v10
; RV32-NEXT: vsll.vi v10, v8, 8 ; RV32-NEXT: vand.vx v10, v8, a1
; RV32-NEXT: lui a1, 4080 ; RV32-NEXT: vsll.vi v10, v10, 8
; RV32-NEXT: vand.vx v10, v10, a1
; RV32-NEXT: vsll.vi v8, v8, 24 ; RV32-NEXT: vsll.vi v8, v8, 24
; RV32-NEXT: vor.vv v8, v8, v10 ; RV32-NEXT: vor.vv v8, v8, v10
; RV32-NEXT: vor.vv v8, v8, v9 ; RV32-NEXT: vor.vv v8, v8, v9
; RV32-NEXT: vse32.v v8, (a0) ; RV32-NEXT: vse32.v v8, (a0)
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: bswap_v4i32: ; RV64-LABEL: bswap_v4i32:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV64-NEXT: vle32.v v8, (a0) ; RV64-NEXT: vle32.v v8, (a0)
; RV64-NEXT: vsrl.vi v9, v8, 8 ; RV64-NEXT: vsrl.vi v9, v8, 8
; RV64-NEXT: lui a1, 16 ; RV64-NEXT: lui a1, 16
; RV64-NEXT: addiw a1, a1, -256 ; RV64-NEXT: addiw a1, a1, -256
; RV64-NEXT: vand.vx v9, v9, a1 ; RV64-NEXT: vand.vx v9, v9, a1
; RV64-NEXT: vsrl.vi v10, v8, 24 ; RV64-NEXT: vsrl.vi v10, v8, 24
; RV64-NEXT: vor.vv v9, v9, v10 ; RV64-NEXT: vor.vv v9, v9, v10
; RV64-NEXT: vsll.vi v10, v8, 8 ; RV64-NEXT: vand.vx v10, v8, a1
; RV64-NEXT: lui a1, 4080 ; RV64-NEXT: vsll.vi v10, v10, 8
; RV64-NEXT: vand.vx v10, v10, a1
; RV64-NEXT: vsll.vi v8, v8, 24 ; RV64-NEXT: vsll.vi v8, v8, 24
; RV64-NEXT: vor.vv v8, v8, v10 ; RV64-NEXT: vor.vv v8, v8, v10
; RV64-NEXT: vor.vv v8, v8, v9 ; RV64-NEXT: vor.vv v8, v8, v9
; RV64-NEXT: vse32.v v8, (a0) ; RV64-NEXT: vse32.v v8, (a0)
; RV64-NEXT: ret ; RV64-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x %a = load <4 x i32>, <4 x i32>* %x
%b = load <4 x i32>, <4 x i32>* %y %b = load <4 x i32>, <4 x i32>* %y
%c = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %a) %c = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %a)
Show All 21 Lines
; RV32-NEXT: li a5, 5 ; RV32-NEXT: li a5, 5
; RV32-NEXT: vmv.s.x v0, a5 ; RV32-NEXT: vmv.s.x v0, a5
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV32-NEXT: vmv.v.i v11, 0 ; RV32-NEXT: vmv.v.i v11, 0
; RV32-NEXT: lui a5, 1044480 ; RV32-NEXT: lui a5, 1044480
; RV32-NEXT: vmerge.vxm v11, v11, a5, v0 ; RV32-NEXT: vmerge.vxm v11, v11, a5, v0
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV32-NEXT: vsrl.vi v12, v8, 8 ; RV32-NEXT: vsrl.vi v12, v8, 8
; RV32-NEXT: vand.vv v11, v12, v11 ; RV32-NEXT: vand.vv v12, v12, v11
; RV32-NEXT: vor.vv v10, v11, v10 ; RV32-NEXT: vor.vv v10, v12, v10
; RV32-NEXT: vor.vv v9, v10, v9 ; RV32-NEXT: vor.vv v9, v10, v9
; RV32-NEXT: li a5, 255 ; RV32-NEXT: vsll.vx v10, v8, a1
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; RV32-NEXT: vand.vx v12, v8, a3
; RV32-NEXT: vmv.v.x v10, a5 ; RV32-NEXT: vsll.vx v12, v12, a2
; RV32-NEXT: vmerge.vim v10, v10, 0, v0 ; RV32-NEXT: vor.vv v10, v10, v12
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; RV32-NEXT: vand.vx v12, v8, a4
; RV32-NEXT: vsll.vi v11, v8, 8 ; RV32-NEXT: vsll.vi v12, v12, 24
; RV32-NEXT: vand.vv v10, v11, v10 ; RV32-NEXT: vand.vv v8, v8, v11
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; RV32-NEXT: vsll.vi v8, v8, 8
; RV32-NEXT: vmv.v.x v11, a3 ; RV32-NEXT: vor.vv v8, v12, v8
; RV32-NEXT: vmerge.vim v11, v11, 0, v0 ; RV32-NEXT: vor.vv v8, v10, v8
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV32-NEXT: vsll.vi v12, v8, 24
; RV32-NEXT: vand.vv v11, v12, v11
; RV32-NEXT: vor.vv v10, v11, v10
; RV32-NEXT: vsll.vx v11, v8, a2
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV32-NEXT: vmv.v.x v12, a4
; RV32-NEXT: vmerge.vim v12, v12, 0, v0
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV32-NEXT: vand.vv v11, v11, v12
; RV32-NEXT: vsll.vx v8, v8, a1
; RV32-NEXT: vor.vv v8, v8, v11
; RV32-NEXT: vor.vv v8, v8, v10
; RV32-NEXT: vor.vv v8, v8, v9 ; RV32-NEXT: vor.vv v8, v8, v9
; RV32-NEXT: vse64.v v8, (a0) ; RV32-NEXT: vse64.v v8, (a0)
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: bswap_v2i64: ; RV64-LABEL: bswap_v2i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV64-NEXT: vle64.v v8, (a0) ; RV64-NEXT: vle64.v v8, (a0)
; RV64-NEXT: li a1, 56 ; RV64-NEXT: li a1, 56
; RV64-NEXT: vsrl.vx v9, v8, a1 ; RV64-NEXT: vsrl.vx v9, v8, a1
; RV64-NEXT: li a2, 40 ; RV64-NEXT: li a2, 40
; RV64-NEXT: vsrl.vx v10, v8, a2 ; RV64-NEXT: vsrl.vx v10, v8, a2
; RV64-NEXT: lui a3, 16 ; RV64-NEXT: lui a3, 16
; RV64-NEXT: addiw a3, a3, -256 ; RV64-NEXT: addiw a3, a3, -256
; RV64-NEXT: vand.vx v10, v10, a3 ; RV64-NEXT: vand.vx v10, v10, a3
; RV64-NEXT: vor.vv v9, v10, v9 ; RV64-NEXT: vor.vv v9, v10, v9
; RV64-NEXT: vsrl.vi v10, v8, 24 ; RV64-NEXT: vsrl.vi v10, v8, 24
; RV64-NEXT: lui a3, 4080 ; RV64-NEXT: lui a4, 4080
; RV64-NEXT: vand.vx v10, v10, a3 ; RV64-NEXT: vand.vx v10, v10, a4
; RV64-NEXT: vsrl.vi v11, v8, 8 ; RV64-NEXT: vsrl.vi v11, v8, 8
; RV64-NEXT: li a3, 255 ; RV64-NEXT: li a5, 255
; RV64-NEXT: slli a4, a3, 24 ; RV64-NEXT: slli a5, a5, 24
; RV64-NEXT: vand.vx v11, v11, a4 ; RV64-NEXT: vand.vx v11, v11, a5
; RV64-NEXT: vor.vv v10, v11, v10 ; RV64-NEXT: vor.vv v10, v11, v10
; RV64-NEXT: vor.vv v9, v10, v9 ; RV64-NEXT: vor.vv v9, v10, v9
; RV64-NEXT: vsll.vi v10, v8, 8 ; RV64-NEXT: vand.vx v10, v8, a5
; RV64-NEXT: slli a4, a3, 32 ; RV64-NEXT: vsll.vi v10, v10, 8
; RV64-NEXT: vand.vx v10, v10, a4 ; RV64-NEXT: vand.vx v11, v8, a4
; RV64-NEXT: vsll.vi v11, v8, 24 ; RV64-NEXT: vsll.vi v11, v11, 24
; RV64-NEXT: slli a4, a3, 40
; RV64-NEXT: vand.vx v11, v11, a4
; RV64-NEXT: vor.vv v10, v11, v10 ; RV64-NEXT: vor.vv v10, v11, v10
; RV64-NEXT: vsll.vx v11, v8, a1 ; RV64-NEXT: vsll.vx v11, v8, a1
; RV64-NEXT: vand.vx v8, v8, a3
; RV64-NEXT: vsll.vx v8, v8, a2 ; RV64-NEXT: vsll.vx v8, v8, a2
; RV64-NEXT: slli a1, a3, 48
; RV64-NEXT: vand.vx v8, v8, a1
; RV64-NEXT: vor.vv v8, v11, v8 ; RV64-NEXT: vor.vv v8, v11, v8
; RV64-NEXT: vor.vv v8, v8, v10 ; RV64-NEXT: vor.vv v8, v8, v10
; RV64-NEXT: vor.vv v8, v8, v9 ; RV64-NEXT: vor.vv v8, v8, v9
; RV64-NEXT: vse64.v v8, (a0) ; RV64-NEXT: vse64.v v8, (a0)
; RV64-NEXT: ret ; RV64-NEXT: ret
%a = load <2 x i64>, <2 x i64>* %x %a = load <2 x i64>, <2 x i64>* %x
%b = load <2 x i64>, <2 x i64>* %y %b = load <2 x i64>, <2 x i64>* %y
%c = call <2 x i64> @llvm.bswap.v2i64(<2 x i64> %a) %c = call <2 x i64> @llvm.bswap.v2i64(<2 x i64> %a)
▲ Show 20 Lines • Show All 68 Lines • ▼ Show 20 Lines
; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; LMULMAX2-RV32-NEXT: vle32.v v8, (a0) ; LMULMAX2-RV32-NEXT: vle32.v v8, (a0)
; LMULMAX2-RV32-NEXT: vsrl.vi v10, v8, 8 ; LMULMAX2-RV32-NEXT: vsrl.vi v10, v8, 8
; LMULMAX2-RV32-NEXT: lui a1, 16 ; LMULMAX2-RV32-NEXT: lui a1, 16
; LMULMAX2-RV32-NEXT: addi a1, a1, -256 ; LMULMAX2-RV32-NEXT: addi a1, a1, -256
; LMULMAX2-RV32-NEXT: vand.vx v10, v10, a1 ; LMULMAX2-RV32-NEXT: vand.vx v10, v10, a1
; LMULMAX2-RV32-NEXT: vsrl.vi v12, v8, 24 ; LMULMAX2-RV32-NEXT: vsrl.vi v12, v8, 24
; LMULMAX2-RV32-NEXT: vor.vv v10, v10, v12 ; LMULMAX2-RV32-NEXT: vor.vv v10, v10, v12
; LMULMAX2-RV32-NEXT: vsll.vi v12, v8, 8 ; LMULMAX2-RV32-NEXT: vand.vx v12, v8, a1
; LMULMAX2-RV32-NEXT: lui a1, 4080 ; LMULMAX2-RV32-NEXT: vsll.vi v12, v12, 8
; LMULMAX2-RV32-NEXT: vand.vx v12, v12, a1
; LMULMAX2-RV32-NEXT: vsll.vi v8, v8, 24 ; LMULMAX2-RV32-NEXT: vsll.vi v8, v8, 24
; LMULMAX2-RV32-NEXT: vor.vv v8, v8, v12 ; LMULMAX2-RV32-NEXT: vor.vv v8, v8, v12
; LMULMAX2-RV32-NEXT: vor.vv v8, v8, v10 ; LMULMAX2-RV32-NEXT: vor.vv v8, v8, v10
; LMULMAX2-RV32-NEXT: vse32.v v8, (a0) ; LMULMAX2-RV32-NEXT: vse32.v v8, (a0)
; LMULMAX2-RV32-NEXT: ret ; LMULMAX2-RV32-NEXT: ret
; ;
; LMULMAX2-RV64-LABEL: bswap_v8i32: ; LMULMAX2-RV64-LABEL: bswap_v8i32:
; LMULMAX2-RV64: # %bb.0: ; LMULMAX2-RV64: # %bb.0:
; LMULMAX2-RV64-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; LMULMAX2-RV64-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; LMULMAX2-RV64-NEXT: vle32.v v8, (a0) ; LMULMAX2-RV64-NEXT: vle32.v v8, (a0)
; LMULMAX2-RV64-NEXT: vsrl.vi v10, v8, 8 ; LMULMAX2-RV64-NEXT: vsrl.vi v10, v8, 8
; LMULMAX2-RV64-NEXT: lui a1, 16 ; LMULMAX2-RV64-NEXT: lui a1, 16
; LMULMAX2-RV64-NEXT: addiw a1, a1, -256 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -256
; LMULMAX2-RV64-NEXT: vand.vx v10, v10, a1 ; LMULMAX2-RV64-NEXT: vand.vx v10, v10, a1
; LMULMAX2-RV64-NEXT: vsrl.vi v12, v8, 24 ; LMULMAX2-RV64-NEXT: vsrl.vi v12, v8, 24
; LMULMAX2-RV64-NEXT: vor.vv v10, v10, v12 ; LMULMAX2-RV64-NEXT: vor.vv v10, v10, v12
; LMULMAX2-RV64-NEXT: vsll.vi v12, v8, 8 ; LMULMAX2-RV64-NEXT: vand.vx v12, v8, a1
; LMULMAX2-RV64-NEXT: lui a1, 4080 ; LMULMAX2-RV64-NEXT: vsll.vi v12, v12, 8
; LMULMAX2-RV64-NEXT: vand.vx v12, v12, a1
; LMULMAX2-RV64-NEXT: vsll.vi v8, v8, 24 ; LMULMAX2-RV64-NEXT: vsll.vi v8, v8, 24
; LMULMAX2-RV64-NEXT: vor.vv v8, v8, v12 ; LMULMAX2-RV64-NEXT: vor.vv v8, v8, v12
; LMULMAX2-RV64-NEXT: vor.vv v8, v8, v10 ; LMULMAX2-RV64-NEXT: vor.vv v8, v8, v10
; LMULMAX2-RV64-NEXT: vse32.v v8, (a0) ; LMULMAX2-RV64-NEXT: vse32.v v8, (a0)
; LMULMAX2-RV64-NEXT: ret ; LMULMAX2-RV64-NEXT: ret
; ;
; LMULMAX1-RV32-LABEL: bswap_v8i32: ; LMULMAX1-RV32-LABEL: bswap_v8i32:
; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-RV32-NEXT: addi a1, a0, 16 ; LMULMAX1-RV32-NEXT: addi a1, a0, 16
; LMULMAX1-RV32-NEXT: vle32.v v8, (a1) ; LMULMAX1-RV32-NEXT: vle32.v v8, (a1)
; LMULMAX1-RV32-NEXT: vle32.v v9, (a0) ; LMULMAX1-RV32-NEXT: vle32.v v9, (a0)
; LMULMAX1-RV32-NEXT: vsrl.vi v10, v8, 8 ; LMULMAX1-RV32-NEXT: vsrl.vi v10, v8, 8
; LMULMAX1-RV32-NEXT: lui a2, 16 ; LMULMAX1-RV32-NEXT: lui a2, 16
; LMULMAX1-RV32-NEXT: addi a2, a2, -256 ; LMULMAX1-RV32-NEXT: addi a2, a2, -256
; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a2 ; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a2
; LMULMAX1-RV32-NEXT: vsrl.vi v11, v8, 24 ; LMULMAX1-RV32-NEXT: vsrl.vi v11, v8, 24
; LMULMAX1-RV32-NEXT: vor.vv v10, v10, v11 ; LMULMAX1-RV32-NEXT: vor.vv v10, v10, v11
; LMULMAX1-RV32-NEXT: vsll.vi v11, v8, 8 ; LMULMAX1-RV32-NEXT: vand.vx v11, v8, a2
; LMULMAX1-RV32-NEXT: lui a3, 4080 ; LMULMAX1-RV32-NEXT: vsll.vi v11, v11, 8
; LMULMAX1-RV32-NEXT: vand.vx v11, v11, a3
; LMULMAX1-RV32-NEXT: vsll.vi v8, v8, 24 ; LMULMAX1-RV32-NEXT: vsll.vi v8, v8, 24
; LMULMAX1-RV32-NEXT: vor.vv v8, v8, v11 ; LMULMAX1-RV32-NEXT: vor.vv v8, v8, v11
; LMULMAX1-RV32-NEXT: vor.vv v8, v8, v10 ; LMULMAX1-RV32-NEXT: vor.vv v8, v8, v10
; LMULMAX1-RV32-NEXT: vsrl.vi v10, v9, 8 ; LMULMAX1-RV32-NEXT: vsrl.vi v10, v9, 8
; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a2 ; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a2
; LMULMAX1-RV32-NEXT: vsrl.vi v11, v9, 24 ; LMULMAX1-RV32-NEXT: vsrl.vi v11, v9, 24
; LMULMAX1-RV32-NEXT: vor.vv v10, v10, v11 ; LMULMAX1-RV32-NEXT: vor.vv v10, v10, v11
; LMULMAX1-RV32-NEXT: vsll.vi v11, v9, 8 ; LMULMAX1-RV32-NEXT: vand.vx v11, v9, a2
; LMULMAX1-RV32-NEXT: vand.vx v11, v11, a3 ; LMULMAX1-RV32-NEXT: vsll.vi v11, v11, 8
; LMULMAX1-RV32-NEXT: vsll.vi v9, v9, 24 ; LMULMAX1-RV32-NEXT: vsll.vi v9, v9, 24
; LMULMAX1-RV32-NEXT: vor.vv v9, v9, v11 ; LMULMAX1-RV32-NEXT: vor.vv v9, v9, v11
; LMULMAX1-RV32-NEXT: vor.vv v9, v9, v10 ; LMULMAX1-RV32-NEXT: vor.vv v9, v9, v10
; LMULMAX1-RV32-NEXT: vse32.v v9, (a0) ; LMULMAX1-RV32-NEXT: vse32.v v9, (a0)
; LMULMAX1-RV32-NEXT: vse32.v v8, (a1) ; LMULMAX1-RV32-NEXT: vse32.v v8, (a1)
; LMULMAX1-RV32-NEXT: ret ; LMULMAX1-RV32-NEXT: ret
; ;
; LMULMAX1-RV64-LABEL: bswap_v8i32: ; LMULMAX1-RV64-LABEL: bswap_v8i32:
; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-RV64-NEXT: addi a1, a0, 16 ; LMULMAX1-RV64-NEXT: addi a1, a0, 16
; LMULMAX1-RV64-NEXT: vle32.v v8, (a1) ; LMULMAX1-RV64-NEXT: vle32.v v8, (a1)
; LMULMAX1-RV64-NEXT: vle32.v v9, (a0) ; LMULMAX1-RV64-NEXT: vle32.v v9, (a0)
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 8 ; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 8
; LMULMAX1-RV64-NEXT: lui a2, 16 ; LMULMAX1-RV64-NEXT: lui a2, 16
; LMULMAX1-RV64-NEXT: addiw a2, a2, -256 ; LMULMAX1-RV64-NEXT: addiw a2, a2, -256
; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a2 ; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a2
; LMULMAX1-RV64-NEXT: vsrl.vi v11, v8, 24 ; LMULMAX1-RV64-NEXT: vsrl.vi v11, v8, 24
; LMULMAX1-RV64-NEXT: vor.vv v10, v10, v11 ; LMULMAX1-RV64-NEXT: vor.vv v10, v10, v11
; LMULMAX1-RV64-NEXT: vsll.vi v11, v8, 8 ; LMULMAX1-RV64-NEXT: vand.vx v11, v8, a2
; LMULMAX1-RV64-NEXT: lui a3, 4080 ; LMULMAX1-RV64-NEXT: vsll.vi v11, v11, 8
; LMULMAX1-RV64-NEXT: vand.vx v11, v11, a3
; LMULMAX1-RV64-NEXT: vsll.vi v8, v8, 24 ; LMULMAX1-RV64-NEXT: vsll.vi v8, v8, 24
; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v11 ; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v11
; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v10 ; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v10
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 8 ; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 8
; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a2 ; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a2
; LMULMAX1-RV64-NEXT: vsrl.vi v11, v9, 24 ; LMULMAX1-RV64-NEXT: vsrl.vi v11, v9, 24
; LMULMAX1-RV64-NEXT: vor.vv v10, v10, v11 ; LMULMAX1-RV64-NEXT: vor.vv v10, v10, v11
; LMULMAX1-RV64-NEXT: vsll.vi v11, v9, 8 ; LMULMAX1-RV64-NEXT: vand.vx v11, v9, a2
; LMULMAX1-RV64-NEXT: vand.vx v11, v11, a3 ; LMULMAX1-RV64-NEXT: vsll.vi v11, v11, 8
; LMULMAX1-RV64-NEXT: vsll.vi v9, v9, 24 ; LMULMAX1-RV64-NEXT: vsll.vi v9, v9, 24
; LMULMAX1-RV64-NEXT: vor.vv v9, v9, v11 ; LMULMAX1-RV64-NEXT: vor.vv v9, v9, v11
; LMULMAX1-RV64-NEXT: vor.vv v9, v9, v10 ; LMULMAX1-RV64-NEXT: vor.vv v9, v9, v10
; LMULMAX1-RV64-NEXT: vse32.v v9, (a0) ; LMULMAX1-RV64-NEXT: vse32.v v9, (a0)
; LMULMAX1-RV64-NEXT: vse32.v v8, (a1) ; LMULMAX1-RV64-NEXT: vse32.v v8, (a1)
; LMULMAX1-RV64-NEXT: ret ; LMULMAX1-RV64-NEXT: ret
%a = load <8 x i32>, <8 x i32>* %x %a = load <8 x i32>, <8 x i32>* %x
%b = load <8 x i32>, <8 x i32>* %y %b = load <8 x i32>, <8 x i32>* %y
Show All 22 Lines
; LMULMAX2-RV32-NEXT: li a5, 85 ; LMULMAX2-RV32-NEXT: li a5, 85
; LMULMAX2-RV32-NEXT: vmv.s.x v0, a5 ; LMULMAX2-RV32-NEXT: vmv.s.x v0, a5
; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; LMULMAX2-RV32-NEXT: vmv.v.i v14, 0 ; LMULMAX2-RV32-NEXT: vmv.v.i v14, 0
; LMULMAX2-RV32-NEXT: lui a5, 1044480 ; LMULMAX2-RV32-NEXT: lui a5, 1044480
; LMULMAX2-RV32-NEXT: vmerge.vxm v14, v14, a5, v0 ; LMULMAX2-RV32-NEXT: vmerge.vxm v14, v14, a5, v0
; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; LMULMAX2-RV32-NEXT: vsrl.vi v16, v8, 8 ; LMULMAX2-RV32-NEXT: vsrl.vi v16, v8, 8
; LMULMAX2-RV32-NEXT: vand.vv v14, v16, v14 ; LMULMAX2-RV32-NEXT: vand.vv v16, v16, v14
; LMULMAX2-RV32-NEXT: vor.vv v12, v14, v12 ; LMULMAX2-RV32-NEXT: vor.vv v12, v16, v12
; LMULMAX2-RV32-NEXT: vor.vv v10, v12, v10 ; LMULMAX2-RV32-NEXT: vor.vv v10, v12, v10
; LMULMAX2-RV32-NEXT: li a5, 255 ; LMULMAX2-RV32-NEXT: vsll.vx v12, v8, a1
; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; LMULMAX2-RV32-NEXT: vand.vx v16, v8, a3
; LMULMAX2-RV32-NEXT: vmv.v.x v12, a5 ; LMULMAX2-RV32-NEXT: vsll.vx v16, v16, a2
; LMULMAX2-RV32-NEXT: vmerge.vim v12, v12, 0, v0 ; LMULMAX2-RV32-NEXT: vor.vv v12, v12, v16
; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; LMULMAX2-RV32-NEXT: vand.vx v16, v8, a4
; LMULMAX2-RV32-NEXT: vsll.vi v14, v8, 8 ; LMULMAX2-RV32-NEXT: vsll.vi v16, v16, 24
; LMULMAX2-RV32-NEXT: vand.vv v12, v14, v12 ; LMULMAX2-RV32-NEXT: vand.vv v8, v8, v14
; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; LMULMAX2-RV32-NEXT: vsll.vi v8, v8, 8
; LMULMAX2-RV32-NEXT: vmv.v.x v14, a3 ; LMULMAX2-RV32-NEXT: vor.vv v8, v16, v8
; LMULMAX2-RV32-NEXT: vmerge.vim v14, v14, 0, v0 ; LMULMAX2-RV32-NEXT: vor.vv v8, v12, v8
; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; LMULMAX2-RV32-NEXT: vsll.vi v16, v8, 24
; LMULMAX2-RV32-NEXT: vand.vv v14, v16, v14
; LMULMAX2-RV32-NEXT: vor.vv v12, v14, v12
; LMULMAX2-RV32-NEXT: vsll.vx v14, v8, a2
; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; LMULMAX2-RV32-NEXT: vmv.v.x v16, a4
; LMULMAX2-RV32-NEXT: vmerge.vim v16, v16, 0, v0
; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; LMULMAX2-RV32-NEXT: vand.vv v14, v14, v16
; LMULMAX2-RV32-NEXT: vsll.vx v8, v8, a1
; LMULMAX2-RV32-NEXT: vor.vv v8, v8, v14
; LMULMAX2-RV32-NEXT: vor.vv v8, v8, v12
; LMULMAX2-RV32-NEXT: vor.vv v8, v8, v10 ; LMULMAX2-RV32-NEXT: vor.vv v8, v8, v10
; LMULMAX2-RV32-NEXT: vse64.v v8, (a0) ; LMULMAX2-RV32-NEXT: vse64.v v8, (a0)
; LMULMAX2-RV32-NEXT: ret ; LMULMAX2-RV32-NEXT: ret
; ;
; LMULMAX2-RV64-LABEL: bswap_v4i64: ; LMULMAX2-RV64-LABEL: bswap_v4i64:
; LMULMAX2-RV64: # %bb.0: ; LMULMAX2-RV64: # %bb.0:
; LMULMAX2-RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; LMULMAX2-RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; LMULMAX2-RV64-NEXT: vle64.v v8, (a0) ; LMULMAX2-RV64-NEXT: vle64.v v8, (a0)
; LMULMAX2-RV64-NEXT: li a1, 56 ; LMULMAX2-RV64-NEXT: li a1, 56
; LMULMAX2-RV64-NEXT: vsrl.vx v10, v8, a1 ; LMULMAX2-RV64-NEXT: vsrl.vx v10, v8, a1
; LMULMAX2-RV64-NEXT: li a2, 40 ; LMULMAX2-RV64-NEXT: li a2, 40
; LMULMAX2-RV64-NEXT: vsrl.vx v12, v8, a2 ; LMULMAX2-RV64-NEXT: vsrl.vx v12, v8, a2
; LMULMAX2-RV64-NEXT: lui a3, 16 ; LMULMAX2-RV64-NEXT: lui a3, 16
; LMULMAX2-RV64-NEXT: addiw a3, a3, -256 ; LMULMAX2-RV64-NEXT: addiw a3, a3, -256
; LMULMAX2-RV64-NEXT: vand.vx v12, v12, a3 ; LMULMAX2-RV64-NEXT: vand.vx v12, v12, a3
; LMULMAX2-RV64-NEXT: vor.vv v10, v12, v10 ; LMULMAX2-RV64-NEXT: vor.vv v10, v12, v10
; LMULMAX2-RV64-NEXT: vsrl.vi v12, v8, 24 ; LMULMAX2-RV64-NEXT: vsrl.vi v12, v8, 24
; LMULMAX2-RV64-NEXT: lui a3, 4080 ; LMULMAX2-RV64-NEXT: lui a4, 4080
; LMULMAX2-RV64-NEXT: vand.vx v12, v12, a3 ; LMULMAX2-RV64-NEXT: vand.vx v12, v12, a4
; LMULMAX2-RV64-NEXT: vsrl.vi v14, v8, 8 ; LMULMAX2-RV64-NEXT: vsrl.vi v14, v8, 8
; LMULMAX2-RV64-NEXT: li a3, 255 ; LMULMAX2-RV64-NEXT: li a5, 255
; LMULMAX2-RV64-NEXT: slli a4, a3, 24 ; LMULMAX2-RV64-NEXT: slli a5, a5, 24
; LMULMAX2-RV64-NEXT: vand.vx v14, v14, a4 ; LMULMAX2-RV64-NEXT: vand.vx v14, v14, a5
; LMULMAX2-RV64-NEXT: vor.vv v12, v14, v12 ; LMULMAX2-RV64-NEXT: vor.vv v12, v14, v12
; LMULMAX2-RV64-NEXT: vor.vv v10, v12, v10 ; LMULMAX2-RV64-NEXT: vor.vv v10, v12, v10
; LMULMAX2-RV64-NEXT: vsll.vi v12, v8, 8 ; LMULMAX2-RV64-NEXT: vand.vx v12, v8, a5
; LMULMAX2-RV64-NEXT: slli a4, a3, 32 ; LMULMAX2-RV64-NEXT: vsll.vi v12, v12, 8
; LMULMAX2-RV64-NEXT: vand.vx v12, v12, a4 ; LMULMAX2-RV64-NEXT: vand.vx v14, v8, a4
; LMULMAX2-RV64-NEXT: vsll.vi v14, v8, 24 ; LMULMAX2-RV64-NEXT: vsll.vi v14, v14, 24
; LMULMAX2-RV64-NEXT: slli a4, a3, 40
; LMULMAX2-RV64-NEXT: vand.vx v14, v14, a4
; LMULMAX2-RV64-NEXT: vor.vv v12, v14, v12 ; LMULMAX2-RV64-NEXT: vor.vv v12, v14, v12
; LMULMAX2-RV64-NEXT: vsll.vx v14, v8, a1 ; LMULMAX2-RV64-NEXT: vsll.vx v14, v8, a1
; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a3
; LMULMAX2-RV64-NEXT: vsll.vx v8, v8, a2 ; LMULMAX2-RV64-NEXT: vsll.vx v8, v8, a2
; LMULMAX2-RV64-NEXT: slli a1, a3, 48
; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a1
; LMULMAX2-RV64-NEXT: vor.vv v8, v14, v8 ; LMULMAX2-RV64-NEXT: vor.vv v8, v14, v8
; LMULMAX2-RV64-NEXT: vor.vv v8, v8, v12 ; LMULMAX2-RV64-NEXT: vor.vv v8, v8, v12
; LMULMAX2-RV64-NEXT: vor.vv v8, v8, v10 ; LMULMAX2-RV64-NEXT: vor.vv v8, v8, v10
; LMULMAX2-RV64-NEXT: vse64.v v8, (a0) ; LMULMAX2-RV64-NEXT: vse64.v v8, (a0)
; LMULMAX2-RV64-NEXT: ret ; LMULMAX2-RV64-NEXT: ret
; ;
; LMULMAX1-RV32-LABEL: bswap_v4i64: ; LMULMAX1-RV32-LABEL: bswap_v4i64:
; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-RV32-NEXT: addi a1, a0, 16 ; LMULMAX1-RV32-NEXT: addi a1, a0, 16
; LMULMAX1-RV32-NEXT: vle64.v v9, (a1) ; LMULMAX1-RV32-NEXT: vle64.v v8, (a1)
; LMULMAX1-RV32-NEXT: vle64.v v8, (a0) ; LMULMAX1-RV32-NEXT: vle64.v v9, (a0)
; LMULMAX1-RV32-NEXT: li a2, 56 ; LMULMAX1-RV32-NEXT: li a2, 56
; LMULMAX1-RV32-NEXT: vsrl.vx v10, v9, a2 ; LMULMAX1-RV32-NEXT: vsrl.vx v10, v8, a2
; LMULMAX1-RV32-NEXT: li a3, 40 ; LMULMAX1-RV32-NEXT: li a3, 40
; LMULMAX1-RV32-NEXT: vsrl.vx v11, v9, a3 ; LMULMAX1-RV32-NEXT: vsrl.vx v11, v8, a3
; LMULMAX1-RV32-NEXT: lui a4, 16 ; LMULMAX1-RV32-NEXT: lui a4, 16
; LMULMAX1-RV32-NEXT: addi a4, a4, -256 ; LMULMAX1-RV32-NEXT: addi a4, a4, -256
; LMULMAX1-RV32-NEXT: vand.vx v11, v11, a4 ; LMULMAX1-RV32-NEXT: vand.vx v11, v11, a4
; LMULMAX1-RV32-NEXT: vor.vv v10, v11, v10 ; LMULMAX1-RV32-NEXT: vor.vv v10, v11, v10
; LMULMAX1-RV32-NEXT: vsrl.vi v11, v9, 24 ; LMULMAX1-RV32-NEXT: vsrl.vi v11, v8, 24
; LMULMAX1-RV32-NEXT: lui a5, 4080 ; LMULMAX1-RV32-NEXT: lui a5, 4080
; LMULMAX1-RV32-NEXT: vand.vx v11, v11, a5 ; LMULMAX1-RV32-NEXT: vand.vx v11, v11, a5
; LMULMAX1-RV32-NEXT: li a6, 5 ; LMULMAX1-RV32-NEXT: li a6, 5
; LMULMAX1-RV32-NEXT: vmv.s.x v0, a6 ; LMULMAX1-RV32-NEXT: vmv.s.x v0, a6
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-RV32-NEXT: vmv.v.i v12, 0 ; LMULMAX1-RV32-NEXT: vmv.v.i v12, 0
; LMULMAX1-RV32-NEXT: lui a6, 1044480 ; LMULMAX1-RV32-NEXT: lui a6, 1044480
; LMULMAX1-RV32-NEXT: vmerge.vxm v12, v12, a6, v0 ; LMULMAX1-RV32-NEXT: vmerge.vxm v12, v12, a6, v0
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-RV32-NEXT: vsrl.vi v13, v8, 8
; LMULMAX1-RV32-NEXT: vand.vv v13, v13, v12
; LMULMAX1-RV32-NEXT: vor.vv v11, v13, v11
; LMULMAX1-RV32-NEXT: vor.vv v10, v11, v10
; LMULMAX1-RV32-NEXT: vsll.vx v11, v8, a2
; LMULMAX1-RV32-NEXT: vand.vx v13, v8, a4
; LMULMAX1-RV32-NEXT: vsll.vx v13, v13, a3
; LMULMAX1-RV32-NEXT: vor.vv v11, v11, v13
; LMULMAX1-RV32-NEXT: vand.vx v13, v8, a5
; LMULMAX1-RV32-NEXT: vsll.vi v13, v13, 24
; LMULMAX1-RV32-NEXT: vand.vv v8, v8, v12
; LMULMAX1-RV32-NEXT: vsll.vi v8, v8, 8
; LMULMAX1-RV32-NEXT: vor.vv v8, v13, v8
; LMULMAX1-RV32-NEXT: vor.vv v8, v11, v8
; LMULMAX1-RV32-NEXT: vor.vv v8, v8, v10
; LMULMAX1-RV32-NEXT: vsrl.vx v10, v9, a2
; LMULMAX1-RV32-NEXT: vsrl.vx v11, v9, a3
; LMULMAX1-RV32-NEXT: vand.vx v11, v11, a4
; LMULMAX1-RV32-NEXT: vor.vv v10, v11, v10
; LMULMAX1-RV32-NEXT: vsrl.vi v11, v9, 24
; LMULMAX1-RV32-NEXT: vand.vx v11, v11, a5
; LMULMAX1-RV32-NEXT: vsrl.vi v13, v9, 8 ; LMULMAX1-RV32-NEXT: vsrl.vi v13, v9, 8
; LMULMAX1-RV32-NEXT: vand.vv v13, v13, v12 ; LMULMAX1-RV32-NEXT: vand.vv v13, v13, v12
; LMULMAX1-RV32-NEXT: vor.vv v11, v13, v11 ; LMULMAX1-RV32-NEXT: vor.vv v11, v13, v11
; LMULMAX1-RV32-NEXT: vor.vv v10, v11, v10 ; LMULMAX1-RV32-NEXT: vor.vv v10, v11, v10
; LMULMAX1-RV32-NEXT: li a6, 255 ; LMULMAX1-RV32-NEXT: vsll.vx v11, v9, a2
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX1-RV32-NEXT: vand.vx v13, v9, a4
; LMULMAX1-RV32-NEXT: vmv.v.x v11, a6 ; LMULMAX1-RV32-NEXT: vsll.vx v13, v13, a3
; LMULMAX1-RV32-NEXT: vmerge.vim v11, v11, 0, v0 ; LMULMAX1-RV32-NEXT: vor.vv v11, v11, v13
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-RV32-NEXT: vand.vx v13, v9, a5
; LMULMAX1-RV32-NEXT: vsll.vi v13, v9, 8 ; LMULMAX1-RV32-NEXT: vsll.vi v13, v13, 24
; LMULMAX1-RV32-NEXT: vand.vv v13, v13, v11 ; LMULMAX1-RV32-NEXT: vand.vv v9, v9, v12
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX1-RV32-NEXT: vsll.vi v9, v9, 8
; LMULMAX1-RV32-NEXT: vmv.v.x v14, a4 ; LMULMAX1-RV32-NEXT: vor.vv v9, v13, v9
; LMULMAX1-RV32-NEXT: vmerge.vim v14, v14, 0, v0 ; LMULMAX1-RV32-NEXT: vor.vv v9, v11, v9
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-RV32-NEXT: vsll.vi v15, v9, 24
; LMULMAX1-RV32-NEXT: vand.vv v15, v15, v14
; LMULMAX1-RV32-NEXT: vor.vv v13, v15, v13
; LMULMAX1-RV32-NEXT: vsll.vx v15, v9, a3
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-RV32-NEXT: vmv.v.x v16, a5
; LMULMAX1-RV32-NEXT: vmerge.vim v16, v16, 0, v0
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-RV32-NEXT: vand.vv v15, v15, v16
; LMULMAX1-RV32-NEXT: vsll.vx v9, v9, a2
; LMULMAX1-RV32-NEXT: vor.vv v9, v9, v15
; LMULMAX1-RV32-NEXT: vor.vv v9, v9, v13
; LMULMAX1-RV32-NEXT: vor.vv v9, v9, v10 ; LMULMAX1-RV32-NEXT: vor.vv v9, v9, v10
; LMULMAX1-RV32-NEXT: vsrl.vx v10, v8, a2 ; LMULMAX1-RV32-NEXT: vse64.v v9, (a0)
; LMULMAX1-RV32-NEXT: vsrl.vx v13, v8, a3 ; LMULMAX1-RV32-NEXT: vse64.v v8, (a1)
; LMULMAX1-RV32-NEXT: vand.vx v13, v13, a4
; LMULMAX1-RV32-NEXT: vor.vv v10, v13, v10
; LMULMAX1-RV32-NEXT: vsrl.vi v13, v8, 24
; LMULMAX1-RV32-NEXT: vand.vx v13, v13, a5
; LMULMAX1-RV32-NEXT: vsrl.vi v15, v8, 8
; LMULMAX1-RV32-NEXT: vand.vv v12, v15, v12
; LMULMAX1-RV32-NEXT: vor.vv v12, v12, v13
; LMULMAX1-RV32-NEXT: vor.vv v10, v12, v10
; LMULMAX1-RV32-NEXT: vsll.vi v12, v8, 8
; LMULMAX1-RV32-NEXT: vand.vv v11, v12, v11
; LMULMAX1-RV32-NEXT: vsll.vi v12, v8, 24
; LMULMAX1-RV32-NEXT: vand.vv v12, v12, v14
; LMULMAX1-RV32-NEXT: vor.vv v11, v12, v11
; LMULMAX1-RV32-NEXT: vsll.vx v12, v8, a3
; LMULMAX1-RV32-NEXT: vand.vv v12, v12, v16
; LMULMAX1-RV32-NEXT: vsll.vx v8, v8, a2
; LMULMAX1-RV32-NEXT: vor.vv v8, v8, v12
; LMULMAX1-RV32-NEXT: vor.vv v8, v8, v11
; LMULMAX1-RV32-NEXT: vor.vv v8, v8, v10
; LMULMAX1-RV32-NEXT: vse64.v v8, (a0)
; LMULMAX1-RV32-NEXT: vse64.v v9, (a1)
; LMULMAX1-RV32-NEXT: ret ; LMULMAX1-RV32-NEXT: ret
; ;
; LMULMAX1-RV64-LABEL: bswap_v4i64: ; LMULMAX1-RV64-LABEL: bswap_v4i64:
; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-RV64-NEXT: addi a1, a0, 16 ; LMULMAX1-RV64-NEXT: addi a1, a0, 16
; LMULMAX1-RV64-NEXT: vle64.v v8, (a1) ; LMULMAX1-RV64-NEXT: vle64.v v8, (a1)
; LMULMAX1-RV64-NEXT: vle64.v v9, (a0) ; LMULMAX1-RV64-NEXT: vle64.v v9, (a0)
; LMULMAX1-RV64-NEXT: li a2, 56 ; LMULMAX1-RV64-NEXT: li a2, 56
; LMULMAX1-RV64-NEXT: vsrl.vx v10, v8, a2 ; LMULMAX1-RV64-NEXT: vsrl.vx v10, v8, a2
; LMULMAX1-RV64-NEXT: li a3, 40 ; LMULMAX1-RV64-NEXT: li a3, 40
; LMULMAX1-RV64-NEXT: vsrl.vx v11, v8, a3 ; LMULMAX1-RV64-NEXT: vsrl.vx v11, v8, a3
; LMULMAX1-RV64-NEXT: lui a4, 16 ; LMULMAX1-RV64-NEXT: lui a4, 16
; LMULMAX1-RV64-NEXT: addiw a4, a4, -256 ; LMULMAX1-RV64-NEXT: addiw a4, a4, -256
; LMULMAX1-RV64-NEXT: vand.vx v11, v11, a4 ; LMULMAX1-RV64-NEXT: vand.vx v11, v11, a4
; LMULMAX1-RV64-NEXT: vor.vv v10, v11, v10 ; LMULMAX1-RV64-NEXT: vor.vv v10, v11, v10
; LMULMAX1-RV64-NEXT: vsrl.vi v11, v8, 24 ; LMULMAX1-RV64-NEXT: vsrl.vi v11, v8, 24
; LMULMAX1-RV64-NEXT: lui a5, 4080 ; LMULMAX1-RV64-NEXT: lui a5, 4080
; LMULMAX1-RV64-NEXT: vand.vx v11, v11, a5 ; LMULMAX1-RV64-NEXT: vand.vx v11, v11, a5
; LMULMAX1-RV64-NEXT: vsrl.vi v12, v8, 8 ; LMULMAX1-RV64-NEXT: vsrl.vi v12, v8, 8
; LMULMAX1-RV64-NEXT: li a6, 255 ; LMULMAX1-RV64-NEXT: li a6, 255
; LMULMAX1-RV64-NEXT: slli a7, a6, 24 ; LMULMAX1-RV64-NEXT: slli a6, a6, 24
; LMULMAX1-RV64-NEXT: vand.vx v12, v12, a7 ; LMULMAX1-RV64-NEXT: vand.vx v12, v12, a6
; LMULMAX1-RV64-NEXT: vor.vv v11, v12, v11 ; LMULMAX1-RV64-NEXT: vor.vv v11, v12, v11
; LMULMAX1-RV64-NEXT: vor.vv v10, v11, v10 ; LMULMAX1-RV64-NEXT: vor.vv v10, v11, v10
; LMULMAX1-RV64-NEXT: vsll.vi v11, v8, 8 ; LMULMAX1-RV64-NEXT: vand.vx v11, v8, a6
; LMULMAX1-RV64-NEXT: slli t0, a6, 32 ; LMULMAX1-RV64-NEXT: vsll.vi v11, v11, 8
; LMULMAX1-RV64-NEXT: vand.vx v11, v11, t0 ; LMULMAX1-RV64-NEXT: vand.vx v12, v8, a5
; LMULMAX1-RV64-NEXT: vsll.vi v12, v8, 24 ; LMULMAX1-RV64-NEXT: vsll.vi v12, v12, 24
; LMULMAX1-RV64-NEXT: slli t1, a6, 40
; LMULMAX1-RV64-NEXT: vand.vx v12, v12, t1
; LMULMAX1-RV64-NEXT: vor.vv v11, v12, v11 ; LMULMAX1-RV64-NEXT: vor.vv v11, v12, v11
; LMULMAX1-RV64-NEXT: vsll.vx v12, v8, a2 ; LMULMAX1-RV64-NEXT: vsll.vx v12, v8, a2
; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a4
; LMULMAX1-RV64-NEXT: vsll.vx v8, v8, a3 ; LMULMAX1-RV64-NEXT: vsll.vx v8, v8, a3
; LMULMAX1-RV64-NEXT: slli a6, a6, 48
; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a6
; LMULMAX1-RV64-NEXT: vor.vv v8, v12, v8 ; LMULMAX1-RV64-NEXT: vor.vv v8, v12, v8
; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v11 ; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v11
; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v10 ; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v10
; LMULMAX1-RV64-NEXT: vsrl.vx v10, v9, a2 ; LMULMAX1-RV64-NEXT: vsrl.vx v10, v9, a2
; LMULMAX1-RV64-NEXT: vsrl.vx v11, v9, a3 ; LMULMAX1-RV64-NEXT: vsrl.vx v11, v9, a3
; LMULMAX1-RV64-NEXT: vand.vx v11, v11, a4 ; LMULMAX1-RV64-NEXT: vand.vx v11, v11, a4
; LMULMAX1-RV64-NEXT: vor.vv v10, v11, v10 ; LMULMAX1-RV64-NEXT: vor.vv v10, v11, v10
; LMULMAX1-RV64-NEXT: vsrl.vi v11, v9, 24 ; LMULMAX1-RV64-NEXT: vsrl.vi v11, v9, 24
; LMULMAX1-RV64-NEXT: vand.vx v11, v11, a5 ; LMULMAX1-RV64-NEXT: vand.vx v11, v11, a5
; LMULMAX1-RV64-NEXT: vsrl.vi v12, v9, 8 ; LMULMAX1-RV64-NEXT: vsrl.vi v12, v9, 8
; LMULMAX1-RV64-NEXT: vand.vx v12, v12, a7 ; LMULMAX1-RV64-NEXT: vand.vx v12, v12, a6
; LMULMAX1-RV64-NEXT: vor.vv v11, v12, v11 ; LMULMAX1-RV64-NEXT: vor.vv v11, v12, v11
; LMULMAX1-RV64-NEXT: vor.vv v10, v11, v10 ; LMULMAX1-RV64-NEXT: vor.vv v10, v11, v10
; LMULMAX1-RV64-NEXT: vsll.vi v11, v9, 8 ; LMULMAX1-RV64-NEXT: vand.vx v11, v9, a6
; LMULMAX1-RV64-NEXT: vand.vx v11, v11, t0 ; LMULMAX1-RV64-NEXT: vsll.vi v11, v11, 8
; LMULMAX1-RV64-NEXT: vsll.vi v12, v9, 24 ; LMULMAX1-RV64-NEXT: vand.vx v12, v9, a5
; LMULMAX1-RV64-NEXT: vand.vx v12, v12, t1 ; LMULMAX1-RV64-NEXT: vsll.vi v12, v12, 24
; LMULMAX1-RV64-NEXT: vor.vv v11, v12, v11 ; LMULMAX1-RV64-NEXT: vor.vv v11, v12, v11
; LMULMAX1-RV64-NEXT: vsll.vx v12, v9, a2 ; LMULMAX1-RV64-NEXT: vsll.vx v12, v9, a2
; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a4
; LMULMAX1-RV64-NEXT: vsll.vx v9, v9, a3 ; LMULMAX1-RV64-NEXT: vsll.vx v9, v9, a3
; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a6
; LMULMAX1-RV64-NEXT: vor.vv v9, v12, v9 ; LMULMAX1-RV64-NEXT: vor.vv v9, v12, v9
; LMULMAX1-RV64-NEXT: vor.vv v9, v9, v11 ; LMULMAX1-RV64-NEXT: vor.vv v9, v9, v11
; LMULMAX1-RV64-NEXT: vor.vv v9, v9, v10 ; LMULMAX1-RV64-NEXT: vor.vv v9, v9, v10
; LMULMAX1-RV64-NEXT: vse64.v v9, (a0) ; LMULMAX1-RV64-NEXT: vse64.v v9, (a0)
; LMULMAX1-RV64-NEXT: vse64.v v8, (a1) ; LMULMAX1-RV64-NEXT: vse64.v v8, (a1)
; LMULMAX1-RV64-NEXT: ret ; LMULMAX1-RV64-NEXT: ret
%a = load <4 x i64>, <4 x i64>* %x %a = load <4 x i64>, <4 x i64>* %x
%b = load <4 x i64>, <4 x i64>* %y %b = load <4 x i64>, <4 x i64>* %y
%c = call <4 x i64> @llvm.bswap.v4i64(<4 x i64> %a) %c = call <4 x i64> @llvm.bswap.v4i64(<4 x i64> %a)
store <4 x i64> %c, <4 x i64>* %x store <4 x i64> %c, <4 x i64>* %x
ret void ret void
} }
declare <4 x i64> @llvm.bswap.v4i64(<4 x i64>) declare <4 x i64> @llvm.bswap.v4i64(<4 x i64>)