[AMDGPU][AsmParser] Forbid TFE modifiers for MBUF stores.

[dp]

Could you add a test to check the reported error position? Unfortunately, AsmMatcher often fails to report the location of offending operand. Moving the check to validator may improve diagnostic by using getImmLoc.

[Joe_Nash]

llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

3280

I would prefer dynamic_cast, for safe downcasting.

[foad]

llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

3280

LLVM is generally built with -fno-rtti so I don't think you can use dynamic_cast (can you?).

[Joe_Nash]

llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

3280

Good point, I don't know if it's available. LLVM dyn_cast may also be an option.

[arsenm]

llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

3280

the llvm pseudo-RTTI doesn't just happen and isn't implemented for AMDGPUOperand

[kosarev]

Could you add a test to check the reported error position? Unfortunately, AsmMatcher often fails to report the location of offending operand. Moving the check to validator may improve diagnostic by using getImmLoc.

The currently reported position is the beginning of the first operand and in the current design there seems to be no way to do better, which looks a somewhat severe problem to me and I'd be happy to improve it, but that feels well beyond the scope of this patch, doesn't it.

llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

3280

I understand dyn_cast<> is normally used where we have to discriminate between several possibilities with static_cast<> being the standard solution when we know the dynamic type.

[kosarev]

Moving the check to validator may improve diagnostic by using getImmLoc.

Sorry, missed that part. Will try it.

[dp]

The currently reported position is the beginning of the first operand and in the current design there seems to be no way to do better

If AsmMatcher cannot report error position, why do not move the check to AMDGPUAsmParser::validateInstruction then?

[kosarev]

If AsmMatcher cannot report error position, why do not move the check to AMDGPUAsmParser::validateInstruction then?

Yes, I think the patch actually misuses checkEarlyTargetMatchPredicate(), which looks more like a mean to exclude unrelated instructions from viable candidates (and that's why there supposed to be no diagnostic output). Here, in contrast, we already know it that the chosen instruction is the right one, but don't want it be used, so validation should be the right point for the check, though that will require introducing another relation table, it seems.

[kosarev]

Reworked as suggested and added a test on error position.

[dp]

LGTM.

llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

4607

Maybe "is not enabled with" would be better?

[dp]

llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

4604

With getImmLoc this loop may be reduced to the following code:

auto Loc = getImmLoc(AMDGPUOperand::ImmTyTFE, Operands);
if (Loc != getInstLoc(Operands)) {
  Error(Loc, "...");
  return false;
}

[kosarev]

Reworked to use getInstLoc() and rebased.

[dp]

Still LGTM.

llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

private:
   bool validateVGPRAlign(const MCInst &Inst) const;
   bool validateBLGP(const MCInst &Inst, const OperandVector &Operands);
   bool validateGWS(const MCInst &Inst, const OperandVector &Operands);
   bool validateDivScale(const MCInst &Inst);
   bool validateWaitCnt(const MCInst &Inst, const OperandVector &Operands);
   bool validateCoherencyBits(const MCInst &Inst, const OperandVector &Operands,
                              const SMLoc &IDLoc);
   bool validateExeczVcczOperands(const OperandVector &Operands);
+  bool validateTFE(const MCInst &Inst, const OperandVector &Operands);
   Optional<StringRef> validateLdsDirect(const MCInst &Inst);
   unsigned getConstantBusLimit(unsigned Opcode) const;
   bool usesConstantBus(const MCInst &Inst, unsigned OpIdx);
   bool isInlineConstant(const MCInst &Inst, unsigned OpIdx) const;
   unsigned findImplicitSGPRReadInVOP(const MCInst &Inst) const;
 
   bool isSupportedMnemo(StringRef Mnemo,
                         const FeatureBitset &FBS);

 unsigned AMDGPUAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
   uint64_t TSFlags = MII.get(Inst.getOpcode()).TSFlags;
 
   if ((getForcedEncodingSize() == 32 && (TSFlags & SIInstrFlags::VOP3)) ||
       (getForcedEncodingSize() == 64 && !(TSFlags & SIInstrFlags::VOP3)) ||
       (isForcedDPP() && !(TSFlags & SIInstrFlags::DPP)) ||
       (isForcedSDWA() && !(TSFlags & SIInstrFlags::SDWA)) )
     return Match_InvalidOperand;
 
   if ((TSFlags & SIInstrFlags::VOP3) &&
       (TSFlags & SIInstrFlags::VOPAsmPrefer32Bit) &&
       getForcedEncodingSize() != 64)
     return Match_PreferE32;
 
   if (Inst.getOpcode() == AMDGPU::V_MAC_F32_sdwa_vi ||
       Inst.getOpcode() == AMDGPU::V_MAC_F16_sdwa_vi) {
     // v_mac_f32/16 allow only dst_sel == DWORD;
if (Reg == SRC_EXECZ || Reg == SRC_VCCZ) {
       Error(getRegLoc(Reg, Operands),
             "execz and vccz are not supported on this GPU");
       return false;
     }
   }
   return true;
 }
 
+bool AMDGPUAsmParser::validateTFE(const MCInst &Inst,
+                                  const OperandVector &Operands) {
+  const MCInstrDesc &Desc = MII.get(Inst.getOpcode());
+  if (Desc.mayStore() &&
+      (Desc.TSFlags & (SIInstrFlags::MUBUF | SIInstrFlags::MTBUF))) {
+    SMLoc Loc = getImmLoc(AMDGPUOperand::ImmTyTFE, Operands);
+    if (Loc != getInstLoc(Operands)) {
+      Error(Loc, "TFE modifier has no meaning for store instructions");
+      return false;
+    }
+  }
+
+  return true;
+}
+
 bool AMDGPUAsmParser::validateInstruction(const MCInst &Inst,
                                           const SMLoc &IDLoc,
                                           const OperandVector &Operands) {
   if (auto ErrMsg = validateLdsDirect(Inst)) {
     Error(getRegLoc(LDS_DIRECT, Operands), *ErrMsg);
     return false;
   }
   if (!validateSOPLiteral(Inst)) {
if (!validateDivScale(Inst)) {
     return false;
   }
   if (!validateWaitCnt(Inst, Operands)) {
     return false;
   }
   if (!validateExeczVcczOperands(Operands)) {
     return false;
   }
+  if (!validateTFE(Inst, Operands)) {
+    return false;
+  }
 
   return true;
 }
 
 static std::string AMDGPUMnemonicSpellCheck(StringRef S,
                                             const FeatureBitset &FBS,
                                             unsigned VariantID = 0);
 

llvm/test/MC/AMDGPU/gfx10_err_pos.s

 
 //==============================================================================
 // not a valid operand
 
 v_cndmask_b32_sdwa v5, v1, sext(v2), vcc dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:BYTE_0 src1_sel:WORD_0
 // CHECK: error: not a valid operand.
 // CHECK-NEXT:{{^}}v_cndmask_b32_sdwa v5, v1, sext(v2), vcc dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:BYTE_0 src1_sel:WORD_0
 // CHECK-NEXT:{{^}}                           ^
+
+//==============================================================================
+// TFE modifier has no meaning for store instructions
+
+buffer_store_dword v[1:2], off, s[12:15], s4 tfe
+// CHECK: error: TFE modifier has no meaning for store instructions
+// CHECK-NEXT:{{^}}buffer_store_dword v[1:2], off, s[12:15], s4 tfe
+// CHECK-NEXT:{{^}}                                             ^

llvm/test/MC/AMDGPU/gfx11_asm_err.s

 v_fma_mix_f32_e64_dpp v5, v1, s3, v4 dpp8:[7,6,5,4,3,2,1,0]
 // GFX11: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
 
 v_fma_mixhi_f16_e64_dpp v5, v1, 0, v4 quad_perm:[3,2,1,0]
 // GFX11: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
 
 v_fma_mixlo_f16_e64_dpp v5, v1, 1, v4 dpp8:[7,6,5,4,3,2,1,0]
 // GFX11: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+buffer_store_d16_hi_format_x v[1:2], off, s[12:15], s4 offset:4095 glc slc dlc tfe
+// GFX11: [[@LINE-1]]:{{[0-9]+}}: error: TFE modifier has no meaning for store instructions

llvm/test/MC/AMDGPU/gfx11_asm_mubuf.s

 //  GFX11: encoding: [0xff,0x1f,0x9c,0xe0,0x00,0x01,0x03,0x04]
 
 buffer_store_d16_hi_format_x v1, off, s[12:15], s4 offset:4095 dlc
 //  GFX11: encoding: [0xff,0x2f,0x9c,0xe0,0x00,0x01,0x03,0x04]
 
 buffer_store_d16_hi_format_x v1, off, s[12:15], s4 offset:4095 glc slc dlc
 //  GFX11: encoding: [0xff,0x7f,0x9c,0xe0,0x00,0x01,0x03,0x04]
 
-buffer_store_d16_hi_format_x v[1:2], off, s[12:15], s4 offset:4095 glc slc dlc tfe
-//  GFX11: encoding: [0xff,0x7f,0x9c,0xe0,0x00,0x01,0x23,0x04]
-
 buffer_store_format_x v1, off, s[12:15], s4 offset:4095
 //  GFX11: encoding: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0x04]
 
 buffer_store_format_x v255, off, s[12:15], s4 offset:4095
 //  GFX11: encoding: [0xff,0x0f,0x10,0xe0,0x00,0xff,0x03,0x04]
 
 buffer_store_format_x v1, off, s[16:19], s4 offset:4095
 //  GFX11: encoding: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x04,0x04]

llvm/test/MC/AMDGPU/mubuf-gfx9.s

 buffer_store_byte_d16_hi v1, off, s[4:7], s1
 // GFX9: buffer_store_byte_d16_hi v1, off, s[4:7], s1 ; encoding: [0x00,0x00,0x64,0xe0,0x00,0x01,0x01,0x01]
 // VI-ERR: error: instruction not supported on this GPU
 
 buffer_store_short_d16_hi v1, off, s[4:7], s1
 // GFX9: buffer_store_short_d16_hi v1, off, s[4:7], s1 ; encoding: [0x00,0x00,0x6c,0xe0,0x00,0x01,0x01,0x01]
 // VI-ERR: error: instruction not supported on this GPU
 
-buffer_store_short_d16_hi v[1:2], off, s[4:7], s1 tfe
-// GFX9: buffer_store_short_d16_hi v[1:2], off, s[4:7], s1 tfe ; encoding: [0x00,0x00,0x6c,0xe0,0x00,0x01,0x81,0x01]
-// VI-ERR: error: instruction not supported on this GPU
-
 buffer_load_format_d16_hi_x v5, off, s[8:11], s3
 // GFX9: buffer_load_format_d16_hi_x v5, off, s[8:11], s3 ; encoding: [0x00,0x00,0x98,0xe0,0x00,0x05,0x02,0x03]
 // VI-ERR: error: instruction not supported on this GPU
 
 buffer_load_format_d16_hi_x v5, off, s[8:11], s3 offset:4095
 // GFX9: buffer_load_format_d16_hi_x v5, off, s[8:11], s3 offset:4095 ; encoding: [0xff,0x0f,0x98,0xe0,0x00,0x05,0x02,0x03]
 // VI-ERR: error: instruction not supported on this GPU
 

 buffer_store_format_d16_hi_x v255, off, s[12:15], s4 offset:4095
 // GFX9: buffer_store_format_d16_hi_x v255, off, s[12:15], s4 offset:4095 ; encoding: [0xff,0x0f,0x9c,0xe0,0x00,0xff,0x03,0x04]
 // VI-ERR: error: instruction not supported on this GPU
 
 buffer_store_format_d16_hi_x v1, v0, s[12:15], s4 idxen offset:4095
 // GFX9: buffer_store_format_d16_hi_x v1, v0, s[12:15], s4 idxen offset:4095 ; encoding: [0xff,0x2f,0x9c,0xe0,0x00,0x01,0x03,0x04]
 // VI-ERR: error: instruction not supported on this GPU
 
-buffer_store_format_d16_hi_x v[1:2], v0, s[12:15], s4 idxen offset:4095 tfe
-// GFX9: buffer_store_format_d16_hi_x v[1:2], v0, s[12:15], s4 idxen offset:4095 tfe ; encoding: [0xff,0x2f,0x9c,0xe0,0x00,0x01,0x83,0x04]
-// VI-ERR: error: instruction not supported on this GPU
-
 buffer_store_format_d16_hi_x v1, v0, s[12:15], s4 offen offset:4095
 // GFX9: buffer_store_format_d16_hi_x v1, v0, s[12:15], s4 offen offset:4095 ; encoding: [0xff,0x1f,0x9c,0xe0,0x00,0x01,0x03,0x04]
 // VI-ERR: error: instruction not supported on this GPU
 
 buffer_store_format_d16_hi_x v1, off, s[12:15], s4 offset:4095 glc
 // GFX9: buffer_store_format_d16_hi_x v1, off, s[12:15], s4 offset:4095 glc ; encoding: [0xff,0x4f,0x9c,0xe0,0x00,0x01,0x03,0x04]
 // VI-ERR: error: instruction not supported on this GPU
 
 buffer_store_format_d16_hi_x v1, off, s[12:15], s4 offset:4095 slc
 // GFX9: buffer_store_format_d16_hi_x v1, off, s[12:15], s4 offset:4095 slc ; encoding: [0xff,0x0f,0x9e,0xe0,0x00,0x01,0x03,0x04]
 // VI-ERR: error: instruction not supported on this GPU

llvm/test/MC/AMDGPU/mubuf.s

 buffer_store_dword v1, off, s[4:7], s1 offset:4 glc
 // SICI: buffer_store_dword v1, off, s[4:7], s1 offset:4 glc ; encoding: [0x04,0x40,0x70,0xe0,0x00,0x01,0x01,0x01]
 // VI:   buffer_store_dword v1, off, s[4:7], s1 offset:4 glc ; encoding: [0x04,0x40,0x70,0xe0,0x00,0x01,0x01,0x01]
 
 buffer_store_dword v1, off, s[4:7], s1 offset:4 slc
 // SICI: buffer_store_dword v1, off, s[4:7], s1 offset:4 slc ; encoding: [0x04,0x00,0x70,0xe0,0x00,0x01,0x41,0x01]
 // VI:   buffer_store_dword v1, off, s[4:7], s1 offset:4 slc ; encoding: [0x04,0x00,0x72,0xe0,0x00,0x01,0x01,0x01]
 
-buffer_store_dword v[1:2], off, s[4:7], s1 offset:4 tfe
-// SICI: buffer_store_dword v[1:2], off, s[4:7], s1 offset:4 tfe ; encoding: [0x04,0x00,0x70,0xe0,0x00,0x01,0x81,0x01]
-// VI:   buffer_store_dword v[1:2], off, s[4:7], s1 offset:4 tfe ; encoding: [0x04,0x00,0x70,0xe0,0x00,0x01,0x81,0x01]
-
-buffer_store_dword v[1:2], off, s[4:7], s1 glc tfe
-// SICI: buffer_store_dword v[1:2], off, s[4:7], s1 glc tfe ; encoding: [0x00,0x40,0x70,0xe0,0x00,0x01,0x81,0x01]
-// VI:   buffer_store_dword v[1:2], off, s[4:7], s1 glc tfe ; encoding: [0x00,0x40,0x70,0xe0,0x00,0x01,0x81,0x01]
-
-buffer_store_dword v[1:2], off, s[4:7], s1 offset:4 glc slc tfe
-// SICI: buffer_store_dword v[1:2], off, s[4:7], s1 offset:4 glc slc tfe ; encoding: [0x04,0x40,0x70,0xe0,0x00,0x01,0xc1,0x01]
-// VI:   buffer_store_dword v[1:2], off, s[4:7], s1 offset:4 glc slc tfe ; encoding: [0x04,0x40,0x72,0xe0,0x00,0x01,0x81,0x01]
-
-buffer_store_dword v[1:2], off, ttmp[4:7], ttmp1 offset:4 glc slc tfe
-// SICI: buffer_store_dword v[1:2], off, ttmp[4:7], ttmp1 offset:4 glc slc tfe ; encoding: [0x04,0x40,0x70,0xe0,0x00,0x01,0xdd,0x71]
-// VI:   buffer_store_dword v[1:2], off, ttmp[4:7], ttmp1 offset:4 glc slc tfe ; encoding: [0x04,0x40,0x72,0xe0,0x00,0x01,0x9d,0x71]
-
-buffer_store_dwordx2 v[1:3], off, ttmp[4:7], ttmp1 offset:4 glc slc tfe
-// SICI: buffer_store_dwordx2 v[1:3], off, ttmp[4:7], ttmp1 offset:4 glc slc tfe ; encoding: [0x04,0x40,0x74,0xe0,0x00,0x01,0xdd,0x71]
-// VI:   buffer_store_dwordx2 v[1:3], off, ttmp[4:7], ttmp1 offset:4 glc slc tfe ; encoding: [0x04,0x40,0x76,0xe0,0x00,0x01,0x9d,0x71]
-
 //===----------------------------------------------------------------------===//
 // store - vgpr offset
 //===----------------------------------------------------------------------===//
 
 buffer_store_dword v1, v2, s[4:7], s1 offen
 // SICI: buffer_store_dword v1, v2, s[4:7], s1 offen ; encoding: [0x00,0x10,0x70,0xe0,0x02,0x01,0x01,0x01]
 // VI:   buffer_store_dword v1, v2, s[4:7], s1 offen ; encoding: [0x00,0x10,0x70,0xe0,0x02,0x01,0x01,0x01]
 
 buffer_store_dword v1, v2, s[4:7], s1 offen offset:4
 // SICI: buffer_store_dword v1, v2, s[4:7], s1 offen offset:4 ; encoding: [0x04,0x10,0x70,0xe0,0x02,0x01,0x01,0x01]
 // VI:   buffer_store_dword v1, v2, s[4:7], s1 offen offset:4 ; encoding: [0x04,0x10,0x70,0xe0,0x02,0x01,0x01,0x01]
 
 buffer_store_dword v1, v2, s[4:7], s1 offen offset:4 glc
 // SICI: buffer_store_dword v1, v2, s[4:7], s1 offen  offset:4 glc ; encoding: [0x04,0x50,0x70,0xe0,0x02,0x01,0x01,0x01]
 // VI:   buffer_store_dword v1, v2, s[4:7], s1 offen offset:4 glc ; encoding: [0x04,0x50,0x70,0xe0,0x02,0x01,0x01,0x01]
 
 buffer_store_dword v1, v2, s[4:7], s1 offen offset:4 slc
 // SICI: buffer_store_dword v1, v2, s[4:7], s1 offen offset:4 slc ; encoding: [0x04,0x10,0x70,0xe0,0x02,0x01,0x41,0x01]
 // VI:   buffer_store_dword v1, v2, s[4:7], s1 offen offset:4 slc ; encoding: [0x04,0x10,0x72,0xe0,0x02,0x01,0x01,0x01]
 
-buffer_store_dword v[1:2], v2, s[4:7], s1 offen offset:4 tfe
-// SICI: buffer_store_dword v[1:2], v2, s[4:7], s1 offen offset:4 tfe ; encoding: [0x04,0x10,0x70,0xe0,0x02,0x01,0x81,0x01]
-// VI:   buffer_store_dword v[1:2], v2, s[4:7], s1 offen offset:4 tfe ; encoding: [0x04,0x10,0x70,0xe0,0x02,0x01,0x81,0x01]
-
-buffer_store_dword v[1:2], v2, s[4:7], s1 offen glc tfe
-// SICI: buffer_store_dword v[1:2], v2, s[4:7], s1 offen glc tfe ; encoding: [0x00,0x50,0x70,0xe0,0x02,0x01,0x81,0x01]
-// VI:   buffer_store_dword v[1:2], v2, s[4:7], s1 offen glc tfe ; encoding: [0x00,0x50,0x70,0xe0,0x02,0x01,0x81,0x01]
-
-buffer_store_dword v[1:2], v2, s[4:7], s1 offen offset:4 glc slc tfe
-// SICI: buffer_store_dword v[1:2], v2, s[4:7], s1 offen offset:4 glc slc tfe ; encoding: [0x04,0x50,0x70,0xe0,0x02,0x01,0xc1,0x01]
-// VI:   buffer_store_dword v[1:2], v2, s[4:7], s1 offen offset:4 glc slc tfe ; encoding: [0x04,0x50,0x72,0xe0,0x02,0x01,0x81,0x01]
-
-buffer_store_dword v[1:2], v2, ttmp[4:7], ttmp1 offen offset:4 glc slc tfe
-// SICI: buffer_store_dword v[1:2], v2, ttmp[4:7], ttmp1 offen offset:4 glc slc tfe ; encoding: [0x04,0x50,0x70,0xe0,0x02,0x01,0xdd,0x71]
-// VI:   buffer_store_dword v[1:2], v2, ttmp[4:7], ttmp1 offen offset:4 glc slc tfe ; encoding: [0x04,0x50,0x72,0xe0,0x02,0x01,0x9d,0x71]
-
-buffer_store_dwordx3 v[1:4], v2, ttmp[4:7], ttmp1 offen offset:4 glc slc tfe
-// SICI: buffer_store_dwordx3 v[1:4], v2, ttmp[4:7], ttmp1 offen offset:4 glc slc tfe ; encoding: [0x04,0x50,0x7c,0xe0,0x02,0x01,0xdd,0x71]
-// VI:   buffer_store_dwordx3 v[1:4], v2, ttmp[4:7], ttmp1 offen offset:4 glc slc tfe ; encoding: [0x04,0x50,0x7a,0xe0,0x02,0x01,0x9d,0x71]
-
 //===----------------------------------------------------------------------===//
 // store - vgpr index
 //===----------------------------------------------------------------------===//
 
 buffer_store_dword v1, v2, s[4:7], s1 idxen
 // SICI: buffer_store_dword v1, v2, s[4:7], s1 idxen ; encoding: [0x00,0x20,0x70,0xe0,0x02,0x01,0x01,0x01]
 // VI:   buffer_store_dword v1, v2, s[4:7], s1 idxen ; encoding: [0x00,0x20,0x70,0xe0,0x02,0x01,0x01,0x01]
 
 buffer_store_dword v1, v2, s[4:7], s1 idxen offset:4
 // SICI: buffer_store_dword v1, v2, s[4:7], s1 idxen offset:4 ; encoding: [0x04,0x20,0x70,0xe0,0x02,0x01,0x01,0x01]
 // VI:   buffer_store_dword v1, v2, s[4:7], s1 idxen offset:4 ; encoding: [0x04,0x20,0x70,0xe0,0x02,0x01,0x01,0x01]
 
 buffer_store_dword v1, v2, s[4:7], s1 idxen offset:4 glc
 // SICI: buffer_store_dword v1, v2, s[4:7], s1 idxen offset:4 glc ; encoding: [0x04,0x60,0x70,0xe0,0x02,0x01,0x01,0x01]
 // VI:   buffer_store_dword v1, v2, s[4:7], s1 idxen offset:4 glc ; encoding: [0x04,0x60,0x70,0xe0,0x02,0x01,0x01,0x01]
 
 buffer_store_dword v1, v2, s[4:7], s1 idxen offset:4 slc
 // SICI: buffer_store_dword v1, v2, s[4:7], s1 idxen offset:4 slc ; encoding: [0x04,0x20,0x70,0xe0,0x02,0x01,0x41,0x01]
 // VI:   buffer_store_dword v1, v2, s[4:7], s1 idxen offset:4 slc ; encoding: [0x04,0x20,0x72,0xe0,0x02,0x01,0x01,0x01]
 
-buffer_store_dword v[1:2], v2, s[4:7], s1 idxen offset:4 tfe
-// SICI: buffer_store_dword v[1:2], v2, s[4:7], s1 idxen offset:4 tfe ; encoding: [0x04,0x20,0x70,0xe0,0x02,0x01,0x81,0x01]
-// VI:   buffer_store_dword v[1:2], v2, s[4:7], s1 idxen offset:4 tfe ; encoding: [0x04,0x20,0x70,0xe0,0x02,0x01,0x81,0x01]
-
-buffer_store_dword v[1:2], v2, s[4:7], s1 idxen glc tfe
-// SICI: buffer_store_dword v[1:2], v2, s[4:7], s1 idxen glc tfe ; encoding: [0x00,0x60,0x70,0xe0,0x02,0x01,0x81,0x01]
-// VI:   buffer_store_dword v[1:2], v2, s[4:7], s1 idxen glc tfe ; encoding: [0x00,0x60,0x70,0xe0,0x02,0x01,0x81,0x01]
-
-buffer_store_dword v[1:2], v2, s[4:7], s1 idxen offset:4 glc slc tfe
-// SICI: buffer_store_dword v[1:2], v2, s[4:7], s1 idxen offset:4 glc slc tfe ; encoding: [0x04,0x60,0x70,0xe0,0x02,0x01,0xc1,0x01]
-// VI:   buffer_store_dword v[1:2], v2, s[4:7], s1 idxen offset:4 glc slc tfe ; encoding: [0x04,0x60,0x72,0xe0,0x02,0x01,0x81,0x01]
-
-buffer_store_dword v[1:2], v2, ttmp[4:7], ttmp1 idxen offset:4 glc slc tfe
-// SICI: buffer_store_dword v[1:2], v2, ttmp[4:7], ttmp1 idxen offset:4 glc slc tfe ; encoding: [0x04,0x60,0x70,0xe0,0x02,0x01,0xdd,0x71]
-// VI:   buffer_store_dword v[1:2], v2, ttmp[4:7], ttmp1 idxen offset:4 glc slc tfe ; encoding: [0x04,0x60,0x72,0xe0,0x02,0x01,0x9d,0x71]
-
 //===----------------------------------------------------------------------===//
 // store - vgpr index and offset
 //===----------------------------------------------------------------------===//
 
 buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen
 // SICI: buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen ; encoding: [0x00,0x30,0x70,0xe0,0x02,0x01,0x01,0x01]
 // VI:   buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen ; encoding: [0x00,0x30,0x70,0xe0,0x02,0x01,0x01,0x01]
 
 buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4
 // SICI: buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 ; encoding: [0x04,0x30,0x70,0xe0,0x02,0x01,0x01,0x01]
 // VI:   buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 ; encoding: [0x04,0x30,0x70,0xe0,0x02,0x01,0x01,0x01]
 
 buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 glc
 // SICI: buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 glc ; encoding: [0x04,0x70,0x70,0xe0,0x02,0x01,0x01,0x01]
 // VI:   buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 glc ; encoding: [0x04,0x70,0x70,0xe0,0x02,0x01,0x01,0x01]
 
 buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 slc
 // SICI: buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 slc ; encoding: [0x04,0x30,0x70,0xe0,0x02,0x01,0x41,0x01]
 // VI:   buffer_store_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 slc ; encoding: [0x04,0x30,0x72,0xe0,0x02,0x01,0x01,0x01]
 
-buffer_store_dword v[1:2], v[2:3], s[4:7], s1 idxen offen offset:4 tfe
-// SICI: buffer_store_dword v[1:2], v[2:3], s[4:7], s1 idxen offen offset:4 tfe ; encoding: [0x04,0x30,0x70,0xe0,0x02,0x01,0x81,0x01]
-// VI:   buffer_store_dword v[1:2], v[2:3], s[4:7], s1 idxen offen offset:4 tfe ; encoding: [0x04,0x30,0x70,0xe0,0x02,0x01,0x81,0x01]
-
-buffer_store_dword v[1:2], v[2:3], s[4:7], s1 idxen offen glc tfe
-// SICI: buffer_store_dword v[1:2], v[2:3], s[4:7], s1 idxen offen glc tfe ; encoding: [0x00,0x70,0x70,0xe0,0x02,0x01,0x81,0x01]
-// VI:   buffer_store_dword v[1:2], v[2:3], s[4:7], s1 idxen offen glc tfe ; encoding: [0x00,0x70,0x70,0xe0,0x02,0x01,0x81,0x01]
-
-buffer_store_dword v[1:2], v[2:3], s[4:7], s1 idxen offen offset:4 glc slc tfe
-// SICI: buffer_store_dword v[1:2], v[2:3], s[4:7], s1 idxen offen offset:4 glc slc tfe ; encoding: [0x04,0x70,0x70,0xe0,0x02,0x01,0xc1,0x01]
-// VI:   buffer_store_dword v[1:2], v[2:3], s[4:7], s1 idxen offen offset:4 glc slc tfe ; encoding: [0x04,0x70,0x72,0xe0,0x02,0x01,0x81,0x01]
-
-buffer_store_dword v[1:2], v[2:3], ttmp[4:7], ttmp1 idxen offen offset:4 glc slc tfe
-// SICI: buffer_store_dword v[1:2], v[2:3], ttmp[4:7], ttmp1 idxen offen offset:4 glc slc tfe ; encoding: [0x04,0x70,0x70,0xe0,0x02,0x01,0xdd,0x71]
-// VI:   buffer_store_dword v[1:2], v[2:3], ttmp[4:7], ttmp1 idxen offen offset:4 glc slc tfe ; encoding: [0x04,0x70,0x72,0xe0,0x02,0x01,0x9d,0x71]
-
 //===----------------------------------------------------------------------===//
 // store - addr64
 //===----------------------------------------------------------------------===//
 
 buffer_store_dword v1, v[2:3], s[4:7], s1 addr64
 // SICI: buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 ; encoding: [0x00,0x80,0x70,0xe0,0x02,0x01,0x01,0x01]
 // NOVI: error: operands are not valid for this GPU or mode
 
 buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 offset:4
 // SICI: buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 ; encoding: [0x04,0x80,0x70,0xe0,0x02,0x01,0x01,0x01]
 // NOVI: error: operands are not valid for this GPU or mode
 
 buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 glc
 // SICI: buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 glc ; encoding: [0x04,0xc0,0x70,0xe0,0x02,0x01,0x01,0x01]
 // NOVI: error: operands are not valid for this GPU or mode
 
 buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 slc
 // SICI: buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 slc ; encoding: [0x04,0x80,0x70,0xe0,0x02,0x01,0x41,0x01]
 // NOVI: error: operands are not valid for this GPU or mode
 
-buffer_store_dword v[1:2], v[2:3], s[4:7], s1 addr64 offset:4 tfe
-// SICI: buffer_store_dword v[1:2], v[2:3], s[4:7], s1 addr64 offset:4 tfe ; encoding: [0x04,0x80,0x70,0xe0,0x02,0x01,0x81,0x01]
-// NOVI: error: operands are not valid for this GPU or mode
-
-buffer_store_dword v[1:2], v[2:3], s[4:7], s1 addr64 glc tfe
-// SICI: buffer_store_dword v[1:2], v[2:3], s[4:7], s1 addr64 glc tfe ; encoding: [0x00,0xc0,0x70,0xe0,0x02,0x01,0x81,0x01]
-// NOVI: error: operands are not valid for this GPU or mode
-
-buffer_store_dword v[1:2], v[2:3], s[4:7], s1 addr64 offset:4 glc slc tfe
-// SICI: buffer_store_dword v[1:2], v[2:3], s[4:7], s1 addr64 offset:4 glc slc tfe ; encoding: [0x04,0xc0,0x70,0xe0,0x02,0x01,0xc1,0x01]
-// NOVI: error: operands are not valid for this GPU or mode
-
-buffer_store_dword v[1:2], v[2:3], ttmp[4:7], ttmp1 addr64 offset:4 glc slc tfe
-// SICI: buffer_store_dword v[1:2], v[2:3], ttmp[4:7], ttmp1 addr64 offset:4 glc slc tfe ; encoding: [0x04,0xc0,0x70,0xe0,0x02,0x01,0xdd,0x71]
-// NOVI: error: operands are not valid for this GPU or mode
-
 //===----------------------------------------------------------------------===//
 // Instructions
 //===----------------------------------------------------------------------===//
 
 buffer_load_format_x v1, off, s[4:7], s1
 // SICI: buffer_load_format_x v1, off, s[4:7], s1 ; encoding: [0x00,0x00,0x00,0xe0,0x00,0x01,0x01,0x01]
 // VI:   buffer_load_format_x v1, off, s[4:7], s1 ; encoding: [0x00,0x00,0x00,0xe0,0x00,0x01,0x01,0x01]
 

 // NOSICI: error: instruction not supported on this GPU
 // NOVI:   error: invalid operand for instruction
 
 buffer_load_dword off, s[8:11], s3
 // NOSICIVI: error: too few operands for instruction
 
 buffer_load_dword off, s[8:11], s3 offset:1
 // NOSICIVI: error: too few operands for instruction
+
+buffer_store_dword v[1:2], off, s[4:7], s1 tfe
+// NOSICIVI: error: TFE modifier has no meaning for store instructions