[PowerPC] Implement 64-bit ELFv2 Calling Convention in TableGen (for integers/floats/vectors in registers)

[amyk]

Summary

This patch partially implements the parameter passing rules outlined in the ELFv2 ABI
within TableGen. Specifically, it implements the parameter assignment of integers, floats, and
vectors within registers - where the GPR numbering will be "skipped" depending on the ordering
of floats and vectors that appear within a parameter list.

As we begin to adopt GlobalISel to the PowerPC backend, there is a need for a TableGen definition
that encapsulates the ELFv2 parameter passing rules. Thus, this patch also changes the default
calling convention that is returned within the ccAssignFnForCall() function used in our GlobalISel
implementation, and also adds some additional testing of the calling convention that is implemented.

Future patches that build on top of this initial TableGen definition will aim to add more of the
ABI complexities, including support for additional types and also in-memory arguments.

[Kai]

Some nit comments but in general looks good to me.

llvm/lib/Target/PowerPC/PPCCallingConv.cpp

1

Sorry, that is not really part of your functionality but it confused me a lot.

16–18

Since this is only used in CC_PPC64_ELF_Shadow_GPR_Regs it can be moved inside the function.
You could also think about using an ArrayRef which would eliminate the need for ELF64NumArgGPRs:

static ArrayRef<MCPhysReg> ELF64ArgGPRs = {PPC::X3, PPC::X4, PPC::X5, PPC::X6,
                                           PPC::X7, PPC::X8, PPC::X9, PPC::X10};

31

I wonder if the following conditions will be easier to understand if you add an quick exit here:

if (FirstUnallocGPR == ELF64NumArgGPRs)
  return false;

llvm/lib/Target/PowerPC/PPCCallingConv.td

134

Please check the length of the line here and the long lines below.

[amyk]

llvm/lib/Target/PowerPC/PPCCallingConv.cpp

16–18

Thanks for the suggestion, Kai!
I just wanted to understand this a bit more. Is the suggestion to instead use ArrayRef and also the size() utility that comes along with it? If that is the case, wouldn't I still require ELF64NumArgGPRs?

My apologies if I may have misunderstood the suggestion.

[amyk]

Address review comments from Kai regarding early exit, moving variables into the calling convention function and TD file definition line length.

I will address the comments regarding ArrayRef comment once I receive clarification.

[amyk]

Rebase patch. I also sync'd with Kai offline and the current implementation using a static const MCPhysReg array and keeping ELF64NumArgGPRs is OK to keep.

@nemanjai Whenever you get the chance, are you able to take a look at this patch?

[stefanp]

Silly question:
Can we now get rid of CC_PPC64_ELF_FIS completely?

llvm/lib/Target/PowerPC/PPCCallingConv.cpp

24

nit:

This function handles the shadowing the GPRs for fp and vector types.

to:

This function handles the shadowing of GPRs for fp and vector types.

43

I'm not sure you need this computation at all.
LocVT.getSizeInBits() is either 32 or 64 because we know that LocVT is either MVT::f32 or MVT::f64.
However, in that case

f32
SizeInDWord = (32 + 63) / 64 = 1
f64
SizeInDWord = (64 + 63) / 64 = 1

Both are integer divisions which just discard the decimal part. So, it looks to always be 1 in this situation.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

18258

Does this also need to be changed in PPCFastISel?

[amyk]

llvm/lib/Target/PowerPC/PPCCallingConv.cpp

24

Good catch, I will update this.

43

That's actually a good point. Thanks Stefan.

[amyk]

Address review comments:

• Update comments.
• Clean up section involving shadowing GPRs for float/double.

[amyk]

@stefanp Thanks for the review and the questions!

Can we now get rid of CC_PPC64_ELF_FIS completely?

That’s a good question! This is related to your question about updating PPCFastISel. From what I can tell, it looks like mine covers everything the PPCFastISel one covers:

// Simple calling convention for 64-bit ELF PowerPC fast isel.
// Only handle ints and floats.  All ints are promoted to i64.
// Vector types and quadword ints are not handled.
let Entry = 1 in
def CC_PPC64_ELF_FIS : CallingConv<[
  CCIfCC<“CallingConv::AnyReg”, CCDelegateTo<CC_PPC64_AnyReg>>,

  CCIfType<[i1],  CCPromoteToType<i64>>,
  CCIfType<[i8],  CCPromoteToType<i64>>,
  CCIfType<[i16], CCPromoteToType<i64>>,
  CCIfType<[i32], CCPromoteToType<i64>>,
  CCIfType<[i64], CCAssignToReg<[X3, X4, X5, X6, X7, X8, X9, X10]>>,
  CCIfType<[f32, f64], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>
]>;

Although I realize there is a separate return value one that handles i128 that this patch does not yet handle:

// Simple return-value convention for 64-bit ELF PowerPC fast isel.
// All small ints are promoted to i64.  Vector types, quadword ints,
// and multiple register returns are “supported” to avoid compile
// errors, but none are handled by the fast selector.
let Entry = 1 in
def RetCC_PPC64_ELF_FIS : CallingConv<[
  CCIfCC<“CallingConv::AnyReg”, CCDelegateTo<RetCC_PPC64_AnyReg>>,

  CCIfType<[i1],   CCPromoteToType<i64>>,
  CCIfType<[i8],   CCPromoteToType<i64>>,
  CCIfType<[i16],  CCPromoteToType<i64>>,
  CCIfType<[i32],  CCPromoteToType<i64>>,
  CCIfType<[i64],  CCAssignToReg<[X3, X4, X5, X6]>>,
  CCIfType<[i128], CCAssignToReg<[X3, X4, X5, X6]>>,
  CCIfType<[f32],  CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>,
  CCIfType<[f64],  CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>,
  CCIfType<[f128],
           CCIfSubtarget<“hasAltivec()“,
           CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9]>>>,
  CCIfType<[v16i8, v8i16, v4i32, v2i64, v1i128, v4f32, v2f64],
           CCIfSubtarget<“hasAltivec()“,
           CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9]>>>
]>;

As I mentioned in one of my replies to your other comments, I did try to use this definition instead of the FastISel ones within PPCFastISel.cpp and there weren’t any issues.
It may be possible that we can get rid of CC_PPC64_ELF_FIS, although I’m not sure if we should do it within this patch. @nemanjai Do you have any thoughts on this?

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

18258

Just wanted to double check, do you mean if I need to update the calling convention used within PPCFastISel from CC_PPC64_ELF_FIS -> CC_PPC64_ELF?

If so, that’s actually a good point. I see that the FastISel TableGen definition is only a super simple one that handles ints and floats, and this one is supposed to be a more full implementation.

I actually did a quick test to see if anything went wrong if I removed the old FastISel definitions and replaced them with these ones. The testing came out clean and had no issues, so perhaps it’s a possibility that I could update the PPCFastISel one, as well. Or, I can probably put up a separate NFC patch afterwards to update this?

[amyk]

Ping.

[amyk]

Ping.

[amyk]

Ping.

[nemanjai]

llvm/lib/Target/PowerPC/PPCCallingConv.cpp

24

Please note the section of the ABI document that describes this allocation algorithms (and then below, which part of the section talks about the specific aspect - such as allocating even GPRs for vectors, skipping odd ones, etc.).

40

Why does it not suffice for the rest of this function to be something simple like the following:

// For single/double precision, shadow a single GPR.
if (LocVT == MVT::f32 || LocVT == MVT::f64)
  State.AllocateReg(ELF64ArgGPRs);
else if (LocVT.is128BitVector() || (LocVT == MVT::f128)) {
  // For vector and __float128, shadow two even GPRs (skipping
  // the odd one if it is next in the allocation order).
  if ((State.AllocateReg(ELF64ArgGPRs) - PPC::X3) % 2 == 0)
    State.AllocateReg(ELF64ArgGPRs);
  State.AllocateReg(ELF64ArgGPRs);
  }
}

47–48

Is it possible for this loop to iterate more than once?

51

Please add a comment as to what happens with MVT::ppcf128. Does it get broken up into two MVT::f64's before here? Do we just ignore/skip it for now? Should it be an assert until it is implemented if it isn't already implemented?

[nemanjai]

In D137504#3968225, @amyk wrote:

@stefanp Thanks for the review and the questions!

Can we now get rid of CC_PPC64_ELF_FIS completely?

As I mentioned in one of my replies to your other comments, I did try to use this definition instead of the FastISel ones within PPCFastISel.cpp and there weren’t any issues.
It may be possible that we can get rid of CC_PPC64_ELF_FIS, although I’m not sure if we should do it within this patch. @nemanjai Do you have any thoughts on this?

I'd rather not change anything in FastISel for now. But feel free to add a TODO to remove it in the future if it is completely equivalent to the new one (although I am not convinced it is completely equivalent nor that it will remain so as we add functionality to it).

[amyk]

Address review comments from Nemanja to simplify the register allocation function and also to add documentation to parts of the code.

llvm/lib/Target/PowerPC/PPCCallingConv.cpp

40

Thank you for the suggestion Nemanja. I've looked into this and tweaked it slightly. This simplification should suffice.

47–48

I thought it was before, but realized that after I updated the patch after Stefan's comment, this should only run once. Thus, it would make sense to remove this loop.

51

I have added a comment to state that MVT::ppcf128 does indeed get broken up to two MVT::f64s here.

[stefanp]

Overall I think this patch looks great.

I've only added one comment. It relates to the way that a test case has changed when a struct is being passed in as a parameter.
I know that this is work in progress and it is quite possible that passing structs is not yet supported. If that's the case just add a comment (or TODO) into the test to show that the results are wrong and we know they are wrong and that they will be fixed at a later date.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

18258

I'm happy if this is a separate patch that comes after or even as a TODO in the code for us to look at later.

llvm/test/CodeGen/PowerPC/GlobalISel/irtranslator-args-lowering.ll

82

This is interesting because we are changing the way that a struct is being passed in registers.
Which of these set of liveins is correct?

My understanding of the ABI (and I could be wrong here so please read and make sure) is that non-homogeneous structs are passed as a block of memory. For example the i8 and float would be in R3 at the same time.
So, it might look something like this:

R3 -> i8, float
R4 -> i32, i32
R5 -> i32

If we look at it that way we should only be using R3, R4, R5.

Either way, I think it is important to look at this and figure out why it changes and what the ABI says.

[amyk]

llvm/test/CodeGen/PowerPC/GlobalISel/irtranslator-args-lowering.ll

82

I count be misunderstanding this as well but when reading the ABI initially, I understood it the same as you described in your comment where we would be utilizing r2, r4 and r5 for this particular struct.

Essentially, I thought that both the original and updated liveins is incorrect, just because this implementation is meant to handle simple cases of integers, floats and vectors within registers and doesn't fully support structs yet. I thought I had put a comment denoting this before but it turns out that I didn't, so thank you for pointing this out, Stefan.

I can definitely add the TODO here, and we can plan to add support for structs in a follow up patch at a later time. I also just wanted to check with @nemanjai if this is a reasonable approach for this patch.

[amyk]

Ping.

[amyk]

Ping.

[amyk]

Ping.

[nemanjai]

LGTM.

llvm/test/CodeGen/PowerPC/GlobalISel/irtranslator-args-lowering.ll

82

One easy way to resolve this is to compile something with current compilers that accesses the members from Stefan's example and see which register they're expected to be in.

Also, if we happen to do the wrong thing for GlobalISel for now for passing structs, I'm perfectly fine with marking it as a TODO to fix it later.

[amyk]

llvm/test/CodeGen/PowerPC/GlobalISel/irtranslator-args-lowering.ll

82

Sounds good. I have added a TODO when I committed the patch. The correct way appears to be what Stefan has outlined/what was discussed (R3, R4, R5).

llvm/lib/Target/PowerPC/PPCCallingConv.h

bool RetCC_PPC64_ELF_FIS(unsigned ValNo, MVT ValVT, MVT LocVT,
                          CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
                          CCState &State);
 bool RetCC_PPC_Cold(unsigned ValNo, MVT ValVT, MVT LocVT,
                     CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
                     CCState &State);
 bool CC_PPC32_SVR4(unsigned ValNo, MVT ValVT, MVT LocVT,
                    CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
                    CCState &State);
+bool CC_PPC64_ELF(unsigned ValNo, MVT ValVT, MVT LocVT,
+                  CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
+                  CCState &State);
 bool CC_PPC64_ELF_FIS(unsigned ValNo, MVT ValVT, MVT LocVT,
                       CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
                       CCState &State);
 bool CC_PPC32_SVR4_ByVal(unsigned ValNo, MVT ValVT, MVT LocVT,
                          CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
                          CCState &State);
 bool CC_PPC32_SVR4_VarArg(unsigned ValNo, MVT ValVT, MVT LocVT,
                           CCValAssign::LocInfo LocInfo,
                           ISD::ArgFlagsTy ArgFlags, CCState &State);
 
 } // End llvm namespace
 
 #endif
 

llvm/lib/Target/PowerPC/PPCCallingConv.cpp

-//===-- PPCCallingConv.h - --------------------------------------*- C++ -*-===//
+//===-- PPCCallingConv.cpp - ------------------------------------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #include "PPCRegisterInfo.h"
 #include "PPCCallingConv.h"
 #include "PPCSubtarget.h"
 #include "PPCCCState.h"
 using namespace llvm;
 
 inline bool CC_PPC_AnyReg_Error(unsigned &, MVT &, MVT &,
                                 CCValAssign::LocInfo &, ISD::ArgFlagsTy &,
                                 CCState &) {
   llvm_unreachable("The AnyReg calling convention is only supported by the " \
                    "stackmap and patchpoint intrinsics.");
   // gracefully fallback to PPC C calling convention on Release builds.
   return false;
 }
 
+// This function handles the shadowing of GPRs for fp and vector types,
+// and is a depiction of the algorithm described in the ELFv2 ABI,
+// Section 2.2.4.1: Parameter Passing Register Selection Algorithm.
+inline bool CC_PPC64_ELF_Shadow_GPR_Regs(unsigned &ValNo, MVT &ValVT,
+                                         MVT &LocVT,
+                                         CCValAssign::LocInfo &LocInfo,
+                                         ISD::ArgFlagsTy &ArgFlags,
+                                         CCState &State) {
+
+  // The 64-bit ELFv2 ABI-defined parameter passing general purpose registers.
+  static const MCPhysReg ELF64ArgGPRs[] = {PPC::X3, PPC::X4, PPC::X5, PPC::X6,
+                                           PPC::X7, PPC::X8, PPC::X9, PPC::X10};
+  const unsigned ELF64NumArgGPRs = std::size(ELF64ArgGPRs);
+
+  unsigned FirstUnallocGPR = State.getFirstUnallocated(ELF64ArgGPRs);
+  if (FirstUnallocGPR == ELF64NumArgGPRs)
+    return false;
+
+  // As described in 2.2.4.1 under the "float" section, shadow a single GPR
+  // for single/double precision. ppcf128 gets broken up into two doubles
+  // and will also shadow GPRs within this section.
+  if (LocVT == MVT::f32 || LocVT == MVT::f64)
+    State.AllocateReg(ELF64ArgGPRs);
+  else if (LocVT.is128BitVector() || (LocVT == MVT::f128)) {
+    // For vector and __float128 (which is represents the "vector" section
+    // in 2.2.4.1), shadow two even GPRs (skipping the odd one if it is next
+    // in the allocation order). To check if the GPR is even, the specific
+    // condition checks if the register allocated is odd, because the even
+    // physical registers are odd values.
+    if ((State.AllocateReg(ELF64ArgGPRs) - PPC::X3) % 2 == 1)
+      State.AllocateReg(ELF64ArgGPRs);
+    State.AllocateReg(ELF64ArgGPRs);
+  }
+  return false;
+}
+
 static bool CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
                                        CCValAssign::LocInfo &LocInfo,
                                        ISD::ArgFlagsTy &ArgFlags,
                                        CCState &State) {
   return true;
 }
 
 static bool CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,

llvm/lib/Target/PowerPC/PPCCallingConv.td

 //
 // This calling convention is currently only supported by the stackmap and
 // patchpoint intrinsics. All other uses will result in an assert on Debug
 // builds. On Release builds we fallback to the PPC C calling convention.
 def CC_PPC64_AnyReg : CallingConv<[
   CCCustom<"CC_PPC_AnyReg_Error">
 ]>;
 
-// Note that we don't currently have calling conventions for 64-bit
-// PowerPC, but handle all the complexities of the ABI in the lowering
-// logic.  FIXME: See if the logic can be simplified with use of CCs.
-// This may require some extensions to current table generation.
+// Calling Convention corresponding to the 64-bit PowerPC ELFv2 ABI.
+// This calling convention currently only handles integers, floats and
+// vectors within registers, as well as it handles the shadowing of GPRs
+// when floating point and vector arguments are used.
+// FIXME: This calling convention needs to be extended to handle all types and
+// complexities of the ABI.
+let Entry = 1 in
+def CC_PPC64_ELF : CallingConv<[
+  CCIfCC<"CallingConv::AnyReg", CCDelegateTo<CC_PPC64_AnyReg>>,
+
+  CCIfType<[i1],  CCPromoteToType<i64>>,
+  CCIfType<[i8],  CCPromoteToType<i64>>,
+  CCIfType<[i16], CCPromoteToType<i64>>,
+  CCIfType<[i32], CCPromoteToType<i64>>,
+  CCIfType<[i64], CCAssignToReg<[X3, X4, X5, X6, X7, X8, X9, X10]>>,
+
+  // Handle fp types and shadow the corresponding registers as necessary.
+  CCIfType<[f32, f64], CCIfNotVarArg<CCCustom<"CC_PPC64_ELF_Shadow_GPR_Regs">>>,
+  CCIfType<[f32, f64],
+           CCIfNotVarArg<CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8, F9, F10,
+                                        F11, F12, F13]>>>,
+
+  // f128 is handled through vector registers instead of fp registers.
+  CCIfType<[f128],
+           CCIfSubtarget<"hasAltivec()",
+           CCIfNotVarArg<CCCustom<"CC_PPC64_ELF_Shadow_GPR_Regs">>>>,
+  CCIfType<[f128],
+           CCIfSubtarget<"hasAltivec()",
+           CCIfNotVarArg<CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9, V10,
+                                        V11, V12, V13]>>>>,
+
+  // Handle support for vector types, and shadow GPRs as necessary.
+  CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64, v1i128],
+           CCIfSubtarget<"hasAltivec()",
+           CCIfNotVarArg<CCCustom<"CC_PPC64_ELF_Shadow_GPR_Regs">>>>,
+  CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64, v1i128],
+           CCIfSubtarget<"hasAltivec()",
+           CCIfNotVarArg<CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9, V10,
+                                        V11, V12, V13]>>>>,
+]>;
 
 // Simple calling convention for 64-bit ELF PowerPC fast isel.
 // Only handle ints and floats.  All ints are promoted to i64.
 // Vector types and quadword ints are not handled.
 let Entry = 1 in
 def CC_PPC64_ELF_FIS : CallingConv<[
   CCIfCC<"CallingConv::AnyReg", CCDelegateTo<CC_PPC64_AnyReg>>,
 

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

PPC::AddrMode PPCTargetLowering::SelectOptimalAddrMode(const SDNode *Parent,
   return Mode;
 }
 
 CCAssignFn *PPCTargetLowering::ccAssignFnForCall(CallingConv::ID CC,
                                                  bool Return,
                                                  bool IsVarArg) const {
   switch (CC) {
   case CallingConv::Cold:
-    return (Return ? RetCC_PPC_Cold : CC_PPC64_ELF_FIS);
+    return (Return ? RetCC_PPC_Cold : CC_PPC64_ELF);
   default:
-    return CC_PPC64_ELF_FIS;
+    return CC_PPC64_ELF;
   }
 }
 
 bool PPCTargetLowering::shouldInlineQuadwordAtomics() const {
   // TODO: 16-byte atomic type support for AIX is in progress; we should be able
   // to inline 16-byte atomic ops on AIX too in the future.
   return Subtarget.isPPC64() &&
          (EnableQuadwordAtomics || !Subtarget.getTargetTriple().isOSAIX()) &&

llvm/test/CodeGen/PowerPC/GlobalISel/irtranslator-args-lowering-fp128.ll

+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -global-isel \
+; RUN:     -verify-machineinstrs -stop-after=irtranslator < %s | FileCheck %s
+
+; Passing ppc_fp128 in registers (in fp registers as f64)
+define void @test_ppc_fp128_1(ppc_fp128 %a, ppc_fp128 %b, ppc_fp128 %c, ppc_fp128 %d, ppc_fp128 %e) {
+  ; CHECK-LABEL: name: test_ppc_fp128_1
+  ; CHECK: bb.1.entry:
+  ; CHECK-NEXT:   liveins: $f1, $f2, $f3, $f4, $f5, $f6, $f7, $f8, $f9, $f10
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(s64) = COPY $f2
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(s64) = COPY $f1
+  ; CHECK-NEXT:   [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY]](s64), [[COPY1]](s64)
+  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:_(s64) = COPY $f4
+  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:_(s64) = COPY $f3
+  ; CHECK-NEXT:   [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY2]](s64), [[COPY3]](s64)
+  ; CHECK-NEXT:   [[COPY4:%[0-9]+]]:_(s64) = COPY $f6
+  ; CHECK-NEXT:   [[COPY5:%[0-9]+]]:_(s64) = COPY $f5
+  ; CHECK-NEXT:   [[MV2:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY4]](s64), [[COPY5]](s64)
+  ; CHECK-NEXT:   [[COPY6:%[0-9]+]]:_(s64) = COPY $f8
+  ; CHECK-NEXT:   [[COPY7:%[0-9]+]]:_(s64) = COPY $f7
+  ; CHECK-NEXT:   [[MV3:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY6]](s64), [[COPY7]](s64)
+  ; CHECK-NEXT:   [[COPY8:%[0-9]+]]:_(s64) = COPY $f10
+  ; CHECK-NEXT:   [[COPY9:%[0-9]+]]:_(s64) = COPY $f9
+  ; CHECK-NEXT:   [[MV4:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY8]](s64), [[COPY9]](s64)
+  ; CHECK-NEXT:   BLR8 implicit $lr8, implicit $rm
+entry:
+  ret void
+}
+
+define void @test_ppc_fp128_2(i32 %a, i32 %b, ppc_fp128 %c, i32 %d) {
+  ; CHECK-LABEL: name: test_ppc_fp128_2
+  ; CHECK: bb.1.entry:
+  ; CHECK-NEXT:   liveins: $f1, $f2, $x3, $x4, $x7
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(s64) = COPY $x3
+  ; CHECK-NEXT:   [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(s64) = COPY $x4
+  ; CHECK-NEXT:   [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
+  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:_(s64) = COPY $f2
+  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:_(s64) = COPY $f1
+  ; CHECK-NEXT:   [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY2]](s64), [[COPY3]](s64)
+  ; CHECK-NEXT:   [[COPY4:%[0-9]+]]:_(s64) = COPY $x7
+  ; CHECK-NEXT:   [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY4]](s64)
+  ; CHECK-NEXT:   BLR8 implicit $lr8, implicit $rm
+entry:
+  ret void
+}
+
+define void @test_ppc_fp128_3(ppc_fp128 %a, i32 %b, ppc_fp128 %c, i32 %d, i32 %e) {
+  ; CHECK-LABEL: name: test_ppc_fp128_3
+  ; CHECK: bb.1.entry:
+  ; CHECK-NEXT:   liveins: $f1, $f2, $f3, $f4, $x5, $x8, $x9
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(s64) = COPY $f2
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(s64) = COPY $f1
+  ; CHECK-NEXT:   [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY]](s64), [[COPY1]](s64)
+  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:_(s64) = COPY $x5
+  ; CHECK-NEXT:   [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY2]](s64)
+  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:_(s64) = COPY $f4
+  ; CHECK-NEXT:   [[COPY4:%[0-9]+]]:_(s64) = COPY $f3
+  ; CHECK-NEXT:   [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY3]](s64), [[COPY4]](s64)
+  ; CHECK-NEXT:   [[COPY5:%[0-9]+]]:_(s64) = COPY $x8
+  ; CHECK-NEXT:   [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY5]](s64)
+  ; CHECK-NEXT:   [[COPY6:%[0-9]+]]:_(s64) = COPY $x9
+  ; CHECK-NEXT:   [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY6]](s64)
+  ; CHECK-NEXT:   BLR8 implicit $lr8, implicit $rm
+entry:
+  ret void
+}
+
+; Passing fp128 in registers (in vector registers)
+define void @test_fp128_1(fp128 %a, fp128 %b, fp128 %c, fp128 %d, fp128 %e) {
+  ; CHECK-LABEL: name: test_fp128_1
+  ; CHECK: bb.1.entry:
+  ; CHECK-NEXT:   liveins: $v2, $v3, $v4, $v5, $v6
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(s128) = COPY $v2
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(s128) = COPY $v3
+  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:_(s128) = COPY $v4
+  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:_(s128) = COPY $v5
+  ; CHECK-NEXT:   [[COPY4:%[0-9]+]]:_(s128) = COPY $v6
+  ; CHECK-NEXT:   BLR8 implicit $lr8, implicit $rm
+entry:
+  ret void
+}
+
+define void @test_fp128_2(i32 %a, i32 %b, fp128 %c, i32 %d) {
+  ; CHECK-LABEL: name: test_fp128_2
+  ; CHECK: bb.1.entry:
+  ; CHECK-NEXT:   liveins: $v2, $x3, $x4, $x7
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(s64) = COPY $x3
+  ; CHECK-NEXT:   [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(s64) = COPY $x4
+  ; CHECK-NEXT:   [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
+  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:_(s128) = COPY $v2
+  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:_(s64) = COPY $x7
+  ; CHECK-NEXT:   [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY3]](s64)
+  ; CHECK-NEXT:   BLR8 implicit $lr8, implicit $rm
+entry:
+  ret void
+}
+
+define void @test_fp128_3(fp128 %a, i32 %b, fp128 %c, i32 %d, i32 %e) {
+  ; CHECK-LABEL: name: test_fp128_3
+  ; CHECK: bb.1.entry:
+  ; CHECK-NEXT:   liveins: $v2, $v3, $x5, $x9, $x10
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(s128) = COPY $v2
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(s64) = COPY $x5
+  ; CHECK-NEXT:   [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
+  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:_(s128) = COPY $v3
+  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:_(s64) = COPY $x9
+  ; CHECK-NEXT:   [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY3]](s64)
+  ; CHECK-NEXT:   [[COPY4:%[0-9]+]]:_(s64) = COPY $x10
+  ; CHECK-NEXT:   [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY4]](s64)
+  ; CHECK-NEXT:   BLR8 implicit $lr8, implicit $rm
+entry:
+  ret void
+}
+

llvm/test/CodeGen/PowerPC/GlobalISel/irtranslator-args-lowering-mixed-types.ll

+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -global-isel \
+; RUN:     -verify-machineinstrs -stop-after=irtranslator < %s | FileCheck %s
+
+; Mixed parameter passing involving integers, floats, vectors (all in registers).
+define void @test_mixed_arg1(i32 %a, i32 %b, i32 %c, <4 x i32> %d) {
+  ; CHECK-LABEL: name: test_mixed_arg1
+  ; CHECK: bb.1.entry:
+  ; CHECK-NEXT:   liveins: $v2, $x3, $x4, $x5
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(s64) = COPY $x3
+  ; CHECK-NEXT:   [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(s64) = COPY $x4
+  ; CHECK-NEXT:   [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
+  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:_(s64) = COPY $x5
+  ; CHECK-NEXT:   [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY2]](s64)
+  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:_(<4 x s32>) = COPY $v2
+  ; CHECK-NEXT:   BLR8 implicit $lr8, implicit $rm
+entry:
+  ret void
+}
+
+define void @test_mixed_arg2(i32 %a, i32 %b, <4 x i32> %c, i32 %d) {
+  ; CHECK-LABEL: name: test_mixed_arg2
+  ; CHECK: bb.1.entry:
+  ; CHECK-NEXT:   liveins: $v2, $x3, $x4, $x7
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(s64) = COPY $x3
+  ; CHECK-NEXT:   [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(s64) = COPY $x4
+  ; CHECK-NEXT:   [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
+  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:_(<4 x s32>) = COPY $v2
+  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:_(s64) = COPY $x7
+  ; CHECK-NEXT:   [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY3]](s64)
+  ; CHECK-NEXT:   BLR8 implicit $lr8, implicit $rm
+entry:
+  ret void
+}
+
+define void @test_mixed_arg3(i32 %a, i32 %b, i32 %c, <4 x i32> %d, i32 %e) {
+  ; CHECK-LABEL: name: test_mixed_arg3
+  ; CHECK: bb.1.entry:
+  ; CHECK-NEXT:   liveins: $v2, $x3, $x4, $x5, $x9
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(s64) = COPY $x3
+  ; CHECK-NEXT:   [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(s64) = COPY $x4
+  ; CHECK-NEXT:   [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
+  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:_(s64) = COPY $x5
+  ; CHECK-NEXT:   [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY2]](s64)
+  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:_(<4 x s32>) = COPY $v2
+  ; CHECK-NEXT:   [[COPY4:%[0-9]+]]:_(s64) = COPY $x9
+  ; CHECK-NEXT:   [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[COPY4]](s64)
+  ; CHECK-NEXT:   BLR8 implicit $lr8, implicit $rm
+entry:
+  ret void
+}
+
+define void @test_mixed_arg4(<2 x double> %a, <4 x i32> %b, <4 x i32> %c, i32 %d, i64 %e, double %f) {
+  ; CHECK-LABEL: name: test_mixed_arg4
+  ; CHECK: bb.1.entry:
+  ; CHECK-NEXT:   liveins: $f1, $v2, $v3, $v4, $x9, $x10
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $v2
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $v3
+  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:_(<4 x s32>) = COPY $v4
+  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:_(s64) = COPY $x9
+  ; CHECK-NEXT:   [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY3]](s64)
+  ; CHECK-NEXT:   [[COPY4:%[0-9]+]]:_(s64) = COPY $x10
+  ; CHECK-NEXT:   [[COPY5:%[0-9]+]]:_(s64) = COPY $f1
+  ; CHECK-NEXT:   BLR8 implicit $lr8, implicit $rm
+entry:
+  ret void
+}
+
+define void @test_mixed_arg5(float %a, i32 %b, <2 x i64> %c, i64 %d, double %e, <4 x float> %f) {
+  ; CHECK-LABEL: name: test_mixed_arg5
+  ; CHECK: bb.1.entry:
+  ; CHECK-NEXT:   liveins: $f1, $f2, $v2, $v3, $x4, $x7
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY $f1
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(s64) = COPY $x4
+  ; CHECK-NEXT:   [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
+  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:_(<2 x s64>) = COPY $v2
+  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:_(s64) = COPY $x7
+  ; CHECK-NEXT:   [[COPY4:%[0-9]+]]:_(s64) = COPY $f2
+  ; CHECK-NEXT:   [[COPY5:%[0-9]+]]:_(<4 x s32>) = COPY $v3
+  ; CHECK-NEXT:   BLR8 implicit $lr8, implicit $rm
+entry:
+  ret void
+}
+
+define void @test_mixed_arg6(i64 %a, double %b, i32 %c, i32 %d, <2 x i64> %e, <4 x i32> %f, <4 x i32> %g, <4 x float> %h) {
+  ; CHECK-LABEL: name: test_mixed_arg6
+  ; CHECK: bb.1.entry:
+  ; CHECK-NEXT:   liveins: $f1, $v2, $v3, $v4, $v5, $x3, $x5, $x6
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(s64) = COPY $x3
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(s64) = COPY $f1
+  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:_(s64) = COPY $x5
+  ; CHECK-NEXT:   [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY2]](s64)
+  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:_(s64) = COPY $x6
+  ; CHECK-NEXT:   [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY3]](s64)
+  ; CHECK-NEXT:   [[COPY4:%[0-9]+]]:_(<2 x s64>) = COPY $v2
+  ; CHECK-NEXT:   [[COPY5:%[0-9]+]]:_(<4 x s32>) = COPY $v3
+  ; CHECK-NEXT:   [[COPY6:%[0-9]+]]:_(<4 x s32>) = COPY $v4
+  ; CHECK-NEXT:   [[COPY7:%[0-9]+]]:_(<4 x s32>) = COPY $v5
+  ; CHECK-NEXT:   BLR8 implicit $lr8, implicit $rm
+entry:
+  ret void
+}
+
+define void @test_mixed_arg7(i32 %a, float %b, i32 %c, float %d, <4 x float> %e, <4 x i32> %f) {
+  ; CHECK-LABEL: name: test_mixed_arg7
+  ; CHECK: bb.1.entry:
+  ; CHECK-NEXT:   liveins: $f1, $f2, $v2, $v3, $x3, $x5
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(s64) = COPY $x3
+  ; CHECK-NEXT:   [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(s32) = COPY $f1
+  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:_(s64) = COPY $x5
+  ; CHECK-NEXT:   [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY2]](s64)
+  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:_(s32) = COPY $f2
+  ; CHECK-NEXT:   [[COPY4:%[0-9]+]]:_(<4 x s32>) = COPY $v2
+  ; CHECK-NEXT:   [[COPY5:%[0-9]+]]:_(<4 x s32>) = COPY $v3
+  ; CHECK-NEXT:   BLR8 implicit $lr8, implicit $rm
+entry:
+  ret void
+}
+
+define void @test_mixed_arg8(<4 x i32> %a, float %b, i32 %c, i64 %d, <2 x double> %e, double %f) {
+  ; CHECK-LABEL: name: test_mixed_arg8
+  ; CHECK: bb.1.entry:
+  ; CHECK-NEXT:   liveins: $f1, $f2, $v2, $v3, $x6, $x7
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $v2
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(s32) = COPY $f1
+  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:_(s64) = COPY $x6
+  ; CHECK-NEXT:   [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY2]](s64)
+  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:_(s64) = COPY $x7
+  ; CHECK-NEXT:   [[COPY4:%[0-9]+]]:_(<2 x s64>) = COPY $v3
+  ; CHECK-NEXT:   [[COPY5:%[0-9]+]]:_(s64) = COPY $f2
+  ; CHECK-NEXT:   BLR8 implicit $lr8, implicit $rm
+entry:
+  ret void
+}
+
+define void @test_mixed_arg9(<4 x float> %a, i32 %b, i32 %c, <4 x i32> %d, i32 %e, double %f) {
+  ; CHECK-LABEL: name: test_mixed_arg9
+  ; CHECK: bb.1.entry:
+  ; CHECK-NEXT:   liveins: $f1, $v2, $v3, $x5, $x6, $x9
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $v2
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(s64) = COPY $x5
+  ; CHECK-NEXT:   [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
+  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:_(s64) = COPY $x6
+  ; CHECK-NEXT:   [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY2]](s64)
+  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:_(<4 x s32>) = COPY $v3
+  ; CHECK-NEXT:   [[COPY4:%[0-9]+]]:_(s64) = COPY $x9
+  ; CHECK-NEXT:   [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY4]](s64)
+  ; CHECK-NEXT:   [[COPY5:%[0-9]+]]:_(s64) = COPY $f1
+  ; CHECK-NEXT:   BLR8 implicit $lr8, implicit $rm
+entry:
+  ret void
+}
+
+define void @test_mixed_arg10(i32 %a, float %b, i64 %c, <2 x double> %d, <4 x float> %e, double %f) {
+  ; CHECK-LABEL: name: test_mixed_arg10
+  ; CHECK: bb.1.entry:
+  ; CHECK-NEXT:   liveins: $f1, $f2, $v2, $v3, $x3, $x5
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(s64) = COPY $x3
+  ; CHECK-NEXT:   [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(s32) = COPY $f1
+  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:_(s64) = COPY $x5
+  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:_(<2 x s64>) = COPY $v2
+  ; CHECK-NEXT:   [[COPY4:%[0-9]+]]:_(<4 x s32>) = COPY $v3
+  ; CHECK-NEXT:   [[COPY5:%[0-9]+]]:_(s64) = COPY $f2
+  ; CHECK-NEXT:   BLR8 implicit $lr8, implicit $rm
+entry:
+  ret void
+}
+
+define void @test_mixed_arg11(double %a, float %b, i32 %c, i64 %d, i32 %e, double %f, <4 x i32> %g) {
+  ; CHECK-LABEL: name: test_mixed_arg11
+  ; CHECK: bb.1.entry:
+  ; CHECK-NEXT:   liveins: $f1, $f2, $f3, $v2, $x5, $x6, $x7
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(s64) = COPY $f1
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(s32) = COPY $f2
+  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:_(s64) = COPY $x5
+  ; CHECK-NEXT:   [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY2]](s64)
+  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:_(s64) = COPY $x6
+  ; CHECK-NEXT:   [[COPY4:%[0-9]+]]:_(s64) = COPY $x7
+  ; CHECK-NEXT:   [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY4]](s64)
+  ; CHECK-NEXT:   [[COPY5:%[0-9]+]]:_(s64) = COPY $f3
+  ; CHECK-NEXT:   [[COPY6:%[0-9]+]]:_(<4 x s32>) = COPY $v2
+  ; CHECK-NEXT:   BLR8 implicit $lr8, implicit $rm
+entry:
+  ret void
+}
+
+define void @test_mixed_arg12(<2 x double> %a, <4 x i32> %b, i32 %c, i32 %d, i64 %e, float %f) {
+  ; CHECK-LABEL: name: test_mixed_arg12
+  ; CHECK: bb.1.entry:
+  ; CHECK-NEXT:   liveins: $f1, $v2, $v3, $x7, $x8, $x9
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $v2
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $v3
+  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:_(s64) = COPY $x7
+  ; CHECK-NEXT:   [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY2]](s64)
+  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:_(s64) = COPY $x8
+  ; CHECK-NEXT:   [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY3]](s64)
+  ; CHECK-NEXT:   [[COPY4:%[0-9]+]]:_(s64) = COPY $x9
+  ; CHECK-NEXT:   [[COPY5:%[0-9]+]]:_(s32) = COPY $f1
+  ; CHECK-NEXT:   BLR8 implicit $lr8, implicit $rm
+entry:
+  ret void
+}
+
+define void @test_mixed_arg13(i8 %a, <2 x double> %b, i64 %c, <4 x i32> %d, double %e) {
+  ; CHECK-LABEL: name: test_mixed_arg13
+  ; CHECK: bb.1.entry:
+  ; CHECK-NEXT:   liveins: $f1, $v2, $v3, $x3, $x7
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(s64) = COPY $x3
+  ; CHECK-NEXT:   [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s64)
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $v2
+  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:_(s64) = COPY $x7
+  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:_(<4 x s32>) = COPY $v3
+  ; CHECK-NEXT:   [[COPY4:%[0-9]+]]:_(s64) = COPY $f1
+  ; CHECK-NEXT:   BLR8 implicit $lr8, implicit $rm
+entry:
+  ret void
+}

llvm/test/CodeGen/PowerPC/GlobalISel/irtranslator-args-lowering-scalar.ll

+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -global-isel \
+; RUN:     -verify-machineinstrs -stop-after=irtranslator < %s | FileCheck %s
+
+; Pass up to eight integer arguments in registers.
+define void @test_scalar1(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 %h) {
+  ; CHECK-LABEL: name: test_scalar1
+  ; CHECK: bb.1.entry:
+  ; CHECK-NEXT:   liveins: $x3, $x4, $x5, $x6, $x7, $x8, $x9, $x10
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(s64) = COPY $x3
+  ; CHECK-NEXT:   [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(s64) = COPY $x4
+  ; CHECK-NEXT:   [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
+  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:_(s64) = COPY $x5
+  ; CHECK-NEXT:   [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY2]](s64)
+  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:_(s64) = COPY $x6
+  ; CHECK-NEXT:   [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[COPY3]](s64)
+  ; CHECK-NEXT:   [[COPY4:%[0-9]+]]:_(s64) = COPY $x7
+  ; CHECK-NEXT:   [[TRUNC4:%[0-9]+]]:_(s32) = G_TRUNC [[COPY4]](s64)
+  ; CHECK-NEXT:   [[COPY5:%[0-9]+]]:_(s64) = COPY $x8
+  ; CHECK-NEXT:   [[TRUNC5:%[0-9]+]]:_(s32) = G_TRUNC [[COPY5]](s64)
+  ; CHECK-NEXT:   [[COPY6:%[0-9]+]]:_(s64) = COPY $x9
+  ; CHECK-NEXT:   [[TRUNC6:%[0-9]+]]:_(s32) = G_TRUNC [[COPY6]](s64)
+  ; CHECK-NEXT:   [[COPY7:%[0-9]+]]:_(s64) = COPY $x10
+  ; CHECK-NEXT:   [[TRUNC7:%[0-9]+]]:_(s32) = G_TRUNC [[COPY7]](s64)
+  ; CHECK-NEXT:   BLR8 implicit $lr8, implicit $rm
+entry:
+  ret void
+}
+
+define void @test_scalar2(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e, i64 %f, i64 %g, i64 %h) {
+  ; CHECK-LABEL: name: test_scalar2
+  ; CHECK: bb.1.entry:
+  ; CHECK-NEXT:   liveins: $x3, $x4, $x5, $x6, $x7, $x8, $x9, $x10
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(s64) = COPY $x3
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(s64) = COPY $x4
+  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:_(s64) = COPY $x5
+  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:_(s64) = COPY $x6
+  ; CHECK-NEXT:   [[COPY4:%[0-9]+]]:_(s64) = COPY $x7
+  ; CHECK-NEXT:   [[COPY5:%[0-9]+]]:_(s64) = COPY $x8
+  ; CHECK-NEXT:   [[COPY6:%[0-9]+]]:_(s64) = COPY $x9
+  ; CHECK-NEXT:   [[COPY7:%[0-9]+]]:_(s64) = COPY $x10
+  ; CHECK-NEXT:   BLR8 implicit $lr8, implicit $rm
+entry:
+  ret void
+}
+
+define void @test_scalar3(i8 %a, i8 %b, i8 %c, i8 %d, i8 %e, i8 %f, i8 %g, i8 %h) {
+  ; CHECK-LABEL: name: test_scalar3
+  ; CHECK: bb.1.entry:
+  ; CHECK-NEXT:   liveins: $x3, $x4, $x5, $x6, $x7, $x8, $x9, $x10
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(s64) = COPY $x3
+  ; CHECK-NEXT:   [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s64)
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(s64) = COPY $x4
+  ; CHECK-NEXT:   [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s64)
+  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:_(s64) = COPY $x5
+  ; CHECK-NEXT:   [[TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[COPY2]](s64)
+  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:_(s64) = COPY $x6
+  ; CHECK-NEXT:   [[TRUNC3:%[0-9]+]]:_(s8) = G_TRUNC [[COPY3]](s64)
+  ; CHECK-NEXT:   [[COPY4:%[0-9]+]]:_(s64) = COPY $x7
+  ; CHECK-NEXT:   [[TRUNC4:%[0-9]+]]:_(s8) = G_TRUNC [[COPY4]](s64)
+  ; CHECK-NEXT:   [[COPY5:%[0-9]+]]:_(s64) = COPY $x8
+  ; CHECK-NEXT:   [[TRUNC5:%[0-9]+]]:_(s8) = G_TRUNC [[COPY5]](s64)
+  ; CHECK-NEXT:   [[COPY6:%[0-9]+]]:_(s64) = COPY $x9
+  ; CHECK-NEXT:   [[TRUNC6:%[0-9]+]]:_(s8) = G_TRUNC [[COPY6]](s64)
+  ; CHECK-NEXT:   [[COPY7:%[0-9]+]]:_(s64) = COPY $x10
+  ; CHECK-NEXT:   [[TRUNC7:%[0-9]+]]:_(s8) = G_TRUNC [[COPY7]](s64)
+  ; CHECK-NEXT:   BLR8 implicit $lr8, implicit $rm
+entry:
+  ret void
+}
+
+define void @test_scalar4(i16 %a, i16 %b, i16 %c, i16 %d, i16 %e, i16 %f, i16 %g, i16 %h) {
+  ; CHECK-LABEL: name: test_scalar4
+  ; CHECK: bb.1.entry:
+  ; CHECK-NEXT:   liveins: $x3, $x4, $x5, $x6, $x7, $x8, $x9, $x10
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(s64) = COPY $x3
+  ; CHECK-NEXT:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s64)
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(s64) = COPY $x4
+  ; CHECK-NEXT:   [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s64)
+  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:_(s64) = COPY $x5
+  ; CHECK-NEXT:   [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY2]](s64)
+  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:_(s64) = COPY $x6
+  ; CHECK-NEXT:   [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[COPY3]](s64)
+  ; CHECK-NEXT:   [[COPY4:%[0-9]+]]:_(s64) = COPY $x7
+  ; CHECK-NEXT:   [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[COPY4]](s64)
+  ; CHECK-NEXT:   [[COPY5:%[0-9]+]]:_(s64) = COPY $x8
+  ; CHECK-NEXT:   [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[COPY5]](s64)
+  ; CHECK-NEXT:   [[COPY6:%[0-9]+]]:_(s64) = COPY $x9
+  ; CHECK-NEXT:   [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[COPY6]](s64)
+  ; CHECK-NEXT:   [[COPY7:%[0-9]+]]:_(s64) = COPY $x10
+  ; CHECK-NEXT:   [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[COPY7]](s64)
+  ; CHECK-NEXT:   BLR8 implicit $lr8, implicit $rm
+entry:
+  ret void
+}
+
+define void @test_scalar5(i128 %a, i128 %b, i128 %c, i128 %d) {
+  ; CHECK-LABEL: name: test_scalar5
+  ; CHECK: bb.1.entry:
+  ; CHECK-NEXT:   liveins: $x3, $x4, $x5, $x6, $x7, $x8, $x9, $x10
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(s64) = COPY $x3
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(s64) = COPY $x4
+  ; CHECK-NEXT:   [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY]](s64), [[COPY1]](s64)
+  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:_(s64) = COPY $x5
+  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:_(s64) = COPY $x6
+  ; CHECK-NEXT:   [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY2]](s64), [[COPY3]](s64)
+  ; CHECK-NEXT:   [[COPY4:%[0-9]+]]:_(s64) = COPY $x7
+  ; CHECK-NEXT:   [[COPY5:%[0-9]+]]:_(s64) = COPY $x8
+  ; CHECK-NEXT:   [[MV2:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY4]](s64), [[COPY5]](s64)
+  ; CHECK-NEXT:   [[COPY6:%[0-9]+]]:_(s64) = COPY $x9
+  ; CHECK-NEXT:   [[COPY7:%[0-9]+]]:_(s64) = COPY $x10
+  ; CHECK-NEXT:   [[MV3:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY6]](s64), [[COPY7]](s64)
+  ; CHECK-NEXT:   BLR8 implicit $lr8, implicit $rm
+entry:
+  ret void
+}
+
+; Pass up to thirteen fp arguments in registers.
+define void @test_scalar6(float %a, float %b, float %c, float %d, float %e, float %f, float %g, float %h, float %i, float %j, float %k, float %l, float %m) {
+  ; CHECK-LABEL: name: test_scalar6
+  ; CHECK: bb.1.entry:
+  ; CHECK-NEXT:   liveins: $f1, $f2, $f3, $f4, $f5, $f6, $f7, $f8, $f9, $f10, $f11, $f12, $f13
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY $f1
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(s32) = COPY $f2
+  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:_(s32) = COPY $f3
+  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:_(s32) = COPY $f4
+  ; CHECK-NEXT:   [[COPY4:%[0-9]+]]:_(s32) = COPY $f5
+  ; CHECK-NEXT:   [[COPY5:%[0-9]+]]:_(s32) = COPY $f6
+  ; CHECK-NEXT:   [[COPY6:%[0-9]+]]:_(s32) = COPY $f7
+  ; CHECK-NEXT:   [[COPY7:%[0-9]+]]:_(s32) = COPY $f8
+  ; CHECK-NEXT:   [[COPY8:%[0-9]+]]:_(s32) = COPY $f9
+  ; CHECK-NEXT:   [[COPY9:%[0-9]+]]:_(s32) = COPY $f10
+  ; CHECK-NEXT:   [[COPY10:%[0-9]+]]:_(s32) = COPY $f11
+  ; CHECK-NEXT:   [[COPY11:%[0-9]+]]:_(s32) = COPY $f12
+  ; CHECK-NEXT:   [[COPY12:%[0-9]+]]:_(s32) = COPY $f13
+  ; CHECK-NEXT:   BLR8 implicit $lr8, implicit $rm
+entry:
+  ret void
+}
+
+define void @test_scalar7(double %a, double %b, double %c, double %d, double %e, double %f, double %g, double %h, double %i, double %j, double %k, double %l, double %m) {
+  ; CHECK-LABEL: name: test_scalar7
+  ; CHECK: bb.1.entry:
+  ; CHECK-NEXT:   liveins: $f1, $f2, $f3, $f4, $f5, $f6, $f7, $f8, $f9, $f10, $f11, $f12, $f13
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(s64) = COPY $f1
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(s64) = COPY $f2
+  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:_(s64) = COPY $f3
+  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:_(s64) = COPY $f4
+  ; CHECK-NEXT:   [[COPY4:%[0-9]+]]:_(s64) = COPY $f5
+  ; CHECK-NEXT:   [[COPY5:%[0-9]+]]:_(s64) = COPY $f6
+  ; CHECK-NEXT:   [[COPY6:%[0-9]+]]:_(s64) = COPY $f7
+  ; CHECK-NEXT:   [[COPY7:%[0-9]+]]:_(s64) = COPY $f8
+  ; CHECK-NEXT:   [[COPY8:%[0-9]+]]:_(s64) = COPY $f9
+  ; CHECK-NEXT:   [[COPY9:%[0-9]+]]:_(s64) = COPY $f10
+  ; CHECK-NEXT:   [[COPY10:%[0-9]+]]:_(s64) = COPY $f11
+  ; CHECK-NEXT:   [[COPY11:%[0-9]+]]:_(s64) = COPY $f12
+  ; CHECK-NEXT:   [[COPY12:%[0-9]+]]:_(s64) = COPY $f13
+  ; CHECK-NEXT:   BLR8 implicit $lr8, implicit $rm
+entry:
+  ret void
+}
+

llvm/test/CodeGen/PowerPC/GlobalISel/irtranslator-args-lowering-vectors.ll

+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -global-isel \
+; RUN:     -verify-machineinstrs -stop-after=irtranslator < %s | FileCheck %s
+
+; Pass up to twelve vector arguments in registers.
+define void @test_vec1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d, <4 x i32> %e, <4 x i32> %f, <4 x i32> %g, <4 x i32> %h, <4 x i32> %i, <4 x i32> %j, <4 x i32> %k, <4 x i32> %l) {
+  ; CHECK-LABEL: name: test_vec1
+  ; CHECK: bb.1.entry:
+  ; CHECK-NEXT:   liveins: $v2, $v3, $v4, $v5, $v6, $v7, $v8, $v9, $v10, $v11, $v12, $v13
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $v2
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $v3
+  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:_(<4 x s32>) = COPY $v4
+  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:_(<4 x s32>) = COPY $v5
+  ; CHECK-NEXT:   [[COPY4:%[0-9]+]]:_(<4 x s32>) = COPY $v6
+  ; CHECK-NEXT:   [[COPY5:%[0-9]+]]:_(<4 x s32>) = COPY $v7
+  ; CHECK-NEXT:   [[COPY6:%[0-9]+]]:_(<4 x s32>) = COPY $v8
+  ; CHECK-NEXT:   [[COPY7:%[0-9]+]]:_(<4 x s32>) = COPY $v9
+  ; CHECK-NEXT:   [[COPY8:%[0-9]+]]:_(<4 x s32>) = COPY $v10
+  ; CHECK-NEXT:   [[COPY9:%[0-9]+]]:_(<4 x s32>) = COPY $v11
+  ; CHECK-NEXT:   [[COPY10:%[0-9]+]]:_(<4 x s32>) = COPY $v12
+  ; CHECK-NEXT:   [[COPY11:%[0-9]+]]:_(<4 x s32>) = COPY $v13
+  ; CHECK-NEXT:   BLR8 implicit $lr8, implicit $rm
+entry:
+  ret void
+}
+
+define void @test_vec2(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c, <2 x i64> %d, <2 x i64> %e, <2 x i64> %f, <2 x i64> %g, <2 x i64> %h, <2 x i64> %i, <2 x i64> %j, <2 x i64> %k, <2 x i64> %l) {
+  ; CHECK-LABEL: name: test_vec2
+  ; CHECK: bb.1.entry:
+  ; CHECK-NEXT:   liveins: $v2, $v3, $v4, $v5, $v6, $v7, $v8, $v9, $v10, $v11, $v12, $v13
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $v2
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $v3
+  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:_(<2 x s64>) = COPY $v4
+  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:_(<2 x s64>) = COPY $v5
+  ; CHECK-NEXT:   [[COPY4:%[0-9]+]]:_(<2 x s64>) = COPY $v6
+  ; CHECK-NEXT:   [[COPY5:%[0-9]+]]:_(<2 x s64>) = COPY $v7
+  ; CHECK-NEXT:   [[COPY6:%[0-9]+]]:_(<2 x s64>) = COPY $v8
+  ; CHECK-NEXT:   [[COPY7:%[0-9]+]]:_(<2 x s64>) = COPY $v9
+  ; CHECK-NEXT:   [[COPY8:%[0-9]+]]:_(<2 x s64>) = COPY $v10
+  ; CHECK-NEXT:   [[COPY9:%[0-9]+]]:_(<2 x s64>) = COPY $v11
+  ; CHECK-NEXT:   [[COPY10:%[0-9]+]]:_(<2 x s64>) = COPY $v12
+  ; CHECK-NEXT:   [[COPY11:%[0-9]+]]:_(<2 x s64>) = COPY $v13
+  ; CHECK-NEXT:   BLR8 implicit $lr8, implicit $rm
+entry:
+  ret void
+}
+
+define void @test_vec3(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c, <8 x i16> %d, <8 x i16> %e, <8 x i16> %f, <8 x i16> %g, <8 x i16> %h, <8 x i16> %i, <8 x i16> %j, <8 x i16> %k, <8 x i16> %l) {
+  ; CHECK-LABEL: name: test_vec3
+  ; CHECK: bb.1.entry:
+  ; CHECK-NEXT:   liveins: $v2, $v3, $v4, $v5, $v6, $v7, $v8, $v9, $v10, $v11, $v12, $v13
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $v2
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $v3
+  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:_(<8 x s16>) = COPY $v4
+  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:_(<8 x s16>) = COPY $v5
+  ; CHECK-NEXT:   [[COPY4:%[0-9]+]]:_(<8 x s16>) = COPY $v6
+  ; CHECK-NEXT:   [[COPY5:%[0-9]+]]:_(<8 x s16>) = COPY $v7
+  ; CHECK-NEXT:   [[COPY6:%[0-9]+]]:_(<8 x s16>) = COPY $v8
+  ; CHECK-NEXT:   [[COPY7:%[0-9]+]]:_(<8 x s16>) = COPY $v9
+  ; CHECK-NEXT:   [[COPY8:%[0-9]+]]:_(<8 x s16>) = COPY $v10
+  ; CHECK-NEXT:   [[COPY9:%[0-9]+]]:_(<8 x s16>) = COPY $v11
+  ; CHECK-NEXT:   [[COPY10:%[0-9]+]]:_(<8 x s16>) = COPY $v12
+  ; CHECK-NEXT:   [[COPY11:%[0-9]+]]:_(<8 x s16>) = COPY $v13
+  ; CHECK-NEXT:   BLR8 implicit $lr8, implicit $rm
+entry:
+  ret void
+}
+
+define void @test_vec4(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c, <16 x i8> %d, <16 x i8> %e, <16 x i8> %f, <16 x i8> %g, <16 x i8> %h, <16 x i8> %i, <16 x i8> %j, <16 x i8> %k, <16 x i8> %l) {
+  ; CHECK-LABEL: name: test_vec4
+  ; CHECK: bb.1.entry:
+  ; CHECK-NEXT:   liveins: $v2, $v3, $v4, $v5, $v6, $v7, $v8, $v9, $v10, $v11, $v12, $v13
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $v2
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $v3
+  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:_(<16 x s8>) = COPY $v4
+  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:_(<16 x s8>) = COPY $v5
+  ; CHECK-NEXT:   [[COPY4:%[0-9]+]]:_(<16 x s8>) = COPY $v6
+  ; CHECK-NEXT:   [[COPY5:%[0-9]+]]:_(<16 x s8>) = COPY $v7
+  ; CHECK-NEXT:   [[COPY6:%[0-9]+]]:_(<16 x s8>) = COPY $v8
+  ; CHECK-NEXT:   [[COPY7:%[0-9]+]]:_(<16 x s8>) = COPY $v9
+  ; CHECK-NEXT:   [[COPY8:%[0-9]+]]:_(<16 x s8>) = COPY $v10
+  ; CHECK-NEXT:   [[COPY9:%[0-9]+]]:_(<16 x s8>) = COPY $v11
+  ; CHECK-NEXT:   [[COPY10:%[0-9]+]]:_(<16 x s8>) = COPY $v12
+  ; CHECK-NEXT:   [[COPY11:%[0-9]+]]:_(<16 x s8>) = COPY $v13
+  ; CHECK-NEXT:   BLR8 implicit $lr8, implicit $rm
+entry:
+  ret void
+}
+
+define void @test_vec5(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d, <4 x float> %e, <4 x float> %f, <4 x float> %g, <4 x float> %h, <4 x float> %i, <4 x float> %j, <4 x float> %k, <4 x float> %l) {
+  ; CHECK-LABEL: name: test_vec5
+  ; CHECK: bb.1.entry:
+  ; CHECK-NEXT:   liveins: $v2, $v3, $v4, $v5, $v6, $v7, $v8, $v9, $v10, $v11, $v12, $v13
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $v2
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $v3
+  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:_(<4 x s32>) = COPY $v4
+  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:_(<4 x s32>) = COPY $v5
+  ; CHECK-NEXT:   [[COPY4:%[0-9]+]]:_(<4 x s32>) = COPY $v6
+  ; CHECK-NEXT:   [[COPY5:%[0-9]+]]:_(<4 x s32>) = COPY $v7
+  ; CHECK-NEXT:   [[COPY6:%[0-9]+]]:_(<4 x s32>) = COPY $v8
+  ; CHECK-NEXT:   [[COPY7:%[0-9]+]]:_(<4 x s32>) = COPY $v9
+  ; CHECK-NEXT:   [[COPY8:%[0-9]+]]:_(<4 x s32>) = COPY $v10
+  ; CHECK-NEXT:   [[COPY9:%[0-9]+]]:_(<4 x s32>) = COPY $v11
+  ; CHECK-NEXT:   [[COPY10:%[0-9]+]]:_(<4 x s32>) = COPY $v12
+  ; CHECK-NEXT:   [[COPY11:%[0-9]+]]:_(<4 x s32>) = COPY $v13
+  ; CHECK-NEXT:   BLR8 implicit $lr8, implicit $rm
+entry:
+  ret void
+}
+
+define void @test_vec6(<2 x double> %a, <2 x double> %b, <2 x double> %c, <2 x double> %d, <2 x double> %e, <2 x double> %f, <2 x double> %g, <2 x double> %h, <2 x double> %i, <2 x double> %j, <2 x double> %k, <2 x double> %l) {
+  ; CHECK-LABEL: name: test_vec6
+  ; CHECK: bb.1.entry:
+  ; CHECK-NEXT:   liveins: $v2, $v3, $v4, $v5, $v6, $v7, $v8, $v9, $v10, $v11, $v12, $v13
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $v2
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $v3
+  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:_(<2 x s64>) = COPY $v4
+  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:_(<2 x s64>) = COPY $v5
+  ; CHECK-NEXT:   [[COPY4:%[0-9]+]]:_(<2 x s64>) = COPY $v6
+  ; CHECK-NEXT:   [[COPY5:%[0-9]+]]:_(<2 x s64>) = COPY $v7
+  ; CHECK-NEXT:   [[COPY6:%[0-9]+]]:_(<2 x s64>) = COPY $v8
+  ; CHECK-NEXT:   [[COPY7:%[0-9]+]]:_(<2 x s64>) = COPY $v9
+  ; CHECK-NEXT:   [[COPY8:%[0-9]+]]:_(<2 x s64>) = COPY $v10
+  ; CHECK-NEXT:   [[COPY9:%[0-9]+]]:_(<2 x s64>) = COPY $v11
+  ; CHECK-NEXT:   [[COPY10:%[0-9]+]]:_(<2 x s64>) = COPY $v12
+  ; CHECK-NEXT:   [[COPY11:%[0-9]+]]:_(<2 x s64>) = COPY $v13
+  ; CHECK-NEXT:   BLR8 implicit $lr8, implicit $rm
+entry:
+  ret void
+}
+
+define void @test_vec7(<1 x i128> %a, <1 x i128> %b, <1 x i128> %c, <1 x i128> %d, <1 x i128> %e, <1 x i128> %f, <1 x i128> %g, <1 x i128> %h, <1 x i128> %i, <1 x i128> %j, <1 x i128> %k, <1 x i128> %l) {
+  ; CHECK-LABEL: name: test_vec7
+  ; CHECK: bb.1.entry:
+  ; CHECK-NEXT:   liveins: $v2, $v3, $v4, $v5, $v6, $v7, $v8, $v9, $v10, $v11, $v12, $v13
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(s128) = COPY $v2
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(s128) = COPY $v3
+  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:_(s128) = COPY $v4
+  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:_(s128) = COPY $v5
+  ; CHECK-NEXT:   [[COPY4:%[0-9]+]]:_(s128) = COPY $v6
+  ; CHECK-NEXT:   [[COPY5:%[0-9]+]]:_(s128) = COPY $v7
+  ; CHECK-NEXT:   [[COPY6:%[0-9]+]]:_(s128) = COPY $v8
+  ; CHECK-NEXT:   [[COPY7:%[0-9]+]]:_(s128) = COPY $v9
+  ; CHECK-NEXT:   [[COPY8:%[0-9]+]]:_(s128) = COPY $v10
+  ; CHECK-NEXT:   [[COPY9:%[0-9]+]]:_(s128) = COPY $v11
+  ; CHECK-NEXT:   [[COPY10:%[0-9]+]]:_(s128) = COPY $v12
+  ; CHECK-NEXT:   [[COPY11:%[0-9]+]]:_(s128) = COPY $v13
+  ; CHECK-NEXT:   BLR8 implicit $lr8, implicit $rm
+entry:
+  ret void
+}
+

llvm/test/CodeGen/PowerPC/GlobalISel/irtranslator-args-lowering.ll

define void @foo_pt(ptr %x) {
   ; CHECK-LABEL: name: foo_pt
   ; CHECK: bb.1 (%ir-block.0):
   ; CHECK:   liveins: $x3
   ; CHECK:   [[COPY:%[0-9]+]]:_(p0) = COPY $x3
   ; CHECK:   BLR8 implicit $lr8, implicit $rm
   ret void
 }
 
+; TODO: The correct registers used to pass struct arguments in this example
+; are R3, R4 and R5. Currently, the calling convention used for GlobalISel
+; does not handle passing structs and will need to implemented at a later time.
 define dso_local void @foo_struct(%struct.A %a) #0 {
   ; CHECK-LABEL: name: foo_struct
   ; CHECK: bb.1.entry:
-  ; CHECK:   liveins: $f1, $x3, $x4, $x5, $x6
+  ; CHECK:   liveins: $f1, $x3, $x5, $x6, $x7
   ; CHECK:   [[COPY:%[0-9]+]]:_(s64) = COPY $x3
   ; CHECK:   [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s64)
   ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $f1
-  ; CHECK:   [[COPY2:%[0-9]+]]:_(s64) = COPY $x4
+  ; CHECK:   [[COPY2:%[0-9]+]]:_(s64) = COPY $x5
   ; CHECK:   [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY2]](s64)
-  ; CHECK:   [[COPY3:%[0-9]+]]:_(s64) = COPY $x5
+  ; CHECK:   [[COPY3:%[0-9]+]]:_(s64) = COPY $x6
   ; CHECK:   [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[COPY3]](s64)
-  ; CHECK:   [[COPY4:%[0-9]+]]:_(s64) = COPY $x6
+  ; CHECK:   [[COPY4:%[0-9]+]]:_(s64) = COPY $x7
   ; CHECK:   [[TRUNC4:%[0-9]+]]:_(s32) = G_TRUNC [[COPY4]](s64)
   ; CHECK:   BLR8 implicit $lr8, implicit $rm
 entry:
   ret void
 }
 
 define void @foo_int(ptr %x) {
   ; CHECK-LABEL: name: foo_int