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Differential D137423

[PowerPC] make expensive mflr be away from its user in the function prologue
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Authored by shchenz on Nov 4 2022, 7:16 AM.

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Reviewers
RolandF
nemanjai
Group Reviewers
Restricted Project
Commits
rGeb7d16ea2564: [PowerPC] make expensive mflr be away from its user in the function prologue
Summary

mflr is kind of expensive on Power version smaller than 10, so we should schedule the store for the mflr's def away from mflr.

In epilogue, the expensive mtlr has no user for its def, so it doesn't matter that the load and the mtlr are back-to-back.

Diff Detail

Event Timeline

shchenz created this revision.Nov 4 2022, 7:16 AM
Herald added a project: Restricted Project. · View Herald TranscriptNov 4 2022, 7:16 AM
Herald added subscribers: kbarton, hiraditya. · View Herald Transcript
shchenz requested review of this revision.Nov 4 2022, 7:16 AM
Herald added a project: Restricted Project. · View Herald TranscriptNov 4 2022, 7:16 AM
Herald added a subscriber: llvm-commits. · View Herald Transcript
shchenz added a subscriber: power-llvm-team.Nov 4 2022, 7:16 AM
shchenz edited the summary of this revision. (Show Details)Nov 4 2022, 7:25 AM
Harbormaster completed remote builds in B196138: Diff 473225.Nov 4 2022, 8:05 AM
RolandF added inline comments.Nov 7 2022, 7:59 AM
llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
621

The cost of an mflr is a characteristic of an implementation, not of the architecture. A future processor might have a slow mflr. I think a new subtarget feature is needed for this.

shchenz updated this revision to Diff 473874.Nov 7 2022, 10:03 PM
shchenz retitled this revision from [PowerPC][WIP] make expensive mflr be awfy from its user in the function prologue to [PowerPC] make expensive mflr be away from its user in the function prologue.

fix all LIT failures

Herald added subscribers: arphaman, qcolombet. · View Herald TranscriptNov 7 2022, 10:03 PM
shchenz updated this revision to Diff 473881.Nov 7 2022, 10:43 PM
shchenz mentioned this in D137612: [PowerPC] add a new subtarget feature FastMFLR.

rebase for D137612

shchenz added a parent revision: D137612: [PowerPC] add a new subtarget feature FastMFLR.Nov 7 2022, 10:47 PM
shchenz marked an inline comment as done.
shchenz added inline comments.
llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
621

I added a new patch https://reviews.llvm.org/D137612 to add the subtarget feature. Seems for P10, the latency for mflr is only 2 cycles, so I only set the new feature for P10.

Harbormaster completed remote builds in B196641: Diff 473881.Nov 7 2022, 11:03 PM
shchenz updated this revision to Diff 474124.Nov 8 2022, 5:33 PM
shchenz marked an inline comment as done.
Harbormaster completed remote builds in B196800: Diff 474124.Nov 8 2022, 6:22 PM
shchenz mentioned this in rG454758ab6931: [PowerPC] add a new subtarget feature fastMFLR.Nov 9 2022, 9:25 PM
shchenz edited the summary of this revision. (Show Details)Nov 10 2022, 6:30 PM
RolandF accepted this revision.Nov 14 2022, 10:05 AM

LGTM

This revision is now accepted and ready to land.Nov 14 2022, 10:05 AM
This revision was landed with ongoing or failed builds.Nov 14 2022, 6:14 PM
Closed by commit rGeb7d16ea2564: [PowerPC] make expensive mflr be away from its user in the function prologue (authored by shchenz). · Explain Why
This revision was automatically updated to reflect the committed changes.
shchenz added a commit: rGeb7d16ea2564: [PowerPC] make expensive mflr be away from its user in the function prologue.

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Diff 475324

llvm/lib/Target/PowerPC/PPCFrameLowering.cpp

Show First 20 Lines • Show All 610 Lines • ▼ Show 20 Linesvoid PPCFrameLowering::emitPrologue(MachineFunction &MF,
const PPCTargetLowering &TLI = *Subtarget.getTargetLowering(); const PPCTargetLowering &TLI = *Subtarget.getTargetLowering();
MachineModuleInfo &MMI = MF.getMMI(); MachineModuleInfo &MMI = MF.getMMI();
const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo(); const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
DebugLoc dl; DebugLoc dl;
// AIX assembler does not support cfi directives. // AIX assembler does not support cfi directives.
const bool needsCFI = MF.needsFrameMoves() && !Subtarget.isAIXABI(); const bool needsCFI = MF.needsFrameMoves() && !Subtarget.isAIXABI();
const bool HasFastMFLR = Subtarget.hasFastMFLR();
// Get processor type. // Get processor type.
RolandFUnsubmitted
Done
ReplyInline Actions

The cost of an mflr is a characteristic of an implementation, not of the architecture. A future processor might have a slow mflr. I think a new subtarget feature is needed for this.

RolandF: The cost of an mflr is a characteristic of an implementation, not of the architecture. A…
shchenzAuthorUnsubmitted
Done
ReplyInline Actions

I added a new patch https://reviews.llvm.org/D137612 to add the subtarget feature. Seems for P10, the latency for mflr is only 2 cycles, so I only set the new feature for P10.

shchenz: I added a new patch https://reviews.llvm.org/D137612 to add the subtarget feature. Seems for…
bool isPPC64 = Subtarget.isPPC64(); bool isPPC64 = Subtarget.isPPC64();
// Get the ABI. // Get the ABI.
bool isSVR4ABI = Subtarget.isSVR4ABI(); bool isSVR4ABI = Subtarget.isSVR4ABI();
bool isELFv2ABI = Subtarget.isELFv2ABI(); bool isELFv2ABI = Subtarget.isELFv2ABI();
assert((isSVR4ABI || Subtarget.isAIXABI()) && "Unsupported PPC ABI."); assert((isSVR4ABI || Subtarget.isAIXABI()) && "Unsupported PPC ABI.");
// Work out frame sizes. // Work out frame sizes.
uint64_t FrameSize = determineFrameLayoutAndUpdate(MF); uint64_t FrameSize = determineFrameLayoutAndUpdate(MF);
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Lines if (HasBP)
.addReg(BPReg) .addReg(BPReg)
.addImm(BPOffset) .addImm(BPOffset)
.addReg(SPReg); .addReg(SPReg);
} }
// Generate the instruction to store the LR. In the case where ROP protection // Generate the instruction to store the LR. In the case where ROP protection
// is required the register holding the LR should not be killed as it will be // is required the register holding the LR should not be killed as it will be
// used by the hash store instruction. // used by the hash store instruction.
if (MustSaveLR) { auto SaveLR = [&](int64_t Offset) {
assert(MustSaveLR && "LR is not required to be saved!");
BuildMI(MBB, StackUpdateLoc, dl, StoreInst) BuildMI(MBB, StackUpdateLoc, dl, StoreInst)
.addReg(ScratchReg, getKillRegState(!HasROPProtect)) .addReg(ScratchReg, getKillRegState(!HasROPProtect))
.addImm(LROffset) .addImm(Offset)
.addReg(SPReg); .addReg(SPReg);
// Add the ROP protection Hash Store instruction. // Add the ROP protection Hash Store instruction.
// NOTE: This is technically a violation of the ABI. The hash can be saved // NOTE: This is technically a violation of the ABI. The hash can be saved
// up to 512 bytes into the Protected Zone. This can be outside of the // up to 512 bytes into the Protected Zone. This can be outside of the
// initial 288 byte volatile program storage region in the Protected Zone. // initial 288 byte volatile program storage region in the Protected Zone.
// However, this restriction will be removed in an upcoming revision of the // However, this restriction will be removed in an upcoming revision of the
// ABI. // ABI.
if (HasROPProtect) { if (HasROPProtect) {
const int SaveIndex = FI->getROPProtectionHashSaveIndex(); const int SaveIndex = FI->getROPProtectionHashSaveIndex();
const int64_t ImmOffset = MFI.getObjectOffset(SaveIndex); const int64_t ImmOffset = MFI.getObjectOffset(SaveIndex);
assert((ImmOffset <= -8 && ImmOffset >= -512) && assert((ImmOffset <= -8 && ImmOffset >= -512) &&
"ROP hash save offset out of range."); "ROP hash save offset out of range.");
assert(((ImmOffset & 0x7) == 0) && assert(((ImmOffset & 0x7) == 0) &&
"ROP hash save offset must be 8 byte aligned."); "ROP hash save offset must be 8 byte aligned.");
BuildMI(MBB, StackUpdateLoc, dl, HashST) BuildMI(MBB, StackUpdateLoc, dl, HashST)
.addReg(ScratchReg, getKillRegState(true)) .addReg(ScratchReg, getKillRegState(true))
.addImm(ImmOffset) .addImm(ImmOffset)
.addReg(SPReg); .addReg(SPReg);
} }
} };
if (MustSaveLR && HasFastMFLR)
SaveLR(LROffset);
if (MustSaveCR && if (MustSaveCR &&
!(SingleScratchReg && MustSaveLR)) { !(SingleScratchReg && MustSaveLR)) {
assert(HasRedZone && "A red zone is always available on PPC64"); assert(HasRedZone && "A red zone is always available on PPC64");
BuildMI(MBB, MBBI, dl, StoreWordInst) BuildMI(MBB, MBBI, dl, StoreWordInst)
.addReg(TempReg, getKillRegState(true)) .addReg(TempReg, getKillRegState(true))
.addImm(CRSaveOffset) .addImm(CRSaveOffset)
.addReg(SPReg); .addReg(SPReg);
} }
// Skip the rest if this is a leaf function & all spills fit in the Red Zone. // Skip the rest if this is a leaf function & all spills fit in the Red Zone.
if (!FrameSize) if (!FrameSize) {
if (MustSaveLR && !HasFastMFLR)
SaveLR(LROffset);
return; return;
}
// Adjust stack pointer: r1 += NegFrameSize. // Adjust stack pointer: r1 += NegFrameSize.
// If there is a preferred stack alignment, align R1 now // If there is a preferred stack alignment, align R1 now
if (HasBP && HasRedZone) { if (HasBP && HasRedZone) {
// Save a copy of r1 as the base pointer. // Save a copy of r1 as the base pointer.
BuildMI(MBB, MBBI, dl, OrInst, BPReg) BuildMI(MBB, MBBI, dl, OrInst, BPReg)
.addReg(SPReg) .addReg(SPReg)
.addReg(SPReg); .addReg(SPReg);
} }
// Have we generated a STUX instruction to claim stack frame? If so, // Have we generated a STUX instruction to claim stack frame? If so,
// the negated frame size will be placed in ScratchReg. // the negated frame size will be placed in ScratchReg.
bool HasSTUX = false; bool HasSTUX =
(TLI.hasInlineStackProbe(MF) && FrameSize > TLI.getStackProbeSize(MF)) ||
(HasBP && MaxAlign > 1) || isLargeFrame;
// If we use STUX to update the stack pointer, we need the two scratch
// registers TempReg and ScratchReg, we have to save LR here which is stored
// in ScratchReg.
if (HasSTUX && MustSaveLR && !HasFastMFLR)
SaveLR(LROffset);
// If FrameSize <= TLI.getStackProbeSize(MF), as POWER ABI requires backchain // If FrameSize <= TLI.getStackProbeSize(MF), as POWER ABI requires backchain
// pointer is always stored at SP, we will get a free probe due to an essential // pointer is always stored at SP, we will get a free probe due to an essential
// STU(X) instruction. // STU(X) instruction.
if (TLI.hasInlineStackProbe(MF) && FrameSize > TLI.getStackProbeSize(MF)) { if (TLI.hasInlineStackProbe(MF) && FrameSize > TLI.getStackProbeSize(MF)) {
// To be consistent with other targets, a pseudo instruction is emitted and // To be consistent with other targets, a pseudo instruction is emitted and
// will be later expanded in `inlineStackProbe`. // will be later expanded in `inlineStackProbe`.
BuildMI(MBB, MBBI, dl, BuildMI(MBB, MBBI, dl,
TII.get(isPPC64 ? PPC::PROBED_STACKALLOC_64 TII.get(isPPC64 ? PPC::PROBED_STACKALLOC_64
: PPC::PROBED_STACKALLOC_32)) : PPC::PROBED_STACKALLOC_32))
.addDef(TempReg) .addDef(TempReg)
.addDef(ScratchReg) // ScratchReg stores the old sp. .addDef(ScratchReg) // ScratchReg stores the old sp.
.addImm(NegFrameSize); .addImm(NegFrameSize);
// FIXME: HasSTUX is only read if HasRedZone is not set, in such case, we // FIXME: HasSTUX is only read if HasRedZone is not set, in such case, we
// update the ScratchReg to meet the assumption that ScratchReg contains // update the ScratchReg to meet the assumption that ScratchReg contains
// the NegFrameSize. This solution is rather tricky. // the NegFrameSize. This solution is rather tricky.
if (!HasRedZone) { if (!HasRedZone) {
BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBF), ScratchReg) BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBF), ScratchReg)
.addReg(ScratchReg) .addReg(ScratchReg)
.addReg(SPReg); .addReg(SPReg);
HasSTUX = true;
} }
} else { } else {
// This condition must be kept in sync with canUseAsPrologue. // This condition must be kept in sync with canUseAsPrologue.
if (HasBP && MaxAlign > 1) { if (HasBP && MaxAlign > 1) {
if (isPPC64) if (isPPC64)
BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), ScratchReg) BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), ScratchReg)
.addReg(SPReg) .addReg(SPReg)
.addImm(0) .addImm(0)
Show All 15 Lines if (HasBP && MaxAlign > 1) {
.addReg(ScratchReg, RegState::Kill) .addReg(ScratchReg, RegState::Kill)
.addReg(TempReg, RegState::Kill); .addReg(TempReg, RegState::Kill);
} }
BuildMI(MBB, MBBI, dl, StoreUpdtIdxInst, SPReg) BuildMI(MBB, MBBI, dl, StoreUpdtIdxInst, SPReg)
.addReg(SPReg, RegState::Kill) .addReg(SPReg, RegState::Kill)
.addReg(SPReg) .addReg(SPReg)
.addReg(ScratchReg); .addReg(ScratchReg);
HasSTUX = true;
} else if (!isLargeFrame) { } else if (!isLargeFrame) {
BuildMI(MBB, StackUpdateLoc, dl, StoreUpdtInst, SPReg) BuildMI(MBB, StackUpdateLoc, dl, StoreUpdtInst, SPReg)
.addReg(SPReg) .addReg(SPReg)
.addImm(NegFrameSize) .addImm(NegFrameSize)
.addReg(SPReg); .addReg(SPReg);
} else { } else {
TII.materializeImmPostRA(MBB, MBBI, dl, ScratchReg, NegFrameSize); TII.materializeImmPostRA(MBB, MBBI, dl, ScratchReg, NegFrameSize);
BuildMI(MBB, MBBI, dl, StoreUpdtIdxInst, SPReg) BuildMI(MBB, MBBI, dl, StoreUpdtIdxInst, SPReg)
.addReg(SPReg, RegState::Kill) .addReg(SPReg, RegState::Kill)
.addReg(SPReg) .addReg(SPReg)
.addReg(ScratchReg); .addReg(ScratchReg);
HasSTUX = true;
} }
} }
// Save the TOC register after the stack pointer update if a prologue TOC // Save the TOC register after the stack pointer update if a prologue TOC
// save is required for the function. // save is required for the function.
if (MustSaveTOC) { if (MustSaveTOC) {
assert(isELFv2ABI && "TOC saves in the prologue only supported on ELFv2"); assert(isELFv2ABI && "TOC saves in the prologue only supported on ELFv2");
BuildMI(MBB, StackUpdateLoc, dl, TII.get(PPC::STD)) BuildMI(MBB, StackUpdateLoc, dl, TII.get(PPC::STD))
▲ Show 20 Lines • Show All 110 Lines • ▼ Show 20 Lines if (HasSTUX) {
.addReg(SPReg); .addReg(SPReg);
BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), BPReg) BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), BPReg)
.addReg(SPReg) .addReg(SPReg)
.addImm(FrameSize); .addImm(FrameSize);
} }
} }
} }
// Save the LR now.
if (!HasSTUX && MustSaveLR && !HasFastMFLR)
SaveLR(LROffset + FrameSize);
// Add Call Frame Information for the instructions we generated above. // Add Call Frame Information for the instructions we generated above.
if (needsCFI) { if (needsCFI) {
unsigned CFIIndex; unsigned CFIIndex;
if (HasBP) { if (HasBP) {
// Define CFA in terms of BP. Do this in preference to using FP/SP, // Define CFA in terms of BP. Do this in preference to using FP/SP,
// because if the stack needed aligning then CFA won't be at a fixed // because if the stack needed aligning then CFA won't be at a fixed
// offset from FP/SP. // offset from FP/SP.
▲ Show 20 Lines • Show All 1,602 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/2007-09-08-unaligned.ll

Show First 20 Lines • Show All 48 Lines • ▼ Show 20 Linesreturn: ; preds = %entry
%retval6 = load i32, ptr %retval ; <i32> [#uses=1] %retval6 = load i32, ptr %retval ; <i32> [#uses=1]
ret i32 %retval6 ret i32 %retval6
} }
define i32 @main() { define i32 @main() {
; CHECK-LABEL: main: ; CHECK-LABEL: main:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; CHECK-NEXT: stw 0, 4(1)
; CHECK-NEXT: stwu 1, -16(1) ; CHECK-NEXT: stwu 1, -16(1)
; CHECK-NEXT: stw 0, 20(1)
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset lr, 4 ; CHECK-NEXT: .cfi_offset lr, 4
; CHECK-NEXT: bl foo ; CHECK-NEXT: bl foo
; CHECK-NEXT: lis 3, t@ha ; CHECK-NEXT: lis 3, t@ha
; CHECK-NEXT: la 3, t@l(3) ; CHECK-NEXT: la 3, t@l(3)
; CHECK-NEXT: lfs 1, 1(3) ; CHECK-NEXT: lfs 1, 1(3)
; CHECK-NEXT: lis 3, v@ha ; CHECK-NEXT: lis 3, v@ha
; CHECK-NEXT: la 3, v@l(3) ; CHECK-NEXT: la 3, v@l(3)
Show All 29 Lines

llvm/test/CodeGen/PowerPC/2007-11-16-landingpad-split.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck %s ; RUN: llc -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck %s
;; Formerly crashed, see PR 1508 ;; Formerly crashed, see PR 1508
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
%struct.Range = type { i64, i64 } %struct.Range = type { i64, i64 }
define void @Bork(i64 %range.0.0, i64 %range.0.1, i64 %size) personality ptr @__gxx_personality_v0 { define void @Bork(i64 %range.0.0, i64 %range.0.1, i64 %size) personality ptr @__gxx_personality_v0 {
; CHECK-LABEL: Bork: ; CHECK-LABEL: Bork:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; CHECK-NEXT: std 31, -8(1) ; CHECK-NEXT: std 31, -8(1)
; CHECK-NEXT: std 0, 16(1)
; CHECK-NEXT: stdu 1, -176(1) ; CHECK-NEXT: stdu 1, -176(1)
; CHECK-NEXT: std 0, 192(1)
; CHECK-NEXT: .cfi_def_cfa_offset 176 ; CHECK-NEXT: .cfi_def_cfa_offset 176
; CHECK-NEXT: .cfi_offset r31, -8 ; CHECK-NEXT: .cfi_offset r31, -8
; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: mr 31, 1 ; CHECK-NEXT: mr 31, 1
; CHECK-NEXT: .cfi_def_cfa_register r31 ; CHECK-NEXT: .cfi_def_cfa_register r31
; CHECK-NEXT: .cfi_offset r27, -40 ; CHECK-NEXT: .cfi_offset r27, -40
; CHECK-NEXT: .cfi_offset r28, -32 ; CHECK-NEXT: .cfi_offset r28, -32
; CHECK-NEXT: .cfi_offset r29, -24 ; CHECK-NEXT: .cfi_offset r29, -24
▲ Show 20 Lines • Show All 104 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/2008-10-28-f128-i32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -o - | FileCheck %s ; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -o - | FileCheck %s
define i64 @__fixunstfdi(ppc_fp128 %a) nounwind readnone { define i64 @__fixunstfdi(ppc_fp128 %a) nounwind readnone {
; CHECK-LABEL: __fixunstfdi: ; CHECK-LABEL: __fixunstfdi:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; CHECK-NEXT: stw 0, 4(1)
; CHECK-NEXT: stwu 1, -464(1) ; CHECK-NEXT: stwu 1, -464(1)
; CHECK-NEXT: mfcr 12 ; CHECK-NEXT: mfcr 12
; CHECK-NEXT: stw 29, 412(1) # 4-byte Folded Spill ; CHECK-NEXT: stw 0, 468(1)
; CHECK-NEXT: lis 3, .LCPI0_0@ha ; CHECK-NEXT: lis 3, .LCPI0_0@ha
; CHECK-NEXT: stw 29, 412(1) # 4-byte Folded Spill
; CHECK-NEXT: stw 30, 416(1) # 4-byte Folded Spill ; CHECK-NEXT: stw 30, 416(1) # 4-byte Folded Spill
; CHECK-NEXT: stw 12, 408(1) ; CHECK-NEXT: stw 12, 408(1)
; CHECK-NEXT: stfd 2, 376(1) ; CHECK-NEXT: stfd 2, 376(1)
; CHECK-NEXT: lwz 4, 380(1) ; CHECK-NEXT: lwz 4, 380(1)
; CHECK-NEXT: stfd 27, 424(1) # 8-byte Folded Spill ; CHECK-NEXT: stfd 27, 424(1) # 8-byte Folded Spill
; CHECK-NEXT: stw 4, 396(1) ; CHECK-NEXT: stw 4, 396(1)
; CHECK-NEXT: lwz 4, 376(1) ; CHECK-NEXT: lwz 4, 376(1)
; CHECK-NEXT: lfs 27, .LCPI0_0@l(3) ; CHECK-NEXT: lfs 27, .LCPI0_0@l(3)
▲ Show 20 Lines • Show All 319 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/2010-05-03-retaddr1.ll

Show All 14 Lines
} }
declare ptr @llvm.returnaddress(i32) nounwind readnone declare ptr @llvm.returnaddress(i32) nounwind readnone
define ptr @g() nounwind readnone { define ptr @g() nounwind readnone {
; CHECK-LABEL: g: ; CHECK-LABEL: g:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; CHECK-NEXT: stw 0, 4(1)
; CHECK-NEXT: stwu 1, -16(1) ; CHECK-NEXT: stwu 1, -16(1)
; CHECK-NEXT: stw 0, 20(1)
; CHECK-NEXT: lwz 3, 0(1) ; CHECK-NEXT: lwz 3, 0(1)
; CHECK-NEXT: lwz 3, 0(3) ; CHECK-NEXT: lwz 3, 0(3)
; CHECK-NEXT: lwz 3, 4(3) ; CHECK-NEXT: lwz 3, 4(3)
; CHECK-NEXT: lwz 0, 20(1) ; CHECK-NEXT: lwz 0, 20(1)
; CHECK-NEXT: addi 1, 1, 16 ; CHECK-NEXT: addi 1, 1, 16
; CHECK-NEXT: mtlr 0 ; CHECK-NEXT: mtlr 0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%0 = tail call ptr @llvm.returnaddress(i32 1) ; <ptr> [#uses=1] %0 = tail call ptr @llvm.returnaddress(i32 1) ; <ptr> [#uses=1]
ret ptr %0 ret ptr %0
} }

llvm/test/CodeGen/PowerPC/CSR-fit.ll

Show All 11 Lines
; CHECK-PWR8: # %bb.0: # %entry ; CHECK-PWR8: # %bb.0: # %entry
; CHECK-PWR8-NEXT: mflr r0 ; CHECK-PWR8-NEXT: mflr r0
; CHECK-PWR8-NEXT: .cfi_def_cfa_offset 176 ; CHECK-PWR8-NEXT: .cfi_def_cfa_offset 176
; CHECK-PWR8-NEXT: .cfi_offset lr, 16 ; CHECK-PWR8-NEXT: .cfi_offset lr, 16
; CHECK-PWR8-NEXT: .cfi_offset r14, -144 ; CHECK-PWR8-NEXT: .cfi_offset r14, -144
; CHECK-PWR8-NEXT: .cfi_offset r15, -136 ; CHECK-PWR8-NEXT: .cfi_offset r15, -136
; CHECK-PWR8-NEXT: std r14, -144(r1) # 8-byte Folded Spill ; CHECK-PWR8-NEXT: std r14, -144(r1) # 8-byte Folded Spill
; CHECK-PWR8-NEXT: std r15, -136(r1) # 8-byte Folded Spill ; CHECK-PWR8-NEXT: std r15, -136(r1) # 8-byte Folded Spill
; CHECK-PWR8-NEXT: std r0, 16(r1)
; CHECK-PWR8-NEXT: stdu r1, -176(r1) ; CHECK-PWR8-NEXT: stdu r1, -176(r1)
; CHECK-PWR8-NEXT: #APP ; CHECK-PWR8-NEXT: #APP
; CHECK-PWR8-NEXT: add r3, r3, r4 ; CHECK-PWR8-NEXT: add r3, r3, r4
; CHECK-PWR8-NEXT: #NO_APP ; CHECK-PWR8-NEXT: #NO_APP
; CHECK-PWR8-NEXT: std r0, 192(r1)
; CHECK-PWR8-NEXT: extsw r3, r3 ; CHECK-PWR8-NEXT: extsw r3, r3
; CHECK-PWR8-NEXT: bl callee ; CHECK-PWR8-NEXT: bl callee
; CHECK-PWR8-NEXT: nop ; CHECK-PWR8-NEXT: nop
; CHECK-PWR8-NEXT: addi r1, r1, 176 ; CHECK-PWR8-NEXT: addi r1, r1, 176
; CHECK-PWR8-NEXT: ld r0, 16(r1) ; CHECK-PWR8-NEXT: ld r0, 16(r1)
; CHECK-PWR8-NEXT: ld r15, -136(r1) # 8-byte Folded Reload ; CHECK-PWR8-NEXT: ld r15, -136(r1) # 8-byte Folded Reload
; CHECK-PWR8-NEXT: ld r14, -144(r1) # 8-byte Folded Reload ; CHECK-PWR8-NEXT: ld r14, -144(r1) # 8-byte Folded Reload
; CHECK-PWR8-NEXT: mtlr r0 ; CHECK-PWR8-NEXT: mtlr r0
; CHECK-PWR8-NEXT: blr ; CHECK-PWR8-NEXT: blr
; ;
; CHECK-PWR9-LABEL: caller1: ; CHECK-PWR9-LABEL: caller1:
; CHECK-PWR9: # %bb.0: # %entry ; CHECK-PWR9: # %bb.0: # %entry
; CHECK-PWR9-NEXT: mflr r0 ; CHECK-PWR9-NEXT: mflr r0
; CHECK-PWR9-NEXT: .cfi_def_cfa_offset 176 ; CHECK-PWR9-NEXT: .cfi_def_cfa_offset 176
; CHECK-PWR9-NEXT: .cfi_offset lr, 16 ; CHECK-PWR9-NEXT: .cfi_offset lr, 16
; CHECK-PWR9-NEXT: .cfi_offset r14, -144 ; CHECK-PWR9-NEXT: .cfi_offset r14, -144
; CHECK-PWR9-NEXT: .cfi_offset r15, -136 ; CHECK-PWR9-NEXT: .cfi_offset r15, -136
; CHECK-PWR9-NEXT: std r14, -144(r1) # 8-byte Folded Spill ; CHECK-PWR9-NEXT: std r14, -144(r1) # 8-byte Folded Spill
; CHECK-PWR9-NEXT: std r15, -136(r1) # 8-byte Folded Spill ; CHECK-PWR9-NEXT: std r15, -136(r1) # 8-byte Folded Spill
; CHECK-PWR9-NEXT: std r0, 16(r1)
; CHECK-PWR9-NEXT: stdu r1, -176(r1) ; CHECK-PWR9-NEXT: stdu r1, -176(r1)
; CHECK-PWR9-NEXT: #APP ; CHECK-PWR9-NEXT: #APP
; CHECK-PWR9-NEXT: add r3, r3, r4 ; CHECK-PWR9-NEXT: add r3, r3, r4
; CHECK-PWR9-NEXT: #NO_APP ; CHECK-PWR9-NEXT: #NO_APP
; CHECK-PWR9-NEXT: extsw r3, r3 ; CHECK-PWR9-NEXT: extsw r3, r3
; CHECK-PWR9-NEXT: std r0, 192(r1)
; CHECK-PWR9-NEXT: bl callee ; CHECK-PWR9-NEXT: bl callee
; CHECK-PWR9-NEXT: nop ; CHECK-PWR9-NEXT: nop
; CHECK-PWR9-NEXT: addi r1, r1, 176 ; CHECK-PWR9-NEXT: addi r1, r1, 176
; CHECK-PWR9-NEXT: ld r0, 16(r1) ; CHECK-PWR9-NEXT: ld r0, 16(r1)
; CHECK-PWR9-NEXT: ld r15, -136(r1) # 8-byte Folded Reload ; CHECK-PWR9-NEXT: ld r15, -136(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: ld r14, -144(r1) # 8-byte Folded Reload ; CHECK-PWR9-NEXT: ld r14, -144(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: mtlr r0 ; CHECK-PWR9-NEXT: mtlr r0
; CHECK-PWR9-NEXT: blr ; CHECK-PWR9-NEXT: blr
entry: entry:
%0 = tail call i32 asm "add $0, $1, $2", "=r,r,r,~{r14},~{r15}"(i32 %a, i32 %b) %0 = tail call i32 asm "add $0, $1, $2", "=r,r,r,~{r14},~{r15}"(i32 %a, i32 %b)
%call = tail call signext i32 @callee(i32 signext %0) %call = tail call signext i32 @callee(i32 signext %0)
ret i32 %call ret i32 %call
} }
define dso_local signext i32 @caller2(i32 signext %a, i32 signext %b) local_unnamed_addr { define dso_local signext i32 @caller2(i32 signext %a, i32 signext %b) local_unnamed_addr {
; CHECK-PWR8-LABEL: caller2: ; CHECK-PWR8-LABEL: caller2:
; CHECK-PWR8: # %bb.0: # %entry ; CHECK-PWR8: # %bb.0: # %entry
; CHECK-PWR8-NEXT: mflr r0 ; CHECK-PWR8-NEXT: mflr r0
; CHECK-PWR8-NEXT: .cfi_def_cfa_offset 176 ; CHECK-PWR8-NEXT: .cfi_def_cfa_offset 176
; CHECK-PWR8-NEXT: .cfi_offset lr, 16 ; CHECK-PWR8-NEXT: .cfi_offset lr, 16
; CHECK-PWR8-NEXT: .cfi_offset f14, -144 ; CHECK-PWR8-NEXT: .cfi_offset f14, -144
; CHECK-PWR8-NEXT: .cfi_offset f15, -136 ; CHECK-PWR8-NEXT: .cfi_offset f15, -136
; CHECK-PWR8-NEXT: stfd f14, -144(r1) # 8-byte Folded Spill ; CHECK-PWR8-NEXT: stfd f14, -144(r1) # 8-byte Folded Spill
; CHECK-PWR8-NEXT: stfd f15, -136(r1) # 8-byte Folded Spill ; CHECK-PWR8-NEXT: stfd f15, -136(r1) # 8-byte Folded Spill
; CHECK-PWR8-NEXT: std r0, 16(r1)
; CHECK-PWR8-NEXT: stdu r1, -176(r1) ; CHECK-PWR8-NEXT: stdu r1, -176(r1)
; CHECK-PWR8-NEXT: #APP ; CHECK-PWR8-NEXT: #APP
; CHECK-PWR8-NEXT: add r3, r3, r4 ; CHECK-PWR8-NEXT: add r3, r3, r4
; CHECK-PWR8-NEXT: #NO_APP ; CHECK-PWR8-NEXT: #NO_APP
; CHECK-PWR8-NEXT: std r0, 192(r1)
; CHECK-PWR8-NEXT: extsw r3, r3 ; CHECK-PWR8-NEXT: extsw r3, r3
; CHECK-PWR8-NEXT: bl callee ; CHECK-PWR8-NEXT: bl callee
; CHECK-PWR8-NEXT: nop ; CHECK-PWR8-NEXT: nop
; CHECK-PWR8-NEXT: addi r1, r1, 176 ; CHECK-PWR8-NEXT: addi r1, r1, 176
; CHECK-PWR8-NEXT: ld r0, 16(r1) ; CHECK-PWR8-NEXT: ld r0, 16(r1)
; CHECK-PWR8-NEXT: lfd f15, -136(r1) # 8-byte Folded Reload ; CHECK-PWR8-NEXT: lfd f15, -136(r1) # 8-byte Folded Reload
; CHECK-PWR8-NEXT: lfd f14, -144(r1) # 8-byte Folded Reload ; CHECK-PWR8-NEXT: lfd f14, -144(r1) # 8-byte Folded Reload
; CHECK-PWR8-NEXT: mtlr r0 ; CHECK-PWR8-NEXT: mtlr r0
; CHECK-PWR8-NEXT: blr ; CHECK-PWR8-NEXT: blr
; ;
; CHECK-PWR9-LABEL: caller2: ; CHECK-PWR9-LABEL: caller2:
; CHECK-PWR9: # %bb.0: # %entry ; CHECK-PWR9: # %bb.0: # %entry
; CHECK-PWR9-NEXT: mflr r0 ; CHECK-PWR9-NEXT: mflr r0
; CHECK-PWR9-NEXT: .cfi_def_cfa_offset 176 ; CHECK-PWR9-NEXT: .cfi_def_cfa_offset 176
; CHECK-PWR9-NEXT: .cfi_offset lr, 16 ; CHECK-PWR9-NEXT: .cfi_offset lr, 16
; CHECK-PWR9-NEXT: .cfi_offset f14, -144 ; CHECK-PWR9-NEXT: .cfi_offset f14, -144
; CHECK-PWR9-NEXT: .cfi_offset f15, -136 ; CHECK-PWR9-NEXT: .cfi_offset f15, -136
; CHECK-PWR9-NEXT: stfd f14, -144(r1) # 8-byte Folded Spill ; CHECK-PWR9-NEXT: stfd f14, -144(r1) # 8-byte Folded Spill
; CHECK-PWR9-NEXT: stfd f15, -136(r1) # 8-byte Folded Spill ; CHECK-PWR9-NEXT: stfd f15, -136(r1) # 8-byte Folded Spill
; CHECK-PWR9-NEXT: std r0, 16(r1)
; CHECK-PWR9-NEXT: stdu r1, -176(r1) ; CHECK-PWR9-NEXT: stdu r1, -176(r1)
; CHECK-PWR9-NEXT: #APP ; CHECK-PWR9-NEXT: #APP
; CHECK-PWR9-NEXT: add r3, r3, r4 ; CHECK-PWR9-NEXT: add r3, r3, r4
; CHECK-PWR9-NEXT: #NO_APP ; CHECK-PWR9-NEXT: #NO_APP
; CHECK-PWR9-NEXT: extsw r3, r3 ; CHECK-PWR9-NEXT: extsw r3, r3
; CHECK-PWR9-NEXT: std r0, 192(r1)
; CHECK-PWR9-NEXT: bl callee ; CHECK-PWR9-NEXT: bl callee
; CHECK-PWR9-NEXT: nop ; CHECK-PWR9-NEXT: nop
; CHECK-PWR9-NEXT: addi r1, r1, 176 ; CHECK-PWR9-NEXT: addi r1, r1, 176
; CHECK-PWR9-NEXT: ld r0, 16(r1) ; CHECK-PWR9-NEXT: ld r0, 16(r1)
; CHECK-PWR9-NEXT: lfd f15, -136(r1) # 8-byte Folded Reload ; CHECK-PWR9-NEXT: lfd f15, -136(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: lfd f14, -144(r1) # 8-byte Folded Reload ; CHECK-PWR9-NEXT: lfd f14, -144(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: mtlr r0 ; CHECK-PWR9-NEXT: mtlr r0
; CHECK-PWR9-NEXT: blr ; CHECK-PWR9-NEXT: blr
entry: entry:
%0 = tail call i32 asm "add $0, $1, $2", "=r,r,r,~{f14},~{f15}"(i32 %a, i32 %b) %0 = tail call i32 asm "add $0, $1, $2", "=r,r,r,~{f14},~{f15}"(i32 %a, i32 %b)
%call = tail call signext i32 @callee(i32 signext %0) %call = tail call signext i32 @callee(i32 signext %0)
ret i32 %call ret i32 %call
} }
define dso_local signext i32 @caller3(i32 signext %a, i32 signext %b) local_unnamed_addr { define dso_local signext i32 @caller3(i32 signext %a, i32 signext %b) local_unnamed_addr {
; CHECK-PWR8-LABEL: caller3: ; CHECK-PWR8-LABEL: caller3:
; CHECK-PWR8: # %bb.0: # %entry ; CHECK-PWR8: # %bb.0: # %entry
; CHECK-PWR8-NEXT: mflr r0 ; CHECK-PWR8-NEXT: mflr r0
; CHECK-PWR8-NEXT: std r0, 16(r1)
; CHECK-PWR8-NEXT: stdu r1, -240(r1) ; CHECK-PWR8-NEXT: stdu r1, -240(r1)
; CHECK-PWR8-NEXT: std r0, 256(r1)
; CHECK-PWR8-NEXT: .cfi_def_cfa_offset 240 ; CHECK-PWR8-NEXT: .cfi_def_cfa_offset 240
; CHECK-PWR8-NEXT: .cfi_offset lr, 16 ; CHECK-PWR8-NEXT: .cfi_offset lr, 16
; CHECK-PWR8-NEXT: .cfi_offset v20, -192 ; CHECK-PWR8-NEXT: .cfi_offset v20, -192
; CHECK-PWR8-NEXT: .cfi_offset v21, -176 ; CHECK-PWR8-NEXT: .cfi_offset v21, -176
; CHECK-PWR8-NEXT: li r5, 48 ; CHECK-PWR8-NEXT: li r5, 48
; CHECK-PWR8-NEXT: stvx v20, r1, r5 # 16-byte Folded Spill ; CHECK-PWR8-NEXT: stvx v20, r1, r5 # 16-byte Folded Spill
; CHECK-PWR8-NEXT: li r5, 64 ; CHECK-PWR8-NEXT: li r5, 64
; CHECK-PWR8-NEXT: stvx v21, r1, r5 # 16-byte Folded Spill ; CHECK-PWR8-NEXT: stvx v21, r1, r5 # 16-byte Folded Spill
Show All 10 Lines
; CHECK-PWR8-NEXT: addi r1, r1, 240 ; CHECK-PWR8-NEXT: addi r1, r1, 240
; CHECK-PWR8-NEXT: ld r0, 16(r1) ; CHECK-PWR8-NEXT: ld r0, 16(r1)
; CHECK-PWR8-NEXT: mtlr r0 ; CHECK-PWR8-NEXT: mtlr r0
; CHECK-PWR8-NEXT: blr ; CHECK-PWR8-NEXT: blr
; ;
; CHECK-PWR9-LABEL: caller3: ; CHECK-PWR9-LABEL: caller3:
; CHECK-PWR9: # %bb.0: # %entry ; CHECK-PWR9: # %bb.0: # %entry
; CHECK-PWR9-NEXT: mflr r0 ; CHECK-PWR9-NEXT: mflr r0
; CHECK-PWR9-NEXT: std r0, 16(r1)
; CHECK-PWR9-NEXT: stdu r1, -224(r1) ; CHECK-PWR9-NEXT: stdu r1, -224(r1)
; CHECK-PWR9-NEXT: std r0, 240(r1)
; CHECK-PWR9-NEXT: .cfi_def_cfa_offset 224 ; CHECK-PWR9-NEXT: .cfi_def_cfa_offset 224
; CHECK-PWR9-NEXT: .cfi_offset lr, 16 ; CHECK-PWR9-NEXT: .cfi_offset lr, 16
; CHECK-PWR9-NEXT: .cfi_offset v20, -192 ; CHECK-PWR9-NEXT: .cfi_offset v20, -192
; CHECK-PWR9-NEXT: .cfi_offset v21, -176 ; CHECK-PWR9-NEXT: .cfi_offset v21, -176
; CHECK-PWR9-NEXT: stxv v20, 32(r1) # 16-byte Folded Spill ; CHECK-PWR9-NEXT: stxv v20, 32(r1) # 16-byte Folded Spill
; CHECK-PWR9-NEXT: stxv v21, 48(r1) # 16-byte Folded Spill ; CHECK-PWR9-NEXT: stxv v21, 48(r1) # 16-byte Folded Spill
; CHECK-PWR9-NEXT: #APP ; CHECK-PWR9-NEXT: #APP
; CHECK-PWR9-NEXT: add r3, r3, r4 ; CHECK-PWR9-NEXT: add r3, r3, r4
Show All 12 Linesentry:
%call = tail call signext i32 @callee(i32 signext %0) %call = tail call signext i32 @callee(i32 signext %0)
ret i32 %call ret i32 %call
} }
define dso_local signext i32 @caller4(i32 signext %a, i32 signext %b) local_unnamed_addr { define dso_local signext i32 @caller4(i32 signext %a, i32 signext %b) local_unnamed_addr {
; CHECK-PWR8-LABEL: caller4: ; CHECK-PWR8-LABEL: caller4:
; CHECK-PWR8: # %bb.0: # %entry ; CHECK-PWR8: # %bb.0: # %entry
; CHECK-PWR8-NEXT: mflr r0 ; CHECK-PWR8-NEXT: mflr r0
; CHECK-PWR8-NEXT: std r0, 16(r1)
; CHECK-PWR8-NEXT: stdu r1, -240(r1) ; CHECK-PWR8-NEXT: stdu r1, -240(r1)
; CHECK-PWR8-NEXT: std r0, 256(r1)
; CHECK-PWR8-NEXT: .cfi_def_cfa_offset 240 ; CHECK-PWR8-NEXT: .cfi_def_cfa_offset 240
; CHECK-PWR8-NEXT: .cfi_offset lr, 16 ; CHECK-PWR8-NEXT: .cfi_offset lr, 16
; CHECK-PWR8-NEXT: .cfi_offset v20, -192 ; CHECK-PWR8-NEXT: .cfi_offset v20, -192
; CHECK-PWR8-NEXT: .cfi_offset v21, -176 ; CHECK-PWR8-NEXT: .cfi_offset v21, -176
; CHECK-PWR8-NEXT: li r5, 48 ; CHECK-PWR8-NEXT: li r5, 48
; CHECK-PWR8-NEXT: stvx v20, r1, r5 # 16-byte Folded Spill ; CHECK-PWR8-NEXT: stvx v20, r1, r5 # 16-byte Folded Spill
; CHECK-PWR8-NEXT: li r5, 64 ; CHECK-PWR8-NEXT: li r5, 64
; CHECK-PWR8-NEXT: stvx v21, r1, r5 # 16-byte Folded Spill ; CHECK-PWR8-NEXT: stvx v21, r1, r5 # 16-byte Folded Spill
Show All 10 Lines
; CHECK-PWR8-NEXT: addi r1, r1, 240 ; CHECK-PWR8-NEXT: addi r1, r1, 240
; CHECK-PWR8-NEXT: ld r0, 16(r1) ; CHECK-PWR8-NEXT: ld r0, 16(r1)
; CHECK-PWR8-NEXT: mtlr r0 ; CHECK-PWR8-NEXT: mtlr r0
; CHECK-PWR8-NEXT: blr ; CHECK-PWR8-NEXT: blr
; ;
; CHECK-PWR9-LABEL: caller4: ; CHECK-PWR9-LABEL: caller4:
; CHECK-PWR9: # %bb.0: # %entry ; CHECK-PWR9: # %bb.0: # %entry
; CHECK-PWR9-NEXT: mflr r0 ; CHECK-PWR9-NEXT: mflr r0
; CHECK-PWR9-NEXT: std r0, 16(r1)
; CHECK-PWR9-NEXT: stdu r1, -224(r1) ; CHECK-PWR9-NEXT: stdu r1, -224(r1)
; CHECK-PWR9-NEXT: std r0, 240(r1)
; CHECK-PWR9-NEXT: .cfi_def_cfa_offset 224 ; CHECK-PWR9-NEXT: .cfi_def_cfa_offset 224
; CHECK-PWR9-NEXT: .cfi_offset lr, 16 ; CHECK-PWR9-NEXT: .cfi_offset lr, 16
; CHECK-PWR9-NEXT: .cfi_offset v20, -192 ; CHECK-PWR9-NEXT: .cfi_offset v20, -192
; CHECK-PWR9-NEXT: .cfi_offset v21, -176 ; CHECK-PWR9-NEXT: .cfi_offset v21, -176
; CHECK-PWR9-NEXT: stxv v20, 32(r1) # 16-byte Folded Spill ; CHECK-PWR9-NEXT: stxv v20, 32(r1) # 16-byte Folded Spill
; CHECK-PWR9-NEXT: stxv v21, 48(r1) # 16-byte Folded Spill ; CHECK-PWR9-NEXT: stxv v21, 48(r1) # 16-byte Folded Spill
; CHECK-PWR9-NEXT: #APP ; CHECK-PWR9-NEXT: #APP
; CHECK-PWR9-NEXT: add r3, r3, r4 ; CHECK-PWR9-NEXT: add r3, r3, r4
Show All 12 Linesentry:
%call = tail call signext i32 @callee(i32 signext %0) %call = tail call signext i32 @callee(i32 signext %0)
ret i32 %call ret i32 %call
} }
define dso_local signext i32 @caller_mixed(i32 signext %a, i32 signext %b) local_unnamed_addr { define dso_local signext i32 @caller_mixed(i32 signext %a, i32 signext %b) local_unnamed_addr {
; CHECK-PWR8-LABEL: caller_mixed: ; CHECK-PWR8-LABEL: caller_mixed:
; CHECK-PWR8: # %bb.0: # %entry ; CHECK-PWR8: # %bb.0: # %entry
; CHECK-PWR8-NEXT: mflr r0 ; CHECK-PWR8-NEXT: mflr r0
; CHECK-PWR8-NEXT: std r0, 16(r1)
; CHECK-PWR8-NEXT: stdu r1, -528(r1) ; CHECK-PWR8-NEXT: stdu r1, -528(r1)
; CHECK-PWR8-NEXT: std r0, 544(r1)
; CHECK-PWR8-NEXT: .cfi_def_cfa_offset 528 ; CHECK-PWR8-NEXT: .cfi_def_cfa_offset 528
; CHECK-PWR8-NEXT: .cfi_offset lr, 16 ; CHECK-PWR8-NEXT: .cfi_offset lr, 16
; CHECK-PWR8-NEXT: .cfi_offset r14, -288 ; CHECK-PWR8-NEXT: .cfi_offset r14, -288
; CHECK-PWR8-NEXT: .cfi_offset f14, -144 ; CHECK-PWR8-NEXT: .cfi_offset f14, -144
; CHECK-PWR8-NEXT: .cfi_offset v20, -480 ; CHECK-PWR8-NEXT: .cfi_offset v20, -480
; CHECK-PWR8-NEXT: .cfi_offset v21, -464 ; CHECK-PWR8-NEXT: .cfi_offset v21, -464
; CHECK-PWR8-NEXT: li r5, 48 ; CHECK-PWR8-NEXT: li r5, 48
; CHECK-PWR8-NEXT: std r14, 240(r1) # 8-byte Folded Spill ; CHECK-PWR8-NEXT: std r14, 240(r1) # 8-byte Folded Spill
Show All 16 Lines
; CHECK-PWR8-NEXT: addi r1, r1, 528 ; CHECK-PWR8-NEXT: addi r1, r1, 528
; CHECK-PWR8-NEXT: ld r0, 16(r1) ; CHECK-PWR8-NEXT: ld r0, 16(r1)
; CHECK-PWR8-NEXT: mtlr r0 ; CHECK-PWR8-NEXT: mtlr r0
; CHECK-PWR8-NEXT: blr ; CHECK-PWR8-NEXT: blr
; ;
; CHECK-PWR9-LABEL: caller_mixed: ; CHECK-PWR9-LABEL: caller_mixed:
; CHECK-PWR9: # %bb.0: # %entry ; CHECK-PWR9: # %bb.0: # %entry
; CHECK-PWR9-NEXT: mflr r0 ; CHECK-PWR9-NEXT: mflr r0
; CHECK-PWR9-NEXT: std r0, 16(r1)
; CHECK-PWR9-NEXT: stdu r1, -512(r1) ; CHECK-PWR9-NEXT: stdu r1, -512(r1)
; CHECK-PWR9-NEXT: std r0, 528(r1)
; CHECK-PWR9-NEXT: .cfi_def_cfa_offset 512 ; CHECK-PWR9-NEXT: .cfi_def_cfa_offset 512
; CHECK-PWR9-NEXT: .cfi_offset lr, 16 ; CHECK-PWR9-NEXT: .cfi_offset lr, 16
; CHECK-PWR9-NEXT: .cfi_offset r14, -288 ; CHECK-PWR9-NEXT: .cfi_offset r14, -288
; CHECK-PWR9-NEXT: .cfi_offset f14, -144 ; CHECK-PWR9-NEXT: .cfi_offset f14, -144
; CHECK-PWR9-NEXT: .cfi_offset v20, -480 ; CHECK-PWR9-NEXT: .cfi_offset v20, -480
; CHECK-PWR9-NEXT: .cfi_offset v21, -464 ; CHECK-PWR9-NEXT: .cfi_offset v21, -464
; CHECK-PWR9-NEXT: std r14, 224(r1) # 8-byte Folded Spill ; CHECK-PWR9-NEXT: std r14, 224(r1) # 8-byte Folded Spill
; CHECK-PWR9-NEXT: stfd f14, 368(r1) # 8-byte Folded Spill ; CHECK-PWR9-NEXT: stfd f14, 368(r1) # 8-byte Folded Spill
Show All 23 Lines

llvm/test/CodeGen/PowerPC/Frames-dyn-alloca-with-func-call.ll

Show First 20 Lines • Show All 43 Lines • ▼ Show 20 Linesentry:
%call = call i32 @bar(ptr %1, ptr %2, ptr %3, ptr %4, ptr %5, ptr %6, ptr %7, ptr %8, ptr %9) %call = call i32 @bar(ptr %1, ptr %2, ptr %3, ptr %4, ptr %5, ptr %6, ptr %7, ptr %8, ptr %9)
ret i32 %call ret i32 %call
} }
declare i32 @bar(ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr) declare i32 @bar(ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr)
; PPC32-LINUX-LABEL: foo ; PPC32-LINUX-LABEL: foo
; PPC32-LINUX: mflr 0 ; PPC32-LINUX: mflr 0
; PPC32-LINUX: stw 0, 4(1)
; PPC32-LINUX: stwu 1, -32(1) ; PPC32-LINUX: stwu 1, -32(1)
; PPC32-LINUX: stw 31, 28(1) ; PPC32-LINUX: stw 31, 28(1)
; PPC32-LINUX: stw 0, 36(1)
; PPC32-LINUX: mr 31, 1 ; PPC32-LINUX: mr 31, 1
; PPC32-LINUX: addi 3, 31, 32 ; PPC32-LINUX: addi 3, 31, 32
; PPC32-LINUX: stwux 3, 1, 10 ; PPC32-LINUX: stwux 3, 1, 10
; Allocated area is referred by stack pointer. ; Allocated area is referred by stack pointer.
; PPC32-LINUX: addi 11, 1, 16 ; PPC32-LINUX: addi 11, 1, 16
; Local variable area is referred by frame pointer. ; Local variable area is referred by frame pointer.
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; PPC32-LINUX: lwz 0, -4(31) ; PPC32-LINUX: lwz 0, -4(31)
; PPC32-LINUX: mr 1, 31 ; PPC32-LINUX: mr 1, 31
; PPC32-LINUX: mr 31, 0 ; PPC32-LINUX: mr 31, 0
; PPC32-LINUX: lwz 0, 4(1) ; PPC32-LINUX: lwz 0, 4(1)
; PPC32-LINUX: mtlr 0 ; PPC32-LINUX: mtlr 0
; PPC32-LINUX: blr ; PPC32-LINUX: blr
; PPC64-LABEL: foo ; PPC64-LABEL: foo
; PPC64: mflr 0 ; PPC64: mflr 0
; PPC64: std 31, -8(1) ; PPC64: std 31, -8(1)
; PPC64: std 0, 16(1)
; PPC64: stdu 1, -160(1) ; PPC64: stdu 1, -160(1)
; PPC64: mr 31, 1 ; PPC64-DAG: mr 31, 1
; PPC64-DAG: std 0, 176(1)
; PPC64: addi 3, 31, 160 ; PPC64: addi 3, 31, 160
; PPC64: stdux 3, 1, 10 ; PPC64: stdux 3, 1, 10
; Allocated area is referred by stack pointer. ; Allocated area is referred by stack pointer.
; PPC64: addi 11, 1, 128 ; PPC64: addi 11, 1, 128
; Local variable area is referred by frame pointer. ; Local variable area is referred by frame pointer.
; PPC64: std 11, 144(31) ; PPC64: std 11, 144(31)
; PPC64: stdux ; PPC64: stdux
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; PPC64: ld 1, 0(1) ; PPC64: ld 1, 0(1)
; PPC64: ld 0, 16(1) ; PPC64: ld 0, 16(1)
; PPC64-DAG: ld 31, -8(1) ; PPC64-DAG: ld 31, -8(1)
; PPC64-DAG: mtlr 0 ; PPC64-DAG: mtlr 0
; PPC64: blr ; PPC64: blr
; PPC32-AIX: mflr 0 ; PPC32-AIX: mflr 0
; PPC32-AIX: stw 31, -4(1) ; PPC32-AIX: stw 31, -4(1)
; PPC32-AIX: stw 0, 8(1)
; PPC32-AIX: stwu 1, -80(1) ; PPC32-AIX: stwu 1, -80(1)
; PPC32-AIX: mr 31, 1 ; PPC32-AIX: mr 31, 1
; PPC32-AIX: stw 0, 88(1)
; PPC32-AIX: addi 3, 31, 80 ; PPC32-AIX: addi 3, 31, 80
; PPC32-AIX: stwux 3, 1, 10 ; PPC32-AIX: stwux 3, 1, 10
; Allocated area is referred by stack pointer. ; Allocated area is referred by stack pointer.
; PPC32-AIX: addi 11, 1, 64 ; PPC32-AIX: addi 11, 1, 64
; Local variable area is referred by frame pointer. ; Local variable area is referred by frame pointer.
; PPC32-AIX: stw 11, 72(31) ; PPC32-AIX: stw 11, 72(31)
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llvm/test/CodeGen/PowerPC/MCSE-caller-preserved-reg.ll

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@_ZN2CC2ccE = external thread_local global %"struct.CC::TT", align 8 @_ZN2CC2ccE = external thread_local global %"struct.CC::TT", align 8
define noalias ptr @_ZN2CC3funEv(ptr %this) nounwind { define noalias ptr @_ZN2CC3funEv(ptr %this) nounwind {
; CHECK-LABEL: _ZN2CC3funEv: ; CHECK-LABEL: _ZN2CC3funEv:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; CHECK-NEXT: std 30, -16(1) # 8-byte Folded Spill ; CHECK-NEXT: std 30, -16(1) # 8-byte Folded Spill
; CHECK-NEXT: std 0, 16(1)
; CHECK-NEXT: stdu 1, -48(1) ; CHECK-NEXT: stdu 1, -48(1)
; CHECK-NEXT: std 2, 24(1) ; CHECK-NEXT: std 2, 24(1)
; CHECK-NEXT: std 0, 64(1)
; CHECK-NEXT: mr 30, 3 ; CHECK-NEXT: mr 30, 3
; CHECK-NEXT: ld 12, 0(3) ; CHECK-NEXT: ld 12, 0(3)
; CHECK-NEXT: mtctr 12 ; CHECK-NEXT: mtctr 12
; CHECK-NEXT: bctrl ; CHECK-NEXT: bctrl
; CHECK-NEXT: ld 2, 24(1) ; CHECK-NEXT: ld 2, 24(1)
; CHECK-NEXT: addis 3, 2, _ZN2CC2ccE@got@tlsgd@ha ; CHECK-NEXT: addis 3, 2, _ZN2CC2ccE@got@tlsgd@ha
; CHECK-NEXT: addi 3, 3, _ZN2CC2ccE@got@tlsgd@l ; CHECK-NEXT: addi 3, 3, _ZN2CC2ccE@got@tlsgd@l
; CHECK-NEXT: bl __tls_get_addr(_ZN2CC2ccE@tlsgd) ; CHECK-NEXT: bl __tls_get_addr(_ZN2CC2ccE@tlsgd)
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llvm/test/CodeGen/PowerPC/P10-stack-alignment.ll

Show First 20 Lines • Show All 151 Lines • ▼ Show 20 Lines
define dso_local void @test_Array() nounwind { define dso_local void @test_Array() nounwind {
; CHECK-OPT-LABEL: @test_Array( ; CHECK-OPT-LABEL: @test_Array(
; CHECK-OPT-NEXT: entry: ; CHECK-OPT-NEXT: entry:
; CHECK-OPT-NEXT: %Arr2 = alloca [64 x i16], align 2 ; CHECK-OPT-NEXT: %Arr2 = alloca [64 x i16], align 2
; CHECK-OPT: store <16 x i16> [[TMP0:%.*]], ptr [[TMP0:%.*]], align 2 ; CHECK-OPT: store <16 x i16> [[TMP0:%.*]], ptr [[TMP0:%.*]], align 2
; CHECK-LE-LABEL: test_Array: ; CHECK-LE-LABEL: test_Array:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: mflr r0 ; CHECK-LE-NEXT: mflr r0
; CHECK-LE-NEXT: std r0, 16(r1)
; CHECK-LE-NEXT: stdu r1, -176(r1) ; CHECK-LE-NEXT: stdu r1, -176(r1)
; CHECK-LE-NEXT: addis r4, r2, Arr1@toc@ha ; CHECK-LE-NEXT: addis r4, r2, Arr1@toc@ha
; CHECK-LE-NEXT: li r3, 0 ; CHECK-LE-NEXT: li r3, 0
; CHECK-LE-NEXT: std r0, 192(r1)
; CHECK-LE-NEXT: li r6, 65 ; CHECK-LE-NEXT: li r6, 65
; CHECK-LE-NEXT: addi r5, r1, 46 ; CHECK-LE-NEXT: addi r5, r1, 46
; CHECK-LE-NEXT: addi r4, r4, Arr1@toc@l ; CHECK-LE-NEXT: addi r4, r4, Arr1@toc@l
; CHECK-LE-NEXT: stw r3, 44(r1) ; CHECK-LE-NEXT: stw r3, 44(r1)
; CHECK-LE-NEXT: addi r4, r4, -1 ; CHECK-LE-NEXT: addi r4, r4, -1
; CHECK-LE-NEXT: mtctr r6 ; CHECK-LE-NEXT: mtctr r6
; CHECK-LE-NEXT: bdz .LBB2_2 ; CHECK-LE-NEXT: bdz .LBB2_2
; CHECK-LE-NEXT: .p2align 5 ; CHECK-LE-NEXT: .p2align 5
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; CHECK-LE-NEXT: addi r1, r1, 176 ; CHECK-LE-NEXT: addi r1, r1, 176
; CHECK-LE-NEXT: ld r0, 16(r1) ; CHECK-LE-NEXT: ld r0, 16(r1)
; CHECK-LE-NEXT: mtlr r0 ; CHECK-LE-NEXT: mtlr r0
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
; ;
; CHECK-BE-LABEL: test_Array: ; CHECK-BE-LABEL: test_Array:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: mflr r0 ; CHECK-BE-NEXT: mflr r0
; CHECK-BE-NEXT: std r0, 16(r1)
; CHECK-BE-NEXT: stdu r1, -256(r1) ; CHECK-BE-NEXT: stdu r1, -256(r1)
; CHECK-BE-NEXT: addis r5, r2, Arr1@toc@ha ; CHECK-BE-NEXT: addis r5, r2, Arr1@toc@ha
; CHECK-BE-NEXT: li r3, 0 ; CHECK-BE-NEXT: li r3, 0
; CHECK-BE-NEXT: addi r5, r5, Arr1@toc@l ; CHECK-BE-NEXT: addi r5, r5, Arr1@toc@l
; CHECK-BE-NEXT: std r0, 272(r1)
; CHECK-BE-NEXT: addi r4, r1, 126 ; CHECK-BE-NEXT: addi r4, r1, 126
; CHECK-BE-NEXT: li r6, 65 ; CHECK-BE-NEXT: li r6, 65
; CHECK-BE-NEXT: stw r3, 124(r1) ; CHECK-BE-NEXT: stw r3, 124(r1)
; CHECK-BE-NEXT: addi r5, r5, -1 ; CHECK-BE-NEXT: addi r5, r5, -1
; CHECK-BE-NEXT: mtctr r6 ; CHECK-BE-NEXT: mtctr r6
; CHECK-BE-NEXT: bdz .LBB2_2 ; CHECK-BE-NEXT: bdz .LBB2_2
; CHECK-BE-NEXT: .LBB2_1: # %for.body ; CHECK-BE-NEXT: .LBB2_1: # %for.body
; CHECK-BE-NEXT: # ; CHECK-BE-NEXT: #
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llvm/test/CodeGen/PowerPC/PR35812-neg-cmpxchg.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; Make sure that a negative value for the compare-and-swap is zero extended ; Make sure that a negative value for the compare-and-swap is zero extended
; from i8/i16 to i32 since it will be compared for equality. ; from i8/i16 to i32 since it will be compared for equality.
; RUN: llc -mtriple=powerpc64le-linux-gnu -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=powerpc64le-linux-gnu -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=powerpc64le-linux-gnu -mcpu=pwr7 -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-P7 ; RUN: llc -mtriple=powerpc64le-linux-gnu -mcpu=pwr7 -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-P7
@str = private unnamed_addr constant [46 x i8] c"FAILED: __atomic_compare_exchange_n() failed.\00" @str = private unnamed_addr constant [46 x i8] c"FAILED: __atomic_compare_exchange_n() failed.\00"
@str.1 = private unnamed_addr constant [59 x i8] c"FAILED: __atomic_compare_exchange_n() set the wrong value.\00" @str.1 = private unnamed_addr constant [59 x i8] c"FAILED: __atomic_compare_exchange_n() set the wrong value.\00"
@str.2 = private unnamed_addr constant [7 x i8] c"PASSED\00" @str.2 = private unnamed_addr constant [7 x i8] c"PASSED\00"
define signext i32 @main() nounwind { define signext i32 @main() nounwind {
; CHECK-LABEL: main: ; CHECK-LABEL: main:
; CHECK: # %bb.0: # %L.entry ; CHECK: # %bb.0: # %L.entry
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; CHECK-NEXT: std 0, 16(1)
; CHECK-NEXT: stdu 1, -48(1) ; CHECK-NEXT: stdu 1, -48(1)
; CHECK-NEXT: li 3, -32477 ; CHECK-NEXT: li 3, -32477
; CHECK-NEXT: std 0, 64(1)
; CHECK-NEXT: li 4, 234 ; CHECK-NEXT: li 4, 234
; CHECK-NEXT: addi 6, 1, 46 ; CHECK-NEXT: addi 6, 1, 46
; CHECK-NEXT: sth 3, 46(1) ; CHECK-NEXT: sth 3, 46(1)
; CHECK-NEXT: lis 3, 0 ; CHECK-NEXT: lis 3, 0
; CHECK-NEXT: ori 3, 3, 33059 ; CHECK-NEXT: ori 3, 3, 33059
; CHECK-NEXT: sync ; CHECK-NEXT: sync
; CHECK-NEXT: .LBB0_1: # %L.entry ; CHECK-NEXT: .LBB0_1: # %L.entry
; CHECK-NEXT: # ; CHECK-NEXT: #
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; CHECK-NEXT: addi 1, 1, 48 ; CHECK-NEXT: addi 1, 1, 48
; CHECK-NEXT: ld 0, 16(1) ; CHECK-NEXT: ld 0, 16(1)
; CHECK-NEXT: mtlr 0 ; CHECK-NEXT: mtlr 0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P7-LABEL: main: ; CHECK-P7-LABEL: main:
; CHECK-P7: # %bb.0: # %L.entry ; CHECK-P7: # %bb.0: # %L.entry
; CHECK-P7-NEXT: mflr 0 ; CHECK-P7-NEXT: mflr 0
; CHECK-P7-NEXT: std 0, 16(1)
; CHECK-P7-NEXT: stdu 1, -48(1) ; CHECK-P7-NEXT: stdu 1, -48(1)
; CHECK-P7-NEXT: li 3, -32477 ; CHECK-P7-NEXT: li 3, -32477
; CHECK-P7-NEXT: lis 5, 0 ; CHECK-P7-NEXT: lis 5, 0
; CHECK-P7-NEXT: addi 4, 1, 46 ; CHECK-P7-NEXT: addi 4, 1, 46
; CHECK-P7-NEXT: li 7, 0 ; CHECK-P7-NEXT: li 7, 0
; CHECK-P7-NEXT: std 0, 64(1)
; CHECK-P7-NEXT: sth 3, 46(1) ; CHECK-P7-NEXT: sth 3, 46(1)
; CHECK-P7-NEXT: li 6, 234 ; CHECK-P7-NEXT: li 6, 234
; CHECK-P7-NEXT: ori 5, 5, 33059
; CHECK-P7-NEXT: rlwinm 3, 4, 3, 27, 27 ; CHECK-P7-NEXT: rlwinm 3, 4, 3, 27, 27
; CHECK-P7-NEXT: ori 5, 5, 33059
; CHECK-P7-NEXT: ori 7, 7, 65535 ; CHECK-P7-NEXT: ori 7, 7, 65535
; CHECK-P7-NEXT: sync ; CHECK-P7-NEXT: sync
; CHECK-P7-NEXT: slw 6, 6, 3 ; CHECK-P7-NEXT: slw 6, 6, 3
; CHECK-P7-NEXT: slw 8, 5, 3 ; CHECK-P7-NEXT: slw 8, 5, 3
; CHECK-P7-NEXT: slw 5, 7, 3 ; CHECK-P7-NEXT: slw 5, 7, 3
; CHECK-P7-NEXT: rldicr 4, 4, 0, 61 ; CHECK-P7-NEXT: rldicr 4, 4, 0, 61
; CHECK-P7-NEXT: and 6, 6, 5 ; CHECK-P7-NEXT: and 6, 6, 5
; CHECK-P7-NEXT: and 7, 8, 5 ; CHECK-P7-NEXT: and 7, 8, 5
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llvm/test/CodeGen/PowerPC/aix-cc-abi.ll

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; 32BIT-DAG: $f13 = COPY renamable $f1 ; 32BIT-DAG: $f13 = COPY renamable $f1
; 32BIT-NEXT: BL_NOP <mcsymbol .test_fpr_max>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $f1, implicit killed $f2, implicit killed $f3, implicit killed $f4, implicit killed $f5, implicit killed $f6, implicit killed $f7, implicit killed $f8, implicit killed $f9, implicit killed $f10, implicit killed $f11, implicit killed $f12, implicit killed $f13, implicit $r2, implicit-def $r1, implicit-def dead $f1 ; 32BIT-NEXT: BL_NOP <mcsymbol .test_fpr_max>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $f1, implicit killed $f2, implicit killed $f3, implicit killed $f4, implicit killed $f5, implicit killed $f6, implicit killed $f7, implicit killed $f8, implicit killed $f9, implicit killed $f10, implicit killed $f11, implicit killed $f12, implicit killed $f13, implicit $r2, implicit-def $r1, implicit-def dead $f1
; 32BIT-NEXT: ADJCALLSTACKUP 128, 0, implicit-def dead $r1, implicit $r1 ; 32BIT-NEXT: ADJCALLSTACKUP 128, 0, implicit-def dead $r1, implicit $r1
; CHECKASM-LABEL: .call_test_fpr_max: ; CHECKASM-LABEL: .call_test_fpr_max:
; ASM32PWR4: stwu 1, -128(1) ; ASM32PWR4: stwu 1, -128(1)
; ASM32PWR4-NEXT: lwz [[REG:[0-9]+]], L..C2(2) ; ASM32PWR4-NEXT: lwz [[REG:[0-9]+]], L..C2(2)
; ASM32PWR4-NEXT: stw 0, 136(1)
; ASM32PWR4-NEXT: lfd 1, 0([[REG]]) ; ASM32PWR4-NEXT: lfd 1, 0([[REG]])
; ASM32PWR4-DAG: stfd 1, 56(1) ; ASM32PWR4-DAG: stfd 1, 56(1)
; ASM32PWR4-DAG: stfd 1, 64(1) ; ASM32PWR4-DAG: stfd 1, 64(1)
; ASM32PWR4-DAG: stfd 1, 72(1) ; ASM32PWR4-DAG: stfd 1, 72(1)
; ASM32PWR4-DAG: stfd 1, 80(1) ; ASM32PWR4-DAG: stfd 1, 80(1)
; ASM32PWR4-DAG: stfd 1, 88(1) ; ASM32PWR4-DAG: stfd 1, 88(1)
; ASM32PWR4-DAG: stfd 1, 96(1) ; ASM32PWR4-DAG: stfd 1, 96(1)
; ASM32PWR4-DAG: stfd 1, 104(1) ; ASM32PWR4-DAG: stfd 1, 104(1)
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; 64BIT-DAG: $f11 = COPY renamable $f1 ; 64BIT-DAG: $f11 = COPY renamable $f1
; 64BIT-DAG: $f12 = COPY renamable $f1 ; 64BIT-DAG: $f12 = COPY renamable $f1
; 64BIT-DAG: $f13 = COPY renamable $f1 ; 64BIT-DAG: $f13 = COPY renamable $f1
; 64BIT-NEXT: BL8_NOP <mcsymbol .test_fpr_max>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $f1, implicit killed $f2, implicit killed $f3, implicit killed $f4, implicit killed $f5, implicit killed $f6, implicit killed $f7, implicit killed $f8, implicit killed $f9, implicit killed $f10, implicit killed $f11, implicit killed $f12, implicit killed $f13, implicit $x2, implicit-def $r1 ; 64BIT-NEXT: BL8_NOP <mcsymbol .test_fpr_max>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $f1, implicit killed $f2, implicit killed $f3, implicit killed $f4, implicit killed $f5, implicit killed $f6, implicit killed $f7, implicit killed $f8, implicit killed $f9, implicit killed $f10, implicit killed $f11, implicit killed $f12, implicit killed $f13, implicit $x2, implicit-def $r1
; 64BIT-NEXT: ADJCALLSTACKUP 152, 0, implicit-def dead $r1, implicit $r1 ; 64BIT-NEXT: ADJCALLSTACKUP 152, 0, implicit-def dead $r1, implicit $r1
; ASM64PWR4: stdu 1, -160(1) ; ASM64PWR4: stdu 1, -160(1)
; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], L..C2(2) ; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], L..C2(2)
; ASM64PWR4-NEXT: std 0, 176(1)
; ASM64PWR4-NEXT: lfd 1, 0([[REG]]) ; ASM64PWR4-NEXT: lfd 1, 0([[REG]])
; ASM64PWR4-DAG: stfd 1, 112(1) ; ASM64PWR4-DAG: stfd 1, 112(1)
; ASM64PWR4-DAG: stfd 1, 120(1) ; ASM64PWR4-DAG: stfd 1, 120(1)
; ASM64PWR4-DAG: stfd 1, 128(1) ; ASM64PWR4-DAG: stfd 1, 128(1)
; ASM64PWR4-DAG: stfd 1, 136(1) ; ASM64PWR4-DAG: stfd 1, 136(1)
; ASM64PWR4-DAG: stfd 1, 144(1) ; ASM64PWR4-DAG: stfd 1, 144(1)
; ASM64PWR4-DAG: fmr 2, 1 ; ASM64PWR4-DAG: fmr 2, 1
; ASM64PWR4-DAG: fmr 3, 1 ; ASM64PWR4-DAG: fmr 3, 1
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; 32BIT-NEXT: $r3 = LI 42 ; 32BIT-NEXT: $r3 = LI 42
; 32BIT-NEXT: BL_NOP <mcsymbol .test_vararg[PR]>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $f1, implicit $r4, implicit $r5, implicit $f2, implicit $r6, implicit $r7, implicit $r2, implicit-def $r1 ; 32BIT-NEXT: BL_NOP <mcsymbol .test_vararg[PR]>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $f1, implicit $r4, implicit $r5, implicit $f2, implicit $r6, implicit $r7, implicit $r2, implicit-def $r1
; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1 ; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
; CHECKASM-LABEL: .call_test_vararg: ; CHECKASM-LABEL: .call_test_vararg:
; ASM32PWR4: stwu 1, -80(1) ; ASM32PWR4: stwu 1, -80(1)
; ASM32PWR4-NEXT: lwz [[REG:[0-9]+]], L..C1(2) ; ASM32PWR4-NEXT: lwz [[REG:[0-9]+]], L..C1(2)
; ASM32PWR4-NEXT: stw 0, 88(1)
; ASM32PWR4-NEXT: lfs 1, 0([[REG]]) ; ASM32PWR4-NEXT: lfs 1, 0([[REG]])
; ASM32PWR4-NEXT: lwz [[REG:[0-9]+]], L..C2(2) ; ASM32PWR4-NEXT: lwz [[REG:[0-9]+]], L..C2(2)
; ASM32PWR4-NEXT: stfd 1, 64(1) ; ASM32PWR4-NEXT: stfd 1, 64(1)
; ASM32PWR4-NEXT: lfd 2, 0([[REG]]) ; ASM32PWR4-NEXT: lfd 2, 0([[REG]])
; ASM32PWR4-NEXT: li 3, 42 ; ASM32PWR4-NEXT: li 3, 42
; ASM32PWR4-NEXT: stfd 2, 72(1) ; ASM32PWR4-NEXT: stfd 2, 72(1)
; ASM32PWR4-DAG: lwz 4, 64(1) ; ASM32PWR4-DAG: lwz 4, 64(1)
; ASM32PWR4-DAG: lwz 5, 68(1) ; ASM32PWR4-DAG: lwz 5, 68(1)
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; 64BIT-NEXT: renamable $x5 = LD 0, %stack.[[SLOT2]] :: (load (s64) from %stack.[[SLOT2]]) ; 64BIT-NEXT: renamable $x5 = LD 0, %stack.[[SLOT2]] :: (load (s64) from %stack.[[SLOT2]])
; 64BIT-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1 ; 64BIT-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
; 64BIT-NEXT: $x3 = LI8 42 ; 64BIT-NEXT: $x3 = LI8 42
; 64BIT-NEXT: BL8_NOP <mcsymbol .test_vararg[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $f1, implicit $x4, implicit $f2, implicit $x5, implicit $x2, implicit-def $r1 ; 64BIT-NEXT: BL8_NOP <mcsymbol .test_vararg[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $f1, implicit $x4, implicit $f2, implicit $x5, implicit $x2, implicit-def $r1
; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 ; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
; ASM64PWR4: stdu 1, -128(1) ; ASM64PWR4: stdu 1, -128(1)
; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], L..C1(2) ; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], L..C1(2)
; ASM64PWR4-NEXT: std 0, 144(1)
; ASM64PWR4-NEXT: lfs 1, 0([[REG]]) ; ASM64PWR4-NEXT: lfs 1, 0([[REG]])
; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], L..C2(2) ; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], L..C2(2)
; ASM64PWR4-NEXT: stfd 1, 112(1) ; ASM64PWR4-NEXT: stfd 1, 112(1)
; ASM64PWR4-NEXT: lfd 2, 0([[REG]]) ; ASM64PWR4-NEXT: lfd 2, 0([[REG]])
; ASM64PWR4-NEXT: li 3, 42 ; ASM64PWR4-NEXT: li 3, 42
; ASM64PWR4-NEXT: stfd 2, 120(1) ; ASM64PWR4-NEXT: stfd 2, 120(1)
; ASM64PWR4-NEXT: ld 4, 112(1) ; ASM64PWR4-NEXT: ld 4, 112(1)
; ASM64PWR4-NEXT: ld 5, 120(1) ; ASM64PWR4-NEXT: ld 5, 120(1)
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; 32BIT-NEXT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1 ; 32BIT-NEXT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
; 32BIT-NEXT: $r3 = LI 42 ; 32BIT-NEXT: $r3 = LI 42
; 32BIT-NEXT: $r6 = LI 42 ; 32BIT-NEXT: $r6 = LI 42
; 32BIT-NEXT: BL_NOP <mcsymbol .test_vararg[PR]>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $f1, implicit $r4, implicit $r5, implicit killed $r6, implicit $f2, implicit $r7, implicit $r8, implicit $r2, implicit-def $r1 ; 32BIT-NEXT: BL_NOP <mcsymbol .test_vararg[PR]>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $f1, implicit $r4, implicit $r5, implicit killed $r6, implicit $f2, implicit $r7, implicit $r8, implicit $r2, implicit-def $r1
; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1 ; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
; ASM32PWR4: stwu 1, -80(1) ; ASM32PWR4: stwu 1, -80(1)
; ASM32PWR4-NEXT: lwz [[REG:[0-9]+]], L..C1(2) ; ASM32PWR4-NEXT: lwz [[REG:[0-9]+]], L..C1(2)
; ASM32PWR4-NEXT: stw 0, 88(1)
; ASM32PWR4-NEXT: li 6, 42 ; ASM32PWR4-NEXT: li 6, 42
; ASM32PWR4-NEXT: lfs 1, 0([[REG]]) ; ASM32PWR4-NEXT: lfs 1, 0([[REG]])
; ASM32PWR4-NEXT: lwz [[REG:[0-9]+]], L..C2(2) ; ASM32PWR4-NEXT: lwz [[REG:[0-9]+]], L..C2(2)
; ASM32PWR4-NEXT: stfd 1, 64(1) ; ASM32PWR4-NEXT: stfd 1, 64(1)
; ASM32PWR4-NEXT: lfd 2, 0([[REG]]) ; ASM32PWR4-NEXT: lfd 2, 0([[REG]])
; ASM32PWR4-NEXT: li 3, 42 ; ASM32PWR4-NEXT: li 3, 42
; ASM32PWR4-NEXT: stfd 2, 72(1) ; ASM32PWR4-NEXT: stfd 2, 72(1)
; ASM32PWR4-DAG: lwz 4, 64(1) ; ASM32PWR4-DAG: lwz 4, 64(1)
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; 64BIT-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1 ; 64BIT-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
; 64BIT-NEXT: $x3 = LI8 42 ; 64BIT-NEXT: $x3 = LI8 42
; 64BIT-NEXT: $x5 = LI8 42 ; 64BIT-NEXT: $x5 = LI8 42
; 64BIT-NEXT: BL8_NOP <mcsymbol .test_vararg[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $f1, implicit $x4, implicit killed $x5, implicit $f2, implicit $x6, implicit $x2, implicit-def $r1 ; 64BIT-NEXT: BL8_NOP <mcsymbol .test_vararg[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $f1, implicit $x4, implicit killed $x5, implicit $f2, implicit $x6, implicit $x2, implicit-def $r1
; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 ; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
; ASM64PWR4: stdu 1, -128(1) ; ASM64PWR4: stdu 1, -128(1)
; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], L..C1(2) ; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], L..C1(2)
; ASM64PWR4-NEXT: std 0, 144(1)
; ASM64PWR4-NEXT: li 5, 42 ; ASM64PWR4-NEXT: li 5, 42
; ASM64PWR4-NEXT: lfs 1, 0([[REG]]) ; ASM64PWR4-NEXT: lfs 1, 0([[REG]])
; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], L..C2(2) ; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], L..C2(2)
; ASM64PWR4-NEXT: stfd 1, 112(1) ; ASM64PWR4-NEXT: stfd 1, 112(1)
; ASM64PWR4-NEXT: lfd 2, 0([[REG]]) ; ASM64PWR4-NEXT: lfd 2, 0([[REG]])
; ASM64PWR4-NEXT: li 3, 42 ; ASM64PWR4-NEXT: li 3, 42
; ASM64PWR4-NEXT: stfd 2, 120(1) ; ASM64PWR4-NEXT: stfd 2, 120(1)
; ASM64PWR4-NEXT: ld 4, 112(1) ; ASM64PWR4-NEXT: ld 4, 112(1)
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; 64BIT-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1 ; 64BIT-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
; 64BIT-NEXT: $x3 = LI8 42 ; 64BIT-NEXT: $x3 = LI8 42
; 64BIT-NEXT: $x5 = LI8 42 ; 64BIT-NEXT: $x5 = LI8 42
; 64BIT-NEXT: BL8_NOP <mcsymbol .test_vararg[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $f1, implicit $x4, implicit killed $x5, implicit $f2, implicit $x6, implicit $x2, implicit-def $r1 ; 64BIT-NEXT: BL8_NOP <mcsymbol .test_vararg[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $f1, implicit $x4, implicit killed $x5, implicit $f2, implicit $x6, implicit $x2, implicit-def $r1
; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 ; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
; ASM64PWR4: stdu 1, -128(1) ; ASM64PWR4: stdu 1, -128(1)
; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], L..C1(2) ; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], L..C1(2)
; ASM64PWR4-NEXT: std 0, 144(1)
; ASM64PWR4-NEXT: li 5, 42 ; ASM64PWR4-NEXT: li 5, 42
; ASM64PWR4-NEXT: lfs 1, 0([[REG]]) ; ASM64PWR4-NEXT: lfs 1, 0([[REG]])
; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], L..C2(2) ; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], L..C2(2)
; ASM64PWR4-NEXT: stfd 1, 112(1) ; ASM64PWR4-NEXT: stfd 1, 112(1)
; ASM64PWR4-NEXT: lfd 2, 0([[REG]]) ; ASM64PWR4-NEXT: lfd 2, 0([[REG]])
; ASM64PWR4-NEXT: li 3, 42 ; ASM64PWR4-NEXT: li 3, 42
; ASM64PWR4-NEXT: stfd 2, 120(1) ; ASM64PWR4-NEXT: stfd 2, 120(1)
; ASM64PWR4-DAG: ld 4, 112(1) ; ASM64PWR4-DAG: ld 4, 112(1)
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; 32BIT-NEXT: renamable $r4 = LWZ 0, %stack.[[SLOT]] :: (load (s32) from %stack.[[SLOT]]) ; 32BIT-NEXT: renamable $r4 = LWZ 0, %stack.[[SLOT]] :: (load (s32) from %stack.[[SLOT]])
; 32BIT-NEXT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1 ; 32BIT-NEXT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
; 32BIT-NEXT: $r3 = LI 42 ; 32BIT-NEXT: $r3 = LI 42
; 32BIT-NEXT: BL_NOP <mcsymbol .test_vararg[PR]>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $f1, implicit $r4, implicit $r2, implicit-def $r1 ; 32BIT-NEXT: BL_NOP <mcsymbol .test_vararg[PR]>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $f1, implicit $r4, implicit $r2, implicit-def $r1
; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1 ; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
; ASM32PWR4: stwu 1, -64(1) ; ASM32PWR4: stwu 1, -64(1)
; ASM32PWR4-NEXT: lwz [[REG:[0-9]+]], L..C1(2) ; ASM32PWR4-NEXT: lwz [[REG:[0-9]+]], L..C1(2)
; ASM32PWR4-NEXT: stw 0, 72(1)
; ASM32PWR4-NEXT: lfs 1, 0([[REG]]) ; ASM32PWR4-NEXT: lfs 1, 0([[REG]])
; ASM32PWR4-NEXT: li 3, 42 ; ASM32PWR4-NEXT: li 3, 42
; ASM32PWR4-NEXT: stfs 1, 60(1) ; ASM32PWR4-NEXT: stfs 1, 60(1)
; ASM32PWR4-NEXT: lwz 4, 60(1) ; ASM32PWR4-NEXT: lwz 4, 60(1)
; ASM32PWR4-NEXT: bl .test_vararg[PR] ; ASM32PWR4-NEXT: bl .test_vararg[PR]
; ASM32PWR4-NEXT: nop ; ASM32PWR4-NEXT: nop
; 64BIT: renamable $x[[REG:[0-9]+]] = LDtoc @f1, $x2 :: (load (s64) from got) ; 64BIT: renamable $x[[REG:[0-9]+]] = LDtoc @f1, $x2 :: (load (s64) from got)
; 64BIT-NEXT: renamable $f1 = LFS 0, killed renamable $x[[REG]] :: (dereferenceable load (s32) from @f1) ; 64BIT-NEXT: renamable $f1 = LFS 0, killed renamable $x[[REG]] :: (dereferenceable load (s32) from @f1)
; 64BIT-NEXT: STFS renamable $f1, 0, %stack.[[SLOT:[0-9]+]] :: (store (s32) into %stack.[[SLOT]]) ; 64BIT-NEXT: STFS renamable $f1, 0, %stack.[[SLOT:[0-9]+]] :: (store (s32) into %stack.[[SLOT]])
; 64BIT-NEXT: renamable $x4 = LWZ8 0, %stack.[[SLOT]] :: (load (s32) from %stack.[[SLOT]]) ; 64BIT-NEXT: renamable $x4 = LWZ8 0, %stack.[[SLOT]] :: (load (s32) from %stack.[[SLOT]])
; 64BIT-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1 ; 64BIT-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
; 64BIT-NEXT: $x3 = LI8 42 ; 64BIT-NEXT: $x3 = LI8 42
; 64BIT-NEXT: BL8_NOP <mcsymbol .test_vararg[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $f1, implicit $x4, implicit $x2, implicit-def $r1 ; 64BIT-NEXT: BL8_NOP <mcsymbol .test_vararg[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $f1, implicit $x4, implicit $x2, implicit-def $r1
; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 ; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
; ASM64PWR4: stdu 1, -128(1) ; ASM64PWR4: stdu 1, -128(1)
; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], L..C1(2) ; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], L..C1(2)
; ASM64PWR4-NEXT: std 0, 144(1)
; ASM64PWR4-NEXT: lfs 1, 0([[REG]]) ; ASM64PWR4-NEXT: lfs 1, 0([[REG]])
; ASM64PWR4-NEXT: li 3, 42 ; ASM64PWR4-NEXT: li 3, 42
; ASM64PWR4-NEXT: stfs 1, 124(1) ; ASM64PWR4-NEXT: stfs 1, 124(1)
; ASM64PWR4-NEXT: lwz 4, 124(1) ; ASM64PWR4-NEXT: lwz 4, 124(1)
; ASM64PWR4-NEXT: bl .test_vararg[PR] ; ASM64PWR4-NEXT: bl .test_vararg[PR]
; ASM64PWR4-NEXT: nop ; ASM64PWR4-NEXT: nop
@c = common global i8 0, align 1 @c = common global i8 0, align 1
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; 64BIT-DAG: ADJCALLSTACKDOWN 176, 0, implicit-def dead $r1, implicit $r1 ; 64BIT-DAG: ADJCALLSTACKDOWN 176, 0, implicit-def dead $r1, implicit $r1
; 64BIT-NEXT: BL8_NOP <mcsymbol .test_ints_stack>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x7, implicit $x8, implicit $x9, implicit $x10, implicit $x2, implicit-def $r1, implicit-def dead $x3 ; 64BIT-NEXT: BL8_NOP <mcsymbol .test_ints_stack>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x7, implicit $x8, implicit $x9, implicit $x10, implicit $x2, implicit-def $r1, implicit-def dead $x3
; 64BIT-NEXT: ADJCALLSTACKUP 176, 0, implicit-def dead $r1, implicit $r1 ; 64BIT-NEXT: ADJCALLSTACKUP 176, 0, implicit-def dead $r1, implicit $r1
; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm ; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm
; CHECKASM-LABEL: .caller_ints_stack: ; CHECKASM-LABEL: .caller_ints_stack:
; ASM32PWR4: mflr 0 ; ASM32PWR4: mflr 0
; ASM32PWR4-DAG: stw 0, 8(1) ; ASM32PWR4-NEXT: stwu 1, -96(1)
; ASM32PWR4-DAG: stwu 1, -96(1) ; ASM32PWR4-DAG: stw 0, 104(1)
; ASM32PWR4-DAG: li 3, 1 ; ASM32PWR4-DAG: li 3, 1
; ASM32PWR4-DAG: li 4, 2 ; ASM32PWR4-DAG: li 4, 2
; ASM32PWR4-DAG: li 5, 3 ; ASM32PWR4-DAG: li 5, 3
; ASM32PWR4-DAG: li 6, 4 ; ASM32PWR4-DAG: li 6, 4
; ASM32PWR4-DAG: li 7, 5 ; ASM32PWR4-DAG: li 7, 5
; ASM32PWR4-DAG: li 9, 7 ; ASM32PWR4-DAG: li 9, 7
; ASM32PWR4-DAG: li 8, 6 ; ASM32PWR4-DAG: li 8, 6
; ASM32PWR4-DAG: li 10, 8 ; ASM32PWR4-DAG: li 10, 8
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; ASM32PWR4-DAG: bl .test_ints_stack ; ASM32PWR4-DAG: bl .test_ints_stack
; ASM32PWR4-DAG: nop ; ASM32PWR4-DAG: nop
; ASM32PWR4-DAG: addi 1, 1, 96 ; ASM32PWR4-DAG: addi 1, 1, 96
; ASM32PWR4-DAG: lwz 0, 8(1) ; ASM32PWR4-DAG: lwz 0, 8(1)
; ASM32PWR4-NEXT: mtlr 0 ; ASM32PWR4-NEXT: mtlr 0
; ASM32PWR4-NEXT: blr ; ASM32PWR4-NEXT: blr
; ASM64PWR4: mflr 0 ; ASM64PWR4: mflr 0
; ASM64PWR4-DAG: std 0, 16(1) ; ASM64PWR4-NEXT: stdu 1, -176(1)
; ASM64PWR4-DAG: stdu 1, -176(1) ; ASM64PWR4-DAG: std 0, 192(1)
; ASM64PWR4-DAG: li 3, 1 ; ASM64PWR4-DAG: li 3, 1
; ASM64PWR4-DAG: li 4, 2 ; ASM64PWR4-DAG: li 4, 2
; ASM64PWR4-DAG: li 5, 3 ; ASM64PWR4-DAG: li 5, 3
; ASM64PWR4-DAG: li 6, 4 ; ASM64PWR4-DAG: li 6, 4
; ASM64PWR4-DAG: li 7, 5 ; ASM64PWR4-DAG: li 7, 5
; ASM64PWR4-DAG: li 8, 6 ; ASM64PWR4-DAG: li 8, 6
; ASM64PWR4-DAG: li 9, 7 ; ASM64PWR4-DAG: li 9, 7
; ASM64PWR4-DAG: li 10, 8 ; ASM64PWR4-DAG: li 10, 8
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; 64BIT-DAG: renamable $f13 = LFD 0, killed renamable $x[[SCRATCHREG:[0-9]+]] :: (load (s64) from constant-pool) ; 64BIT-DAG: renamable $f13 = LFD 0, killed renamable $x[[SCRATCHREG:[0-9]+]] :: (load (s64) from constant-pool)
; 64BIT-DAG: BL8_NOP <mcsymbol .test_fpr_stack>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $f1, implicit $f2, implicit $f3, implicit $f4, implicit $f5, implicit $f6, implicit $f7, implicit $f8, implicit $f9, implicit killed $f10, implicit $f11, implicit $f12, implicit $f13, implicit $x2, implicit-def $r1, implicit-def dead $f1 ; 64BIT-DAG: BL8_NOP <mcsymbol .test_fpr_stack>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $f1, implicit $f2, implicit $f3, implicit $f4, implicit $f5, implicit $f6, implicit $f7, implicit $f8, implicit $f9, implicit killed $f10, implicit $f11, implicit $f12, implicit $f13, implicit $x2, implicit-def $r1, implicit-def dead $f1
; 64BIT-NEXT: ADJCALLSTACKUP 176, 0, implicit-def dead $r1, implicit $r1 ; 64BIT-NEXT: ADJCALLSTACKUP 176, 0, implicit-def dead $r1, implicit $r1
; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm ; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm
; CHECKASM-LABEL: .caller_fpr_stack: ; CHECKASM-LABEL: .caller_fpr_stack:
; ASM32PWR4: mflr 0 ; ASM32PWR4: mflr 0
; ASM32PWR4-DAG: stw 0, 8(1) ; ASM32PWR4-NEXT: stwu 1, -144(1)
; ASM32PWR4-DAG: stwu 1, -144(1) ; ASM32PWR4-DAG: stw 0, 152(1)
; ASM32PWR4-DAG: lwz [[REGF1ADDR:[0-9]+]], L..C20(2) ; ASM32PWR4-DAG: lwz [[REGF1ADDR:[0-9]+]], L..C20(2)
; ASM32PWR4-DAG: lwz [[REGF1:[0-9]+]], 0([[REGF1ADDR]]) ; ASM32PWR4-DAG: lwz [[REGF1:[0-9]+]], 0([[REGF1ADDR]])
; ASM32PWR4-DAG: lwz [[REGDADDR:[0-9]+]], L..C19(2) ; ASM32PWR4-DAG: lwz [[REGDADDR:[0-9]+]], L..C19(2)
; ASM32PWR4-DAG: lfd [[REGD:[0-9]+]], 0([[REGDADDR]]) ; ASM32PWR4-DAG: lfd [[REGD:[0-9]+]], 0([[REGDADDR]])
; ASM32PWR4-DAG: lwz [[REGF2ADDR:[0-9]+]], L..C21(2) ; ASM32PWR4-DAG: lwz [[REGF2ADDR:[0-9]+]], L..C21(2)
; ASM32PWR4-DAG: lwz [[REGF2:[0-9]+]], 0([[REGF2ADDR]]) ; ASM32PWR4-DAG: lwz [[REGF2:[0-9]+]], 0([[REGF2ADDR]])
; ASM32PWR4-DAG: stw [[SCRATCHREG:[0-9]+]], 56(1) ; ASM32PWR4-DAG: stw [[SCRATCHREG:[0-9]+]], 56(1)
; ASM32PWR4-DAG: stw [[SCRATCHREG:[0-9]+]], 60(1) ; ASM32PWR4-DAG: stw [[SCRATCHREG:[0-9]+]], 60(1)
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; ASM32PWR4-DAG: stw [[SCRATCHREG:[0-9]+]], 120(1) ; ASM32PWR4-DAG: stw [[SCRATCHREG:[0-9]+]], 120(1)
; ASM32PWR4-DAG: stw [[SCRATCHREG:[0-9]+]], 124(1) ; ASM32PWR4-DAG: stw [[SCRATCHREG:[0-9]+]], 124(1)
; ASM32PWR4-DAG: stw [[REGF1]], 128(1) ; ASM32PWR4-DAG: stw [[REGF1]], 128(1)
; ASM32PWR4-DAG: stfd [[REGD]], 132(1) ; ASM32PWR4-DAG: stfd [[REGD]], 132(1)
; ASM32PWR4-DAG: stw [[REGF2]], 140(1) ; ASM32PWR4-DAG: stw [[REGF2]], 140(1)
; ASM32PWR4-NEXT: bl .test_fpr_stack ; ASM32PWR4-NEXT: bl .test_fpr_stack
; ASM64PWR4: mflr 0 ; ASM64PWR4: mflr 0
; ASM64PWR4-DAG: std 0, 16(1) ; ASM64PWR4-NEXT: stdu 1, -176(1)
; ASM64PWR4-DAG: stdu 1, -176(1) ; ASM64PWR4-DAG: std 0, 192(1)
; ASM64PWR4-DAG: ld [[REGF1ADDR:[0-9]+]], L..C18(2) ; ASM64PWR4-DAG: ld [[REGF1ADDR:[0-9]+]], L..C18(2)
; ASM64PWR4-DAG: lwz [[REGF1:[0-9]+]], 0([[REGF1ADDR]]) ; ASM64PWR4-DAG: lwz [[REGF1:[0-9]+]], 0([[REGF1ADDR]])
; ASM64PWR4-DAG: ld [[REGDADDR:[0-9]+]], L..C19(2) ; ASM64PWR4-DAG: ld [[REGDADDR:[0-9]+]], L..C19(2)
; ASM64PWR4-DAG: ld [[REGD:[0-9]+]], 0([[REGDADDR]]) ; ASM64PWR4-DAG: ld [[REGD:[0-9]+]], 0([[REGDADDR]])
; ASM64PWR4-DAG: ld [[REGF2ADDR:[0-9]+]], L..C20(2) ; ASM64PWR4-DAG: ld [[REGF2ADDR:[0-9]+]], L..C20(2)
; ASM64PWR4-DAG: lwz [[REGF2:[0-9]+]], 0([[REGF2ADDR]]) ; ASM64PWR4-DAG: lwz [[REGF2:[0-9]+]], 0([[REGF2ADDR]])
; ASM64PWR4-DAG: std [[SCRATCHREG:[0-9]+]], 112(1) ; ASM64PWR4-DAG: std [[SCRATCHREG:[0-9]+]], 112(1)
; ASM64PWR4-DAG: std [[SCRATCHREG:[0-9]+]], 120(1) ; ASM64PWR4-DAG: std [[SCRATCHREG:[0-9]+]], 120(1)
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; 64BIT-DAG: STD killed renamable $x[[REG14:[0-9]+]], 208, $x1 :: (store (s64)) ; 64BIT-DAG: STD killed renamable $x[[REG14:[0-9]+]], 208, $x1 :: (store (s64))
; 64BIT-DAG: STD killed renamable $x[[REG15:[0-9]+]], 216, $x1 :: (store (s64)) ; 64BIT-DAG: STD killed renamable $x[[REG15:[0-9]+]], 216, $x1 :: (store (s64))
; 64BIT-DAG: BL8_NOP <mcsymbol .mix_floats>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x7, implicit $x8, implicit $x9, implicit $x10, implicit $f1, implicit $f2, implicit $f3, implicit $f4, implicit $f5, implicit $f6, implicit $f7, implicit $f8, implicit $f9, implicit $f10, implicit $f11, implicit $f12, implicit $f13, implicit $x2, implicit-def $r1, implicit-def dead $x3 ; 64BIT-DAG: BL8_NOP <mcsymbol .mix_floats>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x7, implicit $x8, implicit $x9, implicit $x10, implicit $f1, implicit $f2, implicit $f3, implicit $f4, implicit $f5, implicit $f6, implicit $f7, implicit $f8, implicit $f9, implicit $f10, implicit $f11, implicit $f12, implicit $f13, implicit $x2, implicit-def $r1, implicit-def dead $x3
; 64BIT-NEXT: ADJCALLSTACKUP 224, 0, implicit-def dead $r1, implicit $r1 ; 64BIT-NEXT: ADJCALLSTACKUP 224, 0, implicit-def dead $r1, implicit $r1
; CHEKASM-LABEL: .mix_floats_caller: ; CHEKASM-LABEL: .mix_floats_caller:
; ASM32PWR4: mflr 0 ; ASM32PWR4: mflr 0
; ASM32PWR4-DAG: stw 0, 8(1) ; ASM32PWR4-NEXT: stwu 1, -176(1)
; ASM32PWR4-DAG: stwu 1, -176(1) ; ASM32PWR4-DAG: stw 0, 184(1)
; ASM32PWR4-DAG: stw [[REG:[0-9]+]], 56(1) ; ASM32PWR4-DAG: stw [[REG:[0-9]+]], 56(1)
; ASM32PWR4-DAG: stw [[REG:[0-9]+]], 60(1) ; ASM32PWR4-DAG: stw [[REG:[0-9]+]], 60(1)
; ASM32PWR4-DAG: stw [[REG:[0-9]+]], 64(1) ; ASM32PWR4-DAG: stw [[REG:[0-9]+]], 64(1)
; ASM32PWR4-DAG: stw [[REG:[0-9]+]], 68(1) ; ASM32PWR4-DAG: stw [[REG:[0-9]+]], 68(1)
; ASM32PWR4-DAG: stw [[REG:[0-9]+]], 72(1) ; ASM32PWR4-DAG: stw [[REG:[0-9]+]], 72(1)
; ASM32PWR4-DAG: stw [[REG:[0-9]+]], 76(1) ; ASM32PWR4-DAG: stw [[REG:[0-9]+]], 76(1)
; ASM32PWR4-DAG: stw [[REG:[0-9]+]], 80(1) ; ASM32PWR4-DAG: stw [[REG:[0-9]+]], 80(1)
; ASM32PWR4-DAG: stw [[REG:[0-9]+]], 84(1) ; ASM32PWR4-DAG: stw [[REG:[0-9]+]], 84(1)
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; ASM32PWR4-DAG: stw [[REG:[0-9]+]], 148(1) ; ASM32PWR4-DAG: stw [[REG:[0-9]+]], 148(1)
; ASM32PWR4-DAG: stw [[REG:[0-9]+]], 152(1) ; ASM32PWR4-DAG: stw [[REG:[0-9]+]], 152(1)
; ASM32PWR4-DAG: stw [[REG:[0-9]+]], 156(1) ; ASM32PWR4-DAG: stw [[REG:[0-9]+]], 156(1)
; ASM32PWR4-DAG: stw [[REG:[0-9]+]], 160(1) ; ASM32PWR4-DAG: stw [[REG:[0-9]+]], 160(1)
; ASM32PWR4-DAG: stw [[REG:[0-9]+]], 164(1) ; ASM32PWR4-DAG: stw [[REG:[0-9]+]], 164(1)
; ASM32PWR4: bl .mix_floats ; ASM32PWR4: bl .mix_floats
; ASM64PWR4: mflr 0 ; ASM64PWR4: mflr 0
; ASM64PWR4-DAG: std 0, 16(1) ; ASM64PWR4-NEXT: stdu 1, -240(1)
; ASM64PWR4-DAG: stdu 1, -240(1) ; ASM64PWR4-DAG: std 0, 256(1)
; ASM64PWR4-DAG: std [[REG:[0-9]+]], 112(1) ; ASM64PWR4-DAG: std [[REG:[0-9]+]], 112(1)
; ASM64PWR4-DAG: std [[REG:[0-9]+]], 120(1) ; ASM64PWR4-DAG: std [[REG:[0-9]+]], 120(1)
; ASM64PWR4-DAG: std [[REG:[0-9]+]], 128(1) ; ASM64PWR4-DAG: std [[REG:[0-9]+]], 128(1)
; ASM64PWR4-DAG: std [[REG:[0-9]+]], 136(1) ; ASM64PWR4-DAG: std [[REG:[0-9]+]], 136(1)
; ASM64PWR4-DAG: std [[REG:[0-9]+]], 144(1) ; ASM64PWR4-DAG: std [[REG:[0-9]+]], 144(1)
; ASM64PWR4-DAG: std [[REG:[0-9]+]], 152(1) ; ASM64PWR4-DAG: std [[REG:[0-9]+]], 152(1)
; ASM64PWR4-DAG: std [[REG:[0-9]+]], 160(1) ; ASM64PWR4-DAG: std [[REG:[0-9]+]], 160(1)
; ASM64PWR4-DAG: std [[REG:[0-9]+]], 168(1) ; ASM64PWR4-DAG: std [[REG:[0-9]+]], 168(1)
; ASM64PWR4-DAG: std [[REG:[0-9]+]], 176(1) ; ASM64PWR4-DAG: std [[REG:[0-9]+]], 176(1)
; ASM64PWR4-DAG: std [[REG:[0-9]+]], 184(1) ; ASM64PWR4-DAG: std [[REG:[0-9]+]], 184(1)
; ASM64PWR4-DAG: std [[REG:[0-9]+]], 192(1) ; ASM64PWR4-DAG: std [[REG:[0-9]+]], 192(1)
; ASM64PWR4-DAG: std [[REG:[0-9]+]], 200(1) ; ASM64PWR4-DAG: std [[REG:[0-9]+]], 200(1)
; ASM64PWR4-DAG: std [[REG:[0-9]+]], 208(1) ; ASM64PWR4-DAG: std [[REG:[0-9]+]], 208(1)
; ASM64PWR4-DAG: std [[REG:[0-9]+]], 216(1) ; ASM64PWR4-DAG: std [[REG:[0-9]+]], 216(1)
; ASM64PWR4: bl .mix_floats ; ASM64PWR4: bl .mix_floats

llvm/test/CodeGen/PowerPC/aix-cc-byval-mem.ll

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; 32BIT-NEXT: ADJCALLSTACKUP 312, 0, implicit-def dead $r1, implicit $r1 ; 32BIT-NEXT: ADJCALLSTACKUP 312, 0, implicit-def dead $r1, implicit $r1
; CHECKASM-LABEL: .call_test_byval_mem2: ; CHECKASM-LABEL: .call_test_byval_mem2:
; ASM32BIT: stwu 1, -320(1) ; ASM32BIT: stwu 1, -320(1)
; ASM32BIT-DAG: addi 3, 1, 56 ; ASM32BIT-DAG: addi 3, 1, 56
; ASM32BIT-DAG: lwz 4, L..C{{[0-9]+}}(2) ; ASM32BIT-DAG: lwz 4, L..C{{[0-9]+}}(2)
; ASM32BIT-DAG: li 5, 256 ; ASM32BIT-DAG: li 5, 256
; ASM32BIT-DAG: stw 0, 328(1)
; ASM32BIT-NEXT: bl .memcpy[PR] ; ASM32BIT-NEXT: bl .memcpy[PR]
; ASM32BIT: bl .test_byval_mem2 ; ASM32BIT: bl .test_byval_mem2
; ASM32BIT: addi 1, 1, 320 ; ASM32BIT: addi 1, 1, 320
; Confirm the expected memcpy call is independent of the call to test_byval_mem2. ; Confirm the expected memcpy call is independent of the call to test_byval_mem2.
; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1 ; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
; 64BIT-NEXT: %0:g8rc = nuw ADDI8 $x1, 112 ; 64BIT-NEXT: %0:g8rc = nuw ADDI8 $x1, 112
; 64BIT-NEXT: %1:g8rc = LDtoc @gS256, $x2 :: (load (s64) from got) ; 64BIT-NEXT: %1:g8rc = LDtoc @gS256, $x2 :: (load (s64) from got)
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; 64BIT-DAG: $x10 = COPY %{{[0-9]+}} ; 64BIT-DAG: $x10 = COPY %{{[0-9]+}}
; 64BIT-NEXT: BL8_NOP <mcsymbol .test_byval_mem2>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x7, implicit $x8, implicit $x9, implicit $x10, implicit $x2, implicit-def $r1 ; 64BIT-NEXT: BL8_NOP <mcsymbol .test_byval_mem2>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x7, implicit $x8, implicit $x9, implicit $x10, implicit $x2, implicit-def $r1
; 64BIT-NEXT: ADJCALLSTACKUP 368, 0, implicit-def dead $r1, implicit $r1 ; 64BIT-NEXT: ADJCALLSTACKUP 368, 0, implicit-def dead $r1, implicit $r1
; ASM64BIT: stdu 1, -368(1) ; ASM64BIT: stdu 1, -368(1)
; ASM64BIT-DAG: addi 3, 1, 112 ; ASM64BIT-DAG: addi 3, 1, 112
; ASM64BIT-DAG: ld 4, L..C{{[0-9]+}}(2) ; ASM64BIT-DAG: ld 4, L..C{{[0-9]+}}(2)
; ASM64BIT-DAG: li 5, 256 ; ASM64BIT-DAG: li 5, 256
; ASM64BIT-DAG: std 0, 384(1)
; ASM64BIT-NEXT: bl .memcpy[PR] ; ASM64BIT-NEXT: bl .memcpy[PR]
; ASM64BIT: bl .test_byval_mem2 ; ASM64BIT: bl .test_byval_mem2
; ASM64BIT: addi 1, 1, 368 ; ASM64BIT: addi 1, 1, 368
define zeroext i8 @test_byval_mem2(i32, i32, i32, i32, i32, i32, i32, i32, ptr byval(%struct_S256) align 1 %s) { define zeroext i8 @test_byval_mem2(i32, i32, i32, i32, i32, i32, i32, i32, ptr byval(%struct_S256) align 1 %s) {
entry: entry:
%gep = getelementptr inbounds %struct_S256, ptr %s, i32 0, i32 0, i32 255 %gep = getelementptr inbounds %struct_S256, ptr %s, i32 0, i32 0, i32 255
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; 32BIT-DAG: $r7 = COPY %{{[0-9]+}} ; 32BIT-DAG: $r7 = COPY %{{[0-9]+}}
; 32BIT-DAG: $r8 = COPY %{{[0-9]+}} ; 32BIT-DAG: $r8 = COPY %{{[0-9]+}}
; 32BIT-DAG: $r9 = COPY %{{[0-9]+}} ; 32BIT-DAG: $r9 = COPY %{{[0-9]+}}
; 32BIT-DAG: $r10 = COPY %{{[0-9]+}} ; 32BIT-DAG: $r10 = COPY %{{[0-9]+}}
; 32BIT-NEXT: BL_NOP <mcsymbol .test_byval_mem4>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r5, implicit $r6, implicit $r7, implicit $r8, implicit $r9, implicit $r10, implicit $r2, implicit-def $r1 ; 32BIT-NEXT: BL_NOP <mcsymbol .test_byval_mem4>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r5, implicit $r6, implicit $r7, implicit $r8, implicit $r9, implicit $r10, implicit $r2, implicit-def $r1
; 32BIT-NEXT: ADJCALLSTACKUP 316, 0, implicit-def dead $r1, implicit $r1 ; 32BIT-NEXT: ADJCALLSTACKUP 316, 0, implicit-def dead $r1, implicit $r1
; ASM32BIT: stwu 1, -320(1) ; ASM32BIT: stwu 1, -320(1)
; ASM32BIT-NEXT: stw [[REG1:[0-9]+]], {{[0-9]+}}(1) ; ASM32BIT-NEXT: stw 0, 328(1)
; ASM32BIT: lwz [[REG1]], L..C{{[0-9]+}}(2) ; ASM32BIT-DAG: stw [[REG1:[0-9]+]], {{[0-9]+}}(1)
; ASM32BIT-DAG: lwz [[REG1]], L..C{{[0-9]+}}(2)
; ASM32BIT-DAG: lhz [[REG2:[0-9]+]], 28([[REG1]]) ; ASM32BIT-DAG: lhz [[REG2:[0-9]+]], 28([[REG1]])
; ASM32BIT-DAG: sth [[REG2]], 56(1) ; ASM32BIT-DAG: sth [[REG2]], 56(1)
; ASM32BIT-DAG: lbz [[REG3:[0-9]+]], 30([[REG1]]) ; ASM32BIT-DAG: lbz [[REG3:[0-9]+]], 30([[REG1]])
; ASM32BIT-DAG: stb [[REG3]], 58(1) ; ASM32BIT-DAG: stb [[REG3]], 58(1)
; ASM32BIT-DAG: addi 3, 1, 60 ; ASM32BIT-DAG: addi 3, 1, 60
; ASM32BIT-DAG: lwz 4, L..C{{[0-9]+}}(2) ; ASM32BIT-DAG: lwz 4, L..C{{[0-9]+}}(2)
; ASM32BIT-DAG: li 5, 256 ; ASM32BIT-DAG: li 5, 256
; ASM32BIT-NEXT: bl .memcpy[PR] ; ASM32BIT-NEXT: bl .memcpy[PR]
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llvm/test/CodeGen/PowerPC/aix-cc-byval.ll

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; 32BIT-NEXT: renamable $r3 = RLWINM killed renamable $r3, 24, 0, 7 ; 32BIT-NEXT: renamable $r3 = RLWINM killed renamable $r3, 24, 0, 7
; 32BIT-NEXT: BL_NOP <mcsymbol .test_byval_1Byte>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r2, implicit-def $r1 ; 32BIT-NEXT: BL_NOP <mcsymbol .test_byval_1Byte>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r2, implicit-def $r1
; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1 ; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
; CHECKASM-LABEL: .call_test_byval_1Byte: ; CHECKASM-LABEL: .call_test_byval_1Byte:
; ASM32: stwu 1, -64(1) ; ASM32: stwu 1, -64(1)
; ASM32-NEXT: lwz [[REG:[0-9]+]], L..C{{[0-9]+}}(2) ; ASM32-NEXT: lwz [[REG:[0-9]+]], L..C{{[0-9]+}}(2)
; ASM32-NEXT: stw 0, 72(1)
; ASM32-NEXT: lbz 3, 0([[REG]]) ; ASM32-NEXT: lbz 3, 0([[REG]])
; ASM32-NEXT: slwi 3, 3, 24 ; ASM32-NEXT: slwi 3, 3, 24
; ASM32-NEXT: bl .test_byval_1Byte ; ASM32-NEXT: bl .test_byval_1Byte
; ASM32-NEXT: nop ; ASM32-NEXT: nop
; ASM32-NEXT: addi 1, 1, 64 ; ASM32-NEXT: addi 1, 1, 64
; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1 ; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
; 64BIT-NEXT: renamable $x[[REG:[0-9]+]] = LDtoc @gS1, $x2 :: (load (s64) from got) ; 64BIT-NEXT: renamable $x[[REG:[0-9]+]] = LDtoc @gS1, $x2 :: (load (s64) from got)
; 64BIT-NEXT: renamable $x3 = LBZ8 0, killed renamable $x[[REG]] :: (load (s8)) ; 64BIT-NEXT: renamable $x3 = LBZ8 0, killed renamable $x[[REG]] :: (load (s8))
; 64BIT-NEXT: renamable $x3 = RLDICR killed renamable $x3, 56, 7 ; 64BIT-NEXT: renamable $x3 = RLDICR killed renamable $x3, 56, 7
; 64BIT-NEXT: BL8_NOP <mcsymbol .test_byval_1Byte>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1 ; 64BIT-NEXT: BL8_NOP <mcsymbol .test_byval_1Byte>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 ; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
; ASM64: std 0, 16(1) ; ASM64: stdu 1, -128(1)
; ASM64-NEXT: stdu 1, -128(1)
; ASM64-NEXT: ld [[REG:[0-9]+]], L..C{{[0-9]+}}(2) ; ASM64-NEXT: ld [[REG:[0-9]+]], L..C{{[0-9]+}}(2)
; ASM64-NEXT: std 0, 144(1)
; ASM64-NEXT: lbz 3, 0([[REG]]) ; ASM64-NEXT: lbz 3, 0([[REG]])
; ASM64-NEXT: sldi 3, 3, 56 ; ASM64-NEXT: sldi 3, 3, 56
; ASM64-NEXT: bl .test_byval_1Byte ; ASM64-NEXT: bl .test_byval_1Byte
; ASM64-NEXT: nop ; ASM64-NEXT: nop
; ASM64-NEXT: addi 1, 1, 128 ; ASM64-NEXT: addi 1, 1, 128
define zeroext i8 @test_byval_1Byte(ptr byval(%struct.S0) align 1 %s0, ptr byval(%struct.S1) align 1 %s) { define zeroext i8 @test_byval_1Byte(ptr byval(%struct.S0) align 1 %s0, ptr byval(%struct.S1) align 1 %s) {
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; 64BIT-DAG: renamable $x[[REG3:[0-9]+]] = LHZ8 0, killed renamable $x[[REG2]] :: (load (s16)) ; 64BIT-DAG: renamable $x[[REG3:[0-9]+]] = LHZ8 0, killed renamable $x[[REG2]] :: (load (s16))
; 64BIT-DAG: renamable $x5 = RLDICR killed renamable $x[[REG3]], 48, 15 ; 64BIT-DAG: renamable $x5 = RLDICR killed renamable $x[[REG3]], 48, 15
; 64BIT-DAG: $f2 = COPY renamable $f1 ; 64BIT-DAG: $f2 = COPY renamable $f1
; 64BIT-DAG: $x7 = LI8 43 ; 64BIT-DAG: $x7 = LI8 43
; 64BIT-NEXT: BL8_NOP <mcsymbol .test_byval_2Byte>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $f1, implicit $x5, implicit killed $f2, implicit killed $x7, implicit $x2, implicit-def $r1 ; 64BIT-NEXT: BL8_NOP <mcsymbol .test_byval_2Byte>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $f1, implicit $x5, implicit killed $f2, implicit killed $x7, implicit $x2, implicit-def $r1
; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 ; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
; ASM64: std 0, 16(1) ; ASM64: stdu 1, -112(1)
; ASM64-NEXT: stdu 1, -112(1) ; ASM64-DAG: std 0, 128(1)
; ASM64-DAG: li 3, 42 ; ASM64-DAG: li 3, 42
; ASM64-DAG: ld [[REG1:[0-9]+]], L..C{{[0-9]+}}(2) ; ASM64-DAG: ld [[REG1:[0-9]+]], L..C{{[0-9]+}}(2)
; ASM64-DAG: lfs 1, 0([[REG1]]) ; ASM64-DAG: lfs 1, 0([[REG1]])
; ASM64-DAG: ld [[REG2:[0-9]+]], L..C{{[0-9]+}}(2) ; ASM64-DAG: ld [[REG2:[0-9]+]], L..C{{[0-9]+}}(2)
; ASM64-DAG: lhz [[REG3:[0-9]+]], 0([[REG2]]) ; ASM64-DAG: lhz [[REG3:[0-9]+]], 0([[REG2]])
; ASM64-DAG: sldi 5, [[REG3]], 48 ; ASM64-DAG: sldi 5, [[REG3]], 48
; ASM64-DAG: fmr 2, 1 ; ASM64-DAG: fmr 2, 1
; ASM64-DAG: li 7, 43 ; ASM64-DAG: li 7, 43
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; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1 ; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
; 64BIT-NEXT: renamable $x[[REGADDR:[0-9]+]] = LDtoc @gS8, $x2 :: (load (s64) from got) ; 64BIT-NEXT: renamable $x[[REGADDR:[0-9]+]] = LDtoc @gS8, $x2 :: (load (s64) from got)
; 64BIT-NEXT: renamable $x3 = LD 0, killed renamable $x[[REGADDR]] :: (load (s64)) ; 64BIT-NEXT: renamable $x3 = LD 0, killed renamable $x[[REGADDR]] :: (load (s64))
; 64BIT-NEXT: BL8_NOP <mcsymbol .test_byval_8Byte[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1 ; 64BIT-NEXT: BL8_NOP <mcsymbol .test_byval_8Byte[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 ; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
; ASM64: stdu 1, -112(1) ; ASM64: stdu 1, -112(1)
; ASM64-NEXT: ld [[REGADDR:[0-9]+]], L..C{{[0-9]+}}(2) ; ASM64-NEXT: ld [[REGADDR:[0-9]+]], L..C{{[0-9]+}}(2)
; ASM64-NEXT: std 0, 128(1)
; ASM64-NEXT: ld 3, 0([[REGADDR]]) ; ASM64-NEXT: ld 3, 0([[REGADDR]])
; ASM64-NEXT: bl .test_byval_8Byte[PR] ; ASM64-NEXT: bl .test_byval_8Byte[PR]
; ASM64-NEXT: nop ; ASM64-NEXT: nop
%struct.S32 = type { [32 x i8] } %struct.S32 = type { [32 x i8] }
@gS32 = external global %struct.S32, align 1 @gS32 = external global %struct.S32, align 1
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llvm/test/CodeGen/PowerPC/aix-cc-ext-vec-abi.ll

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entry: entry:
%call = call <4 x i32> @vec_callee(<4 x i32> <i32 1, i32 2, i32 3, i32 4>, <4 x i32> <i32 5, i32 6, i32 7, i32 8>, <4 x i32> <i32 9, i32 10, i32 11, i32 12>, <4 x i32> <i32 13, i32 14, i32 15, i32 16>, <4 x i32> <i32 17, i32 18, i32 19, i32 20>, <4 x i32> <i32 21, i32 22, i32 23, i32 24>, <4 x i32> <i32 25, i32 26, i32 27, i32 28>, <4 x i32> <i32 29, i32 30, i32 31, i32 32>, <4 x i32> <i32 33, i32 34, i32 35, i32 36>, <4 x i32> <i32 37, i32 38, i32 39, i32 40>, <4 x i32> <i32 41, i32 42, i32 43, i32 44>, <4 x i32> <i32 45, i32 46, i32 47, i32 48>) %call = call <4 x i32> @vec_callee(<4 x i32> <i32 1, i32 2, i32 3, i32 4>, <4 x i32> <i32 5, i32 6, i32 7, i32 8>, <4 x i32> <i32 9, i32 10, i32 11, i32 12>, <4 x i32> <i32 13, i32 14, i32 15, i32 16>, <4 x i32> <i32 17, i32 18, i32 19, i32 20>, <4 x i32> <i32 21, i32 22, i32 23, i32 24>, <4 x i32> <i32 25, i32 26, i32 27, i32 28>, <4 x i32> <i32 29, i32 30, i32 31, i32 32>, <4 x i32> <i32 33, i32 34, i32 35, i32 36>, <4 x i32> <i32 37, i32 38, i32 39, i32 40>, <4 x i32> <i32 41, i32 42, i32 43, i32 44>, <4 x i32> <i32 45, i32 46, i32 47, i32 48>)
ret i32 0 ret i32 0
} }
; ASM-LABEL: .vec_caller: ; ASM-LABEL: .vec_caller:
; ASM32: # %bb.0: # %entry ; ASM32: # %bb.0: # %entry
; ASM32-DAG: mflr 0 ; ASM32-DAG: mflr 0
; ASM32-DAG: stw 0, 8(1)
; ASM32-DAG: stwu 1, -64(1) ; ASM32-DAG: stwu 1, -64(1)
; ASM32-DAG: lwz [[REG1:[0-9]+]], L..C0(2) ; ASM32-DAG: lwz [[REG1:[0-9]+]], L..C0(2)
; ASM32-DAG: lxvw4x 34, 0, [[REG1]] ; ASM32-DAG: lxvw4x 34, 0, [[REG1]]
; ASM32-DAG: lwz [[REG2:[0-9]+]], L..C1(2) ; ASM32-DAG: lwz [[REG2:[0-9]+]], L..C1(2)
; ASM32-DAG: lxvw4x 35, 0, [[REG2]] ; ASM32-DAG: lxvw4x 35, 0, [[REG2]]
; ASM32-DAG: lwz [[REG3:[0-9]+]], L..C2(2) ; ASM32-DAG: lwz [[REG3:[0-9]+]], L..C2(2)
; ASM32-DAG: lxvw4x 36, 0, [[REG3]] ; ASM32-DAG: lxvw4x 36, 0, [[REG3]]
; ASM32-DAG: lwz [[REG4:[0-9]+]], L..C3(2) ; ASM32-DAG: lwz [[REG4:[0-9]+]], L..C3(2)
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; ASM32-DAG: lwz [[REG9:[0-9]+]], L..C8(2) ; ASM32-DAG: lwz [[REG9:[0-9]+]], L..C8(2)
; ASM32-DAG: lxvw4x 42, 0, [[REG9]] ; ASM32-DAG: lxvw4x 42, 0, [[REG9]]
; ASM32-DAG: lwz [[REG10:[0-9]+]], L..C9(2) ; ASM32-DAG: lwz [[REG10:[0-9]+]], L..C9(2)
; ASM32-DAG: lxvw4x 43, 0, [[REG10]] ; ASM32-DAG: lxvw4x 43, 0, [[REG10]]
; ASM32-DAG: lwz [[REG11:[0-9]+]], L..C10(2) ; ASM32-DAG: lwz [[REG11:[0-9]+]], L..C10(2)
; ASM32-DAG: lxvw4x 44, 0, [[REG11]] ; ASM32-DAG: lxvw4x 44, 0, [[REG11]]
; ASM32-DAG: lwz [[REG12:[0-9]+]], L..C11(2) ; ASM32-DAG: lwz [[REG12:[0-9]+]], L..C11(2)
; ASM32-DAG: lxvw4x 45, 0, [[REG12]] ; ASM32-DAG: lxvw4x 45, 0, [[REG12]]
; ASM32-DAG: stw 0, 72(1)
; ASM32-DAG: bl .vec_callee ; ASM32-DAG: bl .vec_callee
; ASM32-DAG: li 3, 0 ; ASM32-DAG: li 3, 0
; ASM32-DAG: addi 1, 1, 64 ; ASM32-DAG: addi 1, 1, 64
; ASM32-DAG: lwz 0, 8(1) ; ASM32-DAG: lwz 0, 8(1)
; ASM32-DAG: mtlr 0 ; ASM32-DAG: mtlr 0
; ASM32: blr ; ASM32: blr
; ASM64: # %entry ; ASM64: # %entry
; ASM64-DAG: std 0, 16(1)
; ASM64-DAG: stdu 1, -112(1) ; ASM64-DAG: stdu 1, -112(1)
; ASM64-DAG: ld [[REG1:[0-9]+]], L..C0(2) ; ASM64-DAG: ld [[REG1:[0-9]+]], L..C0(2)
; ASM64-DAG: lxvw4x 34, 0, [[REG1]] ; ASM64-DAG: lxvw4x 34, 0, [[REG1]]
; ASM64-DAG: ld [[REG2:[0-9]+]], L..C1(2) ; ASM64-DAG: ld [[REG2:[0-9]+]], L..C1(2)
; ASM64-DAG: lxvw4x 35, 0, [[REG2]] ; ASM64-DAG: lxvw4x 35, 0, [[REG2]]
; ASM64-DAG: ld [[REG3:[0-9]+]], L..C2(2) ; ASM64-DAG: ld [[REG3:[0-9]+]], L..C2(2)
; ASM64-DAG: lxvw4x 36, 0, [[REG3]] ; ASM64-DAG: lxvw4x 36, 0, [[REG3]]
; ASM64-DAG: ld [[REG4:[0-9]+]], L..C3(2) ; ASM64-DAG: ld [[REG4:[0-9]+]], L..C3(2)
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; ASM64-DAG: ld [[REG9:[0-9]+]], L..C8(2) ; ASM64-DAG: ld [[REG9:[0-9]+]], L..C8(2)
; ASM64-DAG: lxvw4x 42, 0, [[REG9]] ; ASM64-DAG: lxvw4x 42, 0, [[REG9]]
; ASM64-DAG: ld [[REG10:[0-9]+]], L..C9(2) ; ASM64-DAG: ld [[REG10:[0-9]+]], L..C9(2)
; ASM64-DAG: lxvw4x 43, 0, [[REG10]] ; ASM64-DAG: lxvw4x 43, 0, [[REG10]]
; ASM64-DAG: ld [[REG11:[0-9]+]], L..C10(2) ; ASM64-DAG: ld [[REG11:[0-9]+]], L..C10(2)
; ASM64-DAG: lxvw4x 44, 0, [[REG11]] ; ASM64-DAG: lxvw4x 44, 0, [[REG11]]
; ASM64-DAG: ld [[REG12:[0-9]+]], L..C11(2) ; ASM64-DAG: ld [[REG12:[0-9]+]], L..C11(2)
; ASM64-DAG: lxvw4x 45, 0, [[REG12]] ; ASM64-DAG: lxvw4x 45, 0, [[REG12]]
; ASM64-DAG: std 0, 128(1)
; ASM64-DAG: bl .vec_callee ; ASM64-DAG: bl .vec_callee
; ASM64-DAG: li 3, 0 ; ASM64-DAG: li 3, 0
; ASM64-DAG: addi 1, 1, 112 ; ASM64-DAG: addi 1, 1, 112
; ASM64-DAG: ld 0, 16(1) ; ASM64-DAG: ld 0, 16(1)
; ASM64-DAG: mtlr 0 ; ASM64-DAG: mtlr 0
; ASM64: blr ; ASM64: blr

llvm/test/CodeGen/PowerPC/aix-crspill.ll

Show All 16 Linesentry:
%call = call signext i32 @do_something(i32 %i) %call = call signext i32 @do_something(i32 %i)
ret i32 %call ret i32 %call
} }
declare signext i32 @do_something(i32 signext) declare signext i32 @do_something(i32 signext)
; 64BIT-LABEL: .killOne: ; 64BIT-LABEL: .killOne:
; 64BIT: mflr 0 ; 64BIT: mfcr 12
; 64BIT-NEXT: std 0, 16(1)
; 64BIT-NEXT: mfcr 12
; 64BIT-NEXT: stw 12, 8(1) ; 64BIT-NEXT: stw 12, 8(1)
; 64BIT: stdu 1, -112(1) ; 64BIT-NEXT: mflr 0
; 64BIT-NEXT: stdu 1, -112(1)
; 64BIT: std 0, 128(1)
; 64BIT: # Clobber CR ; 64BIT: # Clobber CR
; 64BIT: bl .do_something ; 64BIT: bl .do_something
; 64BIT: addi 1, 1, 112 ; 64BIT: addi 1, 1, 112
; 64BIT-NEXT: ld 0, 16(1) ; 64BIT-NEXT: ld 0, 16(1)
; 64BIT-NEXT: lwz 12, 8(1) ; 64BIT-NEXT: lwz 12, 8(1)
; 64BIT-NEXT: mtlr 0 ; 64BIT-NEXT: mtlr 0
; 64BIT-NEXT: mtocrf 8, 12 ; 64BIT-NEXT: mtocrf 8, 12
; 64BIT: blr ; 64BIT: blr
; 32BIT-LABEL: .killOne: ; 32BIT-LABEL: .killOne:
; 32BIT: mflr 0 ; 32BIT: mfcr 12
; 32BIT-NEXT: stw 0, 8(1)
; 32BIT-NEXT: mfcr 12
; 32BIT-NEXT: stw 12, 4(1) ; 32BIT-NEXT: stw 12, 4(1)
; 32BIT: stwu 1, -64(1) ; 32BIT-NEXT: mflr 0
; 32BIT-NEXT: stwu 1, -64(1)
; 32BIT: stw 0, 72(1)
; 32BIT: # Clobber CR ; 32BIT: # Clobber CR
; 32BIT: bl .do_something ; 32BIT: bl .do_something
; 32BIT: addi 1, 1, 64 ; 32BIT: addi 1, 1, 64
; 32BIT-NEXT: lwz 0, 8(1) ; 32BIT-NEXT: lwz 0, 8(1)
; 32BIT-NEXT: lwz 12, 4(1) ; 32BIT-NEXT: lwz 12, 4(1)
; 32BIT-NEXT: mtlr 0 ; 32BIT-NEXT: mtlr 0
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llvm/test/CodeGen/PowerPC/aix-csr.ll

Show First 20 Lines • Show All 153 Lines • ▼ Show 20 Lines
; MIR32-NEXT: callee-saved-register: '$r13', callee-saved-restored: true, debug-info-variable: '', ; MIR32-NEXT: callee-saved-register: '$r13', callee-saved-restored: true, debug-info-variable: '',
; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' } ; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' }
; MIR32-NEXT: stack: [] ; MIR32-NEXT: stack: []
; MIR64: liveins: $x3, $x14, $x25, $x31, $f14, $f19, $f21, $f31 ; MIR64: liveins: $x3, $x14, $x25, $x31, $f14, $f19, $f21, $f31
; MIR64: $x0 = MFLR8 implicit $lr8 ; MIR64: $x0 = MFLR8 implicit $lr8
; MIR64-NEXT: STD killed $x0, 16, $x1
; MIR64-NEXT: $x1 = STDU $x1, -400, $x1 ; MIR64-NEXT: $x1 = STDU $x1, -400, $x1
; MIR64-NEXT: STD killed $x0, 416, $x1
; MIR64-DAG: STD killed $x14, 112, $x1 :: (store (s64) into %fixed-stack.6, align 16) ; MIR64-DAG: STD killed $x14, 112, $x1 :: (store (s64) into %fixed-stack.6, align 16)
; MIR64-DAG: STD killed $x25, 200, $x1 :: (store (s64) into %fixed-stack.5) ; MIR64-DAG: STD killed $x25, 200, $x1 :: (store (s64) into %fixed-stack.5)
; MIR64-DAG: STD killed $x31, 248, $x1 :: (store (s64) into %fixed-stack.4) ; MIR64-DAG: STD killed $x31, 248, $x1 :: (store (s64) into %fixed-stack.4)
; MIR64-DAG: STFD killed $f14, 256, $x1 :: (store (s64) into %fixed-stack.3, align 16) ; MIR64-DAG: STFD killed $f14, 256, $x1 :: (store (s64) into %fixed-stack.3, align 16)
; MIR64-DAG: STFD killed $f19, 296, $x1 :: (store (s64) into %fixed-stack.2) ; MIR64-DAG: STFD killed $f19, 296, $x1 :: (store (s64) into %fixed-stack.2)
; MIR64-DAG: STFD killed $f21, 312, $x1 :: (store (s64) into %fixed-stack.1) ; MIR64-DAG: STFD killed $f21, 312, $x1 :: (store (s64) into %fixed-stack.1)
; MIR64-DAG: STFD killed $f31, 392, $x1 :: (store (s64) into %fixed-stack.0) ; MIR64-DAG: STFD killed $f31, 392, $x1 :: (store (s64) into %fixed-stack.0)
Show All 11 Lines
; MIR64-NEXT: $x0 = LD 16, $x1 ; MIR64-NEXT: $x0 = LD 16, $x1
; MIR64-NEXT: MTLR8 $x0, implicit-def $lr8 ; MIR64-NEXT: MTLR8 $x0, implicit-def $lr8
; MIR64-NEXT: BLR8 implicit $lr8, implicit $rm, implicit $f1 ; MIR64-NEXT: BLR8 implicit $lr8, implicit $rm, implicit $f1
; MIR32: liveins: $r3, $r13, $r14, $r25, $r31, $f14, $f19, $f21, $f31 ; MIR32: liveins: $r3, $r13, $r14, $r25, $r31, $f14, $f19, $f21, $f31
; MIR32: $r0 = MFLR implicit $lr ; MIR32: $r0 = MFLR implicit $lr
; MIR32-NEXT: STW killed $r0, 8, $r1
; MIR32-NEXT: $r1 = STWU $r1, -288, $r1 ; MIR32-NEXT: $r1 = STWU $r1, -288, $r1
; MIR32-NEXT: STW killed $r0, 296, $r1
; MIR32-DAG: STW killed $r13, 68, $r1 :: (store (s32) into %fixed-stack.7) ; MIR32-DAG: STW killed $r13, 68, $r1 :: (store (s32) into %fixed-stack.7)
; MIR32-DAG: STW killed $r14, 72, $r1 :: (store (s32) into %fixed-stack.6, align 8) ; MIR32-DAG: STW killed $r14, 72, $r1 :: (store (s32) into %fixed-stack.6, align 8)
; MIR32-DAG: STW killed $r25, 116, $r1 :: (store (s32) into %fixed-stack.5) ; MIR32-DAG: STW killed $r25, 116, $r1 :: (store (s32) into %fixed-stack.5)
; MIR32-DAG: STW killed $r31, 140, $r1 :: (store (s32) into %fixed-stack.4) ; MIR32-DAG: STW killed $r31, 140, $r1 :: (store (s32) into %fixed-stack.4)
; MIR32-DAG: STFD killed $f14, 144, $r1 :: (store (s64) into %fixed-stack.3, align 16) ; MIR32-DAG: STFD killed $f14, 144, $r1 :: (store (s64) into %fixed-stack.3, align 16)
; MIR32-DAG: STFD killed $f19, 184, $r1 :: (store (s64) into %fixed-stack.2) ; MIR32-DAG: STFD killed $f19, 184, $r1 :: (store (s64) into %fixed-stack.2)
; MIR32-DAG: STFD killed $f21, 200, $r1 :: (store (s64) into %fixed-stack.1) ; MIR32-DAG: STFD killed $f21, 200, $r1 :: (store (s64) into %fixed-stack.1)
; MIR32-DAG: STFD killed $f31, 280, $r1 :: (store (s64) into %fixed-stack.0) ; MIR32-DAG: STFD killed $f31, 280, $r1 :: (store (s64) into %fixed-stack.0)
Show All 11 Lines
; MIR32-DAG: $r13 = LWZ 68, $r1 :: (load (s32) from %fixed-stack.7) ; MIR32-DAG: $r13 = LWZ 68, $r1 :: (load (s32) from %fixed-stack.7)
; MIR32: $r1 = ADDI $r1, 288 ; MIR32: $r1 = ADDI $r1, 288
; MIR32-NEXT: $r0 = LWZ 8, $r1 ; MIR32-NEXT: $r0 = LWZ 8, $r1
; MIR32-NEXT: MTLR $r0, implicit-def $lr ; MIR32-NEXT: MTLR $r0, implicit-def $lr
; MIR32-NEXT: BLR implicit $lr, implicit $rm, implicit $f1 ; MIR32-NEXT: BLR implicit $lr, implicit $rm, implicit $f1
; ASM64-LABEL: .fprs_and_gprs: ; ASM64-LABEL: .fprs_and_gprs:
; ASM64: mflr 0 ; ASM64: mflr 0
; ASM64-NEXT: std 0, 16(1)
; ASM64-NEXT: stdu 1, -400(1) ; ASM64-NEXT: stdu 1, -400(1)
; ASM64-NEXT: std 0, 416(1)
; ASM64-DAG: std 14, 112(1) # 8-byte Folded Spill ; ASM64-DAG: std 14, 112(1) # 8-byte Folded Spill
; ASM64-DAG: std 25, 200(1) # 8-byte Folded Spill ; ASM64-DAG: std 25, 200(1) # 8-byte Folded Spill
; ASM64-DAG: std 31, 248(1) # 8-byte Folded Spill ; ASM64-DAG: std 31, 248(1) # 8-byte Folded Spill
; ASM64-DAG: stfd 14, 256(1) # 8-byte Folded Spill ; ASM64-DAG: stfd 14, 256(1) # 8-byte Folded Spill
; ASM64-DAG: stfd 19, 296(1) # 8-byte Folded Spill ; ASM64-DAG: stfd 19, 296(1) # 8-byte Folded Spill
; ASM64-DAG: stfd 21, 312(1) # 8-byte Folded Spill ; ASM64-DAG: stfd 21, 312(1) # 8-byte Folded Spill
; ASM64-DAG: stfd 31, 392(1) # 8-byte Folded Spill ; ASM64-DAG: stfd 31, 392(1) # 8-byte Folded Spill
; ASM64: bl .dummy ; ASM64: bl .dummy
; ASM64-DAG: lfd 31, 392(1) # 8-byte Folded Reload ; ASM64-DAG: lfd 31, 392(1) # 8-byte Folded Reload
; ASM64-DAG: lfd 21, 312(1) # 8-byte Folded Reload ; ASM64-DAG: lfd 21, 312(1) # 8-byte Folded Reload
; ASM64-DAG: lfd 19, 296(1) # 8-byte Folded Reload ; ASM64-DAG: lfd 19, 296(1) # 8-byte Folded Reload
; ASM64-DAG: lfd 14, 256(1) # 8-byte Folded Reload ; ASM64-DAG: lfd 14, 256(1) # 8-byte Folded Reload
; ASM64-DAG: ld 31, 248(1) # 8-byte Folded Reload ; ASM64-DAG: ld 31, 248(1) # 8-byte Folded Reload
; ASM64-DAG: ld 25, 200(1) # 8-byte Folded Reload ; ASM64-DAG: ld 25, 200(1) # 8-byte Folded Reload
; ASM64-DAG: ld 14, 112(1) # 8-byte Folded Reload ; ASM64-DAG: ld 14, 112(1) # 8-byte Folded Reload
; ASM64: addi 1, 1, 400 ; ASM64: addi 1, 1, 400
; ASM64-NEXT: ld 0, 16(1) ; ASM64-NEXT: ld 0, 16(1)
; ASM64-NEXT: mtlr 0 ; ASM64-NEXT: mtlr 0
; ASM64-NEXT: blr ; ASM64-NEXT: blr
; ASM32-LABEL: .fprs_and_gprs: ; ASM32-LABEL: .fprs_and_gprs:
; ASM32: mflr 0 ; ASM32: mflr 0
; ASM32-NEXT: stw 0, 8(1)
; ASM32-NEXT: stwu 1, -288(1) ; ASM32-NEXT: stwu 1, -288(1)
; ASM32-NEXT: stw 0, 296(1)
; ASM32-DAG: stw 13, 68(1) # 4-byte Folded Spill ; ASM32-DAG: stw 13, 68(1) # 4-byte Folded Spill
; ASM32-DAG: stw 14, 72(1) # 4-byte Folded Spill ; ASM32-DAG: stw 14, 72(1) # 4-byte Folded Spill
; ASM32-DAG: stw 25, 116(1) # 4-byte Folded Spill ; ASM32-DAG: stw 25, 116(1) # 4-byte Folded Spill
; ASM32-DAG: stw 31, 140(1) # 4-byte Folded Spill ; ASM32-DAG: stw 31, 140(1) # 4-byte Folded Spill
; ASM32-DAG: stfd 14, 144(1) # 8-byte Folded Spill ; ASM32-DAG: stfd 14, 144(1) # 8-byte Folded Spill
; ASM32-DAG: stfd 19, 184(1) # 8-byte Folded Spill ; ASM32-DAG: stfd 19, 184(1) # 8-byte Folded Spill
; ASM32-DAG: stfd 21, 200(1) # 8-byte Folded Spill ; ASM32-DAG: stfd 21, 200(1) # 8-byte Folded Spill
; ASM32-DAG: stfd 31, 280(1) # 8-byte Folded Spill ; ASM32-DAG: stfd 31, 280(1) # 8-byte Folded Spill
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llvm/test/CodeGen/PowerPC/aix-emit-tracebacktable.ll

Show First 20 Lines • Show All 154 Lines • ▼ Show 20 Lines
; COMMON-NEXT: .vbyte 2, 0x001a # Function name len = 26 ; COMMON-NEXT: .vbyte 2, 0x001a # Function name len = 26
; COMMON-NEXT: .byte "_Z10add_structifd1SP2SD1Di" # Function Name ; COMMON-NEXT: .byte "_Z10add_structifd1SP2SD1Di" # Function Name
; COMMON-NEXT: # -- End function ; COMMON-NEXT: # -- End function
; CHECK-ASM-LABEL: .main:{{[[:space:]] *}}# %bb.0: ; CHECK-ASM-LABEL: .main:{{[[:space:]] *}}# %bb.0:
; CHECK-FUNC-LABEL: .csect .main[PR],5{{[[:space:]] *}}# %bb.0 ; CHECK-FUNC-LABEL: .csect .main[PR],5{{[[:space:]] *}}# %bb.0
; COMMON-NEXT: mflr 0 ; COMMON-NEXT: mflr 0
; COMMON-NEXT: stw 0, 8(1) ; COMMON: stw 0, 168(1)
; COMMON: mtlr 0 ; COMMON: mtlr 0
; COMMON-NEXT: blr ; COMMON-NEXT: blr
; COMMON-NEXT: L..main0: ; COMMON-NEXT: L..main0:
; COMMON-NEXT: .vbyte 4, 0x00000000 # Traceback table begin ; COMMON-NEXT: .vbyte 4, 0x00000000 # Traceback table begin
; COMMON-NEXT: .byte 0x00 # Version = 0 ; COMMON-NEXT: .byte 0x00 # Version = 0
; COMMON-NEXT: .byte 0x09 # Language = CPlusPlus ; COMMON-NEXT: .byte 0x09 # Language = CPlusPlus
; COMMON-NEXT: .byte 0x22 # -IsGlobaLinkage, -IsOutOfLineEpilogOrPrologue ; COMMON-NEXT: .byte 0x22 # -IsGlobaLinkage, -IsOutOfLineEpilogOrPrologue
; COMMON-NEXT: # +HasTraceBackTableOffset, -IsInternalProcedure ; COMMON-NEXT: # +HasTraceBackTableOffset, -IsInternalProcedure
▲ Show 20 Lines • Show All 65 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/aix-framepointer-save-restore.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs < %s -mcpu=pwr4 -mattr=-altivec \ ; RUN: llc -verify-machineinstrs < %s -mcpu=pwr4 -mattr=-altivec \
; RUN: -mtriple=powerpc-ibm-aix-xcoff | \ ; RUN: -mtriple=powerpc-ibm-aix-xcoff | \
; RUN: FileCheck %s -check-prefix=AIX32 ; RUN: FileCheck %s -check-prefix=AIX32
; RUN: llc -verify-machineinstrs < %s -mcpu=pwr4 -mattr=-altivec \ ; RUN: llc -verify-machineinstrs < %s -mcpu=pwr4 -mattr=-altivec \
; RUN: -mtriple=powerpc64-ibm-aix-xcoff | \ ; RUN: -mtriple=powerpc64-ibm-aix-xcoff | \
; RUN: FileCheck %s -check-prefixes=AIX64 ; RUN: FileCheck %s -check-prefixes=AIX64
declare void @clobber(ptr) declare void @clobber(ptr)
define dso_local float @frameptr_only(i32 %n, float %f) { define dso_local float @frameptr_only(i32 %n, float %f) {
; AIX32-LABEL: frameptr_only: ; AIX32-LABEL: frameptr_only:
; AIX32: # %bb.0: # %entry ; AIX32: # %bb.0: # %entry
; AIX32-NEXT: mflr 0 ; AIX32-NEXT: mflr 0
; AIX32-NEXT: stw 31, -12(1) ; AIX32-NEXT: stw 31, -12(1)
; AIX32-NEXT: stw 0, 8(1)
; AIX32-NEXT: stwu 1, -80(1) ; AIX32-NEXT: stwu 1, -80(1)
; AIX32-NEXT: slwi 3, 3, 2 ; AIX32-NEXT: slwi 3, 3, 2
; AIX32-NEXT: mr 31, 1 ; AIX32-NEXT: mr 31, 1
; AIX32-NEXT: stfd 31, 72(31) # 8-byte Folded Spill ; AIX32-NEXT: stw 0, 88(1)
; AIX32-NEXT: fmr 31, 1
; AIX32-NEXT: addi 3, 3, 15 ; AIX32-NEXT: addi 3, 3, 15
; AIX32-NEXT: addi 4, 31, 80 ; AIX32-NEXT: addi 4, 31, 80
; AIX32-NEXT: stfd 31, 72(31) # 8-byte Folded Spill
; AIX32-NEXT: fmr 31, 1
; AIX32-NEXT: rlwinm 3, 3, 0, 0, 27 ; AIX32-NEXT: rlwinm 3, 3, 0, 0, 27
; AIX32-NEXT: neg 3, 3 ; AIX32-NEXT: neg 3, 3
; AIX32-NEXT: stwux 4, 1, 3 ; AIX32-NEXT: stwux 4, 1, 3
; AIX32-NEXT: addi 3, 1, 64 ; AIX32-NEXT: addi 3, 1, 64
; AIX32-NEXT: bl .clobber[PR] ; AIX32-NEXT: bl .clobber[PR]
; AIX32-NEXT: nop ; AIX32-NEXT: nop
; AIX32-NEXT: fmr 1, 31 ; AIX32-NEXT: fmr 1, 31
; AIX32-NEXT: lfd 31, 72(31) # 8-byte Folded Reload ; AIX32-NEXT: lfd 31, 72(31) # 8-byte Folded Reload
; AIX32-NEXT: lwz 1, 0(1) ; AIX32-NEXT: lwz 1, 0(1)
; AIX32-NEXT: lwz 0, 8(1) ; AIX32-NEXT: lwz 0, 8(1)
; AIX32-NEXT: mtlr 0 ; AIX32-NEXT: mtlr 0
; AIX32-NEXT: lwz 31, -12(1) ; AIX32-NEXT: lwz 31, -12(1)
; AIX32-NEXT: blr ; AIX32-NEXT: blr
; ;
; AIX64-LABEL: frameptr_only: ; AIX64-LABEL: frameptr_only:
; AIX64: # %bb.0: # %entry ; AIX64: # %bb.0: # %entry
; AIX64-NEXT: mflr 0 ; AIX64-NEXT: mflr 0
; AIX64-NEXT: std 31, -16(1) ; AIX64-NEXT: std 31, -16(1)
; AIX64-NEXT: std 0, 16(1)
; AIX64-NEXT: stdu 1, -144(1) ; AIX64-NEXT: stdu 1, -144(1)
; AIX64-NEXT: rldic 3, 3, 2, 30 ; AIX64-NEXT: rldic 3, 3, 2, 30
; AIX64-NEXT: mr 31, 1 ; AIX64-NEXT: mr 31, 1
; AIX64-NEXT: stfd 31, 136(31) # 8-byte Folded Spill ; AIX64-NEXT: std 0, 160(1)
; AIX64-NEXT: fmr 31, 1
; AIX64-NEXT: addi 3, 3, 15 ; AIX64-NEXT: addi 3, 3, 15
; AIX64-NEXT: addi 4, 31, 144 ; AIX64-NEXT: addi 4, 31, 144
; AIX64-NEXT: stfd 31, 136(31) # 8-byte Folded Spill
; AIX64-NEXT: fmr 31, 1
; AIX64-NEXT: rldicl 3, 3, 60, 4 ; AIX64-NEXT: rldicl 3, 3, 60, 4
; AIX64-NEXT: rldicl 3, 3, 4, 29 ; AIX64-NEXT: rldicl 3, 3, 4, 29
; AIX64-NEXT: neg 3, 3 ; AIX64-NEXT: neg 3, 3
; AIX64-NEXT: stdux 4, 1, 3 ; AIX64-NEXT: stdux 4, 1, 3
; AIX64-NEXT: addi 3, 1, 112 ; AIX64-NEXT: addi 3, 1, 112
; AIX64-NEXT: bl .clobber[PR] ; AIX64-NEXT: bl .clobber[PR]
; AIX64-NEXT: nop ; AIX64-NEXT: nop
; AIX64-NEXT: fmr 1, 31 ; AIX64-NEXT: fmr 1, 31
▲ Show 20 Lines • Show All 75 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/aix-llvm-intrinsic.ll

Show First 20 Lines • Show All 66 Lines • ▼ Show 20 Lines
; CHECKSYM32-NEXT: StabSectNum: 0x0 ; CHECKSYM32-NEXT: StabSectNum: 0x0
; CHECKSYM64-NEXT: Auxiliary Type: AUX_CSECT (0xFB) ; CHECKSYM64-NEXT: Auxiliary Type: AUX_CSECT (0xFB)
; CHECKSYM-NEXT: } ; CHECKSYM-NEXT: }
; CHECKSYM-NEXT: } ; CHECKSYM-NEXT: }
; CHECKRELOC32: 00000000 (idx: 7) .bar: ; CHECKRELOC32: 00000000 (idx: 7) .bar:
; CHECKRELOC64: 0000000000000000 (idx: 7) .bar: ; CHECKRELOC64: 0000000000000000 (idx: 7) .bar:
; CHECKRELOC-NEXT: 0: 7c 08 02 a6 mflr 0 ; CHECKRELOC-NEXT: 0: 7c 08 02 a6 mflr 0
; CHECKRELOC32-NEXT: 4: 90 01 00 08 stw 0, 8(1) ; CHECKRELOC32-NEXT: 4: 94 21 ff c0 stwu 1, -64(1)
; CHECKRELOC32-NEXT: 8: 94 21 ff c0 stwu 1, -64(1) ; CHECKRELOC32-NEXT: 8: 80 62 00 00 lwz 3, 0(2)
; CHECKRELOC32-NEXT: c: 80 62 00 00 lwz 3, 0(2) ; CHECKRELOC32-NEXT: 0000000a: R_TOC (idx: 13) s[TC]
; CHECKRELOC64-NEXT: 4: f8 01 00 10 std 0, 16(1) ; CHECKRELOC32-NEXT: c: 90 01 00 48 stw 0, 72(1)
; CHECKRELOC64-NEXT: 8: f8 21 ff 91 stdu 1, -112(1) ; CHECKRELOC64-NEXT: 4: f8 21 ff 91 stdu 1, -112(1)
; CHECKRELOC64-NEXT: c: e8 62 00 00 ld 3, 0(2) ; CHECKRELOC64-NEXT: 8: e8 62 00 00 ld 3, 0(2)
; CHECKRELOC32-NEXT: 0000000e: R_TOC (idx: 13) s[TC] ; CHECKRELOC64-NEXT: 000000000000000a: R_TOC (idx: 13) s[TC]
; CHECKRELOC64-NEXT: 000000000000000e: R_TOC (idx: 13) s[TC] ; CHECKRELOC64-NEXT: c: f8 01 00 80 std 0, 128(1)
; CHECKRELOC-NEXT: 10: 80 83 00 04 lwz 4, 4(3) ; CHECKRELOC-NEXT: 10: 80 83 00 04 lwz 4, 4(3)
; CHECKRELOC-NEXT: 14: 7c 85 23 78 mr 5, 4 ; CHECKRELOC-NEXT: 14: 7c 85 23 78 mr 5, 4
; CHECKRELOC-NEXT: 18: 4b ff ff e9 bl 0x0 ; CHECKRELOC-NEXT: 18: 4b ff ff e9 bl 0x0
; CHECKRELOC32-NEXT: 00000018: R_RBR (idx: 1) .memset[PR] ; CHECKRELOC32-NEXT: 00000018: R_RBR (idx: 1) .memset[PR]
; CHECKRELOC64-NEXT: 0000000000000018: R_RBR (idx: 1) .memset[PR] ; CHECKRELOC64-NEXT: 0000000000000018: R_RBR (idx: 1) .memset[PR]

llvm/test/CodeGen/PowerPC/aix-lr.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff < %s | \ ; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff < %s | \
; RUN: FileCheck --check-prefix=32BIT %s ; RUN: FileCheck --check-prefix=32BIT %s
; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff < %s | \ ; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff < %s | \
; RUN: FileCheck --check-prefix=64BIT %s ; RUN: FileCheck --check-prefix=64BIT %s
define void @bar() { define void @bar() {
; 32BIT-LABEL: bar: ; 32BIT-LABEL: bar:
; 32BIT: # %bb.0: # %entry ; 32BIT: # %bb.0: # %entry
; 32BIT-NEXT: mflr 0 ; 32BIT-NEXT: mflr 0
; 32BIT-NEXT: stw 0, 8(1)
; 32BIT-NEXT: stwu 1, -64(1) ; 32BIT-NEXT: stwu 1, -64(1)
; 32BIT-NEXT: stw 0, 72(1)
; 32BIT-NEXT: bl .foo[PR] ; 32BIT-NEXT: bl .foo[PR]
; 32BIT-NEXT: nop ; 32BIT-NEXT: nop
; 32BIT-NEXT: addi 1, 1, 64 ; 32BIT-NEXT: addi 1, 1, 64
; 32BIT-NEXT: lwz 0, 8(1) ; 32BIT-NEXT: lwz 0, 8(1)
; 32BIT-NEXT: mtlr 0 ; 32BIT-NEXT: mtlr 0
; 32BIT-NEXT: blr ; 32BIT-NEXT: blr
; ;
; 64BIT-LABEL: bar: ; 64BIT-LABEL: bar:
; 64BIT: # %bb.0: # %entry ; 64BIT: # %bb.0: # %entry
; 64BIT-NEXT: mflr 0 ; 64BIT-NEXT: mflr 0
; 64BIT-NEXT: std 0, 16(1)
; 64BIT-NEXT: stdu 1, -112(1) ; 64BIT-NEXT: stdu 1, -112(1)
; 64BIT-NEXT: std 0, 128(1)
; 64BIT-NEXT: bl .foo[PR] ; 64BIT-NEXT: bl .foo[PR]
; 64BIT-NEXT: nop ; 64BIT-NEXT: nop
; 64BIT-NEXT: addi 1, 1, 112 ; 64BIT-NEXT: addi 1, 1, 112
; 64BIT-NEXT: ld 0, 16(1) ; 64BIT-NEXT: ld 0, 16(1)
; 64BIT-NEXT: mtlr 0 ; 64BIT-NEXT: mtlr 0
; 64BIT-NEXT: blr ; 64BIT-NEXT: blr
entry: entry:
call void @foo() call void @foo()
ret void ret void
} }
declare void @foo(...) declare void @foo(...)

llvm/test/CodeGen/PowerPC/aix-sret-param.ll

Show First 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
; MIR64-NEXT: BL8_NOP <mcsymbol .foo[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1 ; MIR64-NEXT: BL8_NOP <mcsymbol .foo[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
; MIR64-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 ; MIR64-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
; ASM-LABEL: .test1: ; ASM-LABEL: .test1:
; ASM32: stwu 1, -64(1) ; ASM32: stwu 1, -64(1)
; ASM32-NEXT: addi 3, 1, 56 ; ASM32-NEXT: addi 3, 1, 56
; ASM32-NEXT: stw 0, 72(1)
; ASM32-NEXT: bl .foo[PR] ; ASM32-NEXT: bl .foo[PR]
; ASM32-NEXT: nop ; ASM32-NEXT: nop
; ASM32-NEXT: addi 1, 1, 64 ; ASM32-NEXT: addi 1, 1, 64
; ASM64: stdu 1, -128(1) ; ASM64: stdu 1, -128(1)
; ASM64-NEXT: addi 3, 1, 120 ; ASM64-NEXT: addi 3, 1, 120
; ASM64-NEXT: std 0, 144(1)
; ASM64-NEXT: bl .foo[PR] ; ASM64-NEXT: bl .foo[PR]
; ASM64-NEXT: nop ; ASM64-NEXT: nop
; ASM64-NEXT: addi 1, 1, 128 ; ASM64-NEXT: addi 1, 1, 128
; MIR: name: test2 ; MIR: name: test2
; MIR: stack: ; MIR: stack:
Show All 11 Lines
; MIR64-NEXT: BL8_NOP <mcsymbol .bar[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1 ; MIR64-NEXT: BL8_NOP <mcsymbol .bar[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
; MIR64-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 ; MIR64-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
; ASM-LABEL: .test2: ; ASM-LABEL: .test2:
; ASM32: stwu 1, -80(1) ; ASM32: stwu 1, -80(1)
; ASM32-NEXT: addi 3, 1, 56 ; ASM32-NEXT: addi 3, 1, 56
; ASM32-NEXT: stw 0, 88(1)
; ASM32-NEXT: bl .bar[PR] ; ASM32-NEXT: bl .bar[PR]
; ASM32-NEXT: nop ; ASM32-NEXT: nop
; ASM32-NEXT: addi 1, 1, 80 ; ASM32-NEXT: addi 1, 1, 80
; ASM64: stdu 1, -144(1) ; ASM64: stdu 1, -144(1)
; ASM64-NEXT: addi 3, 1, 120 ; ASM64-NEXT: addi 3, 1, 120
; ASM64-NEXT: std 0, 160(1)
; ASM64-NEXT: bl .bar[PR] ; ASM64-NEXT: bl .bar[PR]
; ASM64-NEXT: nop ; ASM64-NEXT: nop
; ASM64-NEXT: addi 1, 1, 144 ; ASM64-NEXT: addi 1, 1, 144

llvm/test/CodeGen/PowerPC/aix-tls-gd-double.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec \ ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec \
; RUN: -mtriple powerpc-ibm-aix-xcoff < %s | FileCheck %s \ ; RUN: -mtriple powerpc-ibm-aix-xcoff < %s | FileCheck %s \
; RUN: --check-prefix=SMALL32 ; RUN: --check-prefix=SMALL32
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec \ ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec \
; RUN: -mtriple powerpc-ibm-aix-xcoff --code-model=large < %s \ ; RUN: -mtriple powerpc-ibm-aix-xcoff --code-model=large < %s \
; RUN: | FileCheck %s --check-prefix=LARGE32 ; RUN: | FileCheck %s --check-prefix=LARGE32
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec \ ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec \
; RUN: -mtriple powerpc64-ibm-aix-xcoff < %s | FileCheck %s \ ; RUN: -mtriple powerpc64-ibm-aix-xcoff < %s | FileCheck %s \
; RUN: --check-prefix=SMALL64 ; RUN: --check-prefix=SMALL64
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec \ ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec \
; RUN: -mtriple powerpc64-ibm-aix-xcoff --code-model=large < %s \ ; RUN: -mtriple powerpc64-ibm-aix-xcoff --code-model=large < %s \
; RUN: | FileCheck %s --check-prefix=LARGE64 ; RUN: | FileCheck %s --check-prefix=LARGE64
@TGInit = thread_local global double 1.000000e+00, align 8 @TGInit = thread_local global double 1.000000e+00, align 8
@TWInit = weak thread_local global double 1.000000e+00, align 8 @TWInit = weak thread_local global double 1.000000e+00, align 8
@GInit = global double 1.000000e+00, align 8 @GInit = global double 1.000000e+00, align 8
@TGUninit = thread_local global double 0.000000e+00, align 8 @TGUninit = thread_local global double 0.000000e+00, align 8
@TIInit = internal thread_local global double 1.000000e+00, align 8 @TIInit = internal thread_local global double 1.000000e+00, align 8
; Function Attrs: nofree norecurse nounwind willreturn writeonly ; Function Attrs: nofree norecurse nounwind willreturn writeonly
define void @storesTGUninit(double %Val) #0 { define void @storesTGUninit(double %Val) #0 {
; SMALL32-LABEL: storesTGUninit: ; SMALL32-LABEL: storesTGUninit:
; SMALL32: # %bb.0: # %entry ; SMALL32: # %bb.0: # %entry
; SMALL32-NEXT: mflr 0 ; SMALL32-NEXT: mflr 0
; SMALL32-NEXT: stw 0, 8(1)
; SMALL32-NEXT: stwu 1, -32(1) ; SMALL32-NEXT: stwu 1, -32(1)
; SMALL32-NEXT: lwz 3, L..C0(2) ; SMALL32-NEXT: lwz 3, L..C0(2) # target-flags(ppc-lo) @TGUninit
; SMALL32-NEXT: lwz 4, L..C1(2) ; SMALL32-NEXT: lwz 4, L..C1(2) # target-flags(ppc-tlsgd) @TGUninit
; SMALL32-NEXT: stw 0, 40(1)
; SMALL32-NEXT: bla .__tls_get_addr[PR] ; SMALL32-NEXT: bla .__tls_get_addr[PR]
; SMALL32-NEXT: stfd 1, 0(3) ; SMALL32-NEXT: stfd 1, 0(3)
; SMALL32-NEXT: addi 1, 1, 32 ; SMALL32-NEXT: addi 1, 1, 32
; SMALL32-NEXT: lwz 0, 8(1) ; SMALL32-NEXT: lwz 0, 8(1)
; SMALL32-NEXT: mtlr 0 ; SMALL32-NEXT: mtlr 0
; SMALL32-NEXT: blr ; SMALL32-NEXT: blr
; ;
; LARGE32-LABEL: storesTGUninit: ; LARGE32-LABEL: storesTGUninit:
; LARGE32: # %bb.0: # %entry ; LARGE32: # %bb.0: # %entry
; LARGE32-NEXT: mflr 0 ; LARGE32-NEXT: mflr 0
; LARGE32-NEXT: stw 0, 8(1)
; LARGE32-NEXT: stwu 1, -32(1) ; LARGE32-NEXT: stwu 1, -32(1)
; LARGE32-NEXT: stw 0, 40(1)
; LARGE32-NEXT: addis 3, L..C0@u(2) ; LARGE32-NEXT: addis 3, L..C0@u(2)
; LARGE32-NEXT: addis 4, L..C1@u(2) ; LARGE32-NEXT: addis 4, L..C1@u(2)
; LARGE32-NEXT: lwz 3, L..C0@l(3) ; LARGE32-NEXT: lwz 3, L..C0@l(3)
; LARGE32-NEXT: lwz 4, L..C1@l(4) ; LARGE32-NEXT: lwz 4, L..C1@l(4)
; LARGE32-NEXT: bla .__tls_get_addr[PR] ; LARGE32-NEXT: bla .__tls_get_addr[PR]
; LARGE32-NEXT: stfd 1, 0(3) ; LARGE32-NEXT: stfd 1, 0(3)
; LARGE32-NEXT: addi 1, 1, 32 ; LARGE32-NEXT: addi 1, 1, 32
; LARGE32-NEXT: lwz 0, 8(1) ; LARGE32-NEXT: lwz 0, 8(1)
; LARGE32-NEXT: mtlr 0 ; LARGE32-NEXT: mtlr 0
; LARGE32-NEXT: blr ; LARGE32-NEXT: blr
; ;
; SMALL64-LABEL: storesTGUninit: ; SMALL64-LABEL: storesTGUninit:
; SMALL64: # %bb.0: # %entry ; SMALL64: # %bb.0: # %entry
; SMALL64-NEXT: mflr 0 ; SMALL64-NEXT: mflr 0
; SMALL64-NEXT: std 0, 16(1)
; SMALL64-NEXT: stdu 1, -48(1) ; SMALL64-NEXT: stdu 1, -48(1)
; SMALL64-NEXT: ld 3, L..C0(2) ; SMALL64-NEXT: ld 3, L..C0(2) # target-flags(ppc-lo) @TGUninit
; SMALL64-NEXT: ld 4, L..C1(2) ; SMALL64-NEXT: ld 4, L..C1(2) # target-flags(ppc-tlsgd) @TGUninit
; SMALL64-NEXT: std 0, 64(1)
; SMALL64-NEXT: bla .__tls_get_addr[PR] ; SMALL64-NEXT: bla .__tls_get_addr[PR]
; SMALL64-NEXT: stfd 1, 0(3) ; SMALL64-NEXT: stfd 1, 0(3)
; SMALL64-NEXT: addi 1, 1, 48 ; SMALL64-NEXT: addi 1, 1, 48
; SMALL64-NEXT: ld 0, 16(1) ; SMALL64-NEXT: ld 0, 16(1)
; SMALL64-NEXT: mtlr 0 ; SMALL64-NEXT: mtlr 0
; SMALL64-NEXT: blr ; SMALL64-NEXT: blr
; ;
; LARGE64-LABEL: storesTGUninit: ; LARGE64-LABEL: storesTGUninit:
; LARGE64: # %bb.0: # %entry ; LARGE64: # %bb.0: # %entry
; LARGE64-NEXT: mflr 0 ; LARGE64-NEXT: mflr 0
; LARGE64-NEXT: std 0, 16(1)
; LARGE64-NEXT: stdu 1, -48(1) ; LARGE64-NEXT: stdu 1, -48(1)
; LARGE64-NEXT: addis 3, L..C0@u(2) ; LARGE64-NEXT: addis 3, L..C0@u(2)
; LARGE64-NEXT: addis 4, L..C1@u(2) ; LARGE64-NEXT: addis 4, L..C1@u(2)
; LARGE64-NEXT: std 0, 64(1)
; LARGE64-NEXT: ld 3, L..C0@l(3) ; LARGE64-NEXT: ld 3, L..C0@l(3)
; LARGE64-NEXT: ld 4, L..C1@l(4) ; LARGE64-NEXT: ld 4, L..C1@l(4)
; LARGE64-NEXT: bla .__tls_get_addr[PR] ; LARGE64-NEXT: bla .__tls_get_addr[PR]
; LARGE64-NEXT: stfd 1, 0(3) ; LARGE64-NEXT: stfd 1, 0(3)
; LARGE64-NEXT: addi 1, 1, 48 ; LARGE64-NEXT: addi 1, 1, 48
; LARGE64-NEXT: ld 0, 16(1) ; LARGE64-NEXT: ld 0, 16(1)
; LARGE64-NEXT: mtlr 0 ; LARGE64-NEXT: mtlr 0
; LARGE64-NEXT: blr ; LARGE64-NEXT: blr
entry: entry:
store double %Val, ptr @TGUninit, align 8 store double %Val, ptr @TGUninit, align 8
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind willreturn writeonly ; Function Attrs: nofree norecurse nounwind willreturn writeonly
define void @storesTGInit(double %Val) #0 { define void @storesTGInit(double %Val) #0 {
; SMALL32-LABEL: storesTGInit: ; SMALL32-LABEL: storesTGInit:
; SMALL32: # %bb.0: # %entry ; SMALL32: # %bb.0: # %entry
; SMALL32-NEXT: mflr 0 ; SMALL32-NEXT: mflr 0
; SMALL32-NEXT: stw 0, 8(1)
; SMALL32-NEXT: stwu 1, -32(1) ; SMALL32-NEXT: stwu 1, -32(1)
; SMALL32-NEXT: lwz 3, L..C2(2) ; SMALL32-NEXT: lwz 3, L..C2(2) # target-flags(ppc-lo) @TGInit
; SMALL32-NEXT: lwz 4, L..C3(2) ; SMALL32-NEXT: lwz 4, L..C3(2) # target-flags(ppc-tlsgd) @TGInit
; SMALL32-NEXT: stw 0, 40(1)
; SMALL32-NEXT: bla .__tls_get_addr[PR] ; SMALL32-NEXT: bla .__tls_get_addr[PR]
; SMALL32-NEXT: stfd 1, 0(3) ; SMALL32-NEXT: stfd 1, 0(3)
; SMALL32-NEXT: addi 1, 1, 32 ; SMALL32-NEXT: addi 1, 1, 32
; SMALL32-NEXT: lwz 0, 8(1) ; SMALL32-NEXT: lwz 0, 8(1)
; SMALL32-NEXT: mtlr 0 ; SMALL32-NEXT: mtlr 0
; SMALL32-NEXT: blr ; SMALL32-NEXT: blr
; ;
; LARGE32-LABEL: storesTGInit: ; LARGE32-LABEL: storesTGInit:
; LARGE32: # %bb.0: # %entry ; LARGE32: # %bb.0: # %entry
; LARGE32-NEXT: mflr 0 ; LARGE32-NEXT: mflr 0
; LARGE32-NEXT: stw 0, 8(1)
; LARGE32-NEXT: stwu 1, -32(1) ; LARGE32-NEXT: stwu 1, -32(1)
; LARGE32-NEXT: stw 0, 40(1)
; LARGE32-NEXT: addis 3, L..C2@u(2) ; LARGE32-NEXT: addis 3, L..C2@u(2)
; LARGE32-NEXT: addis 4, L..C3@u(2) ; LARGE32-NEXT: addis 4, L..C3@u(2)
; LARGE32-NEXT: lwz 3, L..C2@l(3) ; LARGE32-NEXT: lwz 3, L..C2@l(3)
; LARGE32-NEXT: lwz 4, L..C3@l(4) ; LARGE32-NEXT: lwz 4, L..C3@l(4)
; LARGE32-NEXT: bla .__tls_get_addr[PR] ; LARGE32-NEXT: bla .__tls_get_addr[PR]
; LARGE32-NEXT: stfd 1, 0(3) ; LARGE32-NEXT: stfd 1, 0(3)
; LARGE32-NEXT: addi 1, 1, 32 ; LARGE32-NEXT: addi 1, 1, 32
; LARGE32-NEXT: lwz 0, 8(1) ; LARGE32-NEXT: lwz 0, 8(1)
; LARGE32-NEXT: mtlr 0 ; LARGE32-NEXT: mtlr 0
; LARGE32-NEXT: blr ; LARGE32-NEXT: blr
; ;
; SMALL64-LABEL: storesTGInit: ; SMALL64-LABEL: storesTGInit:
; SMALL64: # %bb.0: # %entry ; SMALL64: # %bb.0: # %entry
; SMALL64-NEXT: mflr 0 ; SMALL64-NEXT: mflr 0
; SMALL64-NEXT: std 0, 16(1)
; SMALL64-NEXT: stdu 1, -48(1) ; SMALL64-NEXT: stdu 1, -48(1)
; SMALL64-NEXT: ld 3, L..C2(2) ; SMALL64-NEXT: ld 3, L..C2(2) # target-flags(ppc-lo) @TGInit
; SMALL64-NEXT: ld 4, L..C3(2) ; SMALL64-NEXT: ld 4, L..C3(2) # target-flags(ppc-tlsgd) @TGInit
; SMALL64-NEXT: std 0, 64(1)
; SMALL64-NEXT: bla .__tls_get_addr[PR] ; SMALL64-NEXT: bla .__tls_get_addr[PR]
; SMALL64-NEXT: stfd 1, 0(3) ; SMALL64-NEXT: stfd 1, 0(3)
; SMALL64-NEXT: addi 1, 1, 48 ; SMALL64-NEXT: addi 1, 1, 48
; SMALL64-NEXT: ld 0, 16(1) ; SMALL64-NEXT: ld 0, 16(1)
; SMALL64-NEXT: mtlr 0 ; SMALL64-NEXT: mtlr 0
; SMALL64-NEXT: blr ; SMALL64-NEXT: blr
; ;
; LARGE64-LABEL: storesTGInit: ; LARGE64-LABEL: storesTGInit:
; LARGE64: # %bb.0: # %entry ; LARGE64: # %bb.0: # %entry
; LARGE64-NEXT: mflr 0 ; LARGE64-NEXT: mflr 0
; LARGE64-NEXT: std 0, 16(1)
; LARGE64-NEXT: stdu 1, -48(1) ; LARGE64-NEXT: stdu 1, -48(1)
; LARGE64-NEXT: addis 3, L..C2@u(2) ; LARGE64-NEXT: addis 3, L..C2@u(2)
; LARGE64-NEXT: addis 4, L..C3@u(2) ; LARGE64-NEXT: addis 4, L..C3@u(2)
; LARGE64-NEXT: std 0, 64(1)
; LARGE64-NEXT: ld 3, L..C2@l(3) ; LARGE64-NEXT: ld 3, L..C2@l(3)
; LARGE64-NEXT: ld 4, L..C3@l(4) ; LARGE64-NEXT: ld 4, L..C3@l(4)
; LARGE64-NEXT: bla .__tls_get_addr[PR] ; LARGE64-NEXT: bla .__tls_get_addr[PR]
; LARGE64-NEXT: stfd 1, 0(3) ; LARGE64-NEXT: stfd 1, 0(3)
; LARGE64-NEXT: addi 1, 1, 48 ; LARGE64-NEXT: addi 1, 1, 48
; LARGE64-NEXT: ld 0, 16(1) ; LARGE64-NEXT: ld 0, 16(1)
; LARGE64-NEXT: mtlr 0 ; LARGE64-NEXT: mtlr 0
; LARGE64-NEXT: blr ; LARGE64-NEXT: blr
entry: entry:
store double %Val, ptr @TGInit, align 8 store double %Val, ptr @TGInit, align 8
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind willreturn writeonly ; Function Attrs: nofree norecurse nounwind willreturn writeonly
define void @storesTIInit(double %Val) #0 { define void @storesTIInit(double %Val) #0 {
; SMALL32-LABEL: storesTIInit: ; SMALL32-LABEL: storesTIInit:
; SMALL32: # %bb.0: # %entry ; SMALL32: # %bb.0: # %entry
; SMALL32-NEXT: mflr 0 ; SMALL32-NEXT: mflr 0
; SMALL32-NEXT: stw 0, 8(1)
; SMALL32-NEXT: stwu 1, -32(1) ; SMALL32-NEXT: stwu 1, -32(1)
; SMALL32-NEXT: lwz 3, L..C4(2) ; SMALL32-NEXT: lwz 3, L..C4(2) # target-flags(ppc-lo) @TIInit
; SMALL32-NEXT: lwz 4, L..C5(2) ; SMALL32-NEXT: lwz 4, L..C5(2) # target-flags(ppc-tlsgd) @TIInit
; SMALL32-NEXT: stw 0, 40(1)
; SMALL32-NEXT: bla .__tls_get_addr[PR] ; SMALL32-NEXT: bla .__tls_get_addr[PR]
; SMALL32-NEXT: stfd 1, 0(3) ; SMALL32-NEXT: stfd 1, 0(3)
; SMALL32-NEXT: addi 1, 1, 32 ; SMALL32-NEXT: addi 1, 1, 32
; SMALL32-NEXT: lwz 0, 8(1) ; SMALL32-NEXT: lwz 0, 8(1)
; SMALL32-NEXT: mtlr 0 ; SMALL32-NEXT: mtlr 0
; SMALL32-NEXT: blr ; SMALL32-NEXT: blr
; ;
; LARGE32-LABEL: storesTIInit: ; LARGE32-LABEL: storesTIInit:
; LARGE32: # %bb.0: # %entry ; LARGE32: # %bb.0: # %entry
; LARGE32-NEXT: mflr 0 ; LARGE32-NEXT: mflr 0
; LARGE32-NEXT: stw 0, 8(1)
; LARGE32-NEXT: stwu 1, -32(1) ; LARGE32-NEXT: stwu 1, -32(1)
; LARGE32-NEXT: stw 0, 40(1)
; LARGE32-NEXT: addis 3, L..C4@u(2) ; LARGE32-NEXT: addis 3, L..C4@u(2)
; LARGE32-NEXT: addis 4, L..C5@u(2) ; LARGE32-NEXT: addis 4, L..C5@u(2)
; LARGE32-NEXT: lwz 3, L..C4@l(3) ; LARGE32-NEXT: lwz 3, L..C4@l(3)
; LARGE32-NEXT: lwz 4, L..C5@l(4) ; LARGE32-NEXT: lwz 4, L..C5@l(4)
; LARGE32-NEXT: bla .__tls_get_addr[PR] ; LARGE32-NEXT: bla .__tls_get_addr[PR]
; LARGE32-NEXT: stfd 1, 0(3) ; LARGE32-NEXT: stfd 1, 0(3)
; LARGE32-NEXT: addi 1, 1, 32 ; LARGE32-NEXT: addi 1, 1, 32
; LARGE32-NEXT: lwz 0, 8(1) ; LARGE32-NEXT: lwz 0, 8(1)
; LARGE32-NEXT: mtlr 0 ; LARGE32-NEXT: mtlr 0
; LARGE32-NEXT: blr ; LARGE32-NEXT: blr
; ;
; SMALL64-LABEL: storesTIInit: ; SMALL64-LABEL: storesTIInit:
; SMALL64: # %bb.0: # %entry ; SMALL64: # %bb.0: # %entry
; SMALL64-NEXT: mflr 0 ; SMALL64-NEXT: mflr 0
; SMALL64-NEXT: std 0, 16(1)
; SMALL64-NEXT: stdu 1, -48(1) ; SMALL64-NEXT: stdu 1, -48(1)
; SMALL64-NEXT: ld 3, L..C4(2) ; SMALL64-NEXT: ld 3, L..C4(2) # target-flags(ppc-lo) @TIInit
; SMALL64-NEXT: ld 4, L..C5(2) ; SMALL64-NEXT: ld 4, L..C5(2) # target-flags(ppc-tlsgd) @TIInit
; SMALL64-NEXT: std 0, 64(1)
; SMALL64-NEXT: bla .__tls_get_addr[PR] ; SMALL64-NEXT: bla .__tls_get_addr[PR]
; SMALL64-NEXT: stfd 1, 0(3) ; SMALL64-NEXT: stfd 1, 0(3)
; SMALL64-NEXT: addi 1, 1, 48 ; SMALL64-NEXT: addi 1, 1, 48
; SMALL64-NEXT: ld 0, 16(1) ; SMALL64-NEXT: ld 0, 16(1)
; SMALL64-NEXT: mtlr 0 ; SMALL64-NEXT: mtlr 0
; SMALL64-NEXT: blr ; SMALL64-NEXT: blr
; ;
; LARGE64-LABEL: storesTIInit: ; LARGE64-LABEL: storesTIInit:
; LARGE64: # %bb.0: # %entry ; LARGE64: # %bb.0: # %entry
; LARGE64-NEXT: mflr 0 ; LARGE64-NEXT: mflr 0
; LARGE64-NEXT: std 0, 16(1)
; LARGE64-NEXT: stdu 1, -48(1) ; LARGE64-NEXT: stdu 1, -48(1)
; LARGE64-NEXT: addis 3, L..C4@u(2) ; LARGE64-NEXT: addis 3, L..C4@u(2)
; LARGE64-NEXT: addis 4, L..C5@u(2) ; LARGE64-NEXT: addis 4, L..C5@u(2)
; LARGE64-NEXT: std 0, 64(1)
; LARGE64-NEXT: ld 3, L..C4@l(3) ; LARGE64-NEXT: ld 3, L..C4@l(3)
; LARGE64-NEXT: ld 4, L..C5@l(4) ; LARGE64-NEXT: ld 4, L..C5@l(4)
; LARGE64-NEXT: bla .__tls_get_addr[PR] ; LARGE64-NEXT: bla .__tls_get_addr[PR]
; LARGE64-NEXT: stfd 1, 0(3) ; LARGE64-NEXT: stfd 1, 0(3)
; LARGE64-NEXT: addi 1, 1, 48 ; LARGE64-NEXT: addi 1, 1, 48
; LARGE64-NEXT: ld 0, 16(1) ; LARGE64-NEXT: ld 0, 16(1)
; LARGE64-NEXT: mtlr 0 ; LARGE64-NEXT: mtlr 0
; LARGE64-NEXT: blr ; LARGE64-NEXT: blr
entry: entry:
store double %Val, ptr @TIInit, align 8 store double %Val, ptr @TIInit, align 8
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind willreturn writeonly ; Function Attrs: nofree norecurse nounwind willreturn writeonly
define void @storesTWInit(double %Val) #0 { define void @storesTWInit(double %Val) #0 {
; SMALL32-LABEL: storesTWInit: ; SMALL32-LABEL: storesTWInit:
; SMALL32: # %bb.0: # %entry ; SMALL32: # %bb.0: # %entry
; SMALL32-NEXT: mflr 0 ; SMALL32-NEXT: mflr 0
; SMALL32-NEXT: stw 0, 8(1)
; SMALL32-NEXT: stwu 1, -32(1) ; SMALL32-NEXT: stwu 1, -32(1)
; SMALL32-NEXT: lwz 3, L..C6(2) ; SMALL32-NEXT: lwz 3, L..C6(2) # target-flags(ppc-lo) @TWInit
; SMALL32-NEXT: lwz 4, L..C7(2) ; SMALL32-NEXT: lwz 4, L..C7(2) # target-flags(ppc-tlsgd) @TWInit
; SMALL32-NEXT: stw 0, 40(1)
; SMALL32-NEXT: bla .__tls_get_addr[PR] ; SMALL32-NEXT: bla .__tls_get_addr[PR]
; SMALL32-NEXT: stfd 1, 0(3) ; SMALL32-NEXT: stfd 1, 0(3)
; SMALL32-NEXT: addi 1, 1, 32 ; SMALL32-NEXT: addi 1, 1, 32
; SMALL32-NEXT: lwz 0, 8(1) ; SMALL32-NEXT: lwz 0, 8(1)
; SMALL32-NEXT: mtlr 0 ; SMALL32-NEXT: mtlr 0
; SMALL32-NEXT: blr ; SMALL32-NEXT: blr
; ;
; LARGE32-LABEL: storesTWInit: ; LARGE32-LABEL: storesTWInit:
; LARGE32: # %bb.0: # %entry ; LARGE32: # %bb.0: # %entry
; LARGE32-NEXT: mflr 0 ; LARGE32-NEXT: mflr 0
; LARGE32-NEXT: stw 0, 8(1)
; LARGE32-NEXT: stwu 1, -32(1) ; LARGE32-NEXT: stwu 1, -32(1)
; LARGE32-NEXT: stw 0, 40(1)
; LARGE32-NEXT: addis 3, L..C6@u(2) ; LARGE32-NEXT: addis 3, L..C6@u(2)
; LARGE32-NEXT: addis 4, L..C7@u(2) ; LARGE32-NEXT: addis 4, L..C7@u(2)
; LARGE32-NEXT: lwz 3, L..C6@l(3) ; LARGE32-NEXT: lwz 3, L..C6@l(3)
; LARGE32-NEXT: lwz 4, L..C7@l(4) ; LARGE32-NEXT: lwz 4, L..C7@l(4)
; LARGE32-NEXT: bla .__tls_get_addr[PR] ; LARGE32-NEXT: bla .__tls_get_addr[PR]
; LARGE32-NEXT: stfd 1, 0(3) ; LARGE32-NEXT: stfd 1, 0(3)
; LARGE32-NEXT: addi 1, 1, 32 ; LARGE32-NEXT: addi 1, 1, 32
; LARGE32-NEXT: lwz 0, 8(1) ; LARGE32-NEXT: lwz 0, 8(1)
; LARGE32-NEXT: mtlr 0 ; LARGE32-NEXT: mtlr 0
; LARGE32-NEXT: blr ; LARGE32-NEXT: blr
; ;
; SMALL64-LABEL: storesTWInit: ; SMALL64-LABEL: storesTWInit:
; SMALL64: # %bb.0: # %entry ; SMALL64: # %bb.0: # %entry
; SMALL64-NEXT: mflr 0 ; SMALL64-NEXT: mflr 0
; SMALL64-NEXT: std 0, 16(1)
; SMALL64-NEXT: stdu 1, -48(1) ; SMALL64-NEXT: stdu 1, -48(1)
; SMALL64-NEXT: ld 3, L..C6(2) ; SMALL64-NEXT: ld 3, L..C6(2) # target-flags(ppc-lo) @TWInit
; SMALL64-NEXT: ld 4, L..C7(2) ; SMALL64-NEXT: ld 4, L..C7(2) # target-flags(ppc-tlsgd) @TWInit
; SMALL64-NEXT: std 0, 64(1)
; SMALL64-NEXT: bla .__tls_get_addr[PR] ; SMALL64-NEXT: bla .__tls_get_addr[PR]
; SMALL64-NEXT: stfd 1, 0(3) ; SMALL64-NEXT: stfd 1, 0(3)
; SMALL64-NEXT: addi 1, 1, 48 ; SMALL64-NEXT: addi 1, 1, 48
; SMALL64-NEXT: ld 0, 16(1) ; SMALL64-NEXT: ld 0, 16(1)
; SMALL64-NEXT: mtlr 0 ; SMALL64-NEXT: mtlr 0
; SMALL64-NEXT: blr ; SMALL64-NEXT: blr
; ;
; LARGE64-LABEL: storesTWInit: ; LARGE64-LABEL: storesTWInit:
; LARGE64: # %bb.0: # %entry ; LARGE64: # %bb.0: # %entry
; LARGE64-NEXT: mflr 0 ; LARGE64-NEXT: mflr 0
; LARGE64-NEXT: std 0, 16(1)
; LARGE64-NEXT: stdu 1, -48(1) ; LARGE64-NEXT: stdu 1, -48(1)
; LARGE64-NEXT: addis 3, L..C6@u(2) ; LARGE64-NEXT: addis 3, L..C6@u(2)
; LARGE64-NEXT: addis 4, L..C7@u(2) ; LARGE64-NEXT: addis 4, L..C7@u(2)
; LARGE64-NEXT: std 0, 64(1)
; LARGE64-NEXT: ld 3, L..C6@l(3) ; LARGE64-NEXT: ld 3, L..C6@l(3)
; LARGE64-NEXT: ld 4, L..C7@l(4) ; LARGE64-NEXT: ld 4, L..C7@l(4)
; LARGE64-NEXT: bla .__tls_get_addr[PR] ; LARGE64-NEXT: bla .__tls_get_addr[PR]
; LARGE64-NEXT: stfd 1, 0(3) ; LARGE64-NEXT: stfd 1, 0(3)
; LARGE64-NEXT: addi 1, 1, 48 ; LARGE64-NEXT: addi 1, 1, 48
; LARGE64-NEXT: ld 0, 16(1) ; LARGE64-NEXT: ld 0, 16(1)
; LARGE64-NEXT: mtlr 0 ; LARGE64-NEXT: mtlr 0
; LARGE64-NEXT: blr ; LARGE64-NEXT: blr
entry: entry:
store double %Val, ptr @TWInit, align 8 store double %Val, ptr @TWInit, align 8
ret void ret void
} }
; Function Attrs: norecurse nounwind readonly willreturn ; Function Attrs: norecurse nounwind readonly willreturn
define double @loadsTGUninit() #1 { define double @loadsTGUninit() #1 {
; SMALL32-LABEL: loadsTGUninit: ; SMALL32-LABEL: loadsTGUninit:
; SMALL32: # %bb.0: # %entry ; SMALL32: # %bb.0: # %entry
; SMALL32-NEXT: mflr 0 ; SMALL32-NEXT: mflr 0
; SMALL32-NEXT: stw 0, 8(1)
; SMALL32-NEXT: stwu 1, -32(1) ; SMALL32-NEXT: stwu 1, -32(1)
; SMALL32-NEXT: lwz 3, L..C0(2) ; SMALL32-NEXT: lwz 3, L..C0(2) # target-flags(ppc-lo) @TGUninit
; SMALL32-NEXT: lwz 4, L..C1(2) ; SMALL32-NEXT: lwz 4, L..C1(2) # target-flags(ppc-tlsgd) @TGUninit
; SMALL32-NEXT: stw 0, 40(1)
; SMALL32-NEXT: bla .__tls_get_addr[PR] ; SMALL32-NEXT: bla .__tls_get_addr[PR]
; SMALL32-NEXT: lwz 4, L..C8(2) ; SMALL32-NEXT: lwz 4, L..C8(2) # @GInit
; SMALL32-NEXT: lfd 0, 0(3) ; SMALL32-NEXT: lfd 0, 0(3)
; SMALL32-NEXT: lfd 1, 0(4) ; SMALL32-NEXT: lfd 1, 0(4)
; SMALL32-NEXT: fadd 1, 0, 1 ; SMALL32-NEXT: fadd 1, 0, 1
; SMALL32-NEXT: addi 1, 1, 32 ; SMALL32-NEXT: addi 1, 1, 32
; SMALL32-NEXT: lwz 0, 8(1) ; SMALL32-NEXT: lwz 0, 8(1)
; SMALL32-NEXT: mtlr 0 ; SMALL32-NEXT: mtlr 0
; SMALL32-NEXT: blr ; SMALL32-NEXT: blr
; ;
; LARGE32-LABEL: loadsTGUninit: ; LARGE32-LABEL: loadsTGUninit:
; LARGE32: # %bb.0: # %entry ; LARGE32: # %bb.0: # %entry
; LARGE32-NEXT: mflr 0 ; LARGE32-NEXT: mflr 0
; LARGE32-NEXT: stw 0, 8(1)
; LARGE32-NEXT: stwu 1, -32(1) ; LARGE32-NEXT: stwu 1, -32(1)
; LARGE32-NEXT: stw 0, 40(1)
; LARGE32-NEXT: addis 3, L..C0@u(2) ; LARGE32-NEXT: addis 3, L..C0@u(2)
; LARGE32-NEXT: addis 4, L..C1@u(2) ; LARGE32-NEXT: addis 4, L..C1@u(2)
; LARGE32-NEXT: lwz 3, L..C0@l(3) ; LARGE32-NEXT: lwz 3, L..C0@l(3)
; LARGE32-NEXT: lwz 4, L..C1@l(4) ; LARGE32-NEXT: lwz 4, L..C1@l(4)
; LARGE32-NEXT: bla .__tls_get_addr[PR] ; LARGE32-NEXT: bla .__tls_get_addr[PR]
; LARGE32-NEXT: lfd 0, 0(3) ; LARGE32-NEXT: lfd 0, 0(3)
; LARGE32-NEXT: addis 3, L..C8@u(2) ; LARGE32-NEXT: addis 3, L..C8@u(2)
; LARGE32-NEXT: lwz 3, L..C8@l(3) ; LARGE32-NEXT: lwz 3, L..C8@l(3)
; LARGE32-NEXT: lfd 1, 0(3) ; LARGE32-NEXT: lfd 1, 0(3)
; LARGE32-NEXT: fadd 1, 0, 1 ; LARGE32-NEXT: fadd 1, 0, 1
; LARGE32-NEXT: addi 1, 1, 32 ; LARGE32-NEXT: addi 1, 1, 32
; LARGE32-NEXT: lwz 0, 8(1) ; LARGE32-NEXT: lwz 0, 8(1)
; LARGE32-NEXT: mtlr 0 ; LARGE32-NEXT: mtlr 0
; LARGE32-NEXT: blr ; LARGE32-NEXT: blr
; ;
; SMALL64-LABEL: loadsTGUninit: ; SMALL64-LABEL: loadsTGUninit:
; SMALL64: # %bb.0: # %entry ; SMALL64: # %bb.0: # %entry
; SMALL64-NEXT: mflr 0 ; SMALL64-NEXT: mflr 0
; SMALL64-NEXT: std 0, 16(1)
; SMALL64-NEXT: stdu 1, -48(1) ; SMALL64-NEXT: stdu 1, -48(1)
; SMALL64-NEXT: ld 3, L..C0(2) ; SMALL64-NEXT: ld 3, L..C0(2) # target-flags(ppc-lo) @TGUninit
; SMALL64-NEXT: ld 4, L..C1(2) ; SMALL64-NEXT: ld 4, L..C1(2) # target-flags(ppc-tlsgd) @TGUninit
; SMALL64-NEXT: std 0, 64(1)
; SMALL64-NEXT: bla .__tls_get_addr[PR] ; SMALL64-NEXT: bla .__tls_get_addr[PR]
; SMALL64-NEXT: ld 4, L..C8(2) ; SMALL64-NEXT: ld 4, L..C8(2) # @GInit
; SMALL64-NEXT: lfd 0, 0(3) ; SMALL64-NEXT: lfd 0, 0(3)
; SMALL64-NEXT: lfd 1, 0(4) ; SMALL64-NEXT: lfd 1, 0(4)
; SMALL64-NEXT: fadd 1, 0, 1 ; SMALL64-NEXT: fadd 1, 0, 1
; SMALL64-NEXT: addi 1, 1, 48 ; SMALL64-NEXT: addi 1, 1, 48
; SMALL64-NEXT: ld 0, 16(1) ; SMALL64-NEXT: ld 0, 16(1)
; SMALL64-NEXT: mtlr 0 ; SMALL64-NEXT: mtlr 0
; SMALL64-NEXT: blr ; SMALL64-NEXT: blr
; ;
; LARGE64-LABEL: loadsTGUninit: ; LARGE64-LABEL: loadsTGUninit:
; LARGE64: # %bb.0: # %entry ; LARGE64: # %bb.0: # %entry
; LARGE64-NEXT: mflr 0 ; LARGE64-NEXT: mflr 0
; LARGE64-NEXT: std 0, 16(1)
; LARGE64-NEXT: stdu 1, -48(1) ; LARGE64-NEXT: stdu 1, -48(1)
; LARGE64-NEXT: addis 3, L..C0@u(2) ; LARGE64-NEXT: addis 3, L..C0@u(2)
; LARGE64-NEXT: addis 4, L..C1@u(2) ; LARGE64-NEXT: addis 4, L..C1@u(2)
; LARGE64-NEXT: std 0, 64(1)
; LARGE64-NEXT: ld 3, L..C0@l(3) ; LARGE64-NEXT: ld 3, L..C0@l(3)
; LARGE64-NEXT: ld 4, L..C1@l(4) ; LARGE64-NEXT: ld 4, L..C1@l(4)
; LARGE64-NEXT: bla .__tls_get_addr[PR] ; LARGE64-NEXT: bla .__tls_get_addr[PR]
; LARGE64-NEXT: addis 4, L..C8@u(2) ; LARGE64-NEXT: addis 4, L..C8@u(2)
; LARGE64-NEXT: lfd 0, 0(3) ; LARGE64-NEXT: lfd 0, 0(3)
; LARGE64-NEXT: ld 3, L..C8@l(4) ; LARGE64-NEXT: ld 3, L..C8@l(4)
; LARGE64-NEXT: lfd 1, 0(3) ; LARGE64-NEXT: lfd 1, 0(3)
; LARGE64-NEXT: fadd 1, 0, 1 ; LARGE64-NEXT: fadd 1, 0, 1
; LARGE64-NEXT: addi 1, 1, 48 ; LARGE64-NEXT: addi 1, 1, 48
; LARGE64-NEXT: ld 0, 16(1) ; LARGE64-NEXT: ld 0, 16(1)
; LARGE64-NEXT: mtlr 0 ; LARGE64-NEXT: mtlr 0
; LARGE64-NEXT: blr ; LARGE64-NEXT: blr
entry: entry:
%0 = load double, ptr @TGUninit, align 8 %0 = load double, ptr @TGUninit, align 8
%1 = load double, ptr @GInit, align 8 %1 = load double, ptr @GInit, align 8
%add = fadd double %0, %1 %add = fadd double %0, %1
ret double %add ret double %add
} }
; Function Attrs: norecurse nounwind readonly willreturn ; Function Attrs: norecurse nounwind readonly willreturn
define double @loadsTGInit() #1 { define double @loadsTGInit() #1 {
; SMALL32-LABEL: loadsTGInit: ; SMALL32-LABEL: loadsTGInit:
; SMALL32: # %bb.0: # %entry ; SMALL32: # %bb.0: # %entry
; SMALL32-NEXT: mflr 0 ; SMALL32-NEXT: mflr 0
; SMALL32-NEXT: stw 0, 8(1)
; SMALL32-NEXT: stwu 1, -32(1) ; SMALL32-NEXT: stwu 1, -32(1)
; SMALL32-NEXT: lwz 3, L..C2(2) ; SMALL32-NEXT: lwz 3, L..C2(2) # target-flags(ppc-lo) @TGInit
; SMALL32-NEXT: lwz 4, L..C3(2) ; SMALL32-NEXT: lwz 4, L..C3(2) # target-flags(ppc-tlsgd) @TGInit
; SMALL32-NEXT: stw 0, 40(1)
; SMALL32-NEXT: bla .__tls_get_addr[PR] ; SMALL32-NEXT: bla .__tls_get_addr[PR]
; SMALL32-NEXT: lwz 4, L..C8(2) ; SMALL32-NEXT: lwz 4, L..C8(2) # @GInit
; SMALL32-NEXT: lfd 0, 0(3) ; SMALL32-NEXT: lfd 0, 0(3)
; SMALL32-NEXT: lfd 1, 0(4) ; SMALL32-NEXT: lfd 1, 0(4)
; SMALL32-NEXT: fadd 1, 0, 1 ; SMALL32-NEXT: fadd 1, 0, 1
; SMALL32-NEXT: addi 1, 1, 32 ; SMALL32-NEXT: addi 1, 1, 32
; SMALL32-NEXT: lwz 0, 8(1) ; SMALL32-NEXT: lwz 0, 8(1)
; SMALL32-NEXT: mtlr 0 ; SMALL32-NEXT: mtlr 0
; SMALL32-NEXT: blr ; SMALL32-NEXT: blr
; ;
; LARGE32-LABEL: loadsTGInit: ; LARGE32-LABEL: loadsTGInit:
; LARGE32: # %bb.0: # %entry ; LARGE32: # %bb.0: # %entry
; LARGE32-NEXT: mflr 0 ; LARGE32-NEXT: mflr 0
; LARGE32-NEXT: stw 0, 8(1)
; LARGE32-NEXT: stwu 1, -32(1) ; LARGE32-NEXT: stwu 1, -32(1)
; LARGE32-NEXT: stw 0, 40(1)
; LARGE32-NEXT: addis 3, L..C2@u(2) ; LARGE32-NEXT: addis 3, L..C2@u(2)
; LARGE32-NEXT: addis 4, L..C3@u(2) ; LARGE32-NEXT: addis 4, L..C3@u(2)
; LARGE32-NEXT: lwz 3, L..C2@l(3) ; LARGE32-NEXT: lwz 3, L..C2@l(3)
; LARGE32-NEXT: lwz 4, L..C3@l(4) ; LARGE32-NEXT: lwz 4, L..C3@l(4)
; LARGE32-NEXT: bla .__tls_get_addr[PR] ; LARGE32-NEXT: bla .__tls_get_addr[PR]
; LARGE32-NEXT: lfd 0, 0(3) ; LARGE32-NEXT: lfd 0, 0(3)
; LARGE32-NEXT: addis 3, L..C8@u(2) ; LARGE32-NEXT: addis 3, L..C8@u(2)
; LARGE32-NEXT: lwz 3, L..C8@l(3) ; LARGE32-NEXT: lwz 3, L..C8@l(3)
; LARGE32-NEXT: lfd 1, 0(3) ; LARGE32-NEXT: lfd 1, 0(3)
; LARGE32-NEXT: fadd 1, 0, 1 ; LARGE32-NEXT: fadd 1, 0, 1
; LARGE32-NEXT: addi 1, 1, 32 ; LARGE32-NEXT: addi 1, 1, 32
; LARGE32-NEXT: lwz 0, 8(1) ; LARGE32-NEXT: lwz 0, 8(1)
; LARGE32-NEXT: mtlr 0 ; LARGE32-NEXT: mtlr 0
; LARGE32-NEXT: blr ; LARGE32-NEXT: blr
; ;
; SMALL64-LABEL: loadsTGInit: ; SMALL64-LABEL: loadsTGInit:
; SMALL64: # %bb.0: # %entry ; SMALL64: # %bb.0: # %entry
; SMALL64-NEXT: mflr 0 ; SMALL64-NEXT: mflr 0
; SMALL64-NEXT: std 0, 16(1)
; SMALL64-NEXT: stdu 1, -48(1) ; SMALL64-NEXT: stdu 1, -48(1)
; SMALL64-NEXT: ld 3, L..C2(2) ; SMALL64-NEXT: ld 3, L..C2(2) # target-flags(ppc-lo) @TGInit
; SMALL64-NEXT: ld 4, L..C3(2) ; SMALL64-NEXT: ld 4, L..C3(2) # target-flags(ppc-tlsgd) @TGInit
; SMALL64-NEXT: std 0, 64(1)
; SMALL64-NEXT: bla .__tls_get_addr[PR] ; SMALL64-NEXT: bla .__tls_get_addr[PR]
; SMALL64-NEXT: ld 4, L..C8(2) ; SMALL64-NEXT: ld 4, L..C8(2) # @GInit
; SMALL64-NEXT: lfd 0, 0(3) ; SMALL64-NEXT: lfd 0, 0(3)
; SMALL64-NEXT: lfd 1, 0(4) ; SMALL64-NEXT: lfd 1, 0(4)
; SMALL64-NEXT: fadd 1, 0, 1 ; SMALL64-NEXT: fadd 1, 0, 1
; SMALL64-NEXT: addi 1, 1, 48 ; SMALL64-NEXT: addi 1, 1, 48
; SMALL64-NEXT: ld 0, 16(1) ; SMALL64-NEXT: ld 0, 16(1)
; SMALL64-NEXT: mtlr 0 ; SMALL64-NEXT: mtlr 0
; SMALL64-NEXT: blr ; SMALL64-NEXT: blr
; ;
; LARGE64-LABEL: loadsTGInit: ; LARGE64-LABEL: loadsTGInit:
; LARGE64: # %bb.0: # %entry ; LARGE64: # %bb.0: # %entry
; LARGE64-NEXT: mflr 0 ; LARGE64-NEXT: mflr 0
; LARGE64-NEXT: std 0, 16(1)
; LARGE64-NEXT: stdu 1, -48(1) ; LARGE64-NEXT: stdu 1, -48(1)
; LARGE64-NEXT: addis 3, L..C2@u(2) ; LARGE64-NEXT: addis 3, L..C2@u(2)
; LARGE64-NEXT: addis 4, L..C3@u(2) ; LARGE64-NEXT: addis 4, L..C3@u(2)
; LARGE64-NEXT: std 0, 64(1)
; LARGE64-NEXT: ld 3, L..C2@l(3) ; LARGE64-NEXT: ld 3, L..C2@l(3)
; LARGE64-NEXT: ld 4, L..C3@l(4) ; LARGE64-NEXT: ld 4, L..C3@l(4)
; LARGE64-NEXT: bla .__tls_get_addr[PR] ; LARGE64-NEXT: bla .__tls_get_addr[PR]
; LARGE64-NEXT: addis 4, L..C8@u(2) ; LARGE64-NEXT: addis 4, L..C8@u(2)
; LARGE64-NEXT: lfd 0, 0(3) ; LARGE64-NEXT: lfd 0, 0(3)
; LARGE64-NEXT: ld 3, L..C8@l(4) ; LARGE64-NEXT: ld 3, L..C8@l(4)
; LARGE64-NEXT: lfd 1, 0(3) ; LARGE64-NEXT: lfd 1, 0(3)
; LARGE64-NEXT: fadd 1, 0, 1 ; LARGE64-NEXT: fadd 1, 0, 1
; LARGE64-NEXT: addi 1, 1, 48 ; LARGE64-NEXT: addi 1, 1, 48
; LARGE64-NEXT: ld 0, 16(1) ; LARGE64-NEXT: ld 0, 16(1)
; LARGE64-NEXT: mtlr 0 ; LARGE64-NEXT: mtlr 0
; LARGE64-NEXT: blr ; LARGE64-NEXT: blr
entry: entry:
%0 = load double, ptr @TGInit, align 8 %0 = load double, ptr @TGInit, align 8
%1 = load double, ptr @GInit, align 8 %1 = load double, ptr @GInit, align 8
%add = fadd double %0, %1 %add = fadd double %0, %1
ret double %add ret double %add
} }
; Function Attrs: norecurse nounwind readonly willreturn ; Function Attrs: norecurse nounwind readonly willreturn
define double @loadsTIInit() #1 { define double @loadsTIInit() #1 {
; SMALL32-LABEL: loadsTIInit: ; SMALL32-LABEL: loadsTIInit:
; SMALL32: # %bb.0: # %entry ; SMALL32: # %bb.0: # %entry
; SMALL32-NEXT: mflr 0 ; SMALL32-NEXT: mflr 0
; SMALL32-NEXT: stw 0, 8(1)
; SMALL32-NEXT: stwu 1, -32(1) ; SMALL32-NEXT: stwu 1, -32(1)
; SMALL32-NEXT: lwz 3, L..C4(2) ; SMALL32-NEXT: lwz 3, L..C4(2) # target-flags(ppc-lo) @TIInit
; SMALL32-NEXT: lwz 4, L..C5(2) ; SMALL32-NEXT: lwz 4, L..C5(2) # target-flags(ppc-tlsgd) @TIInit
; SMALL32-NEXT: stw 0, 40(1)
; SMALL32-NEXT: bla .__tls_get_addr[PR] ; SMALL32-NEXT: bla .__tls_get_addr[PR]
; SMALL32-NEXT: lwz 4, L..C8(2) ; SMALL32-NEXT: lwz 4, L..C8(2) # @GInit
; SMALL32-NEXT: lfd 0, 0(3) ; SMALL32-NEXT: lfd 0, 0(3)
; SMALL32-NEXT: lfd 1, 0(4) ; SMALL32-NEXT: lfd 1, 0(4)
; SMALL32-NEXT: fadd 1, 0, 1 ; SMALL32-NEXT: fadd 1, 0, 1
; SMALL32-NEXT: addi 1, 1, 32 ; SMALL32-NEXT: addi 1, 1, 32
; SMALL32-NEXT: lwz 0, 8(1) ; SMALL32-NEXT: lwz 0, 8(1)
; SMALL32-NEXT: mtlr 0 ; SMALL32-NEXT: mtlr 0
; SMALL32-NEXT: blr ; SMALL32-NEXT: blr
; ;
; LARGE32-LABEL: loadsTIInit: ; LARGE32-LABEL: loadsTIInit:
; LARGE32: # %bb.0: # %entry ; LARGE32: # %bb.0: # %entry
; LARGE32-NEXT: mflr 0 ; LARGE32-NEXT: mflr 0
; LARGE32-NEXT: stw 0, 8(1)
; LARGE32-NEXT: stwu 1, -32(1) ; LARGE32-NEXT: stwu 1, -32(1)
; LARGE32-NEXT: stw 0, 40(1)
; LARGE32-NEXT: addis 3, L..C4@u(2) ; LARGE32-NEXT: addis 3, L..C4@u(2)
; LARGE32-NEXT: addis 4, L..C5@u(2) ; LARGE32-NEXT: addis 4, L..C5@u(2)
; LARGE32-NEXT: lwz 3, L..C4@l(3) ; LARGE32-NEXT: lwz 3, L..C4@l(3)
; LARGE32-NEXT: lwz 4, L..C5@l(4) ; LARGE32-NEXT: lwz 4, L..C5@l(4)
; LARGE32-NEXT: bla .__tls_get_addr[PR] ; LARGE32-NEXT: bla .__tls_get_addr[PR]
; LARGE32-NEXT: lfd 0, 0(3) ; LARGE32-NEXT: lfd 0, 0(3)
; LARGE32-NEXT: addis 3, L..C8@u(2) ; LARGE32-NEXT: addis 3, L..C8@u(2)
; LARGE32-NEXT: lwz 3, L..C8@l(3) ; LARGE32-NEXT: lwz 3, L..C8@l(3)
; LARGE32-NEXT: lfd 1, 0(3) ; LARGE32-NEXT: lfd 1, 0(3)
; LARGE32-NEXT: fadd 1, 0, 1 ; LARGE32-NEXT: fadd 1, 0, 1
; LARGE32-NEXT: addi 1, 1, 32 ; LARGE32-NEXT: addi 1, 1, 32
; LARGE32-NEXT: lwz 0, 8(1) ; LARGE32-NEXT: lwz 0, 8(1)
; LARGE32-NEXT: mtlr 0 ; LARGE32-NEXT: mtlr 0
; LARGE32-NEXT: blr ; LARGE32-NEXT: blr
; ;
; SMALL64-LABEL: loadsTIInit: ; SMALL64-LABEL: loadsTIInit:
; SMALL64: # %bb.0: # %entry ; SMALL64: # %bb.0: # %entry
; SMALL64-NEXT: mflr 0 ; SMALL64-NEXT: mflr 0
; SMALL64-NEXT: std 0, 16(1)
; SMALL64-NEXT: stdu 1, -48(1) ; SMALL64-NEXT: stdu 1, -48(1)
; SMALL64-NEXT: ld 3, L..C4(2) ; SMALL64-NEXT: ld 3, L..C4(2) # target-flags(ppc-lo) @TIInit
; SMALL64-NEXT: ld 4, L..C5(2) ; SMALL64-NEXT: ld 4, L..C5(2) # target-flags(ppc-tlsgd) @TIInit
; SMALL64-NEXT: std 0, 64(1)
; SMALL64-NEXT: bla .__tls_get_addr[PR] ; SMALL64-NEXT: bla .__tls_get_addr[PR]
; SMALL64-NEXT: ld 4, L..C8(2) ; SMALL64-NEXT: ld 4, L..C8(2) # @GInit
; SMALL64-NEXT: lfd 0, 0(3) ; SMALL64-NEXT: lfd 0, 0(3)
; SMALL64-NEXT: lfd 1, 0(4) ; SMALL64-NEXT: lfd 1, 0(4)
; SMALL64-NEXT: fadd 1, 0, 1 ; SMALL64-NEXT: fadd 1, 0, 1
; SMALL64-NEXT: addi 1, 1, 48 ; SMALL64-NEXT: addi 1, 1, 48
; SMALL64-NEXT: ld 0, 16(1) ; SMALL64-NEXT: ld 0, 16(1)
; SMALL64-NEXT: mtlr 0 ; SMALL64-NEXT: mtlr 0
; SMALL64-NEXT: blr ; SMALL64-NEXT: blr
; ;
; LARGE64-LABEL: loadsTIInit: ; LARGE64-LABEL: loadsTIInit:
; LARGE64: # %bb.0: # %entry ; LARGE64: # %bb.0: # %entry
; LARGE64-NEXT: mflr 0 ; LARGE64-NEXT: mflr 0
; LARGE64-NEXT: std 0, 16(1)
; LARGE64-NEXT: stdu 1, -48(1) ; LARGE64-NEXT: stdu 1, -48(1)
; LARGE64-NEXT: addis 3, L..C4@u(2) ; LARGE64-NEXT: addis 3, L..C4@u(2)
; LARGE64-NEXT: addis 4, L..C5@u(2) ; LARGE64-NEXT: addis 4, L..C5@u(2)
; LARGE64-NEXT: std 0, 64(1)
; LARGE64-NEXT: ld 3, L..C4@l(3) ; LARGE64-NEXT: ld 3, L..C4@l(3)
; LARGE64-NEXT: ld 4, L..C5@l(4) ; LARGE64-NEXT: ld 4, L..C5@l(4)
; LARGE64-NEXT: bla .__tls_get_addr[PR] ; LARGE64-NEXT: bla .__tls_get_addr[PR]
; LARGE64-NEXT: addis 4, L..C8@u(2) ; LARGE64-NEXT: addis 4, L..C8@u(2)
; LARGE64-NEXT: lfd 0, 0(3) ; LARGE64-NEXT: lfd 0, 0(3)
; LARGE64-NEXT: ld 3, L..C8@l(4) ; LARGE64-NEXT: ld 3, L..C8@l(4)
; LARGE64-NEXT: lfd 1, 0(3) ; LARGE64-NEXT: lfd 1, 0(3)
; LARGE64-NEXT: fadd 1, 0, 1 ; LARGE64-NEXT: fadd 1, 0, 1
; LARGE64-NEXT: addi 1, 1, 48 ; LARGE64-NEXT: addi 1, 1, 48
; LARGE64-NEXT: ld 0, 16(1) ; LARGE64-NEXT: ld 0, 16(1)
; LARGE64-NEXT: mtlr 0 ; LARGE64-NEXT: mtlr 0
; LARGE64-NEXT: blr ; LARGE64-NEXT: blr
entry: entry:
%0 = load double, ptr @TIInit, align 8 %0 = load double, ptr @TIInit, align 8
%1 = load double, ptr @GInit, align 8 %1 = load double, ptr @GInit, align 8
%add = fadd double %0, %1 %add = fadd double %0, %1
ret double %add ret double %add
} }
; Function Attrs: norecurse nounwind readonly willreturn ; Function Attrs: norecurse nounwind readonly willreturn
define double @loadsTWInit() #1 { define double @loadsTWInit() #1 {
; SMALL32-LABEL: loadsTWInit: ; SMALL32-LABEL: loadsTWInit:
; SMALL32: # %bb.0: # %entry ; SMALL32: # %bb.0: # %entry
; SMALL32-NEXT: mflr 0 ; SMALL32-NEXT: mflr 0
; SMALL32-NEXT: stw 0, 8(1)
; SMALL32-NEXT: stwu 1, -32(1) ; SMALL32-NEXT: stwu 1, -32(1)
; SMALL32-NEXT: lwz 3, L..C6(2) ; SMALL32-NEXT: lwz 3, L..C6(2) # target-flags(ppc-lo) @TWInit
; SMALL32-NEXT: lwz 4, L..C7(2) ; SMALL32-NEXT: lwz 4, L..C7(2) # target-flags(ppc-tlsgd) @TWInit
; SMALL32-NEXT: stw 0, 40(1)
; SMALL32-NEXT: bla .__tls_get_addr[PR] ; SMALL32-NEXT: bla .__tls_get_addr[PR]
; SMALL32-NEXT: lwz 4, L..C8(2) ; SMALL32-NEXT: lwz 4, L..C8(2) # @GInit
; SMALL32-NEXT: lfd 0, 0(3) ; SMALL32-NEXT: lfd 0, 0(3)
; SMALL32-NEXT: lfd 1, 0(4) ; SMALL32-NEXT: lfd 1, 0(4)
; SMALL32-NEXT: fadd 1, 0, 1 ; SMALL32-NEXT: fadd 1, 0, 1
; SMALL32-NEXT: addi 1, 1, 32 ; SMALL32-NEXT: addi 1, 1, 32
; SMALL32-NEXT: lwz 0, 8(1) ; SMALL32-NEXT: lwz 0, 8(1)
; SMALL32-NEXT: mtlr 0 ; SMALL32-NEXT: mtlr 0
; SMALL32-NEXT: blr ; SMALL32-NEXT: blr
; ;
; LARGE32-LABEL: loadsTWInit: ; LARGE32-LABEL: loadsTWInit:
; LARGE32: # %bb.0: # %entry ; LARGE32: # %bb.0: # %entry
; LARGE32-NEXT: mflr 0 ; LARGE32-NEXT: mflr 0
; LARGE32-NEXT: stw 0, 8(1)
; LARGE32-NEXT: stwu 1, -32(1) ; LARGE32-NEXT: stwu 1, -32(1)
; LARGE32-NEXT: stw 0, 40(1)
; LARGE32-NEXT: addis 3, L..C6@u(2) ; LARGE32-NEXT: addis 3, L..C6@u(2)
; LARGE32-NEXT: addis 4, L..C7@u(2) ; LARGE32-NEXT: addis 4, L..C7@u(2)
; LARGE32-NEXT: lwz 3, L..C6@l(3) ; LARGE32-NEXT: lwz 3, L..C6@l(3)
; LARGE32-NEXT: lwz 4, L..C7@l(4) ; LARGE32-NEXT: lwz 4, L..C7@l(4)
; LARGE32-NEXT: bla .__tls_get_addr[PR] ; LARGE32-NEXT: bla .__tls_get_addr[PR]
; LARGE32-NEXT: lfd 0, 0(3) ; LARGE32-NEXT: lfd 0, 0(3)
; LARGE32-NEXT: addis 3, L..C8@u(2) ; LARGE32-NEXT: addis 3, L..C8@u(2)
; LARGE32-NEXT: lwz 3, L..C8@l(3) ; LARGE32-NEXT: lwz 3, L..C8@l(3)
; LARGE32-NEXT: lfd 1, 0(3) ; LARGE32-NEXT: lfd 1, 0(3)
; LARGE32-NEXT: fadd 1, 0, 1 ; LARGE32-NEXT: fadd 1, 0, 1
; LARGE32-NEXT: addi 1, 1, 32 ; LARGE32-NEXT: addi 1, 1, 32
; LARGE32-NEXT: lwz 0, 8(1) ; LARGE32-NEXT: lwz 0, 8(1)
; LARGE32-NEXT: mtlr 0 ; LARGE32-NEXT: mtlr 0
; LARGE32-NEXT: blr ; LARGE32-NEXT: blr
; ;
; SMALL64-LABEL: loadsTWInit: ; SMALL64-LABEL: loadsTWInit:
; SMALL64: # %bb.0: # %entry ; SMALL64: # %bb.0: # %entry
; SMALL64-NEXT: mflr 0 ; SMALL64-NEXT: mflr 0
; SMALL64-NEXT: std 0, 16(1)
; SMALL64-NEXT: stdu 1, -48(1) ; SMALL64-NEXT: stdu 1, -48(1)
; SMALL64-NEXT: ld 3, L..C6(2) ; SMALL64-NEXT: ld 3, L..C6(2) # target-flags(ppc-lo) @TWInit
; SMALL64-NEXT: ld 4, L..C7(2) ; SMALL64-NEXT: ld 4, L..C7(2) # target-flags(ppc-tlsgd) @TWInit
; SMALL64-NEXT: std 0, 64(1)
; SMALL64-NEXT: bla .__tls_get_addr[PR] ; SMALL64-NEXT: bla .__tls_get_addr[PR]
; SMALL64-NEXT: ld 4, L..C8(2) ; SMALL64-NEXT: ld 4, L..C8(2) # @GInit
; SMALL64-NEXT: lfd 0, 0(3) ; SMALL64-NEXT: lfd 0, 0(3)
; SMALL64-NEXT: lfd 1, 0(4) ; SMALL64-NEXT: lfd 1, 0(4)
; SMALL64-NEXT: fadd 1, 0, 1 ; SMALL64-NEXT: fadd 1, 0, 1
; SMALL64-NEXT: addi 1, 1, 48 ; SMALL64-NEXT: addi 1, 1, 48
; SMALL64-NEXT: ld 0, 16(1) ; SMALL64-NEXT: ld 0, 16(1)
; SMALL64-NEXT: mtlr 0 ; SMALL64-NEXT: mtlr 0
; SMALL64-NEXT: blr ; SMALL64-NEXT: blr
; ;
; LARGE64-LABEL: loadsTWInit: ; LARGE64-LABEL: loadsTWInit:
; LARGE64: # %bb.0: # %entry ; LARGE64: # %bb.0: # %entry
; LARGE64-NEXT: mflr 0 ; LARGE64-NEXT: mflr 0
; LARGE64-NEXT: std 0, 16(1)
; LARGE64-NEXT: stdu 1, -48(1) ; LARGE64-NEXT: stdu 1, -48(1)
; LARGE64-NEXT: addis 3, L..C6@u(2) ; LARGE64-NEXT: addis 3, L..C6@u(2)
; LARGE64-NEXT: addis 4, L..C7@u(2) ; LARGE64-NEXT: addis 4, L..C7@u(2)
; LARGE64-NEXT: std 0, 64(1)
; LARGE64-NEXT: ld 3, L..C6@l(3) ; LARGE64-NEXT: ld 3, L..C6@l(3)
; LARGE64-NEXT: ld 4, L..C7@l(4) ; LARGE64-NEXT: ld 4, L..C7@l(4)
; LARGE64-NEXT: bla .__tls_get_addr[PR] ; LARGE64-NEXT: bla .__tls_get_addr[PR]
; LARGE64-NEXT: addis 4, L..C8@u(2) ; LARGE64-NEXT: addis 4, L..C8@u(2)
; LARGE64-NEXT: lfd 0, 0(3) ; LARGE64-NEXT: lfd 0, 0(3)
; LARGE64-NEXT: ld 3, L..C8@l(4) ; LARGE64-NEXT: ld 3, L..C8@l(4)
; LARGE64-NEXT: lfd 1, 0(3) ; LARGE64-NEXT: lfd 1, 0(3)
; LARGE64-NEXT: fadd 1, 0, 1 ; LARGE64-NEXT: fadd 1, 0, 1
▲ Show 20 Lines • Show All 103 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/aix-tls-gd-int.ll

Show All 16 Lines
@TIUninit = internal thread_local global i32 0, align 4 @TIUninit = internal thread_local global i32 0, align 4
@TWUninit = weak thread_local global i32 0, align 4 @TWUninit = weak thread_local global i32 0, align 4
; Function Attrs: nofree norecurse nounwind willreturn writeonly ; Function Attrs: nofree norecurse nounwind willreturn writeonly
define void @storesTGUninit(i32 %Val) #0 { define void @storesTGUninit(i32 %Val) #0 {
; SMALL32-LABEL: storesTGUninit: ; SMALL32-LABEL: storesTGUninit:
; SMALL32: # %bb.0: # %entry ; SMALL32: # %bb.0: # %entry
; SMALL32-NEXT: mflr 0 ; SMALL32-NEXT: mflr 0
; SMALL32-NEXT: stw 0, 8(1)
; SMALL32-NEXT: stwu 1, -32(1) ; SMALL32-NEXT: stwu 1, -32(1)
; SMALL32-NEXT: mr 6, 3 ; SMALL32-NEXT: mr 6, 3
; SMALL32-NEXT: lwz 3, L..C0(2) ; SMALL32-NEXT: lwz 3, L..C0(2)
; SMALL32-NEXT: lwz 4, L..C1(2) ; SMALL32-NEXT: lwz 4, L..C1(2)
; SMALL32-NEXT: stw 0, 40(1)
; SMALL32-NEXT: bla .__tls_get_addr[PR] ; SMALL32-NEXT: bla .__tls_get_addr[PR]
; SMALL32-NEXT: stw 6, 0(3) ; SMALL32-NEXT: stw 6, 0(3)
; SMALL32-NEXT: addi 1, 1, 32 ; SMALL32-NEXT: addi 1, 1, 32
; SMALL32-NEXT: lwz 0, 8(1) ; SMALL32-NEXT: lwz 0, 8(1)
; SMALL32-NEXT: mtlr 0 ; SMALL32-NEXT: mtlr 0
; SMALL32-NEXT: blr ; SMALL32-NEXT: blr
; ;
; LARGE32-LABEL: storesTGUninit: ; LARGE32-LABEL: storesTGUninit:
; LARGE32: # %bb.0: # %entry ; LARGE32: # %bb.0: # %entry
; LARGE32-NEXT: mflr 0 ; LARGE32-NEXT: mflr 0
; LARGE32-NEXT: stw 0, 8(1)
; LARGE32-NEXT: stwu 1, -32(1) ; LARGE32-NEXT: stwu 1, -32(1)
; LARGE32-NEXT: stw 0, 40(1)
; LARGE32-NEXT: mr 6, 3 ; LARGE32-NEXT: mr 6, 3
; LARGE32-NEXT: addis 3, L..C0@u(2) ; LARGE32-NEXT: addis 3, L..C0@u(2)
; LARGE32-NEXT: addis 4, L..C1@u(2) ; LARGE32-NEXT: addis 4, L..C1@u(2)
; LARGE32-NEXT: lwz 3, L..C0@l(3) ; LARGE32-NEXT: lwz 3, L..C0@l(3)
; LARGE32-NEXT: lwz 4, L..C1@l(4) ; LARGE32-NEXT: lwz 4, L..C1@l(4)
; LARGE32-NEXT: bla .__tls_get_addr[PR] ; LARGE32-NEXT: bla .__tls_get_addr[PR]
; LARGE32-NEXT: stw 6, 0(3) ; LARGE32-NEXT: stw 6, 0(3)
; LARGE32-NEXT: addi 1, 1, 32 ; LARGE32-NEXT: addi 1, 1, 32
; LARGE32-NEXT: lwz 0, 8(1) ; LARGE32-NEXT: lwz 0, 8(1)
; LARGE32-NEXT: mtlr 0 ; LARGE32-NEXT: mtlr 0
; LARGE32-NEXT: blr ; LARGE32-NEXT: blr
; ;
; SMALL64-LABEL: storesTGUninit: ; SMALL64-LABEL: storesTGUninit:
; SMALL64: # %bb.0: # %entry ; SMALL64: # %bb.0: # %entry
; SMALL64-NEXT: mflr 0 ; SMALL64-NEXT: mflr 0
; SMALL64-NEXT: std 0, 16(1)
; SMALL64-NEXT: stdu 1, -48(1) ; SMALL64-NEXT: stdu 1, -48(1)
; SMALL64-NEXT: mr 6, 3 ; SMALL64-NEXT: mr 6, 3
; SMALL64-NEXT: ld 3, L..C0(2) ; SMALL64-NEXT: ld 3, L..C0(2)
; SMALL64-NEXT: ld 4, L..C1(2) ; SMALL64-NEXT: ld 4, L..C1(2)
; SMALL64-NEXT: std 0, 64(1)
; SMALL64-NEXT: bla .__tls_get_addr[PR] ; SMALL64-NEXT: bla .__tls_get_addr[PR]
; SMALL64-NEXT: stw 6, 0(3) ; SMALL64-NEXT: stw 6, 0(3)
; SMALL64-NEXT: addi 1, 1, 48 ; SMALL64-NEXT: addi 1, 1, 48
; SMALL64-NEXT: ld 0, 16(1) ; SMALL64-NEXT: ld 0, 16(1)
; SMALL64-NEXT: mtlr 0 ; SMALL64-NEXT: mtlr 0
; SMALL64-NEXT: blr ; SMALL64-NEXT: blr
; ;
; LARGE64-LABEL: storesTGUninit: ; LARGE64-LABEL: storesTGUninit:
; LARGE64: # %bb.0: # %entry ; LARGE64: # %bb.0: # %entry
; LARGE64-NEXT: mflr 0 ; LARGE64-NEXT: mflr 0
; LARGE64-NEXT: std 0, 16(1)
; LARGE64-NEXT: stdu 1, -48(1) ; LARGE64-NEXT: stdu 1, -48(1)
; LARGE64-NEXT: mr 6, 3 ; LARGE64-NEXT: mr 6, 3
; LARGE64-NEXT: addis 3, L..C0@u(2) ; LARGE64-NEXT: addis 3, L..C0@u(2)
; LARGE64-NEXT: addis 4, L..C1@u(2) ; LARGE64-NEXT: addis 4, L..C1@u(2)
; LARGE64-NEXT: std 0, 64(1)
; LARGE64-NEXT: ld 3, L..C0@l(3) ; LARGE64-NEXT: ld 3, L..C0@l(3)
; LARGE64-NEXT: ld 4, L..C1@l(4) ; LARGE64-NEXT: ld 4, L..C1@l(4)
; LARGE64-NEXT: bla .__tls_get_addr[PR] ; LARGE64-NEXT: bla .__tls_get_addr[PR]
; LARGE64-NEXT: stw 6, 0(3) ; LARGE64-NEXT: stw 6, 0(3)
; LARGE64-NEXT: addi 1, 1, 48 ; LARGE64-NEXT: addi 1, 1, 48
; LARGE64-NEXT: ld 0, 16(1) ; LARGE64-NEXT: ld 0, 16(1)
; LARGE64-NEXT: mtlr 0 ; LARGE64-NEXT: mtlr 0
; LARGE64-NEXT: blr ; LARGE64-NEXT: blr
entry: entry:
store i32 %Val, ptr @TGUninit, align 4 store i32 %Val, ptr @TGUninit, align 4
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind willreturn writeonly ; Function Attrs: nofree norecurse nounwind willreturn writeonly
define void @storesTGInit(i32 %Val) #0 { define void @storesTGInit(i32 %Val) #0 {
; SMALL32-LABEL: storesTGInit: ; SMALL32-LABEL: storesTGInit:
; SMALL32: # %bb.0: # %entry ; SMALL32: # %bb.0: # %entry
; SMALL32-NEXT: mflr 0 ; SMALL32-NEXT: mflr 0
; SMALL32-NEXT: stw 0, 8(1)
; SMALL32-NEXT: stwu 1, -32(1) ; SMALL32-NEXT: stwu 1, -32(1)
; SMALL32-NEXT: mr 6, 3 ; SMALL32-NEXT: mr 6, 3
; SMALL32-NEXT: lwz 3, L..C2(2) ; SMALL32-NEXT: lwz 3, L..C2(2)
; SMALL32-NEXT: lwz 4, L..C3(2) ; SMALL32-NEXT: lwz 4, L..C3(2)
; SMALL32-NEXT: stw 0, 40(1)
; SMALL32-NEXT: bla .__tls_get_addr[PR] ; SMALL32-NEXT: bla .__tls_get_addr[PR]
; SMALL32-NEXT: stw 6, 0(3) ; SMALL32-NEXT: stw 6, 0(3)
; SMALL32-NEXT: addi 1, 1, 32 ; SMALL32-NEXT: addi 1, 1, 32
; SMALL32-NEXT: lwz 0, 8(1) ; SMALL32-NEXT: lwz 0, 8(1)
; SMALL32-NEXT: mtlr 0 ; SMALL32-NEXT: mtlr 0
; SMALL32-NEXT: blr ; SMALL32-NEXT: blr
; ;
; LARGE32-LABEL: storesTGInit: ; LARGE32-LABEL: storesTGInit:
; LARGE32: # %bb.0: # %entry ; LARGE32: # %bb.0: # %entry
; LARGE32-NEXT: mflr 0 ; LARGE32-NEXT: mflr 0
; LARGE32-NEXT: stw 0, 8(1)
; LARGE32-NEXT: stwu 1, -32(1) ; LARGE32-NEXT: stwu 1, -32(1)
; LARGE32-NEXT: stw 0, 40(1)
; LARGE32-NEXT: mr 6, 3 ; LARGE32-NEXT: mr 6, 3
; LARGE32-NEXT: addis 3, L..C2@u(2) ; LARGE32-NEXT: addis 3, L..C2@u(2)
; LARGE32-NEXT: addis 4, L..C3@u(2) ; LARGE32-NEXT: addis 4, L..C3@u(2)
; LARGE32-NEXT: lwz 3, L..C2@l(3) ; LARGE32-NEXT: lwz 3, L..C2@l(3)
; LARGE32-NEXT: lwz 4, L..C3@l(4) ; LARGE32-NEXT: lwz 4, L..C3@l(4)
; LARGE32-NEXT: bla .__tls_get_addr[PR] ; LARGE32-NEXT: bla .__tls_get_addr[PR]
; LARGE32-NEXT: stw 6, 0(3) ; LARGE32-NEXT: stw 6, 0(3)
; LARGE32-NEXT: addi 1, 1, 32 ; LARGE32-NEXT: addi 1, 1, 32
; LARGE32-NEXT: lwz 0, 8(1) ; LARGE32-NEXT: lwz 0, 8(1)
; LARGE32-NEXT: mtlr 0 ; LARGE32-NEXT: mtlr 0
; LARGE32-NEXT: blr ; LARGE32-NEXT: blr
; ;
; SMALL64-LABEL: storesTGInit: ; SMALL64-LABEL: storesTGInit:
; SMALL64: # %bb.0: # %entry ; SMALL64: # %bb.0: # %entry
; SMALL64-NEXT: mflr 0 ; SMALL64-NEXT: mflr 0
; SMALL64-NEXT: std 0, 16(1)
; SMALL64-NEXT: stdu 1, -48(1) ; SMALL64-NEXT: stdu 1, -48(1)
; SMALL64-NEXT: mr 6, 3 ; SMALL64-NEXT: mr 6, 3
; SMALL64-NEXT: ld 3, L..C2(2) ; SMALL64-NEXT: ld 3, L..C2(2)
; SMALL64-NEXT: ld 4, L..C3(2) ; SMALL64-NEXT: ld 4, L..C3(2)
; SMALL64-NEXT: std 0, 64(1)
; SMALL64-NEXT: bla .__tls_get_addr[PR] ; SMALL64-NEXT: bla .__tls_get_addr[PR]
; SMALL64-NEXT: stw 6, 0(3) ; SMALL64-NEXT: stw 6, 0(3)
; SMALL64-NEXT: addi 1, 1, 48 ; SMALL64-NEXT: addi 1, 1, 48
; SMALL64-NEXT: ld 0, 16(1) ; SMALL64-NEXT: ld 0, 16(1)
; SMALL64-NEXT: mtlr 0 ; SMALL64-NEXT: mtlr 0
; SMALL64-NEXT: blr ; SMALL64-NEXT: blr
; ;
; LARGE64-LABEL: storesTGInit: ; LARGE64-LABEL: storesTGInit:
; LARGE64: # %bb.0: # %entry ; LARGE64: # %bb.0: # %entry
; LARGE64-NEXT: mflr 0 ; LARGE64-NEXT: mflr 0
; LARGE64-NEXT: std 0, 16(1)
; LARGE64-NEXT: stdu 1, -48(1) ; LARGE64-NEXT: stdu 1, -48(1)
; LARGE64-NEXT: mr 6, 3 ; LARGE64-NEXT: mr 6, 3
; LARGE64-NEXT: addis 3, L..C2@u(2) ; LARGE64-NEXT: addis 3, L..C2@u(2)
; LARGE64-NEXT: addis 4, L..C3@u(2) ; LARGE64-NEXT: addis 4, L..C3@u(2)
; LARGE64-NEXT: std 0, 64(1)
; LARGE64-NEXT: ld 3, L..C2@l(3) ; LARGE64-NEXT: ld 3, L..C2@l(3)
; LARGE64-NEXT: ld 4, L..C3@l(4) ; LARGE64-NEXT: ld 4, L..C3@l(4)
; LARGE64-NEXT: bla .__tls_get_addr[PR] ; LARGE64-NEXT: bla .__tls_get_addr[PR]
; LARGE64-NEXT: stw 6, 0(3) ; LARGE64-NEXT: stw 6, 0(3)
; LARGE64-NEXT: addi 1, 1, 48 ; LARGE64-NEXT: addi 1, 1, 48
; LARGE64-NEXT: ld 0, 16(1) ; LARGE64-NEXT: ld 0, 16(1)
; LARGE64-NEXT: mtlr 0 ; LARGE64-NEXT: mtlr 0
; LARGE64-NEXT: blr ; LARGE64-NEXT: blr
entry: entry:
store i32 %Val, ptr @TGInit, align 4 store i32 %Val, ptr @TGInit, align 4
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind willreturn writeonly ; Function Attrs: nofree norecurse nounwind willreturn writeonly
define void @storesTIUninit(i32 %Val) #0 { define void @storesTIUninit(i32 %Val) #0 {
; SMALL32-LABEL: storesTIUninit: ; SMALL32-LABEL: storesTIUninit:
; SMALL32: # %bb.0: # %entry ; SMALL32: # %bb.0: # %entry
; SMALL32-NEXT: mflr 0 ; SMALL32-NEXT: mflr 0
; SMALL32-NEXT: stw 0, 8(1)
; SMALL32-NEXT: stwu 1, -32(1) ; SMALL32-NEXT: stwu 1, -32(1)
; SMALL32-NEXT: mr 6, 3 ; SMALL32-NEXT: mr 6, 3
; SMALL32-NEXT: lwz 3, L..C4(2) ; SMALL32-NEXT: lwz 3, L..C4(2)
; SMALL32-NEXT: lwz 4, L..C5(2) ; SMALL32-NEXT: lwz 4, L..C5(2)
; SMALL32-NEXT: stw 0, 40(1)
; SMALL32-NEXT: bla .__tls_get_addr[PR] ; SMALL32-NEXT: bla .__tls_get_addr[PR]
; SMALL32-NEXT: stw 6, 0(3) ; SMALL32-NEXT: stw 6, 0(3)
; SMALL32-NEXT: addi 1, 1, 32 ; SMALL32-NEXT: addi 1, 1, 32
; SMALL32-NEXT: lwz 0, 8(1) ; SMALL32-NEXT: lwz 0, 8(1)
; SMALL32-NEXT: mtlr 0 ; SMALL32-NEXT: mtlr 0
; SMALL32-NEXT: blr ; SMALL32-NEXT: blr
; ;
; LARGE32-LABEL: storesTIUninit: ; LARGE32-LABEL: storesTIUninit:
; LARGE32: # %bb.0: # %entry ; LARGE32: # %bb.0: # %entry
; LARGE32-NEXT: mflr 0 ; LARGE32-NEXT: mflr 0
; LARGE32-NEXT: stw 0, 8(1)
; LARGE32-NEXT: stwu 1, -32(1) ; LARGE32-NEXT: stwu 1, -32(1)
; LARGE32-NEXT: stw 0, 40(1)
; LARGE32-NEXT: mr 6, 3 ; LARGE32-NEXT: mr 6, 3
; LARGE32-NEXT: addis 3, L..C4@u(2) ; LARGE32-NEXT: addis 3, L..C4@u(2)
; LARGE32-NEXT: addis 4, L..C5@u(2) ; LARGE32-NEXT: addis 4, L..C5@u(2)
; LARGE32-NEXT: lwz 3, L..C4@l(3) ; LARGE32-NEXT: lwz 3, L..C4@l(3)
; LARGE32-NEXT: lwz 4, L..C5@l(4) ; LARGE32-NEXT: lwz 4, L..C5@l(4)
; LARGE32-NEXT: bla .__tls_get_addr[PR] ; LARGE32-NEXT: bla .__tls_get_addr[PR]
; LARGE32-NEXT: stw 6, 0(3) ; LARGE32-NEXT: stw 6, 0(3)
; LARGE32-NEXT: addi 1, 1, 32 ; LARGE32-NEXT: addi 1, 1, 32
; LARGE32-NEXT: lwz 0, 8(1) ; LARGE32-NEXT: lwz 0, 8(1)
; LARGE32-NEXT: mtlr 0 ; LARGE32-NEXT: mtlr 0
; LARGE32-NEXT: blr ; LARGE32-NEXT: blr
; ;
; SMALL64-LABEL: storesTIUninit: ; SMALL64-LABEL: storesTIUninit:
; SMALL64: # %bb.0: # %entry ; SMALL64: # %bb.0: # %entry
; SMALL64-NEXT: mflr 0 ; SMALL64-NEXT: mflr 0
; SMALL64-NEXT: std 0, 16(1)
; SMALL64-NEXT: stdu 1, -48(1) ; SMALL64-NEXT: stdu 1, -48(1)
; SMALL64-NEXT: mr 6, 3 ; SMALL64-NEXT: mr 6, 3
; SMALL64-NEXT: ld 3, L..C4(2) ; SMALL64-NEXT: ld 3, L..C4(2)
; SMALL64-NEXT: ld 4, L..C5(2) ; SMALL64-NEXT: ld 4, L..C5(2)
; SMALL64-NEXT: std 0, 64(1)
; SMALL64-NEXT: bla .__tls_get_addr[PR] ; SMALL64-NEXT: bla .__tls_get_addr[PR]
; SMALL64-NEXT: stw 6, 0(3) ; SMALL64-NEXT: stw 6, 0(3)
; SMALL64-NEXT: addi 1, 1, 48 ; SMALL64-NEXT: addi 1, 1, 48
; SMALL64-NEXT: ld 0, 16(1) ; SMALL64-NEXT: ld 0, 16(1)
; SMALL64-NEXT: mtlr 0 ; SMALL64-NEXT: mtlr 0
; SMALL64-NEXT: blr ; SMALL64-NEXT: blr
; ;
; LARGE64-LABEL: storesTIUninit: ; LARGE64-LABEL: storesTIUninit:
; LARGE64: # %bb.0: # %entry ; LARGE64: # %bb.0: # %entry
; LARGE64-NEXT: mflr 0 ; LARGE64-NEXT: mflr 0
; LARGE64-NEXT: std 0, 16(1)
; LARGE64-NEXT: stdu 1, -48(1) ; LARGE64-NEXT: stdu 1, -48(1)
; LARGE64-NEXT: mr 6, 3 ; LARGE64-NEXT: mr 6, 3
; LARGE64-NEXT: addis 3, L..C4@u(2) ; LARGE64-NEXT: addis 3, L..C4@u(2)
; LARGE64-NEXT: addis 4, L..C5@u(2) ; LARGE64-NEXT: addis 4, L..C5@u(2)
; LARGE64-NEXT: std 0, 64(1)
; LARGE64-NEXT: ld 3, L..C4@l(3) ; LARGE64-NEXT: ld 3, L..C4@l(3)
; LARGE64-NEXT: ld 4, L..C5@l(4) ; LARGE64-NEXT: ld 4, L..C5@l(4)
; LARGE64-NEXT: bla .__tls_get_addr[PR] ; LARGE64-NEXT: bla .__tls_get_addr[PR]
; LARGE64-NEXT: stw 6, 0(3) ; LARGE64-NEXT: stw 6, 0(3)
; LARGE64-NEXT: addi 1, 1, 48 ; LARGE64-NEXT: addi 1, 1, 48
; LARGE64-NEXT: ld 0, 16(1) ; LARGE64-NEXT: ld 0, 16(1)
; LARGE64-NEXT: mtlr 0 ; LARGE64-NEXT: mtlr 0
; LARGE64-NEXT: blr ; LARGE64-NEXT: blr
entry: entry:
store i32 %Val, ptr @TIUninit, align 4 store i32 %Val, ptr @TIUninit, align 4
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind willreturn writeonly ; Function Attrs: nofree norecurse nounwind willreturn writeonly
define void @storesTWUninit(i32 %Val) #0 { define void @storesTWUninit(i32 %Val) #0 {
; SMALL32-LABEL: storesTWUninit: ; SMALL32-LABEL: storesTWUninit:
; SMALL32: # %bb.0: # %entry ; SMALL32: # %bb.0: # %entry
; SMALL32-NEXT: mflr 0 ; SMALL32-NEXT: mflr 0
; SMALL32-NEXT: stw 0, 8(1)
; SMALL32-NEXT: stwu 1, -32(1) ; SMALL32-NEXT: stwu 1, -32(1)
; SMALL32-NEXT: mr 6, 3 ; SMALL32-NEXT: mr 6, 3
; SMALL32-NEXT: lwz 3, L..C6(2) ; SMALL32-NEXT: lwz 3, L..C6(2)
; SMALL32-NEXT: lwz 4, L..C7(2) ; SMALL32-NEXT: lwz 4, L..C7(2)
; SMALL32-NEXT: stw 0, 40(1)
; SMALL32-NEXT: bla .__tls_get_addr[PR] ; SMALL32-NEXT: bla .__tls_get_addr[PR]
; SMALL32-NEXT: stw 6, 0(3) ; SMALL32-NEXT: stw 6, 0(3)
; SMALL32-NEXT: addi 1, 1, 32 ; SMALL32-NEXT: addi 1, 1, 32
; SMALL32-NEXT: lwz 0, 8(1) ; SMALL32-NEXT: lwz 0, 8(1)
; SMALL32-NEXT: mtlr 0 ; SMALL32-NEXT: mtlr 0
; SMALL32-NEXT: blr ; SMALL32-NEXT: blr
; ;
; LARGE32-LABEL: storesTWUninit: ; LARGE32-LABEL: storesTWUninit:
; LARGE32: # %bb.0: # %entry ; LARGE32: # %bb.0: # %entry
; LARGE32-NEXT: mflr 0 ; LARGE32-NEXT: mflr 0
; LARGE32-NEXT: stw 0, 8(1)
; LARGE32-NEXT: stwu 1, -32(1) ; LARGE32-NEXT: stwu 1, -32(1)
; LARGE32-NEXT: stw 0, 40(1)
; LARGE32-NEXT: mr 6, 3 ; LARGE32-NEXT: mr 6, 3
; LARGE32-NEXT: addis 3, L..C6@u(2) ; LARGE32-NEXT: addis 3, L..C6@u(2)
; LARGE32-NEXT: addis 4, L..C7@u(2) ; LARGE32-NEXT: addis 4, L..C7@u(2)
; LARGE32-NEXT: lwz 3, L..C6@l(3) ; LARGE32-NEXT: lwz 3, L..C6@l(3)
; LARGE32-NEXT: lwz 4, L..C7@l(4) ; LARGE32-NEXT: lwz 4, L..C7@l(4)
; LARGE32-NEXT: bla .__tls_get_addr[PR] ; LARGE32-NEXT: bla .__tls_get_addr[PR]
; LARGE32-NEXT: stw 6, 0(3) ; LARGE32-NEXT: stw 6, 0(3)
; LARGE32-NEXT: addi 1, 1, 32 ; LARGE32-NEXT: addi 1, 1, 32
; LARGE32-NEXT: lwz 0, 8(1) ; LARGE32-NEXT: lwz 0, 8(1)
; LARGE32-NEXT: mtlr 0 ; LARGE32-NEXT: mtlr 0
; LARGE32-NEXT: blr ; LARGE32-NEXT: blr
; ;
; SMALL64-LABEL: storesTWUninit: ; SMALL64-LABEL: storesTWUninit:
; SMALL64: # %bb.0: # %entry ; SMALL64: # %bb.0: # %entry
; SMALL64-NEXT: mflr 0 ; SMALL64-NEXT: mflr 0
; SMALL64-NEXT: std 0, 16(1)
; SMALL64-NEXT: stdu 1, -48(1) ; SMALL64-NEXT: stdu 1, -48(1)
; SMALL64-NEXT: mr 6, 3 ; SMALL64-NEXT: mr 6, 3
; SMALL64-NEXT: ld 3, L..C6(2) ; SMALL64-NEXT: ld 3, L..C6(2)
; SMALL64-NEXT: ld 4, L..C7(2) ; SMALL64-NEXT: ld 4, L..C7(2)
; SMALL64-NEXT: std 0, 64(1)
; SMALL64-NEXT: bla .__tls_get_addr[PR] ; SMALL64-NEXT: bla .__tls_get_addr[PR]
; SMALL64-NEXT: stw 6, 0(3) ; SMALL64-NEXT: stw 6, 0(3)
; SMALL64-NEXT: addi 1, 1, 48 ; SMALL64-NEXT: addi 1, 1, 48
; SMALL64-NEXT: ld 0, 16(1) ; SMALL64-NEXT: ld 0, 16(1)
; SMALL64-NEXT: mtlr 0 ; SMALL64-NEXT: mtlr 0
; SMALL64-NEXT: blr ; SMALL64-NEXT: blr
; ;
; LARGE64-LABEL: storesTWUninit: ; LARGE64-LABEL: storesTWUninit:
; LARGE64: # %bb.0: # %entry ; LARGE64: # %bb.0: # %entry
; LARGE64-NEXT: mflr 0 ; LARGE64-NEXT: mflr 0
; LARGE64-NEXT: std 0, 16(1)
; LARGE64-NEXT: stdu 1, -48(1) ; LARGE64-NEXT: stdu 1, -48(1)
; LARGE64-NEXT: mr 6, 3 ; LARGE64-NEXT: mr 6, 3
; LARGE64-NEXT: addis 3, L..C6@u(2) ; LARGE64-NEXT: addis 3, L..C6@u(2)
; LARGE64-NEXT: addis 4, L..C7@u(2) ; LARGE64-NEXT: addis 4, L..C7@u(2)
; LARGE64-NEXT: std 0, 64(1)
; LARGE64-NEXT: ld 3, L..C6@l(3) ; LARGE64-NEXT: ld 3, L..C6@l(3)
; LARGE64-NEXT: ld 4, L..C7@l(4) ; LARGE64-NEXT: ld 4, L..C7@l(4)
; LARGE64-NEXT: bla .__tls_get_addr[PR] ; LARGE64-NEXT: bla .__tls_get_addr[PR]
; LARGE64-NEXT: stw 6, 0(3) ; LARGE64-NEXT: stw 6, 0(3)
; LARGE64-NEXT: addi 1, 1, 48 ; LARGE64-NEXT: addi 1, 1, 48
; LARGE64-NEXT: ld 0, 16(1) ; LARGE64-NEXT: ld 0, 16(1)
; LARGE64-NEXT: mtlr 0 ; LARGE64-NEXT: mtlr 0
; LARGE64-NEXT: blr ; LARGE64-NEXT: blr
entry: entry:
store i32 %Val, ptr @TWUninit, align 4 store i32 %Val, ptr @TWUninit, align 4
ret void ret void
} }
; Function Attrs: norecurse nounwind readonly willreturn ; Function Attrs: norecurse nounwind readonly willreturn
define i32 @loadsTGUninit() #1 { define i32 @loadsTGUninit() #1 {
; SMALL32-LABEL: loadsTGUninit: ; SMALL32-LABEL: loadsTGUninit:
; SMALL32: # %bb.0: # %entry ; SMALL32: # %bb.0: # %entry
; SMALL32-NEXT: mflr 0 ; SMALL32-NEXT: mflr 0
; SMALL32-NEXT: stw 0, 8(1)
; SMALL32-NEXT: stwu 1, -32(1) ; SMALL32-NEXT: stwu 1, -32(1)
; SMALL32-NEXT: lwz 3, L..C0(2) ; SMALL32-NEXT: lwz 3, L..C0(2)
; SMALL32-NEXT: lwz 4, L..C1(2) ; SMALL32-NEXT: lwz 4, L..C1(2)
; SMALL32-NEXT: stw 0, 40(1)
; SMALL32-NEXT: bla .__tls_get_addr[PR] ; SMALL32-NEXT: bla .__tls_get_addr[PR]
; SMALL32-NEXT: lwz 4, L..C8(2) ; SMALL32-NEXT: lwz 4, L..C8(2)
; SMALL32-NEXT: lwz 3, 0(3) ; SMALL32-NEXT: lwz 3, 0(3)
; SMALL32-NEXT: lwz 4, 0(4) ; SMALL32-NEXT: lwz 4, 0(4)
; SMALL32-NEXT: add 3, 4, 3 ; SMALL32-NEXT: add 3, 4, 3
; SMALL32-NEXT: addi 1, 1, 32 ; SMALL32-NEXT: addi 1, 1, 32
; SMALL32-NEXT: lwz 0, 8(1) ; SMALL32-NEXT: lwz 0, 8(1)
; SMALL32-NEXT: mtlr 0 ; SMALL32-NEXT: mtlr 0
; SMALL32-NEXT: blr ; SMALL32-NEXT: blr
; ;
; LARGE32-LABEL: loadsTGUninit: ; LARGE32-LABEL: loadsTGUninit:
; LARGE32: # %bb.0: # %entry ; LARGE32: # %bb.0: # %entry
; LARGE32-NEXT: mflr 0 ; LARGE32-NEXT: mflr 0
; LARGE32-NEXT: stw 0, 8(1)
; LARGE32-NEXT: stwu 1, -32(1) ; LARGE32-NEXT: stwu 1, -32(1)
; LARGE32-NEXT: stw 0, 40(1)
; LARGE32-NEXT: addis 3, L..C0@u(2) ; LARGE32-NEXT: addis 3, L..C0@u(2)
; LARGE32-NEXT: addis 4, L..C1@u(2) ; LARGE32-NEXT: addis 4, L..C1@u(2)
; LARGE32-NEXT: lwz 3, L..C0@l(3) ; LARGE32-NEXT: lwz 3, L..C0@l(3)
; LARGE32-NEXT: lwz 4, L..C1@l(4) ; LARGE32-NEXT: lwz 4, L..C1@l(4)
; LARGE32-NEXT: bla .__tls_get_addr[PR] ; LARGE32-NEXT: bla .__tls_get_addr[PR]
; LARGE32-NEXT: lwz 3, 0(3) ; LARGE32-NEXT: lwz 3, 0(3)
; LARGE32-NEXT: addis 4, L..C8@u(2) ; LARGE32-NEXT: addis 4, L..C8@u(2)
; LARGE32-NEXT: lwz 4, L..C8@l(4) ; LARGE32-NEXT: lwz 4, L..C8@l(4)
; LARGE32-NEXT: lwz 4, 0(4) ; LARGE32-NEXT: lwz 4, 0(4)
; LARGE32-NEXT: add 3, 4, 3 ; LARGE32-NEXT: add 3, 4, 3
; LARGE32-NEXT: addi 1, 1, 32 ; LARGE32-NEXT: addi 1, 1, 32
; LARGE32-NEXT: lwz 0, 8(1) ; LARGE32-NEXT: lwz 0, 8(1)
; LARGE32-NEXT: mtlr 0 ; LARGE32-NEXT: mtlr 0
; LARGE32-NEXT: blr ; LARGE32-NEXT: blr
; ;
; SMALL64-LABEL: loadsTGUninit: ; SMALL64-LABEL: loadsTGUninit:
; SMALL64: # %bb.0: # %entry ; SMALL64: # %bb.0: # %entry
; SMALL64-NEXT: mflr 0 ; SMALL64-NEXT: mflr 0
; SMALL64-NEXT: std 0, 16(1)
; SMALL64-NEXT: stdu 1, -48(1) ; SMALL64-NEXT: stdu 1, -48(1)
; SMALL64-NEXT: ld 3, L..C0(2) ; SMALL64-NEXT: ld 3, L..C0(2)
; SMALL64-NEXT: ld 4, L..C1(2) ; SMALL64-NEXT: ld 4, L..C1(2)
; SMALL64-NEXT: std 0, 64(1)
; SMALL64-NEXT: bla .__tls_get_addr[PR] ; SMALL64-NEXT: bla .__tls_get_addr[PR]
; SMALL64-NEXT: ld 4, L..C8(2) ; SMALL64-NEXT: ld 4, L..C8(2)
; SMALL64-NEXT: lwz 3, 0(3) ; SMALL64-NEXT: lwz 3, 0(3)
; SMALL64-NEXT: lwz 4, 0(4) ; SMALL64-NEXT: lwz 4, 0(4)
; SMALL64-NEXT: add 3, 4, 3 ; SMALL64-NEXT: add 3, 4, 3
; SMALL64-NEXT: addi 1, 1, 48 ; SMALL64-NEXT: addi 1, 1, 48
; SMALL64-NEXT: ld 0, 16(1) ; SMALL64-NEXT: ld 0, 16(1)
; SMALL64-NEXT: mtlr 0 ; SMALL64-NEXT: mtlr 0
; SMALL64-NEXT: blr ; SMALL64-NEXT: blr
; ;
; LARGE64-LABEL: loadsTGUninit: ; LARGE64-LABEL: loadsTGUninit:
; LARGE64: # %bb.0: # %entry ; LARGE64: # %bb.0: # %entry
; LARGE64-NEXT: mflr 0 ; LARGE64-NEXT: mflr 0
; LARGE64-NEXT: std 0, 16(1)
; LARGE64-NEXT: stdu 1, -48(1) ; LARGE64-NEXT: stdu 1, -48(1)
; LARGE64-NEXT: addis 3, L..C0@u(2) ; LARGE64-NEXT: addis 3, L..C0@u(2)
; LARGE64-NEXT: addis 4, L..C1@u(2) ; LARGE64-NEXT: addis 4, L..C1@u(2)
; LARGE64-NEXT: std 0, 64(1)
; LARGE64-NEXT: ld 3, L..C0@l(3) ; LARGE64-NEXT: ld 3, L..C0@l(3)
; LARGE64-NEXT: ld 4, L..C1@l(4) ; LARGE64-NEXT: ld 4, L..C1@l(4)
; LARGE64-NEXT: bla .__tls_get_addr[PR] ; LARGE64-NEXT: bla .__tls_get_addr[PR]
; LARGE64-NEXT: addis 4, L..C8@u(2) ; LARGE64-NEXT: addis 4, L..C8@u(2)
; LARGE64-NEXT: lwz 3, 0(3) ; LARGE64-NEXT: lwz 3, 0(3)
; LARGE64-NEXT: ld 4, L..C8@l(4) ; LARGE64-NEXT: ld 4, L..C8@l(4)
; LARGE64-NEXT: lwz 4, 0(4) ; LARGE64-NEXT: lwz 4, 0(4)
; LARGE64-NEXT: add 3, 4, 3 ; LARGE64-NEXT: add 3, 4, 3
; LARGE64-NEXT: addi 1, 1, 48 ; LARGE64-NEXT: addi 1, 1, 48
; LARGE64-NEXT: ld 0, 16(1) ; LARGE64-NEXT: ld 0, 16(1)
; LARGE64-NEXT: mtlr 0 ; LARGE64-NEXT: mtlr 0
; LARGE64-NEXT: blr ; LARGE64-NEXT: blr
entry: entry:
%0 = load i32, ptr @TGUninit, align 4 %0 = load i32, ptr @TGUninit, align 4
%1 = load i32, ptr @GInit, align 4 %1 = load i32, ptr @GInit, align 4
%add = add nsw i32 %1, %0 %add = add nsw i32 %1, %0
ret i32 %add ret i32 %add
} }
; Function Attrs: norecurse nounwind readonly willreturn ; Function Attrs: norecurse nounwind readonly willreturn
define i32 @loadsTGInit() #1 { define i32 @loadsTGInit() #1 {
; SMALL32-LABEL: loadsTGInit: ; SMALL32-LABEL: loadsTGInit:
; SMALL32: # %bb.0: # %entry ; SMALL32: # %bb.0: # %entry
; SMALL32-NEXT: mflr 0 ; SMALL32-NEXT: mflr 0
; SMALL32-NEXT: stw 0, 8(1)
; SMALL32-NEXT: stwu 1, -32(1) ; SMALL32-NEXT: stwu 1, -32(1)
; SMALL32-NEXT: lwz 3, L..C2(2) ; SMALL32-NEXT: lwz 3, L..C2(2)
; SMALL32-NEXT: lwz 4, L..C3(2) ; SMALL32-NEXT: lwz 4, L..C3(2)
; SMALL32-NEXT: stw 0, 40(1)
; SMALL32-NEXT: bla .__tls_get_addr[PR] ; SMALL32-NEXT: bla .__tls_get_addr[PR]
; SMALL32-NEXT: lwz 4, L..C8(2) ; SMALL32-NEXT: lwz 4, L..C8(2)
; SMALL32-NEXT: lwz 3, 0(3) ; SMALL32-NEXT: lwz 3, 0(3)
; SMALL32-NEXT: lwz 4, 0(4) ; SMALL32-NEXT: lwz 4, 0(4)
; SMALL32-NEXT: add 3, 4, 3 ; SMALL32-NEXT: add 3, 4, 3
; SMALL32-NEXT: addi 1, 1, 32 ; SMALL32-NEXT: addi 1, 1, 32
; SMALL32-NEXT: lwz 0, 8(1) ; SMALL32-NEXT: lwz 0, 8(1)
; SMALL32-NEXT: mtlr 0 ; SMALL32-NEXT: mtlr 0
; SMALL32-NEXT: blr ; SMALL32-NEXT: blr
; ;
; LARGE32-LABEL: loadsTGInit: ; LARGE32-LABEL: loadsTGInit:
; LARGE32: # %bb.0: # %entry ; LARGE32: # %bb.0: # %entry
; LARGE32-NEXT: mflr 0 ; LARGE32-NEXT: mflr 0
; LARGE32-NEXT: stw 0, 8(1)
; LARGE32-NEXT: stwu 1, -32(1) ; LARGE32-NEXT: stwu 1, -32(1)
; LARGE32-NEXT: stw 0, 40(1)
; LARGE32-NEXT: addis 3, L..C2@u(2) ; LARGE32-NEXT: addis 3, L..C2@u(2)
; LARGE32-NEXT: addis 4, L..C3@u(2) ; LARGE32-NEXT: addis 4, L..C3@u(2)
; LARGE32-NEXT: lwz 3, L..C2@l(3) ; LARGE32-NEXT: lwz 3, L..C2@l(3)
; LARGE32-NEXT: lwz 4, L..C3@l(4) ; LARGE32-NEXT: lwz 4, L..C3@l(4)
; LARGE32-NEXT: bla .__tls_get_addr[PR] ; LARGE32-NEXT: bla .__tls_get_addr[PR]
; LARGE32-NEXT: lwz 3, 0(3) ; LARGE32-NEXT: lwz 3, 0(3)
; LARGE32-NEXT: addis 4, L..C8@u(2) ; LARGE32-NEXT: addis 4, L..C8@u(2)
; LARGE32-NEXT: lwz 4, L..C8@l(4) ; LARGE32-NEXT: lwz 4, L..C8@l(4)
; LARGE32-NEXT: lwz 4, 0(4) ; LARGE32-NEXT: lwz 4, 0(4)
; LARGE32-NEXT: add 3, 4, 3 ; LARGE32-NEXT: add 3, 4, 3
; LARGE32-NEXT: addi 1, 1, 32 ; LARGE32-NEXT: addi 1, 1, 32
; LARGE32-NEXT: lwz 0, 8(1) ; LARGE32-NEXT: lwz 0, 8(1)
; LARGE32-NEXT: mtlr 0 ; LARGE32-NEXT: mtlr 0
; LARGE32-NEXT: blr ; LARGE32-NEXT: blr
; ;
; SMALL64-LABEL: loadsTGInit: ; SMALL64-LABEL: loadsTGInit:
; SMALL64: # %bb.0: # %entry ; SMALL64: # %bb.0: # %entry
; SMALL64-NEXT: mflr 0 ; SMALL64-NEXT: mflr 0
; SMALL64-NEXT: std 0, 16(1)
; SMALL64-NEXT: stdu 1, -48(1) ; SMALL64-NEXT: stdu 1, -48(1)
; SMALL64-NEXT: ld 3, L..C2(2) ; SMALL64-NEXT: ld 3, L..C2(2)
; SMALL64-NEXT: ld 4, L..C3(2) ; SMALL64-NEXT: ld 4, L..C3(2)
; SMALL64-NEXT: std 0, 64(1)
; SMALL64-NEXT: bla .__tls_get_addr[PR] ; SMALL64-NEXT: bla .__tls_get_addr[PR]
; SMALL64-NEXT: ld 4, L..C8(2) ; SMALL64-NEXT: ld 4, L..C8(2)
; SMALL64-NEXT: lwz 3, 0(3) ; SMALL64-NEXT: lwz 3, 0(3)
; SMALL64-NEXT: lwz 4, 0(4) ; SMALL64-NEXT: lwz 4, 0(4)
; SMALL64-NEXT: add 3, 4, 3 ; SMALL64-NEXT: add 3, 4, 3
; SMALL64-NEXT: addi 1, 1, 48 ; SMALL64-NEXT: addi 1, 1, 48
; SMALL64-NEXT: ld 0, 16(1) ; SMALL64-NEXT: ld 0, 16(1)
; SMALL64-NEXT: mtlr 0 ; SMALL64-NEXT: mtlr 0
; SMALL64-NEXT: blr ; SMALL64-NEXT: blr
; ;
; LARGE64-LABEL: loadsTGInit: ; LARGE64-LABEL: loadsTGInit:
; LARGE64: # %bb.0: # %entry ; LARGE64: # %bb.0: # %entry
; LARGE64-NEXT: mflr 0 ; LARGE64-NEXT: mflr 0
; LARGE64-NEXT: std 0, 16(1)
; LARGE64-NEXT: stdu 1, -48(1) ; LARGE64-NEXT: stdu 1, -48(1)
; LARGE64-NEXT: addis 3, L..C2@u(2) ; LARGE64-NEXT: addis 3, L..C2@u(2)
; LARGE64-NEXT: addis 4, L..C3@u(2) ; LARGE64-NEXT: addis 4, L..C3@u(2)
; LARGE64-NEXT: std 0, 64(1)
; LARGE64-NEXT: ld 3, L..C2@l(3) ; LARGE64-NEXT: ld 3, L..C2@l(3)
; LARGE64-NEXT: ld 4, L..C3@l(4) ; LARGE64-NEXT: ld 4, L..C3@l(4)
; LARGE64-NEXT: bla .__tls_get_addr[PR] ; LARGE64-NEXT: bla .__tls_get_addr[PR]
; LARGE64-NEXT: addis 4, L..C8@u(2) ; LARGE64-NEXT: addis 4, L..C8@u(2)
; LARGE64-NEXT: lwz 3, 0(3) ; LARGE64-NEXT: lwz 3, 0(3)
; LARGE64-NEXT: ld 4, L..C8@l(4) ; LARGE64-NEXT: ld 4, L..C8@l(4)
; LARGE64-NEXT: lwz 4, 0(4) ; LARGE64-NEXT: lwz 4, 0(4)
; LARGE64-NEXT: add 3, 4, 3 ; LARGE64-NEXT: add 3, 4, 3
; LARGE64-NEXT: addi 1, 1, 48 ; LARGE64-NEXT: addi 1, 1, 48
; LARGE64-NEXT: ld 0, 16(1) ; LARGE64-NEXT: ld 0, 16(1)
; LARGE64-NEXT: mtlr 0 ; LARGE64-NEXT: mtlr 0
; LARGE64-NEXT: blr ; LARGE64-NEXT: blr
entry: entry:
%0 = load i32, ptr @TGInit, align 4 %0 = load i32, ptr @TGInit, align 4
%1 = load i32, ptr @GInit, align 4 %1 = load i32, ptr @GInit, align 4
%add = add nsw i32 %1, %0 %add = add nsw i32 %1, %0
ret i32 %add ret i32 %add
} }
; Function Attrs: norecurse nounwind readonly willreturn ; Function Attrs: norecurse nounwind readonly willreturn
define i32 @loadsTIUninit() #1 { define i32 @loadsTIUninit() #1 {
; SMALL32-LABEL: loadsTIUninit: ; SMALL32-LABEL: loadsTIUninit:
; SMALL32: # %bb.0: # %entry ; SMALL32: # %bb.0: # %entry
; SMALL32-NEXT: mflr 0 ; SMALL32-NEXT: mflr 0
; SMALL32-NEXT: stw 0, 8(1)
; SMALL32-NEXT: stwu 1, -32(1) ; SMALL32-NEXT: stwu 1, -32(1)
; SMALL32-NEXT: lwz 3, L..C4(2) ; SMALL32-NEXT: lwz 3, L..C4(2)
; SMALL32-NEXT: lwz 4, L..C5(2) ; SMALL32-NEXT: lwz 4, L..C5(2)
; SMALL32-NEXT: stw 0, 40(1)
; SMALL32-NEXT: bla .__tls_get_addr[PR] ; SMALL32-NEXT: bla .__tls_get_addr[PR]
; SMALL32-NEXT: lwz 4, L..C8(2) ; SMALL32-NEXT: lwz 4, L..C8(2)
; SMALL32-NEXT: lwz 3, 0(3) ; SMALL32-NEXT: lwz 3, 0(3)
; SMALL32-NEXT: lwz 4, 0(4) ; SMALL32-NEXT: lwz 4, 0(4)
; SMALL32-NEXT: add 3, 4, 3 ; SMALL32-NEXT: add 3, 4, 3
; SMALL32-NEXT: addi 1, 1, 32 ; SMALL32-NEXT: addi 1, 1, 32
; SMALL32-NEXT: lwz 0, 8(1) ; SMALL32-NEXT: lwz 0, 8(1)
; SMALL32-NEXT: mtlr 0 ; SMALL32-NEXT: mtlr 0
; SMALL32-NEXT: blr ; SMALL32-NEXT: blr
; ;
; LARGE32-LABEL: loadsTIUninit: ; LARGE32-LABEL: loadsTIUninit:
; LARGE32: # %bb.0: # %entry ; LARGE32: # %bb.0: # %entry
; LARGE32-NEXT: mflr 0 ; LARGE32-NEXT: mflr 0
; LARGE32-NEXT: stw 0, 8(1)
; LARGE32-NEXT: stwu 1, -32(1) ; LARGE32-NEXT: stwu 1, -32(1)
; LARGE32-NEXT: stw 0, 40(1)
; LARGE32-NEXT: addis 3, L..C4@u(2) ; LARGE32-NEXT: addis 3, L..C4@u(2)
; LARGE32-NEXT: addis 4, L..C5@u(2) ; LARGE32-NEXT: addis 4, L..C5@u(2)
; LARGE32-NEXT: lwz 3, L..C4@l(3) ; LARGE32-NEXT: lwz 3, L..C4@l(3)
; LARGE32-NEXT: lwz 4, L..C5@l(4) ; LARGE32-NEXT: lwz 4, L..C5@l(4)
; LARGE32-NEXT: bla .__tls_get_addr[PR] ; LARGE32-NEXT: bla .__tls_get_addr[PR]
; LARGE32-NEXT: lwz 3, 0(3) ; LARGE32-NEXT: lwz 3, 0(3)
; LARGE32-NEXT: addis 4, L..C8@u(2) ; LARGE32-NEXT: addis 4, L..C8@u(2)
; LARGE32-NEXT: lwz 4, L..C8@l(4) ; LARGE32-NEXT: lwz 4, L..C8@l(4)
; LARGE32-NEXT: lwz 4, 0(4) ; LARGE32-NEXT: lwz 4, 0(4)
; LARGE32-NEXT: add 3, 4, 3 ; LARGE32-NEXT: add 3, 4, 3
; LARGE32-NEXT: addi 1, 1, 32 ; LARGE32-NEXT: addi 1, 1, 32
; LARGE32-NEXT: lwz 0, 8(1) ; LARGE32-NEXT: lwz 0, 8(1)
; LARGE32-NEXT: mtlr 0 ; LARGE32-NEXT: mtlr 0
; LARGE32-NEXT: blr ; LARGE32-NEXT: blr
; ;
; SMALL64-LABEL: loadsTIUninit: ; SMALL64-LABEL: loadsTIUninit:
; SMALL64: # %bb.0: # %entry ; SMALL64: # %bb.0: # %entry
; SMALL64-NEXT: mflr 0 ; SMALL64-NEXT: mflr 0
; SMALL64-NEXT: std 0, 16(1)
; SMALL64-NEXT: stdu 1, -48(1) ; SMALL64-NEXT: stdu 1, -48(1)
; SMALL64-NEXT: ld 3, L..C4(2) ; SMALL64-NEXT: ld 3, L..C4(2)
; SMALL64-NEXT: ld 4, L..C5(2) ; SMALL64-NEXT: ld 4, L..C5(2)
; SMALL64-NEXT: std 0, 64(1)
; SMALL64-NEXT: bla .__tls_get_addr[PR] ; SMALL64-NEXT: bla .__tls_get_addr[PR]
; SMALL64-NEXT: ld 4, L..C8(2) ; SMALL64-NEXT: ld 4, L..C8(2)
; SMALL64-NEXT: lwz 3, 0(3) ; SMALL64-NEXT: lwz 3, 0(3)
; SMALL64-NEXT: lwz 4, 0(4) ; SMALL64-NEXT: lwz 4, 0(4)
; SMALL64-NEXT: add 3, 4, 3 ; SMALL64-NEXT: add 3, 4, 3
; SMALL64-NEXT: addi 1, 1, 48 ; SMALL64-NEXT: addi 1, 1, 48
; SMALL64-NEXT: ld 0, 16(1) ; SMALL64-NEXT: ld 0, 16(1)
; SMALL64-NEXT: mtlr 0 ; SMALL64-NEXT: mtlr 0
; SMALL64-NEXT: blr ; SMALL64-NEXT: blr
; ;
; LARGE64-LABEL: loadsTIUninit: ; LARGE64-LABEL: loadsTIUninit:
; LARGE64: # %bb.0: # %entry ; LARGE64: # %bb.0: # %entry
; LARGE64-NEXT: mflr 0 ; LARGE64-NEXT: mflr 0
; LARGE64-NEXT: std 0, 16(1)
; LARGE64-NEXT: stdu 1, -48(1) ; LARGE64-NEXT: stdu 1, -48(1)
; LARGE64-NEXT: addis 3, L..C4@u(2) ; LARGE64-NEXT: addis 3, L..C4@u(2)
; LARGE64-NEXT: addis 4, L..C5@u(2) ; LARGE64-NEXT: addis 4, L..C5@u(2)
; LARGE64-NEXT: std 0, 64(1)
; LARGE64-NEXT: ld 3, L..C4@l(3) ; LARGE64-NEXT: ld 3, L..C4@l(3)
; LARGE64-NEXT: ld 4, L..C5@l(4) ; LARGE64-NEXT: ld 4, L..C5@l(4)
; LARGE64-NEXT: bla .__tls_get_addr[PR] ; LARGE64-NEXT: bla .__tls_get_addr[PR]
; LARGE64-NEXT: addis 4, L..C8@u(2) ; LARGE64-NEXT: addis 4, L..C8@u(2)
; LARGE64-NEXT: lwz 3, 0(3) ; LARGE64-NEXT: lwz 3, 0(3)
; LARGE64-NEXT: ld 4, L..C8@l(4) ; LARGE64-NEXT: ld 4, L..C8@l(4)
; LARGE64-NEXT: lwz 4, 0(4) ; LARGE64-NEXT: lwz 4, 0(4)
; LARGE64-NEXT: add 3, 4, 3 ; LARGE64-NEXT: add 3, 4, 3
; LARGE64-NEXT: addi 1, 1, 48 ; LARGE64-NEXT: addi 1, 1, 48
; LARGE64-NEXT: ld 0, 16(1) ; LARGE64-NEXT: ld 0, 16(1)
; LARGE64-NEXT: mtlr 0 ; LARGE64-NEXT: mtlr 0
; LARGE64-NEXT: blr ; LARGE64-NEXT: blr
entry: entry:
%0 = load i32, ptr @TIUninit, align 4 %0 = load i32, ptr @TIUninit, align 4
%1 = load i32, ptr @GInit, align 4 %1 = load i32, ptr @GInit, align 4
%add = add nsw i32 %1, %0 %add = add nsw i32 %1, %0
ret i32 %add ret i32 %add
} }
; Function Attrs: norecurse nounwind readonly willreturn ; Function Attrs: norecurse nounwind readonly willreturn
define i32 @loadsTWUninit() #1 { define i32 @loadsTWUninit() #1 {
; SMALL32-LABEL: loadsTWUninit: ; SMALL32-LABEL: loadsTWUninit:
; SMALL32: # %bb.0: # %entry ; SMALL32: # %bb.0: # %entry
; SMALL32-NEXT: mflr 0 ; SMALL32-NEXT: mflr 0
; SMALL32-NEXT: stw 0, 8(1)
; SMALL32-NEXT: stwu 1, -32(1) ; SMALL32-NEXT: stwu 1, -32(1)
; SMALL32-NEXT: lwz 3, L..C6(2) ; SMALL32-NEXT: lwz 3, L..C6(2)
; SMALL32-NEXT: lwz 4, L..C7(2) ; SMALL32-NEXT: lwz 4, L..C7(2)
; SMALL32-NEXT: stw 0, 40(1)
; SMALL32-NEXT: bla .__tls_get_addr[PR] ; SMALL32-NEXT: bla .__tls_get_addr[PR]
; SMALL32-NEXT: lwz 4, L..C8(2) ; SMALL32-NEXT: lwz 4, L..C8(2)
; SMALL32-NEXT: lwz 3, 0(3) ; SMALL32-NEXT: lwz 3, 0(3)
; SMALL32-NEXT: lwz 4, 0(4) ; SMALL32-NEXT: lwz 4, 0(4)
; SMALL32-NEXT: add 3, 4, 3 ; SMALL32-NEXT: add 3, 4, 3
; SMALL32-NEXT: addi 1, 1, 32 ; SMALL32-NEXT: addi 1, 1, 32
; SMALL32-NEXT: lwz 0, 8(1) ; SMALL32-NEXT: lwz 0, 8(1)
; SMALL32-NEXT: mtlr 0 ; SMALL32-NEXT: mtlr 0
; SMALL32-NEXT: blr ; SMALL32-NEXT: blr
; ;
; LARGE32-LABEL: loadsTWUninit: ; LARGE32-LABEL: loadsTWUninit:
; LARGE32: # %bb.0: # %entry ; LARGE32: # %bb.0: # %entry
; LARGE32-NEXT: mflr 0 ; LARGE32-NEXT: mflr 0
; LARGE32-NEXT: stw 0, 8(1)
; LARGE32-NEXT: stwu 1, -32(1) ; LARGE32-NEXT: stwu 1, -32(1)
; LARGE32-NEXT: stw 0, 40(1)
; LARGE32-NEXT: addis 3, L..C6@u(2) ; LARGE32-NEXT: addis 3, L..C6@u(2)
; LARGE32-NEXT: addis 4, L..C7@u(2) ; LARGE32-NEXT: addis 4, L..C7@u(2)
; LARGE32-NEXT: lwz 3, L..C6@l(3) ; LARGE32-NEXT: lwz 3, L..C6@l(3)
; LARGE32-NEXT: lwz 4, L..C7@l(4) ; LARGE32-NEXT: lwz 4, L..C7@l(4)
; LARGE32-NEXT: bla .__tls_get_addr[PR] ; LARGE32-NEXT: bla .__tls_get_addr[PR]
; LARGE32-NEXT: lwz 3, 0(3) ; LARGE32-NEXT: lwz 3, 0(3)
; LARGE32-NEXT: addis 4, L..C8@u(2) ; LARGE32-NEXT: addis 4, L..C8@u(2)
; LARGE32-NEXT: lwz 4, L..C8@l(4) ; LARGE32-NEXT: lwz 4, L..C8@l(4)
; LARGE32-NEXT: lwz 4, 0(4) ; LARGE32-NEXT: lwz 4, 0(4)
; LARGE32-NEXT: add 3, 4, 3 ; LARGE32-NEXT: add 3, 4, 3
; LARGE32-NEXT: addi 1, 1, 32 ; LARGE32-NEXT: addi 1, 1, 32
; LARGE32-NEXT: lwz 0, 8(1) ; LARGE32-NEXT: lwz 0, 8(1)
; LARGE32-NEXT: mtlr 0 ; LARGE32-NEXT: mtlr 0
; LARGE32-NEXT: blr ; LARGE32-NEXT: blr
; ;
; SMALL64-LABEL: loadsTWUninit: ; SMALL64-LABEL: loadsTWUninit:
; SMALL64: # %bb.0: # %entry ; SMALL64: # %bb.0: # %entry
; SMALL64-NEXT: mflr 0 ; SMALL64-NEXT: mflr 0
; SMALL64-NEXT: std 0, 16(1)
; SMALL64-NEXT: stdu 1, -48(1) ; SMALL64-NEXT: stdu 1, -48(1)
; SMALL64-NEXT: ld 3, L..C6(2) ; SMALL64-NEXT: ld 3, L..C6(2)
; SMALL64-NEXT: ld 4, L..C7(2) ; SMALL64-NEXT: ld 4, L..C7(2)
; SMALL64-NEXT: std 0, 64(1)
; SMALL64-NEXT: bla .__tls_get_addr[PR] ; SMALL64-NEXT: bla .__tls_get_addr[PR]
; SMALL64-NEXT: ld 4, L..C8(2) ; SMALL64-NEXT: ld 4, L..C8(2)
; SMALL64-NEXT: lwz 3, 0(3) ; SMALL64-NEXT: lwz 3, 0(3)
; SMALL64-NEXT: lwz 4, 0(4) ; SMALL64-NEXT: lwz 4, 0(4)
; SMALL64-NEXT: add 3, 4, 3 ; SMALL64-NEXT: add 3, 4, 3
; SMALL64-NEXT: addi 1, 1, 48 ; SMALL64-NEXT: addi 1, 1, 48
; SMALL64-NEXT: ld 0, 16(1) ; SMALL64-NEXT: ld 0, 16(1)
; SMALL64-NEXT: mtlr 0 ; SMALL64-NEXT: mtlr 0
; SMALL64-NEXT: blr ; SMALL64-NEXT: blr
; ;
; LARGE64-LABEL: loadsTWUninit: ; LARGE64-LABEL: loadsTWUninit:
; LARGE64: # %bb.0: # %entry ; LARGE64: # %bb.0: # %entry
; LARGE64-NEXT: mflr 0 ; LARGE64-NEXT: mflr 0
; LARGE64-NEXT: std 0, 16(1)
; LARGE64-NEXT: stdu 1, -48(1) ; LARGE64-NEXT: stdu 1, -48(1)
; LARGE64-NEXT: addis 3, L..C6@u(2) ; LARGE64-NEXT: addis 3, L..C6@u(2)
; LARGE64-NEXT: addis 4, L..C7@u(2) ; LARGE64-NEXT: addis 4, L..C7@u(2)
; LARGE64-NEXT: std 0, 64(1)
; LARGE64-NEXT: ld 3, L..C6@l(3) ; LARGE64-NEXT: ld 3, L..C6@l(3)
; LARGE64-NEXT: ld 4, L..C7@l(4) ; LARGE64-NEXT: ld 4, L..C7@l(4)
; LARGE64-NEXT: bla .__tls_get_addr[PR] ; LARGE64-NEXT: bla .__tls_get_addr[PR]
; LARGE64-NEXT: addis 4, L..C8@u(2) ; LARGE64-NEXT: addis 4, L..C8@u(2)
; LARGE64-NEXT: lwz 3, 0(3) ; LARGE64-NEXT: lwz 3, 0(3)
; LARGE64-NEXT: ld 4, L..C8@l(4) ; LARGE64-NEXT: ld 4, L..C8@l(4)
; LARGE64-NEXT: lwz 4, 0(4) ; LARGE64-NEXT: lwz 4, 0(4)
; LARGE64-NEXT: add 3, 4, 3 ; LARGE64-NEXT: add 3, 4, 3
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llvm/test/CodeGen/PowerPC/aix-tls-gd-longlong.ll

Show All 16 Lines
@TIUninit = internal thread_local global i64 0, align 8 @TIUninit = internal thread_local global i64 0, align 8
@TIInit = internal thread_local global i64 1, align 8 @TIInit = internal thread_local global i64 1, align 8
; Function Attrs: nofree norecurse nounwind willreturn writeonly ; Function Attrs: nofree norecurse nounwind willreturn writeonly
define void @storesTGInit(i64 %Val) #0 { define void @storesTGInit(i64 %Val) #0 {
; SMALL32-LABEL: storesTGInit: ; SMALL32-LABEL: storesTGInit:
; SMALL32: # %bb.0: # %entry ; SMALL32: # %bb.0: # %entry
; SMALL32-NEXT: mflr 0 ; SMALL32-NEXT: mflr 0
; SMALL32-NEXT: stw 0, 8(1)
; SMALL32-NEXT: stwu 1, -32(1) ; SMALL32-NEXT: stwu 1, -32(1)
; SMALL32-NEXT: mr 6, 4 ; SMALL32-NEXT: mr 6, 4
; SMALL32-NEXT: mr 7, 3 ; SMALL32-NEXT: mr 7, 3
; SMALL32-NEXT: lwz 3, L..C0(2) ; SMALL32-NEXT: lwz 3, L..C0(2)
; SMALL32-NEXT: lwz 4, L..C1(2) ; SMALL32-NEXT: lwz 4, L..C1(2)
; SMALL32-NEXT: stw 0, 40(1)
; SMALL32-NEXT: bla .__tls_get_addr[PR] ; SMALL32-NEXT: bla .__tls_get_addr[PR]
; SMALL32-NEXT: stw 6, 4(3) ; SMALL32-NEXT: stw 6, 4(3)
; SMALL32-NEXT: stw 7, 0(3) ; SMALL32-NEXT: stw 7, 0(3)
; SMALL32-NEXT: addi 1, 1, 32 ; SMALL32-NEXT: addi 1, 1, 32
; SMALL32-NEXT: lwz 0, 8(1) ; SMALL32-NEXT: lwz 0, 8(1)
; SMALL32-NEXT: mtlr 0 ; SMALL32-NEXT: mtlr 0
; SMALL32-NEXT: blr ; SMALL32-NEXT: blr
; ;
; LARGE32-LABEL: storesTGInit: ; LARGE32-LABEL: storesTGInit:
; LARGE32: # %bb.0: # %entry ; LARGE32: # %bb.0: # %entry
; LARGE32-NEXT: mflr 0 ; LARGE32-NEXT: mflr 0
; LARGE32-NEXT: stw 0, 8(1)
; LARGE32-NEXT: stwu 1, -32(1) ; LARGE32-NEXT: stwu 1, -32(1)
; LARGE32-NEXT: stw 0, 40(1)
; LARGE32-NEXT: mr 6, 4 ; LARGE32-NEXT: mr 6, 4
; LARGE32-NEXT: mr 7, 3 ; LARGE32-NEXT: mr 7, 3
; LARGE32-NEXT: addis 3, L..C0@u(2) ; LARGE32-NEXT: addis 3, L..C0@u(2)
; LARGE32-NEXT: addis 4, L..C1@u(2) ; LARGE32-NEXT: addis 4, L..C1@u(2)
; LARGE32-NEXT: lwz 3, L..C0@l(3) ; LARGE32-NEXT: lwz 3, L..C0@l(3)
; LARGE32-NEXT: lwz 4, L..C1@l(4) ; LARGE32-NEXT: lwz 4, L..C1@l(4)
; LARGE32-NEXT: bla .__tls_get_addr[PR] ; LARGE32-NEXT: bla .__tls_get_addr[PR]
; LARGE32-NEXT: stw 6, 4(3) ; LARGE32-NEXT: stw 6, 4(3)
; LARGE32-NEXT: stw 7, 0(3) ; LARGE32-NEXT: stw 7, 0(3)
; LARGE32-NEXT: addi 1, 1, 32 ; LARGE32-NEXT: addi 1, 1, 32
; LARGE32-NEXT: lwz 0, 8(1) ; LARGE32-NEXT: lwz 0, 8(1)
; LARGE32-NEXT: mtlr 0 ; LARGE32-NEXT: mtlr 0
; LARGE32-NEXT: blr ; LARGE32-NEXT: blr
; ;
; SMALL64-LABEL: storesTGInit: ; SMALL64-LABEL: storesTGInit:
; SMALL64: # %bb.0: # %entry ; SMALL64: # %bb.0: # %entry
; SMALL64-NEXT: mflr 0 ; SMALL64-NEXT: mflr 0
; SMALL64-NEXT: std 0, 16(1)
; SMALL64-NEXT: stdu 1, -48(1) ; SMALL64-NEXT: stdu 1, -48(1)
; SMALL64-NEXT: mr 6, 3 ; SMALL64-NEXT: mr 6, 3
; SMALL64-NEXT: ld 3, L..C0(2) ; SMALL64-NEXT: ld 3, L..C0(2)
; SMALL64-NEXT: ld 4, L..C1(2) ; SMALL64-NEXT: ld 4, L..C1(2)
; SMALL64-NEXT: std 0, 64(1)
; SMALL64-NEXT: bla .__tls_get_addr[PR] ; SMALL64-NEXT: bla .__tls_get_addr[PR]
; SMALL64-NEXT: std 6, 0(3) ; SMALL64-NEXT: std 6, 0(3)
; SMALL64-NEXT: addi 1, 1, 48 ; SMALL64-NEXT: addi 1, 1, 48
; SMALL64-NEXT: ld 0, 16(1) ; SMALL64-NEXT: ld 0, 16(1)
; SMALL64-NEXT: mtlr 0 ; SMALL64-NEXT: mtlr 0
; SMALL64-NEXT: blr ; SMALL64-NEXT: blr
; ;
; LARGE64-LABEL: storesTGInit: ; LARGE64-LABEL: storesTGInit:
; LARGE64: # %bb.0: # %entry ; LARGE64: # %bb.0: # %entry
; LARGE64-NEXT: mflr 0 ; LARGE64-NEXT: mflr 0
; LARGE64-NEXT: std 0, 16(1)
; LARGE64-NEXT: stdu 1, -48(1) ; LARGE64-NEXT: stdu 1, -48(1)
; LARGE64-NEXT: mr 6, 3 ; LARGE64-NEXT: mr 6, 3
; LARGE64-NEXT: addis 3, L..C0@u(2) ; LARGE64-NEXT: addis 3, L..C0@u(2)
; LARGE64-NEXT: addis 4, L..C1@u(2) ; LARGE64-NEXT: addis 4, L..C1@u(2)
; LARGE64-NEXT: std 0, 64(1)
; LARGE64-NEXT: ld 3, L..C0@l(3) ; LARGE64-NEXT: ld 3, L..C0@l(3)
; LARGE64-NEXT: ld 4, L..C1@l(4) ; LARGE64-NEXT: ld 4, L..C1@l(4)
; LARGE64-NEXT: bla .__tls_get_addr[PR] ; LARGE64-NEXT: bla .__tls_get_addr[PR]
; LARGE64-NEXT: std 6, 0(3) ; LARGE64-NEXT: std 6, 0(3)
; LARGE64-NEXT: addi 1, 1, 48 ; LARGE64-NEXT: addi 1, 1, 48
; LARGE64-NEXT: ld 0, 16(1) ; LARGE64-NEXT: ld 0, 16(1)
; LARGE64-NEXT: mtlr 0 ; LARGE64-NEXT: mtlr 0
; LARGE64-NEXT: blr ; LARGE64-NEXT: blr
entry: entry:
store i64 %Val, ptr @TGInit, align 8 store i64 %Val, ptr @TGInit, align 8
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind willreturn writeonly ; Function Attrs: nofree norecurse nounwind willreturn writeonly
define void @storesTIUninit(i64 %Val) #0 { define void @storesTIUninit(i64 %Val) #0 {
; SMALL32-LABEL: storesTIUninit: ; SMALL32-LABEL: storesTIUninit:
; SMALL32: # %bb.0: # %entry ; SMALL32: # %bb.0: # %entry
; SMALL32-NEXT: mflr 0 ; SMALL32-NEXT: mflr 0
; SMALL32-NEXT: stw 0, 8(1)
; SMALL32-NEXT: stwu 1, -32(1) ; SMALL32-NEXT: stwu 1, -32(1)
; SMALL32-NEXT: mr 6, 4 ; SMALL32-NEXT: mr 6, 4
; SMALL32-NEXT: mr 7, 3 ; SMALL32-NEXT: mr 7, 3
; SMALL32-NEXT: lwz 3, L..C2(2) ; SMALL32-NEXT: lwz 3, L..C2(2)
; SMALL32-NEXT: lwz 4, L..C3(2) ; SMALL32-NEXT: lwz 4, L..C3(2)
; SMALL32-NEXT: stw 0, 40(1)
; SMALL32-NEXT: bla .__tls_get_addr[PR] ; SMALL32-NEXT: bla .__tls_get_addr[PR]
; SMALL32-NEXT: stw 6, 4(3) ; SMALL32-NEXT: stw 6, 4(3)
; SMALL32-NEXT: stw 7, 0(3) ; SMALL32-NEXT: stw 7, 0(3)
; SMALL32-NEXT: addi 1, 1, 32 ; SMALL32-NEXT: addi 1, 1, 32
; SMALL32-NEXT: lwz 0, 8(1) ; SMALL32-NEXT: lwz 0, 8(1)
; SMALL32-NEXT: mtlr 0 ; SMALL32-NEXT: mtlr 0
; SMALL32-NEXT: blr ; SMALL32-NEXT: blr
; ;
; LARGE32-LABEL: storesTIUninit: ; LARGE32-LABEL: storesTIUninit:
; LARGE32: # %bb.0: # %entry ; LARGE32: # %bb.0: # %entry
; LARGE32-NEXT: mflr 0 ; LARGE32-NEXT: mflr 0
; LARGE32-NEXT: stw 0, 8(1)
; LARGE32-NEXT: stwu 1, -32(1) ; LARGE32-NEXT: stwu 1, -32(1)
; LARGE32-NEXT: stw 0, 40(1)
; LARGE32-NEXT: mr 6, 4 ; LARGE32-NEXT: mr 6, 4
; LARGE32-NEXT: mr 7, 3 ; LARGE32-NEXT: mr 7, 3
; LARGE32-NEXT: addis 3, L..C2@u(2) ; LARGE32-NEXT: addis 3, L..C2@u(2)
; LARGE32-NEXT: addis 4, L..C3@u(2) ; LARGE32-NEXT: addis 4, L..C3@u(2)
; LARGE32-NEXT: lwz 3, L..C2@l(3) ; LARGE32-NEXT: lwz 3, L..C2@l(3)
; LARGE32-NEXT: lwz 4, L..C3@l(4) ; LARGE32-NEXT: lwz 4, L..C3@l(4)
; LARGE32-NEXT: bla .__tls_get_addr[PR] ; LARGE32-NEXT: bla .__tls_get_addr[PR]
; LARGE32-NEXT: stw 6, 4(3) ; LARGE32-NEXT: stw 6, 4(3)
; LARGE32-NEXT: stw 7, 0(3) ; LARGE32-NEXT: stw 7, 0(3)
; LARGE32-NEXT: addi 1, 1, 32 ; LARGE32-NEXT: addi 1, 1, 32
; LARGE32-NEXT: lwz 0, 8(1) ; LARGE32-NEXT: lwz 0, 8(1)
; LARGE32-NEXT: mtlr 0 ; LARGE32-NEXT: mtlr 0
; LARGE32-NEXT: blr ; LARGE32-NEXT: blr
; ;
; SMALL64-LABEL: storesTIUninit: ; SMALL64-LABEL: storesTIUninit:
; SMALL64: # %bb.0: # %entry ; SMALL64: # %bb.0: # %entry
; SMALL64-NEXT: mflr 0 ; SMALL64-NEXT: mflr 0
; SMALL64-NEXT: std 0, 16(1)
; SMALL64-NEXT: stdu 1, -48(1) ; SMALL64-NEXT: stdu 1, -48(1)
; SMALL64-NEXT: mr 6, 3 ; SMALL64-NEXT: mr 6, 3
; SMALL64-NEXT: ld 3, L..C2(2) ; SMALL64-NEXT: ld 3, L..C2(2)
; SMALL64-NEXT: ld 4, L..C3(2) ; SMALL64-NEXT: ld 4, L..C3(2)
; SMALL64-NEXT: std 0, 64(1)
; SMALL64-NEXT: bla .__tls_get_addr[PR] ; SMALL64-NEXT: bla .__tls_get_addr[PR]
; SMALL64-NEXT: std 6, 0(3) ; SMALL64-NEXT: std 6, 0(3)
; SMALL64-NEXT: addi 1, 1, 48 ; SMALL64-NEXT: addi 1, 1, 48
; SMALL64-NEXT: ld 0, 16(1) ; SMALL64-NEXT: ld 0, 16(1)
; SMALL64-NEXT: mtlr 0 ; SMALL64-NEXT: mtlr 0
; SMALL64-NEXT: blr ; SMALL64-NEXT: blr
; ;
; LARGE64-LABEL: storesTIUninit: ; LARGE64-LABEL: storesTIUninit:
; LARGE64: # %bb.0: # %entry ; LARGE64: # %bb.0: # %entry
; LARGE64-NEXT: mflr 0 ; LARGE64-NEXT: mflr 0
; LARGE64-NEXT: std 0, 16(1)
; LARGE64-NEXT: stdu 1, -48(1) ; LARGE64-NEXT: stdu 1, -48(1)
; LARGE64-NEXT: mr 6, 3 ; LARGE64-NEXT: mr 6, 3
; LARGE64-NEXT: addis 3, L..C2@u(2) ; LARGE64-NEXT: addis 3, L..C2@u(2)
; LARGE64-NEXT: addis 4, L..C3@u(2) ; LARGE64-NEXT: addis 4, L..C3@u(2)
; LARGE64-NEXT: std 0, 64(1)
; LARGE64-NEXT: ld 3, L..C2@l(3) ; LARGE64-NEXT: ld 3, L..C2@l(3)
; LARGE64-NEXT: ld 4, L..C3@l(4) ; LARGE64-NEXT: ld 4, L..C3@l(4)
; LARGE64-NEXT: bla .__tls_get_addr[PR] ; LARGE64-NEXT: bla .__tls_get_addr[PR]
; LARGE64-NEXT: std 6, 0(3) ; LARGE64-NEXT: std 6, 0(3)
; LARGE64-NEXT: addi 1, 1, 48 ; LARGE64-NEXT: addi 1, 1, 48
; LARGE64-NEXT: ld 0, 16(1) ; LARGE64-NEXT: ld 0, 16(1)
; LARGE64-NEXT: mtlr 0 ; LARGE64-NEXT: mtlr 0
; LARGE64-NEXT: blr ; LARGE64-NEXT: blr
entry: entry:
store i64 %Val, ptr @TIUninit, align 8 store i64 %Val, ptr @TIUninit, align 8
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind willreturn writeonly ; Function Attrs: nofree norecurse nounwind willreturn writeonly
define void @storesTIInit(i64 %Val) #0 { define void @storesTIInit(i64 %Val) #0 {
; SMALL32-LABEL: storesTIInit: ; SMALL32-LABEL: storesTIInit:
; SMALL32: # %bb.0: # %entry ; SMALL32: # %bb.0: # %entry
; SMALL32-NEXT: mflr 0 ; SMALL32-NEXT: mflr 0
; SMALL32-NEXT: stw 0, 8(1)
; SMALL32-NEXT: stwu 1, -32(1) ; SMALL32-NEXT: stwu 1, -32(1)
; SMALL32-NEXT: mr 6, 4 ; SMALL32-NEXT: mr 6, 4
; SMALL32-NEXT: mr 7, 3 ; SMALL32-NEXT: mr 7, 3
; SMALL32-NEXT: lwz 3, L..C4(2) ; SMALL32-NEXT: lwz 3, L..C4(2)
; SMALL32-NEXT: lwz 4, L..C5(2) ; SMALL32-NEXT: lwz 4, L..C5(2)
; SMALL32-NEXT: stw 0, 40(1)
; SMALL32-NEXT: bla .__tls_get_addr[PR] ; SMALL32-NEXT: bla .__tls_get_addr[PR]
; SMALL32-NEXT: stw 6, 4(3) ; SMALL32-NEXT: stw 6, 4(3)
; SMALL32-NEXT: stw 7, 0(3) ; SMALL32-NEXT: stw 7, 0(3)
; SMALL32-NEXT: addi 1, 1, 32 ; SMALL32-NEXT: addi 1, 1, 32
; SMALL32-NEXT: lwz 0, 8(1) ; SMALL32-NEXT: lwz 0, 8(1)
; SMALL32-NEXT: mtlr 0 ; SMALL32-NEXT: mtlr 0
; SMALL32-NEXT: blr ; SMALL32-NEXT: blr
; ;
; LARGE32-LABEL: storesTIInit: ; LARGE32-LABEL: storesTIInit:
; LARGE32: # %bb.0: # %entry ; LARGE32: # %bb.0: # %entry
; LARGE32-NEXT: mflr 0 ; LARGE32-NEXT: mflr 0
; LARGE32-NEXT: stw 0, 8(1)
; LARGE32-NEXT: stwu 1, -32(1) ; LARGE32-NEXT: stwu 1, -32(1)
; LARGE32-NEXT: stw 0, 40(1)
; LARGE32-NEXT: mr 6, 4 ; LARGE32-NEXT: mr 6, 4
; LARGE32-NEXT: mr 7, 3 ; LARGE32-NEXT: mr 7, 3
; LARGE32-NEXT: addis 3, L..C4@u(2) ; LARGE32-NEXT: addis 3, L..C4@u(2)
; LARGE32-NEXT: addis 4, L..C5@u(2) ; LARGE32-NEXT: addis 4, L..C5@u(2)
; LARGE32-NEXT: lwz 3, L..C4@l(3) ; LARGE32-NEXT: lwz 3, L..C4@l(3)
; LARGE32-NEXT: lwz 4, L..C5@l(4) ; LARGE32-NEXT: lwz 4, L..C5@l(4)
; LARGE32-NEXT: bla .__tls_get_addr[PR] ; LARGE32-NEXT: bla .__tls_get_addr[PR]
; LARGE32-NEXT: stw 6, 4(3) ; LARGE32-NEXT: stw 6, 4(3)
; LARGE32-NEXT: stw 7, 0(3) ; LARGE32-NEXT: stw 7, 0(3)
; LARGE32-NEXT: addi 1, 1, 32 ; LARGE32-NEXT: addi 1, 1, 32
; LARGE32-NEXT: lwz 0, 8(1) ; LARGE32-NEXT: lwz 0, 8(1)
; LARGE32-NEXT: mtlr 0 ; LARGE32-NEXT: mtlr 0
; LARGE32-NEXT: blr ; LARGE32-NEXT: blr
; ;
; SMALL64-LABEL: storesTIInit: ; SMALL64-LABEL: storesTIInit:
; SMALL64: # %bb.0: # %entry ; SMALL64: # %bb.0: # %entry
; SMALL64-NEXT: mflr 0 ; SMALL64-NEXT: mflr 0
; SMALL64-NEXT: std 0, 16(1)
; SMALL64-NEXT: stdu 1, -48(1) ; SMALL64-NEXT: stdu 1, -48(1)
; SMALL64-NEXT: mr 6, 3 ; SMALL64-NEXT: mr 6, 3
; SMALL64-NEXT: ld 3, L..C4(2) ; SMALL64-NEXT: ld 3, L..C4(2)
; SMALL64-NEXT: ld 4, L..C5(2) ; SMALL64-NEXT: ld 4, L..C5(2)
; SMALL64-NEXT: std 0, 64(1)
; SMALL64-NEXT: bla .__tls_get_addr[PR] ; SMALL64-NEXT: bla .__tls_get_addr[PR]
; SMALL64-NEXT: std 6, 0(3) ; SMALL64-NEXT: std 6, 0(3)
; SMALL64-NEXT: addi 1, 1, 48 ; SMALL64-NEXT: addi 1, 1, 48
; SMALL64-NEXT: ld 0, 16(1) ; SMALL64-NEXT: ld 0, 16(1)
; SMALL64-NEXT: mtlr 0 ; SMALL64-NEXT: mtlr 0
; SMALL64-NEXT: blr ; SMALL64-NEXT: blr
; ;
; LARGE64-LABEL: storesTIInit: ; LARGE64-LABEL: storesTIInit:
; LARGE64: # %bb.0: # %entry ; LARGE64: # %bb.0: # %entry
; LARGE64-NEXT: mflr 0 ; LARGE64-NEXT: mflr 0
; LARGE64-NEXT: std 0, 16(1)
; LARGE64-NEXT: stdu 1, -48(1) ; LARGE64-NEXT: stdu 1, -48(1)
; LARGE64-NEXT: mr 6, 3 ; LARGE64-NEXT: mr 6, 3
; LARGE64-NEXT: addis 3, L..C4@u(2) ; LARGE64-NEXT: addis 3, L..C4@u(2)
; LARGE64-NEXT: addis 4, L..C5@u(2) ; LARGE64-NEXT: addis 4, L..C5@u(2)
; LARGE64-NEXT: std 0, 64(1)
; LARGE64-NEXT: ld 3, L..C4@l(3) ; LARGE64-NEXT: ld 3, L..C4@l(3)
; LARGE64-NEXT: ld 4, L..C5@l(4) ; LARGE64-NEXT: ld 4, L..C5@l(4)
; LARGE64-NEXT: bla .__tls_get_addr[PR] ; LARGE64-NEXT: bla .__tls_get_addr[PR]
; LARGE64-NEXT: std 6, 0(3) ; LARGE64-NEXT: std 6, 0(3)
; LARGE64-NEXT: addi 1, 1, 48 ; LARGE64-NEXT: addi 1, 1, 48
; LARGE64-NEXT: ld 0, 16(1) ; LARGE64-NEXT: ld 0, 16(1)
; LARGE64-NEXT: mtlr 0 ; LARGE64-NEXT: mtlr 0
; LARGE64-NEXT: blr ; LARGE64-NEXT: blr
entry: entry:
store i64 %Val, ptr @TIInit, align 8 store i64 %Val, ptr @TIInit, align 8
ret void ret void
} }
; Function Attrs: nofree norecurse nounwind willreturn writeonly ; Function Attrs: nofree norecurse nounwind willreturn writeonly
define void @storesTWInit(i64 %Val) #0 { define void @storesTWInit(i64 %Val) #0 {
; SMALL32-LABEL: storesTWInit: ; SMALL32-LABEL: storesTWInit:
; SMALL32: # %bb.0: # %entry ; SMALL32: # %bb.0: # %entry
; SMALL32-NEXT: mflr 0 ; SMALL32-NEXT: mflr 0
; SMALL32-NEXT: stw 0, 8(1)
; SMALL32-NEXT: stwu 1, -32(1) ; SMALL32-NEXT: stwu 1, -32(1)
; SMALL32-NEXT: mr 6, 4 ; SMALL32-NEXT: mr 6, 4
; SMALL32-NEXT: mr 7, 3 ; SMALL32-NEXT: mr 7, 3
; SMALL32-NEXT: lwz 3, L..C6(2) ; SMALL32-NEXT: lwz 3, L..C6(2)
; SMALL32-NEXT: lwz 4, L..C7(2) ; SMALL32-NEXT: lwz 4, L..C7(2)
; SMALL32-NEXT: stw 0, 40(1)
; SMALL32-NEXT: bla .__tls_get_addr[PR] ; SMALL32-NEXT: bla .__tls_get_addr[PR]
; SMALL32-NEXT: stw 6, 4(3) ; SMALL32-NEXT: stw 6, 4(3)
; SMALL32-NEXT: stw 7, 0(3) ; SMALL32-NEXT: stw 7, 0(3)
; SMALL32-NEXT: addi 1, 1, 32 ; SMALL32-NEXT: addi 1, 1, 32
; SMALL32-NEXT: lwz 0, 8(1) ; SMALL32-NEXT: lwz 0, 8(1)
; SMALL32-NEXT: mtlr 0 ; SMALL32-NEXT: mtlr 0
; SMALL32-NEXT: blr ; SMALL32-NEXT: blr
; ;
; LARGE32-LABEL: storesTWInit: ; LARGE32-LABEL: storesTWInit:
; LARGE32: # %bb.0: # %entry ; LARGE32: # %bb.0: # %entry
; LARGE32-NEXT: mflr 0 ; LARGE32-NEXT: mflr 0
; LARGE32-NEXT: stw 0, 8(1)
; LARGE32-NEXT: stwu 1, -32(1) ; LARGE32-NEXT: stwu 1, -32(1)
; LARGE32-NEXT: stw 0, 40(1)
; LARGE32-NEXT: mr 6, 4 ; LARGE32-NEXT: mr 6, 4
; LARGE32-NEXT: mr 7, 3 ; LARGE32-NEXT: mr 7, 3
; LARGE32-NEXT: addis 3, L..C6@u(2) ; LARGE32-NEXT: addis 3, L..C6@u(2)
; LARGE32-NEXT: addis 4, L..C7@u(2) ; LARGE32-NEXT: addis 4, L..C7@u(2)
; LARGE32-NEXT: lwz 3, L..C6@l(3) ; LARGE32-NEXT: lwz 3, L..C6@l(3)
; LARGE32-NEXT: lwz 4, L..C7@l(4) ; LARGE32-NEXT: lwz 4, L..C7@l(4)
; LARGE32-NEXT: bla .__tls_get_addr[PR] ; LARGE32-NEXT: bla .__tls_get_addr[PR]
; LARGE32-NEXT: stw 6, 4(3) ; LARGE32-NEXT: stw 6, 4(3)
; LARGE32-NEXT: stw 7, 0(3) ; LARGE32-NEXT: stw 7, 0(3)
; LARGE32-NEXT: addi 1, 1, 32 ; LARGE32-NEXT: addi 1, 1, 32
; LARGE32-NEXT: lwz 0, 8(1) ; LARGE32-NEXT: lwz 0, 8(1)
; LARGE32-NEXT: mtlr 0 ; LARGE32-NEXT: mtlr 0
; LARGE32-NEXT: blr ; LARGE32-NEXT: blr
; ;
; SMALL64-LABEL: storesTWInit: ; SMALL64-LABEL: storesTWInit:
; SMALL64: # %bb.0: # %entry ; SMALL64: # %bb.0: # %entry
; SMALL64-NEXT: mflr 0 ; SMALL64-NEXT: mflr 0
; SMALL64-NEXT: std 0, 16(1)
; SMALL64-NEXT: stdu 1, -48(1) ; SMALL64-NEXT: stdu 1, -48(1)
; SMALL64-NEXT: mr 6, 3 ; SMALL64-NEXT: mr 6, 3
; SMALL64-NEXT: ld 3, L..C6(2) ; SMALL64-NEXT: ld 3, L..C6(2)
; SMALL64-NEXT: ld 4, L..C7(2) ; SMALL64-NEXT: ld 4, L..C7(2)
; SMALL64-NEXT: std 0, 64(1)
; SMALL64-NEXT: bla .__tls_get_addr[PR] ; SMALL64-NEXT: bla .__tls_get_addr[PR]
; SMALL64-NEXT: std 6, 0(3) ; SMALL64-NEXT: std 6, 0(3)
; SMALL64-NEXT: addi 1, 1, 48 ; SMALL64-NEXT: addi 1, 1, 48
; SMALL64-NEXT: ld 0, 16(1) ; SMALL64-NEXT: ld 0, 16(1)
; SMALL64-NEXT: mtlr 0 ; SMALL64-NEXT: mtlr 0
; SMALL64-NEXT: blr ; SMALL64-NEXT: blr
; ;
; LARGE64-LABEL: storesTWInit: ; LARGE64-LABEL: storesTWInit:
; LARGE64: # %bb.0: # %entry ; LARGE64: # %bb.0: # %entry
; LARGE64-NEXT: mflr 0 ; LARGE64-NEXT: mflr 0
; LARGE64-NEXT: std 0, 16(1)
; LARGE64-NEXT: stdu 1, -48(1) ; LARGE64-NEXT: stdu 1, -48(1)
; LARGE64-NEXT: mr 6, 3 ; LARGE64-NEXT: mr 6, 3
; LARGE64-NEXT: addis 3, L..C6@u(2) ; LARGE64-NEXT: addis 3, L..C6@u(2)
; LARGE64-NEXT: addis 4, L..C7@u(2) ; LARGE64-NEXT: addis 4, L..C7@u(2)
; LARGE64-NEXT: std 0, 64(1)
; LARGE64-NEXT: ld 3, L..C6@l(3) ; LARGE64-NEXT: ld 3, L..C6@l(3)
; LARGE64-NEXT: ld 4, L..C7@l(4) ; LARGE64-NEXT: ld 4, L..C7@l(4)
; LARGE64-NEXT: bla .__tls_get_addr[PR] ; LARGE64-NEXT: bla .__tls_get_addr[PR]
; LARGE64-NEXT: std 6, 0(3) ; LARGE64-NEXT: std 6, 0(3)
; LARGE64-NEXT: addi 1, 1, 48 ; LARGE64-NEXT: addi 1, 1, 48
; LARGE64-NEXT: ld 0, 16(1) ; LARGE64-NEXT: ld 0, 16(1)
; LARGE64-NEXT: mtlr 0 ; LARGE64-NEXT: mtlr 0
; LARGE64-NEXT: blr ; LARGE64-NEXT: blr
entry: entry:
store i64 %Val, ptr @TWInit, align 8 store i64 %Val, ptr @TWInit, align 8
ret void ret void
} }
; Function Attrs: norecurse nounwind readonly willreturn ; Function Attrs: norecurse nounwind readonly willreturn
define i64 @loadsTGInit() #1 { define i64 @loadsTGInit() #1 {
; SMALL32-LABEL: loadsTGInit: ; SMALL32-LABEL: loadsTGInit:
; SMALL32: # %bb.0: # %entry ; SMALL32: # %bb.0: # %entry
; SMALL32-NEXT: mflr 0 ; SMALL32-NEXT: mflr 0
; SMALL32-NEXT: stw 0, 8(1)
; SMALL32-NEXT: stwu 1, -32(1) ; SMALL32-NEXT: stwu 1, -32(1)
; SMALL32-NEXT: lwz 3, L..C0(2) ; SMALL32-NEXT: lwz 3, L..C0(2)
; SMALL32-NEXT: lwz 4, L..C1(2) ; SMALL32-NEXT: lwz 4, L..C1(2)
; SMALL32-NEXT: stw 0, 40(1)
; SMALL32-NEXT: bla .__tls_get_addr[PR] ; SMALL32-NEXT: bla .__tls_get_addr[PR]
; SMALL32-NEXT: lwz 4, L..C8(2) ; SMALL32-NEXT: lwz 4, L..C8(2)
; SMALL32-NEXT: lwz 5, 4(3) ; SMALL32-NEXT: lwz 5, 4(3)
; SMALL32-NEXT: lwz 6, 4(4) ; SMALL32-NEXT: lwz 6, 4(4)
; SMALL32-NEXT: lwz 3, 0(3) ; SMALL32-NEXT: lwz 3, 0(3)
; SMALL32-NEXT: lwz 7, 0(4) ; SMALL32-NEXT: lwz 7, 0(4)
; SMALL32-NEXT: addc 4, 6, 5 ; SMALL32-NEXT: addc 4, 6, 5
; SMALL32-NEXT: adde 3, 7, 3 ; SMALL32-NEXT: adde 3, 7, 3
; SMALL32-NEXT: addi 1, 1, 32 ; SMALL32-NEXT: addi 1, 1, 32
; SMALL32-NEXT: lwz 0, 8(1) ; SMALL32-NEXT: lwz 0, 8(1)
; SMALL32-NEXT: mtlr 0 ; SMALL32-NEXT: mtlr 0
; SMALL32-NEXT: blr ; SMALL32-NEXT: blr
; ;
; LARGE32-LABEL: loadsTGInit: ; LARGE32-LABEL: loadsTGInit:
; LARGE32: # %bb.0: # %entry ; LARGE32: # %bb.0: # %entry
; LARGE32-NEXT: mflr 0 ; LARGE32-NEXT: mflr 0
; LARGE32-NEXT: stw 0, 8(1)
; LARGE32-NEXT: stwu 1, -32(1) ; LARGE32-NEXT: stwu 1, -32(1)
; LARGE32-NEXT: stw 0, 40(1)
; LARGE32-NEXT: addis 3, L..C0@u(2) ; LARGE32-NEXT: addis 3, L..C0@u(2)
; LARGE32-NEXT: addis 4, L..C1@u(2) ; LARGE32-NEXT: addis 4, L..C1@u(2)
; LARGE32-NEXT: lwz 3, L..C0@l(3) ; LARGE32-NEXT: lwz 3, L..C0@l(3)
; LARGE32-NEXT: lwz 4, L..C1@l(4) ; LARGE32-NEXT: lwz 4, L..C1@l(4)
; LARGE32-NEXT: bla .__tls_get_addr[PR] ; LARGE32-NEXT: bla .__tls_get_addr[PR]
; LARGE32-NEXT: lwz 4, 4(3) ; LARGE32-NEXT: lwz 4, 4(3)
; LARGE32-NEXT: lwz 3, 0(3) ; LARGE32-NEXT: lwz 3, 0(3)
; LARGE32-NEXT: addis 5, L..C8@u(2) ; LARGE32-NEXT: addis 5, L..C8@u(2)
; LARGE32-NEXT: lwz 5, L..C8@l(5) ; LARGE32-NEXT: lwz 5, L..C8@l(5)
; LARGE32-NEXT: lwz 6, 4(5) ; LARGE32-NEXT: lwz 6, 4(5)
; LARGE32-NEXT: lwz 5, 0(5) ; LARGE32-NEXT: lwz 5, 0(5)
; LARGE32-NEXT: addc 4, 6, 4 ; LARGE32-NEXT: addc 4, 6, 4
; LARGE32-NEXT: adde 3, 5, 3 ; LARGE32-NEXT: adde 3, 5, 3
; LARGE32-NEXT: addi 1, 1, 32 ; LARGE32-NEXT: addi 1, 1, 32
; LARGE32-NEXT: lwz 0, 8(1) ; LARGE32-NEXT: lwz 0, 8(1)
; LARGE32-NEXT: mtlr 0 ; LARGE32-NEXT: mtlr 0
; LARGE32-NEXT: blr ; LARGE32-NEXT: blr
; ;
; SMALL64-LABEL: loadsTGInit: ; SMALL64-LABEL: loadsTGInit:
; SMALL64: # %bb.0: # %entry ; SMALL64: # %bb.0: # %entry
; SMALL64-NEXT: mflr 0 ; SMALL64-NEXT: mflr 0
; SMALL64-NEXT: std 0, 16(1)
; SMALL64-NEXT: stdu 1, -48(1) ; SMALL64-NEXT: stdu 1, -48(1)
; SMALL64-NEXT: ld 3, L..C0(2) ; SMALL64-NEXT: ld 3, L..C0(2)
; SMALL64-NEXT: ld 4, L..C1(2) ; SMALL64-NEXT: ld 4, L..C1(2)
; SMALL64-NEXT: std 0, 64(1)
; SMALL64-NEXT: bla .__tls_get_addr[PR] ; SMALL64-NEXT: bla .__tls_get_addr[PR]
; SMALL64-NEXT: ld 4, L..C8(2) ; SMALL64-NEXT: ld 4, L..C8(2)
; SMALL64-NEXT: ld 3, 0(3) ; SMALL64-NEXT: ld 3, 0(3)
; SMALL64-NEXT: ld 4, 0(4) ; SMALL64-NEXT: ld 4, 0(4)
; SMALL64-NEXT: add 3, 4, 3 ; SMALL64-NEXT: add 3, 4, 3
; SMALL64-NEXT: addi 1, 1, 48 ; SMALL64-NEXT: addi 1, 1, 48
; SMALL64-NEXT: ld 0, 16(1) ; SMALL64-NEXT: ld 0, 16(1)
; SMALL64-NEXT: mtlr 0 ; SMALL64-NEXT: mtlr 0
; SMALL64-NEXT: blr ; SMALL64-NEXT: blr
; ;
; LARGE64-LABEL: loadsTGInit: ; LARGE64-LABEL: loadsTGInit:
; LARGE64: # %bb.0: # %entry ; LARGE64: # %bb.0: # %entry
; LARGE64-NEXT: mflr 0 ; LARGE64-NEXT: mflr 0
; LARGE64-NEXT: std 0, 16(1)
; LARGE64-NEXT: stdu 1, -48(1) ; LARGE64-NEXT: stdu 1, -48(1)
; LARGE64-NEXT: addis 3, L..C0@u(2) ; LARGE64-NEXT: addis 3, L..C0@u(2)
; LARGE64-NEXT: addis 4, L..C1@u(2) ; LARGE64-NEXT: addis 4, L..C1@u(2)
; LARGE64-NEXT: std 0, 64(1)
; LARGE64-NEXT: ld 3, L..C0@l(3) ; LARGE64-NEXT: ld 3, L..C0@l(3)
; LARGE64-NEXT: ld 4, L..C1@l(4) ; LARGE64-NEXT: ld 4, L..C1@l(4)
; LARGE64-NEXT: bla .__tls_get_addr[PR] ; LARGE64-NEXT: bla .__tls_get_addr[PR]
; LARGE64-NEXT: addis 4, L..C8@u(2) ; LARGE64-NEXT: addis 4, L..C8@u(2)
; LARGE64-NEXT: ld 3, 0(3) ; LARGE64-NEXT: ld 3, 0(3)
; LARGE64-NEXT: ld 4, L..C8@l(4) ; LARGE64-NEXT: ld 4, L..C8@l(4)
; LARGE64-NEXT: ld 4, 0(4) ; LARGE64-NEXT: ld 4, 0(4)
; LARGE64-NEXT: add 3, 4, 3 ; LARGE64-NEXT: add 3, 4, 3
; LARGE64-NEXT: addi 1, 1, 48 ; LARGE64-NEXT: addi 1, 1, 48
; LARGE64-NEXT: ld 0, 16(1) ; LARGE64-NEXT: ld 0, 16(1)
; LARGE64-NEXT: mtlr 0 ; LARGE64-NEXT: mtlr 0
; LARGE64-NEXT: blr ; LARGE64-NEXT: blr
entry: entry:
%0 = load i64, ptr @TGInit, align 8 %0 = load i64, ptr @TGInit, align 8
%1 = load i64, ptr @GInit, align 8 %1 = load i64, ptr @GInit, align 8
%add = add nsw i64 %1, %0 %add = add nsw i64 %1, %0
ret i64 %add ret i64 %add
} }
; Function Attrs: norecurse nounwind readonly willreturn ; Function Attrs: norecurse nounwind readonly willreturn
define i64 @loadsTIUninit() #1 { define i64 @loadsTIUninit() #1 {
; SMALL32-LABEL: loadsTIUninit: ; SMALL32-LABEL: loadsTIUninit:
; SMALL32: # %bb.0: # %entry ; SMALL32: # %bb.0: # %entry
; SMALL32-NEXT: mflr 0 ; SMALL32-NEXT: mflr 0
; SMALL32-NEXT: stw 0, 8(1)
; SMALL32-NEXT: stwu 1, -32(1) ; SMALL32-NEXT: stwu 1, -32(1)
; SMALL32-NEXT: lwz 3, L..C2(2) ; SMALL32-NEXT: lwz 3, L..C2(2)
; SMALL32-NEXT: lwz 4, L..C3(2) ; SMALL32-NEXT: lwz 4, L..C3(2)
; SMALL32-NEXT: stw 0, 40(1)
; SMALL32-NEXT: bla .__tls_get_addr[PR] ; SMALL32-NEXT: bla .__tls_get_addr[PR]
; SMALL32-NEXT: lwz 4, L..C8(2) ; SMALL32-NEXT: lwz 4, L..C8(2)
; SMALL32-NEXT: lwz 5, 4(3) ; SMALL32-NEXT: lwz 5, 4(3)
; SMALL32-NEXT: lwz 6, 4(4) ; SMALL32-NEXT: lwz 6, 4(4)
; SMALL32-NEXT: lwz 3, 0(3) ; SMALL32-NEXT: lwz 3, 0(3)
; SMALL32-NEXT: lwz 7, 0(4) ; SMALL32-NEXT: lwz 7, 0(4)
; SMALL32-NEXT: addc 4, 6, 5 ; SMALL32-NEXT: addc 4, 6, 5
; SMALL32-NEXT: adde 3, 7, 3 ; SMALL32-NEXT: adde 3, 7, 3
; SMALL32-NEXT: addi 1, 1, 32 ; SMALL32-NEXT: addi 1, 1, 32
; SMALL32-NEXT: lwz 0, 8(1) ; SMALL32-NEXT: lwz 0, 8(1)
; SMALL32-NEXT: mtlr 0 ; SMALL32-NEXT: mtlr 0
; SMALL32-NEXT: blr ; SMALL32-NEXT: blr
; ;
; LARGE32-LABEL: loadsTIUninit: ; LARGE32-LABEL: loadsTIUninit:
; LARGE32: # %bb.0: # %entry ; LARGE32: # %bb.0: # %entry
; LARGE32-NEXT: mflr 0 ; LARGE32-NEXT: mflr 0
; LARGE32-NEXT: stw 0, 8(1)
; LARGE32-NEXT: stwu 1, -32(1) ; LARGE32-NEXT: stwu 1, -32(1)
; LARGE32-NEXT: stw 0, 40(1)
; LARGE32-NEXT: addis 3, L..C2@u(2) ; LARGE32-NEXT: addis 3, L..C2@u(2)
; LARGE32-NEXT: addis 4, L..C3@u(2) ; LARGE32-NEXT: addis 4, L..C3@u(2)
; LARGE32-NEXT: lwz 3, L..C2@l(3) ; LARGE32-NEXT: lwz 3, L..C2@l(3)
; LARGE32-NEXT: lwz 4, L..C3@l(4) ; LARGE32-NEXT: lwz 4, L..C3@l(4)
; LARGE32-NEXT: bla .__tls_get_addr[PR] ; LARGE32-NEXT: bla .__tls_get_addr[PR]
; LARGE32-NEXT: lwz 4, 4(3) ; LARGE32-NEXT: lwz 4, 4(3)
; LARGE32-NEXT: lwz 3, 0(3) ; LARGE32-NEXT: lwz 3, 0(3)
; LARGE32-NEXT: addis 5, L..C8@u(2) ; LARGE32-NEXT: addis 5, L..C8@u(2)
; LARGE32-NEXT: lwz 5, L..C8@l(5) ; LARGE32-NEXT: lwz 5, L..C8@l(5)
; LARGE32-NEXT: lwz 6, 4(5) ; LARGE32-NEXT: lwz 6, 4(5)
; LARGE32-NEXT: lwz 5, 0(5) ; LARGE32-NEXT: lwz 5, 0(5)
; LARGE32-NEXT: addc 4, 6, 4 ; LARGE32-NEXT: addc 4, 6, 4
; LARGE32-NEXT: adde 3, 5, 3 ; LARGE32-NEXT: adde 3, 5, 3
; LARGE32-NEXT: addi 1, 1, 32 ; LARGE32-NEXT: addi 1, 1, 32
; LARGE32-NEXT: lwz 0, 8(1) ; LARGE32-NEXT: lwz 0, 8(1)
; LARGE32-NEXT: mtlr 0 ; LARGE32-NEXT: mtlr 0
; LARGE32-NEXT: blr ; LARGE32-NEXT: blr
; ;
; SMALL64-LABEL: loadsTIUninit: ; SMALL64-LABEL: loadsTIUninit:
; SMALL64: # %bb.0: # %entry ; SMALL64: # %bb.0: # %entry
; SMALL64-NEXT: mflr 0 ; SMALL64-NEXT: mflr 0
; SMALL64-NEXT: std 0, 16(1)
; SMALL64-NEXT: stdu 1, -48(1) ; SMALL64-NEXT: stdu 1, -48(1)
; SMALL64-NEXT: ld 3, L..C2(2) ; SMALL64-NEXT: ld 3, L..C2(2)
; SMALL64-NEXT: ld 4, L..C3(2) ; SMALL64-NEXT: ld 4, L..C3(2)
; SMALL64-NEXT: std 0, 64(1)
; SMALL64-NEXT: bla .__tls_get_addr[PR] ; SMALL64-NEXT: bla .__tls_get_addr[PR]
; SMALL64-NEXT: ld 4, L..C8(2) ; SMALL64-NEXT: ld 4, L..C8(2)
; SMALL64-NEXT: ld 3, 0(3) ; SMALL64-NEXT: ld 3, 0(3)
; SMALL64-NEXT: ld 4, 0(4) ; SMALL64-NEXT: ld 4, 0(4)
; SMALL64-NEXT: add 3, 4, 3 ; SMALL64-NEXT: add 3, 4, 3
; SMALL64-NEXT: addi 1, 1, 48 ; SMALL64-NEXT: addi 1, 1, 48
; SMALL64-NEXT: ld 0, 16(1) ; SMALL64-NEXT: ld 0, 16(1)
; SMALL64-NEXT: mtlr 0 ; SMALL64-NEXT: mtlr 0
; SMALL64-NEXT: blr ; SMALL64-NEXT: blr
; ;
; LARGE64-LABEL: loadsTIUninit: ; LARGE64-LABEL: loadsTIUninit:
; LARGE64: # %bb.0: # %entry ; LARGE64: # %bb.0: # %entry
; LARGE64-NEXT: mflr 0 ; LARGE64-NEXT: mflr 0
; LARGE64-NEXT: std 0, 16(1)
; LARGE64-NEXT: stdu 1, -48(1) ; LARGE64-NEXT: stdu 1, -48(1)
; LARGE64-NEXT: addis 3, L..C2@u(2) ; LARGE64-NEXT: addis 3, L..C2@u(2)
; LARGE64-NEXT: addis 4, L..C3@u(2) ; LARGE64-NEXT: addis 4, L..C3@u(2)
; LARGE64-NEXT: std 0, 64(1)
; LARGE64-NEXT: ld 3, L..C2@l(3) ; LARGE64-NEXT: ld 3, L..C2@l(3)
; LARGE64-NEXT: ld 4, L..C3@l(4) ; LARGE64-NEXT: ld 4, L..C3@l(4)
; LARGE64-NEXT: bla .__tls_get_addr[PR] ; LARGE64-NEXT: bla .__tls_get_addr[PR]
; LARGE64-NEXT: addis 4, L..C8@u(2) ; LARGE64-NEXT: addis 4, L..C8@u(2)
; LARGE64-NEXT: ld 3, 0(3) ; LARGE64-NEXT: ld 3, 0(3)
; LARGE64-NEXT: ld 4, L..C8@l(4) ; LARGE64-NEXT: ld 4, L..C8@l(4)
; LARGE64-NEXT: ld 4, 0(4) ; LARGE64-NEXT: ld 4, 0(4)
; LARGE64-NEXT: add 3, 4, 3 ; LARGE64-NEXT: add 3, 4, 3
; LARGE64-NEXT: addi 1, 1, 48 ; LARGE64-NEXT: addi 1, 1, 48
; LARGE64-NEXT: ld 0, 16(1) ; LARGE64-NEXT: ld 0, 16(1)
; LARGE64-NEXT: mtlr 0 ; LARGE64-NEXT: mtlr 0
; LARGE64-NEXT: blr ; LARGE64-NEXT: blr
entry: entry:
%0 = load i64, ptr @TIUninit, align 8 %0 = load i64, ptr @TIUninit, align 8
%1 = load i64, ptr @GInit, align 8 %1 = load i64, ptr @GInit, align 8
%add = add nsw i64 %1, %0 %add = add nsw i64 %1, %0
ret i64 %add ret i64 %add
} }
; Function Attrs: norecurse nounwind readonly willreturn ; Function Attrs: norecurse nounwind readonly willreturn
define i64 @loadsTIInit() #1 { define i64 @loadsTIInit() #1 {
; SMALL32-LABEL: loadsTIInit: ; SMALL32-LABEL: loadsTIInit:
; SMALL32: # %bb.0: # %entry ; SMALL32: # %bb.0: # %entry
; SMALL32-NEXT: mflr 0 ; SMALL32-NEXT: mflr 0
; SMALL32-NEXT: stw 0, 8(1)
; SMALL32-NEXT: stwu 1, -32(1) ; SMALL32-NEXT: stwu 1, -32(1)
; SMALL32-NEXT: lwz 3, L..C4(2) ; SMALL32-NEXT: lwz 3, L..C4(2)
; SMALL32-NEXT: lwz 4, L..C5(2) ; SMALL32-NEXT: lwz 4, L..C5(2)
; SMALL32-NEXT: stw 0, 40(1)
; SMALL32-NEXT: bla .__tls_get_addr[PR] ; SMALL32-NEXT: bla .__tls_get_addr[PR]
; SMALL32-NEXT: lwz 4, L..C8(2) ; SMALL32-NEXT: lwz 4, L..C8(2)
; SMALL32-NEXT: lwz 5, 4(3) ; SMALL32-NEXT: lwz 5, 4(3)
; SMALL32-NEXT: lwz 6, 4(4) ; SMALL32-NEXT: lwz 6, 4(4)
; SMALL32-NEXT: lwz 3, 0(3) ; SMALL32-NEXT: lwz 3, 0(3)
; SMALL32-NEXT: lwz 7, 0(4) ; SMALL32-NEXT: lwz 7, 0(4)
; SMALL32-NEXT: addc 4, 6, 5 ; SMALL32-NEXT: addc 4, 6, 5
; SMALL32-NEXT: adde 3, 7, 3 ; SMALL32-NEXT: adde 3, 7, 3
; SMALL32-NEXT: addi 1, 1, 32 ; SMALL32-NEXT: addi 1, 1, 32
; SMALL32-NEXT: lwz 0, 8(1) ; SMALL32-NEXT: lwz 0, 8(1)
; SMALL32-NEXT: mtlr 0 ; SMALL32-NEXT: mtlr 0
; SMALL32-NEXT: blr ; SMALL32-NEXT: blr
; ;
; LARGE32-LABEL: loadsTIInit: ; LARGE32-LABEL: loadsTIInit:
; LARGE32: # %bb.0: # %entry ; LARGE32: # %bb.0: # %entry
; LARGE32-NEXT: mflr 0 ; LARGE32-NEXT: mflr 0
; LARGE32-NEXT: stw 0, 8(1)
; LARGE32-NEXT: stwu 1, -32(1) ; LARGE32-NEXT: stwu 1, -32(1)
; LARGE32-NEXT: stw 0, 40(1)
; LARGE32-NEXT: addis 3, L..C4@u(2) ; LARGE32-NEXT: addis 3, L..C4@u(2)
; LARGE32-NEXT: addis 4, L..C5@u(2) ; LARGE32-NEXT: addis 4, L..C5@u(2)
; LARGE32-NEXT: lwz 3, L..C4@l(3) ; LARGE32-NEXT: lwz 3, L..C4@l(3)
; LARGE32-NEXT: lwz 4, L..C5@l(4) ; LARGE32-NEXT: lwz 4, L..C5@l(4)
; LARGE32-NEXT: bla .__tls_get_addr[PR] ; LARGE32-NEXT: bla .__tls_get_addr[PR]
; LARGE32-NEXT: lwz 4, 4(3) ; LARGE32-NEXT: lwz 4, 4(3)
; LARGE32-NEXT: lwz 3, 0(3) ; LARGE32-NEXT: lwz 3, 0(3)
; LARGE32-NEXT: addis 5, L..C8@u(2) ; LARGE32-NEXT: addis 5, L..C8@u(2)
; LARGE32-NEXT: lwz 5, L..C8@l(5) ; LARGE32-NEXT: lwz 5, L..C8@l(5)
; LARGE32-NEXT: lwz 6, 4(5) ; LARGE32-NEXT: lwz 6, 4(5)
; LARGE32-NEXT: lwz 5, 0(5) ; LARGE32-NEXT: lwz 5, 0(5)
; LARGE32-NEXT: addc 4, 6, 4 ; LARGE32-NEXT: addc 4, 6, 4
; LARGE32-NEXT: adde 3, 5, 3 ; LARGE32-NEXT: adde 3, 5, 3
; LARGE32-NEXT: addi 1, 1, 32 ; LARGE32-NEXT: addi 1, 1, 32
; LARGE32-NEXT: lwz 0, 8(1) ; LARGE32-NEXT: lwz 0, 8(1)
; LARGE32-NEXT: mtlr 0 ; LARGE32-NEXT: mtlr 0
; LARGE32-NEXT: blr ; LARGE32-NEXT: blr
; ;
; SMALL64-LABEL: loadsTIInit: ; SMALL64-LABEL: loadsTIInit:
; SMALL64: # %bb.0: # %entry ; SMALL64: # %bb.0: # %entry
; SMALL64-NEXT: mflr 0 ; SMALL64-NEXT: mflr 0
; SMALL64-NEXT: std 0, 16(1)
; SMALL64-NEXT: stdu 1, -48(1) ; SMALL64-NEXT: stdu 1, -48(1)
; SMALL64-NEXT: ld 3, L..C4(2) ; SMALL64-NEXT: ld 3, L..C4(2)
; SMALL64-NEXT: ld 4, L..C5(2) ; SMALL64-NEXT: ld 4, L..C5(2)
; SMALL64-NEXT: std 0, 64(1)
; SMALL64-NEXT: bla .__tls_get_addr[PR] ; SMALL64-NEXT: bla .__tls_get_addr[PR]
; SMALL64-NEXT: ld 4, L..C8(2) ; SMALL64-NEXT: ld 4, L..C8(2)
; SMALL64-NEXT: ld 3, 0(3) ; SMALL64-NEXT: ld 3, 0(3)
; SMALL64-NEXT: ld 4, 0(4) ; SMALL64-NEXT: ld 4, 0(4)
; SMALL64-NEXT: add 3, 4, 3 ; SMALL64-NEXT: add 3, 4, 3
; SMALL64-NEXT: addi 1, 1, 48 ; SMALL64-NEXT: addi 1, 1, 48
; SMALL64-NEXT: ld 0, 16(1) ; SMALL64-NEXT: ld 0, 16(1)
; SMALL64-NEXT: mtlr 0 ; SMALL64-NEXT: mtlr 0
; SMALL64-NEXT: blr ; SMALL64-NEXT: blr
; ;
; LARGE64-LABEL: loadsTIInit: ; LARGE64-LABEL: loadsTIInit:
; LARGE64: # %bb.0: # %entry ; LARGE64: # %bb.0: # %entry
; LARGE64-NEXT: mflr 0 ; LARGE64-NEXT: mflr 0
; LARGE64-NEXT: std 0, 16(1)
; LARGE64-NEXT: stdu 1, -48(1) ; LARGE64-NEXT: stdu 1, -48(1)
; LARGE64-NEXT: addis 3, L..C4@u(2) ; LARGE64-NEXT: addis 3, L..C4@u(2)
; LARGE64-NEXT: addis 4, L..C5@u(2) ; LARGE64-NEXT: addis 4, L..C5@u(2)
; LARGE64-NEXT: std 0, 64(1)
; LARGE64-NEXT: ld 3, L..C4@l(3) ; LARGE64-NEXT: ld 3, L..C4@l(3)
; LARGE64-NEXT: ld 4, L..C5@l(4) ; LARGE64-NEXT: ld 4, L..C5@l(4)
; LARGE64-NEXT: bla .__tls_get_addr[PR] ; LARGE64-NEXT: bla .__tls_get_addr[PR]
; LARGE64-NEXT: addis 4, L..C8@u(2) ; LARGE64-NEXT: addis 4, L..C8@u(2)
; LARGE64-NEXT: ld 3, 0(3) ; LARGE64-NEXT: ld 3, 0(3)
; LARGE64-NEXT: ld 4, L..C8@l(4) ; LARGE64-NEXT: ld 4, L..C8@l(4)
; LARGE64-NEXT: ld 4, 0(4) ; LARGE64-NEXT: ld 4, 0(4)
; LARGE64-NEXT: add 3, 4, 3 ; LARGE64-NEXT: add 3, 4, 3
; LARGE64-NEXT: addi 1, 1, 48 ; LARGE64-NEXT: addi 1, 1, 48
; LARGE64-NEXT: ld 0, 16(1) ; LARGE64-NEXT: ld 0, 16(1)
; LARGE64-NEXT: mtlr 0 ; LARGE64-NEXT: mtlr 0
; LARGE64-NEXT: blr ; LARGE64-NEXT: blr
entry: entry:
%0 = load i64, ptr @TIInit, align 8 %0 = load i64, ptr @TIInit, align 8
%1 = load i64, ptr @GInit, align 8 %1 = load i64, ptr @GInit, align 8
%add = add nsw i64 %1, %0 %add = add nsw i64 %1, %0
ret i64 %add ret i64 %add
} }
; Function Attrs: norecurse nounwind readonly willreturn ; Function Attrs: norecurse nounwind readonly willreturn
define i64 @loadsTWInit() #1 { define i64 @loadsTWInit() #1 {
; SMALL32-LABEL: loadsTWInit: ; SMALL32-LABEL: loadsTWInit:
; SMALL32: # %bb.0: # %entry ; SMALL32: # %bb.0: # %entry
; SMALL32-NEXT: mflr 0 ; SMALL32-NEXT: mflr 0
; SMALL32-NEXT: stw 0, 8(1)
; SMALL32-NEXT: stwu 1, -32(1) ; SMALL32-NEXT: stwu 1, -32(1)
; SMALL32-NEXT: lwz 3, L..C6(2) ; SMALL32-NEXT: lwz 3, L..C6(2)
; SMALL32-NEXT: lwz 4, L..C7(2) ; SMALL32-NEXT: lwz 4, L..C7(2)
; SMALL32-NEXT: stw 0, 40(1)
; SMALL32-NEXT: bla .__tls_get_addr[PR] ; SMALL32-NEXT: bla .__tls_get_addr[PR]
; SMALL32-NEXT: lwz 4, L..C8(2) ; SMALL32-NEXT: lwz 4, L..C8(2)
; SMALL32-NEXT: lwz 5, 4(3) ; SMALL32-NEXT: lwz 5, 4(3)
; SMALL32-NEXT: lwz 6, 4(4) ; SMALL32-NEXT: lwz 6, 4(4)
; SMALL32-NEXT: lwz 3, 0(3) ; SMALL32-NEXT: lwz 3, 0(3)
; SMALL32-NEXT: lwz 7, 0(4) ; SMALL32-NEXT: lwz 7, 0(4)
; SMALL32-NEXT: addc 4, 6, 5 ; SMALL32-NEXT: addc 4, 6, 5
; SMALL32-NEXT: adde 3, 7, 3 ; SMALL32-NEXT: adde 3, 7, 3
; SMALL32-NEXT: addi 1, 1, 32 ; SMALL32-NEXT: addi 1, 1, 32
; SMALL32-NEXT: lwz 0, 8(1) ; SMALL32-NEXT: lwz 0, 8(1)
; SMALL32-NEXT: mtlr 0 ; SMALL32-NEXT: mtlr 0
; SMALL32-NEXT: blr ; SMALL32-NEXT: blr
; ;
; LARGE32-LABEL: loadsTWInit: ; LARGE32-LABEL: loadsTWInit:
; LARGE32: # %bb.0: # %entry ; LARGE32: # %bb.0: # %entry
; LARGE32-NEXT: mflr 0 ; LARGE32-NEXT: mflr 0
; LARGE32-NEXT: stw 0, 8(1)
; LARGE32-NEXT: stwu 1, -32(1) ; LARGE32-NEXT: stwu 1, -32(1)
; LARGE32-NEXT: stw 0, 40(1)
; LARGE32-NEXT: addis 3, L..C6@u(2) ; LARGE32-NEXT: addis 3, L..C6@u(2)
; LARGE32-NEXT: addis 4, L..C7@u(2) ; LARGE32-NEXT: addis 4, L..C7@u(2)
; LARGE32-NEXT: lwz 3, L..C6@l(3) ; LARGE32-NEXT: lwz 3, L..C6@l(3)
; LARGE32-NEXT: lwz 4, L..C7@l(4) ; LARGE32-NEXT: lwz 4, L..C7@l(4)
; LARGE32-NEXT: bla .__tls_get_addr[PR] ; LARGE32-NEXT: bla .__tls_get_addr[PR]
; LARGE32-NEXT: lwz 4, 4(3) ; LARGE32-NEXT: lwz 4, 4(3)
; LARGE32-NEXT: lwz 3, 0(3) ; LARGE32-NEXT: lwz 3, 0(3)
; LARGE32-NEXT: addis 5, L..C8@u(2) ; LARGE32-NEXT: addis 5, L..C8@u(2)
; LARGE32-NEXT: lwz 5, L..C8@l(5) ; LARGE32-NEXT: lwz 5, L..C8@l(5)
; LARGE32-NEXT: lwz 6, 4(5) ; LARGE32-NEXT: lwz 6, 4(5)
; LARGE32-NEXT: lwz 5, 0(5) ; LARGE32-NEXT: lwz 5, 0(5)
; LARGE32-NEXT: addc 4, 6, 4 ; LARGE32-NEXT: addc 4, 6, 4
; LARGE32-NEXT: adde 3, 5, 3 ; LARGE32-NEXT: adde 3, 5, 3
; LARGE32-NEXT: addi 1, 1, 32 ; LARGE32-NEXT: addi 1, 1, 32
; LARGE32-NEXT: lwz 0, 8(1) ; LARGE32-NEXT: lwz 0, 8(1)
; LARGE32-NEXT: mtlr 0 ; LARGE32-NEXT: mtlr 0
; LARGE32-NEXT: blr ; LARGE32-NEXT: blr
; ;
; SMALL64-LABEL: loadsTWInit: ; SMALL64-LABEL: loadsTWInit:
; SMALL64: # %bb.0: # %entry ; SMALL64: # %bb.0: # %entry
; SMALL64-NEXT: mflr 0 ; SMALL64-NEXT: mflr 0
; SMALL64-NEXT: std 0, 16(1)
; SMALL64-NEXT: stdu 1, -48(1) ; SMALL64-NEXT: stdu 1, -48(1)
; SMALL64-NEXT: ld 3, L..C6(2) ; SMALL64-NEXT: ld 3, L..C6(2)
; SMALL64-NEXT: ld 4, L..C7(2) ; SMALL64-NEXT: ld 4, L..C7(2)
; SMALL64-NEXT: std 0, 64(1)
; SMALL64-NEXT: bla .__tls_get_addr[PR] ; SMALL64-NEXT: bla .__tls_get_addr[PR]
; SMALL64-NEXT: ld 4, L..C8(2) ; SMALL64-NEXT: ld 4, L..C8(2)
; SMALL64-NEXT: ld 3, 0(3) ; SMALL64-NEXT: ld 3, 0(3)
; SMALL64-NEXT: ld 4, 0(4) ; SMALL64-NEXT: ld 4, 0(4)
; SMALL64-NEXT: add 3, 4, 3 ; SMALL64-NEXT: add 3, 4, 3
; SMALL64-NEXT: addi 1, 1, 48 ; SMALL64-NEXT: addi 1, 1, 48
; SMALL64-NEXT: ld 0, 16(1) ; SMALL64-NEXT: ld 0, 16(1)
; SMALL64-NEXT: mtlr 0 ; SMALL64-NEXT: mtlr 0
; SMALL64-NEXT: blr ; SMALL64-NEXT: blr
; ;
; LARGE64-LABEL: loadsTWInit: ; LARGE64-LABEL: loadsTWInit:
; LARGE64: # %bb.0: # %entry ; LARGE64: # %bb.0: # %entry
; LARGE64-NEXT: mflr 0 ; LARGE64-NEXT: mflr 0
; LARGE64-NEXT: std 0, 16(1)
; LARGE64-NEXT: stdu 1, -48(1) ; LARGE64-NEXT: stdu 1, -48(1)
; LARGE64-NEXT: addis 3, L..C6@u(2) ; LARGE64-NEXT: addis 3, L..C6@u(2)
; LARGE64-NEXT: addis 4, L..C7@u(2) ; LARGE64-NEXT: addis 4, L..C7@u(2)
; LARGE64-NEXT: std 0, 64(1)
; LARGE64-NEXT: ld 3, L..C6@l(3) ; LARGE64-NEXT: ld 3, L..C6@l(3)
; LARGE64-NEXT: ld 4, L..C7@l(4) ; LARGE64-NEXT: ld 4, L..C7@l(4)
; LARGE64-NEXT: bla .__tls_get_addr[PR] ; LARGE64-NEXT: bla .__tls_get_addr[PR]
; LARGE64-NEXT: addis 4, L..C8@u(2) ; LARGE64-NEXT: addis 4, L..C8@u(2)
; LARGE64-NEXT: ld 3, 0(3) ; LARGE64-NEXT: ld 3, 0(3)
; LARGE64-NEXT: ld 4, L..C8@l(4) ; LARGE64-NEXT: ld 4, L..C8@l(4)
; LARGE64-NEXT: ld 4, 0(4) ; LARGE64-NEXT: ld 4, 0(4)
; LARGE64-NEXT: add 3, 4, 3 ; LARGE64-NEXT: add 3, 4, 3
▲ Show 20 Lines • Show All 102 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/aix-tls-xcoff-reloc-large.ll

Show First 20 Lines • Show All 518 Lines • ▼ Show 20 Lines
; SYM-NEXT: } ; SYM-NEXT: }
; SYM-NEXT: } ; SYM-NEXT: }
; SYM-NEXT: ] ; SYM-NEXT: ]
; DIS: {{.*}}aix-tls-xcoff-reloc-large.ll.tmp.o: file format aixcoff-rs6000 ; DIS: {{.*}}aix-tls-xcoff-reloc-large.ll.tmp.o: file format aixcoff-rs6000
; DIS: Disassembly of section .text: ; DIS: Disassembly of section .text:
; DIS: 00000000 (idx: 5) .storesTIInit: ; DIS: 00000000 (idx: 5) .storesTIInit:
; DIS-NEXT: mflr 0 ; DIS-NEXT: mflr 0
; DIS-NEXT: stw 0, 8(1)
; DIS-NEXT: stwu 1, -32(1) ; DIS-NEXT: stwu 1, -32(1)
; DIS-NEXT: stw 0, 40(1)
; DIS-NEXT: mr 6, 4 ; DIS-NEXT: mr 6, 4
; DIS-NEXT: mr 7, 3 ; DIS-NEXT: mr 7, 3
; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} addis 3, 2, 0 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} addis 3, 2, 0
; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: 17) .TIInit[TE] ; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: 17) .TIInit[TE]
; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} addis 4, 2, 0 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} addis 4, 2, 0
; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: 19) TIInit[TE] ; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: 19) TIInit[TE]
; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 3, 0(3) ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 3, 0(3)
; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: 17) .TIInit[TE] ; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: 17) .TIInit[TE]
; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 4, 4(4) ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 4, 4(4)
; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: 19) TIInit[TE] ; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: 19) TIInit[TE]
; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} bla 0 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} bla 0
; DIS-NEXT: {{0*}}[[#ADDR]]: R_RBA (idx: 1) .__tls_get_addr[PR] ; DIS-NEXT: {{0*}}[[#ADDR]]: R_RBA (idx: 1) .__tls_get_addr[PR]
; DIS-NEXT: stw 6, 4(3) ; DIS-NEXT: stw 6, 4(3)
; DIS-NEXT: stw 7, 0(3) ; DIS-NEXT: stw 7, 0(3)
; DIS-NEXT: addi 1, 1, 32 ; DIS-NEXT: addi 1, 1, 32
; DIS-NEXT: lwz 0, 8(1) ; DIS-NEXT: lwz 0, 8(1)
; DIS-NEXT: mtlr 0 ; DIS-NEXT: mtlr 0
; DIS-NEXT: blr ; DIS-NEXT: blr
; DIS: 00000040 (idx: 7) .loadsTWInit: ; DIS: 00000040 (idx: 7) .loadsTWInit:
; DIS-NEXT: mflr 0 ; DIS-NEXT: mflr 0
; DIS-NEXT: stw 0, 8(1)
; DIS-NEXT: stwu 1, -32(1) ; DIS-NEXT: stwu 1, -32(1)
; DIS-NEXT: stw 0, 40(1)
; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} addis 3, 2, 0 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} addis 3, 2, 0
; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: 21) .TWInit[TE] ; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: 21) .TWInit[TE]
; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} addis 4, 2, 0 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} addis 4, 2, 0
; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: 23) TWInit[TE] ; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: 23) TWInit[TE]
; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 3, 8(3) ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 3, 8(3)
; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: 21) .TWInit[TE] ; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: 21) .TWInit[TE]
; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 4, 12(4) ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 4, 12(4)
; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: 23) TWInit[TE] ; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: 23) TWInit[TE]
▲ Show 20 Lines • Show All 56 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/aix-tls-xcoff-reloc.ll

Show All 26 Lines
; RELOC: File: {{.*}}aix-tls-xcoff-reloc.ll.tmp.o ; RELOC: File: {{.*}}aix-tls-xcoff-reloc.ll.tmp.o
; RELOC-NEXT: Format: aixcoff-rs6000 ; RELOC-NEXT: Format: aixcoff-rs6000
; RELOC-NEXT: Arch: powerpc ; RELOC-NEXT: Arch: powerpc
; RELOC-NEXT: AddressSize: 32bit ; RELOC-NEXT: AddressSize: 32bit
; RELOC-NEXT: Relocations [ ; RELOC-NEXT: Relocations [
; RELOC-NEXT: Section (index: 1) .text { ; RELOC-NEXT: Section (index: 1) .text {
; RELOC-NEXT: Relocation { ; RELOC-NEXT: Relocation {
; RELOC-NEXT: Virtual Address: 0x12 ; RELOC-NEXT: Virtual Address: 0xE
; RELOC-NEXT: Symbol: .TIUninit (23) ; RELOC-NEXT: Symbol: .TIUninit (23)
; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: IsSigned: No
; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: FixupBitValue: 0
; RELOC-NEXT: Length: 16 ; RELOC-NEXT: Length: 16
; RELOC-NEXT: Type: R_TOC (0x3) ; RELOC-NEXT: Type: R_TOC (0x3)
; RELOC-NEXT: } ; RELOC-NEXT: }
; RELOC-NEXT: Relocation { ; RELOC-NEXT: Relocation {
; RELOC-NEXT: Virtual Address: 0x16 ; RELOC-NEXT: Virtual Address: 0x12
; RELOC-NEXT: Symbol: TIUninit (25) ; RELOC-NEXT: Symbol: TIUninit (25)
; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: IsSigned: No
; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: FixupBitValue: 0
; RELOC-NEXT: Length: 16 ; RELOC-NEXT: Length: 16
; RELOC-NEXT: Type: R_TOC (0x3) ; RELOC-NEXT: Type: R_TOC (0x3)
; RELOC-NEXT: } ; RELOC-NEXT: }
; RELOC-NEXT: Relocation { ; RELOC-NEXT: Relocation {
; RELOC-NEXT: Virtual Address: 0x18 ; RELOC-NEXT: Virtual Address: 0x18
; RELOC-NEXT: Symbol: .__tls_get_addr (1) ; RELOC-NEXT: Symbol: .__tls_get_addr (1)
; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: IsSigned: No
; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: FixupBitValue: 0
; RELOC-NEXT: Length: 26 ; RELOC-NEXT: Length: 26
; RELOC-NEXT: Type: R_RBA (0x18) ; RELOC-NEXT: Type: R_RBA (0x18)
; RELOC-NEXT: } ; RELOC-NEXT: }
; RELOC-NEXT: Relocation { ; RELOC-NEXT: Relocation {
; RELOC-NEXT: Virtual Address: 0x3E ; RELOC-NEXT: Virtual Address: 0x3A
; RELOC-NEXT: Symbol: .TGInit (27) ; RELOC-NEXT: Symbol: .TGInit (27)
; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: IsSigned: No
; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: FixupBitValue: 0
; RELOC-NEXT: Length: 16 ; RELOC-NEXT: Length: 16
; RELOC-NEXT: Type: R_TOC (0x3) ; RELOC-NEXT: Type: R_TOC (0x3)
; RELOC-NEXT: } ; RELOC-NEXT: }
; RELOC-NEXT: Relocation { ; RELOC-NEXT: Relocation {
; RELOC-NEXT: Virtual Address: 0x42 ; RELOC-NEXT: Virtual Address: 0x3E
; RELOC-NEXT: Symbol: TGInit (29) ; RELOC-NEXT: Symbol: TGInit (29)
; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: IsSigned: No
; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: FixupBitValue: 0
; RELOC-NEXT: Length: 16 ; RELOC-NEXT: Length: 16
; RELOC-NEXT: Type: R_TOC (0x3) ; RELOC-NEXT: Type: R_TOC (0x3)
; RELOC-NEXT: } ; RELOC-NEXT: }
; RELOC-NEXT: Relocation { ; RELOC-NEXT: Relocation {
; RELOC-NEXT: Virtual Address: 0x44 ; RELOC-NEXT: Virtual Address: 0x44
▲ Show 20 Lines • Show All 484 Lines • ▼ Show 20 Lines
; SYM-NEXT: } ; SYM-NEXT: }
; SYM-NEXT: } ; SYM-NEXT: }
; SYM-NEXT: ] ; SYM-NEXT: ]
; DIS: {{.*}}aix-tls-xcoff-reloc.ll.tmp.o: file format aixcoff-rs6000 ; DIS: {{.*}}aix-tls-xcoff-reloc.ll.tmp.o: file format aixcoff-rs6000
; DIS: Disassembly of section .text: ; DIS: Disassembly of section .text:
; DIS: 00000000 (idx: 5) .storesTIUninit: ; DIS: 00000000 (idx: 5) .storesTIUninit:
; DIS-NEXT: mflr 0 ; DIS-NEXT: mflr 0
; DIS-NEXT: stw 0, 8(1)
; DIS-NEXT: stwu 1, -32(1) ; DIS-NEXT: stwu 1, -32(1)
; DIS-NEXT: mr 6, 3 ; DIS-NEXT: mr 6, 3
; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 3, 0(2) ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 3, 0(2)
; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC (idx: 23) .TIUninit[TC] ; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC (idx: 23) .TIUninit[TC]
; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 4, 4(2) ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 4, 4(2)
; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC (idx: 25) TIUninit[TC] ; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC (idx: 25) TIUninit[TC]
; DIS-NEXT: stw 0, 40(1)
; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} bla 0 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} bla 0
; DIS-NEXT: {{0*}}[[#ADDR]]: R_RBA (idx: 1) .__tls_get_addr[PR] ; DIS-NEXT: {{0*}}[[#ADDR]]: R_RBA (idx: 1) .__tls_get_addr[PR]
; DIS-NEXT: stw 6, 0(3) ; DIS-NEXT: stw 6, 0(3)
; DIS-NEXT: addi 1, 1, 32 ; DIS-NEXT: addi 1, 1, 32
; DIS-NEXT: lwz 0, 8(1) ; DIS-NEXT: lwz 0, 8(1)
; DIS-NEXT: mtlr 0 ; DIS-NEXT: mtlr 0
; DIS-NEXT: blr ; DIS-NEXT: blr
; DIS: 00000030 (idx: 7) .loadsTGInit: ; DIS: 00000030 (idx: 7) .loadsTGInit:
; DIS-NEXT: mflr 0 ; DIS-NEXT: mflr 0
; DIS-NEXT: stw 0, 8(1)
; DIS-NEXT: stwu 1, -32(1) ; DIS-NEXT: stwu 1, -32(1)
; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 3, 8(2) ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 3, 8(2)
; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC (idx: 27) .TGInit[TC] ; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC (idx: 27) .TGInit[TC]
; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 4, 12(2) ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 4, 12(2)
; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC (idx: 29) TGInit[TC] ; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC (idx: 29) TGInit[TC]
; DIS-NEXT: stw 0, 40(1)
; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} bla 0 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} bla 0
; DIS-NEXT: {{0*}}[[#ADDR]]: R_RBA (idx: 1) .__tls_get_addr[PR] ; DIS-NEXT: {{0*}}[[#ADDR]]: R_RBA (idx: 1) .__tls_get_addr[PR]
; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 4, 16(2) ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 4, 16(2)
; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC (idx: 31) GInit[TC] ; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC (idx: 31) GInit[TC]
; DIS-NEXT: lwz 3, 0(3) ; DIS-NEXT: lwz 3, 0(3)
; DIS-NEXT: lwz 4, 0(4) ; DIS-NEXT: lwz 4, 0(4)
; DIS-NEXT: add 3, 4, 3 ; DIS-NEXT: add 3, 4, 3
; DIS-NEXT: addi 1, 1, 32 ; DIS-NEXT: addi 1, 1, 32
▲ Show 20 Lines • Show All 47 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/aix-user-defined-memcpy.ll

Show First 20 Lines • Show All 100 Lines • ▼ Show 20 Lines
; 32-DIS: Disassembly of section .text: ; 32-DIS: Disassembly of section .text:
; 32-DIS: 00000000 <.memcpy>: ; 32-DIS: 00000000 <.memcpy>:
; 32-DIS-NEXT: 0: 38 60 00 03 li 3, 3 ; 32-DIS-NEXT: 0: 38 60 00 03 li 3, 3
; 32-DIS-NEXT: 4: 4e 80 00 20 blr ; 32-DIS-NEXT: 4: 4e 80 00 20 blr
; 32-DIS-NEXT: 8: 60 00 00 00 nop ; 32-DIS-NEXT: 8: 60 00 00 00 nop
; 32-DIS-NEXT: c: 60 00 00 00 nop ; 32-DIS-NEXT: c: 60 00 00 00 nop
; 32-DIS: 00000010 <.call_memcpy>: ; 32-DIS: 00000010 <.call_memcpy>:
; 32-DIS-NEXT: 10: 7c 08 02 a6 mflr 0 ; 32-DIS-NEXT: 10: 7c 08 02 a6 mflr 0
; 32-DIS-NEXT: 14: 90 01 00 08 stw 0, 8(1) ; 32-DIS-NEXT: 14: 94 21 ff c0 stwu 1, -64(1)
; 32-DIS-NEXT: 18: 94 21 ff c0 stwu 1, -64(1) ; 32-DIS-NEXT: 18: 90 01 00 48 stw 0, 72(1)
; 32-DIS-NEXT: 1c: 4b ff ff e5 bl 0x0 ; 32-DIS-NEXT: 1c: 4b ff ff e5 bl 0x0
; 32-DIS-NEXT: 20: 60 00 00 00 nop ; 32-DIS-NEXT: 20: 60 00 00 00 nop
; 32-DIS-NEXT: 24: 38 21 00 40 addi 1, 1, 64 ; 32-DIS-NEXT: 24: 38 21 00 40 addi 1, 1, 64
; 32-DIS-NEXT: 28: 80 01 00 08 lwz 0, 8(1) ; 32-DIS-NEXT: 28: 80 01 00 08 lwz 0, 8(1)
; 32-DIS-NEXT: 2c: 7c 08 03 a6 mtlr 0 ; 32-DIS-NEXT: 2c: 7c 08 03 a6 mtlr 0
; 32-DIS-NEXT: 30: 4e 80 00 20 blr ; 32-DIS-NEXT: 30: 4e 80 00 20 blr

llvm/test/CodeGen/PowerPC/aix-vec-arg-spills.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+altivec \ ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+altivec \
; RUN: -vec-extabi -mtriple powerpc-ibm-aix-xcoff < %s | \ ; RUN: -vec-extabi -mtriple powerpc-ibm-aix-xcoff < %s | \
; RUN: FileCheck %s --check-prefix=32BIT ; RUN: FileCheck %s --check-prefix=32BIT
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+altivec \ ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+altivec \
; RUN: -vec-extabi -mtriple powerpc64-ibm-aix-xcoff < %s | \ ; RUN: -vec-extabi -mtriple powerpc64-ibm-aix-xcoff < %s | \
; RUN: FileCheck %s --check-prefix=64BIT ; RUN: FileCheck %s --check-prefix=64BIT
%struct.Test = type { double, double, double, double } %struct.Test = type { double, double, double, double }
@__const.caller.t = private unnamed_addr constant %struct.Test { double 0.000000e+00, double 1.000000e+00, double 2.000000e+00, double 3.000000e+00 }, align 8 @__const.caller.t = private unnamed_addr constant %struct.Test { double 0.000000e+00, double 1.000000e+00, double 2.000000e+00, double 3.000000e+00 }, align 8
define double @caller() { define double @caller() {
; 32BIT-LABEL: caller: ; 32BIT-LABEL: caller:
; 32BIT: # %bb.0: # %entry ; 32BIT: # %bb.0: # %entry
; 32BIT-NEXT: mflr 0 ; 32BIT-NEXT: mflr 0
; 32BIT-NEXT: stw 0, 8(1)
; 32BIT-NEXT: stwu 1, -192(1) ; 32BIT-NEXT: stwu 1, -192(1)
; 32BIT-NEXT: lis 3, 16392 ; 32BIT-NEXT: lis 3, 16392
; 32BIT-NEXT: stw 0, 200(1)
; 32BIT-NEXT: lis 4, 16384 ; 32BIT-NEXT: lis 4, 16384
; 32BIT-NEXT: xxlxor 0, 0, 0 ; 32BIT-NEXT: xxlxor 0, 0, 0
; 32BIT-NEXT: lwz 5, L..C0(2) # %const.0 ; 32BIT-NEXT: lwz 5, L..C0(2) # %const.0
; 32BIT-NEXT: li 6, 512
; 32BIT-NEXT: stw 3, 180(1) ; 32BIT-NEXT: stw 3, 180(1)
; 32BIT-NEXT: li 3, 0 ; 32BIT-NEXT: li 3, 0
; 32BIT-NEXT: xxlxor 1, 1, 1 ; 32BIT-NEXT: xxlxor 1, 1, 1
; 32BIT-NEXT: li 6, 512
; 32BIT-NEXT: stw 4, 172(1) ; 32BIT-NEXT: stw 4, 172(1)
; 32BIT-NEXT: lis 4, 16368 ; 32BIT-NEXT: lis 4, 16368
; 32BIT-NEXT: xxlxor 2, 2, 2 ; 32BIT-NEXT: xxlxor 2, 2, 2
; 32BIT-NEXT: stw 3, 184(1) ; 32BIT-NEXT: stw 3, 184(1)
; 32BIT-NEXT: stw 3, 176(1) ; 32BIT-NEXT: stw 3, 176(1)
; 32BIT-NEXT: xxlxor 34, 34, 34 ; 32BIT-NEXT: xxlxor 34, 34, 34
; 32BIT-NEXT: stw 3, 168(1) ; 32BIT-NEXT: stw 3, 168(1)
; 32BIT-NEXT: stw 3, 160(1) ; 32BIT-NEXT: stw 3, 160(1)
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
; 32BIT-NEXT: addi 1, 1, 192 ; 32BIT-NEXT: addi 1, 1, 192
; 32BIT-NEXT: lwz 0, 8(1) ; 32BIT-NEXT: lwz 0, 8(1)
; 32BIT-NEXT: mtlr 0 ; 32BIT-NEXT: mtlr 0
; 32BIT-NEXT: blr ; 32BIT-NEXT: blr
; ;
; 64BIT-LABEL: caller: ; 64BIT-LABEL: caller:
; 64BIT: # %bb.0: # %entry ; 64BIT: # %bb.0: # %entry
; 64BIT-NEXT: mflr 0 ; 64BIT-NEXT: mflr 0
; 64BIT-NEXT: std 0, 16(1)
; 64BIT-NEXT: stdu 1, -224(1) ; 64BIT-NEXT: stdu 1, -224(1)
; 64BIT-NEXT: li 3, 2049 ; 64BIT-NEXT: li 3, 2049
; 64BIT-NEXT: std 0, 240(1)
; 64BIT-NEXT: li 4, 1 ; 64BIT-NEXT: li 4, 1
; 64BIT-NEXT: xxlxor 0, 0, 0 ; 64BIT-NEXT: xxlxor 0, 0, 0
; 64BIT-NEXT: li 5, 0
; 64BIT-NEXT: rldic 3, 3, 51, 1 ; 64BIT-NEXT: rldic 3, 3, 51, 1
; 64BIT-NEXT: rldic 4, 4, 62, 1 ; 64BIT-NEXT: rldic 4, 4, 62, 1
; 64BIT-NEXT: li 5, 0
; 64BIT-NEXT: xxlxor 1, 1, 1 ; 64BIT-NEXT: xxlxor 1, 1, 1
; 64BIT-NEXT: li 6, 144
; 64BIT-NEXT: std 3, 216(1) ; 64BIT-NEXT: std 3, 216(1)
; 64BIT-NEXT: li 3, 1023 ; 64BIT-NEXT: li 3, 1023
; 64BIT-NEXT: xxlxor 2, 2, 2 ; 64BIT-NEXT: xxlxor 2, 2, 2
; 64BIT-NEXT: li 6, 144
; 64BIT-NEXT: rldic 3, 3, 52, 2 ; 64BIT-NEXT: rldic 3, 3, 52, 2
; 64BIT-NEXT: std 4, 208(1) ; 64BIT-NEXT: std 4, 208(1)
; 64BIT-NEXT: li 4, 160 ; 64BIT-NEXT: li 4, 160
; 64BIT-NEXT: xxlxor 34, 34, 34 ; 64BIT-NEXT: xxlxor 34, 34, 34
; 64BIT-NEXT: std 3, 200(1) ; 64BIT-NEXT: std 3, 200(1)
; 64BIT-NEXT: ld 3, L..C0(2) # %const.0 ; 64BIT-NEXT: ld 3, L..C0(2) # %const.0
; 64BIT-NEXT: std 5, 192(1) ; 64BIT-NEXT: std 5, 192(1)
; 64BIT-NEXT: xxlxor 35, 35, 35 ; 64BIT-NEXT: xxlxor 35, 35, 35
▲ Show 20 Lines • Show All 45 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/aix-vector-stack-caller.ll

Show All 16 Lines
; LITERAL-NEXT: .vbyte 4, 49 ; LITERAL-NEXT: .vbyte 4, 49
; LITERAL-NEXT: .vbyte 4, 50 ; LITERAL-NEXT: .vbyte 4, 50
; LITERAL-NEXT: .vbyte 4, 51 ; LITERAL-NEXT: .vbyte 4, 51
; LITERAL-NEXT: .vbyte 4, 52 ; LITERAL-NEXT: .vbyte 4, 52
; 32BIT-LABEL: vec_caller: ; 32BIT-LABEL: vec_caller:
; 32BIT: # %bb.0: # %entry ; 32BIT: # %bb.0: # %entry
; 32BIT-NEXT: mflr 0 ; 32BIT-NEXT: mflr 0
; 32BIT-NEXT: stw 0, 8(1)
; 32BIT-NEXT: stwu 1, -64(1) ; 32BIT-NEXT: stwu 1, -64(1)
; 32BIT-NEXT: lwz 3, L..C0(2) ; 32BIT-NEXT: lwz 3, L..C0(2)
; 32BIT-NEXT: lwz 4, L..C1(2) ; 32BIT-NEXT: lwz 4, L..C1(2)
; 32BIT-NEXT: xxlxor 34, 34, 34 ; 32BIT-NEXT: xxlxor 34, 34, 34
; 32BIT-NEXT: stw 0, 72(1)
; 32BIT-NEXT: xxlxor 35, 35, 35 ; 32BIT-NEXT: xxlxor 35, 35, 35
; 32BIT-NEXT: xxlxor 36, 36, 36 ; 32BIT-NEXT: xxlxor 36, 36, 36
; 32BIT-NEXT: lxvw4x 0, 0, 3 ; 32BIT-NEXT: lxvw4x 0, 0, 3
; 32BIT-NEXT: lxvw4x 1, 0, 4 ; 32BIT-NEXT: lxvw4x 1, 0, 4
; 32BIT-NEXT: xxlxor 37, 37, 37 ; 32BIT-NEXT: xxlxor 37, 37, 37
; 32BIT-NEXT: li 3, 48 ; 32BIT-NEXT: li 3, 48
; 32BIT-NEXT: xxlxor 38, 38, 38 ; 32BIT-NEXT: xxlxor 38, 38, 38
; 32BIT-NEXT: li 4, 32 ; 32BIT-NEXT: li 4, 32
Show All 12 Lines
; 32BIT-NEXT: lwz 0, 8(1) ; 32BIT-NEXT: lwz 0, 8(1)
; 32BIT-NEXT: mtlr 0 ; 32BIT-NEXT: mtlr 0
; 32BIT-NEXT: blr ; 32BIT-NEXT: blr
; 64BIT-LABEL: vec_caller: ; 64BIT-LABEL: vec_caller:
; 64BIT: # %bb.0: # %entry ; 64BIT: # %bb.0: # %entry
; 64BIT-NEXT: mflr 0 ; 64BIT-NEXT: mflr 0
; 64BIT-NEXT: std 0, 16(1)
; 64BIT-NEXT: stdu 1, -112(1) ; 64BIT-NEXT: stdu 1, -112(1)
; 64BIT-NEXT: ld 3, L..C0(2) ; 64BIT-NEXT: ld 3, L..C0(2)
; 64BIT-NEXT: ld 4, L..C1(2) ; 64BIT-NEXT: ld 4, L..C1(2)
; 64BIT-NEXT: xxlxor 34, 34, 34 ; 64BIT-NEXT: xxlxor 34, 34, 34
; 64BIT-NEXT: std 0, 128(1)
; 64BIT-NEXT: xxlxor 35, 35, 35 ; 64BIT-NEXT: xxlxor 35, 35, 35
; 64BIT-NEXT: xxlxor 36, 36, 36 ; 64BIT-NEXT: xxlxor 36, 36, 36
; 64BIT-NEXT: lxvw4x 0, 0, 3 ; 64BIT-NEXT: lxvw4x 0, 0, 3
; 64BIT-NEXT: lxvw4x 1, 0, 4 ; 64BIT-NEXT: lxvw4x 1, 0, 4
; 64BIT-NEXT: xxlxor 37, 37, 37 ; 64BIT-NEXT: xxlxor 37, 37, 37
; 64BIT-NEXT: li 3, 64 ; 64BIT-NEXT: li 3, 64
; 64BIT-NEXT: xxlxor 38, 38, 38 ; 64BIT-NEXT: xxlxor 38, 38, 38
; 64BIT-NEXT: li 4, 48 ; 64BIT-NEXT: li 4, 48
Show All 28 Lines

llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll

Show First 20 Lines • Show All 453 Lines • ▼ Show 20 Lines
; SYM-NEXT: } ; SYM-NEXT: }
; SYM-NEXT: ] ; SYM-NEXT: ]
; DIS: {{.*}}aix-xcoff-reloc.ll.tmp.o: file format aixcoff-rs6000 ; DIS: {{.*}}aix-xcoff-reloc.ll.tmp.o: file format aixcoff-rs6000
; DIS: Disassembly of section .text: ; DIS: Disassembly of section .text:
; DIS: 00000000 <.foo>: ; DIS: 00000000 <.foo>:
; DIS-NEXT: 0: 7c 08 02 a6 mflr 0 ; DIS-NEXT: 0: 7c 08 02 a6 mflr 0
; DIS-NEXT: 4: 90 01 00 08 stw 0, 8(1) ; DIS-NEXT: 4: 94 21 ff c0 stwu 1, -64(1)
; DIS-NEXT: 8: 94 21 ff c0 stwu 1, -64(1) ; DIS-NEXT: 8: 38 60 00 01 li 3, 1
; DIS-NEXT: c: 38 60 00 01 li 3, 1 ; DIS-NEXT: c: 90 01 00 48 stw 0, 72(1)
; DIS-NEXT: 10: 4b ff ff f1 bl 0x0 ; DIS-NEXT: 10: 4b ff ff f1 bl 0x0
; DIS-NEXT: 14: 60 00 00 00 nop ; DIS-NEXT: 14: 60 00 00 00 nop
; DIS-NEXT: 18: 80 82 00 00 lwz 4, 0(2) ; DIS-NEXT: 18: 80 82 00 00 lwz 4, 0(2)
; DIS-NEXT: 1c: 80 a2 00 04 lwz 5, 4(2) ; DIS-NEXT: 1c: 80 a2 00 04 lwz 5, 4(2)
; DIS-NEXT: 20: 80 84 00 00 lwz 4, 0(4) ; DIS-NEXT: 20: 80 84 00 00 lwz 4, 0(4)
; DIS-NEXT: 24: 80 a5 00 00 lwz 5, 0(5) ; DIS-NEXT: 24: 80 a5 00 00 lwz 5, 0(5)
; DIS-NEXT: 28: 7c 63 22 14 add 3, 3, 4 ; DIS-NEXT: 28: 7c 63 22 14 add 3, 3, 4
; DIS-NEXT: 2c: 7c 63 2a 14 add 3, 3, 5 ; DIS-NEXT: 2c: 7c 63 2a 14 add 3, 3, 5
Show All 33 Lines
; DIS_REL-NEXT: 00000034 R_POS .foo ; DIS_REL-NEXT: 00000034 R_POS .foo
; DIS_REL-NEXT: 00000038 R_POS TOC ; DIS_REL-NEXT: 00000038 R_POS TOC
; DIS_REL-NEXT: 00000040 R_POS globalA ; DIS_REL-NEXT: 00000040 R_POS globalA
; DIS_REL-NEXT: 00000044 R_POS globalB ; DIS_REL-NEXT: 00000044 R_POS globalB
; DIS64: Disassembly of section .text: ; DIS64: Disassembly of section .text:
; DIS64: 0000000000000000 <.foo>: ; DIS64: 0000000000000000 <.foo>:
; DIS64-NEXT: 0: 7c 08 02 a6 mflr 0 ; DIS64-NEXT: 0: 7c 08 02 a6 mflr 0
; DIS64-NEXT: 4: f8 01 00 10 std 0, 16(1) ; DIS64-NEXT: 4: f8 21 ff 91 stdu 1, -112(1)
; DIS64-NEXT: 8: f8 21 ff 91 stdu 1, -112(1) ; DIS64-NEXT: 8: 38 60 00 01 li 3, 1
; DIS64-NEXT: c: 38 60 00 01 li 3, 1 ; DIS64-NEXT: c: f8 01 00 80 std 0, 128(1)
; DIS64-NEXT: 10: 4b ff ff f1 bl 0x0 <.foo> ; DIS64-NEXT: 10: 4b ff ff f1 bl 0x0 <.foo>
; DIS64-NEXT: 14: 60 00 00 00 nop ; DIS64-NEXT: 14: 60 00 00 00 nop
; DIS64-NEXT: 18: e8 82 00 00 ld 4, 0(2) ; DIS64-NEXT: 18: e8 82 00 00 ld 4, 0(2)
; DIS64-NEXT: 1c: e8 a2 00 08 ld 5, 8(2) ; DIS64-NEXT: 1c: e8 a2 00 08 ld 5, 8(2)
; DIS64-NEXT: 20: 80 84 00 00 lwz 4, 0(4) ; DIS64-NEXT: 20: 80 84 00 00 lwz 4, 0(4)
; DIS64-NEXT: 24: 80 a5 00 00 lwz 5, 0(5) ; DIS64-NEXT: 24: 80 a5 00 00 lwz 5, 0(5)
; DIS64-NEXT: 28: 7c 63 22 14 add 3, 3, 4 ; DIS64-NEXT: 28: 7c 63 22 14 add 3, 3, 4
; DIS64-NEXT: 2c: 7c 63 2a 14 add 3, 3, 5 ; DIS64-NEXT: 2c: 7c 63 2a 14 add 3, 3, 5
Show All 40 Lines

llvm/test/CodeGen/PowerPC/aix-xcoff-symbol-rename.ll

Show First 20 Lines • Show All 101 Lines • ▼ Show 20 Lines
; ASM-NEXT: L..C1: ; ASM-NEXT: L..C1:
; ASM-NEXT: .tc _Renamed..40f_o[TC],_Renamed..40f_o[DS] ; ASM-NEXT: .tc _Renamed..40f_o[TC],_Renamed..40f_o[DS]
; ASM-NEXT: .rename _Renamed..40f_o[TC],"f@o" ; ASM-NEXT: .rename _Renamed..40f_o[TC],"f@o"
; OBJ: Disassembly of section .text: ; OBJ: Disassembly of section .text:
; OBJ-EMPTY: ; OBJ-EMPTY:
; OBJ-NEXT: 00000000 (idx: 7) .f$o: ; OBJ-NEXT: 00000000 (idx: 7) .f$o:
; OBJ-NEXT: 0: 7c 08 02 a6 mflr 0 ; OBJ-NEXT: 0: 7c 08 02 a6 mflr 0
; OBJ-NEXT: 4: 90 01 00 08 stw 0, 8(1) ; OBJ-NEXT: 4: 94 21 ff c0 stwu 1, -64(1)
; OBJ-NEXT: 8: 94 21 ff c0 stwu 1, -64(1) ; OBJ-NEXT: 8: 90 01 00 48 stw 0, 72(1)
; OBJ-NEXT: c: 4b ff ff f5 bl 0x0 ; OBJ-NEXT: c: 4b ff ff f5 bl 0x0
; OBJ-NEXT: 0000000c: R_RBR (idx: 1) .f@o[PR] ; OBJ-NEXT: 0000000c: R_RBR (idx: 1) .f@o[PR]
; OBJ-NEXT: 10: 60 00 00 00 nop ; OBJ-NEXT: 10: 60 00 00 00 nop
; OBJ-NEXT: 14: 38 21 00 40 addi 1, 1, 64 ; OBJ-NEXT: 14: 38 21 00 40 addi 1, 1, 64
; OBJ-NEXT: 18: 80 01 00 08 lwz 0, 8(1) ; OBJ-NEXT: 18: 80 01 00 08 lwz 0, 8(1)
; OBJ-NEXT: 1c: 7c 08 03 a6 mtlr 0 ; OBJ-NEXT: 1c: 7c 08 03 a6 mtlr 0
; OBJ-NEXT: 20: 4e 80 00 20 blr ; OBJ-NEXT: 20: 4e 80 00 20 blr
; OBJ-NEXT: 24: 60 00 00 00 nop ; OBJ-NEXT: 24: 60 00 00 00 nop
; OBJ-NEXT: 28: 60 00 00 00 nop ; OBJ-NEXT: 28: 60 00 00 00 nop
; OBJ-NEXT: 2c: 60 00 00 00 nop ; OBJ-NEXT: 2c: 60 00 00 00 nop
; OBJ-EMPTY: ; OBJ-EMPTY:
; OBJ-NEXT: 00000030 (idx: 9) .f&o: ; OBJ-NEXT: 00000030 (idx: 9) .f&o:
; OBJ-NEXT: 30: 7c 08 02 a6 mflr 0 ; OBJ-NEXT: 30: 7c 08 02 a6 mflr 0
; OBJ-NEXT: 34: 90 01 00 08 stw 0, 8(1) ; OBJ-NEXT: 34: 94 21 ff c0 stwu 1, -64(1)
; OBJ-NEXT: 38: 94 21 ff c0 stwu 1, -64(1) ; OBJ-NEXT: 38: 90 01 00 48 stw 0, 72(1)
; OBJ-NEXT: 3c: 4b ff ff c5 bl 0x0 ; OBJ-NEXT: 3c: 4b ff ff c5 bl 0x0
; OBJ-NEXT: 40: 80 82 00 00 lwz 4, 0(2) ; OBJ-NEXT: 40: 80 82 00 00 lwz 4, 0(2)
; OBJ-NEXT: 00000042: R_TOC (idx: 25) f=o[TC] ; OBJ-NEXT: 00000042: R_TOC (idx: 25) f=o[TC]
; OBJ-NEXT: 44: 80 84 00 00 lwz 4, 0(4) ; OBJ-NEXT: 44: 80 84 00 00 lwz 4, 0(4)
; OBJ-NEXT: 48: 7c 63 22 14 add 3, 3, 4 ; OBJ-NEXT: 48: 7c 63 22 14 add 3, 3, 4
; OBJ-NEXT: 4c: 38 21 00 40 addi 1, 1, 64 ; OBJ-NEXT: 4c: 38 21 00 40 addi 1, 1, 64
; OBJ-NEXT: 50: 80 01 00 08 lwz 0, 8(1) ; OBJ-NEXT: 50: 80 01 00 08 lwz 0, 8(1)
; OBJ-NEXT: 54: 7c 08 03 a6 mtlr 0 ; OBJ-NEXT: 54: 7c 08 03 a6 mtlr 0
▲ Show 20 Lines • Show All 49 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/all-atomics.ll

Show First 20 Lines • Show All 503 Lines • ▼ Show 20 Lines
; CHECK-NEXT: ld 28, -32(1) # 8-byte Folded Reload ; CHECK-NEXT: ld 28, -32(1) # 8-byte Folded Reload
; CHECK-NEXT: ld 27, -40(1) # 8-byte Folded Reload ; CHECK-NEXT: ld 27, -40(1) # 8-byte Folded Reload
; CHECK-NEXT: ld 26, -48(1) # 8-byte Folded Reload ; CHECK-NEXT: ld 26, -48(1) # 8-byte Folded Reload
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; AIX32-LABEL: test_op_ignore: ; AIX32-LABEL: test_op_ignore:
; AIX32: # %bb.0: # %entry ; AIX32: # %bb.0: # %entry
; AIX32-NEXT: mflr 0 ; AIX32-NEXT: mflr 0
; AIX32-NEXT: stw 0, 8(1)
; AIX32-NEXT: stwu 1, -160(1) ; AIX32-NEXT: stwu 1, -160(1)
; AIX32-NEXT: lwz 3, L..C0(2) # @sc ; AIX32-NEXT: lwz 3, L..C0(2) # @sc
; AIX32-NEXT: stw 0, 168(1)
; AIX32-NEXT: stw 15, 92(1) # 4-byte Folded Spill ; AIX32-NEXT: stw 15, 92(1) # 4-byte Folded Spill
; AIX32-NEXT: stw 26, 136(1) # 4-byte Folded Spill ; AIX32-NEXT: stw 26, 136(1) # 4-byte Folded Spill
; AIX32-NEXT: stw 28, 144(1) # 4-byte Folded Spill ; AIX32-NEXT: stw 28, 144(1) # 4-byte Folded Spill
; AIX32-NEXT: li 15, 1 ; AIX32-NEXT: li 15, 1
; AIX32-NEXT: stw 16, 96(1) # 4-byte Folded Spill ; AIX32-NEXT: stw 16, 96(1) # 4-byte Folded Spill
; AIX32-NEXT: stw 17, 100(1) # 4-byte Folded Spill
; AIX32-NEXT: rlwinm 4, 3, 3, 27, 28 ; AIX32-NEXT: rlwinm 4, 3, 3, 27, 28
; AIX32-NEXT: rlwinm 28, 3, 0, 0, 29 ; AIX32-NEXT: rlwinm 28, 3, 0, 0, 29
; AIX32-NEXT: li 3, 255 ; AIX32-NEXT: li 3, 255
; AIX32-NEXT: xori 26, 4, 24 ; AIX32-NEXT: xori 26, 4, 24
; AIX32-NEXT: stw 17, 100(1) # 4-byte Folded Spill
; AIX32-NEXT: stw 18, 104(1) # 4-byte Folded Spill ; AIX32-NEXT: stw 18, 104(1) # 4-byte Folded Spill
; AIX32-NEXT: stw 19, 108(1) # 4-byte Folded Spill ; AIX32-NEXT: stw 19, 108(1) # 4-byte Folded Spill
; AIX32-NEXT: stw 20, 112(1) # 4-byte Folded Spill ; AIX32-NEXT: stw 20, 112(1) # 4-byte Folded Spill
; AIX32-NEXT: stw 21, 116(1) # 4-byte Folded Spill ; AIX32-NEXT: stw 21, 116(1) # 4-byte Folded Spill
; AIX32-NEXT: stw 22, 120(1) # 4-byte Folded Spill ; AIX32-NEXT: stw 22, 120(1) # 4-byte Folded Spill
; AIX32-NEXT: stw 23, 124(1) # 4-byte Folded Spill ; AIX32-NEXT: stw 23, 124(1) # 4-byte Folded Spill
; AIX32-NEXT: stw 24, 128(1) # 4-byte Folded Spill ; AIX32-NEXT: stw 24, 128(1) # 4-byte Folded Spill
; AIX32-NEXT: stw 25, 132(1) # 4-byte Folded Spill ; AIX32-NEXT: stw 25, 132(1) # 4-byte Folded Spill
▲ Show 20 Lines • Show All 1,217 Lines • ▼ Show 20 Lines
; CHECK-NEXT: ld 24, -64(1) # 8-byte Folded Reload ; CHECK-NEXT: ld 24, -64(1) # 8-byte Folded Reload
; CHECK-NEXT: ld 23, -72(1) # 8-byte Folded Reload ; CHECK-NEXT: ld 23, -72(1) # 8-byte Folded Reload
; CHECK-NEXT: ld 22, -80(1) # 8-byte Folded Reload ; CHECK-NEXT: ld 22, -80(1) # 8-byte Folded Reload
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; AIX32-LABEL: test_fetch_and_op: ; AIX32-LABEL: test_fetch_and_op:
; AIX32: # %bb.0: # %entry ; AIX32: # %bb.0: # %entry
; AIX32-NEXT: mflr 0 ; AIX32-NEXT: mflr 0
; AIX32-NEXT: stw 0, 8(1)
; AIX32-NEXT: stwu 1, -144(1) ; AIX32-NEXT: stwu 1, -144(1)
; AIX32-NEXT: lwz 4, L..C0(2) # @sc ; AIX32-NEXT: lwz 4, L..C0(2) # @sc
; AIX32-NEXT: stw 0, 152(1)
; AIX32-NEXT: stw 26, 120(1) # 4-byte Folded Spill ; AIX32-NEXT: stw 26, 120(1) # 4-byte Folded Spill
; AIX32-NEXT: li 7, 11 ; AIX32-NEXT: li 7, 11
; AIX32-NEXT: stw 13, 68(1) # 4-byte Folded Spill ; AIX32-NEXT: stw 13, 68(1) # 4-byte Folded Spill
; AIX32-NEXT: stw 14, 72(1) # 4-byte Folded Spill ; AIX32-NEXT: stw 14, 72(1) # 4-byte Folded Spill
; AIX32-NEXT: stw 15, 76(1) # 4-byte Folded Spill ; AIX32-NEXT: stw 15, 76(1) # 4-byte Folded Spill
; AIX32-NEXT: stw 16, 80(1) # 4-byte Folded Spill
; AIX32-NEXT: rlwinm 3, 4, 3, 27, 28 ; AIX32-NEXT: rlwinm 3, 4, 3, 27, 28
; AIX32-NEXT: stw 17, 84(1) # 4-byte Folded Spill ; AIX32-NEXT: stw 16, 80(1) # 4-byte Folded Spill
; AIX32-NEXT: xori 26, 3, 24 ; AIX32-NEXT: xori 26, 3, 24
; AIX32-NEXT: li 3, 255 ; AIX32-NEXT: li 3, 255
; AIX32-NEXT: stw 17, 84(1) # 4-byte Folded Spill
; AIX32-NEXT: stw 18, 88(1) # 4-byte Folded Spill ; AIX32-NEXT: stw 18, 88(1) # 4-byte Folded Spill
; AIX32-NEXT: stw 19, 92(1) # 4-byte Folded Spill ; AIX32-NEXT: stw 19, 92(1) # 4-byte Folded Spill
; AIX32-NEXT: stw 20, 96(1) # 4-byte Folded Spill ; AIX32-NEXT: stw 20, 96(1) # 4-byte Folded Spill
; AIX32-NEXT: stw 21, 100(1) # 4-byte Folded Spill ; AIX32-NEXT: stw 21, 100(1) # 4-byte Folded Spill
; AIX32-NEXT: stw 22, 104(1) # 4-byte Folded Spill ; AIX32-NEXT: stw 22, 104(1) # 4-byte Folded Spill
; AIX32-NEXT: stw 23, 108(1) # 4-byte Folded Spill ; AIX32-NEXT: stw 23, 108(1) # 4-byte Folded Spill
; AIX32-NEXT: stw 24, 112(1) # 4-byte Folded Spill ; AIX32-NEXT: stw 24, 112(1) # 4-byte Folded Spill
; AIX32-NEXT: stw 25, 116(1) # 4-byte Folded Spill ; AIX32-NEXT: stw 25, 116(1) # 4-byte Folded Spill
; AIX32-NEXT: stw 27, 124(1) # 4-byte Folded Spill ; AIX32-NEXT: stw 27, 124(1) # 4-byte Folded Spill
; AIX32-NEXT: stw 28, 128(1) # 4-byte Folded Spill ; AIX32-NEXT: stw 28, 128(1) # 4-byte Folded Spill
; AIX32-NEXT: stw 29, 132(1) # 4-byte Folded Spill ; AIX32-NEXT: stw 29, 132(1) # 4-byte Folded Spill
; AIX32-NEXT: stw 30, 136(1) # 4-byte Folded Spill ; AIX32-NEXT: stw 30, 136(1) # 4-byte Folded Spill
; AIX32-NEXT: stw 31, 140(1) # 4-byte Folded Spill ; AIX32-NEXT: stw 31, 140(1) # 4-byte Folded Spill
; AIX32-NEXT: stw 4, 64(1) # 4-byte Folded Spill ; AIX32-NEXT: stw 4, 64(1) # 4-byte Folded Spill
; AIX32-NEXT: rlwinm 24, 4, 0, 0, 29 ; AIX32-NEXT: rlwinm 24, 4, 0, 0, 29
; AIX32-NEXT: slw 23, 7, 26 ; AIX32-NEXT: slw 23, 7, 26
; AIX32-NEXT: sync
; AIX32-NEXT: slw 4, 3, 26 ; AIX32-NEXT: slw 4, 3, 26
; AIX32-NEXT: sync
; AIX32-NEXT: L..BB1_1: # %entry ; AIX32-NEXT: L..BB1_1: # %entry
; AIX32-NEXT: # ; AIX32-NEXT: #
; AIX32-NEXT: lwarx 3, 0, 24 ; AIX32-NEXT: lwarx 3, 0, 24
; AIX32-NEXT: add 5, 23, 3 ; AIX32-NEXT: add 5, 23, 3
; AIX32-NEXT: andc 6, 3, 4 ; AIX32-NEXT: andc 6, 3, 4
; AIX32-NEXT: and 5, 5, 4 ; AIX32-NEXT: and 5, 5, 4
; AIX32-NEXT: or 5, 5, 6 ; AIX32-NEXT: or 5, 5, 6
; AIX32-NEXT: stwcx. 5, 0, 24 ; AIX32-NEXT: stwcx. 5, 0, 24
▲ Show 20 Lines • Show All 1,395 Lines • ▼ Show 20 Lines
; CHECK-NEXT: ld 18, -112(1) # 8-byte Folded Reload ; CHECK-NEXT: ld 18, -112(1) # 8-byte Folded Reload
; CHECK-NEXT: ld 17, -120(1) # 8-byte Folded Reload ; CHECK-NEXT: ld 17, -120(1) # 8-byte Folded Reload
; CHECK-NEXT: ld 16, -128(1) # 8-byte Folded Reload ; CHECK-NEXT: ld 16, -128(1) # 8-byte Folded Reload
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; AIX32-LABEL: test_op_and_fetch: ; AIX32-LABEL: test_op_and_fetch:
; AIX32: # %bb.0: # %entry ; AIX32: # %bb.0: # %entry
; AIX32-NEXT: mflr 0 ; AIX32-NEXT: mflr 0
; AIX32-NEXT: stw 0, 8(1)
; AIX32-NEXT: stwu 1, -176(1) ; AIX32-NEXT: stwu 1, -176(1)
; AIX32-NEXT: stw 0, 184(1)
; AIX32-NEXT: stw 24, 144(1) # 4-byte Folded Spill ; AIX32-NEXT: stw 24, 144(1) # 4-byte Folded Spill
; AIX32-NEXT: lwz 24, L..C0(2) # @sc
; AIX32-NEXT: stw 26, 152(1) # 4-byte Folded Spill ; AIX32-NEXT: stw 26, 152(1) # 4-byte Folded Spill
; AIX32-NEXT: lwz 26, L..C1(2) # @uc ; AIX32-NEXT: lwz 26, L..C1(2) # @uc
; AIX32-NEXT: lwz 24, L..C0(2) # @sc
; AIX32-NEXT: stw 23, 140(1) # 4-byte Folded Spill ; AIX32-NEXT: stw 23, 140(1) # 4-byte Folded Spill
; AIX32-NEXT: li 5, 255 ; AIX32-NEXT: li 5, 255
; AIX32-NEXT: stw 13, 100(1) # 4-byte Folded Spill ; AIX32-NEXT: stw 13, 100(1) # 4-byte Folded Spill
; AIX32-NEXT: rlwinm 4, 24, 3, 27, 28
; AIX32-NEXT: stw 14, 104(1) # 4-byte Folded Spill ; AIX32-NEXT: stw 14, 104(1) # 4-byte Folded Spill
; AIX32-NEXT: lbz 3, 0(26) ; AIX32-NEXT: lbz 3, 0(26)
; AIX32-NEXT: rlwinm 4, 24, 3, 27, 28
; AIX32-NEXT: stw 15, 108(1) # 4-byte Folded Spill
; AIX32-NEXT: xori 23, 4, 24 ; AIX32-NEXT: xori 23, 4, 24
; AIX32-NEXT: stw 15, 108(1) # 4-byte Folded Spill
; AIX32-NEXT: stw 16, 112(1) # 4-byte Folded Spill ; AIX32-NEXT: stw 16, 112(1) # 4-byte Folded Spill
; AIX32-NEXT: stw 17, 116(1) # 4-byte Folded Spill ; AIX32-NEXT: stw 17, 116(1) # 4-byte Folded Spill
; AIX32-NEXT: stw 18, 120(1) # 4-byte Folded Spill ; AIX32-NEXT: stw 18, 120(1) # 4-byte Folded Spill
; AIX32-NEXT: stw 19, 124(1) # 4-byte Folded Spill ; AIX32-NEXT: stw 19, 124(1) # 4-byte Folded Spill
; AIX32-NEXT: stw 20, 128(1) # 4-byte Folded Spill ; AIX32-NEXT: stw 20, 128(1) # 4-byte Folded Spill
; AIX32-NEXT: stw 21, 132(1) # 4-byte Folded Spill ; AIX32-NEXT: stw 21, 132(1) # 4-byte Folded Spill
; AIX32-NEXT: stw 22, 136(1) # 4-byte Folded Spill ; AIX32-NEXT: stw 22, 136(1) # 4-byte Folded Spill
; AIX32-NEXT: stw 25, 148(1) # 4-byte Folded Spill ; AIX32-NEXT: stw 25, 148(1) # 4-byte Folded Spill
; AIX32-NEXT: stw 27, 156(1) # 4-byte Folded Spill ; AIX32-NEXT: stw 27, 156(1) # 4-byte Folded Spill
; AIX32-NEXT: stw 28, 160(1) # 4-byte Folded Spill ; AIX32-NEXT: stw 28, 160(1) # 4-byte Folded Spill
; AIX32-NEXT: stw 29, 164(1) # 4-byte Folded Spill ; AIX32-NEXT: stw 29, 164(1) # 4-byte Folded Spill
; AIX32-NEXT: stw 30, 168(1) # 4-byte Folded Spill ; AIX32-NEXT: stw 30, 168(1) # 4-byte Folded Spill
; AIX32-NEXT: stw 31, 172(1) # 4-byte Folded Spill ; AIX32-NEXT: stw 31, 172(1) # 4-byte Folded Spill
; AIX32-NEXT: rlwinm 22, 24, 0, 0, 29 ; AIX32-NEXT: rlwinm 22, 24, 0, 0, 29
; AIX32-NEXT: li 25, -1 ; AIX32-NEXT: li 25, -1
; AIX32-NEXT: sync
; AIX32-NEXT: slw 4, 3, 23 ; AIX32-NEXT: slw 4, 3, 23
; AIX32-NEXT: slw 6, 5, 23 ; AIX32-NEXT: slw 6, 5, 23
; AIX32-NEXT: sync
; AIX32-NEXT: L..BB2_1: # %entry ; AIX32-NEXT: L..BB2_1: # %entry
; AIX32-NEXT: # ; AIX32-NEXT: #
; AIX32-NEXT: lwarx 5, 0, 22 ; AIX32-NEXT: lwarx 5, 0, 22
; AIX32-NEXT: add 7, 4, 5 ; AIX32-NEXT: add 7, 4, 5
; AIX32-NEXT: andc 8, 5, 6 ; AIX32-NEXT: andc 8, 5, 6
; AIX32-NEXT: and 7, 7, 6 ; AIX32-NEXT: and 7, 7, 6
; AIX32-NEXT: or 7, 7, 8 ; AIX32-NEXT: or 7, 7, 8
; AIX32-NEXT: stwcx. 7, 0, 22 ; AIX32-NEXT: stwcx. 7, 0, 22
▲ Show 20 Lines • Show All 1,410 Lines • ▼ Show 20 Lines
; CHECK-NEXT: ld 27, -40(1) # 8-byte Folded Reload ; CHECK-NEXT: ld 27, -40(1) # 8-byte Folded Reload
; CHECK-NEXT: rldicl 3, 3, 58, 63 ; CHECK-NEXT: rldicl 3, 3, 58, 63
; CHECK-NEXT: stw 3, ui@toc@l(5) ; CHECK-NEXT: stw 3, ui@toc@l(5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; AIX32-LABEL: test_compare_and_swap: ; AIX32-LABEL: test_compare_and_swap:
; AIX32: # %bb.0: # %entry ; AIX32: # %bb.0: # %entry
; AIX32-NEXT: mflr 0 ; AIX32-NEXT: mflr 0
; AIX32-NEXT: stw 0, 8(1)
; AIX32-NEXT: stwu 1, -128(1) ; AIX32-NEXT: stwu 1, -128(1)
; AIX32-NEXT: stw 0, 136(1)
; AIX32-NEXT: stw 28, 112(1) # 4-byte Folded Spill ; AIX32-NEXT: stw 28, 112(1) # 4-byte Folded Spill
; AIX32-NEXT: stw 29, 116(1) # 4-byte Folded Spill
; AIX32-NEXT: lwz 28, L..C0(2) # @sc ; AIX32-NEXT: lwz 28, L..C0(2) # @sc
; AIX32-NEXT: stw 29, 116(1) # 4-byte Folded Spill
; AIX32-NEXT: lwz 29, L..C1(2) # @uc ; AIX32-NEXT: lwz 29, L..C1(2) # @uc
; AIX32-NEXT: stw 23, 92(1) # 4-byte Folded Spill ; AIX32-NEXT: stw 23, 92(1) # 4-byte Folded Spill
; AIX32-NEXT: stw 17, 68(1) # 4-byte Folded Spill ; AIX32-NEXT: stw 17, 68(1) # 4-byte Folded Spill
; AIX32-NEXT: stw 18, 72(1) # 4-byte Folded Spill ; AIX32-NEXT: stw 18, 72(1) # 4-byte Folded Spill
; AIX32-NEXT: stw 19, 76(1) # 4-byte Folded Spill
; AIX32-NEXT: lbz 3, 0(28) ; AIX32-NEXT: lbz 3, 0(28)
; AIX32-NEXT: rlwinm 4, 28, 3, 27, 28 ; AIX32-NEXT: rlwinm 4, 28, 3, 27, 28
; AIX32-NEXT: stw 19, 76(1) # 4-byte Folded Spill
; AIX32-NEXT: lbz 5, 0(29) ; AIX32-NEXT: lbz 5, 0(29)
; AIX32-NEXT: rlwinm 19, 28, 0, 0, 29
; AIX32-NEXT: xori 23, 4, 24 ; AIX32-NEXT: xori 23, 4, 24
; AIX32-NEXT: li 4, 255 ; AIX32-NEXT: li 4, 255
; AIX32-NEXT: slw 6, 3, 23 ; AIX32-NEXT: slw 6, 3, 23
; AIX32-NEXT: slw 5, 5, 23
; AIX32-NEXT: slw 3, 4, 23 ; AIX32-NEXT: slw 3, 4, 23
; AIX32-NEXT: slw 5, 5, 23
; AIX32-NEXT: stw 20, 80(1) # 4-byte Folded Spill ; AIX32-NEXT: stw 20, 80(1) # 4-byte Folded Spill
; AIX32-NEXT: and 4, 6, 3
; AIX32-NEXT: stw 21, 84(1) # 4-byte Folded Spill ; AIX32-NEXT: stw 21, 84(1) # 4-byte Folded Spill
; AIX32-NEXT: stw 22, 88(1) # 4-byte Folded Spill ; AIX32-NEXT: stw 22, 88(1) # 4-byte Folded Spill
; AIX32-NEXT: stw 24, 96(1) # 4-byte Folded Spill ; AIX32-NEXT: stw 24, 96(1) # 4-byte Folded Spill
; AIX32-NEXT: stw 25, 100(1) # 4-byte Folded Spill ; AIX32-NEXT: stw 25, 100(1) # 4-byte Folded Spill
; AIX32-NEXT: stw 26, 104(1) # 4-byte Folded Spill ; AIX32-NEXT: stw 26, 104(1) # 4-byte Folded Spill
; AIX32-NEXT: stw 27, 108(1) # 4-byte Folded Spill ; AIX32-NEXT: stw 27, 108(1) # 4-byte Folded Spill
; AIX32-NEXT: stw 30, 120(1) # 4-byte Folded Spill ; AIX32-NEXT: stw 30, 120(1) # 4-byte Folded Spill
; AIX32-NEXT: stw 31, 124(1) # 4-byte Folded Spill ; AIX32-NEXT: stw 31, 124(1) # 4-byte Folded Spill
; AIX32-NEXT: and 4, 6, 3 ; AIX32-NEXT: rlwinm 19, 28, 0, 0, 29
; AIX32-NEXT: and 5, 5, 3 ; AIX32-NEXT: and 5, 5, 3
; AIX32-NEXT: sync ; AIX32-NEXT: sync
; AIX32-NEXT: L..BB3_1: # %entry ; AIX32-NEXT: L..BB3_1: # %entry
; AIX32-NEXT: # ; AIX32-NEXT: #
; AIX32-NEXT: lwarx 7, 0, 19 ; AIX32-NEXT: lwarx 7, 0, 19
; AIX32-NEXT: and 6, 7, 3 ; AIX32-NEXT: and 6, 7, 3
; AIX32-NEXT: cmpw 6, 5 ; AIX32-NEXT: cmpw 6, 5
; AIX32-NEXT: bne 0, L..BB3_3 ; AIX32-NEXT: bne 0, L..BB3_3
▲ Show 20 Lines • Show All 582 Lines • ▼ Show 20 Lines
; CHECK-NEXT: std 3, sll@toc@l(7) ; CHECK-NEXT: std 3, sll@toc@l(7)
; CHECK-NEXT: lwsync ; CHECK-NEXT: lwsync
; CHECK-NEXT: std 3, ull@toc@l(10) ; CHECK-NEXT: std 3, ull@toc@l(10)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; AIX32-LABEL: test_lock: ; AIX32-LABEL: test_lock:
; AIX32: # %bb.0: # %entry ; AIX32: # %bb.0: # %entry
; AIX32-NEXT: mflr 0 ; AIX32-NEXT: mflr 0
; AIX32-NEXT: stw 0, 8(1)
; AIX32-NEXT: stwu 1, -96(1) ; AIX32-NEXT: stwu 1, -96(1)
; AIX32-NEXT: stw 0, 104(1)
; AIX32-NEXT: stw 29, 84(1) # 4-byte Folded Spill ; AIX32-NEXT: stw 29, 84(1) # 4-byte Folded Spill
; AIX32-NEXT: lwz 29, L..C0(2) # @sc ; AIX32-NEXT: lwz 29, L..C0(2) # @sc
; AIX32-NEXT: li 3, 1 ; AIX32-NEXT: li 3, 1
; AIX32-NEXT: li 5, 255 ; AIX32-NEXT: li 5, 255
; AIX32-NEXT: stw 23, 60(1) # 4-byte Folded Spill ; AIX32-NEXT: stw 23, 60(1) # 4-byte Folded Spill
; AIX32-NEXT: stw 24, 64(1) # 4-byte Folded Spill ; AIX32-NEXT: stw 24, 64(1) # 4-byte Folded Spill
; AIX32-NEXT: stw 25, 68(1) # 4-byte Folded Spill
; AIX32-NEXT: stw 26, 72(1) # 4-byte Folded Spill
; AIX32-NEXT: rlwinm 4, 29, 3, 27, 28 ; AIX32-NEXT: rlwinm 4, 29, 3, 27, 28
; AIX32-NEXT: stw 27, 76(1) # 4-byte Folded Spill ; AIX32-NEXT: stw 25, 68(1) # 4-byte Folded Spill
; AIX32-NEXT: xori 4, 4, 24 ; AIX32-NEXT: xori 4, 4, 24
; AIX32-NEXT: stw 28, 80(1) # 4-byte Folded Spill ; AIX32-NEXT: stw 26, 72(1) # 4-byte Folded Spill
; AIX32-NEXT: slw 8, 3, 4 ; AIX32-NEXT: slw 8, 3, 4
; AIX32-NEXT: slw 6, 5, 4 ; AIX32-NEXT: slw 6, 5, 4
; AIX32-NEXT: stw 27, 76(1) # 4-byte Folded Spill
; AIX32-NEXT: stw 28, 80(1) # 4-byte Folded Spill
; AIX32-NEXT: stw 30, 88(1) # 4-byte Folded Spill ; AIX32-NEXT: stw 30, 88(1) # 4-byte Folded Spill
; AIX32-NEXT: stw 31, 92(1) # 4-byte Folded Spill ; AIX32-NEXT: stw 31, 92(1) # 4-byte Folded Spill
; AIX32-NEXT: rlwinm 7, 29, 0, 0, 29 ; AIX32-NEXT: rlwinm 7, 29, 0, 0, 29
; AIX32-NEXT: and 8, 8, 6 ; AIX32-NEXT: and 8, 8, 6
; AIX32-NEXT: sync ; AIX32-NEXT: sync
; AIX32-NEXT: L..BB4_1: # %entry ; AIX32-NEXT: L..BB4_1: # %entry
; AIX32-NEXT: # ; AIX32-NEXT: #
; AIX32-NEXT: lwarx 5, 0, 7 ; AIX32-NEXT: lwarx 5, 0, 7
▲ Show 20 Lines • Show All 320 Lines • ▼ Show 20 Lines
; CHECK-NEXT: li 3, 66 ; CHECK-NEXT: li 3, 66
; CHECK-NEXT: li 4, 55 ; CHECK-NEXT: li 4, 55
; CHECK-NEXT: isel 3, 4, 3, 6 ; CHECK-NEXT: isel 3, 4, 3, 6
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; AIX32-LABEL: cmpswplp: ; AIX32-LABEL: cmpswplp:
; AIX32: # %bb.0: # %entry ; AIX32: # %bb.0: # %entry
; AIX32-NEXT: mflr 0 ; AIX32-NEXT: mflr 0
; AIX32-NEXT: stw 0, 8(1)
; AIX32-NEXT: stwu 1, -64(1) ; AIX32-NEXT: stwu 1, -64(1)
; AIX32-NEXT: addic 7, 6, 1 ; AIX32-NEXT: addic 7, 6, 1
; AIX32-NEXT: stw 6, 60(1) ; AIX32-NEXT: stw 0, 72(1)
; AIX32-NEXT: addi 4, 1, 56 ; AIX32-NEXT: addi 4, 1, 56
; AIX32-NEXT: addze 8, 5 ; AIX32-NEXT: addze 8, 5
; AIX32-NEXT: stw 5, 56(1) ; AIX32-NEXT: stw 6, 60(1)
; AIX32-NEXT: mr 6, 7 ; AIX32-NEXT: mr 6, 7
; AIX32-NEXT: stw 5, 56(1)
; AIX32-NEXT: mr 5, 8 ; AIX32-NEXT: mr 5, 8
; AIX32-NEXT: li 7, 0 ; AIX32-NEXT: li 7, 0
; AIX32-NEXT: li 8, 0 ; AIX32-NEXT: li 8, 0
; AIX32-NEXT: bl .__atomic_compare_exchange_8[PR] ; AIX32-NEXT: bl .__atomic_compare_exchange_8[PR]
; AIX32-NEXT: nop ; AIX32-NEXT: nop
; AIX32-NEXT: andi. 3, 3, 1 ; AIX32-NEXT: andi. 3, 3, 1
; AIX32-NEXT: li 4, 55 ; AIX32-NEXT: li 4, 55
; AIX32-NEXT: li 3, 66 ; AIX32-NEXT: li 3, 66
Show All 29 Lines
; CHECK-NEXT: li 4, 66 ; CHECK-NEXT: li 4, 66
; CHECK-NEXT: lwsync ; CHECK-NEXT: lwsync
; CHECK-NEXT: isel 3, 4, 3, 5 ; CHECK-NEXT: isel 3, 4, 3, 5
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; AIX32-LABEL: atommax8: ; AIX32-LABEL: atommax8:
; AIX32: # %bb.0: # %entry ; AIX32: # %bb.0: # %entry
; AIX32-NEXT: mflr 0 ; AIX32-NEXT: mflr 0
; AIX32-NEXT: stw 0, 8(1)
; AIX32-NEXT: stwu 1, -80(1) ; AIX32-NEXT: stwu 1, -80(1)
; AIX32-NEXT: stw 0, 88(1)
; AIX32-NEXT: stw 28, 64(1) # 4-byte Folded Spill
; AIX32-NEXT: lwz 9, 4(3) ; AIX32-NEXT: lwz 9, 4(3)
; AIX32-NEXT: lwz 10, 0(3) ; AIX32-NEXT: lwz 10, 0(3)
; AIX32-NEXT: stw 28, 64(1) # 4-byte Folded Spill ; AIX32-NEXT: addi 28, 1, 56
; AIX32-NEXT: stw 29, 68(1) # 4-byte Folded Spill ; AIX32-NEXT: stw 29, 68(1) # 4-byte Folded Spill
; AIX32-NEXT: stw 30, 72(1) # 4-byte Folded Spill ; AIX32-NEXT: stw 30, 72(1) # 4-byte Folded Spill
; AIX32-NEXT: stw 31, 76(1) # 4-byte Folded Spill ; AIX32-NEXT: stw 31, 76(1) # 4-byte Folded Spill
; AIX32-NEXT: mr 31, 5 ; AIX32-NEXT: mr 31, 5
; AIX32-NEXT: mr 29, 3 ; AIX32-NEXT: mr 29, 3
; AIX32-NEXT: mr 30, 4 ; AIX32-NEXT: mr 30, 4
; AIX32-NEXT: addi 28, 1, 56
; AIX32-NEXT: .align 4 ; AIX32-NEXT: .align 4
; AIX32-NEXT: L..BB7_1: # %atomicrmw.start ; AIX32-NEXT: L..BB7_1: # %atomicrmw.start
; AIX32-NEXT: # ; AIX32-NEXT: #
; AIX32-NEXT: cmplw 10, 30 ; AIX32-NEXT: cmplw 10, 30
; AIX32-NEXT: cmpw 1, 10, 30 ; AIX32-NEXT: cmpw 1, 10, 30
; AIX32-NEXT: mr 3, 29 ; AIX32-NEXT: mr 3, 29
; AIX32-NEXT: mr 4, 28 ; AIX32-NEXT: mr 4, 28
; AIX32-NEXT: crandc 20, 5, 2 ; AIX32-NEXT: crandc 20, 5, 2
▲ Show 20 Lines • Show All 206 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/alloca-crspill.ll

Show First 20 Lines • Show All 79 Lines • ▼ Show 20 Lines
; CHECK64: bb.0.entry: ; CHECK64: bb.0.entry:
; CHECK64-NEXT: liveins: $x3, $cr2 ; CHECK64-NEXT: liveins: $x3, $cr2
; Prologue: ; Prologue:
; CHECK64: $x0 = MFLR8 implicit $lr8 ; CHECK64: $x0 = MFLR8 implicit $lr8
; ELFV2-NEXT: $x12 = MFOCRF8 killed $cr2 ; ELFV2-NEXT: $x12 = MFOCRF8 killed $cr2
; V1ANDAIX-NEXT: $x12 = MFCR8 implicit killed $cr2 ; V1ANDAIX-NEXT: $x12 = MFCR8 implicit killed $cr2
; CHECK64-DAG: STD $x31, -8, $x1 ; CHECK64-DAG: STD $x31, -8, $x1
; CHECK64-DAG: STD killed $x0, 16, $x1
; CHECK64-DAG: STW8 killed $x12, 8, $x1 ; CHECK64-DAG: STW8 killed $x12, 8, $x1
; ELFV2-NEXT: $x1 = STDU $x1, -48, $x1 ; ELFV2-NEXT: $x1 = STDU $x1, -48, $x1
; ELFV2-NEXT: STD killed $x0, 64, $x1
; V1ANDAIX-NEXT: x1 = STDU $x1, -128, $x1 ; V1ANDAIX-NEXT: x1 = STDU $x1, -128, $x1
; V1ANDAIX-NEXT: STD killed $x0, 144, $x1
; CHECK64: $x31 = OR8 $x1, $x1 ; CHECK64: $x31 = OR8 $x1, $x1
; ELFV2: $[[ORIGSP:x[0-9]+]] = ADDI8 $x31, 48 ; ELFV2: $[[ORIGSP:x[0-9]+]] = ADDI8 $x31, 48
; V1ANDAIX: $[[ORIGSP:x[0-9]+]] = ADDI8 $x31, 128 ; V1ANDAIX: $[[ORIGSP:x[0-9]+]] = ADDI8 $x31, 128
; CHECK64: $x1 = STDUX killed $[[ORIGSP]], $x1, killed $x{{[0-9]}} ; CHECK64: $x1 = STDUX killed $[[ORIGSP]], $x1, killed $x{{[0-9]}}
; CHECK64: INLINEASM {{.*}} early-clobber $cr2 ; CHECK64: INLINEASM {{.*}} early-clobber $cr2
; CHECK64: BL8_NOP ; CHECK64: BL8_NOP
Show All 10 Lines
; CHECK32: bb.0.entry: ; CHECK32: bb.0.entry:
; CHECK32-NEXT: liveins: $r3, $cr2 ; CHECK32-NEXT: liveins: $r3, $cr2
; Prologue: ; Prologue:
; CHECK32: $r0 = MFLR implicit $lr ; CHECK32: $r0 = MFLR implicit $lr
; CHECK32-NEXT: $r12 = MFCR implicit killed $cr2 ; CHECK32-NEXT: $r12 = MFCR implicit killed $cr2
; CHECK32-DAG: STW $r31, -4, $r1 ; CHECK32-DAG: STW $r31, -4, $r1
; CHECK32-DAG: STW killed $r0, 8, $r1
; CHECK32-DAG: STW killed $r12, 4, $r1 ; CHECK32-DAG: STW killed $r12, 4, $r1
; CHECK32: $r1 = STWU $r1, -80, $r1 ; CHECK32: $r1 = STWU $r1, -80, $r1
; CHECK32-NEXT: STW killed $r0, 88, $r1
; CHECK32: $r31 = OR $r1, $r1 ; CHECK32: $r31 = OR $r1, $r1
; CHECK32: $[[ORIGSP:r[0-9]+]] = ADDI $r31, 80 ; CHECK32: $[[ORIGSP:r[0-9]+]] = ADDI $r31, 80
; CHECK32: $r1 = STWUX killed $[[ORIGSP]], $r1, killed $r{{[0-9]}} ; CHECK32: $r1 = STWUX killed $[[ORIGSP]], $r1, killed $r{{[0-9]}}
; CHECK32: INLINEASM {{.*}} early-clobber $cr2 ; CHECK32: INLINEASM {{.*}} early-clobber $cr2
; CHECK32: BL_NOP ; CHECK32: BL_NOP
; Epilogue: ; Epilogue:
; CHECK32: $r1 = LWZ 0, $r1 ; CHECK32: $r1 = LWZ 0, $r1
; CHECK32-DAG: $r0 = LWZ 8, $r1 ; CHECK32-DAG: $r0 = LWZ 8, $r1
; CHECK32-DAG: $r12 = LWZ 4, $r1 ; CHECK32-DAG: $r12 = LWZ 4, $r1
; CHECK32-DAG: $r31 = LWZ -4, $r1 ; CHECK32-DAG: $r31 = LWZ -4, $r1
; CHECK32: $cr2 = MTOCRF killed $r12 ; CHECK32: $cr2 = MTOCRF killed $r12
; CHECK32-NEXT: MTLR $r0, implicit-def $lr ; CHECK32-NEXT: MTLR $r0, implicit-def $lr
; CHECK32-NEXT: BLR implicit $lr, implicit $rm, implicit $r3 ; CHECK32-NEXT: BLR implicit $lr, implicit $rm, implicit $r3

llvm/test/CodeGen/PowerPC/atomics-i128-ldst.ll

Show All 23 Lines
; P8-NEXT: lq r4, 0(r3) ; P8-NEXT: lq r4, 0(r3)
; P8-NEXT: mr r3, r4 ; P8-NEXT: mr r3, r4
; P8-NEXT: mr r4, r5 ; P8-NEXT: mr r4, r5
; P8-NEXT: blr ; P8-NEXT: blr
; ;
; PWR7-LABEL: lq_unordered: ; PWR7-LABEL: lq_unordered:
; PWR7: # %bb.0: # %entry ; PWR7: # %bb.0: # %entry
; PWR7-NEXT: mflr r0 ; PWR7-NEXT: mflr r0
; PWR7-NEXT: std r0, 16(r1)
; PWR7-NEXT: stdu r1, -112(r1) ; PWR7-NEXT: stdu r1, -112(r1)
; PWR7-NEXT: std r0, 128(r1)
; PWR7-NEXT: .cfi_def_cfa_offset 112 ; PWR7-NEXT: .cfi_def_cfa_offset 112
; PWR7-NEXT: .cfi_offset lr, 16 ; PWR7-NEXT: .cfi_offset lr, 16
; PWR7-NEXT: li r4, 0 ; PWR7-NEXT: li r4, 0
; PWR7-NEXT: bl __atomic_load_16 ; PWR7-NEXT: bl __atomic_load_16
; PWR7-NEXT: nop ; PWR7-NEXT: nop
; PWR7-NEXT: addi r1, r1, 112 ; PWR7-NEXT: addi r1, r1, 112
; PWR7-NEXT: ld r0, 16(r1) ; PWR7-NEXT: ld r0, 16(r1)
; PWR7-NEXT: mtlr r0 ; PWR7-NEXT: mtlr r0
; PWR7-NEXT: blr ; PWR7-NEXT: blr
; ;
; LE-PWR8-LABEL: lq_unordered: ; LE-PWR8-LABEL: lq_unordered:
; LE-PWR8: # %bb.0: # %entry ; LE-PWR8: # %bb.0: # %entry
; LE-PWR8-NEXT: lq r4, 0(r3) ; LE-PWR8-NEXT: lq r4, 0(r3)
; LE-PWR8-NEXT: mr r3, r5 ; LE-PWR8-NEXT: mr r3, r5
; LE-PWR8-NEXT: blr ; LE-PWR8-NEXT: blr
; ;
; AIX64-PWR8-LABEL: lq_unordered: ; AIX64-PWR8-LABEL: lq_unordered:
; AIX64-PWR8: # %bb.0: # %entry ; AIX64-PWR8: # %bb.0: # %entry
; AIX64-PWR8-NEXT: mflr r0 ; AIX64-PWR8-NEXT: mflr r0
; AIX64-PWR8-NEXT: std r0, 16(r1)
; AIX64-PWR8-NEXT: stdu r1, -112(r1) ; AIX64-PWR8-NEXT: stdu r1, -112(r1)
; AIX64-PWR8-NEXT: li r4, 0 ; AIX64-PWR8-NEXT: li r4, 0
; AIX64-PWR8-NEXT: std r0, 128(r1)
; AIX64-PWR8-NEXT: bl .__atomic_load_16[PR] ; AIX64-PWR8-NEXT: bl .__atomic_load_16[PR]
; AIX64-PWR8-NEXT: nop ; AIX64-PWR8-NEXT: nop
; AIX64-PWR8-NEXT: addi r1, r1, 112 ; AIX64-PWR8-NEXT: addi r1, r1, 112
; AIX64-PWR8-NEXT: ld r0, 16(r1) ; AIX64-PWR8-NEXT: ld r0, 16(r1)
; AIX64-PWR8-NEXT: mtlr r0 ; AIX64-PWR8-NEXT: mtlr r0
; AIX64-PWR8-NEXT: blr ; AIX64-PWR8-NEXT: blr
; ;
; PPC-PWR8-LABEL: lq_unordered: ; PPC-PWR8-LABEL: lq_unordered:
; PPC-PWR8: # %bb.0: # %entry ; PPC-PWR8: # %bb.0: # %entry
; PPC-PWR8-NEXT: mflr r0 ; PPC-PWR8-NEXT: mflr r0
; PPC-PWR8-NEXT: stw r0, 4(r1)
; PPC-PWR8-NEXT: stwu r1, -32(r1) ; PPC-PWR8-NEXT: stwu r1, -32(r1)
; PPC-PWR8-NEXT: stw r0, 36(r1)
; PPC-PWR8-NEXT: .cfi_def_cfa_offset 32 ; PPC-PWR8-NEXT: .cfi_def_cfa_offset 32
; PPC-PWR8-NEXT: .cfi_offset lr, 4 ; PPC-PWR8-NEXT: .cfi_offset lr, 4
; PPC-PWR8-NEXT: mr r4, r3 ; PPC-PWR8-NEXT: mr r4, r3
; PPC-PWR8-NEXT: addi r5, r1, 16 ; PPC-PWR8-NEXT: addi r5, r1, 16
; PPC-PWR8-NEXT: li r3, 16 ; PPC-PWR8-NEXT: li r3, 16
; PPC-PWR8-NEXT: li r6, 0 ; PPC-PWR8-NEXT: li r6, 0
; PPC-PWR8-NEXT: bl __atomic_load ; PPC-PWR8-NEXT: bl __atomic_load
; PPC-PWR8-NEXT: lwz r6, 28(r1) ; PPC-PWR8-NEXT: lwz r6, 28(r1)
Show All 17 Lines
; P8-NEXT: lq r4, 0(r3) ; P8-NEXT: lq r4, 0(r3)
; P8-NEXT: mr r3, r4 ; P8-NEXT: mr r3, r4
; P8-NEXT: mr r4, r5 ; P8-NEXT: mr r4, r5
; P8-NEXT: blr ; P8-NEXT: blr
; ;
; PWR7-LABEL: lqx_unordered: ; PWR7-LABEL: lqx_unordered:
; PWR7: # %bb.0: # %entry ; PWR7: # %bb.0: # %entry
; PWR7-NEXT: mflr r0 ; PWR7-NEXT: mflr r0
; PWR7-NEXT: std r0, 16(r1)
; PWR7-NEXT: stdu r1, -112(r1) ; PWR7-NEXT: stdu r1, -112(r1)
; PWR7-NEXT: std r0, 128(r1)
; PWR7-NEXT: .cfi_def_cfa_offset 112 ; PWR7-NEXT: .cfi_def_cfa_offset 112
; PWR7-NEXT: .cfi_offset lr, 16 ; PWR7-NEXT: .cfi_offset lr, 16
; PWR7-NEXT: sldi r4, r4, 4 ; PWR7-NEXT: sldi r4, r4, 4
; PWR7-NEXT: add r3, r3, r4 ; PWR7-NEXT: add r3, r3, r4
; PWR7-NEXT: li r4, 0 ; PWR7-NEXT: li r4, 0
; PWR7-NEXT: bl __atomic_load_16 ; PWR7-NEXT: bl __atomic_load_16
; PWR7-NEXT: nop ; PWR7-NEXT: nop
; PWR7-NEXT: addi r1, r1, 112 ; PWR7-NEXT: addi r1, r1, 112
Show All 9 Lines
; LE-PWR8-NEXT: lq r2, 0(r4) ; LE-PWR8-NEXT: lq r2, 0(r4)
; LE-PWR8-NEXT: mr r4, r2 ; LE-PWR8-NEXT: mr r4, r2
; LE-PWR8-NEXT: ld r2, -8(r1) # 8-byte Folded Reload ; LE-PWR8-NEXT: ld r2, -8(r1) # 8-byte Folded Reload
; LE-PWR8-NEXT: blr ; LE-PWR8-NEXT: blr
; ;
; AIX64-PWR8-LABEL: lqx_unordered: ; AIX64-PWR8-LABEL: lqx_unordered:
; AIX64-PWR8: # %bb.0: # %entry ; AIX64-PWR8: # %bb.0: # %entry
; AIX64-PWR8-NEXT: mflr r0 ; AIX64-PWR8-NEXT: mflr r0
; AIX64-PWR8-NEXT: std r0, 16(r1)
; AIX64-PWR8-NEXT: stdu r1, -112(r1) ; AIX64-PWR8-NEXT: stdu r1, -112(r1)
; AIX64-PWR8-NEXT: sldi r4, r4, 4 ; AIX64-PWR8-NEXT: sldi r4, r4, 4
; AIX64-PWR8-NEXT: std r0, 128(r1)
; AIX64-PWR8-NEXT: add r3, r3, r4 ; AIX64-PWR8-NEXT: add r3, r3, r4
; AIX64-PWR8-NEXT: li r4, 0 ; AIX64-PWR8-NEXT: li r4, 0
; AIX64-PWR8-NEXT: bl .__atomic_load_16[PR] ; AIX64-PWR8-NEXT: bl .__atomic_load_16[PR]
; AIX64-PWR8-NEXT: nop ; AIX64-PWR8-NEXT: nop
; AIX64-PWR8-NEXT: addi r1, r1, 112 ; AIX64-PWR8-NEXT: addi r1, r1, 112
; AIX64-PWR8-NEXT: ld r0, 16(r1) ; AIX64-PWR8-NEXT: ld r0, 16(r1)
; AIX64-PWR8-NEXT: mtlr r0 ; AIX64-PWR8-NEXT: mtlr r0
; AIX64-PWR8-NEXT: blr ; AIX64-PWR8-NEXT: blr
; ;
; PPC-PWR8-LABEL: lqx_unordered: ; PPC-PWR8-LABEL: lqx_unordered:
; PPC-PWR8: # %bb.0: # %entry ; PPC-PWR8: # %bb.0: # %entry
; PPC-PWR8-NEXT: mflr r0 ; PPC-PWR8-NEXT: mflr r0
; PPC-PWR8-NEXT: stw r0, 4(r1)
; PPC-PWR8-NEXT: stwu r1, -32(r1) ; PPC-PWR8-NEXT: stwu r1, -32(r1)
; PPC-PWR8-NEXT: stw r0, 36(r1)
; PPC-PWR8-NEXT: .cfi_def_cfa_offset 32 ; PPC-PWR8-NEXT: .cfi_def_cfa_offset 32
; PPC-PWR8-NEXT: .cfi_offset lr, 4 ; PPC-PWR8-NEXT: .cfi_offset lr, 4
; PPC-PWR8-NEXT: slwi r4, r6, 4 ; PPC-PWR8-NEXT: slwi r4, r6, 4
; PPC-PWR8-NEXT: addi r5, r1, 16 ; PPC-PWR8-NEXT: addi r5, r1, 16
; PPC-PWR8-NEXT: li r6, 0 ; PPC-PWR8-NEXT: li r6, 0
; PPC-PWR8-NEXT: add r4, r3, r4 ; PPC-PWR8-NEXT: add r4, r3, r4
; PPC-PWR8-NEXT: li r3, 16 ; PPC-PWR8-NEXT: li r3, 16
; PPC-PWR8-NEXT: bl __atomic_load ; PPC-PWR8-NEXT: bl __atomic_load
Show All 19 Lines
; P8-NEXT: lq r4, 0(r3) ; P8-NEXT: lq r4, 0(r3)
; P8-NEXT: mr r3, r4 ; P8-NEXT: mr r3, r4
; P8-NEXT: mr r4, r5 ; P8-NEXT: mr r4, r5
; P8-NEXT: blr ; P8-NEXT: blr
; ;
; PWR7-LABEL: lq_big_offset_unordered: ; PWR7-LABEL: lq_big_offset_unordered:
; PWR7: # %bb.0: # %entry ; PWR7: # %bb.0: # %entry
; PWR7-NEXT: mflr r0 ; PWR7-NEXT: mflr r0
; PWR7-NEXT: std r0, 16(r1)
; PWR7-NEXT: stdu r1, -112(r1) ; PWR7-NEXT: stdu r1, -112(r1)
; PWR7-NEXT: std r0, 128(r1)
; PWR7-NEXT: .cfi_def_cfa_offset 112 ; PWR7-NEXT: .cfi_def_cfa_offset 112
; PWR7-NEXT: .cfi_offset lr, 16 ; PWR7-NEXT: .cfi_offset lr, 16
; PWR7-NEXT: addis r3, r3, 32 ; PWR7-NEXT: addis r3, r3, 32
; PWR7-NEXT: li r4, 0 ; PWR7-NEXT: li r4, 0
; PWR7-NEXT: bl __atomic_load_16 ; PWR7-NEXT: bl __atomic_load_16
; PWR7-NEXT: nop ; PWR7-NEXT: nop
; PWR7-NEXT: addi r1, r1, 112 ; PWR7-NEXT: addi r1, r1, 112
; PWR7-NEXT: ld r0, 16(r1) ; PWR7-NEXT: ld r0, 16(r1)
; PWR7-NEXT: mtlr r0 ; PWR7-NEXT: mtlr r0
; PWR7-NEXT: blr ; PWR7-NEXT: blr
; ;
; LE-PWR8-LABEL: lq_big_offset_unordered: ; LE-PWR8-LABEL: lq_big_offset_unordered:
; LE-PWR8: # %bb.0: # %entry ; LE-PWR8: # %bb.0: # %entry
; LE-PWR8-NEXT: lis r4, 32 ; LE-PWR8-NEXT: lis r4, 32
; LE-PWR8-NEXT: std r2, -8(r1) # 8-byte Folded Spill ; LE-PWR8-NEXT: std r2, -8(r1) # 8-byte Folded Spill
; LE-PWR8-NEXT: add r4, r3, r4 ; LE-PWR8-NEXT: add r4, r3, r4
; LE-PWR8-NEXT: lq r2, 0(r4) ; LE-PWR8-NEXT: lq r2, 0(r4)
; LE-PWR8-NEXT: mr r4, r2 ; LE-PWR8-NEXT: mr r4, r2
; LE-PWR8-NEXT: ld r2, -8(r1) # 8-byte Folded Reload ; LE-PWR8-NEXT: ld r2, -8(r1) # 8-byte Folded Reload
; LE-PWR8-NEXT: blr ; LE-PWR8-NEXT: blr
; ;
; AIX64-PWR8-LABEL: lq_big_offset_unordered: ; AIX64-PWR8-LABEL: lq_big_offset_unordered:
; AIX64-PWR8: # %bb.0: # %entry ; AIX64-PWR8: # %bb.0: # %entry
; AIX64-PWR8-NEXT: mflr r0 ; AIX64-PWR8-NEXT: mflr r0
; AIX64-PWR8-NEXT: std r0, 16(r1)
; AIX64-PWR8-NEXT: stdu r1, -112(r1) ; AIX64-PWR8-NEXT: stdu r1, -112(r1)
; AIX64-PWR8-NEXT: addis r3, r3, 32 ; AIX64-PWR8-NEXT: addis r3, r3, 32
; AIX64-PWR8-NEXT: li r4, 0 ; AIX64-PWR8-NEXT: li r4, 0
; AIX64-PWR8-NEXT: std r0, 128(r1)
; AIX64-PWR8-NEXT: bl .__atomic_load_16[PR] ; AIX64-PWR8-NEXT: bl .__atomic_load_16[PR]
; AIX64-PWR8-NEXT: nop ; AIX64-PWR8-NEXT: nop
; AIX64-PWR8-NEXT: addi r1, r1, 112 ; AIX64-PWR8-NEXT: addi r1, r1, 112
; AIX64-PWR8-NEXT: ld r0, 16(r1) ; AIX64-PWR8-NEXT: ld r0, 16(r1)
; AIX64-PWR8-NEXT: mtlr r0 ; AIX64-PWR8-NEXT: mtlr r0
; AIX64-PWR8-NEXT: blr ; AIX64-PWR8-NEXT: blr
; ;
; PPC-PWR8-LABEL: lq_big_offset_unordered: ; PPC-PWR8-LABEL: lq_big_offset_unordered:
; PPC-PWR8: # %bb.0: # %entry ; PPC-PWR8: # %bb.0: # %entry
; PPC-PWR8-NEXT: mflr r0 ; PPC-PWR8-NEXT: mflr r0
; PPC-PWR8-NEXT: stw r0, 4(r1)
; PPC-PWR8-NEXT: stwu r1, -32(r1) ; PPC-PWR8-NEXT: stwu r1, -32(r1)
; PPC-PWR8-NEXT: stw r0, 36(r1)
; PPC-PWR8-NEXT: .cfi_def_cfa_offset 32 ; PPC-PWR8-NEXT: .cfi_def_cfa_offset 32
; PPC-PWR8-NEXT: .cfi_offset lr, 4 ; PPC-PWR8-NEXT: .cfi_offset lr, 4
; PPC-PWR8-NEXT: addis r4, r3, 32 ; PPC-PWR8-NEXT: addis r4, r3, 32
; PPC-PWR8-NEXT: addi r5, r1, 16 ; PPC-PWR8-NEXT: addi r5, r1, 16
; PPC-PWR8-NEXT: li r3, 16 ; PPC-PWR8-NEXT: li r3, 16
; PPC-PWR8-NEXT: li r6, 0 ; PPC-PWR8-NEXT: li r6, 0
; PPC-PWR8-NEXT: bl __atomic_load ; PPC-PWR8-NEXT: bl __atomic_load
; PPC-PWR8-NEXT: lwz r6, 28(r1) ; PPC-PWR8-NEXT: lwz r6, 28(r1)
Show All 16 Lines
; P8-NEXT: lq r4, 0(r3) ; P8-NEXT: lq r4, 0(r3)
; P8-NEXT: mr r3, r4 ; P8-NEXT: mr r3, r4
; P8-NEXT: mr r4, r5 ; P8-NEXT: mr r4, r5
; P8-NEXT: blr ; P8-NEXT: blr
; ;
; PWR7-LABEL: lq_monotonic: ; PWR7-LABEL: lq_monotonic:
; PWR7: # %bb.0: # %entry ; PWR7: # %bb.0: # %entry
; PWR7-NEXT: mflr r0 ; PWR7-NEXT: mflr r0
; PWR7-NEXT: std r0, 16(r1)
; PWR7-NEXT: stdu r1, -112(r1) ; PWR7-NEXT: stdu r1, -112(r1)
; PWR7-NEXT: std r0, 128(r1)
; PWR7-NEXT: .cfi_def_cfa_offset 112 ; PWR7-NEXT: .cfi_def_cfa_offset 112
; PWR7-NEXT: .cfi_offset lr, 16 ; PWR7-NEXT: .cfi_offset lr, 16
; PWR7-NEXT: li r4, 0 ; PWR7-NEXT: li r4, 0
; PWR7-NEXT: bl __atomic_load_16 ; PWR7-NEXT: bl __atomic_load_16
; PWR7-NEXT: nop ; PWR7-NEXT: nop
; PWR7-NEXT: addi r1, r1, 112 ; PWR7-NEXT: addi r1, r1, 112
; PWR7-NEXT: ld r0, 16(r1) ; PWR7-NEXT: ld r0, 16(r1)
; PWR7-NEXT: mtlr r0 ; PWR7-NEXT: mtlr r0
; PWR7-NEXT: blr ; PWR7-NEXT: blr
; ;
; LE-PWR8-LABEL: lq_monotonic: ; LE-PWR8-LABEL: lq_monotonic:
; LE-PWR8: # %bb.0: # %entry ; LE-PWR8: # %bb.0: # %entry
; LE-PWR8-NEXT: lq r4, 0(r3) ; LE-PWR8-NEXT: lq r4, 0(r3)
; LE-PWR8-NEXT: mr r3, r5 ; LE-PWR8-NEXT: mr r3, r5
; LE-PWR8-NEXT: blr ; LE-PWR8-NEXT: blr
; ;
; AIX64-PWR8-LABEL: lq_monotonic: ; AIX64-PWR8-LABEL: lq_monotonic:
; AIX64-PWR8: # %bb.0: # %entry ; AIX64-PWR8: # %bb.0: # %entry
; AIX64-PWR8-NEXT: mflr r0 ; AIX64-PWR8-NEXT: mflr r0
; AIX64-PWR8-NEXT: std r0, 16(r1)
; AIX64-PWR8-NEXT: stdu r1, -112(r1) ; AIX64-PWR8-NEXT: stdu r1, -112(r1)
; AIX64-PWR8-NEXT: li r4, 0 ; AIX64-PWR8-NEXT: li r4, 0
; AIX64-PWR8-NEXT: std r0, 128(r1)
; AIX64-PWR8-NEXT: bl .__atomic_load_16[PR] ; AIX64-PWR8-NEXT: bl .__atomic_load_16[PR]
; AIX64-PWR8-NEXT: nop ; AIX64-PWR8-NEXT: nop
; AIX64-PWR8-NEXT: addi r1, r1, 112 ; AIX64-PWR8-NEXT: addi r1, r1, 112
; AIX64-PWR8-NEXT: ld r0, 16(r1) ; AIX64-PWR8-NEXT: ld r0, 16(r1)
; AIX64-PWR8-NEXT: mtlr r0 ; AIX64-PWR8-NEXT: mtlr r0
; AIX64-PWR8-NEXT: blr ; AIX64-PWR8-NEXT: blr
; ;
; PPC-PWR8-LABEL: lq_monotonic: ; PPC-PWR8-LABEL: lq_monotonic:
; PPC-PWR8: # %bb.0: # %entry ; PPC-PWR8: # %bb.0: # %entry
; PPC-PWR8-NEXT: mflr r0 ; PPC-PWR8-NEXT: mflr r0
; PPC-PWR8-NEXT: stw r0, 4(r1)
; PPC-PWR8-NEXT: stwu r1, -32(r1) ; PPC-PWR8-NEXT: stwu r1, -32(r1)
; PPC-PWR8-NEXT: stw r0, 36(r1)
; PPC-PWR8-NEXT: .cfi_def_cfa_offset 32 ; PPC-PWR8-NEXT: .cfi_def_cfa_offset 32
; PPC-PWR8-NEXT: .cfi_offset lr, 4 ; PPC-PWR8-NEXT: .cfi_offset lr, 4
; PPC-PWR8-NEXT: mr r4, r3 ; PPC-PWR8-NEXT: mr r4, r3
; PPC-PWR8-NEXT: addi r5, r1, 16 ; PPC-PWR8-NEXT: addi r5, r1, 16
; PPC-PWR8-NEXT: li r3, 16 ; PPC-PWR8-NEXT: li r3, 16
; PPC-PWR8-NEXT: li r6, 0 ; PPC-PWR8-NEXT: li r6, 0
; PPC-PWR8-NEXT: bl __atomic_load ; PPC-PWR8-NEXT: bl __atomic_load
; PPC-PWR8-NEXT: lwz r6, 28(r1) ; PPC-PWR8-NEXT: lwz r6, 28(r1)
Show All 18 Lines
; P8-NEXT: mr r4, r5 ; P8-NEXT: mr r4, r5
; P8-NEXT: bne- cr7, .+4 ; P8-NEXT: bne- cr7, .+4
; P8-NEXT: isync ; P8-NEXT: isync
; P8-NEXT: blr ; P8-NEXT: blr
; ;
; PWR7-LABEL: lq_acquire: ; PWR7-LABEL: lq_acquire:
; PWR7: # %bb.0: # %entry ; PWR7: # %bb.0: # %entry
; PWR7-NEXT: mflr r0 ; PWR7-NEXT: mflr r0
; PWR7-NEXT: std r0, 16(r1)
; PWR7-NEXT: stdu r1, -112(r1) ; PWR7-NEXT: stdu r1, -112(r1)
; PWR7-NEXT: std r0, 128(r1)
; PWR7-NEXT: .cfi_def_cfa_offset 112 ; PWR7-NEXT: .cfi_def_cfa_offset 112
; PWR7-NEXT: .cfi_offset lr, 16 ; PWR7-NEXT: .cfi_offset lr, 16
; PWR7-NEXT: li r4, 2 ; PWR7-NEXT: li r4, 2
; PWR7-NEXT: bl __atomic_load_16 ; PWR7-NEXT: bl __atomic_load_16
; PWR7-NEXT: nop ; PWR7-NEXT: nop
; PWR7-NEXT: addi r1, r1, 112 ; PWR7-NEXT: addi r1, r1, 112
; PWR7-NEXT: ld r0, 16(r1) ; PWR7-NEXT: ld r0, 16(r1)
; PWR7-NEXT: mtlr r0 ; PWR7-NEXT: mtlr r0
; PWR7-NEXT: blr ; PWR7-NEXT: blr
; ;
; LE-PWR8-LABEL: lq_acquire: ; LE-PWR8-LABEL: lq_acquire:
; LE-PWR8: # %bb.0: # %entry ; LE-PWR8: # %bb.0: # %entry
; LE-PWR8-NEXT: lq r4, 0(r3) ; LE-PWR8-NEXT: lq r4, 0(r3)
; LE-PWR8-NEXT: cmpd cr7, r5, r5 ; LE-PWR8-NEXT: cmpd cr7, r5, r5
; LE-PWR8-NEXT: mr r3, r5 ; LE-PWR8-NEXT: mr r3, r5
; LE-PWR8-NEXT: bne- cr7, .+4 ; LE-PWR8-NEXT: bne- cr7, .+4
; LE-PWR8-NEXT: isync ; LE-PWR8-NEXT: isync
; LE-PWR8-NEXT: blr ; LE-PWR8-NEXT: blr
; ;
; AIX64-PWR8-LABEL: lq_acquire: ; AIX64-PWR8-LABEL: lq_acquire:
; AIX64-PWR8: # %bb.0: # %entry ; AIX64-PWR8: # %bb.0: # %entry
; AIX64-PWR8-NEXT: mflr r0 ; AIX64-PWR8-NEXT: mflr r0
; AIX64-PWR8-NEXT: std r0, 16(r1)
; AIX64-PWR8-NEXT: stdu r1, -112(r1) ; AIX64-PWR8-NEXT: stdu r1, -112(r1)
; AIX64-PWR8-NEXT: li r4, 2 ; AIX64-PWR8-NEXT: li r4, 2
; AIX64-PWR8-NEXT: std r0, 128(r1)
; AIX64-PWR8-NEXT: bl .__atomic_load_16[PR] ; AIX64-PWR8-NEXT: bl .__atomic_load_16[PR]
; AIX64-PWR8-NEXT: nop ; AIX64-PWR8-NEXT: nop
; AIX64-PWR8-NEXT: addi r1, r1, 112 ; AIX64-PWR8-NEXT: addi r1, r1, 112
; AIX64-PWR8-NEXT: ld r0, 16(r1) ; AIX64-PWR8-NEXT: ld r0, 16(r1)
; AIX64-PWR8-NEXT: mtlr r0 ; AIX64-PWR8-NEXT: mtlr r0
; AIX64-PWR8-NEXT: blr ; AIX64-PWR8-NEXT: blr
; ;
; PPC-PWR8-LABEL: lq_acquire: ; PPC-PWR8-LABEL: lq_acquire:
; PPC-PWR8: # %bb.0: # %entry ; PPC-PWR8: # %bb.0: # %entry
; PPC-PWR8-NEXT: mflr r0 ; PPC-PWR8-NEXT: mflr r0
; PPC-PWR8-NEXT: stw r0, 4(r1)
; PPC-PWR8-NEXT: stwu r1, -32(r1) ; PPC-PWR8-NEXT: stwu r1, -32(r1)
; PPC-PWR8-NEXT: stw r0, 36(r1)
; PPC-PWR8-NEXT: .cfi_def_cfa_offset 32 ; PPC-PWR8-NEXT: .cfi_def_cfa_offset 32
; PPC-PWR8-NEXT: .cfi_offset lr, 4 ; PPC-PWR8-NEXT: .cfi_offset lr, 4
; PPC-PWR8-NEXT: mr r4, r3 ; PPC-PWR8-NEXT: mr r4, r3
; PPC-PWR8-NEXT: addi r5, r1, 16 ; PPC-PWR8-NEXT: addi r5, r1, 16
; PPC-PWR8-NEXT: li r3, 16 ; PPC-PWR8-NEXT: li r3, 16
; PPC-PWR8-NEXT: li r6, 2 ; PPC-PWR8-NEXT: li r6, 2
; PPC-PWR8-NEXT: bl __atomic_load ; PPC-PWR8-NEXT: bl __atomic_load
; PPC-PWR8-NEXT: lwz r6, 28(r1) ; PPC-PWR8-NEXT: lwz r6, 28(r1)
Show All 19 Lines
; P8-NEXT: mr r4, r5 ; P8-NEXT: mr r4, r5
; P8-NEXT: bne- cr7, .+4 ; P8-NEXT: bne- cr7, .+4
; P8-NEXT: isync ; P8-NEXT: isync
; P8-NEXT: blr ; P8-NEXT: blr
; ;
; PWR7-LABEL: lq_seqcst: ; PWR7-LABEL: lq_seqcst:
; PWR7: # %bb.0: # %entry ; PWR7: # %bb.0: # %entry
; PWR7-NEXT: mflr r0 ; PWR7-NEXT: mflr r0
; PWR7-NEXT: std r0, 16(r1)
; PWR7-NEXT: stdu r1, -112(r1) ; PWR7-NEXT: stdu r1, -112(r1)
; PWR7-NEXT: std r0, 128(r1)
; PWR7-NEXT: .cfi_def_cfa_offset 112 ; PWR7-NEXT: .cfi_def_cfa_offset 112
; PWR7-NEXT: .cfi_offset lr, 16 ; PWR7-NEXT: .cfi_offset lr, 16
; PWR7-NEXT: li r4, 5 ; PWR7-NEXT: li r4, 5
; PWR7-NEXT: bl __atomic_load_16 ; PWR7-NEXT: bl __atomic_load_16
; PWR7-NEXT: nop ; PWR7-NEXT: nop
; PWR7-NEXT: addi r1, r1, 112 ; PWR7-NEXT: addi r1, r1, 112
; PWR7-NEXT: ld r0, 16(r1) ; PWR7-NEXT: ld r0, 16(r1)
; PWR7-NEXT: mtlr r0 ; PWR7-NEXT: mtlr r0
; PWR7-NEXT: blr ; PWR7-NEXT: blr
; ;
; LE-PWR8-LABEL: lq_seqcst: ; LE-PWR8-LABEL: lq_seqcst:
; LE-PWR8: # %bb.0: # %entry ; LE-PWR8: # %bb.0: # %entry
; LE-PWR8-NEXT: sync ; LE-PWR8-NEXT: sync
; LE-PWR8-NEXT: lq r4, 0(r3) ; LE-PWR8-NEXT: lq r4, 0(r3)
; LE-PWR8-NEXT: cmpd cr7, r5, r5 ; LE-PWR8-NEXT: cmpd cr7, r5, r5
; LE-PWR8-NEXT: mr r3, r5 ; LE-PWR8-NEXT: mr r3, r5
; LE-PWR8-NEXT: bne- cr7, .+4 ; LE-PWR8-NEXT: bne- cr7, .+4
; LE-PWR8-NEXT: isync ; LE-PWR8-NEXT: isync
; LE-PWR8-NEXT: blr ; LE-PWR8-NEXT: blr
; ;
; AIX64-PWR8-LABEL: lq_seqcst: ; AIX64-PWR8-LABEL: lq_seqcst:
; AIX64-PWR8: # %bb.0: # %entry ; AIX64-PWR8: # %bb.0: # %entry
; AIX64-PWR8-NEXT: mflr r0 ; AIX64-PWR8-NEXT: mflr r0
; AIX64-PWR8-NEXT: std r0, 16(r1)
; AIX64-PWR8-NEXT: stdu r1, -112(r1) ; AIX64-PWR8-NEXT: stdu r1, -112(r1)
; AIX64-PWR8-NEXT: li r4, 5 ; AIX64-PWR8-NEXT: li r4, 5
; AIX64-PWR8-NEXT: std r0, 128(r1)
; AIX64-PWR8-NEXT: bl .__atomic_load_16[PR] ; AIX64-PWR8-NEXT: bl .__atomic_load_16[PR]
; AIX64-PWR8-NEXT: nop ; AIX64-PWR8-NEXT: nop
; AIX64-PWR8-NEXT: addi r1, r1, 112 ; AIX64-PWR8-NEXT: addi r1, r1, 112
; AIX64-PWR8-NEXT: ld r0, 16(r1) ; AIX64-PWR8-NEXT: ld r0, 16(r1)
; AIX64-PWR8-NEXT: mtlr r0 ; AIX64-PWR8-NEXT: mtlr r0
; AIX64-PWR8-NEXT: blr ; AIX64-PWR8-NEXT: blr
; ;
; PPC-PWR8-LABEL: lq_seqcst: ; PPC-PWR8-LABEL: lq_seqcst:
; PPC-PWR8: # %bb.0: # %entry ; PPC-PWR8: # %bb.0: # %entry
; PPC-PWR8-NEXT: mflr r0 ; PPC-PWR8-NEXT: mflr r0
; PPC-PWR8-NEXT: stw r0, 4(r1)
; PPC-PWR8-NEXT: stwu r1, -32(r1) ; PPC-PWR8-NEXT: stwu r1, -32(r1)
; PPC-PWR8-NEXT: stw r0, 36(r1)
; PPC-PWR8-NEXT: .cfi_def_cfa_offset 32 ; PPC-PWR8-NEXT: .cfi_def_cfa_offset 32
; PPC-PWR8-NEXT: .cfi_offset lr, 4 ; PPC-PWR8-NEXT: .cfi_offset lr, 4
; PPC-PWR8-NEXT: mr r4, r3 ; PPC-PWR8-NEXT: mr r4, r3
; PPC-PWR8-NEXT: addi r5, r1, 16 ; PPC-PWR8-NEXT: addi r5, r1, 16
; PPC-PWR8-NEXT: li r3, 16 ; PPC-PWR8-NEXT: li r3, 16
; PPC-PWR8-NEXT: li r6, 5 ; PPC-PWR8-NEXT: li r6, 5
; PPC-PWR8-NEXT: bl __atomic_load ; PPC-PWR8-NEXT: bl __atomic_load
; PPC-PWR8-NEXT: lwz r6, 28(r1) ; PPC-PWR8-NEXT: lwz r6, 28(r1)
Show All 15 Lines
; P8-NEXT: mr r7, r4 ; P8-NEXT: mr r7, r4
; P8-NEXT: mr r6, r3 ; P8-NEXT: mr r6, r3
; P8-NEXT: stq r6, 0(r5) ; P8-NEXT: stq r6, 0(r5)
; P8-NEXT: blr ; P8-NEXT: blr
; ;
; PWR7-LABEL: stq_unordered: ; PWR7-LABEL: stq_unordered:
; PWR7: # %bb.0: # %entry ; PWR7: # %bb.0: # %entry
; PWR7-NEXT: mflr r0 ; PWR7-NEXT: mflr r0
; PWR7-NEXT: std r0, 16(r1)
; PWR7-NEXT: stdu r1, -112(r1) ; PWR7-NEXT: stdu r1, -112(r1)
; PWR7-NEXT: std r0, 128(r1)
; PWR7-NEXT: .cfi_def_cfa_offset 112 ; PWR7-NEXT: .cfi_def_cfa_offset 112
; PWR7-NEXT: .cfi_offset lr, 16 ; PWR7-NEXT: .cfi_offset lr, 16
; PWR7-NEXT: mr r6, r4 ; PWR7-NEXT: mr r6, r4
; PWR7-NEXT: mr r4, r3 ; PWR7-NEXT: mr r4, r3
; PWR7-NEXT: mr r3, r5 ; PWR7-NEXT: mr r3, r5
; PWR7-NEXT: mr r5, r6 ; PWR7-NEXT: mr r5, r6
; PWR7-NEXT: li r6, 0 ; PWR7-NEXT: li r6, 0
; PWR7-NEXT: bl __atomic_store_16 ; PWR7-NEXT: bl __atomic_store_16
; PWR7-NEXT: nop ; PWR7-NEXT: nop
; PWR7-NEXT: addi r1, r1, 112 ; PWR7-NEXT: addi r1, r1, 112
; PWR7-NEXT: ld r0, 16(r1) ; PWR7-NEXT: ld r0, 16(r1)
; PWR7-NEXT: mtlr r0 ; PWR7-NEXT: mtlr r0
; PWR7-NEXT: blr ; PWR7-NEXT: blr
; ;
; LE-PWR8-LABEL: stq_unordered: ; LE-PWR8-LABEL: stq_unordered:
; LE-PWR8: # %bb.0: # %entry ; LE-PWR8: # %bb.0: # %entry
; LE-PWR8-NEXT: mr r7, r3 ; LE-PWR8-NEXT: mr r7, r3
; LE-PWR8-NEXT: mr r6, r4 ; LE-PWR8-NEXT: mr r6, r4
; LE-PWR8-NEXT: stq r6, 0(r5) ; LE-PWR8-NEXT: stq r6, 0(r5)
; LE-PWR8-NEXT: blr ; LE-PWR8-NEXT: blr
; ;
; AIX64-PWR8-LABEL: stq_unordered: ; AIX64-PWR8-LABEL: stq_unordered:
; AIX64-PWR8: # %bb.0: # %entry ; AIX64-PWR8: # %bb.0: # %entry
; AIX64-PWR8-NEXT: mflr r0 ; AIX64-PWR8-NEXT: mflr r0
; AIX64-PWR8-NEXT: std r0, 16(r1)
; AIX64-PWR8-NEXT: stdu r1, -112(r1) ; AIX64-PWR8-NEXT: stdu r1, -112(r1)
; AIX64-PWR8-NEXT: mr r6, r4 ; AIX64-PWR8-NEXT: mr r6, r4
; AIX64-PWR8-NEXT: mr r4, r3 ; AIX64-PWR8-NEXT: mr r4, r3
; AIX64-PWR8-NEXT: mr r3, r5 ; AIX64-PWR8-NEXT: mr r3, r5
; AIX64-PWR8-NEXT: std r0, 128(r1)
; AIX64-PWR8-NEXT: mr r5, r6 ; AIX64-PWR8-NEXT: mr r5, r6
; AIX64-PWR8-NEXT: li r6, 0 ; AIX64-PWR8-NEXT: li r6, 0
; AIX64-PWR8-NEXT: bl .__atomic_store_16[PR] ; AIX64-PWR8-NEXT: bl .__atomic_store_16[PR]
; AIX64-PWR8-NEXT: nop ; AIX64-PWR8-NEXT: nop
; AIX64-PWR8-NEXT: addi r1, r1, 112 ; AIX64-PWR8-NEXT: addi r1, r1, 112
; AIX64-PWR8-NEXT: ld r0, 16(r1) ; AIX64-PWR8-NEXT: ld r0, 16(r1)
; AIX64-PWR8-NEXT: mtlr r0 ; AIX64-PWR8-NEXT: mtlr r0
; AIX64-PWR8-NEXT: blr ; AIX64-PWR8-NEXT: blr
; ;
; PPC-PWR8-LABEL: stq_unordered: ; PPC-PWR8-LABEL: stq_unordered:
; PPC-PWR8: # %bb.0: # %entry ; PPC-PWR8: # %bb.0: # %entry
; PPC-PWR8-NEXT: mflr r0 ; PPC-PWR8-NEXT: mflr r0
; PPC-PWR8-NEXT: stw r0, 4(r1)
; PPC-PWR8-NEXT: stwu r1, -32(r1) ; PPC-PWR8-NEXT: stwu r1, -32(r1)
; PPC-PWR8-NEXT: stw r0, 36(r1)
; PPC-PWR8-NEXT: .cfi_def_cfa_offset 32 ; PPC-PWR8-NEXT: .cfi_def_cfa_offset 32
; PPC-PWR8-NEXT: .cfi_offset lr, 4 ; PPC-PWR8-NEXT: .cfi_offset lr, 4
; PPC-PWR8-NEXT: stw r6, 28(r1) ; PPC-PWR8-NEXT: stw r6, 28(r1)
; PPC-PWR8-NEXT: stw r5, 24(r1) ; PPC-PWR8-NEXT: stw r5, 24(r1)
; PPC-PWR8-NEXT: addi r5, r1, 16 ; PPC-PWR8-NEXT: addi r5, r1, 16
; PPC-PWR8-NEXT: li r6, 0 ; PPC-PWR8-NEXT: li r6, 0
; PPC-PWR8-NEXT: stw r4, 20(r1) ; PPC-PWR8-NEXT: stw r4, 20(r1)
; PPC-PWR8-NEXT: stw r3, 16(r1) ; PPC-PWR8-NEXT: stw r3, 16(r1)
Show All 17 Lines
; P8-NEXT: mr r8, r3 ; P8-NEXT: mr r8, r3
; P8-NEXT: add r3, r5, r6 ; P8-NEXT: add r3, r5, r6
; P8-NEXT: stq r8, 0(r3) ; P8-NEXT: stq r8, 0(r3)
; P8-NEXT: blr ; P8-NEXT: blr
; ;
; PWR7-LABEL: stqx_unordered: ; PWR7-LABEL: stqx_unordered:
; PWR7: # %bb.0: # %entry ; PWR7: # %bb.0: # %entry
; PWR7-NEXT: mflr r0 ; PWR7-NEXT: mflr r0
; PWR7-NEXT: std r0, 16(r1)
; PWR7-NEXT: stdu r1, -112(r1) ; PWR7-NEXT: stdu r1, -112(r1)
; PWR7-NEXT: std r0, 128(r1)
; PWR7-NEXT: .cfi_def_cfa_offset 112 ; PWR7-NEXT: .cfi_def_cfa_offset 112
; PWR7-NEXT: .cfi_offset lr, 16 ; PWR7-NEXT: .cfi_offset lr, 16
; PWR7-NEXT: mr r7, r4 ; PWR7-NEXT: mr r7, r4
; PWR7-NEXT: mr r4, r3 ; PWR7-NEXT: mr r4, r3
; PWR7-NEXT: sldi r3, r6, 4 ; PWR7-NEXT: sldi r3, r6, 4
; PWR7-NEXT: li r6, 0 ; PWR7-NEXT: li r6, 0
; PWR7-NEXT: add r3, r5, r3 ; PWR7-NEXT: add r3, r5, r3
; PWR7-NEXT: mr r5, r7 ; PWR7-NEXT: mr r5, r7
Show All 11 Lines
; LE-PWR8-NEXT: mr r8, r4 ; LE-PWR8-NEXT: mr r8, r4
; LE-PWR8-NEXT: add r3, r5, r6 ; LE-PWR8-NEXT: add r3, r5, r6
; LE-PWR8-NEXT: stq r8, 0(r3) ; LE-PWR8-NEXT: stq r8, 0(r3)
; LE-PWR8-NEXT: blr ; LE-PWR8-NEXT: blr
; ;
; AIX64-PWR8-LABEL: stqx_unordered: ; AIX64-PWR8-LABEL: stqx_unordered:
; AIX64-PWR8: # %bb.0: # %entry ; AIX64-PWR8: # %bb.0: # %entry
; AIX64-PWR8-NEXT: mflr r0 ; AIX64-PWR8-NEXT: mflr r0
; AIX64-PWR8-NEXT: std r0, 16(r1)
; AIX64-PWR8-NEXT: stdu r1, -112(r1) ; AIX64-PWR8-NEXT: stdu r1, -112(r1)
; AIX64-PWR8-NEXT: mr r7, r4 ; AIX64-PWR8-NEXT: mr r7, r4
; AIX64-PWR8-NEXT: mr r4, r3 ; AIX64-PWR8-NEXT: mr r4, r3
; AIX64-PWR8-NEXT: std r0, 128(r1)
; AIX64-PWR8-NEXT: sldi r3, r6, 4 ; AIX64-PWR8-NEXT: sldi r3, r6, 4
; AIX64-PWR8-NEXT: li r6, 0 ; AIX64-PWR8-NEXT: li r6, 0
; AIX64-PWR8-NEXT: add r3, r5, r3 ; AIX64-PWR8-NEXT: add r3, r5, r3
; AIX64-PWR8-NEXT: mr r5, r7 ; AIX64-PWR8-NEXT: mr r5, r7
; AIX64-PWR8-NEXT: bl .__atomic_store_16[PR] ; AIX64-PWR8-NEXT: bl .__atomic_store_16[PR]
; AIX64-PWR8-NEXT: nop ; AIX64-PWR8-NEXT: nop
; AIX64-PWR8-NEXT: addi r1, r1, 112 ; AIX64-PWR8-NEXT: addi r1, r1, 112
; AIX64-PWR8-NEXT: ld r0, 16(r1) ; AIX64-PWR8-NEXT: ld r0, 16(r1)
; AIX64-PWR8-NEXT: mtlr r0 ; AIX64-PWR8-NEXT: mtlr r0
; AIX64-PWR8-NEXT: blr ; AIX64-PWR8-NEXT: blr
; ;
; PPC-PWR8-LABEL: stqx_unordered: ; PPC-PWR8-LABEL: stqx_unordered:
; PPC-PWR8: # %bb.0: # %entry ; PPC-PWR8: # %bb.0: # %entry
; PPC-PWR8-NEXT: mflr r0 ; PPC-PWR8-NEXT: mflr r0
; PPC-PWR8-NEXT: stw r0, 4(r1)
; PPC-PWR8-NEXT: stwu r1, -32(r1) ; PPC-PWR8-NEXT: stwu r1, -32(r1)
; PPC-PWR8-NEXT: stw r0, 36(r1)
; PPC-PWR8-NEXT: .cfi_def_cfa_offset 32 ; PPC-PWR8-NEXT: .cfi_def_cfa_offset 32
; PPC-PWR8-NEXT: .cfi_offset lr, 4 ; PPC-PWR8-NEXT: .cfi_offset lr, 4
; PPC-PWR8-NEXT: slwi r8, r10, 4 ; PPC-PWR8-NEXT: slwi r8, r10, 4
; PPC-PWR8-NEXT: stw r6, 28(r1) ; PPC-PWR8-NEXT: stw r6, 28(r1)
; PPC-PWR8-NEXT: stw r5, 24(r1) ; PPC-PWR8-NEXT: stw r5, 24(r1)
; PPC-PWR8-NEXT: addi r5, r1, 16 ; PPC-PWR8-NEXT: addi r5, r1, 16
; PPC-PWR8-NEXT: add r6, r7, r8 ; PPC-PWR8-NEXT: add r6, r7, r8
; PPC-PWR8-NEXT: stw r4, 20(r1) ; PPC-PWR8-NEXT: stw r4, 20(r1)
Show All 20 Lines
; P8-NEXT: mr r8, r3 ; P8-NEXT: mr r8, r3
; P8-NEXT: add r3, r5, r6 ; P8-NEXT: add r3, r5, r6
; P8-NEXT: stq r8, 0(r3) ; P8-NEXT: stq r8, 0(r3)
; P8-NEXT: blr ; P8-NEXT: blr
; ;
; PWR7-LABEL: stq_big_offset_unordered: ; PWR7-LABEL: stq_big_offset_unordered:
; PWR7: # %bb.0: # %entry ; PWR7: # %bb.0: # %entry
; PWR7-NEXT: mflr r0 ; PWR7-NEXT: mflr r0
; PWR7-NEXT: std r0, 16(r1)
; PWR7-NEXT: stdu r1, -112(r1) ; PWR7-NEXT: stdu r1, -112(r1)
; PWR7-NEXT: std r0, 128(r1)
; PWR7-NEXT: .cfi_def_cfa_offset 112 ; PWR7-NEXT: .cfi_def_cfa_offset 112
; PWR7-NEXT: .cfi_offset lr, 16 ; PWR7-NEXT: .cfi_offset lr, 16
; PWR7-NEXT: mr r6, r4 ; PWR7-NEXT: mr r6, r4
; PWR7-NEXT: mr r4, r3 ; PWR7-NEXT: mr r4, r3
; PWR7-NEXT: addis r3, r5, 32 ; PWR7-NEXT: addis r3, r5, 32
; PWR7-NEXT: mr r5, r6 ; PWR7-NEXT: mr r5, r6
; PWR7-NEXT: li r6, 0 ; PWR7-NEXT: li r6, 0
; PWR7-NEXT: bl __atomic_store_16 ; PWR7-NEXT: bl __atomic_store_16
Show All 10 Lines
; LE-PWR8-NEXT: mr r8, r4 ; LE-PWR8-NEXT: mr r8, r4
; LE-PWR8-NEXT: add r3, r5, r6 ; LE-PWR8-NEXT: add r3, r5, r6
; LE-PWR8-NEXT: stq r8, 0(r3) ; LE-PWR8-NEXT: stq r8, 0(r3)
; LE-PWR8-NEXT: blr ; LE-PWR8-NEXT: blr
; ;
; AIX64-PWR8-LABEL: stq_big_offset_unordered: ; AIX64-PWR8-LABEL: stq_big_offset_unordered:
; AIX64-PWR8: # %bb.0: # %entry ; AIX64-PWR8: # %bb.0: # %entry
; AIX64-PWR8-NEXT: mflr r0 ; AIX64-PWR8-NEXT: mflr r0
; AIX64-PWR8-NEXT: std r0, 16(r1)
; AIX64-PWR8-NEXT: stdu r1, -112(r1) ; AIX64-PWR8-NEXT: stdu r1, -112(r1)
; AIX64-PWR8-NEXT: mr r6, r4 ; AIX64-PWR8-NEXT: mr r6, r4
; AIX64-PWR8-NEXT: mr r4, r3 ; AIX64-PWR8-NEXT: mr r4, r3
; AIX64-PWR8-NEXT: addis r3, r5, 32 ; AIX64-PWR8-NEXT: addis r3, r5, 32
; AIX64-PWR8-NEXT: std r0, 128(r1)
; AIX64-PWR8-NEXT: mr r5, r6 ; AIX64-PWR8-NEXT: mr r5, r6
; AIX64-PWR8-NEXT: li r6, 0 ; AIX64-PWR8-NEXT: li r6, 0
; AIX64-PWR8-NEXT: bl .__atomic_store_16[PR] ; AIX64-PWR8-NEXT: bl .__atomic_store_16[PR]
; AIX64-PWR8-NEXT: nop ; AIX64-PWR8-NEXT: nop
; AIX64-PWR8-NEXT: addi r1, r1, 112 ; AIX64-PWR8-NEXT: addi r1, r1, 112
; AIX64-PWR8-NEXT: ld r0, 16(r1) ; AIX64-PWR8-NEXT: ld r0, 16(r1)
; AIX64-PWR8-NEXT: mtlr r0 ; AIX64-PWR8-NEXT: mtlr r0
; AIX64-PWR8-NEXT: blr ; AIX64-PWR8-NEXT: blr
; ;
; PPC-PWR8-LABEL: stq_big_offset_unordered: ; PPC-PWR8-LABEL: stq_big_offset_unordered:
; PPC-PWR8: # %bb.0: # %entry ; PPC-PWR8: # %bb.0: # %entry
; PPC-PWR8-NEXT: mflr r0 ; PPC-PWR8-NEXT: mflr r0
; PPC-PWR8-NEXT: stw r0, 4(r1)
; PPC-PWR8-NEXT: stwu r1, -32(r1) ; PPC-PWR8-NEXT: stwu r1, -32(r1)
; PPC-PWR8-NEXT: stw r0, 36(r1)
; PPC-PWR8-NEXT: .cfi_def_cfa_offset 32 ; PPC-PWR8-NEXT: .cfi_def_cfa_offset 32
; PPC-PWR8-NEXT: .cfi_offset lr, 4 ; PPC-PWR8-NEXT: .cfi_offset lr, 4
; PPC-PWR8-NEXT: stw r6, 28(r1) ; PPC-PWR8-NEXT: stw r6, 28(r1)
; PPC-PWR8-NEXT: addis r6, r7, 32 ; PPC-PWR8-NEXT: addis r6, r7, 32
; PPC-PWR8-NEXT: stw r5, 24(r1) ; PPC-PWR8-NEXT: stw r5, 24(r1)
; PPC-PWR8-NEXT: addi r5, r1, 16 ; PPC-PWR8-NEXT: addi r5, r1, 16
; PPC-PWR8-NEXT: stw r4, 20(r1) ; PPC-PWR8-NEXT: stw r4, 20(r1)
; PPC-PWR8-NEXT: stw r3, 16(r1) ; PPC-PWR8-NEXT: stw r3, 16(r1)
Show All 17 Lines
; P8-NEXT: mr r7, r4 ; P8-NEXT: mr r7, r4
; P8-NEXT: mr r6, r3 ; P8-NEXT: mr r6, r3
; P8-NEXT: stq r6, 0(r5) ; P8-NEXT: stq r6, 0(r5)
; P8-NEXT: blr ; P8-NEXT: blr
; ;
; PWR7-LABEL: stq_monotonic: ; PWR7-LABEL: stq_monotonic:
; PWR7: # %bb.0: # %entry ; PWR7: # %bb.0: # %entry
; PWR7-NEXT: mflr r0 ; PWR7-NEXT: mflr r0
; PWR7-NEXT: std r0, 16(r1)
; PWR7-NEXT: stdu r1, -112(r1) ; PWR7-NEXT: stdu r1, -112(r1)
; PWR7-NEXT: std r0, 128(r1)
; PWR7-NEXT: .cfi_def_cfa_offset 112 ; PWR7-NEXT: .cfi_def_cfa_offset 112
; PWR7-NEXT: .cfi_offset lr, 16 ; PWR7-NEXT: .cfi_offset lr, 16
; PWR7-NEXT: mr r6, r4 ; PWR7-NEXT: mr r6, r4
; PWR7-NEXT: mr r4, r3 ; PWR7-NEXT: mr r4, r3
; PWR7-NEXT: mr r3, r5 ; PWR7-NEXT: mr r3, r5
; PWR7-NEXT: mr r5, r6 ; PWR7-NEXT: mr r5, r6
; PWR7-NEXT: li r6, 0 ; PWR7-NEXT: li r6, 0
; PWR7-NEXT: bl __atomic_store_16 ; PWR7-NEXT: bl __atomic_store_16
; PWR7-NEXT: nop ; PWR7-NEXT: nop
; PWR7-NEXT: addi r1, r1, 112 ; PWR7-NEXT: addi r1, r1, 112
; PWR7-NEXT: ld r0, 16(r1) ; PWR7-NEXT: ld r0, 16(r1)
; PWR7-NEXT: mtlr r0 ; PWR7-NEXT: mtlr r0
; PWR7-NEXT: blr ; PWR7-NEXT: blr
; ;
; LE-PWR8-LABEL: stq_monotonic: ; LE-PWR8-LABEL: stq_monotonic:
; LE-PWR8: # %bb.0: # %entry ; LE-PWR8: # %bb.0: # %entry
; LE-PWR8-NEXT: mr r7, r3 ; LE-PWR8-NEXT: mr r7, r3
; LE-PWR8-NEXT: mr r6, r4 ; LE-PWR8-NEXT: mr r6, r4
; LE-PWR8-NEXT: stq r6, 0(r5) ; LE-PWR8-NEXT: stq r6, 0(r5)
; LE-PWR8-NEXT: blr ; LE-PWR8-NEXT: blr
; ;
; AIX64-PWR8-LABEL: stq_monotonic: ; AIX64-PWR8-LABEL: stq_monotonic:
; AIX64-PWR8: # %bb.0: # %entry ; AIX64-PWR8: # %bb.0: # %entry
; AIX64-PWR8-NEXT: mflr r0 ; AIX64-PWR8-NEXT: mflr r0
; AIX64-PWR8-NEXT: std r0, 16(r1)
; AIX64-PWR8-NEXT: stdu r1, -112(r1) ; AIX64-PWR8-NEXT: stdu r1, -112(r1)
; AIX64-PWR8-NEXT: mr r6, r4 ; AIX64-PWR8-NEXT: mr r6, r4
; AIX64-PWR8-NEXT: mr r4, r3 ; AIX64-PWR8-NEXT: mr r4, r3
; AIX64-PWR8-NEXT: mr r3, r5 ; AIX64-PWR8-NEXT: mr r3, r5
; AIX64-PWR8-NEXT: std r0, 128(r1)
; AIX64-PWR8-NEXT: mr r5, r6 ; AIX64-PWR8-NEXT: mr r5, r6
; AIX64-PWR8-NEXT: li r6, 0 ; AIX64-PWR8-NEXT: li r6, 0
; AIX64-PWR8-NEXT: bl .__atomic_store_16[PR] ; AIX64-PWR8-NEXT: bl .__atomic_store_16[PR]
; AIX64-PWR8-NEXT: nop ; AIX64-PWR8-NEXT: nop
; AIX64-PWR8-NEXT: addi r1, r1, 112 ; AIX64-PWR8-NEXT: addi r1, r1, 112
; AIX64-PWR8-NEXT: ld r0, 16(r1) ; AIX64-PWR8-NEXT: ld r0, 16(r1)
; AIX64-PWR8-NEXT: mtlr r0 ; AIX64-PWR8-NEXT: mtlr r0
; AIX64-PWR8-NEXT: blr ; AIX64-PWR8-NEXT: blr
; ;
; PPC-PWR8-LABEL: stq_monotonic: ; PPC-PWR8-LABEL: stq_monotonic:
; PPC-PWR8: # %bb.0: # %entry ; PPC-PWR8: # %bb.0: # %entry
; PPC-PWR8-NEXT: mflr r0 ; PPC-PWR8-NEXT: mflr r0
; PPC-PWR8-NEXT: stw r0, 4(r1)
; PPC-PWR8-NEXT: stwu r1, -32(r1) ; PPC-PWR8-NEXT: stwu r1, -32(r1)
; PPC-PWR8-NEXT: stw r0, 36(r1)
; PPC-PWR8-NEXT: .cfi_def_cfa_offset 32 ; PPC-PWR8-NEXT: .cfi_def_cfa_offset 32
; PPC-PWR8-NEXT: .cfi_offset lr, 4 ; PPC-PWR8-NEXT: .cfi_offset lr, 4
; PPC-PWR8-NEXT: stw r6, 28(r1) ; PPC-PWR8-NEXT: stw r6, 28(r1)
; PPC-PWR8-NEXT: stw r5, 24(r1) ; PPC-PWR8-NEXT: stw r5, 24(r1)
; PPC-PWR8-NEXT: addi r5, r1, 16 ; PPC-PWR8-NEXT: addi r5, r1, 16
; PPC-PWR8-NEXT: li r6, 0 ; PPC-PWR8-NEXT: li r6, 0
; PPC-PWR8-NEXT: stw r4, 20(r1) ; PPC-PWR8-NEXT: stw r4, 20(r1)
; PPC-PWR8-NEXT: stw r3, 16(r1) ; PPC-PWR8-NEXT: stw r3, 16(r1)
Show All 16 Lines
; P8-NEXT: mr r7, r4 ; P8-NEXT: mr r7, r4
; P8-NEXT: mr r6, r3 ; P8-NEXT: mr r6, r3
; P8-NEXT: stq r6, 0(r5) ; P8-NEXT: stq r6, 0(r5)
; P8-NEXT: blr ; P8-NEXT: blr
; ;
; PWR7-LABEL: stq_release: ; PWR7-LABEL: stq_release:
; PWR7: # %bb.0: # %entry ; PWR7: # %bb.0: # %entry
; PWR7-NEXT: mflr r0 ; PWR7-NEXT: mflr r0
; PWR7-NEXT: std r0, 16(r1)
; PWR7-NEXT: stdu r1, -112(r1) ; PWR7-NEXT: stdu r1, -112(r1)
; PWR7-NEXT: std r0, 128(r1)
; PWR7-NEXT: .cfi_def_cfa_offset 112 ; PWR7-NEXT: .cfi_def_cfa_offset 112
; PWR7-NEXT: .cfi_offset lr, 16 ; PWR7-NEXT: .cfi_offset lr, 16
; PWR7-NEXT: mr r6, r4 ; PWR7-NEXT: mr r6, r4
; PWR7-NEXT: mr r4, r3 ; PWR7-NEXT: mr r4, r3
; PWR7-NEXT: mr r3, r5 ; PWR7-NEXT: mr r3, r5
; PWR7-NEXT: mr r5, r6 ; PWR7-NEXT: mr r5, r6
; PWR7-NEXT: li r6, 3 ; PWR7-NEXT: li r6, 3
; PWR7-NEXT: bl __atomic_store_16 ; PWR7-NEXT: bl __atomic_store_16
Show All 9 Lines
; LE-PWR8-NEXT: mr r7, r3 ; LE-PWR8-NEXT: mr r7, r3
; LE-PWR8-NEXT: mr r6, r4 ; LE-PWR8-NEXT: mr r6, r4
; LE-PWR8-NEXT: stq r6, 0(r5) ; LE-PWR8-NEXT: stq r6, 0(r5)
; LE-PWR8-NEXT: blr ; LE-PWR8-NEXT: blr
; ;
; AIX64-PWR8-LABEL: stq_release: ; AIX64-PWR8-LABEL: stq_release:
; AIX64-PWR8: # %bb.0: # %entry ; AIX64-PWR8: # %bb.0: # %entry
; AIX64-PWR8-NEXT: mflr r0 ; AIX64-PWR8-NEXT: mflr r0
; AIX64-PWR8-NEXT: std r0, 16(r1)
; AIX64-PWR8-NEXT: stdu r1, -112(r1) ; AIX64-PWR8-NEXT: stdu r1, -112(r1)
; AIX64-PWR8-NEXT: mr r6, r4 ; AIX64-PWR8-NEXT: mr r6, r4
; AIX64-PWR8-NEXT: mr r4, r3 ; AIX64-PWR8-NEXT: mr r4, r3
; AIX64-PWR8-NEXT: mr r3, r5 ; AIX64-PWR8-NEXT: mr r3, r5
; AIX64-PWR8-NEXT: std r0, 128(r1)
; AIX64-PWR8-NEXT: mr r5, r6 ; AIX64-PWR8-NEXT: mr r5, r6
; AIX64-PWR8-NEXT: li r6, 3 ; AIX64-PWR8-NEXT: li r6, 3
; AIX64-PWR8-NEXT: bl .__atomic_store_16[PR] ; AIX64-PWR8-NEXT: bl .__atomic_store_16[PR]
; AIX64-PWR8-NEXT: nop ; AIX64-PWR8-NEXT: nop
; AIX64-PWR8-NEXT: addi r1, r1, 112 ; AIX64-PWR8-NEXT: addi r1, r1, 112
; AIX64-PWR8-NEXT: ld r0, 16(r1) ; AIX64-PWR8-NEXT: ld r0, 16(r1)
; AIX64-PWR8-NEXT: mtlr r0 ; AIX64-PWR8-NEXT: mtlr r0
; AIX64-PWR8-NEXT: blr ; AIX64-PWR8-NEXT: blr
; ;
; PPC-PWR8-LABEL: stq_release: ; PPC-PWR8-LABEL: stq_release:
; PPC-PWR8: # %bb.0: # %entry ; PPC-PWR8: # %bb.0: # %entry
; PPC-PWR8-NEXT: mflr r0 ; PPC-PWR8-NEXT: mflr r0
; PPC-PWR8-NEXT: stw r0, 4(r1)
; PPC-PWR8-NEXT: stwu r1, -32(r1) ; PPC-PWR8-NEXT: stwu r1, -32(r1)
; PPC-PWR8-NEXT: stw r0, 36(r1)
; PPC-PWR8-NEXT: .cfi_def_cfa_offset 32 ; PPC-PWR8-NEXT: .cfi_def_cfa_offset 32
; PPC-PWR8-NEXT: .cfi_offset lr, 4 ; PPC-PWR8-NEXT: .cfi_offset lr, 4
; PPC-PWR8-NEXT: stw r6, 28(r1) ; PPC-PWR8-NEXT: stw r6, 28(r1)
; PPC-PWR8-NEXT: stw r5, 24(r1) ; PPC-PWR8-NEXT: stw r5, 24(r1)
; PPC-PWR8-NEXT: addi r5, r1, 16 ; PPC-PWR8-NEXT: addi r5, r1, 16
; PPC-PWR8-NEXT: li r6, 3 ; PPC-PWR8-NEXT: li r6, 3
; PPC-PWR8-NEXT: stw r4, 20(r1) ; PPC-PWR8-NEXT: stw r4, 20(r1)
; PPC-PWR8-NEXT: stw r3, 16(r1) ; PPC-PWR8-NEXT: stw r3, 16(r1)
Show All 16 Lines
; P8-NEXT: mr r7, r4 ; P8-NEXT: mr r7, r4
; P8-NEXT: mr r6, r3 ; P8-NEXT: mr r6, r3
; P8-NEXT: stq r6, 0(r5) ; P8-NEXT: stq r6, 0(r5)
; P8-NEXT: blr ; P8-NEXT: blr
; ;
; PWR7-LABEL: stq_seqcst: ; PWR7-LABEL: stq_seqcst:
; PWR7: # %bb.0: # %entry ; PWR7: # %bb.0: # %entry
; PWR7-NEXT: mflr r0 ; PWR7-NEXT: mflr r0
; PWR7-NEXT: std r0, 16(r1)
; PWR7-NEXT: stdu r1, -112(r1) ; PWR7-NEXT: stdu r1, -112(r1)
; PWR7-NEXT: std r0, 128(r1)
; PWR7-NEXT: .cfi_def_cfa_offset 112 ; PWR7-NEXT: .cfi_def_cfa_offset 112
; PWR7-NEXT: .cfi_offset lr, 16 ; PWR7-NEXT: .cfi_offset lr, 16
; PWR7-NEXT: mr r6, r4 ; PWR7-NEXT: mr r6, r4
; PWR7-NEXT: mr r4, r3 ; PWR7-NEXT: mr r4, r3
; PWR7-NEXT: mr r3, r5 ; PWR7-NEXT: mr r3, r5
; PWR7-NEXT: mr r5, r6 ; PWR7-NEXT: mr r5, r6
; PWR7-NEXT: li r6, 5 ; PWR7-NEXT: li r6, 5
; PWR7-NEXT: bl __atomic_store_16 ; PWR7-NEXT: bl __atomic_store_16
Show All 9 Lines
; LE-PWR8-NEXT: mr r7, r3 ; LE-PWR8-NEXT: mr r7, r3
; LE-PWR8-NEXT: mr r6, r4 ; LE-PWR8-NEXT: mr r6, r4
; LE-PWR8-NEXT: stq r6, 0(r5) ; LE-PWR8-NEXT: stq r6, 0(r5)
; LE-PWR8-NEXT: blr ; LE-PWR8-NEXT: blr
; ;
; AIX64-PWR8-LABEL: stq_seqcst: ; AIX64-PWR8-LABEL: stq_seqcst:
; AIX64-PWR8: # %bb.0: # %entry ; AIX64-PWR8: # %bb.0: # %entry
; AIX64-PWR8-NEXT: mflr r0 ; AIX64-PWR8-NEXT: mflr r0
; AIX64-PWR8-NEXT: std r0, 16(r1)
; AIX64-PWR8-NEXT: stdu r1, -112(r1) ; AIX64-PWR8-NEXT: stdu r1, -112(r1)
; AIX64-PWR8-NEXT: mr r6, r4 ; AIX64-PWR8-NEXT: mr r6, r4
; AIX64-PWR8-NEXT: mr r4, r3 ; AIX64-PWR8-NEXT: mr r4, r3
; AIX64-PWR8-NEXT: mr r3, r5 ; AIX64-PWR8-NEXT: mr r3, r5
; AIX64-PWR8-NEXT: std r0, 128(r1)
; AIX64-PWR8-NEXT: mr r5, r6 ; AIX64-PWR8-NEXT: mr r5, r6
; AIX64-PWR8-NEXT: li r6, 5 ; AIX64-PWR8-NEXT: li r6, 5
; AIX64-PWR8-NEXT: bl .__atomic_store_16[PR] ; AIX64-PWR8-NEXT: bl .__atomic_store_16[PR]
; AIX64-PWR8-NEXT: nop ; AIX64-PWR8-NEXT: nop
; AIX64-PWR8-NEXT: addi r1, r1, 112 ; AIX64-PWR8-NEXT: addi r1, r1, 112
; AIX64-PWR8-NEXT: ld r0, 16(r1) ; AIX64-PWR8-NEXT: ld r0, 16(r1)
; AIX64-PWR8-NEXT: mtlr r0 ; AIX64-PWR8-NEXT: mtlr r0
; AIX64-PWR8-NEXT: blr ; AIX64-PWR8-NEXT: blr
; ;
; PPC-PWR8-LABEL: stq_seqcst: ; PPC-PWR8-LABEL: stq_seqcst:
; PPC-PWR8: # %bb.0: # %entry ; PPC-PWR8: # %bb.0: # %entry
; PPC-PWR8-NEXT: mflr r0 ; PPC-PWR8-NEXT: mflr r0
; PPC-PWR8-NEXT: stw r0, 4(r1)
; PPC-PWR8-NEXT: stwu r1, -32(r1) ; PPC-PWR8-NEXT: stwu r1, -32(r1)
; PPC-PWR8-NEXT: stw r0, 36(r1)
; PPC-PWR8-NEXT: .cfi_def_cfa_offset 32 ; PPC-PWR8-NEXT: .cfi_def_cfa_offset 32
; PPC-PWR8-NEXT: .cfi_offset lr, 4 ; PPC-PWR8-NEXT: .cfi_offset lr, 4
; PPC-PWR8-NEXT: stw r6, 28(r1) ; PPC-PWR8-NEXT: stw r6, 28(r1)
; PPC-PWR8-NEXT: stw r5, 24(r1) ; PPC-PWR8-NEXT: stw r5, 24(r1)
; PPC-PWR8-NEXT: addi r5, r1, 16 ; PPC-PWR8-NEXT: addi r5, r1, 16
; PPC-PWR8-NEXT: li r6, 5 ; PPC-PWR8-NEXT: li r6, 5
; PPC-PWR8-NEXT: stw r4, 20(r1) ; PPC-PWR8-NEXT: stw r4, 20(r1)
; PPC-PWR8-NEXT: stw r3, 16(r1) ; PPC-PWR8-NEXT: stw r3, 16(r1)
Show All 11 Lines

llvm/test/CodeGen/PowerPC/atomics-i128.ll

Show All 37 Lines
; CHECK-NEXT: lwsync ; CHECK-NEXT: lwsync
; CHECK-NEXT: mr r3, r6 ; CHECK-NEXT: mr r3, r6
; CHECK-NEXT: mr r4, r7 ; CHECK-NEXT: mr r4, r7
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; PWR7-LABEL: swap: ; PWR7-LABEL: swap:
; PWR7: # %bb.0: # %entry ; PWR7: # %bb.0: # %entry
; PWR7-NEXT: mflr r0 ; PWR7-NEXT: mflr r0
; PWR7-NEXT: std r0, 16(r1)
; PWR7-NEXT: stdu r1, -112(r1) ; PWR7-NEXT: stdu r1, -112(r1)
; PWR7-NEXT: std r0, 128(r1)
; PWR7-NEXT: .cfi_def_cfa_offset 112 ; PWR7-NEXT: .cfi_def_cfa_offset 112
; PWR7-NEXT: .cfi_offset lr, 16 ; PWR7-NEXT: .cfi_offset lr, 16
; PWR7-NEXT: li r6, 5 ; PWR7-NEXT: li r6, 5
; PWR7-NEXT: bl __atomic_exchange_16 ; PWR7-NEXT: bl __atomic_exchange_16
; PWR7-NEXT: nop ; PWR7-NEXT: nop
; PWR7-NEXT: addi r1, r1, 112 ; PWR7-NEXT: addi r1, r1, 112
; PWR7-NEXT: ld r0, 16(r1) ; PWR7-NEXT: ld r0, 16(r1)
; PWR7-NEXT: mtlr r0 ; PWR7-NEXT: mtlr r0
Show All 13 Lines
; LE-PWR8-NEXT: lwsync ; LE-PWR8-NEXT: lwsync
; LE-PWR8-NEXT: mr r3, r7 ; LE-PWR8-NEXT: mr r3, r7
; LE-PWR8-NEXT: mr r4, r6 ; LE-PWR8-NEXT: mr r4, r6
; LE-PWR8-NEXT: blr ; LE-PWR8-NEXT: blr
; ;
; AIX64-PWR8-LABEL: swap: ; AIX64-PWR8-LABEL: swap:
; AIX64-PWR8: # %bb.0: # %entry ; AIX64-PWR8: # %bb.0: # %entry
; AIX64-PWR8-NEXT: mflr r0 ; AIX64-PWR8-NEXT: mflr r0
; AIX64-PWR8-NEXT: std r0, 16(r1)
; AIX64-PWR8-NEXT: stdu r1, -112(r1) ; AIX64-PWR8-NEXT: stdu r1, -112(r1)
; AIX64-PWR8-NEXT: li r6, 5 ; AIX64-PWR8-NEXT: li r6, 5
; AIX64-PWR8-NEXT: std r0, 128(r1)
; AIX64-PWR8-NEXT: bl .__atomic_exchange_16[PR] ; AIX64-PWR8-NEXT: bl .__atomic_exchange_16[PR]
; AIX64-PWR8-NEXT: nop ; AIX64-PWR8-NEXT: nop
; AIX64-PWR8-NEXT: addi r1, r1, 112 ; AIX64-PWR8-NEXT: addi r1, r1, 112
; AIX64-PWR8-NEXT: ld r0, 16(r1) ; AIX64-PWR8-NEXT: ld r0, 16(r1)
; AIX64-PWR8-NEXT: mtlr r0 ; AIX64-PWR8-NEXT: mtlr r0
; AIX64-PWR8-NEXT: blr ; AIX64-PWR8-NEXT: blr
; ;
; PPC-PWR8-LABEL: swap: ; PPC-PWR8-LABEL: swap:
; PPC-PWR8: # %bb.0: # %entry ; PPC-PWR8: # %bb.0: # %entry
; PPC-PWR8-NEXT: mflr r0 ; PPC-PWR8-NEXT: mflr r0
; PPC-PWR8-NEXT: stw r0, 4(r1)
; PPC-PWR8-NEXT: stwu r1, -48(r1) ; PPC-PWR8-NEXT: stwu r1, -48(r1)
; PPC-PWR8-NEXT: stw r0, 52(r1)
; PPC-PWR8-NEXT: .cfi_def_cfa_offset 48 ; PPC-PWR8-NEXT: .cfi_def_cfa_offset 48
; PPC-PWR8-NEXT: .cfi_offset lr, 4 ; PPC-PWR8-NEXT: .cfi_offset lr, 4
; PPC-PWR8-NEXT: mr r4, r3 ; PPC-PWR8-NEXT: mr r4, r3
; PPC-PWR8-NEXT: stw r7, 40(r1) ; PPC-PWR8-NEXT: stw r7, 40(r1)
; PPC-PWR8-NEXT: stw r6, 36(r1) ; PPC-PWR8-NEXT: stw r6, 36(r1)
; PPC-PWR8-NEXT: addi r6, r1, 16 ; PPC-PWR8-NEXT: addi r6, r1, 16
; PPC-PWR8-NEXT: li r3, 16 ; PPC-PWR8-NEXT: li r3, 16
; PPC-PWR8-NEXT: li r7, 5 ; PPC-PWR8-NEXT: li r7, 5
Show All 29 Lines
; CHECK-NEXT: lwsync ; CHECK-NEXT: lwsync
; CHECK-NEXT: mr r3, r6 ; CHECK-NEXT: mr r3, r6
; CHECK-NEXT: mr r4, r7 ; CHECK-NEXT: mr r4, r7
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; PWR7-LABEL: add: ; PWR7-LABEL: add:
; PWR7: # %bb.0: # %entry ; PWR7: # %bb.0: # %entry
; PWR7-NEXT: mflr r0 ; PWR7-NEXT: mflr r0
; PWR7-NEXT: std r0, 16(r1)
; PWR7-NEXT: stdu r1, -112(r1) ; PWR7-NEXT: stdu r1, -112(r1)
; PWR7-NEXT: std r0, 128(r1)
; PWR7-NEXT: .cfi_def_cfa_offset 112 ; PWR7-NEXT: .cfi_def_cfa_offset 112
; PWR7-NEXT: .cfi_offset lr, 16 ; PWR7-NEXT: .cfi_offset lr, 16
; PWR7-NEXT: li r6, 5 ; PWR7-NEXT: li r6, 5
; PWR7-NEXT: bl __atomic_fetch_add_16 ; PWR7-NEXT: bl __atomic_fetch_add_16
; PWR7-NEXT: nop ; PWR7-NEXT: nop
; PWR7-NEXT: addi r1, r1, 112 ; PWR7-NEXT: addi r1, r1, 112
; PWR7-NEXT: ld r0, 16(r1) ; PWR7-NEXT: ld r0, 16(r1)
; PWR7-NEXT: mtlr r0 ; PWR7-NEXT: mtlr r0
Show All 13 Lines
; LE-PWR8-NEXT: lwsync ; LE-PWR8-NEXT: lwsync
; LE-PWR8-NEXT: mr r3, r7 ; LE-PWR8-NEXT: mr r3, r7
; LE-PWR8-NEXT: mr r4, r6 ; LE-PWR8-NEXT: mr r4, r6
; LE-PWR8-NEXT: blr ; LE-PWR8-NEXT: blr
; ;
; AIX64-PWR8-LABEL: add: ; AIX64-PWR8-LABEL: add:
; AIX64-PWR8: # %bb.0: # %entry ; AIX64-PWR8: # %bb.0: # %entry
; AIX64-PWR8-NEXT: mflr r0 ; AIX64-PWR8-NEXT: mflr r0
; AIX64-PWR8-NEXT: std r0, 16(r1)
; AIX64-PWR8-NEXT: stdu r1, -112(r1) ; AIX64-PWR8-NEXT: stdu r1, -112(r1)
; AIX64-PWR8-NEXT: li r6, 5 ; AIX64-PWR8-NEXT: li r6, 5
; AIX64-PWR8-NEXT: std r0, 128(r1)
; AIX64-PWR8-NEXT: bl .__atomic_fetch_add_16[PR] ; AIX64-PWR8-NEXT: bl .__atomic_fetch_add_16[PR]
; AIX64-PWR8-NEXT: nop ; AIX64-PWR8-NEXT: nop
; AIX64-PWR8-NEXT: addi r1, r1, 112 ; AIX64-PWR8-NEXT: addi r1, r1, 112
; AIX64-PWR8-NEXT: ld r0, 16(r1) ; AIX64-PWR8-NEXT: ld r0, 16(r1)
; AIX64-PWR8-NEXT: mtlr r0 ; AIX64-PWR8-NEXT: mtlr r0
; AIX64-PWR8-NEXT: blr ; AIX64-PWR8-NEXT: blr
; ;
; PPC-PWR8-LABEL: add: ; PPC-PWR8-LABEL: add:
; PPC-PWR8: # %bb.0: # %entry ; PPC-PWR8: # %bb.0: # %entry
; PPC-PWR8-NEXT: mflr r0 ; PPC-PWR8-NEXT: mflr r0
; PPC-PWR8-NEXT: stw r0, 4(r1)
; PPC-PWR8-NEXT: stwu r1, -80(r1) ; PPC-PWR8-NEXT: stwu r1, -80(r1)
; PPC-PWR8-NEXT: stw r0, 84(r1)
; PPC-PWR8-NEXT: .cfi_def_cfa_offset 80 ; PPC-PWR8-NEXT: .cfi_def_cfa_offset 80
; PPC-PWR8-NEXT: .cfi_offset lr, 4 ; PPC-PWR8-NEXT: .cfi_offset lr, 4
; PPC-PWR8-NEXT: .cfi_offset r24, -32 ; PPC-PWR8-NEXT: .cfi_offset r24, -32
; PPC-PWR8-NEXT: .cfi_offset r25, -28 ; PPC-PWR8-NEXT: .cfi_offset r25, -28
; PPC-PWR8-NEXT: .cfi_offset r26, -24 ; PPC-PWR8-NEXT: .cfi_offset r26, -24
; PPC-PWR8-NEXT: .cfi_offset r27, -20 ; PPC-PWR8-NEXT: .cfi_offset r27, -20
; PPC-PWR8-NEXT: .cfi_offset r28, -16 ; PPC-PWR8-NEXT: .cfi_offset r28, -16
; PPC-PWR8-NEXT: .cfi_offset r29, -12 ; PPC-PWR8-NEXT: .cfi_offset r29, -12
▲ Show 20 Lines • Show All 76 Lines • ▼ Show 20 Lines
; CHECK-NEXT: lwsync ; CHECK-NEXT: lwsync
; CHECK-NEXT: mr r3, r6 ; CHECK-NEXT: mr r3, r6
; CHECK-NEXT: mr r4, r7 ; CHECK-NEXT: mr r4, r7
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; PWR7-LABEL: sub: ; PWR7-LABEL: sub:
; PWR7: # %bb.0: # %entry ; PWR7: # %bb.0: # %entry
; PWR7-NEXT: mflr r0 ; PWR7-NEXT: mflr r0
; PWR7-NEXT: std r0, 16(r1)
; PWR7-NEXT: stdu r1, -112(r1) ; PWR7-NEXT: stdu r1, -112(r1)
; PWR7-NEXT: std r0, 128(r1)
; PWR7-NEXT: .cfi_def_cfa_offset 112 ; PWR7-NEXT: .cfi_def_cfa_offset 112
; PWR7-NEXT: .cfi_offset lr, 16 ; PWR7-NEXT: .cfi_offset lr, 16
; PWR7-NEXT: li r6, 5 ; PWR7-NEXT: li r6, 5
; PWR7-NEXT: bl __atomic_fetch_sub_16 ; PWR7-NEXT: bl __atomic_fetch_sub_16
; PWR7-NEXT: nop ; PWR7-NEXT: nop
; PWR7-NEXT: addi r1, r1, 112 ; PWR7-NEXT: addi r1, r1, 112
; PWR7-NEXT: ld r0, 16(r1) ; PWR7-NEXT: ld r0, 16(r1)
; PWR7-NEXT: mtlr r0 ; PWR7-NEXT: mtlr r0
Show All 13 Lines
; LE-PWR8-NEXT: lwsync ; LE-PWR8-NEXT: lwsync
; LE-PWR8-NEXT: mr r3, r7 ; LE-PWR8-NEXT: mr r3, r7
; LE-PWR8-NEXT: mr r4, r6 ; LE-PWR8-NEXT: mr r4, r6
; LE-PWR8-NEXT: blr ; LE-PWR8-NEXT: blr
; ;
; AIX64-PWR8-LABEL: sub: ; AIX64-PWR8-LABEL: sub:
; AIX64-PWR8: # %bb.0: # %entry ; AIX64-PWR8: # %bb.0: # %entry
; AIX64-PWR8-NEXT: mflr r0 ; AIX64-PWR8-NEXT: mflr r0
; AIX64-PWR8-NEXT: std r0, 16(r1)
; AIX64-PWR8-NEXT: stdu r1, -112(r1) ; AIX64-PWR8-NEXT: stdu r1, -112(r1)
; AIX64-PWR8-NEXT: li r6, 5 ; AIX64-PWR8-NEXT: li r6, 5
; AIX64-PWR8-NEXT: std r0, 128(r1)
; AIX64-PWR8-NEXT: bl .__atomic_fetch_sub_16[PR] ; AIX64-PWR8-NEXT: bl .__atomic_fetch_sub_16[PR]
; AIX64-PWR8-NEXT: nop ; AIX64-PWR8-NEXT: nop
; AIX64-PWR8-NEXT: addi r1, r1, 112 ; AIX64-PWR8-NEXT: addi r1, r1, 112
; AIX64-PWR8-NEXT: ld r0, 16(r1) ; AIX64-PWR8-NEXT: ld r0, 16(r1)
; AIX64-PWR8-NEXT: mtlr r0 ; AIX64-PWR8-NEXT: mtlr r0
; AIX64-PWR8-NEXT: blr ; AIX64-PWR8-NEXT: blr
; ;
; PPC-PWR8-LABEL: sub: ; PPC-PWR8-LABEL: sub:
; PPC-PWR8: # %bb.0: # %entry ; PPC-PWR8: # %bb.0: # %entry
; PPC-PWR8-NEXT: mflr r0 ; PPC-PWR8-NEXT: mflr r0
; PPC-PWR8-NEXT: stw r0, 4(r1)
; PPC-PWR8-NEXT: stwu r1, -80(r1) ; PPC-PWR8-NEXT: stwu r1, -80(r1)
; PPC-PWR8-NEXT: stw r0, 84(r1)
; PPC-PWR8-NEXT: .cfi_def_cfa_offset 80 ; PPC-PWR8-NEXT: .cfi_def_cfa_offset 80
; PPC-PWR8-NEXT: .cfi_offset lr, 4 ; PPC-PWR8-NEXT: .cfi_offset lr, 4
; PPC-PWR8-NEXT: .cfi_offset r24, -32 ; PPC-PWR8-NEXT: .cfi_offset r24, -32
; PPC-PWR8-NEXT: .cfi_offset r25, -28 ; PPC-PWR8-NEXT: .cfi_offset r25, -28
; PPC-PWR8-NEXT: .cfi_offset r26, -24 ; PPC-PWR8-NEXT: .cfi_offset r26, -24
; PPC-PWR8-NEXT: .cfi_offset r27, -20 ; PPC-PWR8-NEXT: .cfi_offset r27, -20
; PPC-PWR8-NEXT: .cfi_offset r28, -16 ; PPC-PWR8-NEXT: .cfi_offset r28, -16
; PPC-PWR8-NEXT: .cfi_offset r29, -12 ; PPC-PWR8-NEXT: .cfi_offset r29, -12
▲ Show 20 Lines • Show All 76 Lines • ▼ Show 20 Lines
; CHECK-NEXT: lwsync ; CHECK-NEXT: lwsync
; CHECK-NEXT: mr r3, r6 ; CHECK-NEXT: mr r3, r6
; CHECK-NEXT: mr r4, r7 ; CHECK-NEXT: mr r4, r7
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; PWR7-LABEL: and: ; PWR7-LABEL: and:
; PWR7: # %bb.0: # %entry ; PWR7: # %bb.0: # %entry
; PWR7-NEXT: mflr r0 ; PWR7-NEXT: mflr r0
; PWR7-NEXT: std r0, 16(r1)
; PWR7-NEXT: stdu r1, -112(r1) ; PWR7-NEXT: stdu r1, -112(r1)
; PWR7-NEXT: std r0, 128(r1)
; PWR7-NEXT: .cfi_def_cfa_offset 112 ; PWR7-NEXT: .cfi_def_cfa_offset 112
; PWR7-NEXT: .cfi_offset lr, 16 ; PWR7-NEXT: .cfi_offset lr, 16
; PWR7-NEXT: li r6, 5 ; PWR7-NEXT: li r6, 5
; PWR7-NEXT: bl __atomic_fetch_and_16 ; PWR7-NEXT: bl __atomic_fetch_and_16
; PWR7-NEXT: nop ; PWR7-NEXT: nop
; PWR7-NEXT: addi r1, r1, 112 ; PWR7-NEXT: addi r1, r1, 112
; PWR7-NEXT: ld r0, 16(r1) ; PWR7-NEXT: ld r0, 16(r1)
; PWR7-NEXT: mtlr r0 ; PWR7-NEXT: mtlr r0
Show All 13 Lines
; LE-PWR8-NEXT: lwsync ; LE-PWR8-NEXT: lwsync
; LE-PWR8-NEXT: mr r3, r7 ; LE-PWR8-NEXT: mr r3, r7
; LE-PWR8-NEXT: mr r4, r6 ; LE-PWR8-NEXT: mr r4, r6
; LE-PWR8-NEXT: blr ; LE-PWR8-NEXT: blr
; ;
; AIX64-PWR8-LABEL: and: ; AIX64-PWR8-LABEL: and:
; AIX64-PWR8: # %bb.0: # %entry ; AIX64-PWR8: # %bb.0: # %entry
; AIX64-PWR8-NEXT: mflr r0 ; AIX64-PWR8-NEXT: mflr r0
; AIX64-PWR8-NEXT: std r0, 16(r1)
; AIX64-PWR8-NEXT: stdu r1, -112(r1) ; AIX64-PWR8-NEXT: stdu r1, -112(r1)
; AIX64-PWR8-NEXT: li r6, 5 ; AIX64-PWR8-NEXT: li r6, 5
; AIX64-PWR8-NEXT: std r0, 128(r1)
; AIX64-PWR8-NEXT: bl .__atomic_fetch_and_16[PR] ; AIX64-PWR8-NEXT: bl .__atomic_fetch_and_16[PR]
; AIX64-PWR8-NEXT: nop ; AIX64-PWR8-NEXT: nop
; AIX64-PWR8-NEXT: addi r1, r1, 112 ; AIX64-PWR8-NEXT: addi r1, r1, 112
; AIX64-PWR8-NEXT: ld r0, 16(r1) ; AIX64-PWR8-NEXT: ld r0, 16(r1)
; AIX64-PWR8-NEXT: mtlr r0 ; AIX64-PWR8-NEXT: mtlr r0
; AIX64-PWR8-NEXT: blr ; AIX64-PWR8-NEXT: blr
; ;
; PPC-PWR8-LABEL: and: ; PPC-PWR8-LABEL: and:
; PPC-PWR8: # %bb.0: # %entry ; PPC-PWR8: # %bb.0: # %entry
; PPC-PWR8-NEXT: mflr r0 ; PPC-PWR8-NEXT: mflr r0
; PPC-PWR8-NEXT: stw r0, 4(r1)
; PPC-PWR8-NEXT: stwu r1, -80(r1) ; PPC-PWR8-NEXT: stwu r1, -80(r1)
; PPC-PWR8-NEXT: stw r0, 84(r1)
; PPC-PWR8-NEXT: .cfi_def_cfa_offset 80 ; PPC-PWR8-NEXT: .cfi_def_cfa_offset 80
; PPC-PWR8-NEXT: .cfi_offset lr, 4 ; PPC-PWR8-NEXT: .cfi_offset lr, 4
; PPC-PWR8-NEXT: .cfi_offset r24, -32 ; PPC-PWR8-NEXT: .cfi_offset r24, -32
; PPC-PWR8-NEXT: .cfi_offset r25, -28 ; PPC-PWR8-NEXT: .cfi_offset r25, -28
; PPC-PWR8-NEXT: .cfi_offset r26, -24 ; PPC-PWR8-NEXT: .cfi_offset r26, -24
; PPC-PWR8-NEXT: .cfi_offset r27, -20 ; PPC-PWR8-NEXT: .cfi_offset r27, -20
; PPC-PWR8-NEXT: .cfi_offset r28, -16 ; PPC-PWR8-NEXT: .cfi_offset r28, -16
; PPC-PWR8-NEXT: .cfi_offset r29, -12 ; PPC-PWR8-NEXT: .cfi_offset r29, -12
▲ Show 20 Lines • Show All 76 Lines • ▼ Show 20 Lines
; CHECK-NEXT: lwsync ; CHECK-NEXT: lwsync
; CHECK-NEXT: mr r3, r6 ; CHECK-NEXT: mr r3, r6
; CHECK-NEXT: mr r4, r7 ; CHECK-NEXT: mr r4, r7
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; PWR7-LABEL: or: ; PWR7-LABEL: or:
; PWR7: # %bb.0: # %entry ; PWR7: # %bb.0: # %entry
; PWR7-NEXT: mflr r0 ; PWR7-NEXT: mflr r0
; PWR7-NEXT: std r0, 16(r1)
; PWR7-NEXT: stdu r1, -112(r1) ; PWR7-NEXT: stdu r1, -112(r1)
; PWR7-NEXT: std r0, 128(r1)
; PWR7-NEXT: .cfi_def_cfa_offset 112 ; PWR7-NEXT: .cfi_def_cfa_offset 112
; PWR7-NEXT: .cfi_offset lr, 16 ; PWR7-NEXT: .cfi_offset lr, 16
; PWR7-NEXT: li r6, 5 ; PWR7-NEXT: li r6, 5
; PWR7-NEXT: bl __atomic_fetch_or_16 ; PWR7-NEXT: bl __atomic_fetch_or_16
; PWR7-NEXT: nop ; PWR7-NEXT: nop
; PWR7-NEXT: addi r1, r1, 112 ; PWR7-NEXT: addi r1, r1, 112
; PWR7-NEXT: ld r0, 16(r1) ; PWR7-NEXT: ld r0, 16(r1)
; PWR7-NEXT: mtlr r0 ; PWR7-NEXT: mtlr r0
Show All 13 Lines
; LE-PWR8-NEXT: lwsync ; LE-PWR8-NEXT: lwsync
; LE-PWR8-NEXT: mr r3, r7 ; LE-PWR8-NEXT: mr r3, r7
; LE-PWR8-NEXT: mr r4, r6 ; LE-PWR8-NEXT: mr r4, r6
; LE-PWR8-NEXT: blr ; LE-PWR8-NEXT: blr
; ;
; AIX64-PWR8-LABEL: or: ; AIX64-PWR8-LABEL: or:
; AIX64-PWR8: # %bb.0: # %entry ; AIX64-PWR8: # %bb.0: # %entry
; AIX64-PWR8-NEXT: mflr r0 ; AIX64-PWR8-NEXT: mflr r0
; AIX64-PWR8-NEXT: std r0, 16(r1)
; AIX64-PWR8-NEXT: stdu r1, -112(r1) ; AIX64-PWR8-NEXT: stdu r1, -112(r1)
; AIX64-PWR8-NEXT: li r6, 5 ; AIX64-PWR8-NEXT: li r6, 5
; AIX64-PWR8-NEXT: std r0, 128(r1)
; AIX64-PWR8-NEXT: bl .__atomic_fetch_or_16[PR] ; AIX64-PWR8-NEXT: bl .__atomic_fetch_or_16[PR]
; AIX64-PWR8-NEXT: nop ; AIX64-PWR8-NEXT: nop
; AIX64-PWR8-NEXT: addi r1, r1, 112 ; AIX64-PWR8-NEXT: addi r1, r1, 112
; AIX64-PWR8-NEXT: ld r0, 16(r1) ; AIX64-PWR8-NEXT: ld r0, 16(r1)
; AIX64-PWR8-NEXT: mtlr r0 ; AIX64-PWR8-NEXT: mtlr r0
; AIX64-PWR8-NEXT: blr ; AIX64-PWR8-NEXT: blr
; ;
; PPC-PWR8-LABEL: or: ; PPC-PWR8-LABEL: or:
; PPC-PWR8: # %bb.0: # %entry ; PPC-PWR8: # %bb.0: # %entry
; PPC-PWR8-NEXT: mflr r0 ; PPC-PWR8-NEXT: mflr r0
; PPC-PWR8-NEXT: stw r0, 4(r1)
; PPC-PWR8-NEXT: stwu r1, -80(r1) ; PPC-PWR8-NEXT: stwu r1, -80(r1)
; PPC-PWR8-NEXT: stw r0, 84(r1)
; PPC-PWR8-NEXT: .cfi_def_cfa_offset 80 ; PPC-PWR8-NEXT: .cfi_def_cfa_offset 80
; PPC-PWR8-NEXT: .cfi_offset lr, 4 ; PPC-PWR8-NEXT: .cfi_offset lr, 4
; PPC-PWR8-NEXT: .cfi_offset r24, -32 ; PPC-PWR8-NEXT: .cfi_offset r24, -32
; PPC-PWR8-NEXT: .cfi_offset r25, -28 ; PPC-PWR8-NEXT: .cfi_offset r25, -28
; PPC-PWR8-NEXT: .cfi_offset r26, -24 ; PPC-PWR8-NEXT: .cfi_offset r26, -24
; PPC-PWR8-NEXT: .cfi_offset r27, -20 ; PPC-PWR8-NEXT: .cfi_offset r27, -20
; PPC-PWR8-NEXT: .cfi_offset r28, -16 ; PPC-PWR8-NEXT: .cfi_offset r28, -16
; PPC-PWR8-NEXT: .cfi_offset r29, -12 ; PPC-PWR8-NEXT: .cfi_offset r29, -12
▲ Show 20 Lines • Show All 76 Lines • ▼ Show 20 Lines
; CHECK-NEXT: lwsync ; CHECK-NEXT: lwsync
; CHECK-NEXT: mr r3, r6 ; CHECK-NEXT: mr r3, r6
; CHECK-NEXT: mr r4, r7 ; CHECK-NEXT: mr r4, r7
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; PWR7-LABEL: xor: ; PWR7-LABEL: xor:
; PWR7: # %bb.0: # %entry ; PWR7: # %bb.0: # %entry
; PWR7-NEXT: mflr r0 ; PWR7-NEXT: mflr r0
; PWR7-NEXT: std r0, 16(r1)
; PWR7-NEXT: stdu r1, -112(r1) ; PWR7-NEXT: stdu r1, -112(r1)
; PWR7-NEXT: std r0, 128(r1)
; PWR7-NEXT: .cfi_def_cfa_offset 112 ; PWR7-NEXT: .cfi_def_cfa_offset 112
; PWR7-NEXT: .cfi_offset lr, 16 ; PWR7-NEXT: .cfi_offset lr, 16
; PWR7-NEXT: li r6, 5 ; PWR7-NEXT: li r6, 5
; PWR7-NEXT: bl __atomic_fetch_xor_16 ; PWR7-NEXT: bl __atomic_fetch_xor_16
; PWR7-NEXT: nop ; PWR7-NEXT: nop
; PWR7-NEXT: addi r1, r1, 112 ; PWR7-NEXT: addi r1, r1, 112
; PWR7-NEXT: ld r0, 16(r1) ; PWR7-NEXT: ld r0, 16(r1)
; PWR7-NEXT: mtlr r0 ; PWR7-NEXT: mtlr r0
Show All 13 Lines
; LE-PWR8-NEXT: lwsync ; LE-PWR8-NEXT: lwsync
; LE-PWR8-NEXT: mr r3, r7 ; LE-PWR8-NEXT: mr r3, r7
; LE-PWR8-NEXT: mr r4, r6 ; LE-PWR8-NEXT: mr r4, r6
; LE-PWR8-NEXT: blr ; LE-PWR8-NEXT: blr
; ;
; AIX64-PWR8-LABEL: xor: ; AIX64-PWR8-LABEL: xor:
; AIX64-PWR8: # %bb.0: # %entry ; AIX64-PWR8: # %bb.0: # %entry
; AIX64-PWR8-NEXT: mflr r0 ; AIX64-PWR8-NEXT: mflr r0
; AIX64-PWR8-NEXT: std r0, 16(r1)
; AIX64-PWR8-NEXT: stdu r1, -112(r1) ; AIX64-PWR8-NEXT: stdu r1, -112(r1)
; AIX64-PWR8-NEXT: li r6, 5 ; AIX64-PWR8-NEXT: li r6, 5
; AIX64-PWR8-NEXT: std r0, 128(r1)
; AIX64-PWR8-NEXT: bl .__atomic_fetch_xor_16[PR] ; AIX64-PWR8-NEXT: bl .__atomic_fetch_xor_16[PR]
; AIX64-PWR8-NEXT: nop ; AIX64-PWR8-NEXT: nop
; AIX64-PWR8-NEXT: addi r1, r1, 112 ; AIX64-PWR8-NEXT: addi r1, r1, 112
; AIX64-PWR8-NEXT: ld r0, 16(r1) ; AIX64-PWR8-NEXT: ld r0, 16(r1)
; AIX64-PWR8-NEXT: mtlr r0 ; AIX64-PWR8-NEXT: mtlr r0
; AIX64-PWR8-NEXT: blr ; AIX64-PWR8-NEXT: blr
; ;
; PPC-PWR8-LABEL: xor: ; PPC-PWR8-LABEL: xor:
; PPC-PWR8: # %bb.0: # %entry ; PPC-PWR8: # %bb.0: # %entry
; PPC-PWR8-NEXT: mflr r0 ; PPC-PWR8-NEXT: mflr r0
; PPC-PWR8-NEXT: stw r0, 4(r1)
; PPC-PWR8-NEXT: stwu r1, -80(r1) ; PPC-PWR8-NEXT: stwu r1, -80(r1)
; PPC-PWR8-NEXT: stw r0, 84(r1)
; PPC-PWR8-NEXT: .cfi_def_cfa_offset 80 ; PPC-PWR8-NEXT: .cfi_def_cfa_offset 80
; PPC-PWR8-NEXT: .cfi_offset lr, 4 ; PPC-PWR8-NEXT: .cfi_offset lr, 4
; PPC-PWR8-NEXT: .cfi_offset r24, -32 ; PPC-PWR8-NEXT: .cfi_offset r24, -32
; PPC-PWR8-NEXT: .cfi_offset r25, -28 ; PPC-PWR8-NEXT: .cfi_offset r25, -28
; PPC-PWR8-NEXT: .cfi_offset r26, -24 ; PPC-PWR8-NEXT: .cfi_offset r26, -24
; PPC-PWR8-NEXT: .cfi_offset r27, -20 ; PPC-PWR8-NEXT: .cfi_offset r27, -20
; PPC-PWR8-NEXT: .cfi_offset r28, -16 ; PPC-PWR8-NEXT: .cfi_offset r28, -16
; PPC-PWR8-NEXT: .cfi_offset r29, -12 ; PPC-PWR8-NEXT: .cfi_offset r29, -12
▲ Show 20 Lines • Show All 76 Lines • ▼ Show 20 Lines
; CHECK-NEXT: lwsync ; CHECK-NEXT: lwsync
; CHECK-NEXT: mr r3, r6 ; CHECK-NEXT: mr r3, r6
; CHECK-NEXT: mr r4, r7 ; CHECK-NEXT: mr r4, r7
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; PWR7-LABEL: nand: ; PWR7-LABEL: nand:
; PWR7: # %bb.0: # %entry ; PWR7: # %bb.0: # %entry
; PWR7-NEXT: mflr r0 ; PWR7-NEXT: mflr r0
; PWR7-NEXT: std r0, 16(r1)
; PWR7-NEXT: stdu r1, -112(r1) ; PWR7-NEXT: stdu r1, -112(r1)
; PWR7-NEXT: std r0, 128(r1)
; PWR7-NEXT: .cfi_def_cfa_offset 112 ; PWR7-NEXT: .cfi_def_cfa_offset 112
; PWR7-NEXT: .cfi_offset lr, 16 ; PWR7-NEXT: .cfi_offset lr, 16
; PWR7-NEXT: li r6, 5 ; PWR7-NEXT: li r6, 5
; PWR7-NEXT: bl __atomic_fetch_nand_16 ; PWR7-NEXT: bl __atomic_fetch_nand_16
; PWR7-NEXT: nop ; PWR7-NEXT: nop
; PWR7-NEXT: addi r1, r1, 112 ; PWR7-NEXT: addi r1, r1, 112
; PWR7-NEXT: ld r0, 16(r1) ; PWR7-NEXT: ld r0, 16(r1)
; PWR7-NEXT: mtlr r0 ; PWR7-NEXT: mtlr r0
Show All 13 Lines
; LE-PWR8-NEXT: lwsync ; LE-PWR8-NEXT: lwsync
; LE-PWR8-NEXT: mr r3, r7 ; LE-PWR8-NEXT: mr r3, r7
; LE-PWR8-NEXT: mr r4, r6 ; LE-PWR8-NEXT: mr r4, r6
; LE-PWR8-NEXT: blr ; LE-PWR8-NEXT: blr
; ;
; AIX64-PWR8-LABEL: nand: ; AIX64-PWR8-LABEL: nand:
; AIX64-PWR8: # %bb.0: # %entry ; AIX64-PWR8: # %bb.0: # %entry
; AIX64-PWR8-NEXT: mflr r0 ; AIX64-PWR8-NEXT: mflr r0
; AIX64-PWR8-NEXT: std r0, 16(r1)
; AIX64-PWR8-NEXT: stdu r1, -112(r1) ; AIX64-PWR8-NEXT: stdu r1, -112(r1)
; AIX64-PWR8-NEXT: li r6, 5 ; AIX64-PWR8-NEXT: li r6, 5
; AIX64-PWR8-NEXT: std r0, 128(r1)
; AIX64-PWR8-NEXT: bl .__atomic_fetch_nand_16[PR] ; AIX64-PWR8-NEXT: bl .__atomic_fetch_nand_16[PR]
; AIX64-PWR8-NEXT: nop ; AIX64-PWR8-NEXT: nop
; AIX64-PWR8-NEXT: addi r1, r1, 112 ; AIX64-PWR8-NEXT: addi r1, r1, 112
; AIX64-PWR8-NEXT: ld r0, 16(r1) ; AIX64-PWR8-NEXT: ld r0, 16(r1)
; AIX64-PWR8-NEXT: mtlr r0 ; AIX64-PWR8-NEXT: mtlr r0
; AIX64-PWR8-NEXT: blr ; AIX64-PWR8-NEXT: blr
; ;
; PPC-PWR8-LABEL: nand: ; PPC-PWR8-LABEL: nand:
; PPC-PWR8: # %bb.0: # %entry ; PPC-PWR8: # %bb.0: # %entry
; PPC-PWR8-NEXT: mflr r0 ; PPC-PWR8-NEXT: mflr r0
; PPC-PWR8-NEXT: stw r0, 4(r1)
; PPC-PWR8-NEXT: stwu r1, -80(r1) ; PPC-PWR8-NEXT: stwu r1, -80(r1)
; PPC-PWR8-NEXT: stw r0, 84(r1)
; PPC-PWR8-NEXT: .cfi_def_cfa_offset 80 ; PPC-PWR8-NEXT: .cfi_def_cfa_offset 80
; PPC-PWR8-NEXT: .cfi_offset lr, 4 ; PPC-PWR8-NEXT: .cfi_offset lr, 4
; PPC-PWR8-NEXT: .cfi_offset r24, -32 ; PPC-PWR8-NEXT: .cfi_offset r24, -32
; PPC-PWR8-NEXT: .cfi_offset r25, -28 ; PPC-PWR8-NEXT: .cfi_offset r25, -28
; PPC-PWR8-NEXT: .cfi_offset r26, -24 ; PPC-PWR8-NEXT: .cfi_offset r26, -24
; PPC-PWR8-NEXT: .cfi_offset r27, -20 ; PPC-PWR8-NEXT: .cfi_offset r27, -20
; PPC-PWR8-NEXT: .cfi_offset r28, -16 ; PPC-PWR8-NEXT: .cfi_offset r28, -16
; PPC-PWR8-NEXT: .cfi_offset r29, -12 ; PPC-PWR8-NEXT: .cfi_offset r29, -12
▲ Show 20 Lines • Show All 85 Lines • ▼ Show 20 Lines
; CHECK-NEXT: lwsync ; CHECK-NEXT: lwsync
; CHECK-NEXT: mr r3, r8 ; CHECK-NEXT: mr r3, r8
; CHECK-NEXT: mr r4, r9 ; CHECK-NEXT: mr r4, r9
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; PWR7-LABEL: cas_weak_acquire_acquire: ; PWR7-LABEL: cas_weak_acquire_acquire:
; PWR7: # %bb.0: # %entry ; PWR7: # %bb.0: # %entry
; PWR7-NEXT: mflr r0 ; PWR7-NEXT: mflr r0
; PWR7-NEXT: std r0, 16(r1)
; PWR7-NEXT: stdu r1, -128(r1) ; PWR7-NEXT: stdu r1, -128(r1)
; PWR7-NEXT: std r0, 144(r1)
; PWR7-NEXT: .cfi_def_cfa_offset 128 ; PWR7-NEXT: .cfi_def_cfa_offset 128
; PWR7-NEXT: .cfi_offset lr, 16 ; PWR7-NEXT: .cfi_offset lr, 16
; PWR7-NEXT: std r5, 120(r1) ; PWR7-NEXT: std r5, 120(r1)
; PWR7-NEXT: std r4, 112(r1) ; PWR7-NEXT: std r4, 112(r1)
; PWR7-NEXT: addi r4, r1, 112 ; PWR7-NEXT: addi r4, r1, 112
; PWR7-NEXT: mr r5, r6 ; PWR7-NEXT: mr r5, r6
; PWR7-NEXT: mr r6, r7 ; PWR7-NEXT: mr r6, r7
; PWR7-NEXT: li r7, 2 ; PWR7-NEXT: li r7, 2
Show All 29 Lines
; LE-PWR8-NEXT: lwsync ; LE-PWR8-NEXT: lwsync
; LE-PWR8-NEXT: mr r3, r9 ; LE-PWR8-NEXT: mr r3, r9
; LE-PWR8-NEXT: mr r4, r8 ; LE-PWR8-NEXT: mr r4, r8
; LE-PWR8-NEXT: blr ; LE-PWR8-NEXT: blr
; ;
; AIX64-PWR8-LABEL: cas_weak_acquire_acquire: ; AIX64-PWR8-LABEL: cas_weak_acquire_acquire:
; AIX64-PWR8: # %bb.0: # %entry ; AIX64-PWR8: # %bb.0: # %entry
; AIX64-PWR8-NEXT: mflr r0 ; AIX64-PWR8-NEXT: mflr r0
; AIX64-PWR8-NEXT: std r0, 16(r1)
; AIX64-PWR8-NEXT: stdu r1, -128(r1) ; AIX64-PWR8-NEXT: stdu r1, -128(r1)
; AIX64-PWR8-NEXT: std r0, 144(r1)
; AIX64-PWR8-NEXT: std r5, 120(r1) ; AIX64-PWR8-NEXT: std r5, 120(r1)
; AIX64-PWR8-NEXT: std r4, 112(r1) ; AIX64-PWR8-NEXT: std r4, 112(r1)
; AIX64-PWR8-NEXT: addi r4, r1, 112 ; AIX64-PWR8-NEXT: addi r4, r1, 112
; AIX64-PWR8-NEXT: mr r5, r6 ; AIX64-PWR8-NEXT: mr r5, r6
; AIX64-PWR8-NEXT: mr r6, r7 ; AIX64-PWR8-NEXT: mr r6, r7
; AIX64-PWR8-NEXT: li r7, 2 ; AIX64-PWR8-NEXT: li r7, 2
; AIX64-PWR8-NEXT: li r8, 2 ; AIX64-PWR8-NEXT: li r8, 2
; AIX64-PWR8-NEXT: bl .__atomic_compare_exchange_16[PR] ; AIX64-PWR8-NEXT: bl .__atomic_compare_exchange_16[PR]
; AIX64-PWR8-NEXT: nop ; AIX64-PWR8-NEXT: nop
; AIX64-PWR8-NEXT: ld r4, 120(r1) ; AIX64-PWR8-NEXT: ld r4, 120(r1)
; AIX64-PWR8-NEXT: ld r3, 112(r1) ; AIX64-PWR8-NEXT: ld r3, 112(r1)
; AIX64-PWR8-NEXT: addi r1, r1, 128 ; AIX64-PWR8-NEXT: addi r1, r1, 128
; AIX64-PWR8-NEXT: ld r0, 16(r1) ; AIX64-PWR8-NEXT: ld r0, 16(r1)
; AIX64-PWR8-NEXT: mtlr r0 ; AIX64-PWR8-NEXT: mtlr r0
; AIX64-PWR8-NEXT: blr ; AIX64-PWR8-NEXT: blr
; ;
; PPC-PWR8-LABEL: cas_weak_acquire_acquire: ; PPC-PWR8-LABEL: cas_weak_acquire_acquire:
; PPC-PWR8: # %bb.0: # %entry ; PPC-PWR8: # %bb.0: # %entry
; PPC-PWR8-NEXT: mflr r0 ; PPC-PWR8-NEXT: mflr r0
; PPC-PWR8-NEXT: stw r0, 4(r1)
; PPC-PWR8-NEXT: stwu r1, -48(r1) ; PPC-PWR8-NEXT: stwu r1, -48(r1)
; PPC-PWR8-NEXT: stw r0, 52(r1)
; PPC-PWR8-NEXT: .cfi_def_cfa_offset 48 ; PPC-PWR8-NEXT: .cfi_def_cfa_offset 48
; PPC-PWR8-NEXT: .cfi_offset lr, 4 ; PPC-PWR8-NEXT: .cfi_offset lr, 4
; PPC-PWR8-NEXT: mr r4, r3 ; PPC-PWR8-NEXT: mr r4, r3
; PPC-PWR8-NEXT: lwz r3, 56(r1) ; PPC-PWR8-NEXT: lwz r3, 56(r1)
; PPC-PWR8-NEXT: lwz r11, 60(r1) ; PPC-PWR8-NEXT: lwz r11, 60(r1)
; PPC-PWR8-NEXT: stw r8, 44(r1) ; PPC-PWR8-NEXT: stw r8, 44(r1)
; PPC-PWR8-NEXT: stw r7, 40(r1) ; PPC-PWR8-NEXT: stw r7, 40(r1)
; PPC-PWR8-NEXT: li r7, 2 ; PPC-PWR8-NEXT: li r7, 2
▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Lines
; CHECK-NEXT: .LBB8_4: # %entry ; CHECK-NEXT: .LBB8_4: # %entry
; CHECK-NEXT: mr r3, r8 ; CHECK-NEXT: mr r3, r8
; CHECK-NEXT: mr r4, r9 ; CHECK-NEXT: mr r4, r9
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; PWR7-LABEL: cas_weak_release_monotonic: ; PWR7-LABEL: cas_weak_release_monotonic:
; PWR7: # %bb.0: # %entry ; PWR7: # %bb.0: # %entry
; PWR7-NEXT: mflr r0 ; PWR7-NEXT: mflr r0
; PWR7-NEXT: std r0, 16(r1)
; PWR7-NEXT: stdu r1, -128(r1) ; PWR7-NEXT: stdu r1, -128(r1)
; PWR7-NEXT: std r0, 144(r1)
; PWR7-NEXT: .cfi_def_cfa_offset 128 ; PWR7-NEXT: .cfi_def_cfa_offset 128
; PWR7-NEXT: .cfi_offset lr, 16 ; PWR7-NEXT: .cfi_offset lr, 16
; PWR7-NEXT: std r5, 120(r1) ; PWR7-NEXT: std r5, 120(r1)
; PWR7-NEXT: std r4, 112(r1) ; PWR7-NEXT: std r4, 112(r1)
; PWR7-NEXT: addi r4, r1, 112 ; PWR7-NEXT: addi r4, r1, 112
; PWR7-NEXT: mr r5, r6 ; PWR7-NEXT: mr r5, r6
; PWR7-NEXT: mr r6, r7 ; PWR7-NEXT: mr r6, r7
; PWR7-NEXT: li r7, 3 ; PWR7-NEXT: li r7, 3
Show All 29 Lines
; LE-PWR8-NEXT: .LBB8_4: # %entry ; LE-PWR8-NEXT: .LBB8_4: # %entry
; LE-PWR8-NEXT: mr r3, r9 ; LE-PWR8-NEXT: mr r3, r9
; LE-PWR8-NEXT: mr r4, r8 ; LE-PWR8-NEXT: mr r4, r8
; LE-PWR8-NEXT: blr ; LE-PWR8-NEXT: blr
; ;
; AIX64-PWR8-LABEL: cas_weak_release_monotonic: ; AIX64-PWR8-LABEL: cas_weak_release_monotonic:
; AIX64-PWR8: # %bb.0: # %entry ; AIX64-PWR8: # %bb.0: # %entry
; AIX64-PWR8-NEXT: mflr r0 ; AIX64-PWR8-NEXT: mflr r0
; AIX64-PWR8-NEXT: std r0, 16(r1)
; AIX64-PWR8-NEXT: stdu r1, -128(r1) ; AIX64-PWR8-NEXT: stdu r1, -128(r1)
; AIX64-PWR8-NEXT: std r0, 144(r1)
; AIX64-PWR8-NEXT: std r5, 120(r1) ; AIX64-PWR8-NEXT: std r5, 120(r1)
; AIX64-PWR8-NEXT: std r4, 112(r1) ; AIX64-PWR8-NEXT: std r4, 112(r1)
; AIX64-PWR8-NEXT: addi r4, r1, 112 ; AIX64-PWR8-NEXT: addi r4, r1, 112
; AIX64-PWR8-NEXT: mr r5, r6 ; AIX64-PWR8-NEXT: mr r5, r6
; AIX64-PWR8-NEXT: mr r6, r7 ; AIX64-PWR8-NEXT: mr r6, r7
; AIX64-PWR8-NEXT: li r7, 3 ; AIX64-PWR8-NEXT: li r7, 3
; AIX64-PWR8-NEXT: li r8, 0 ; AIX64-PWR8-NEXT: li r8, 0
; AIX64-PWR8-NEXT: bl .__atomic_compare_exchange_16[PR] ; AIX64-PWR8-NEXT: bl .__atomic_compare_exchange_16[PR]
; AIX64-PWR8-NEXT: nop ; AIX64-PWR8-NEXT: nop
; AIX64-PWR8-NEXT: ld r4, 120(r1) ; AIX64-PWR8-NEXT: ld r4, 120(r1)
; AIX64-PWR8-NEXT: ld r3, 112(r1) ; AIX64-PWR8-NEXT: ld r3, 112(r1)
; AIX64-PWR8-NEXT: addi r1, r1, 128 ; AIX64-PWR8-NEXT: addi r1, r1, 128
; AIX64-PWR8-NEXT: ld r0, 16(r1) ; AIX64-PWR8-NEXT: ld r0, 16(r1)
; AIX64-PWR8-NEXT: mtlr r0 ; AIX64-PWR8-NEXT: mtlr r0
; AIX64-PWR8-NEXT: blr ; AIX64-PWR8-NEXT: blr
; ;
; PPC-PWR8-LABEL: cas_weak_release_monotonic: ; PPC-PWR8-LABEL: cas_weak_release_monotonic:
; PPC-PWR8: # %bb.0: # %entry ; PPC-PWR8: # %bb.0: # %entry
; PPC-PWR8-NEXT: mflr r0 ; PPC-PWR8-NEXT: mflr r0
; PPC-PWR8-NEXT: stw r0, 4(r1)
; PPC-PWR8-NEXT: stwu r1, -48(r1) ; PPC-PWR8-NEXT: stwu r1, -48(r1)
; PPC-PWR8-NEXT: stw r0, 52(r1)
; PPC-PWR8-NEXT: .cfi_def_cfa_offset 48 ; PPC-PWR8-NEXT: .cfi_def_cfa_offset 48
; PPC-PWR8-NEXT: .cfi_offset lr, 4 ; PPC-PWR8-NEXT: .cfi_offset lr, 4
; PPC-PWR8-NEXT: mr r4, r3 ; PPC-PWR8-NEXT: mr r4, r3
; PPC-PWR8-NEXT: lwz r3, 56(r1) ; PPC-PWR8-NEXT: lwz r3, 56(r1)
; PPC-PWR8-NEXT: lwz r11, 60(r1) ; PPC-PWR8-NEXT: lwz r11, 60(r1)
; PPC-PWR8-NEXT: stw r8, 44(r1) ; PPC-PWR8-NEXT: stw r8, 44(r1)
; PPC-PWR8-NEXT: stw r7, 40(r1) ; PPC-PWR8-NEXT: stw r7, 40(r1)
; PPC-PWR8-NEXT: li r7, 3 ; PPC-PWR8-NEXT: li r7, 3
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
; CHECK-NEXT: lwsync ; CHECK-NEXT: lwsync
; CHECK-NEXT: mr r3, r8 ; CHECK-NEXT: mr r3, r8
; CHECK-NEXT: mr r4, r9 ; CHECK-NEXT: mr r4, r9
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; PWR7-LABEL: cas_sc_sc: ; PWR7-LABEL: cas_sc_sc:
; PWR7: # %bb.0: # %entry ; PWR7: # %bb.0: # %entry
; PWR7-NEXT: mflr r0 ; PWR7-NEXT: mflr r0
; PWR7-NEXT: std r0, 16(r1)
; PWR7-NEXT: stdu r1, -128(r1) ; PWR7-NEXT: stdu r1, -128(r1)
; PWR7-NEXT: std r0, 144(r1)
; PWR7-NEXT: .cfi_def_cfa_offset 128 ; PWR7-NEXT: .cfi_def_cfa_offset 128
; PWR7-NEXT: .cfi_offset lr, 16 ; PWR7-NEXT: .cfi_offset lr, 16
; PWR7-NEXT: std r5, 120(r1) ; PWR7-NEXT: std r5, 120(r1)
; PWR7-NEXT: std r4, 112(r1) ; PWR7-NEXT: std r4, 112(r1)
; PWR7-NEXT: addi r4, r1, 112 ; PWR7-NEXT: addi r4, r1, 112
; PWR7-NEXT: mr r5, r6 ; PWR7-NEXT: mr r5, r6
; PWR7-NEXT: mr r6, r7 ; PWR7-NEXT: mr r6, r7
; PWR7-NEXT: li r7, 5 ; PWR7-NEXT: li r7, 5
Show All 30 Lines
; LE-PWR8-NEXT: lwsync ; LE-PWR8-NEXT: lwsync
; LE-PWR8-NEXT: mr r3, r9 ; LE-PWR8-NEXT: mr r3, r9
; LE-PWR8-NEXT: mr r4, r8 ; LE-PWR8-NEXT: mr r4, r8
; LE-PWR8-NEXT: blr ; LE-PWR8-NEXT: blr
; ;
; AIX64-PWR8-LABEL: cas_sc_sc: ; AIX64-PWR8-LABEL: cas_sc_sc:
; AIX64-PWR8: # %bb.0: # %entry ; AIX64-PWR8: # %bb.0: # %entry
; AIX64-PWR8-NEXT: mflr r0 ; AIX64-PWR8-NEXT: mflr r0
; AIX64-PWR8-NEXT: std r0, 16(r1)
; AIX64-PWR8-NEXT: stdu r1, -128(r1) ; AIX64-PWR8-NEXT: stdu r1, -128(r1)
; AIX64-PWR8-NEXT: std r0, 144(r1)
; AIX64-PWR8-NEXT: std r5, 120(r1) ; AIX64-PWR8-NEXT: std r5, 120(r1)
; AIX64-PWR8-NEXT: std r4, 112(r1) ; AIX64-PWR8-NEXT: std r4, 112(r1)
; AIX64-PWR8-NEXT: addi r4, r1, 112 ; AIX64-PWR8-NEXT: addi r4, r1, 112
; AIX64-PWR8-NEXT: mr r5, r6 ; AIX64-PWR8-NEXT: mr r5, r6
; AIX64-PWR8-NEXT: mr r6, r7 ; AIX64-PWR8-NEXT: mr r6, r7
; AIX64-PWR8-NEXT: li r7, 5 ; AIX64-PWR8-NEXT: li r7, 5
; AIX64-PWR8-NEXT: li r8, 5 ; AIX64-PWR8-NEXT: li r8, 5
; AIX64-PWR8-NEXT: bl .__atomic_compare_exchange_16[PR] ; AIX64-PWR8-NEXT: bl .__atomic_compare_exchange_16[PR]
; AIX64-PWR8-NEXT: nop ; AIX64-PWR8-NEXT: nop
; AIX64-PWR8-NEXT: ld r4, 120(r1) ; AIX64-PWR8-NEXT: ld r4, 120(r1)
; AIX64-PWR8-NEXT: ld r3, 112(r1) ; AIX64-PWR8-NEXT: ld r3, 112(r1)
; AIX64-PWR8-NEXT: addi r1, r1, 128 ; AIX64-PWR8-NEXT: addi r1, r1, 128
; AIX64-PWR8-NEXT: ld r0, 16(r1) ; AIX64-PWR8-NEXT: ld r0, 16(r1)
; AIX64-PWR8-NEXT: mtlr r0 ; AIX64-PWR8-NEXT: mtlr r0
; AIX64-PWR8-NEXT: blr ; AIX64-PWR8-NEXT: blr
; ;
; PPC-PWR8-LABEL: cas_sc_sc: ; PPC-PWR8-LABEL: cas_sc_sc:
; PPC-PWR8: # %bb.0: # %entry ; PPC-PWR8: # %bb.0: # %entry
; PPC-PWR8-NEXT: mflr r0 ; PPC-PWR8-NEXT: mflr r0
; PPC-PWR8-NEXT: stw r0, 4(r1)
; PPC-PWR8-NEXT: stwu r1, -48(r1) ; PPC-PWR8-NEXT: stwu r1, -48(r1)
; PPC-PWR8-NEXT: stw r0, 52(r1)
; PPC-PWR8-NEXT: .cfi_def_cfa_offset 48 ; PPC-PWR8-NEXT: .cfi_def_cfa_offset 48
; PPC-PWR8-NEXT: .cfi_offset lr, 4 ; PPC-PWR8-NEXT: .cfi_offset lr, 4
; PPC-PWR8-NEXT: mr r4, r3 ; PPC-PWR8-NEXT: mr r4, r3
; PPC-PWR8-NEXT: lwz r3, 56(r1) ; PPC-PWR8-NEXT: lwz r3, 56(r1)
; PPC-PWR8-NEXT: lwz r11, 60(r1) ; PPC-PWR8-NEXT: lwz r11, 60(r1)
; PPC-PWR8-NEXT: stw r8, 44(r1) ; PPC-PWR8-NEXT: stw r8, 44(r1)
; PPC-PWR8-NEXT: stw r7, 40(r1) ; PPC-PWR8-NEXT: stw r7, 40(r1)
; PPC-PWR8-NEXT: li r7, 5 ; PPC-PWR8-NEXT: li r7, 5
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
; CHECK-NEXT: lwsync ; CHECK-NEXT: lwsync
; CHECK-NEXT: mr r3, r8 ; CHECK-NEXT: mr r3, r8
; CHECK-NEXT: mr r4, r9 ; CHECK-NEXT: mr r4, r9
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; PWR7-LABEL: cas_acqrel_acquire: ; PWR7-LABEL: cas_acqrel_acquire:
; PWR7: # %bb.0: # %entry ; PWR7: # %bb.0: # %entry
; PWR7-NEXT: mflr r0 ; PWR7-NEXT: mflr r0
; PWR7-NEXT: std r0, 16(r1)
; PWR7-NEXT: stdu r1, -128(r1) ; PWR7-NEXT: stdu r1, -128(r1)
; PWR7-NEXT: std r0, 144(r1)
; PWR7-NEXT: .cfi_def_cfa_offset 128 ; PWR7-NEXT: .cfi_def_cfa_offset 128
; PWR7-NEXT: .cfi_offset lr, 16 ; PWR7-NEXT: .cfi_offset lr, 16
; PWR7-NEXT: std r5, 120(r1) ; PWR7-NEXT: std r5, 120(r1)
; PWR7-NEXT: std r4, 112(r1) ; PWR7-NEXT: std r4, 112(r1)
; PWR7-NEXT: addi r4, r1, 112 ; PWR7-NEXT: addi r4, r1, 112
; PWR7-NEXT: mr r5, r6 ; PWR7-NEXT: mr r5, r6
; PWR7-NEXT: mr r6, r7 ; PWR7-NEXT: mr r6, r7
; PWR7-NEXT: li r7, 4 ; PWR7-NEXT: li r7, 4
Show All 30 Lines
; LE-PWR8-NEXT: lwsync ; LE-PWR8-NEXT: lwsync
; LE-PWR8-NEXT: mr r3, r9 ; LE-PWR8-NEXT: mr r3, r9
; LE-PWR8-NEXT: mr r4, r8 ; LE-PWR8-NEXT: mr r4, r8
; LE-PWR8-NEXT: blr ; LE-PWR8-NEXT: blr
; ;
; AIX64-PWR8-LABEL: cas_acqrel_acquire: ; AIX64-PWR8-LABEL: cas_acqrel_acquire:
; AIX64-PWR8: # %bb.0: # %entry ; AIX64-PWR8: # %bb.0: # %entry
; AIX64-PWR8-NEXT: mflr r0 ; AIX64-PWR8-NEXT: mflr r0
; AIX64-PWR8-NEXT: std r0, 16(r1)
; AIX64-PWR8-NEXT: stdu r1, -128(r1) ; AIX64-PWR8-NEXT: stdu r1, -128(r1)
; AIX64-PWR8-NEXT: std r0, 144(r1)
; AIX64-PWR8-NEXT: std r5, 120(r1) ; AIX64-PWR8-NEXT: std r5, 120(r1)
; AIX64-PWR8-NEXT: std r4, 112(r1) ; AIX64-PWR8-NEXT: std r4, 112(r1)
; AIX64-PWR8-NEXT: addi r4, r1, 112 ; AIX64-PWR8-NEXT: addi r4, r1, 112
; AIX64-PWR8-NEXT: mr r5, r6 ; AIX64-PWR8-NEXT: mr r5, r6
; AIX64-PWR8-NEXT: mr r6, r7 ; AIX64-PWR8-NEXT: mr r6, r7
; AIX64-PWR8-NEXT: li r7, 4 ; AIX64-PWR8-NEXT: li r7, 4
; AIX64-PWR8-NEXT: li r8, 2 ; AIX64-PWR8-NEXT: li r8, 2
; AIX64-PWR8-NEXT: bl .__atomic_compare_exchange_16[PR] ; AIX64-PWR8-NEXT: bl .__atomic_compare_exchange_16[PR]
; AIX64-PWR8-NEXT: nop ; AIX64-PWR8-NEXT: nop
; AIX64-PWR8-NEXT: ld r4, 120(r1) ; AIX64-PWR8-NEXT: ld r4, 120(r1)
; AIX64-PWR8-NEXT: ld r3, 112(r1) ; AIX64-PWR8-NEXT: ld r3, 112(r1)
; AIX64-PWR8-NEXT: addi r1, r1, 128 ; AIX64-PWR8-NEXT: addi r1, r1, 128
; AIX64-PWR8-NEXT: ld r0, 16(r1) ; AIX64-PWR8-NEXT: ld r0, 16(r1)
; AIX64-PWR8-NEXT: mtlr r0 ; AIX64-PWR8-NEXT: mtlr r0
; AIX64-PWR8-NEXT: blr ; AIX64-PWR8-NEXT: blr
; ;
; PPC-PWR8-LABEL: cas_acqrel_acquire: ; PPC-PWR8-LABEL: cas_acqrel_acquire:
; PPC-PWR8: # %bb.0: # %entry ; PPC-PWR8: # %bb.0: # %entry
; PPC-PWR8-NEXT: mflr r0 ; PPC-PWR8-NEXT: mflr r0
; PPC-PWR8-NEXT: stw r0, 4(r1)
; PPC-PWR8-NEXT: stwu r1, -48(r1) ; PPC-PWR8-NEXT: stwu r1, -48(r1)
; PPC-PWR8-NEXT: stw r0, 52(r1)
; PPC-PWR8-NEXT: .cfi_def_cfa_offset 48 ; PPC-PWR8-NEXT: .cfi_def_cfa_offset 48
; PPC-PWR8-NEXT: .cfi_offset lr, 4 ; PPC-PWR8-NEXT: .cfi_offset lr, 4
; PPC-PWR8-NEXT: mr r4, r3 ; PPC-PWR8-NEXT: mr r4, r3
; PPC-PWR8-NEXT: lwz r3, 56(r1) ; PPC-PWR8-NEXT: lwz r3, 56(r1)
; PPC-PWR8-NEXT: lwz r11, 60(r1) ; PPC-PWR8-NEXT: lwz r11, 60(r1)
; PPC-PWR8-NEXT: stw r8, 44(r1) ; PPC-PWR8-NEXT: stw r8, 44(r1)
; PPC-PWR8-NEXT: stw r7, 40(r1) ; PPC-PWR8-NEXT: stw r7, 40(r1)
; PPC-PWR8-NEXT: li r7, 4 ; PPC-PWR8-NEXT: li r7, 4
▲ Show 20 Lines • Show All 49 Lines • ▼ Show 20 Lines
; CHECK-NEXT: or r3, r4, r3 ; CHECK-NEXT: or r3, r4, r3
; CHECK-NEXT: cntlzd r3, r3 ; CHECK-NEXT: cntlzd r3, r3
; CHECK-NEXT: rldicl r3, r3, 58, 63 ; CHECK-NEXT: rldicl r3, r3, 58, 63
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; PWR7-LABEL: cas_acqrel_acquire_check_succ: ; PWR7-LABEL: cas_acqrel_acquire_check_succ:
; PWR7: # %bb.0: # %entry ; PWR7: # %bb.0: # %entry
; PWR7-NEXT: mflr r0 ; PWR7-NEXT: mflr r0
; PWR7-NEXT: std r0, 16(r1)
; PWR7-NEXT: stdu r1, -128(r1) ; PWR7-NEXT: stdu r1, -128(r1)
; PWR7-NEXT: std r0, 144(r1)
; PWR7-NEXT: .cfi_def_cfa_offset 128 ; PWR7-NEXT: .cfi_def_cfa_offset 128
; PWR7-NEXT: .cfi_offset lr, 16 ; PWR7-NEXT: .cfi_offset lr, 16
; PWR7-NEXT: std r5, 120(r1) ; PWR7-NEXT: std r5, 120(r1)
; PWR7-NEXT: std r4, 112(r1) ; PWR7-NEXT: std r4, 112(r1)
; PWR7-NEXT: addi r4, r1, 112 ; PWR7-NEXT: addi r4, r1, 112
; PWR7-NEXT: mr r5, r6 ; PWR7-NEXT: mr r5, r6
; PWR7-NEXT: mr r6, r7 ; PWR7-NEXT: mr r6, r7
; PWR7-NEXT: li r7, 4 ; PWR7-NEXT: li r7, 4
Show All 31 Lines
; LE-PWR8-NEXT: or r3, r4, r3 ; LE-PWR8-NEXT: or r3, r4, r3
; LE-PWR8-NEXT: cntlzd r3, r3 ; LE-PWR8-NEXT: cntlzd r3, r3
; LE-PWR8-NEXT: rldicl r3, r3, 58, 63 ; LE-PWR8-NEXT: rldicl r3, r3, 58, 63
; LE-PWR8-NEXT: blr ; LE-PWR8-NEXT: blr
; ;
; AIX64-PWR8-LABEL: cas_acqrel_acquire_check_succ: ; AIX64-PWR8-LABEL: cas_acqrel_acquire_check_succ:
; AIX64-PWR8: # %bb.0: # %entry ; AIX64-PWR8: # %bb.0: # %entry
; AIX64-PWR8-NEXT: mflr r0 ; AIX64-PWR8-NEXT: mflr r0
; AIX64-PWR8-NEXT: std r0, 16(r1)
; AIX64-PWR8-NEXT: stdu r1, -128(r1) ; AIX64-PWR8-NEXT: stdu r1, -128(r1)
; AIX64-PWR8-NEXT: std r0, 144(r1)
; AIX64-PWR8-NEXT: std r5, 120(r1) ; AIX64-PWR8-NEXT: std r5, 120(r1)
; AIX64-PWR8-NEXT: std r4, 112(r1) ; AIX64-PWR8-NEXT: std r4, 112(r1)
; AIX64-PWR8-NEXT: addi r4, r1, 112 ; AIX64-PWR8-NEXT: addi r4, r1, 112
; AIX64-PWR8-NEXT: mr r5, r6 ; AIX64-PWR8-NEXT: mr r5, r6
; AIX64-PWR8-NEXT: mr r6, r7 ; AIX64-PWR8-NEXT: mr r6, r7
; AIX64-PWR8-NEXT: li r7, 4 ; AIX64-PWR8-NEXT: li r7, 4
; AIX64-PWR8-NEXT: li r8, 2 ; AIX64-PWR8-NEXT: li r8, 2
; AIX64-PWR8-NEXT: bl .__atomic_compare_exchange_16[PR] ; AIX64-PWR8-NEXT: bl .__atomic_compare_exchange_16[PR]
; AIX64-PWR8-NEXT: nop ; AIX64-PWR8-NEXT: nop
; AIX64-PWR8-NEXT: addi r1, r1, 128 ; AIX64-PWR8-NEXT: addi r1, r1, 128
; AIX64-PWR8-NEXT: ld r0, 16(r1) ; AIX64-PWR8-NEXT: ld r0, 16(r1)
; AIX64-PWR8-NEXT: mtlr r0 ; AIX64-PWR8-NEXT: mtlr r0
; AIX64-PWR8-NEXT: blr ; AIX64-PWR8-NEXT: blr
; ;
; PPC-PWR8-LABEL: cas_acqrel_acquire_check_succ: ; PPC-PWR8-LABEL: cas_acqrel_acquire_check_succ:
; PPC-PWR8: # %bb.0: # %entry ; PPC-PWR8: # %bb.0: # %entry
; PPC-PWR8-NEXT: mflr r0 ; PPC-PWR8-NEXT: mflr r0
; PPC-PWR8-NEXT: stw r0, 4(r1)
; PPC-PWR8-NEXT: stwu r1, -48(r1) ; PPC-PWR8-NEXT: stwu r1, -48(r1)
; PPC-PWR8-NEXT: stw r0, 52(r1)
; PPC-PWR8-NEXT: .cfi_def_cfa_offset 48 ; PPC-PWR8-NEXT: .cfi_def_cfa_offset 48
; PPC-PWR8-NEXT: .cfi_offset lr, 4 ; PPC-PWR8-NEXT: .cfi_offset lr, 4
; PPC-PWR8-NEXT: mr r4, r3 ; PPC-PWR8-NEXT: mr r4, r3
; PPC-PWR8-NEXT: lwz r3, 56(r1) ; PPC-PWR8-NEXT: lwz r3, 56(r1)
; PPC-PWR8-NEXT: lwz r11, 60(r1) ; PPC-PWR8-NEXT: lwz r11, 60(r1)
; PPC-PWR8-NEXT: stw r8, 44(r1) ; PPC-PWR8-NEXT: stw r8, 44(r1)
; PPC-PWR8-NEXT: stw r7, 40(r1) ; PPC-PWR8-NEXT: stw r7, 40(r1)
; PPC-PWR8-NEXT: li r7, 4 ; PPC-PWR8-NEXT: li r7, 4
Show All 20 Lines

llvm/test/CodeGen/PowerPC/atomics-indexed.ll

Show First 20 Lines • Show All 63 Lines • ▼ Show 20 Lines; CHECK-NEXT: blr
%ptr = getelementptr inbounds [100000 x i32], ptr %mem, i64 0, i64 90000 %ptr = getelementptr inbounds [100000 x i32], ptr %mem, i64 0, i64 90000
%val = load atomic i32, ptr %ptr monotonic, align 4 %val = load atomic i32, ptr %ptr monotonic, align 4
ret i32 %val ret i32 %val
} }
define i64 @load_x_i64_unordered(ptr %mem) { define i64 @load_x_i64_unordered(ptr %mem) {
; PPC32-LABEL: load_x_i64_unordered: ; PPC32-LABEL: load_x_i64_unordered:
; PPC32: # %bb.0: ; PPC32: # %bb.0:
; PPC32-NEXT: mflr r0 ; PPC32-NEXT: mflr r0
; PPC32-NEXT: stw r0, 4(r1)
; PPC32-NEXT: stwu r1, -16(r1) ; PPC32-NEXT: stwu r1, -16(r1)
; PPC32-NEXT: stw r0, 20(r1)
; PPC32-NEXT: .cfi_def_cfa_offset 16 ; PPC32-NEXT: .cfi_def_cfa_offset 16
; PPC32-NEXT: .cfi_offset lr, 4 ; PPC32-NEXT: .cfi_offset lr, 4
; PPC32-NEXT: addi r3, r3, -896 ; PPC32-NEXT: addi r3, r3, -896
; PPC32-NEXT: addis r3, r3, 11 ; PPC32-NEXT: addis r3, r3, 11
; PPC32-NEXT: li r4, 0 ; PPC32-NEXT: li r4, 0
; PPC32-NEXT: bl __atomic_load_8 ; PPC32-NEXT: bl __atomic_load_8
; PPC32-NEXT: lwz r0, 20(r1) ; PPC32-NEXT: lwz r0, 20(r1)
; PPC32-NEXT: addi r1, r1, 16 ; PPC32-NEXT: addi r1, r1, 16
▲ Show 20 Lines • Show All 49 Lines • ▼ Show 20 Lines; CHECK-NEXT: blr
%ptr = getelementptr inbounds [100000 x i32], ptr %mem, i64 0, i64 90000 %ptr = getelementptr inbounds [100000 x i32], ptr %mem, i64 0, i64 90000
store atomic i32 42, ptr %ptr monotonic, align 4 store atomic i32 42, ptr %ptr monotonic, align 4
ret void ret void
} }
define void @store_x_i64_unordered(ptr %mem) { define void @store_x_i64_unordered(ptr %mem) {
; PPC32-LABEL: store_x_i64_unordered: ; PPC32-LABEL: store_x_i64_unordered:
; PPC32: # %bb.0: ; PPC32: # %bb.0:
; PPC32-NEXT: mflr r0 ; PPC32-NEXT: mflr r0
; PPC32-NEXT: stw r0, 4(r1)
; PPC32-NEXT: stwu r1, -16(r1) ; PPC32-NEXT: stwu r1, -16(r1)
; PPC32-NEXT: stw r0, 20(r1)
; PPC32-NEXT: .cfi_def_cfa_offset 16 ; PPC32-NEXT: .cfi_def_cfa_offset 16
; PPC32-NEXT: .cfi_offset lr, 4 ; PPC32-NEXT: .cfi_offset lr, 4
; PPC32-NEXT: addi r3, r3, -896 ; PPC32-NEXT: addi r3, r3, -896
; PPC32-NEXT: addis r3, r3, 11 ; PPC32-NEXT: addis r3, r3, 11
; PPC32-NEXT: li r5, 0 ; PPC32-NEXT: li r5, 0
; PPC32-NEXT: li r6, 42 ; PPC32-NEXT: li r6, 42
; PPC32-NEXT: li r7, 0 ; PPC32-NEXT: li r7, 0
; PPC32-NEXT: bl __atomic_store_8 ; PPC32-NEXT: bl __atomic_store_8
Show All 16 Lines

llvm/test/CodeGen/PowerPC/atomics.ll

Show First 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
; CHECK-PPC64: bne- [[CR]], .+4 ; CHECK-PPC64: bne- [[CR]], .+4
; CHECK-PPC64: isync ; CHECK-PPC64: isync
ret i32 %val ret i32 %val
} }
define i64 @load_i64_seq_cst(ptr %mem) { define i64 @load_i64_seq_cst(ptr %mem) {
; PPC32-LABEL: load_i64_seq_cst: ; PPC32-LABEL: load_i64_seq_cst:
; PPC32: # %bb.0: ; PPC32: # %bb.0:
; PPC32-NEXT: mflr r0 ; PPC32-NEXT: mflr r0
; PPC32-NEXT: stw r0, 4(r1)
; PPC32-NEXT: stwu r1, -16(r1) ; PPC32-NEXT: stwu r1, -16(r1)
; PPC32-NEXT: stw r0, 20(r1)
; PPC32-NEXT: .cfi_def_cfa_offset 16 ; PPC32-NEXT: .cfi_def_cfa_offset 16
; PPC32-NEXT: .cfi_offset lr, 4 ; PPC32-NEXT: .cfi_offset lr, 4
; PPC32-NEXT: li r4, 5 ; PPC32-NEXT: li r4, 5
; PPC32-NEXT: bl __atomic_load_8 ; PPC32-NEXT: bl __atomic_load_8
; PPC32-NEXT: lwz r0, 20(r1) ; PPC32-NEXT: lwz r0, 20(r1)
; PPC32-NEXT: addi r1, r1, 16 ; PPC32-NEXT: addi r1, r1, 16
; PPC32-NEXT: mtlr r0 ; PPC32-NEXT: mtlr r0
; PPC32-NEXT: blr ; PPC32-NEXT: blr
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
; CHECK-NEXT: blr ; CHECK-NEXT: blr
store atomic i32 42, ptr %mem release, align 4 store atomic i32 42, ptr %mem release, align 4
ret void ret void
} }
define void @store_i64_seq_cst(ptr %mem) { define void @store_i64_seq_cst(ptr %mem) {
; PPC32-LABEL: store_i64_seq_cst: ; PPC32-LABEL: store_i64_seq_cst:
; PPC32: # %bb.0: ; PPC32: # %bb.0:
; PPC32-NEXT: mflr r0 ; PPC32-NEXT: mflr r0
; PPC32-NEXT: stw r0, 4(r1)
; PPC32-NEXT: stwu r1, -16(r1) ; PPC32-NEXT: stwu r1, -16(r1)
; PPC32-NEXT: stw r0, 20(r1)
; PPC32-NEXT: .cfi_def_cfa_offset 16 ; PPC32-NEXT: .cfi_def_cfa_offset 16
; PPC32-NEXT: .cfi_offset lr, 4 ; PPC32-NEXT: .cfi_offset lr, 4
; PPC32-NEXT: li r5, 0 ; PPC32-NEXT: li r5, 0
; PPC32-NEXT: li r6, 42 ; PPC32-NEXT: li r6, 42
; PPC32-NEXT: li r7, 5 ; PPC32-NEXT: li r7, 5
; PPC32-NEXT: bl __atomic_store_8 ; PPC32-NEXT: bl __atomic_store_8
; PPC32-NEXT: lwz r0, 20(r1) ; PPC32-NEXT: lwz r0, 20(r1)
; PPC32-NEXT: addi r1, r1, 16 ; PPC32-NEXT: addi r1, r1, 16
▲ Show 20 Lines • Show All 152 Lines • ▼ Show 20 Lines; CHECK-NEXT: blr
%val = cmpxchg ptr %mem, i32 0, i32 1 acq_rel acquire %val = cmpxchg ptr %mem, i32 0, i32 1 acq_rel acquire
%loaded = extractvalue { i32, i1} %val, 0 %loaded = extractvalue { i32, i1} %val, 0
ret i32 %loaded ret i32 %loaded
} }
define i64 @cas_weak_i64_release_monotonic(ptr %mem) { define i64 @cas_weak_i64_release_monotonic(ptr %mem) {
; PPC32-LABEL: cas_weak_i64_release_monotonic: ; PPC32-LABEL: cas_weak_i64_release_monotonic:
; PPC32: # %bb.0: ; PPC32: # %bb.0:
; PPC32-NEXT: mflr r0 ; PPC32-NEXT: mflr r0
; PPC32-NEXT: stw r0, 4(r1)
; PPC32-NEXT: stwu r1, -16(r1) ; PPC32-NEXT: stwu r1, -16(r1)
; PPC32-NEXT: stw r0, 20(r1)
; PPC32-NEXT: .cfi_def_cfa_offset 16 ; PPC32-NEXT: .cfi_def_cfa_offset 16
; PPC32-NEXT: .cfi_offset lr, 4 ; PPC32-NEXT: .cfi_offset lr, 4
; PPC32-NEXT: li r4, 0 ; PPC32-NEXT: li r4, 0
; PPC32-NEXT: stw r4, 12(r1) ; PPC32-NEXT: stw r4, 12(r1)
; PPC32-NEXT: li r5, 0 ; PPC32-NEXT: li r5, 0
; PPC32-NEXT: stw r4, 8(r1) ; PPC32-NEXT: stw r4, 8(r1)
; PPC32-NEXT: addi r4, r1, 8 ; PPC32-NEXT: addi r4, r1, 8
; PPC32-NEXT: li r6, 1 ; PPC32-NEXT: li r6, 1
▲ Show 20 Lines • Show All 137 Lines • ▼ Show 20 Lines
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%val = atomicrmw xchg ptr %mem, i32 %operand acq_rel %val = atomicrmw xchg ptr %mem, i32 %operand acq_rel
ret i32 %val ret i32 %val
} }
define i64 @and_i64_release(ptr %mem, i64 %operand) { define i64 @and_i64_release(ptr %mem, i64 %operand) {
; PPC32-LABEL: and_i64_release: ; PPC32-LABEL: and_i64_release:
; PPC32: # %bb.0: ; PPC32: # %bb.0:
; PPC32-NEXT: mflr r0 ; PPC32-NEXT: mflr r0
; PPC32-NEXT: stw r0, 4(r1)
; PPC32-NEXT: stwu r1, -16(r1) ; PPC32-NEXT: stwu r1, -16(r1)
; PPC32-NEXT: stw r0, 20(r1)
; PPC32-NEXT: .cfi_def_cfa_offset 16 ; PPC32-NEXT: .cfi_def_cfa_offset 16
; PPC32-NEXT: .cfi_offset lr, 4 ; PPC32-NEXT: .cfi_offset lr, 4
; PPC32-NEXT: li r7, 3 ; PPC32-NEXT: li r7, 3
; PPC32-NEXT: bl __atomic_fetch_and_8 ; PPC32-NEXT: bl __atomic_fetch_and_8
; PPC32-NEXT: lwz r0, 20(r1) ; PPC32-NEXT: lwz r0, 20(r1)
; PPC32-NEXT: addi r1, r1, 16 ; PPC32-NEXT: addi r1, r1, 16
; PPC32-NEXT: mtlr r0 ; PPC32-NEXT: mtlr r0
; PPC32-NEXT: blr ; PPC32-NEXT: blr
Show All 15 Lines

llvm/test/CodeGen/PowerPC/branch-on-store-cond.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK ; RUN: -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
; RUN: -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-AIX ; RUN: -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-AIX
define dso_local zeroext i8 @test1(ptr noundef %addr, i8 noundef zeroext %newval) local_unnamed_addr #0 { define dso_local zeroext i8 @test1(ptr noundef %addr, i8 noundef zeroext %newval) local_unnamed_addr #0 {
; CHECK-LABEL: test1: ; CHECK-LABEL: test1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; CHECK-NEXT: std 0, 16(1)
; CHECK-NEXT: stdu 1, -32(1) ; CHECK-NEXT: stdu 1, -32(1)
; CHECK-NEXT: std 0, 48(1)
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: stbcx. 4, 0, 3 ; CHECK-NEXT: stbcx. 4, 0, 3
; CHECK-NEXT: bne 0, .LBB0_2 ; CHECK-NEXT: bne 0, .LBB0_2
; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: # %bb.1: # %if.then
; CHECK-NEXT: bl dummy ; CHECK-NEXT: bl dummy
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: .LBB0_2: # %if.end ; CHECK-NEXT: .LBB0_2: # %if.end
; CHECK-NEXT: li 3, 55 ; CHECK-NEXT: li 3, 55
; CHECK-NEXT: addi 1, 1, 32 ; CHECK-NEXT: addi 1, 1, 32
; CHECK-NEXT: ld 0, 16(1) ; CHECK-NEXT: ld 0, 16(1)
; CHECK-NEXT: mtlr 0 ; CHECK-NEXT: mtlr 0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-AIX-LABEL: test1: ; CHECK-AIX-LABEL: test1:
; CHECK-AIX: # %bb.0: # %entry ; CHECK-AIX: # %bb.0: # %entry
; CHECK-AIX-NEXT: mflr 0 ; CHECK-AIX-NEXT: mflr 0
; CHECK-AIX-NEXT: std 0, 16(1)
; CHECK-AIX-NEXT: stdu 1, -112(1) ; CHECK-AIX-NEXT: stdu 1, -112(1)
; CHECK-AIX-NEXT: std 0, 128(1)
; CHECK-AIX-NEXT: stbcx. 4, 0, 3 ; CHECK-AIX-NEXT: stbcx. 4, 0, 3
; CHECK-AIX-NEXT: bne 0, L..BB0_2 ; CHECK-AIX-NEXT: bne 0, L..BB0_2
; CHECK-AIX-NEXT: # %bb.1: # %if.then ; CHECK-AIX-NEXT: # %bb.1: # %if.then
; CHECK-AIX-NEXT: bl .dummy[PR] ; CHECK-AIX-NEXT: bl .dummy[PR]
; CHECK-AIX-NEXT: nop ; CHECK-AIX-NEXT: nop
; CHECK-AIX-NEXT: L..BB0_2: # %if.end ; CHECK-AIX-NEXT: L..BB0_2: # %if.end
; CHECK-AIX-NEXT: li 3, 55 ; CHECK-AIX-NEXT: li 3, 55
; CHECK-AIX-NEXT: addi 1, 1, 112 ; CHECK-AIX-NEXT: addi 1, 1, 112
Show All 13 Lines
if.end: ; preds = %if.then, %entry if.end: ; preds = %if.then, %entry
ret i8 55 ret i8 55
} }
define dso_local signext i16 @test2(ptr noundef %addr, i16 noundef signext %newval) local_unnamed_addr #0 { define dso_local signext i16 @test2(ptr noundef %addr, i16 noundef signext %newval) local_unnamed_addr #0 {
; CHECK-LABEL: test2: ; CHECK-LABEL: test2:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; CHECK-NEXT: std 0, 16(1)
; CHECK-NEXT: stdu 1, -32(1) ; CHECK-NEXT: stdu 1, -32(1)
; CHECK-NEXT: std 0, 48(1)
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: sthcx. 4, 0, 3 ; CHECK-NEXT: sthcx. 4, 0, 3
; CHECK-NEXT: bne 0, .LBB1_2 ; CHECK-NEXT: bne 0, .LBB1_2
; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: # %bb.1: # %if.then
; CHECK-NEXT: bl dummy ; CHECK-NEXT: bl dummy
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: .LBB1_2: # %if.end ; CHECK-NEXT: .LBB1_2: # %if.end
; CHECK-NEXT: li 3, 55 ; CHECK-NEXT: li 3, 55
; CHECK-NEXT: addi 1, 1, 32 ; CHECK-NEXT: addi 1, 1, 32
; CHECK-NEXT: ld 0, 16(1) ; CHECK-NEXT: ld 0, 16(1)
; CHECK-NEXT: mtlr 0 ; CHECK-NEXT: mtlr 0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-AIX-LABEL: test2: ; CHECK-AIX-LABEL: test2:
; CHECK-AIX: # %bb.0: # %entry ; CHECK-AIX: # %bb.0: # %entry
; CHECK-AIX-NEXT: mflr 0 ; CHECK-AIX-NEXT: mflr 0
; CHECK-AIX-NEXT: std 0, 16(1)
; CHECK-AIX-NEXT: stdu 1, -112(1) ; CHECK-AIX-NEXT: stdu 1, -112(1)
; CHECK-AIX-NEXT: std 0, 128(1)
; CHECK-AIX-NEXT: sthcx. 4, 0, 3 ; CHECK-AIX-NEXT: sthcx. 4, 0, 3
; CHECK-AIX-NEXT: bne 0, L..BB1_2 ; CHECK-AIX-NEXT: bne 0, L..BB1_2
; CHECK-AIX-NEXT: # %bb.1: # %if.then ; CHECK-AIX-NEXT: # %bb.1: # %if.then
; CHECK-AIX-NEXT: bl .dummy[PR] ; CHECK-AIX-NEXT: bl .dummy[PR]
; CHECK-AIX-NEXT: nop ; CHECK-AIX-NEXT: nop
; CHECK-AIX-NEXT: L..BB1_2: # %if.end ; CHECK-AIX-NEXT: L..BB1_2: # %if.end
; CHECK-AIX-NEXT: li 3, 55 ; CHECK-AIX-NEXT: li 3, 55
; CHECK-AIX-NEXT: addi 1, 1, 112 ; CHECK-AIX-NEXT: addi 1, 1, 112
Show All 13 Lines
if.end: ; preds = %if.then, %entry if.end: ; preds = %if.then, %entry
ret i16 55 ret i16 55
} }
define dso_local signext i32 @test3(ptr noundef %addr, i32 noundef signext %newval) local_unnamed_addr #0 { define dso_local signext i32 @test3(ptr noundef %addr, i32 noundef signext %newval) local_unnamed_addr #0 {
; CHECK-LABEL: test3: ; CHECK-LABEL: test3:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; CHECK-NEXT: std 0, 16(1)
; CHECK-NEXT: stdu 1, -32(1) ; CHECK-NEXT: stdu 1, -32(1)
; CHECK-NEXT: std 0, 48(1)
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: stwcx. 4, 0, 3 ; CHECK-NEXT: stwcx. 4, 0, 3
; CHECK-NEXT: bne 0, .LBB2_2 ; CHECK-NEXT: bne 0, .LBB2_2
; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: # %bb.1: # %if.then
; CHECK-NEXT: bl dummy ; CHECK-NEXT: bl dummy
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: .LBB2_2: # %if.end ; CHECK-NEXT: .LBB2_2: # %if.end
; CHECK-NEXT: li 3, 55 ; CHECK-NEXT: li 3, 55
; CHECK-NEXT: addi 1, 1, 32 ; CHECK-NEXT: addi 1, 1, 32
; CHECK-NEXT: ld 0, 16(1) ; CHECK-NEXT: ld 0, 16(1)
; CHECK-NEXT: mtlr 0 ; CHECK-NEXT: mtlr 0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-AIX-LABEL: test3: ; CHECK-AIX-LABEL: test3:
; CHECK-AIX: # %bb.0: # %entry ; CHECK-AIX: # %bb.0: # %entry
; CHECK-AIX-NEXT: mflr 0 ; CHECK-AIX-NEXT: mflr 0
; CHECK-AIX-NEXT: std 0, 16(1)
; CHECK-AIX-NEXT: stdu 1, -112(1) ; CHECK-AIX-NEXT: stdu 1, -112(1)
; CHECK-AIX-NEXT: std 0, 128(1)
; CHECK-AIX-NEXT: stwcx. 4, 0, 3 ; CHECK-AIX-NEXT: stwcx. 4, 0, 3
; CHECK-AIX-NEXT: bne 0, L..BB2_2 ; CHECK-AIX-NEXT: bne 0, L..BB2_2
; CHECK-AIX-NEXT: # %bb.1: # %if.then ; CHECK-AIX-NEXT: # %bb.1: # %if.then
; CHECK-AIX-NEXT: bl .dummy[PR] ; CHECK-AIX-NEXT: bl .dummy[PR]
; CHECK-AIX-NEXT: nop ; CHECK-AIX-NEXT: nop
; CHECK-AIX-NEXT: L..BB2_2: # %if.end ; CHECK-AIX-NEXT: L..BB2_2: # %if.end
; CHECK-AIX-NEXT: li 3, 55 ; CHECK-AIX-NEXT: li 3, 55
; CHECK-AIX-NEXT: addi 1, 1, 112 ; CHECK-AIX-NEXT: addi 1, 1, 112
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if.end: ; preds = %if.then, %entry if.end: ; preds = %if.then, %entry
ret i32 55 ret i32 55
} }
define dso_local i64 @test4(ptr noundef %addr, i64 noundef %newval) local_unnamed_addr #0 { define dso_local i64 @test4(ptr noundef %addr, i64 noundef %newval) local_unnamed_addr #0 {
; CHECK-LABEL: test4: ; CHECK-LABEL: test4:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; CHECK-NEXT: std 0, 16(1)
; CHECK-NEXT: stdu 1, -32(1) ; CHECK-NEXT: stdu 1, -32(1)
; CHECK-NEXT: std 0, 48(1)
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: stdcx. 4, 0, 3 ; CHECK-NEXT: stdcx. 4, 0, 3
; CHECK-NEXT: bne 0, .LBB3_2 ; CHECK-NEXT: bne 0, .LBB3_2
; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: # %bb.1: # %if.then
; CHECK-NEXT: bl dummy ; CHECK-NEXT: bl dummy
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: .LBB3_2: # %if.end ; CHECK-NEXT: .LBB3_2: # %if.end
; CHECK-NEXT: li 3, 55 ; CHECK-NEXT: li 3, 55
; CHECK-NEXT: addi 1, 1, 32 ; CHECK-NEXT: addi 1, 1, 32
; CHECK-NEXT: ld 0, 16(1) ; CHECK-NEXT: ld 0, 16(1)
; CHECK-NEXT: mtlr 0 ; CHECK-NEXT: mtlr 0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-AIX-LABEL: test4: ; CHECK-AIX-LABEL: test4:
; CHECK-AIX: # %bb.0: # %entry ; CHECK-AIX: # %bb.0: # %entry
; CHECK-AIX-NEXT: mflr 0 ; CHECK-AIX-NEXT: mflr 0
; CHECK-AIX-NEXT: std 0, 16(1)
; CHECK-AIX-NEXT: stdu 1, -112(1) ; CHECK-AIX-NEXT: stdu 1, -112(1)
; CHECK-AIX-NEXT: std 0, 128(1)
; CHECK-AIX-NEXT: stdcx. 4, 0, 3 ; CHECK-AIX-NEXT: stdcx. 4, 0, 3
; CHECK-AIX-NEXT: bne 0, L..BB3_2 ; CHECK-AIX-NEXT: bne 0, L..BB3_2
; CHECK-AIX-NEXT: # %bb.1: # %if.then ; CHECK-AIX-NEXT: # %bb.1: # %if.then
; CHECK-AIX-NEXT: bl .dummy[PR] ; CHECK-AIX-NEXT: bl .dummy[PR]
; CHECK-AIX-NEXT: nop ; CHECK-AIX-NEXT: nop
; CHECK-AIX-NEXT: L..BB3_2: # %if.end ; CHECK-AIX-NEXT: L..BB3_2: # %if.end
; CHECK-AIX-NEXT: li 3, 55 ; CHECK-AIX-NEXT: li 3, 55
; CHECK-AIX-NEXT: addi 1, 1, 112 ; CHECK-AIX-NEXT: addi 1, 1, 112
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llvm/test/CodeGen/PowerPC/byval.ll

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declare dso_local void @foo(ptr %var) declare dso_local void @foo(ptr %var)
; check that 36bytes byval parameter is passed all in registers. ; check that 36bytes byval parameter is passed all in registers.
define dso_local i32 @bar() { define dso_local i32 @bar() {
; CHECK-LABEL: bar: ; CHECK-LABEL: bar:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; CHECK-NEXT: std 0, 16(1)
; CHECK-NEXT: stdu 1, -80(1) ; CHECK-NEXT: stdu 1, -80(1)
; CHECK-NEXT: std 0, 96(1)
; CHECK-NEXT: .cfi_def_cfa_offset 80 ; CHECK-NEXT: .cfi_def_cfa_offset 80
; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: addi 3, 1, 40 ; CHECK-NEXT: addi 3, 1, 40
; CHECK-NEXT: bl foo ; CHECK-NEXT: bl foo
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: lwz 7, 72(1) ; CHECK-NEXT: lwz 7, 72(1)
; CHECK-NEXT: ld 6, 64(1) ; CHECK-NEXT: ld 6, 64(1)
; CHECK-NEXT: ld 5, 56(1) ; CHECK-NEXT: ld 5, 56(1)
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llvm/test/CodeGen/PowerPC/canonical-merge-shuffles.ll

Show First 20 Lines • Show All 553 Lines • ▼ Show 20 Linesentry:
ret <8 x i16> %1 ret <8 x i16> %1
} }
define dso_local void @no_crash_elt0_from_RHS(ptr noalias nocapture dereferenceable(16) %.vtx6) #0 { define dso_local void @no_crash_elt0_from_RHS(ptr noalias nocapture dereferenceable(16) %.vtx6) #0 {
; CHECK-P8-LABEL: no_crash_elt0_from_RHS: ; CHECK-P8-LABEL: no_crash_elt0_from_RHS:
; CHECK-P8: # %bb.0: # %test_entry ; CHECK-P8: # %bb.0: # %test_entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: bl dummy ; CHECK-P8-NEXT: bl dummy
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: xxlxor f0, f0, f0 ; CHECK-P8-NEXT: xxlxor f0, f0, f0
; CHECK-P8-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; CHECK-P8-NEXT: # kill: def $f1 killed $f1 def $vsl1
; CHECK-P8-NEXT: xxmrghd vs0, vs1, vs0 ; CHECK-P8-NEXT: xxmrghd vs0, vs1, vs0
; CHECK-P8-NEXT: xxswapd vs0, vs0 ; CHECK-P8-NEXT: xxswapd vs0, vs0
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; ;
; CHECK-P9-LABEL: no_crash_elt0_from_RHS: ; CHECK-P9-LABEL: no_crash_elt0_from_RHS:
; CHECK-P9: # %bb.0: # %test_entry ; CHECK-P9: # %bb.0: # %test_entry
; CHECK-P9-NEXT: mflr r0 ; CHECK-P9-NEXT: mflr r0
; CHECK-P9-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P9-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P9-NEXT: std r0, 16(r1)
; CHECK-P9-NEXT: stdu r1, -48(r1) ; CHECK-P9-NEXT: stdu r1, -48(r1)
; CHECK-P9-NEXT: std r0, 64(r1)
; CHECK-P9-NEXT: mr r30, r3 ; CHECK-P9-NEXT: mr r30, r3
; CHECK-P9-NEXT: bl dummy ; CHECK-P9-NEXT: bl dummy
; CHECK-P9-NEXT: nop ; CHECK-P9-NEXT: nop
; CHECK-P9-NEXT: xxlxor f0, f0, f0 ; CHECK-P9-NEXT: xxlxor f0, f0, f0
; CHECK-P9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; CHECK-P9-NEXT: # kill: def $f1 killed $f1 def $vsl1
; CHECK-P9-NEXT: xxmrghd vs0, vs1, vs0 ; CHECK-P9-NEXT: xxmrghd vs0, vs1, vs0
; CHECK-P9-NEXT: stxv vs0, 0(r30) ; CHECK-P9-NEXT: stxv vs0, 0(r30)
; ;
; CHECK-P9-BE-LABEL: no_crash_elt0_from_RHS: ; CHECK-P9-BE-LABEL: no_crash_elt0_from_RHS:
; CHECK-P9-BE: # %bb.0: # %test_entry ; CHECK-P9-BE: # %bb.0: # %test_entry
; CHECK-P9-BE-NEXT: mflr r0 ; CHECK-P9-BE-NEXT: mflr r0
; CHECK-P9-BE-NEXT: std r0, 16(r1)
; CHECK-P9-BE-NEXT: stdu r1, -128(r1) ; CHECK-P9-BE-NEXT: stdu r1, -128(r1)
; CHECK-P9-BE-NEXT: std r0, 144(r1)
; CHECK-P9-BE-NEXT: std r30, 112(r1) # 8-byte Folded Spill ; CHECK-P9-BE-NEXT: std r30, 112(r1) # 8-byte Folded Spill
; CHECK-P9-BE-NEXT: mr r30, r3 ; CHECK-P9-BE-NEXT: mr r30, r3
; CHECK-P9-BE-NEXT: bl dummy ; CHECK-P9-BE-NEXT: bl dummy
; CHECK-P9-BE-NEXT: nop ; CHECK-P9-BE-NEXT: nop
; CHECK-P9-BE-NEXT: xxlxor f0, f0, f0 ; CHECK-P9-BE-NEXT: xxlxor f0, f0, f0
; CHECK-P9-BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; CHECK-P9-BE-NEXT: # kill: def $f1 killed $f1 def $vsl1
; CHECK-P9-BE-NEXT: xxmrghd vs0, vs0, vs1 ; CHECK-P9-BE-NEXT: xxmrghd vs0, vs0, vs1
; CHECK-P9-BE-NEXT: stxv vs0, 0(r30) ; CHECK-P9-BE-NEXT: stxv vs0, 0(r30)
; ;
; CHECK-NOVSX-LABEL: no_crash_elt0_from_RHS: ; CHECK-NOVSX-LABEL: no_crash_elt0_from_RHS:
; CHECK-NOVSX: # %bb.0: # %test_entry ; CHECK-NOVSX: # %bb.0: # %test_entry
; CHECK-NOVSX-NEXT: mflr r0 ; CHECK-NOVSX-NEXT: mflr r0
; CHECK-NOVSX-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-NOVSX-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-NOVSX-NEXT: std r0, 16(r1)
; CHECK-NOVSX-NEXT: stdu r1, -48(r1) ; CHECK-NOVSX-NEXT: stdu r1, -48(r1)
; CHECK-NOVSX-NEXT: std r0, 64(r1)
; CHECK-NOVSX-NEXT: mr r30, r3 ; CHECK-NOVSX-NEXT: mr r30, r3
; CHECK-NOVSX-NEXT: bl dummy ; CHECK-NOVSX-NEXT: bl dummy
; CHECK-NOVSX-NEXT: nop ; CHECK-NOVSX-NEXT: nop
; CHECK-NOVSX-NEXT: li r3, 0 ; CHECK-NOVSX-NEXT: li r3, 0
; CHECK-NOVSX-NEXT: stfd f1, 8(r30) ; CHECK-NOVSX-NEXT: stfd f1, 8(r30)
; CHECK-NOVSX-NEXT: std r3, 0(r30) ; CHECK-NOVSX-NEXT: std r3, 0(r30)
; ;
; CHECK-P7-LABEL: no_crash_elt0_from_RHS: ; CHECK-P7-LABEL: no_crash_elt0_from_RHS:
; CHECK-P7: # %bb.0: # %test_entry ; CHECK-P7: # %bb.0: # %test_entry
; CHECK-P7-NEXT: mflr r0 ; CHECK-P7-NEXT: mflr r0
; CHECK-P7-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P7-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P7-NEXT: std r0, 16(r1)
; CHECK-P7-NEXT: stdu r1, -48(r1) ; CHECK-P7-NEXT: stdu r1, -48(r1)
; CHECK-P7-NEXT: std r0, 64(r1)
; CHECK-P7-NEXT: mr r30, r3 ; CHECK-P7-NEXT: mr r30, r3
; CHECK-P7-NEXT: bl dummy ; CHECK-P7-NEXT: bl dummy
; CHECK-P7-NEXT: nop ; CHECK-P7-NEXT: nop
; CHECK-P7-NEXT: xxlxor f0, f0, f0 ; CHECK-P7-NEXT: xxlxor f0, f0, f0
; CHECK-P7-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; CHECK-P7-NEXT: # kill: def $f1 killed $f1 def $vsl1
; CHECK-P7-NEXT: xxmrghd vs0, vs1, vs0 ; CHECK-P7-NEXT: xxmrghd vs0, vs1, vs0
; CHECK-P7-NEXT: xxswapd vs0, vs0 ; CHECK-P7-NEXT: xxswapd vs0, vs0
; CHECK-P7-NEXT: stxvd2x vs0, 0, r30 ; CHECK-P7-NEXT: stxvd2x vs0, 0, r30
; ;
; P8-AIX-64-LABEL: no_crash_elt0_from_RHS: ; P8-AIX-64-LABEL: no_crash_elt0_from_RHS:
; P8-AIX-64: # %bb.0: # %test_entry ; P8-AIX-64: # %bb.0: # %test_entry
; P8-AIX-64-NEXT: mflr r0 ; P8-AIX-64-NEXT: mflr r0
; P8-AIX-64-NEXT: std r0, 16(r1)
; P8-AIX-64-NEXT: stdu r1, -128(r1) ; P8-AIX-64-NEXT: stdu r1, -128(r1)
; P8-AIX-64-NEXT: std r0, 144(r1)
; P8-AIX-64-NEXT: std r31, 120(r1) # 8-byte Folded Spill ; P8-AIX-64-NEXT: std r31, 120(r1) # 8-byte Folded Spill
; P8-AIX-64-NEXT: mr r31, r3 ; P8-AIX-64-NEXT: mr r31, r3
; P8-AIX-64-NEXT: bl .dummy[PR] ; P8-AIX-64-NEXT: bl .dummy[PR]
; P8-AIX-64-NEXT: nop ; P8-AIX-64-NEXT: nop
; P8-AIX-64-NEXT: xxlxor f0, f0, f0 ; P8-AIX-64-NEXT: xxlxor f0, f0, f0
; P8-AIX-64-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; P8-AIX-64-NEXT: # kill: def $f1 killed $f1 def $vsl1
; P8-AIX-64-NEXT: xxmrghd vs0, vs0, vs1 ; P8-AIX-64-NEXT: xxmrghd vs0, vs0, vs1
; P8-AIX-64-NEXT: stxvd2x vs0, 0, r31 ; P8-AIX-64-NEXT: stxvd2x vs0, 0, r31
; ;
; P8-AIX-32-LABEL: no_crash_elt0_from_RHS: ; P8-AIX-32-LABEL: no_crash_elt0_from_RHS:
; P8-AIX-32: # %bb.0: # %test_entry ; P8-AIX-32: # %bb.0: # %test_entry
; P8-AIX-32-NEXT: mflr r0 ; P8-AIX-32-NEXT: mflr r0
; P8-AIX-32-NEXT: stw r0, 8(r1)
; P8-AIX-32-NEXT: stwu r1, -64(r1) ; P8-AIX-32-NEXT: stwu r1, -64(r1)
; P8-AIX-32-NEXT: stw r0, 72(r1)
; P8-AIX-32-NEXT: stw r31, 60(r1) # 4-byte Folded Spill ; P8-AIX-32-NEXT: stw r31, 60(r1) # 4-byte Folded Spill
; P8-AIX-32-NEXT: mr r31, r3 ; P8-AIX-32-NEXT: mr r31, r3
; P8-AIX-32-NEXT: bl .dummy[PR] ; P8-AIX-32-NEXT: bl .dummy[PR]
; P8-AIX-32-NEXT: nop ; P8-AIX-32-NEXT: nop
; P8-AIX-32-NEXT: xxlxor f0, f0, f0 ; P8-AIX-32-NEXT: xxlxor f0, f0, f0
; P8-AIX-32-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; P8-AIX-32-NEXT: # kill: def $f1 killed $f1 def $vsl1
; P8-AIX-32-NEXT: xxmrghd vs0, vs0, vs1 ; P8-AIX-32-NEXT: xxmrghd vs0, vs0, vs1
; P8-AIX-32-NEXT: stxvd2x vs0, 0, r31 ; P8-AIX-32-NEXT: stxvd2x vs0, 0, r31
▲ Show 20 Lines • Show All 563 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/constant-pool.ll

Show First 20 Lines • Show All 383 Lines • ▼ Show 20 Lines
; CHECK-NEXT: addi r1, r1, 48 ; CHECK-NEXT: addi r1, r1, 48
; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: ld r0, 16(r1)
; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: mtlr r0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P9-LABEL: three_constants_ppcf128: ; CHECK-P9-LABEL: three_constants_ppcf128:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mflr r0 ; CHECK-P9-NEXT: mflr r0
; CHECK-P9-NEXT: std r0, 16(r1)
; CHECK-P9-NEXT: stdu r1, -32(r1) ; CHECK-P9-NEXT: stdu r1, -32(r1)
; CHECK-P9-NEXT: std r0, 48(r1)
; CHECK-P9-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P9-NEXT: .cfi_def_cfa_offset 32
; CHECK-P9-NEXT: .cfi_offset lr, 16 ; CHECK-P9-NEXT: .cfi_offset lr, 16
; CHECK-P9-NEXT: addis r3, r2, .LCPI16_0@toc@ha ; CHECK-P9-NEXT: addis r3, r2, .LCPI16_0@toc@ha
; CHECK-P9-NEXT: xxlxor f4, f4, f4 ; CHECK-P9-NEXT: xxlxor f4, f4, f4
; CHECK-P9-NEXT: lfd f3, .LCPI16_0@toc@l(r3) ; CHECK-P9-NEXT: lfd f3, .LCPI16_0@toc@l(r3)
; CHECK-P9-NEXT: bl __gcc_qadd ; CHECK-P9-NEXT: bl __gcc_qadd
; CHECK-P9-NEXT: nop ; CHECK-P9-NEXT: nop
; CHECK-P9-NEXT: addis r3, r2, .LCPI16_1@toc@ha ; CHECK-P9-NEXT: addis r3, r2, .LCPI16_1@toc@ha
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llvm/test/CodeGen/PowerPC/csr-split.ll

Show All 10 Lines
define dso_local signext i32 @test1(ptr %b) local_unnamed_addr { define dso_local signext i32 @test1(ptr %b) local_unnamed_addr {
; CHECK-PWR9-LABEL: test1: ; CHECK-PWR9-LABEL: test1:
; CHECK-PWR9: # %bb.0: # %entry ; CHECK-PWR9: # %bb.0: # %entry
; CHECK-PWR9-NEXT: mflr r0 ; CHECK-PWR9-NEXT: mflr r0
; CHECK-PWR9-NEXT: .cfi_def_cfa_offset 48 ; CHECK-PWR9-NEXT: .cfi_def_cfa_offset 48
; CHECK-PWR9-NEXT: .cfi_offset lr, 16 ; CHECK-PWR9-NEXT: .cfi_offset lr, 16
; CHECK-PWR9-NEXT: .cfi_offset r30, -16 ; CHECK-PWR9-NEXT: .cfi_offset r30, -16
; CHECK-PWR9-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-PWR9-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-PWR9-NEXT: std r0, 16(r1)
; CHECK-PWR9-NEXT: stdu r1, -48(r1) ; CHECK-PWR9-NEXT: stdu r1, -48(r1)
; CHECK-PWR9-NEXT: mr r30, r3 ; CHECK-PWR9-NEXT: mr r30, r3
; CHECK-PWR9-NEXT: addis r3, r2, a@toc@ha ; CHECK-PWR9-NEXT: addis r3, r2, a@toc@ha
; CHECK-PWR9-NEXT: std r0, 64(r1)
; CHECK-PWR9-NEXT: lwa r3, a@toc@l(r3) ; CHECK-PWR9-NEXT: lwa r3, a@toc@l(r3)
; CHECK-PWR9-NEXT: cmpld r3, r30 ; CHECK-PWR9-NEXT: cmpld r3, r30
; CHECK-PWR9-NEXT: # implicit-def: $r3 ; CHECK-PWR9-NEXT: # implicit-def: $r3
; CHECK-PWR9-NEXT: bne cr0, .LBB0_2 ; CHECK-PWR9-NEXT: bne cr0, .LBB0_2
; CHECK-PWR9-NEXT: # %bb.1: # %if.then ; CHECK-PWR9-NEXT: # %bb.1: # %if.then
; CHECK-PWR9-NEXT: bl callVoid ; CHECK-PWR9-NEXT: bl callVoid
; CHECK-PWR9-NEXT: nop ; CHECK-PWR9-NEXT: nop
; CHECK-PWR9-NEXT: mr r3, r30 ; CHECK-PWR9-NEXT: mr r3, r30
; CHECK-PWR9-NEXT: bl callNonVoid ; CHECK-PWR9-NEXT: bl callNonVoid
; CHECK-PWR9-NEXT: nop ; CHECK-PWR9-NEXT: nop
; CHECK-PWR9-NEXT: .LBB0_2: # %if.end ; CHECK-PWR9-NEXT: .LBB0_2: # %if.end
; CHECK-PWR9-NEXT: extsw r3, r3 ; CHECK-PWR9-NEXT: extsw r3, r3
; CHECK-PWR9-NEXT: addi r1, r1, 48 ; CHECK-PWR9-NEXT: addi r1, r1, 48
; CHECK-PWR9-NEXT: ld r0, 16(r1) ; CHECK-PWR9-NEXT: ld r0, 16(r1)
; CHECK-PWR9-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-PWR9-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: mtlr r0 ; CHECK-PWR9-NEXT: mtlr r0
; CHECK-PWR9-NEXT: blr ; CHECK-PWR9-NEXT: blr
; ;
; CHECK-LABEL: test1: ; CHECK-LABEL: test1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr r0 ; CHECK-NEXT: mflr r0
; CHECK-NEXT: std r0, 16(r1)
; CHECK-NEXT: stdu r1, -128(r1) ; CHECK-NEXT: stdu r1, -128(r1)
; CHECK-NEXT: std r0, 144(r1)
; CHECK-NEXT: .cfi_def_cfa_offset 128 ; CHECK-NEXT: .cfi_def_cfa_offset 128
; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: .cfi_offset r30, -16 ; CHECK-NEXT: .cfi_offset r30, -16
; CHECK-NEXT: addis r4, r2, a@toc@ha ; CHECK-NEXT: addis r4, r2, a@toc@ha
; CHECK-NEXT: std r30, 112(r1) # 8-byte Folded Spill ; CHECK-NEXT: std r30, 112(r1) # 8-byte Folded Spill
; CHECK-NEXT: mr r30, r3 ; CHECK-NEXT: mr r30, r3
; CHECK-NEXT: lwa r4, a@toc@l(r4) ; CHECK-NEXT: lwa r4, a@toc@l(r4)
; CHECK-NEXT: cmpld r4, r3 ; CHECK-NEXT: cmpld r4, r3
Show All 36 Lines
define dso_local signext i32 @test2(ptr %p1) local_unnamed_addr { define dso_local signext i32 @test2(ptr %p1) local_unnamed_addr {
; CHECK-PWR9-LABEL: test2: ; CHECK-PWR9-LABEL: test2:
; CHECK-PWR9: # %bb.0: # %entry ; CHECK-PWR9: # %bb.0: # %entry
; CHECK-PWR9-NEXT: mflr r0 ; CHECK-PWR9-NEXT: mflr r0
; CHECK-PWR9-NEXT: .cfi_def_cfa_offset 48 ; CHECK-PWR9-NEXT: .cfi_def_cfa_offset 48
; CHECK-PWR9-NEXT: .cfi_offset lr, 16 ; CHECK-PWR9-NEXT: .cfi_offset lr, 16
; CHECK-PWR9-NEXT: .cfi_offset r30, -16 ; CHECK-PWR9-NEXT: .cfi_offset r30, -16
; CHECK-PWR9-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-PWR9-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-PWR9-NEXT: std r0, 16(r1)
; CHECK-PWR9-NEXT: stdu r1, -48(r1) ; CHECK-PWR9-NEXT: stdu r1, -48(r1)
; CHECK-PWR9-NEXT: mr r30, r3 ; CHECK-PWR9-NEXT: mr r30, r3
; CHECK-PWR9-NEXT: li r3, 0 ; CHECK-PWR9-NEXT: li r3, 0
; CHECK-PWR9-NEXT: std r0, 64(r1)
; CHECK-PWR9-NEXT: cmpldi r30, 0 ; CHECK-PWR9-NEXT: cmpldi r30, 0
; CHECK-PWR9-NEXT: beq cr0, .LBB1_3 ; CHECK-PWR9-NEXT: beq cr0, .LBB1_3
; CHECK-PWR9-NEXT: # %bb.1: # %if.end ; CHECK-PWR9-NEXT: # %bb.1: # %if.end
; CHECK-PWR9-NEXT: addis r4, r2, a@toc@ha ; CHECK-PWR9-NEXT: addis r4, r2, a@toc@ha
; CHECK-PWR9-NEXT: lwa r4, a@toc@l(r4) ; CHECK-PWR9-NEXT: lwa r4, a@toc@l(r4)
; CHECK-PWR9-NEXT: cmpld r4, r30 ; CHECK-PWR9-NEXT: cmpld r4, r30
; CHECK-PWR9-NEXT: bne cr0, .LBB1_3 ; CHECK-PWR9-NEXT: bne cr0, .LBB1_3
; CHECK-PWR9-NEXT: # %bb.2: # %if.then2 ; CHECK-PWR9-NEXT: # %bb.2: # %if.then2
; CHECK-PWR9-NEXT: bl callVoid ; CHECK-PWR9-NEXT: bl callVoid
; CHECK-PWR9-NEXT: nop ; CHECK-PWR9-NEXT: nop
; CHECK-PWR9-NEXT: mr r3, r30 ; CHECK-PWR9-NEXT: mr r3, r30
; CHECK-PWR9-NEXT: bl callNonVoid ; CHECK-PWR9-NEXT: bl callNonVoid
; CHECK-PWR9-NEXT: nop ; CHECK-PWR9-NEXT: nop
; CHECK-PWR9-NEXT: .LBB1_3: # %return ; CHECK-PWR9-NEXT: .LBB1_3: # %return
; CHECK-PWR9-NEXT: addi r1, r1, 48 ; CHECK-PWR9-NEXT: addi r1, r1, 48
; CHECK-PWR9-NEXT: ld r0, 16(r1) ; CHECK-PWR9-NEXT: ld r0, 16(r1)
; CHECK-PWR9-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-PWR9-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: mtlr r0 ; CHECK-PWR9-NEXT: mtlr r0
; CHECK-PWR9-NEXT: blr ; CHECK-PWR9-NEXT: blr
; ;
; CHECK-LABEL: test2: ; CHECK-LABEL: test2:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr r0 ; CHECK-NEXT: mflr r0
; CHECK-NEXT: std r0, 16(r1)
; CHECK-NEXT: stdu r1, -128(r1) ; CHECK-NEXT: stdu r1, -128(r1)
; CHECK-NEXT: std r0, 144(r1)
; CHECK-NEXT: .cfi_def_cfa_offset 128 ; CHECK-NEXT: .cfi_def_cfa_offset 128
; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: .cfi_offset r30, -16 ; CHECK-NEXT: .cfi_offset r30, -16
; CHECK-NEXT: std r30, 112(r1) # 8-byte Folded Spill ; CHECK-NEXT: std r30, 112(r1) # 8-byte Folded Spill
; CHECK-NEXT: mr r30, r3 ; CHECK-NEXT: mr r30, r3
; CHECK-NEXT: cmpldi r3, 0 ; CHECK-NEXT: cmpldi r3, 0
; CHECK-NEXT: li r3, 0 ; CHECK-NEXT: li r3, 0
; CHECK-NEXT: beq cr0, .LBB1_3 ; CHECK-NEXT: beq cr0, .LBB1_3
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; CHECK-PWR9: # %bb.0: # %entry ; CHECK-PWR9: # %bb.0: # %entry
; CHECK-PWR9-NEXT: mflr r0 ; CHECK-PWR9-NEXT: mflr r0
; CHECK-PWR9-NEXT: .cfi_def_cfa_offset 64 ; CHECK-PWR9-NEXT: .cfi_def_cfa_offset 64
; CHECK-PWR9-NEXT: .cfi_offset lr, 16 ; CHECK-PWR9-NEXT: .cfi_offset lr, 16
; CHECK-PWR9-NEXT: .cfi_offset r29, -24 ; CHECK-PWR9-NEXT: .cfi_offset r29, -24
; CHECK-PWR9-NEXT: .cfi_offset r30, -16 ; CHECK-PWR9-NEXT: .cfi_offset r30, -16
; CHECK-PWR9-NEXT: std r29, -24(r1) # 8-byte Folded Spill ; CHECK-PWR9-NEXT: std r29, -24(r1) # 8-byte Folded Spill
; CHECK-PWR9-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-PWR9-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-PWR9-NEXT: std r0, 16(r1)
; CHECK-PWR9-NEXT: stdu r1, -64(r1) ; CHECK-PWR9-NEXT: stdu r1, -64(r1)
; CHECK-PWR9-NEXT: std r0, 80(r1)
; CHECK-PWR9-NEXT: ld r30, 0(r3) ; CHECK-PWR9-NEXT: ld r30, 0(r3)
; CHECK-PWR9-NEXT: cmpldi r30, 0 ; CHECK-PWR9-NEXT: cmpldi r30, 0
; CHECK-PWR9-NEXT: beq cr0, .LBB2_2 ; CHECK-PWR9-NEXT: beq cr0, .LBB2_2
; CHECK-PWR9-NEXT: # %bb.1: # %land.rhs ; CHECK-PWR9-NEXT: # %bb.1: # %land.rhs
; CHECK-PWR9-NEXT: mr r29, r3 ; CHECK-PWR9-NEXT: mr r29, r3
; CHECK-PWR9-NEXT: mr r3, r30 ; CHECK-PWR9-NEXT: mr r3, r30
; CHECK-PWR9-NEXT: bl bar ; CHECK-PWR9-NEXT: bl bar
; CHECK-PWR9-NEXT: nop ; CHECK-PWR9-NEXT: nop
; CHECK-PWR9-NEXT: std r3, 0(r29) ; CHECK-PWR9-NEXT: std r3, 0(r29)
; CHECK-PWR9-NEXT: .LBB2_2: # %land.end ; CHECK-PWR9-NEXT: .LBB2_2: # %land.end
; CHECK-PWR9-NEXT: mr r3, r30 ; CHECK-PWR9-NEXT: mr r3, r30
; CHECK-PWR9-NEXT: addi r1, r1, 64 ; CHECK-PWR9-NEXT: addi r1, r1, 64
; CHECK-PWR9-NEXT: ld r0, 16(r1) ; CHECK-PWR9-NEXT: ld r0, 16(r1)
; CHECK-PWR9-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-PWR9-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: ld r29, -24(r1) # 8-byte Folded Reload ; CHECK-PWR9-NEXT: ld r29, -24(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: mtlr r0 ; CHECK-PWR9-NEXT: mtlr r0
; CHECK-PWR9-NEXT: blr ; CHECK-PWR9-NEXT: blr
; ;
; CHECK-LABEL: test3: ; CHECK-LABEL: test3:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr r0 ; CHECK-NEXT: mflr r0
; CHECK-NEXT: std r0, 16(r1)
; CHECK-NEXT: stdu r1, -144(r1) ; CHECK-NEXT: stdu r1, -144(r1)
; CHECK-NEXT: std r0, 160(r1)
; CHECK-NEXT: .cfi_def_cfa_offset 144 ; CHECK-NEXT: .cfi_def_cfa_offset 144
; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: .cfi_offset r29, -24 ; CHECK-NEXT: .cfi_offset r29, -24
; CHECK-NEXT: .cfi_offset r30, -16 ; CHECK-NEXT: .cfi_offset r30, -16
; CHECK-NEXT: std r30, 128(r1) # 8-byte Folded Spill ; CHECK-NEXT: std r30, 128(r1) # 8-byte Folded Spill
; CHECK-NEXT: ld r30, 0(r3) ; CHECK-NEXT: ld r30, 0(r3)
; CHECK-NEXT: std r29, 120(r1) # 8-byte Folded Spill ; CHECK-NEXT: std r29, 120(r1) # 8-byte Folded Spill
; CHECK-NEXT: cmpldi r30, 0 ; CHECK-NEXT: cmpldi r30, 0
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llvm/test/CodeGen/PowerPC/ctrloop-constrained-fp.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple powerpc64le < %s | FileCheck %s ; RUN: llc -mtriple powerpc64le < %s | FileCheck %s
; Check constrained ops converted to call ; Check constrained ops converted to call
define void @test(ptr %cast) { define void @test(ptr %cast) {
; CHECK-LABEL: test: ; CHECK-LABEL: test:
; CHECK: # %bb.0: # %root ; CHECK: # %bb.0: # %root
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; CHECK-NEXT: .cfi_def_cfa_offset 64 ; CHECK-NEXT: .cfi_def_cfa_offset 64
; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: .cfi_offset r29, -24 ; CHECK-NEXT: .cfi_offset r29, -24
; CHECK-NEXT: .cfi_offset r30, -16 ; CHECK-NEXT: .cfi_offset r30, -16
; CHECK-NEXT: std 29, -24(1) # 8-byte Folded Spill ; CHECK-NEXT: std 29, -24(1) # 8-byte Folded Spill
; CHECK-NEXT: std 30, -16(1) # 8-byte Folded Spill ; CHECK-NEXT: std 30, -16(1) # 8-byte Folded Spill
; CHECK-NEXT: std 0, 16(1)
; CHECK-NEXT: stdu 1, -64(1) ; CHECK-NEXT: stdu 1, -64(1)
; CHECK-NEXT: li 30, 0 ; CHECK-NEXT: li 30, 0
; CHECK-NEXT: addi 29, 3, -8 ; CHECK-NEXT: addi 29, 3, -8
; CHECK-NEXT: std 0, 80(1)
; CHECK-NEXT: .p2align 5 ; CHECK-NEXT: .p2align 5
; CHECK-NEXT: .LBB0_1: # %for.body ; CHECK-NEXT: .LBB0_1: # %for.body
; CHECK-NEXT: # ; CHECK-NEXT: #
; CHECK-NEXT: lfdu 1, 8(29) ; CHECK-NEXT: lfdu 1, 8(29)
; CHECK-NEXT: bl cos ; CHECK-NEXT: bl cos
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: addi 30, 30, 8 ; CHECK-NEXT: addi 30, 30, 8
; CHECK-NEXT: stfd 1, 0(29) ; CHECK-NEXT: stfd 1, 0(29)
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llvm/test/CodeGen/PowerPC/ctrloop-fp128.ll

Show All 30 Lines
; PWR9-NEXT: addi 3, 3, 16 ; PWR9-NEXT: addi 3, 3, 16
; PWR9-NEXT: bne 0, .LBB0_1 ; PWR9-NEXT: bne 0, .LBB0_1
; PWR9-NEXT: # %bb.2: # %for.end ; PWR9-NEXT: # %bb.2: # %for.end
; PWR9-NEXT: blr ; PWR9-NEXT: blr
; ;
; PWR8-LABEL: fmul_ctrloop_fp128: ; PWR8-LABEL: fmul_ctrloop_fp128:
; PWR8: # %bb.0: # %entry ; PWR8: # %bb.0: # %entry
; PWR8-NEXT: mflr 0 ; PWR8-NEXT: mflr 0
; PWR8-NEXT: std 0, 16(1)
; PWR8-NEXT: stdu 1, -112(1) ; PWR8-NEXT: stdu 1, -112(1)
; PWR8-NEXT: li 3, 48 ; PWR8-NEXT: li 3, 48
; PWR8-NEXT: std 0, 128(1)
; PWR8-NEXT: addis 4, 2, x@toc@ha ; PWR8-NEXT: addis 4, 2, x@toc@ha
; PWR8-NEXT: std 28, 80(1) # 8-byte Folded Spill ; PWR8-NEXT: std 28, 80(1) # 8-byte Folded Spill
; PWR8-NEXT: std 29, 88(1) # 8-byte Folded Spill ; PWR8-NEXT: std 29, 88(1) # 8-byte Folded Spill
; PWR8-NEXT: std 30, 96(1) # 8-byte Folded Spill ; PWR8-NEXT: std 30, 96(1) # 8-byte Folded Spill
; PWR8-NEXT: li 30, 0 ; PWR8-NEXT: li 30, 0
; PWR8-NEXT: li 29, 16
; PWR8-NEXT: addi 4, 4, x@toc@l ; PWR8-NEXT: addi 4, 4, x@toc@l
; PWR8-NEXT: std 26, 64(1) # 8-byte Folded Spill ; PWR8-NEXT: li 29, 16
; PWR8-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill ; PWR8-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill
; PWR8-NEXT: addis 3, 2, a@toc@ha ; PWR8-NEXT: addis 3, 2, a@toc@ha
; PWR8-NEXT: std 26, 64(1) # 8-byte Folded Spill
; PWR8-NEXT: std 27, 72(1) # 8-byte Folded Spill ; PWR8-NEXT: std 27, 72(1) # 8-byte Folded Spill
; PWR8-NEXT: addi 3, 3, a@toc@l ; PWR8-NEXT: addi 3, 3, a@toc@l
; PWR8-NEXT: lxvd2x 0, 0, 3 ; PWR8-NEXT: lxvd2x 0, 0, 3
; PWR8-NEXT: addis 3, 2, y@toc@ha ; PWR8-NEXT: addis 3, 2, y@toc@ha
; PWR8-NEXT: addi 3, 3, y@toc@l ; PWR8-NEXT: addi 3, 3, y@toc@l
; PWR8-NEXT: addi 28, 3, -16 ; PWR8-NEXT: addi 28, 3, -16
; PWR8-NEXT: addi 3, 4, -16 ; PWR8-NEXT: addi 3, 4, -16
; PWR8-NEXT: xxswapd 63, 0 ; PWR8-NEXT: xxswapd 63, 0
▲ Show 20 Lines • Show All 68 Lines • ▼ Show 20 Lines
; PWR9-NEXT: blr ; PWR9-NEXT: blr
; ;
; PWR8-LABEL: fpext_ctrloop_fp128: ; PWR8-LABEL: fpext_ctrloop_fp128:
; PWR8: # %bb.0: # %entry ; PWR8: # %bb.0: # %entry
; PWR8-NEXT: mflr 0 ; PWR8-NEXT: mflr 0
; PWR8-NEXT: std 28, -32(1) # 8-byte Folded Spill ; PWR8-NEXT: std 28, -32(1) # 8-byte Folded Spill
; PWR8-NEXT: std 29, -24(1) # 8-byte Folded Spill ; PWR8-NEXT: std 29, -24(1) # 8-byte Folded Spill
; PWR8-NEXT: std 30, -16(1) # 8-byte Folded Spill ; PWR8-NEXT: std 30, -16(1) # 8-byte Folded Spill
; PWR8-NEXT: std 0, 16(1)
; PWR8-NEXT: stdu 1, -64(1) ; PWR8-NEXT: stdu 1, -64(1)
; PWR8-NEXT: addis 4, 2, y@toc@ha ; PWR8-NEXT: addis 4, 2, y@toc@ha
; PWR8-NEXT: addi 30, 3, -8 ; PWR8-NEXT: addi 30, 3, -8
; PWR8-NEXT: li 28, 0 ; PWR8-NEXT: li 28, 0
; PWR8-NEXT: std 0, 80(1)
; PWR8-NEXT: addi 4, 4, y@toc@l ; PWR8-NEXT: addi 4, 4, y@toc@l
; PWR8-NEXT: addi 29, 4, -16 ; PWR8-NEXT: addi 29, 4, -16
; PWR8-NEXT: .p2align 4 ; PWR8-NEXT: .p2align 4
; PWR8-NEXT: .LBB1_1: # %for.body ; PWR8-NEXT: .LBB1_1: # %for.body
; PWR8-NEXT: # ; PWR8-NEXT: #
; PWR8-NEXT: lfdu 1, 8(30) ; PWR8-NEXT: lfdu 1, 8(30)
; PWR8-NEXT: addi 29, 29, 16 ; PWR8-NEXT: addi 29, 29, 16
; PWR8-NEXT: bl __extenddfkf2 ; PWR8-NEXT: bl __extenddfkf2
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; PWR9-NEXT: blr ; PWR9-NEXT: blr
; ;
; PWR8-LABEL: fptrunc_ctrloop_fp128: ; PWR8-LABEL: fptrunc_ctrloop_fp128:
; PWR8: # %bb.0: # %entry ; PWR8: # %bb.0: # %entry
; PWR8-NEXT: mflr 0 ; PWR8-NEXT: mflr 0
; PWR8-NEXT: std 28, -32(1) # 8-byte Folded Spill ; PWR8-NEXT: std 28, -32(1) # 8-byte Folded Spill
; PWR8-NEXT: std 29, -24(1) # 8-byte Folded Spill ; PWR8-NEXT: std 29, -24(1) # 8-byte Folded Spill
; PWR8-NEXT: std 30, -16(1) # 8-byte Folded Spill ; PWR8-NEXT: std 30, -16(1) # 8-byte Folded Spill
; PWR8-NEXT: std 0, 16(1)
; PWR8-NEXT: stdu 1, -64(1) ; PWR8-NEXT: stdu 1, -64(1)
; PWR8-NEXT: addis 4, 2, x@toc@ha ; PWR8-NEXT: addis 4, 2, x@toc@ha
; PWR8-NEXT: addi 30, 3, -8 ; PWR8-NEXT: addi 30, 3, -8
; PWR8-NEXT: li 28, 0 ; PWR8-NEXT: li 28, 0
; PWR8-NEXT: std 0, 80(1)
; PWR8-NEXT: addi 4, 4, x@toc@l ; PWR8-NEXT: addi 4, 4, x@toc@l
; PWR8-NEXT: addi 29, 4, -16 ; PWR8-NEXT: addi 29, 4, -16
; PWR8-NEXT: .p2align 4 ; PWR8-NEXT: .p2align 4
; PWR8-NEXT: .LBB2_1: # %for.body ; PWR8-NEXT: .LBB2_1: # %for.body
; PWR8-NEXT: # ; PWR8-NEXT: #
; PWR8-NEXT: addi 29, 29, 16 ; PWR8-NEXT: addi 29, 29, 16
; PWR8-NEXT: lxvd2x 0, 0, 29 ; PWR8-NEXT: lxvd2x 0, 0, 29
; PWR8-NEXT: xxswapd 34, 0 ; PWR8-NEXT: xxswapd 34, 0
Show All 33 Lines

llvm/test/CodeGen/PowerPC/cxx_tlscc64.ll

Show All 10 Lines
declare void @_ZN1SD1Ev(ptr) declare void @_ZN1SD1Ev(ptr)
declare i32 @_tlv_atexit(ptr, ptr, ptr) declare i32 @_tlv_atexit(ptr, ptr, ptr)
define cxx_fast_tlscc nonnull ptr @_ZTW2sg() nounwind { define cxx_fast_tlscc nonnull ptr @_ZTW2sg() nounwind {
; CHECK-LABEL: _ZTW2sg: ; CHECK-LABEL: _ZTW2sg:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; CHECK-NEXT: std 30, -16(1) # 8-byte Folded Spill ; CHECK-NEXT: std 30, -16(1) # 8-byte Folded Spill
; CHECK-NEXT: std 0, 16(1)
; CHECK-NEXT: stdu 1, -48(1) ; CHECK-NEXT: stdu 1, -48(1)
; CHECK-NEXT: std 0, 64(1)
; CHECK-NEXT: addis 3, 13, __tls_guard@tprel@ha ; CHECK-NEXT: addis 3, 13, __tls_guard@tprel@ha
; CHECK-NEXT: lbz 4, __tls_guard@tprel@l(3) ; CHECK-NEXT: lbz 4, __tls_guard@tprel@l(3)
; CHECK-NEXT: andi. 4, 4, 1 ; CHECK-NEXT: andi. 4, 4, 1
; CHECK-NEXT: bc 12, 1, .LBB0_2 ; CHECK-NEXT: bc 12, 1, .LBB0_2
; CHECK-NEXT: # %bb.1: # %init.i ; CHECK-NEXT: # %bb.1: # %init.i
; CHECK-NEXT: li 4, 1 ; CHECK-NEXT: li 4, 1
; CHECK-NEXT: stb 4, __tls_guard@tprel@l(3) ; CHECK-NEXT: stb 4, __tls_guard@tprel@l(3)
; CHECK-NEXT: addis 3, 13, sg@tprel@ha ; CHECK-NEXT: addis 3, 13, sg@tprel@ha
▲ Show 20 Lines • Show All 51 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/disable-ctr-ppcf128.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mcpu=pwr9 -verify-machineinstrs -ppc-asm-full-reg-names \ ; RUN: llc -mcpu=pwr9 -verify-machineinstrs -ppc-asm-full-reg-names \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s --check-prefix=LE ; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s --check-prefix=LE
; RUN: llc -mcpu=pwr9 -verify-machineinstrs -ppc-asm-full-reg-names \ ; RUN: llc -mcpu=pwr9 -verify-machineinstrs -ppc-asm-full-reg-names \
; RUN: -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s --check-prefix=P9BE ; RUN: -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s --check-prefix=P9BE
; RUN: llc -mcpu=pwr8 -verify-machineinstrs -ppc-asm-full-reg-names \ ; RUN: llc -mcpu=pwr8 -verify-machineinstrs -ppc-asm-full-reg-names \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s --check-prefix=LE ; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s --check-prefix=LE
; RUN: llc -mcpu=pwr8 -verify-machineinstrs -ppc-asm-full-reg-names \ ; RUN: llc -mcpu=pwr8 -verify-machineinstrs -ppc-asm-full-reg-names \
; RUN: -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s --check-prefix=P8BE ; RUN: -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s --check-prefix=P8BE
declare ppc_fp128 @llvm.fmuladd.ppcf128(ppc_fp128, ppc_fp128, ppc_fp128) #2 declare ppc_fp128 @llvm.fmuladd.ppcf128(ppc_fp128, ppc_fp128, ppc_fp128) #2
define ppc_fp128 @test_ctr0() { define ppc_fp128 @test_ctr0() {
; LE-LABEL: test_ctr0:
; LE: # %bb.0: # %bb
; LE-NEXT: mflr r0
; LE-NEXT: .cfi_def_cfa_offset 48
; LE-NEXT: .cfi_offset lr, 16
; LE-NEXT: .cfi_offset r30, -16
; LE-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; LE-NEXT: std r0, 16(r1)
; LE-NEXT: stdu r1, -48(r1)
; LE-NEXT: xxlxor f1, f1, f1
; LE-NEXT: li r30, 0
; LE-NEXT: xxlxor f2, f2, f2
; LE-NEXT: .p2align 5
; LE-NEXT: .LBB0_1: # %bb6
; LE-NEXT: #
; LE-NEXT: xxlxor f3, f3, f3
; LE-NEXT: xxlxor f4, f4, f4
; LE-NEXT: bl __gcc_qadd
; LE-NEXT: nop
; LE-NEXT: addi r30, r30, 4
; LE-NEXT: cmpldi r30, 0
; LE-NEXT: bne cr0, .LBB0_1
; LE-NEXT: # %bb.2: # %bb14
; LE-NEXT: addi r1, r1, 48
; LE-NEXT: ld r0, 16(r1)
; LE-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; LE-NEXT: mtlr r0
; LE-NEXT: blr
;
; P9BE-LABEL: test_ctr0: ; P9BE-LABEL: test_ctr0:
; P9BE: # %bb.0: # %bb ; P9BE: # %bb.0: # %bb
; P9BE-NEXT: mflr r0 ; P9BE-NEXT: mflr r0
; P9BE-NEXT: std r0, 16(r1)
; P9BE-NEXT: stdu r1, -128(r1) ; P9BE-NEXT: stdu r1, -128(r1)
; P9BE-NEXT: std r0, 144(r1)
; P9BE-NEXT: .cfi_def_cfa_offset 128 ; P9BE-NEXT: .cfi_def_cfa_offset 128
; P9BE-NEXT: .cfi_offset lr, 16 ; P9BE-NEXT: .cfi_offset lr, 16
; P9BE-NEXT: .cfi_offset r30, -16 ; P9BE-NEXT: .cfi_offset r30, -16
; P9BE-NEXT: std r30, 112(r1) # 8-byte Folded Spill ; P9BE-NEXT: std r30, 112(r1) # 8-byte Folded Spill
; P9BE-NEXT: xxlxor f1, f1, f1 ; P9BE-NEXT: xxlxor f1, f1, f1
; P9BE-NEXT: li r30, 0 ; P9BE-NEXT: li r30, 0
; P9BE-NEXT: xxlxor f2, f2, f2 ; P9BE-NEXT: xxlxor f2, f2, f2
; P9BE-NEXT: .p2align 5 ; P9BE-NEXT: .p2align 5
Show All 11 Lines
; P9BE-NEXT: addi r1, r1, 128 ; P9BE-NEXT: addi r1, r1, 128
; P9BE-NEXT: ld r0, 16(r1) ; P9BE-NEXT: ld r0, 16(r1)
; P9BE-NEXT: mtlr r0 ; P9BE-NEXT: mtlr r0
; P9BE-NEXT: blr ; P9BE-NEXT: blr
; ;
; P8BE-LABEL: test_ctr0: ; P8BE-LABEL: test_ctr0:
; P8BE: # %bb.0: # %bb ; P8BE: # %bb.0: # %bb
; P8BE-NEXT: mflr r0 ; P8BE-NEXT: mflr r0
; P8BE-NEXT: std r0, 16(r1)
; P8BE-NEXT: stdu r1, -128(r1) ; P8BE-NEXT: stdu r1, -128(r1)
; P8BE-NEXT: std r0, 144(r1)
; P8BE-NEXT: .cfi_def_cfa_offset 128 ; P8BE-NEXT: .cfi_def_cfa_offset 128
; P8BE-NEXT: .cfi_offset lr, 16 ; P8BE-NEXT: .cfi_offset lr, 16
; P8BE-NEXT: .cfi_offset r30, -16 ; P8BE-NEXT: .cfi_offset r30, -16
; P8BE-NEXT: xxlxor f1, f1, f1 ; P8BE-NEXT: xxlxor f1, f1, f1
; P8BE-NEXT: std r30, 112(r1) # 8-byte Folded Spill ; P8BE-NEXT: std r30, 112(r1) # 8-byte Folded Spill
; P8BE-NEXT: li r30, 0 ; P8BE-NEXT: li r30, 0
; P8BE-NEXT: xxlxor f2, f2, f2 ; P8BE-NEXT: xxlxor f2, f2, f2
; P8BE-NEXT: .p2align 5 ; P8BE-NEXT: .p2align 5
Show All 21 Linesbb6: ; preds = %bb6, %bb
%i8 = tail call ppc_fp128 @llvm.fmuladd.ppcf128(ppc_fp128 0xM00000000000000000000000000000000, ppc_fp128 0xM00000000000000000000000000000000, ppc_fp128 %i) #4 %i8 = tail call ppc_fp128 @llvm.fmuladd.ppcf128(ppc_fp128 0xM00000000000000000000000000000000, ppc_fp128 0xM00000000000000000000000000000000, ppc_fp128 %i) #4
%i9 = add i64 %i7, -4 %i9 = add i64 %i7, -4
%i10 = icmp eq i64 %i9, 0 %i10 = icmp eq i64 %i9, 0
br i1 %i10, label %bb14, label %bb6 br i1 %i10, label %bb14, label %bb6
bb14: ; preds = %bb6 bb14: ; preds = %bb6
ret ppc_fp128 %i8 ret ppc_fp128 %i8
} }
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; LE: {{.*}}

llvm/test/CodeGen/PowerPC/elf64-byval-cc.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -verify-machineinstrs < %s | FileCheck %s
target datalayout = "e-m:e-i64:64-n32:64-S128-v256:256:256-v512:512:512" target datalayout = "e-m:e-i64:64-n32:64-S128-v256:256:256-v512:512:512"
target triple = "powerpc64le-unknown-linux-gnu" target triple = "powerpc64le-unknown-linux-gnu"
%struct_S1 = type { [1 x i8] } %struct_S1 = type { [1 x i8] }
@gS1 = external global %struct_S1, align 1 @gS1 = external global %struct_S1, align 1
define void @call_test_byval_mem1() #0 { define void @call_test_byval_mem1() #0 {
; CHECK-LABEL: call_test_byval_mem1: ; CHECK-LABEL: call_test_byval_mem1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; CHECK-NEXT: std 0, 16(1)
; CHECK-NEXT: stdu 1, -32(1) ; CHECK-NEXT: stdu 1, -32(1)
; CHECK-NEXT: std 0, 48(1)
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: addis 3, 2, .LC0@toc@ha ; CHECK-NEXT: addis 3, 2, .LC0@toc@ha
; CHECK-NEXT: ld 3, .LC0@toc@l(3) ; CHECK-NEXT: ld 3, .LC0@toc@l(3)
; CHECK-NEXT: lbz 3, 0(3) ; CHECK-NEXT: lbz 3, 0(3)
; CHECK-NEXT: bl test_byval_mem1 ; CHECK-NEXT: bl test_byval_mem1
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: addi 1, 1, 32 ; CHECK-NEXT: addi 1, 1, 32
Show All 16 Linesentry:
%0 = load i8, ptr %s, align 1 %0 = load i8, ptr %s, align 1
ret i8 %0 ret i8 %0
} }
define void @call_test_byval_mem1_2() #0 { define void @call_test_byval_mem1_2() #0 {
; CHECK-LABEL: call_test_byval_mem1_2: ; CHECK-LABEL: call_test_byval_mem1_2:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; CHECK-NEXT: std 0, 16(1)
; CHECK-NEXT: stdu 1, -112(1) ; CHECK-NEXT: stdu 1, -112(1)
; CHECK-NEXT: std 0, 128(1)
; CHECK-NEXT: .cfi_def_cfa_offset 112 ; CHECK-NEXT: .cfi_def_cfa_offset 112
; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: addis 3, 2, .LC0@toc@ha ; CHECK-NEXT: addis 3, 2, .LC0@toc@ha
; CHECK-NEXT: li 4, 1 ; CHECK-NEXT: li 4, 1
; CHECK-NEXT: li 5, 2 ; CHECK-NEXT: li 5, 2
; CHECK-NEXT: li 6, 3 ; CHECK-NEXT: li 6, 3
; CHECK-NEXT: li 7, 4 ; CHECK-NEXT: li 7, 4
; CHECK-NEXT: li 8, 5 ; CHECK-NEXT: li 8, 5
Show All 23 Linesentry:
%0 = load i8, ptr %s, align 1 %0 = load i8, ptr %s, align 1
ret i8 %0 ret i8 %0
} }
define void @call_test_byval_mem1_3() #0 { define void @call_test_byval_mem1_3() #0 {
; CHECK-LABEL: call_test_byval_mem1_3: ; CHECK-LABEL: call_test_byval_mem1_3:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; CHECK-NEXT: std 0, 16(1)
; CHECK-NEXT: stdu 1, -32(1) ; CHECK-NEXT: stdu 1, -32(1)
; CHECK-NEXT: std 0, 48(1)
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: addis 3, 2, .LC0@toc@ha ; CHECK-NEXT: addis 3, 2, .LC0@toc@ha
; CHECK-NEXT: li 4, 1 ; CHECK-NEXT: li 4, 1
; CHECK-NEXT: li 5, 2 ; CHECK-NEXT: li 5, 2
; CHECK-NEXT: li 6, 3 ; CHECK-NEXT: li 6, 3
; CHECK-NEXT: li 7, 4 ; CHECK-NEXT: li 7, 4
; CHECK-NEXT: li 8, 5 ; CHECK-NEXT: li 8, 5
Show All 22 Linesentry:
%0 = load i8, ptr %s, align 1 %0 = load i8, ptr %s, align 1
ret i8 %0 ret i8 %0
} }
define void @call_test_byval_mem1_4() #0 { define void @call_test_byval_mem1_4() #0 {
; CHECK-LABEL: call_test_byval_mem1_4: ; CHECK-LABEL: call_test_byval_mem1_4:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; CHECK-NEXT: std 0, 16(1)
; CHECK-NEXT: stdu 1, -112(1) ; CHECK-NEXT: stdu 1, -112(1)
; CHECK-NEXT: std 0, 128(1)
; CHECK-NEXT: .cfi_def_cfa_offset 112 ; CHECK-NEXT: .cfi_def_cfa_offset 112
; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: addis 3, 2, .LC0@toc@ha ; CHECK-NEXT: addis 3, 2, .LC0@toc@ha
; CHECK-NEXT: li 4, 7 ; CHECK-NEXT: li 4, 7
; CHECK-NEXT: li 5, 2 ; CHECK-NEXT: li 5, 2
; CHECK-NEXT: li 7, 3 ; CHECK-NEXT: li 7, 3
; CHECK-NEXT: li 8, 4 ; CHECK-NEXT: li 8, 4
; CHECK-NEXT: li 9, 5 ; CHECK-NEXT: li 9, 5
Show All 24 Linesentry:
%0 = load i8, ptr %s, align 1 %0 = load i8, ptr %s, align 1
ret i8 %0 ret i8 %0
} }
define void @call_test_byval_mem1_5() #0 { define void @call_test_byval_mem1_5() #0 {
; CHECK-LABEL: call_test_byval_mem1_5: ; CHECK-LABEL: call_test_byval_mem1_5:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; CHECK-NEXT: std 0, 16(1)
; CHECK-NEXT: stdu 1, -32(1) ; CHECK-NEXT: stdu 1, -32(1)
; CHECK-NEXT: std 0, 48(1)
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: addis 3, 2, .LC0@toc@ha ; CHECK-NEXT: addis 3, 2, .LC0@toc@ha
; CHECK-NEXT: li 4, 1 ; CHECK-NEXT: li 4, 1
; CHECK-NEXT: li 5, 2 ; CHECK-NEXT: li 5, 2
; CHECK-NEXT: li 7, 3 ; CHECK-NEXT: li 7, 3
; CHECK-NEXT: li 8, 4 ; CHECK-NEXT: li 8, 4
; CHECK-NEXT: li 9, 5 ; CHECK-NEXT: li 9, 5
Show All 25 Lines
%struct_S2 = type { [2 x i8] } %struct_S2 = type { [2 x i8] }
@gS2 = external global %struct_S2, align 1 @gS2 = external global %struct_S2, align 1
define void @call_test_byval_mem2() #0 { define void @call_test_byval_mem2() #0 {
; CHECK-LABEL: call_test_byval_mem2: ; CHECK-LABEL: call_test_byval_mem2:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; CHECK-NEXT: std 0, 16(1)
; CHECK-NEXT: stdu 1, -32(1) ; CHECK-NEXT: stdu 1, -32(1)
; CHECK-NEXT: std 0, 48(1)
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: addis 3, 2, .LC1@toc@ha ; CHECK-NEXT: addis 3, 2, .LC1@toc@ha
; CHECK-NEXT: ld 3, .LC1@toc@l(3) ; CHECK-NEXT: ld 3, .LC1@toc@l(3)
; CHECK-NEXT: lhz 3, 0(3) ; CHECK-NEXT: lhz 3, 0(3)
; CHECK-NEXT: bl test_byval_mem2 ; CHECK-NEXT: bl test_byval_mem2
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: addi 1, 1, 32 ; CHECK-NEXT: addi 1, 1, 32
Show All 18 Lines
%struct_S3 = type { [3 x i8] } %struct_S3 = type { [3 x i8] }
@gS3 = external global %struct_S3, align 1 @gS3 = external global %struct_S3, align 1
define void @call_test_byval_mem3() #0 { define void @call_test_byval_mem3() #0 {
; CHECK-LABEL: call_test_byval_mem3: ; CHECK-LABEL: call_test_byval_mem3:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; CHECK-NEXT: std 0, 16(1)
; CHECK-NEXT: stdu 1, -32(1) ; CHECK-NEXT: stdu 1, -32(1)
; CHECK-NEXT: std 0, 48(1)
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: addis 3, 2, .LC2@toc@ha ; CHECK-NEXT: addis 3, 2, .LC2@toc@ha
; CHECK-NEXT: ld 3, .LC2@toc@l(3) ; CHECK-NEXT: ld 3, .LC2@toc@l(3)
; CHECK-NEXT: lbz 4, 2(3) ; CHECK-NEXT: lbz 4, 2(3)
; CHECK-NEXT: stb 4, 34(1) ; CHECK-NEXT: stb 4, 34(1)
; CHECK-NEXT: lhz 3, 0(3) ; CHECK-NEXT: lhz 3, 0(3)
; CHECK-NEXT: sth 3, 32(1) ; CHECK-NEXT: sth 3, 32(1)
Show All 25 Lines
%struct_S4 = type { [4 x i8] } %struct_S4 = type { [4 x i8] }
@gS4 = external global %struct_S4, align 1 @gS4 = external global %struct_S4, align 1
define void @call_test_byval_mem4() #0 { define void @call_test_byval_mem4() #0 {
; CHECK-LABEL: call_test_byval_mem4: ; CHECK-LABEL: call_test_byval_mem4:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; CHECK-NEXT: std 0, 16(1)
; CHECK-NEXT: stdu 1, -32(1) ; CHECK-NEXT: stdu 1, -32(1)
; CHECK-NEXT: std 0, 48(1)
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: addis 3, 2, .LC3@toc@ha ; CHECK-NEXT: addis 3, 2, .LC3@toc@ha
; CHECK-NEXT: ld 3, .LC3@toc@l(3) ; CHECK-NEXT: ld 3, .LC3@toc@l(3)
; CHECK-NEXT: lwz 3, 0(3) ; CHECK-NEXT: lwz 3, 0(3)
; CHECK-NEXT: bl test_byval_mem4 ; CHECK-NEXT: bl test_byval_mem4
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: addi 1, 1, 32 ; CHECK-NEXT: addi 1, 1, 32
Show All 18 Lines
%struct_S8 = type { [8 x i8] } %struct_S8 = type { [8 x i8] }
@gS8 = external global %struct_S8, align 1 @gS8 = external global %struct_S8, align 1
define void @call_test_byval_mem8() #0 { define void @call_test_byval_mem8() #0 {
; CHECK-LABEL: call_test_byval_mem8: ; CHECK-LABEL: call_test_byval_mem8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; CHECK-NEXT: std 0, 16(1)
; CHECK-NEXT: stdu 1, -32(1) ; CHECK-NEXT: stdu 1, -32(1)
; CHECK-NEXT: std 0, 48(1)
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: addis 3, 2, .LC4@toc@ha ; CHECK-NEXT: addis 3, 2, .LC4@toc@ha
; CHECK-NEXT: ld 3, .LC4@toc@l(3) ; CHECK-NEXT: ld 3, .LC4@toc@l(3)
; CHECK-NEXT: ld 3, 0(3) ; CHECK-NEXT: ld 3, 0(3)
; CHECK-NEXT: bl test_byval_mem8 ; CHECK-NEXT: bl test_byval_mem8
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: addi 1, 1, 32 ; CHECK-NEXT: addi 1, 1, 32
Show All 19 Lines
%struct_S32 = type {[32 x i8] } %struct_S32 = type {[32 x i8] }
@gS32 = external global %struct_S32, align 1 @gS32 = external global %struct_S32, align 1
define void @call_test_byval_mem32() #0 { define void @call_test_byval_mem32() #0 {
; CHECK-LABEL: call_test_byval_mem32: ; CHECK-LABEL: call_test_byval_mem32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; CHECK-NEXT: std 0, 16(1)
; CHECK-NEXT: stdu 1, -32(1) ; CHECK-NEXT: stdu 1, -32(1)
; CHECK-NEXT: std 0, 48(1)
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: addis 3, 2, .LC5@toc@ha ; CHECK-NEXT: addis 3, 2, .LC5@toc@ha
; CHECK-NEXT: ld 3, .LC5@toc@l(3) ; CHECK-NEXT: ld 3, .LC5@toc@l(3)
; CHECK-NEXT: ld 6, 24(3) ; CHECK-NEXT: ld 6, 24(3)
; CHECK-NEXT: ld 5, 16(3) ; CHECK-NEXT: ld 5, 16(3)
; CHECK-NEXT: ld 4, 8(3) ; CHECK-NEXT: ld 4, 8(3)
; CHECK-NEXT: ld 3, 0(3) ; CHECK-NEXT: ld 3, 0(3)
Show All 22 Linesentry:
%0 = load i8, ptr %s, align 1 %0 = load i8, ptr %s, align 1
ret i8 %0 ret i8 %0
} }
define void @call_test_byval_mem32_2() #0 { define void @call_test_byval_mem32_2() #0 {
; CHECK-LABEL: call_test_byval_mem32_2: ; CHECK-LABEL: call_test_byval_mem32_2:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; CHECK-NEXT: std 0, 16(1)
; CHECK-NEXT: stdu 1, -32(1) ; CHECK-NEXT: stdu 1, -32(1)
; CHECK-NEXT: std 0, 48(1)
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: addis 3, 2, .LC5@toc@ha ; CHECK-NEXT: addis 3, 2, .LC5@toc@ha
; CHECK-NEXT: addis 8, 2, .LCPI20_0@toc@ha ; CHECK-NEXT: addis 8, 2, .LCPI20_0@toc@ha
; CHECK-NEXT: ld 3, .LC5@toc@l(3) ; CHECK-NEXT: ld 3, .LC5@toc@l(3)
; CHECK-NEXT: lfs 1, .LCPI20_0@toc@l(8) ; CHECK-NEXT: lfs 1, .LCPI20_0@toc@l(8)
; CHECK-NEXT: ld 7, 24(3) ; CHECK-NEXT: ld 7, 24(3)
; CHECK-NEXT: ld 6, 16(3) ; CHECK-NEXT: ld 6, 16(3)
Show All 23 Linesentry:
%0 = load i8, ptr %s, align 1 %0 = load i8, ptr %s, align 1
ret i8 %0 ret i8 %0
} }
define void @call_test_byval_mem32_3() #0 { define void @call_test_byval_mem32_3() #0 {
; CHECK-LABEL: call_test_byval_mem32_3: ; CHECK-LABEL: call_test_byval_mem32_3:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; CHECK-NEXT: std 0, 16(1)
; CHECK-NEXT: stdu 1, -112(1) ; CHECK-NEXT: stdu 1, -112(1)
; CHECK-NEXT: std 0, 128(1)
; CHECK-NEXT: .cfi_def_cfa_offset 112 ; CHECK-NEXT: .cfi_def_cfa_offset 112
; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: addis 3, 2, .LC5@toc@ha ; CHECK-NEXT: addis 3, 2, .LC5@toc@ha
; CHECK-NEXT: li 4, 16 ; CHECK-NEXT: li 4, 16
; CHECK-NEXT: addis 5, 2, .LCPI22_1@toc@ha ; CHECK-NEXT: addis 5, 2, .LCPI22_1@toc@ha
; CHECK-NEXT: li 7, 2 ; CHECK-NEXT: li 7, 2
; CHECK-NEXT: ld 3, .LC5@toc@l(3) ; CHECK-NEXT: ld 3, .LC5@toc@l(3)
; CHECK-NEXT: lfs 2, .LCPI22_1@toc@l(5) ; CHECK-NEXT: lfs 2, .LCPI22_1@toc@l(5)
Show All 36 Lines
%struct_S64 = type {[64 x i8] } %struct_S64 = type {[64 x i8] }
@gS64= external global %struct_S64, align 1 @gS64= external global %struct_S64, align 1
define void @call_test_byval_mem64() #0 { define void @call_test_byval_mem64() #0 {
; CHECK-LABEL: call_test_byval_mem64: ; CHECK-LABEL: call_test_byval_mem64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; CHECK-NEXT: std 0, 16(1)
; CHECK-NEXT: stdu 1, -32(1) ; CHECK-NEXT: stdu 1, -32(1)
; CHECK-NEXT: std 0, 48(1)
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: addis 3, 2, .LC6@toc@ha ; CHECK-NEXT: addis 3, 2, .LC6@toc@ha
; CHECK-NEXT: ld 3, .LC6@toc@l(3) ; CHECK-NEXT: ld 3, .LC6@toc@l(3)
; CHECK-NEXT: ld 10, 56(3) ; CHECK-NEXT: ld 10, 56(3)
; CHECK-NEXT: ld 9, 48(3) ; CHECK-NEXT: ld 9, 48(3)
; CHECK-NEXT: ld 8, 40(3) ; CHECK-NEXT: ld 8, 40(3)
; CHECK-NEXT: ld 7, 32(3) ; CHECK-NEXT: ld 7, 32(3)
Show All 32 Lines
%struct_S65 = type { [65 x i8] } %struct_S65 = type { [65 x i8] }
@gS65 = external global %struct_S65, align 1 @gS65 = external global %struct_S65, align 1
define void @call_test_byval_mem65() #0 { define void @call_test_byval_mem65() #0 {
; CHECK-LABEL: call_test_byval_mem65: ; CHECK-LABEL: call_test_byval_mem65:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; CHECK-NEXT: std 0, 16(1)
; CHECK-NEXT: stdu 1, -112(1) ; CHECK-NEXT: stdu 1, -112(1)
; CHECK-NEXT: std 0, 128(1)
; CHECK-NEXT: .cfi_def_cfa_offset 112 ; CHECK-NEXT: .cfi_def_cfa_offset 112
; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: addis 3, 2, .LC7@toc@ha ; CHECK-NEXT: addis 3, 2, .LC7@toc@ha
; CHECK-NEXT: li 4, 48 ; CHECK-NEXT: li 4, 48
; CHECK-NEXT: li 5, 80 ; CHECK-NEXT: li 5, 80
; CHECK-NEXT: li 6, 64 ; CHECK-NEXT: li 6, 64
; CHECK-NEXT: ld 3, .LC7@toc@l(3) ; CHECK-NEXT: ld 3, .LC7@toc@l(3)
; CHECK-NEXT: lxvd2x 0, 3, 4 ; CHECK-NEXT: lxvd2x 0, 3, 4
▲ Show 20 Lines • Show All 47 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/expand-foldable-isel.ll

Show All 25 Lines
; CHECK-GEN-ISEL-TRUE: # %bb.0: # %entry ; CHECK-GEN-ISEL-TRUE: # %bb.0: # %entry
; CHECK-GEN-ISEL-TRUE-NEXT: mflr r0 ; CHECK-GEN-ISEL-TRUE-NEXT: mflr r0
; CHECK-GEN-ISEL-TRUE-NEXT: .cfi_def_cfa_offset 64 ; CHECK-GEN-ISEL-TRUE-NEXT: .cfi_def_cfa_offset 64
; CHECK-GEN-ISEL-TRUE-NEXT: .cfi_offset lr, 16 ; CHECK-GEN-ISEL-TRUE-NEXT: .cfi_offset lr, 16
; CHECK-GEN-ISEL-TRUE-NEXT: .cfi_offset r29, -24 ; CHECK-GEN-ISEL-TRUE-NEXT: .cfi_offset r29, -24
; CHECK-GEN-ISEL-TRUE-NEXT: .cfi_offset r30, -16 ; CHECK-GEN-ISEL-TRUE-NEXT: .cfi_offset r30, -16
; CHECK-GEN-ISEL-TRUE-NEXT: std r29, -24(r1) # 8-byte Folded Spill ; CHECK-GEN-ISEL-TRUE-NEXT: std r29, -24(r1) # 8-byte Folded Spill
; CHECK-GEN-ISEL-TRUE-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-GEN-ISEL-TRUE-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-GEN-ISEL-TRUE-NEXT: std r0, 16(r1)
; CHECK-GEN-ISEL-TRUE-NEXT: stdu r1, -64(r1) ; CHECK-GEN-ISEL-TRUE-NEXT: stdu r1, -64(r1)
; CHECK-GEN-ISEL-TRUE-NEXT: mr r30, r3 ; CHECK-GEN-ISEL-TRUE-NEXT: mr r30, r3
; CHECK-GEN-ISEL-TRUE-NEXT: # implicit-def: $x3 ; CHECK-GEN-ISEL-TRUE-NEXT: # implicit-def: $x3
; CHECK-GEN-ISEL-TRUE-NEXT: # implicit-def: $r29 ; CHECK-GEN-ISEL-TRUE-NEXT: # implicit-def: $r29
; CHECK-GEN-ISEL-TRUE-NEXT: std r0, 80(r1)
; CHECK-GEN-ISEL-TRUE-NEXT: .p2align 4 ; CHECK-GEN-ISEL-TRUE-NEXT: .p2align 4
; CHECK-GEN-ISEL-TRUE-NEXT: .LBB0_1: # %while.cond11 ; CHECK-GEN-ISEL-TRUE-NEXT: .LBB0_1: # %while.cond11
; CHECK-GEN-ISEL-TRUE-NEXT: # ; CHECK-GEN-ISEL-TRUE-NEXT: #
; CHECK-GEN-ISEL-TRUE-NEXT: lwz r4, 0(r3) ; CHECK-GEN-ISEL-TRUE-NEXT: lwz r4, 0(r3)
; CHECK-GEN-ISEL-TRUE-NEXT: cmplwi r4, 0 ; CHECK-GEN-ISEL-TRUE-NEXT: cmplwi r4, 0
; CHECK-GEN-ISEL-TRUE-NEXT: beq cr0, .LBB0_3 ; CHECK-GEN-ISEL-TRUE-NEXT: beq cr0, .LBB0_3
; CHECK-GEN-ISEL-TRUE-NEXT: # %bb.2: # %while.body21 ; CHECK-GEN-ISEL-TRUE-NEXT: # %bb.2: # %while.body21
; CHECK-GEN-ISEL-TRUE-NEXT: # ; CHECK-GEN-ISEL-TRUE-NEXT: #
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; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr r0 ; CHECK-NEXT: mflr r0
; CHECK-NEXT: .cfi_def_cfa_offset 64 ; CHECK-NEXT: .cfi_def_cfa_offset 64
; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: .cfi_offset r29, -24 ; CHECK-NEXT: .cfi_offset r29, -24
; CHECK-NEXT: .cfi_offset r30, -16 ; CHECK-NEXT: .cfi_offset r30, -16
; CHECK-NEXT: std r29, -24(r1) # 8-byte Folded Spill ; CHECK-NEXT: std r29, -24(r1) # 8-byte Folded Spill
; CHECK-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-NEXT: std r0, 16(r1)
; CHECK-NEXT: stdu r1, -64(r1) ; CHECK-NEXT: stdu r1, -64(r1)
; CHECK-NEXT: mr r30, r3 ; CHECK-NEXT: mr r30, r3
; CHECK-NEXT: # implicit-def: $x3 ; CHECK-NEXT: # implicit-def: $x3
; CHECK-NEXT: # implicit-def: $r29 ; CHECK-NEXT: # implicit-def: $r29
; CHECK-NEXT: std r0, 80(r1)
; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: .p2align 4
; CHECK-NEXT: .LBB0_1: # %while.cond11 ; CHECK-NEXT: .LBB0_1: # %while.cond11
; CHECK-NEXT: # ; CHECK-NEXT: #
; CHECK-NEXT: lwz r4, 0(r3) ; CHECK-NEXT: lwz r4, 0(r3)
; CHECK-NEXT: cmplwi r4, 0 ; CHECK-NEXT: cmplwi r4, 0
; CHECK-NEXT: beq cr0, .LBB0_6 ; CHECK-NEXT: beq cr0, .LBB0_6
; CHECK-NEXT: # %bb.2: # %while.body21 ; CHECK-NEXT: # %bb.2: # %while.body21
; CHECK-NEXT: # ; CHECK-NEXT: #
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llvm/test/CodeGen/PowerPC/f128-aggregates.ll

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; CHECK-BE-NEXT: mtvsrd v3, r9 ; CHECK-BE-NEXT: mtvsrd v3, r9
; CHECK-BE-NEXT: xscvsdqp v3, v3 ; CHECK-BE-NEXT: xscvsdqp v3, v3
; CHECK-BE-NEXT: xsaddqp v2, v2, v3 ; CHECK-BE-NEXT: xsaddqp v2, v2, v3
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-P8-LABEL: testMixedAggregate_03: ; CHECK-P8-LABEL: testMixedAggregate_03:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -96(r1) ; CHECK-P8-NEXT: stdu r1, -96(r1)
; CHECK-P8-NEXT: std r0, 112(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 96 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 96
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: .cfi_offset v31, -32 ; CHECK-P8-NEXT: .cfi_offset v31, -32
; CHECK-P8-NEXT: li r4, 64 ; CHECK-P8-NEXT: li r4, 64
; CHECK-P8-NEXT: std r30, 80(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, 80(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: extsw r3, r3 ; CHECK-P8-NEXT: extsw r3, r3
; CHECK-P8-NEXT: mr r30, r10 ; CHECK-P8-NEXT: mr r30, r10
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; ;
; CHECK-P8-LABEL: sum_float128: ; CHECK-P8-LABEL: sum_float128:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 64 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 64
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -64(r1) ; CHECK-P8-NEXT: stdu r1, -64(r1)
; CHECK-P8-NEXT: addis r11, r2, .LCPI17_0@toc@ha ; CHECK-P8-NEXT: addis r11, r2, .LCPI17_0@toc@ha
; CHECK-P8-NEXT: cmpwi r3, 0 ; CHECK-P8-NEXT: cmpwi r3, 0
; CHECK-P8-NEXT: std r0, 80(r1)
; CHECK-P8-NEXT: std r4, 104(r1) ; CHECK-P8-NEXT: std r4, 104(r1)
; CHECK-P8-NEXT: std r5, 112(r1) ; CHECK-P8-NEXT: std r5, 112(r1)
; CHECK-P8-NEXT: std r6, 120(r1) ; CHECK-P8-NEXT: std r6, 120(r1)
; CHECK-P8-NEXT: std r7, 128(r1)
; CHECK-P8-NEXT: addi r11, r11, .LCPI17_0@toc@l ; CHECK-P8-NEXT: addi r11, r11, .LCPI17_0@toc@l
; CHECK-P8-NEXT: lxvd2x vs0, 0, r11 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r11
; CHECK-P8-NEXT: std r7, 128(r1)
; CHECK-P8-NEXT: std r8, 136(r1) ; CHECK-P8-NEXT: std r8, 136(r1)
; CHECK-P8-NEXT: std r9, 144(r1) ; CHECK-P8-NEXT: std r9, 144(r1)
; CHECK-P8-NEXT: std r10, 152(r1) ; CHECK-P8-NEXT: std r10, 152(r1)
; CHECK-P8-NEXT: xxswapd v3, vs0 ; CHECK-P8-NEXT: xxswapd v3, vs0
; CHECK-P8-NEXT: ble cr0, .LBB17_2 ; CHECK-P8-NEXT: ble cr0, .LBB17_2
; CHECK-P8-NEXT: # %bb.1: # %if.end ; CHECK-P8-NEXT: # %bb.1: # %if.end
; CHECK-P8-NEXT: addi r30, r1, 104 ; CHECK-P8-NEXT: addi r30, r1, 104
; CHECK-P8-NEXT: lxvd2x vs0, 0, r30 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r30
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llvm/test/CodeGen/PowerPC/f128-arith.ll

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; ;
; CHECK-P8-LABEL: qpAdd: ; CHECK-P8-LABEL: qpAdd:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: mr r30, r4 ; CHECK-P8-NEXT: mr r30, r4
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: vmr v3, v2 ; CHECK-P8-NEXT: vmr v3, v2
; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: bl __addkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
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; ;
; CHECK-P8-LABEL: qpSub: ; CHECK-P8-LABEL: qpSub:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: mr r30, r4 ; CHECK-P8-NEXT: mr r30, r4
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: vmr v3, v2 ; CHECK-P8-NEXT: vmr v3, v2
; CHECK-P8-NEXT: bl __subkf3 ; CHECK-P8-NEXT: bl __subkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
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; ;
; CHECK-P8-LABEL: qpMul: ; CHECK-P8-LABEL: qpMul:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: mr r30, r4 ; CHECK-P8-NEXT: mr r30, r4
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: vmr v3, v2 ; CHECK-P8-NEXT: vmr v3, v2
; CHECK-P8-NEXT: bl __mulkf3 ; CHECK-P8-NEXT: bl __mulkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
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; ;
; CHECK-P8-LABEL: qpDiv: ; CHECK-P8-LABEL: qpDiv:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: mr r30, r4 ; CHECK-P8-NEXT: mr r30, r4
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: vmr v3, v2 ; CHECK-P8-NEXT: vmr v3, v2
; CHECK-P8-NEXT: bl __divkf3 ; CHECK-P8-NEXT: bl __divkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
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; ;
; CHECK-P8-LABEL: qpSqrt: ; CHECK-P8-LABEL: qpSqrt:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: mr r30, r4 ; CHECK-P8-NEXT: mr r30, r4
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl sqrtf128 ; CHECK-P8-NEXT: bl sqrtf128
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
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ret void ret void
} }
define fp128 @qp_sin(ptr nocapture readonly %a) { define fp128 @qp_sin(ptr nocapture readonly %a) {
; CHECK-LABEL: qp_sin: ; CHECK-LABEL: qp_sin:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr r0 ; CHECK-NEXT: mflr r0
; CHECK-NEXT: std r0, 16(r1)
; CHECK-NEXT: stdu r1, -32(r1) ; CHECK-NEXT: stdu r1, -32(r1)
; CHECK-NEXT: std r0, 48(r1)
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: lxv v2, 0(r3) ; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: bl sinf128 ; CHECK-NEXT: bl sinf128
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: addi r1, r1, 32 ; CHECK-NEXT: addi r1, r1, 32
; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: ld r0, 16(r1)
; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: mtlr r0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: qp_sin: ; CHECK-P8-LABEL: qp_sin:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: std r0, 48(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl sinf128 ; CHECK-P8-NEXT: bl sinf128
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addi r1, r1, 32 ; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%0 = load fp128, ptr %a, align 16 %0 = load fp128, ptr %a, align 16
%1 = tail call fp128 @llvm.sin.f128(fp128 %0) %1 = tail call fp128 @llvm.sin.f128(fp128 %0)
ret fp128 %1 ret fp128 %1
} }
declare fp128 @llvm.sin.f128(fp128 %Val) declare fp128 @llvm.sin.f128(fp128 %Val)
define fp128 @qp_cos(ptr nocapture readonly %a) { define fp128 @qp_cos(ptr nocapture readonly %a) {
; CHECK-LABEL: qp_cos: ; CHECK-LABEL: qp_cos:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr r0 ; CHECK-NEXT: mflr r0
; CHECK-NEXT: std r0, 16(r1)
; CHECK-NEXT: stdu r1, -32(r1) ; CHECK-NEXT: stdu r1, -32(r1)
; CHECK-NEXT: std r0, 48(r1)
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: lxv v2, 0(r3) ; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: bl cosf128 ; CHECK-NEXT: bl cosf128
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: addi r1, r1, 32 ; CHECK-NEXT: addi r1, r1, 32
; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: ld r0, 16(r1)
; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: mtlr r0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: qp_cos: ; CHECK-P8-LABEL: qp_cos:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: std r0, 48(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl cosf128 ; CHECK-P8-NEXT: bl cosf128
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addi r1, r1, 32 ; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%0 = load fp128, ptr %a, align 16 %0 = load fp128, ptr %a, align 16
%1 = tail call fp128 @llvm.cos.f128(fp128 %0) %1 = tail call fp128 @llvm.cos.f128(fp128 %0)
ret fp128 %1 ret fp128 %1
} }
declare fp128 @llvm.cos.f128(fp128 %Val) declare fp128 @llvm.cos.f128(fp128 %Val)
define fp128 @qp_log(ptr nocapture readonly %a) { define fp128 @qp_log(ptr nocapture readonly %a) {
; CHECK-LABEL: qp_log: ; CHECK-LABEL: qp_log:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr r0 ; CHECK-NEXT: mflr r0
; CHECK-NEXT: std r0, 16(r1)
; CHECK-NEXT: stdu r1, -32(r1) ; CHECK-NEXT: stdu r1, -32(r1)
; CHECK-NEXT: std r0, 48(r1)
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: lxv v2, 0(r3) ; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: bl logf128 ; CHECK-NEXT: bl logf128
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: addi r1, r1, 32 ; CHECK-NEXT: addi r1, r1, 32
; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: ld r0, 16(r1)
; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: mtlr r0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: qp_log: ; CHECK-P8-LABEL: qp_log:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: std r0, 48(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl logf128 ; CHECK-P8-NEXT: bl logf128
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addi r1, r1, 32 ; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%0 = load fp128, ptr %a, align 16 %0 = load fp128, ptr %a, align 16
%1 = tail call fp128 @llvm.log.f128(fp128 %0) %1 = tail call fp128 @llvm.log.f128(fp128 %0)
ret fp128 %1 ret fp128 %1
} }
declare fp128 @llvm.log.f128(fp128 %Val) declare fp128 @llvm.log.f128(fp128 %Val)
define fp128 @qp_log10(ptr nocapture readonly %a) { define fp128 @qp_log10(ptr nocapture readonly %a) {
; CHECK-LABEL: qp_log10: ; CHECK-LABEL: qp_log10:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr r0 ; CHECK-NEXT: mflr r0
; CHECK-NEXT: std r0, 16(r1)
; CHECK-NEXT: stdu r1, -32(r1) ; CHECK-NEXT: stdu r1, -32(r1)
; CHECK-NEXT: std r0, 48(r1)
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: lxv v2, 0(r3) ; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: bl log10f128 ; CHECK-NEXT: bl log10f128
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: addi r1, r1, 32 ; CHECK-NEXT: addi r1, r1, 32
; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: ld r0, 16(r1)
; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: mtlr r0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: qp_log10: ; CHECK-P8-LABEL: qp_log10:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: std r0, 48(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl log10f128 ; CHECK-P8-NEXT: bl log10f128
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addi r1, r1, 32 ; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%0 = load fp128, ptr %a, align 16 %0 = load fp128, ptr %a, align 16
%1 = tail call fp128 @llvm.log10.f128(fp128 %0) %1 = tail call fp128 @llvm.log10.f128(fp128 %0)
ret fp128 %1 ret fp128 %1
} }
declare fp128 @llvm.log10.f128(fp128 %Val) declare fp128 @llvm.log10.f128(fp128 %Val)
define fp128 @qp_log2(ptr nocapture readonly %a) { define fp128 @qp_log2(ptr nocapture readonly %a) {
; CHECK-LABEL: qp_log2: ; CHECK-LABEL: qp_log2:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr r0 ; CHECK-NEXT: mflr r0
; CHECK-NEXT: std r0, 16(r1)
; CHECK-NEXT: stdu r1, -32(r1) ; CHECK-NEXT: stdu r1, -32(r1)
; CHECK-NEXT: std r0, 48(r1)
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: lxv v2, 0(r3) ; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: bl log2f128 ; CHECK-NEXT: bl log2f128
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: addi r1, r1, 32 ; CHECK-NEXT: addi r1, r1, 32
; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: ld r0, 16(r1)
; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: mtlr r0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: qp_log2: ; CHECK-P8-LABEL: qp_log2:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: std r0, 48(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl log2f128 ; CHECK-P8-NEXT: bl log2f128
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addi r1, r1, 32 ; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%0 = load fp128, ptr %a, align 16 %0 = load fp128, ptr %a, align 16
%1 = tail call fp128 @llvm.log2.f128(fp128 %0) %1 = tail call fp128 @llvm.log2.f128(fp128 %0)
ret fp128 %1 ret fp128 %1
} }
declare fp128 @llvm.log2.f128(fp128 %Val) declare fp128 @llvm.log2.f128(fp128 %Val)
define fp128 @qp_minnum(ptr nocapture readonly %a, define fp128 @qp_minnum(ptr nocapture readonly %a,
; CHECK-LABEL: qp_minnum: ; CHECK-LABEL: qp_minnum:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr r0 ; CHECK-NEXT: mflr r0
; CHECK-NEXT: std r0, 16(r1)
; CHECK-NEXT: stdu r1, -32(r1) ; CHECK-NEXT: stdu r1, -32(r1)
; CHECK-NEXT: std r0, 48(r1)
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: lxv v2, 0(r3) ; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: lxv v3, 0(r4) ; CHECK-NEXT: lxv v3, 0(r4)
; CHECK-NEXT: bl fminf128 ; CHECK-NEXT: bl fminf128
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: addi r1, r1, 32 ; CHECK-NEXT: addi r1, r1, 32
; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: ld r0, 16(r1)
; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: mtlr r0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: qp_minnum: ; CHECK-P8-LABEL: qp_minnum:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: std r0, 48(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: lxvd2x vs1, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxswapd v3, vs1 ; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: bl fminf128 ; CHECK-P8-NEXT: bl fminf128
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
Show All 9 Linesentry:
ret fp128 %2 ret fp128 %2
} }
declare fp128 @llvm.minnum.f128(fp128 %Val0, fp128 %Val1) declare fp128 @llvm.minnum.f128(fp128 %Val0, fp128 %Val1)
define fp128 @qp_maxnum(ptr nocapture readonly %a, define fp128 @qp_maxnum(ptr nocapture readonly %a,
; CHECK-LABEL: qp_maxnum: ; CHECK-LABEL: qp_maxnum:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr r0 ; CHECK-NEXT: mflr r0
; CHECK-NEXT: std r0, 16(r1)
; CHECK-NEXT: stdu r1, -32(r1) ; CHECK-NEXT: stdu r1, -32(r1)
; CHECK-NEXT: std r0, 48(r1)
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: lxv v2, 0(r3) ; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: lxv v3, 0(r4) ; CHECK-NEXT: lxv v3, 0(r4)
; CHECK-NEXT: bl fmaxf128 ; CHECK-NEXT: bl fmaxf128
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: addi r1, r1, 32 ; CHECK-NEXT: addi r1, r1, 32
; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: ld r0, 16(r1)
; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: mtlr r0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: qp_maxnum: ; CHECK-P8-LABEL: qp_maxnum:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: std r0, 48(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: lxvd2x vs1, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxswapd v3, vs1 ; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: bl fmaxf128 ; CHECK-P8-NEXT: bl fmaxf128
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
Show All 9 Linesentry:
ret fp128 %2 ret fp128 %2
} }
declare fp128 @llvm.maxnum.f128(fp128 %Val0, fp128 %Val1) declare fp128 @llvm.maxnum.f128(fp128 %Val0, fp128 %Val1)
define fp128 @qp_pow(ptr nocapture readonly %a, define fp128 @qp_pow(ptr nocapture readonly %a,
; CHECK-LABEL: qp_pow: ; CHECK-LABEL: qp_pow:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr r0 ; CHECK-NEXT: mflr r0
; CHECK-NEXT: std r0, 16(r1)
; CHECK-NEXT: stdu r1, -32(r1) ; CHECK-NEXT: stdu r1, -32(r1)
; CHECK-NEXT: std r0, 48(r1)
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: lxv v2, 0(r3) ; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: lxv v3, 0(r4) ; CHECK-NEXT: lxv v3, 0(r4)
; CHECK-NEXT: bl powf128 ; CHECK-NEXT: bl powf128
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: addi r1, r1, 32 ; CHECK-NEXT: addi r1, r1, 32
; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: ld r0, 16(r1)
; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: mtlr r0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: qp_pow: ; CHECK-P8-LABEL: qp_pow:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: std r0, 48(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: lxvd2x vs1, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxswapd v3, vs1 ; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: bl powf128 ; CHECK-P8-NEXT: bl powf128
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
Show All 9 Linesentry:
ret fp128 %2 ret fp128 %2
} }
declare fp128 @llvm.pow.f128(fp128 %Val, fp128 %Power) declare fp128 @llvm.pow.f128(fp128 %Val, fp128 %Power)
define fp128 @qp_exp(ptr nocapture readonly %a) { define fp128 @qp_exp(ptr nocapture readonly %a) {
; CHECK-LABEL: qp_exp: ; CHECK-LABEL: qp_exp:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr r0 ; CHECK-NEXT: mflr r0
; CHECK-NEXT: std r0, 16(r1)
; CHECK-NEXT: stdu r1, -32(r1) ; CHECK-NEXT: stdu r1, -32(r1)
; CHECK-NEXT: std r0, 48(r1)
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: lxv v2, 0(r3) ; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: bl expf128 ; CHECK-NEXT: bl expf128
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: addi r1, r1, 32 ; CHECK-NEXT: addi r1, r1, 32
; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: ld r0, 16(r1)
; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: mtlr r0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: qp_exp: ; CHECK-P8-LABEL: qp_exp:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: std r0, 48(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl expf128 ; CHECK-P8-NEXT: bl expf128
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addi r1, r1, 32 ; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%0 = load fp128, ptr %a, align 16 %0 = load fp128, ptr %a, align 16
%1 = tail call fp128 @llvm.exp.f128(fp128 %0) %1 = tail call fp128 @llvm.exp.f128(fp128 %0)
ret fp128 %1 ret fp128 %1
} }
declare fp128 @llvm.exp.f128(fp128 %Val) declare fp128 @llvm.exp.f128(fp128 %Val)
define fp128 @qp_exp2(ptr nocapture readonly %a) { define fp128 @qp_exp2(ptr nocapture readonly %a) {
; CHECK-LABEL: qp_exp2: ; CHECK-LABEL: qp_exp2:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr r0 ; CHECK-NEXT: mflr r0
; CHECK-NEXT: std r0, 16(r1)
; CHECK-NEXT: stdu r1, -32(r1) ; CHECK-NEXT: stdu r1, -32(r1)
; CHECK-NEXT: std r0, 48(r1)
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: lxv v2, 0(r3) ; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: bl exp2f128 ; CHECK-NEXT: bl exp2f128
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: addi r1, r1, 32 ; CHECK-NEXT: addi r1, r1, 32
; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: ld r0, 16(r1)
; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: mtlr r0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: qp_exp2: ; CHECK-P8-LABEL: qp_exp2:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: std r0, 48(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl exp2f128 ; CHECK-P8-NEXT: bl exp2f128
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addi r1, r1, 32 ; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
Show All 9 Lines
define dso_local void @qp_powi(ptr nocapture readonly %a, ptr nocapture readonly %b, define dso_local void @qp_powi(ptr nocapture readonly %a, ptr nocapture readonly %b,
; CHECK-LABEL: qp_powi: ; CHECK-LABEL: qp_powi:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr r0 ; CHECK-NEXT: mflr r0
; CHECK-NEXT: .cfi_def_cfa_offset 48 ; CHECK-NEXT: .cfi_def_cfa_offset 48
; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: .cfi_offset r30, -16 ; CHECK-NEXT: .cfi_offset r30, -16
; CHECK-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-NEXT: std r0, 16(r1)
; CHECK-NEXT: stdu r1, -48(r1) ; CHECK-NEXT: stdu r1, -48(r1)
; CHECK-NEXT: lxv v2, 0(r3) ; CHECK-NEXT: std r0, 64(r1)
; CHECK-NEXT: mr r30, r5 ; CHECK-NEXT: mr r30, r5
; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: lwz r5, 0(r4) ; CHECK-NEXT: lwz r5, 0(r4)
; CHECK-NEXT: bl __powikf2 ; CHECK-NEXT: bl __powikf2
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: stxv v2, 0(r30) ; CHECK-NEXT: stxv v2, 0(r30)
; CHECK-NEXT: addi r1, r1, 48 ; CHECK-NEXT: addi r1, r1, 48
; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: ld r0, 16(r1)
; CHECK-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: mtlr r0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: qp_powi: ; CHECK-P8-LABEL: qp_powi:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: mr r30, r5
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: lwz r3, 0(r4) ; CHECK-P8-NEXT: lwz r3, 0(r4)
; CHECK-P8-NEXT: mr r30, r5
; CHECK-P8-NEXT: mr r5, r3 ; CHECK-P8-NEXT: mr r5, r3
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl __powikf2 ; CHECK-P8-NEXT: bl __powikf2
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
Show All 12 Lines
@a = common dso_local global fp128 0xL00000000000000000000000000000000, align 16 @a = common dso_local global fp128 0xL00000000000000000000000000000000, align 16
@b = common dso_local global fp128 0xL00000000000000000000000000000000, align 16 @b = common dso_local global fp128 0xL00000000000000000000000000000000, align 16
define fp128 @qp_frem() #0 { define fp128 @qp_frem() #0 {
; CHECK-LABEL: qp_frem: ; CHECK-LABEL: qp_frem:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr r0 ; CHECK-NEXT: mflr r0
; CHECK-NEXT: std r0, 16(r1)
; CHECK-NEXT: stdu r1, -32(r1) ; CHECK-NEXT: stdu r1, -32(r1)
; CHECK-NEXT: std r0, 48(r1)
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: addis r3, r2, a@toc@ha ; CHECK-NEXT: addis r3, r2, a@toc@ha
; CHECK-NEXT: addi r3, r3, a@toc@l ; CHECK-NEXT: addi r3, r3, a@toc@l
; CHECK-NEXT: lxv v2, 0(r3) ; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: addis r3, r2, b@toc@ha ; CHECK-NEXT: addis r3, r2, b@toc@ha
; CHECK-NEXT: addi r3, r3, b@toc@l ; CHECK-NEXT: addi r3, r3, b@toc@l
; CHECK-NEXT: lxv v3, 0(r3) ; CHECK-NEXT: lxv v3, 0(r3)
; CHECK-NEXT: bl fmodf128 ; CHECK-NEXT: bl fmodf128
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: addi r1, r1, 32 ; CHECK-NEXT: addi r1, r1, 32
; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: ld r0, 16(r1)
; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: mtlr r0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: qp_frem: ; CHECK-P8-LABEL: qp_frem:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: std r0, 48(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: addis r3, r2, a@toc@ha ; CHECK-P8-NEXT: addis r3, r2, a@toc@ha
; CHECK-P8-NEXT: addis r4, r2, b@toc@ha ; CHECK-P8-NEXT: addis r4, r2, b@toc@ha
; CHECK-P8-NEXT: addi r3, r3, a@toc@l ; CHECK-P8-NEXT: addi r3, r3, a@toc@l
; CHECK-P8-NEXT: addi r4, r4, b@toc@l ; CHECK-P8-NEXT: addi r4, r4, b@toc@l
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: lxvd2x vs1, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
Show All 22 Lines
; ;
; CHECK-P8-LABEL: qpCeil: ; CHECK-P8-LABEL: qpCeil:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: mr r30, r4 ; CHECK-P8-NEXT: mr r30, r4
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl ceilf128 ; CHECK-P8-NEXT: bl ceilf128
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
Show All 17 Lines
; ;
; CHECK-P8-LABEL: qpFloor: ; CHECK-P8-LABEL: qpFloor:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: mr r30, r4 ; CHECK-P8-NEXT: mr r30, r4
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl floorf128 ; CHECK-P8-NEXT: bl floorf128
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
Show All 17 Lines
; ;
; CHECK-P8-LABEL: qpTrunc: ; CHECK-P8-LABEL: qpTrunc:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: mr r30, r4 ; CHECK-P8-NEXT: mr r30, r4
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl truncf128 ; CHECK-P8-NEXT: bl truncf128
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
Show All 17 Lines
; ;
; CHECK-P8-LABEL: qpRound: ; CHECK-P8-LABEL: qpRound:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: mr r30, r4 ; CHECK-P8-NEXT: mr r30, r4
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl roundf128 ; CHECK-P8-NEXT: bl roundf128
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
Show All 10 Lines
define dso_local void @qpLRound(ptr nocapture readonly %a, ptr nocapture %res) { define dso_local void @qpLRound(ptr nocapture readonly %a, ptr nocapture %res) {
; CHECK-LABEL: qpLRound: ; CHECK-LABEL: qpLRound:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr r0 ; CHECK-NEXT: mflr r0
; CHECK-NEXT: .cfi_def_cfa_offset 48 ; CHECK-NEXT: .cfi_def_cfa_offset 48
; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: .cfi_offset r30, -16 ; CHECK-NEXT: .cfi_offset r30, -16
; CHECK-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-NEXT: std r0, 16(r1)
; CHECK-NEXT: stdu r1, -48(r1) ; CHECK-NEXT: stdu r1, -48(r1)
; CHECK-NEXT: lxv v2, 0(r3) ; CHECK-NEXT: std r0, 64(r1)
; CHECK-NEXT: mr r30, r4 ; CHECK-NEXT: mr r30, r4
; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: bl lroundf128 ; CHECK-NEXT: bl lroundf128
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: stw r3, 0(r30) ; CHECK-NEXT: stw r3, 0(r30)
; CHECK-NEXT: addi r1, r1, 48 ; CHECK-NEXT: addi r1, r1, 48
; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: ld r0, 16(r1)
; CHECK-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: mtlr r0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: qpLRound: ; CHECK-P8-LABEL: qpLRound:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: mr r30, r4 ; CHECK-P8-NEXT: mr r30, r4
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl lroundf128 ; CHECK-P8-NEXT: bl lroundf128
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stw r3, 0(r30) ; CHECK-P8-NEXT: stw r3, 0(r30)
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
Show All 9 Lines
define dso_local void @qpLLRound(ptr nocapture readonly %a, ptr nocapture %res) { define dso_local void @qpLLRound(ptr nocapture readonly %a, ptr nocapture %res) {
; CHECK-LABEL: qpLLRound: ; CHECK-LABEL: qpLLRound:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr r0 ; CHECK-NEXT: mflr r0
; CHECK-NEXT: .cfi_def_cfa_offset 48 ; CHECK-NEXT: .cfi_def_cfa_offset 48
; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: .cfi_offset r30, -16 ; CHECK-NEXT: .cfi_offset r30, -16
; CHECK-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-NEXT: std r0, 16(r1)
; CHECK-NEXT: stdu r1, -48(r1) ; CHECK-NEXT: stdu r1, -48(r1)
; CHECK-NEXT: lxv v2, 0(r3) ; CHECK-NEXT: std r0, 64(r1)
; CHECK-NEXT: mr r30, r4 ; CHECK-NEXT: mr r30, r4
; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: bl llroundf128 ; CHECK-NEXT: bl llroundf128
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: std r3, 0(r30) ; CHECK-NEXT: std r3, 0(r30)
; CHECK-NEXT: addi r1, r1, 48 ; CHECK-NEXT: addi r1, r1, 48
; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: ld r0, 16(r1)
; CHECK-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: mtlr r0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: qpLLRound: ; CHECK-P8-LABEL: qpLLRound:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: mr r30, r4 ; CHECK-P8-NEXT: mr r30, r4
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl llroundf128 ; CHECK-P8-NEXT: bl llroundf128
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: std r3, 0(r30) ; CHECK-P8-NEXT: std r3, 0(r30)
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
Show All 16 Lines
; ;
; CHECK-P8-LABEL: qpRint: ; CHECK-P8-LABEL: qpRint:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: mr r30, r4 ; CHECK-P8-NEXT: mr r30, r4
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl rintf128 ; CHECK-P8-NEXT: bl rintf128
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
Show All 10 Lines
define dso_local void @qpLRint(ptr nocapture readonly %a, ptr nocapture %res) { define dso_local void @qpLRint(ptr nocapture readonly %a, ptr nocapture %res) {
; CHECK-LABEL: qpLRint: ; CHECK-LABEL: qpLRint:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr r0 ; CHECK-NEXT: mflr r0
; CHECK-NEXT: .cfi_def_cfa_offset 48 ; CHECK-NEXT: .cfi_def_cfa_offset 48
; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: .cfi_offset r30, -16 ; CHECK-NEXT: .cfi_offset r30, -16
; CHECK-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-NEXT: std r0, 16(r1)
; CHECK-NEXT: stdu r1, -48(r1) ; CHECK-NEXT: stdu r1, -48(r1)
; CHECK-NEXT: lxv v2, 0(r3) ; CHECK-NEXT: std r0, 64(r1)
; CHECK-NEXT: mr r30, r4 ; CHECK-NEXT: mr r30, r4
; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: bl lrintf128 ; CHECK-NEXT: bl lrintf128
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: stw r3, 0(r30) ; CHECK-NEXT: stw r3, 0(r30)
; CHECK-NEXT: addi r1, r1, 48 ; CHECK-NEXT: addi r1, r1, 48
; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: ld r0, 16(r1)
; CHECK-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: mtlr r0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: qpLRint: ; CHECK-P8-LABEL: qpLRint:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: mr r30, r4 ; CHECK-P8-NEXT: mr r30, r4
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl lrintf128 ; CHECK-P8-NEXT: bl lrintf128
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stw r3, 0(r30) ; CHECK-P8-NEXT: stw r3, 0(r30)
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
Show All 9 Lines
define dso_local void @qpLLRint(ptr nocapture readonly %a, ptr nocapture %res) { define dso_local void @qpLLRint(ptr nocapture readonly %a, ptr nocapture %res) {
; CHECK-LABEL: qpLLRint: ; CHECK-LABEL: qpLLRint:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr r0 ; CHECK-NEXT: mflr r0
; CHECK-NEXT: .cfi_def_cfa_offset 48 ; CHECK-NEXT: .cfi_def_cfa_offset 48
; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: .cfi_offset r30, -16 ; CHECK-NEXT: .cfi_offset r30, -16
; CHECK-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-NEXT: std r0, 16(r1)
; CHECK-NEXT: stdu r1, -48(r1) ; CHECK-NEXT: stdu r1, -48(r1)
; CHECK-NEXT: lxv v2, 0(r3) ; CHECK-NEXT: std r0, 64(r1)
; CHECK-NEXT: mr r30, r4 ; CHECK-NEXT: mr r30, r4
; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: bl llrintf128 ; CHECK-NEXT: bl llrintf128
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: std r3, 0(r30) ; CHECK-NEXT: std r3, 0(r30)
; CHECK-NEXT: addi r1, r1, 48 ; CHECK-NEXT: addi r1, r1, 48
; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: ld r0, 16(r1)
; CHECK-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: mtlr r0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: qpLLRint: ; CHECK-P8-LABEL: qpLLRint:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: mr r30, r4 ; CHECK-P8-NEXT: mr r30, r4
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl llrintf128 ; CHECK-P8-NEXT: bl llrintf128
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: std r3, 0(r30) ; CHECK-P8-NEXT: std r3, 0(r30)
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
Show All 16 Lines
; ;
; CHECK-P8-LABEL: qpNearByInt: ; CHECK-P8-LABEL: qpNearByInt:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: mr r30, r4 ; CHECK-P8-NEXT: mr r30, r4
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl nearbyintf128 ; CHECK-P8-NEXT: bl nearbyintf128
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
Show All 19 Lines
; ;
; CHECK-P8-LABEL: qpFMA: ; CHECK-P8-LABEL: qpFMA:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: mr r30, r6
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: lxvd2x vs1, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: mr r30, r6
; CHECK-P8-NEXT: lxvd2x vs2, 0, r5 ; CHECK-P8-NEXT: lxvd2x vs2, 0, r5
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxswapd v3, vs1 ; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: xxswapd v4, vs2 ; CHECK-P8-NEXT: xxswapd v4, vs2
; CHECK-P8-NEXT: bl fmaf128 ; CHECK-P8-NEXT: bl fmaf128
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
Show All 14 Lines

llvm/test/CodeGen/PowerPC/f128-branch-cond.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=powerpc64le-unknown-linux -mcpu=pwr8 -O0 < %s | \ ; RUN: llc -mtriple=powerpc64le-unknown-linux -mcpu=pwr8 -O0 < %s | \
; RUN: FileCheck %s -check-prefix=P8 ; RUN: FileCheck %s -check-prefix=P8
; RUN: llc -mtriple=powerpc64le-unknown-linux -mcpu=pwr9 -O0 < %s | \ ; RUN: llc -mtriple=powerpc64le-unknown-linux -mcpu=pwr9 -O0 < %s | \
; RUN: FileCheck %s -check-prefix=P9 ; RUN: FileCheck %s -check-prefix=P9
define i32 @test_choice1(fp128 %a, fp128 %b) #0 { define i32 @test_choice1(fp128 %a, fp128 %b) #0 {
; P8-LABEL: test_choice1: ; P8-LABEL: test_choice1:
; P8: # %bb.0: # %entry ; P8: # %bb.0: # %entry
; P8-NEXT: mflr 0 ; P8-NEXT: mflr 0
; P8-NEXT: std 0, 16(1)
; P8-NEXT: stdu 1, -112(1) ; P8-NEXT: stdu 1, -112(1)
; P8-NEXT: std 0, 128(1)
; P8-NEXT: bl __nekf2 ; P8-NEXT: bl __nekf2
; P8-NEXT: nop ; P8-NEXT: nop
; P8-NEXT: # kill: def $r3 killed $r3 killed $x3 ; P8-NEXT: # kill: def $r3 killed $r3 killed $x3
; P8-NEXT: cmplwi 3, 0 ; P8-NEXT: cmplwi 3, 0
; P8-NEXT: bne 0, .LBB0_2 ; P8-NEXT: bne 0, .LBB0_2
; P8-NEXT: b .LBB0_1 ; P8-NEXT: b .LBB0_1
; P8-NEXT: .LBB0_1: # %if.true ; P8-NEXT: .LBB0_1: # %if.true
; P8-NEXT: bl foo ; P8-NEXT: bl foo
Show All 10 Lines
; P8-NEXT: addi 1, 1, 112 ; P8-NEXT: addi 1, 1, 112
; P8-NEXT: ld 0, 16(1) ; P8-NEXT: ld 0, 16(1)
; P8-NEXT: mtlr 0 ; P8-NEXT: mtlr 0
; P8-NEXT: blr ; P8-NEXT: blr
; ;
; P9-LABEL: test_choice1: ; P9-LABEL: test_choice1:
; P9: # %bb.0: # %entry ; P9: # %bb.0: # %entry
; P9-NEXT: mflr 0 ; P9-NEXT: mflr 0
; P9-NEXT: std 0, 16(1)
; P9-NEXT: stdu 1, -112(1) ; P9-NEXT: stdu 1, -112(1)
; P9-NEXT: std 0, 128(1)
; P9-NEXT: xscmpuqp 0, 2, 3 ; P9-NEXT: xscmpuqp 0, 2, 3
; P9-NEXT: bne 0, .LBB0_2 ; P9-NEXT: bne 0, .LBB0_2
; P9-NEXT: b .LBB0_1 ; P9-NEXT: b .LBB0_1
; P9-NEXT: .LBB0_1: # %if.true ; P9-NEXT: .LBB0_1: # %if.true
; P9-NEXT: bl foo ; P9-NEXT: bl foo
; P9-NEXT: nop ; P9-NEXT: nop
; P9-NEXT: stw 3, 108(1) # 4-byte Folded Spill ; P9-NEXT: stw 3, 108(1) # 4-byte Folded Spill
; P9-NEXT: b .LBB0_3 ; P9-NEXT: b .LBB0_3
Show All 24 Linesfinal:
%result = phi i32 [%res1, %if.true], [%res2, %if.false] %result = phi i32 [%res1, %if.true], [%res2, %if.false]
ret i32 %result ret i32 %result
} }
define i32 @test_choice2(fp128 %a, fp128 %b) #0 { define i32 @test_choice2(fp128 %a, fp128 %b) #0 {
; P8-LABEL: test_choice2: ; P8-LABEL: test_choice2:
; P8: # %bb.0: # %entry ; P8: # %bb.0: # %entry
; P8-NEXT: mflr 0 ; P8-NEXT: mflr 0
; P8-NEXT: std 0, 16(1)
; P8-NEXT: stdu 1, -112(1) ; P8-NEXT: stdu 1, -112(1)
; P8-NEXT: std 0, 128(1)
; P8-NEXT: bl __lekf2 ; P8-NEXT: bl __lekf2
; P8-NEXT: nop ; P8-NEXT: nop
; P8-NEXT: # kill: def $r3 killed $r3 killed $x3 ; P8-NEXT: # kill: def $r3 killed $r3 killed $x3
; P8-NEXT: cmpwi 3, 1 ; P8-NEXT: cmpwi 3, 1
; P8-NEXT: blt 0, .LBB1_2 ; P8-NEXT: blt 0, .LBB1_2
; P8-NEXT: b .LBB1_1 ; P8-NEXT: b .LBB1_1
; P8-NEXT: .LBB1_1: # %if.true ; P8-NEXT: .LBB1_1: # %if.true
; P8-NEXT: bl foo ; P8-NEXT: bl foo
Show All 10 Lines
; P8-NEXT: addi 1, 1, 112 ; P8-NEXT: addi 1, 1, 112
; P8-NEXT: ld 0, 16(1) ; P8-NEXT: ld 0, 16(1)
; P8-NEXT: mtlr 0 ; P8-NEXT: mtlr 0
; P8-NEXT: blr ; P8-NEXT: blr
; ;
; P9-LABEL: test_choice2: ; P9-LABEL: test_choice2:
; P9: # %bb.0: # %entry ; P9: # %bb.0: # %entry
; P9-NEXT: mflr 0 ; P9-NEXT: mflr 0
; P9-NEXT: std 0, 16(1)
; P9-NEXT: stdu 1, -112(1) ; P9-NEXT: stdu 1, -112(1)
; P9-NEXT: std 0, 128(1)
; P9-NEXT: xscmpuqp 0, 2, 3 ; P9-NEXT: xscmpuqp 0, 2, 3
; P9-NEXT: crmove 20, 3 ; P9-NEXT: crmove 20, 3
; P9-NEXT: crnot 21, 20 ; P9-NEXT: crnot 21, 20
; P9-NEXT: crmove 20, 1 ; P9-NEXT: crmove 20, 1
; P9-NEXT: crnot 20, 20 ; P9-NEXT: crnot 20, 20
; P9-NEXT: crand 20, 20, 21 ; P9-NEXT: crand 20, 20, 21
; P9-NEXT: crxor 21, 21, 21 ; P9-NEXT: crxor 21, 21, 21
; P9-NEXT: crxor 20, 20, 21 ; P9-NEXT: crxor 20, 20, 21
Show All 31 Linesfinal:
%result = phi i32 [%res1, %if.true], [%res2, %if.false] %result = phi i32 [%res1, %if.true], [%res2, %if.false]
ret i32 %result ret i32 %result
} }
define i32 @test_choice3(fp128 %a, fp128 %b) #0 { define i32 @test_choice3(fp128 %a, fp128 %b) #0 {
; P8-LABEL: test_choice3: ; P8-LABEL: test_choice3:
; P8: # %bb.0: # %entry ; P8: # %bb.0: # %entry
; P8-NEXT: mflr 0 ; P8-NEXT: mflr 0
; P8-NEXT: std 0, 16(1)
; P8-NEXT: stdu 1, -112(1) ; P8-NEXT: stdu 1, -112(1)
; P8-NEXT: std 0, 128(1)
; P8-NEXT: bl __ltkf2 ; P8-NEXT: bl __ltkf2
; P8-NEXT: nop ; P8-NEXT: nop
; P8-NEXT: # kill: def $r3 killed $r3 killed $x3 ; P8-NEXT: # kill: def $r3 killed $r3 killed $x3
; P8-NEXT: cmpwi 3, -1 ; P8-NEXT: cmpwi 3, -1
; P8-NEXT: bgt 0, .LBB2_2 ; P8-NEXT: bgt 0, .LBB2_2
; P8-NEXT: b .LBB2_1 ; P8-NEXT: b .LBB2_1
; P8-NEXT: .LBB2_1: # %if.true ; P8-NEXT: .LBB2_1: # %if.true
; P8-NEXT: bl foo ; P8-NEXT: bl foo
Show All 10 Lines
; P8-NEXT: addi 1, 1, 112 ; P8-NEXT: addi 1, 1, 112
; P8-NEXT: ld 0, 16(1) ; P8-NEXT: ld 0, 16(1)
; P8-NEXT: mtlr 0 ; P8-NEXT: mtlr 0
; P8-NEXT: blr ; P8-NEXT: blr
; ;
; P9-LABEL: test_choice3: ; P9-LABEL: test_choice3:
; P9: # %bb.0: # %entry ; P9: # %bb.0: # %entry
; P9-NEXT: mflr 0 ; P9-NEXT: mflr 0
; P9-NEXT: std 0, 16(1)
; P9-NEXT: stdu 1, -112(1) ; P9-NEXT: stdu 1, -112(1)
; P9-NEXT: std 0, 128(1)
; P9-NEXT: xscmpuqp 0, 2, 3 ; P9-NEXT: xscmpuqp 0, 2, 3
; P9-NEXT: bge 0, .LBB2_2 ; P9-NEXT: bge 0, .LBB2_2
; P9-NEXT: b .LBB2_1 ; P9-NEXT: b .LBB2_1
; P9-NEXT: .LBB2_1: # %if.true ; P9-NEXT: .LBB2_1: # %if.true
; P9-NEXT: bl foo ; P9-NEXT: bl foo
; P9-NEXT: nop ; P9-NEXT: nop
; P9-NEXT: stw 3, 108(1) # 4-byte Folded Spill ; P9-NEXT: stw 3, 108(1) # 4-byte Folded Spill
; P9-NEXT: b .LBB2_3 ; P9-NEXT: b .LBB2_3
Show All 24 Linesfinal:
%result = phi i32 [%res1, %if.true], [%res2, %if.false] %result = phi i32 [%res1, %if.true], [%res2, %if.false]
ret i32 %result ret i32 %result
} }
define i32 @test_choice4(fp128 %a, fp128 %b) #0 { define i32 @test_choice4(fp128 %a, fp128 %b) #0 {
; P8-LABEL: test_choice4: ; P8-LABEL: test_choice4:
; P8: # %bb.0: # %entry ; P8: # %bb.0: # %entry
; P8-NEXT: mflr 0 ; P8-NEXT: mflr 0
; P8-NEXT: std 0, 16(1)
; P8-NEXT: stdu 1, -112(1) ; P8-NEXT: stdu 1, -112(1)
; P8-NEXT: std 0, 128(1)
; P8-NEXT: bl __eqkf2 ; P8-NEXT: bl __eqkf2
; P8-NEXT: nop ; P8-NEXT: nop
; P8-NEXT: # kill: def $r3 killed $r3 killed $x3 ; P8-NEXT: # kill: def $r3 killed $r3 killed $x3
; P8-NEXT: cmplwi 3, 0 ; P8-NEXT: cmplwi 3, 0
; P8-NEXT: beq 0, .LBB3_2 ; P8-NEXT: beq 0, .LBB3_2
; P8-NEXT: b .LBB3_1 ; P8-NEXT: b .LBB3_1
; P8-NEXT: .LBB3_1: # %if.true ; P8-NEXT: .LBB3_1: # %if.true
; P8-NEXT: bl foo ; P8-NEXT: bl foo
Show All 10 Lines
; P8-NEXT: addi 1, 1, 112 ; P8-NEXT: addi 1, 1, 112
; P8-NEXT: ld 0, 16(1) ; P8-NEXT: ld 0, 16(1)
; P8-NEXT: mtlr 0 ; P8-NEXT: mtlr 0
; P8-NEXT: blr ; P8-NEXT: blr
; ;
; P9-LABEL: test_choice4: ; P9-LABEL: test_choice4:
; P9: # %bb.0: # %entry ; P9: # %bb.0: # %entry
; P9-NEXT: mflr 0 ; P9-NEXT: mflr 0
; P9-NEXT: std 0, 16(1)
; P9-NEXT: stdu 1, -112(1) ; P9-NEXT: stdu 1, -112(1)
; P9-NEXT: std 0, 128(1)
; P9-NEXT: xscmpuqp 0, 2, 3 ; P9-NEXT: xscmpuqp 0, 2, 3
; P9-NEXT: beq 0, .LBB3_2 ; P9-NEXT: beq 0, .LBB3_2
; P9-NEXT: b .LBB3_1 ; P9-NEXT: b .LBB3_1
; P9-NEXT: .LBB3_1: # %if.true ; P9-NEXT: .LBB3_1: # %if.true
; P9-NEXT: bl foo ; P9-NEXT: bl foo
; P9-NEXT: nop ; P9-NEXT: nop
; P9-NEXT: stw 3, 108(1) # 4-byte Folded Spill ; P9-NEXT: stw 3, 108(1) # 4-byte Folded Spill
; P9-NEXT: b .LBB3_3 ; P9-NEXT: b .LBB3_3
Show All 32 Lines

llvm/test/CodeGen/PowerPC/f128-compare.ll

Show All 21 Lines
; CHECK-NEXT: li r3, 0 ; CHECK-NEXT: li r3, 0
; CHECK-NEXT: xscmpuqp cr0, v2, v3 ; CHECK-NEXT: xscmpuqp cr0, v2, v3
; CHECK-NEXT: iselgt r3, r4, r3 ; CHECK-NEXT: iselgt r3, r4, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: greater_qp: ; CHECK-P8-LABEL: greater_qp:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: std r0, 48(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: addis r3, r2, a_qp@toc@ha ; CHECK-P8-NEXT: addis r3, r2, a_qp@toc@ha
; CHECK-P8-NEXT: addis r4, r2, b_qp@toc@ha ; CHECK-P8-NEXT: addis r4, r2, b_qp@toc@ha
; CHECK-P8-NEXT: addi r3, r3, a_qp@toc@l ; CHECK-P8-NEXT: addi r3, r3, a_qp@toc@l
; CHECK-P8-NEXT: addi r4, r4, b_qp@toc@l ; CHECK-P8-NEXT: addi r4, r4, b_qp@toc@l
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: lxvd2x vs1, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
Show All 30 Lines
; CHECK-NEXT: li r3, 0 ; CHECK-NEXT: li r3, 0
; CHECK-NEXT: xscmpuqp cr0, v2, v3 ; CHECK-NEXT: xscmpuqp cr0, v2, v3
; CHECK-NEXT: isellt r3, r4, r3 ; CHECK-NEXT: isellt r3, r4, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: less_qp: ; CHECK-P8-LABEL: less_qp:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: std r0, 48(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: addis r3, r2, a_qp@toc@ha ; CHECK-P8-NEXT: addis r3, r2, a_qp@toc@ha
; CHECK-P8-NEXT: addis r4, r2, b_qp@toc@ha ; CHECK-P8-NEXT: addis r4, r2, b_qp@toc@ha
; CHECK-P8-NEXT: addi r3, r3, a_qp@toc@l ; CHECK-P8-NEXT: addi r3, r3, a_qp@toc@l
; CHECK-P8-NEXT: addi r4, r4, b_qp@toc@l ; CHECK-P8-NEXT: addi r4, r4, b_qp@toc@l
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: lxvd2x vs1, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
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; CHECK-NEXT: xscmpuqp cr0, v2, v3 ; CHECK-NEXT: xscmpuqp cr0, v2, v3
; CHECK-NEXT: cror 4*cr5+lt, un, lt ; CHECK-NEXT: cror 4*cr5+lt, un, lt
; CHECK-NEXT: isel r3, 0, r3, 4*cr5+lt ; CHECK-NEXT: isel r3, 0, r3, 4*cr5+lt
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: greater_eq_qp: ; CHECK-P8-LABEL: greater_eq_qp:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: std r0, 48(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: addis r3, r2, a_qp@toc@ha ; CHECK-P8-NEXT: addis r3, r2, a_qp@toc@ha
; CHECK-P8-NEXT: addis r4, r2, b_qp@toc@ha ; CHECK-P8-NEXT: addis r4, r2, b_qp@toc@ha
; CHECK-P8-NEXT: addi r3, r3, a_qp@toc@l ; CHECK-P8-NEXT: addi r3, r3, a_qp@toc@l
; CHECK-P8-NEXT: addi r4, r4, b_qp@toc@l ; CHECK-P8-NEXT: addi r4, r4, b_qp@toc@l
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: lxvd2x vs1, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
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; CHECK-NEXT: xscmpuqp cr0, v2, v3 ; CHECK-NEXT: xscmpuqp cr0, v2, v3
; CHECK-NEXT: cror 4*cr5+lt, un, gt ; CHECK-NEXT: cror 4*cr5+lt, un, gt
; CHECK-NEXT: isel r3, 0, r3, 4*cr5+lt ; CHECK-NEXT: isel r3, 0, r3, 4*cr5+lt
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: less_eq_qp: ; CHECK-P8-LABEL: less_eq_qp:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: std r0, 48(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: addis r3, r2, a_qp@toc@ha ; CHECK-P8-NEXT: addis r3, r2, a_qp@toc@ha
; CHECK-P8-NEXT: addis r4, r2, b_qp@toc@ha ; CHECK-P8-NEXT: addis r4, r2, b_qp@toc@ha
; CHECK-P8-NEXT: addi r3, r3, a_qp@toc@l ; CHECK-P8-NEXT: addi r3, r3, a_qp@toc@l
; CHECK-P8-NEXT: addi r4, r4, b_qp@toc@l ; CHECK-P8-NEXT: addi r4, r4, b_qp@toc@l
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: lxvd2x vs1, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
Show All 31 Lines
; CHECK-NEXT: li r3, 0 ; CHECK-NEXT: li r3, 0
; CHECK-NEXT: xscmpuqp cr0, v2, v3 ; CHECK-NEXT: xscmpuqp cr0, v2, v3
; CHECK-NEXT: iseleq r3, r4, r3 ; CHECK-NEXT: iseleq r3, r4, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: equal_qp: ; CHECK-P8-LABEL: equal_qp:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: std r0, 48(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: addis r3, r2, a_qp@toc@ha ; CHECK-P8-NEXT: addis r3, r2, a_qp@toc@ha
; CHECK-P8-NEXT: addis r4, r2, b_qp@toc@ha ; CHECK-P8-NEXT: addis r4, r2, b_qp@toc@ha
; CHECK-P8-NEXT: addi r3, r3, a_qp@toc@l ; CHECK-P8-NEXT: addi r3, r3, a_qp@toc@l
; CHECK-P8-NEXT: addi r4, r4, b_qp@toc@l ; CHECK-P8-NEXT: addi r4, r4, b_qp@toc@l
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: lxvd2x vs1, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
Show All 28 Lines
; CHECK-NEXT: li r3, 1 ; CHECK-NEXT: li r3, 1
; CHECK-NEXT: xscmpuqp cr0, v2, v3 ; CHECK-NEXT: xscmpuqp cr0, v2, v3
; CHECK-NEXT: iselgt r3, 0, r3 ; CHECK-NEXT: iselgt r3, 0, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: not_greater_qp: ; CHECK-P8-LABEL: not_greater_qp:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: std r0, 48(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: addis r3, r2, a_qp@toc@ha ; CHECK-P8-NEXT: addis r3, r2, a_qp@toc@ha
; CHECK-P8-NEXT: addis r4, r2, b_qp@toc@ha ; CHECK-P8-NEXT: addis r4, r2, b_qp@toc@ha
; CHECK-P8-NEXT: addi r3, r3, a_qp@toc@l ; CHECK-P8-NEXT: addi r3, r3, a_qp@toc@l
; CHECK-P8-NEXT: addi r4, r4, b_qp@toc@l ; CHECK-P8-NEXT: addi r4, r4, b_qp@toc@l
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: lxvd2x vs1, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
Show All 31 Lines
; CHECK-NEXT: li r3, 1 ; CHECK-NEXT: li r3, 1
; CHECK-NEXT: xscmpuqp cr0, v2, v3 ; CHECK-NEXT: xscmpuqp cr0, v2, v3
; CHECK-NEXT: isellt r3, 0, r3 ; CHECK-NEXT: isellt r3, 0, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: not_less_qp: ; CHECK-P8-LABEL: not_less_qp:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: std r0, 48(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: addis r3, r2, a_qp@toc@ha ; CHECK-P8-NEXT: addis r3, r2, a_qp@toc@ha
; CHECK-P8-NEXT: addis r4, r2, b_qp@toc@ha ; CHECK-P8-NEXT: addis r4, r2, b_qp@toc@ha
; CHECK-P8-NEXT: addi r3, r3, a_qp@toc@l ; CHECK-P8-NEXT: addi r3, r3, a_qp@toc@l
; CHECK-P8-NEXT: addi r4, r4, b_qp@toc@l ; CHECK-P8-NEXT: addi r4, r4, b_qp@toc@l
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: lxvd2x vs1, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
Show All 30 Lines
; CHECK-NEXT: xscmpuqp cr0, v2, v3 ; CHECK-NEXT: xscmpuqp cr0, v2, v3
; CHECK-NEXT: crnor 4*cr5+lt, lt, un ; CHECK-NEXT: crnor 4*cr5+lt, lt, un
; CHECK-NEXT: isel r3, 0, r3, 4*cr5+lt ; CHECK-NEXT: isel r3, 0, r3, 4*cr5+lt
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: not_greater_eq_qp: ; CHECK-P8-LABEL: not_greater_eq_qp:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: std r0, 48(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: addis r3, r2, a_qp@toc@ha ; CHECK-P8-NEXT: addis r3, r2, a_qp@toc@ha
; CHECK-P8-NEXT: addis r4, r2, b_qp@toc@ha ; CHECK-P8-NEXT: addis r4, r2, b_qp@toc@ha
; CHECK-P8-NEXT: addi r3, r3, a_qp@toc@l ; CHECK-P8-NEXT: addi r3, r3, a_qp@toc@l
; CHECK-P8-NEXT: addi r4, r4, b_qp@toc@l ; CHECK-P8-NEXT: addi r4, r4, b_qp@toc@l
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: lxvd2x vs1, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
Show All 29 Lines
; CHECK-NEXT: xscmpuqp cr0, v2, v3 ; CHECK-NEXT: xscmpuqp cr0, v2, v3
; CHECK-NEXT: crnor 4*cr5+lt, gt, un ; CHECK-NEXT: crnor 4*cr5+lt, gt, un
; CHECK-NEXT: isel r3, 0, r3, 4*cr5+lt ; CHECK-NEXT: isel r3, 0, r3, 4*cr5+lt
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: not_less_eq_qp: ; CHECK-P8-LABEL: not_less_eq_qp:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: std r0, 48(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: addis r3, r2, a_qp@toc@ha ; CHECK-P8-NEXT: addis r3, r2, a_qp@toc@ha
; CHECK-P8-NEXT: addis r4, r2, b_qp@toc@ha ; CHECK-P8-NEXT: addis r4, r2, b_qp@toc@ha
; CHECK-P8-NEXT: addi r3, r3, a_qp@toc@l ; CHECK-P8-NEXT: addi r3, r3, a_qp@toc@l
; CHECK-P8-NEXT: addi r4, r4, b_qp@toc@l ; CHECK-P8-NEXT: addi r4, r4, b_qp@toc@l
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: lxvd2x vs1, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
Show All 30 Lines
; CHECK-NEXT: li r3, 1 ; CHECK-NEXT: li r3, 1
; CHECK-NEXT: xscmpuqp cr0, v2, v3 ; CHECK-NEXT: xscmpuqp cr0, v2, v3
; CHECK-NEXT: iseleq r3, 0, r3 ; CHECK-NEXT: iseleq r3, 0, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: not_equal_qp: ; CHECK-P8-LABEL: not_equal_qp:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: std r0, 48(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: addis r3, r2, a_qp@toc@ha ; CHECK-P8-NEXT: addis r3, r2, a_qp@toc@ha
; CHECK-P8-NEXT: addis r4, r2, b_qp@toc@ha ; CHECK-P8-NEXT: addis r4, r2, b_qp@toc@ha
; CHECK-P8-NEXT: addi r3, r3, a_qp@toc@l ; CHECK-P8-NEXT: addi r3, r3, a_qp@toc@l
; CHECK-P8-NEXT: addi r4, r4, b_qp@toc@l ; CHECK-P8-NEXT: addi r4, r4, b_qp@toc@l
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: lxvd2x vs1, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
Show All 30 Lines
; CHECK-NEXT: bgtlr cr0 ; CHECK-NEXT: bgtlr cr0
; CHECK-NEXT: # %bb.1: # %entry ; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: vmr v2, v3 ; CHECK-NEXT: vmr v2, v3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: greater_sel_qp: ; CHECK-P8-LABEL: greater_sel_qp:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -80(r1) ; CHECK-P8-NEXT: stdu r1, -80(r1)
; CHECK-P8-NEXT: std r0, 96(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 80 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 80
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset v30, -32 ; CHECK-P8-NEXT: .cfi_offset v30, -32
; CHECK-P8-NEXT: .cfi_offset v31, -16 ; CHECK-P8-NEXT: .cfi_offset v31, -16
; CHECK-P8-NEXT: li r3, 48 ; CHECK-P8-NEXT: li r3, 48
; CHECK-P8-NEXT: addis r4, r2, b_qp@toc@ha ; CHECK-P8-NEXT: addis r4, r2, b_qp@toc@ha
; CHECK-P8-NEXT: stvx v30, r1, r3 # 16-byte Folded Spill ; CHECK-P8-NEXT: stvx v30, r1, r3 # 16-byte Folded Spill
; CHECK-P8-NEXT: li r3, 64 ; CHECK-P8-NEXT: li r3, 64
▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Lines
; CHECK-NEXT: bltlr cr0 ; CHECK-NEXT: bltlr cr0
; CHECK-NEXT: # %bb.1: # %entry ; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: vmr v2, v3 ; CHECK-NEXT: vmr v2, v3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: less_sel_qp: ; CHECK-P8-LABEL: less_sel_qp:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -80(r1) ; CHECK-P8-NEXT: stdu r1, -80(r1)
; CHECK-P8-NEXT: std r0, 96(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 80 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 80
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset v30, -32 ; CHECK-P8-NEXT: .cfi_offset v30, -32
; CHECK-P8-NEXT: .cfi_offset v31, -16 ; CHECK-P8-NEXT: .cfi_offset v31, -16
; CHECK-P8-NEXT: li r3, 48 ; CHECK-P8-NEXT: li r3, 48
; CHECK-P8-NEXT: addis r4, r2, b_qp@toc@ha ; CHECK-P8-NEXT: addis r4, r2, b_qp@toc@ha
; CHECK-P8-NEXT: stvx v30, r1, r3 # 16-byte Folded Spill ; CHECK-P8-NEXT: stvx v30, r1, r3 # 16-byte Folded Spill
; CHECK-P8-NEXT: li r3, 64 ; CHECK-P8-NEXT: li r3, 64
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
; CHECK-NEXT: bclr 12, 4*cr5+lt, 0 ; CHECK-NEXT: bclr 12, 4*cr5+lt, 0
; CHECK-NEXT: # %bb.1: # %entry ; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: vmr v2, v3 ; CHECK-NEXT: vmr v2, v3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: greater_eq_sel_qp: ; CHECK-P8-LABEL: greater_eq_sel_qp:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -80(r1) ; CHECK-P8-NEXT: stdu r1, -80(r1)
; CHECK-P8-NEXT: std r0, 96(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 80 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 80
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset v30, -32 ; CHECK-P8-NEXT: .cfi_offset v30, -32
; CHECK-P8-NEXT: .cfi_offset v31, -16 ; CHECK-P8-NEXT: .cfi_offset v31, -16
; CHECK-P8-NEXT: li r3, 48 ; CHECK-P8-NEXT: li r3, 48
; CHECK-P8-NEXT: addis r4, r2, b_qp@toc@ha ; CHECK-P8-NEXT: addis r4, r2, b_qp@toc@ha
; CHECK-P8-NEXT: stvx v30, r1, r3 # 16-byte Folded Spill ; CHECK-P8-NEXT: stvx v30, r1, r3 # 16-byte Folded Spill
; CHECK-P8-NEXT: li r3, 64 ; CHECK-P8-NEXT: li r3, 64
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
; CHECK-NEXT: bclr 12, 4*cr5+lt, 0 ; CHECK-NEXT: bclr 12, 4*cr5+lt, 0
; CHECK-NEXT: # %bb.1: # %entry ; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: vmr v2, v3 ; CHECK-NEXT: vmr v2, v3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: less_eq_sel_qp: ; CHECK-P8-LABEL: less_eq_sel_qp:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -80(r1) ; CHECK-P8-NEXT: stdu r1, -80(r1)
; CHECK-P8-NEXT: std r0, 96(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 80 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 80
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset v30, -32 ; CHECK-P8-NEXT: .cfi_offset v30, -32
; CHECK-P8-NEXT: .cfi_offset v31, -16 ; CHECK-P8-NEXT: .cfi_offset v31, -16
; CHECK-P8-NEXT: li r3, 48 ; CHECK-P8-NEXT: li r3, 48
; CHECK-P8-NEXT: addis r4, r2, b_qp@toc@ha ; CHECK-P8-NEXT: addis r4, r2, b_qp@toc@ha
; CHECK-P8-NEXT: stvx v30, r1, r3 # 16-byte Folded Spill ; CHECK-P8-NEXT: stvx v30, r1, r3 # 16-byte Folded Spill
; CHECK-P8-NEXT: li r3, 64 ; CHECK-P8-NEXT: li r3, 64
▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Lines
; CHECK-NEXT: beqlr cr0 ; CHECK-NEXT: beqlr cr0
; CHECK-NEXT: # %bb.1: # %entry ; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: vmr v2, v3 ; CHECK-NEXT: vmr v2, v3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: equal_sel_qp: ; CHECK-P8-LABEL: equal_sel_qp:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -80(r1) ; CHECK-P8-NEXT: stdu r1, -80(r1)
; CHECK-P8-NEXT: std r0, 96(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 80 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 80
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset v30, -32 ; CHECK-P8-NEXT: .cfi_offset v30, -32
; CHECK-P8-NEXT: .cfi_offset v31, -16 ; CHECK-P8-NEXT: .cfi_offset v31, -16
; CHECK-P8-NEXT: li r3, 48 ; CHECK-P8-NEXT: li r3, 48
; CHECK-P8-NEXT: addis r4, r2, b_qp@toc@ha ; CHECK-P8-NEXT: addis r4, r2, b_qp@toc@ha
; CHECK-P8-NEXT: stvx v30, r1, r3 # 16-byte Folded Spill ; CHECK-P8-NEXT: stvx v30, r1, r3 # 16-byte Folded Spill
; CHECK-P8-NEXT: li r3, 64 ; CHECK-P8-NEXT: li r3, 64
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llvm/test/CodeGen/PowerPC/f128-conv.ll

Show All 23 Lines
; ;
; CHECK-P8-LABEL: sdwConv2qp: ; CHECK-P8-LABEL: sdwConv2qp:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: mr r3, r4 ; CHECK-P8-NEXT: mr r3, r4
; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: bl __floatdikf ; CHECK-P8-NEXT: bl __floatdikf
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
Show All 9 Lines
define void @sdwConv2qp_01(ptr nocapture %a, i128 %b) { define void @sdwConv2qp_01(ptr nocapture %a, i128 %b) {
; CHECK-LABEL: sdwConv2qp_01: ; CHECK-LABEL: sdwConv2qp_01:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr r0 ; CHECK-NEXT: mflr r0
; CHECK-NEXT: .cfi_def_cfa_offset 48 ; CHECK-NEXT: .cfi_def_cfa_offset 48
; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: .cfi_offset r30, -16 ; CHECK-NEXT: .cfi_offset r30, -16
; CHECK-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-NEXT: std r0, 16(r1)
; CHECK-NEXT: stdu r1, -48(r1) ; CHECK-NEXT: stdu r1, -48(r1)
; CHECK-NEXT: mr r30, r3 ; CHECK-NEXT: mr r30, r3
; CHECK-NEXT: mr r3, r4 ; CHECK-NEXT: mr r3, r4
; CHECK-NEXT: mr r4, r5 ; CHECK-NEXT: mr r4, r5
; CHECK-NEXT: std r0, 64(r1)
; CHECK-NEXT: bl __floattikf ; CHECK-NEXT: bl __floattikf
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: stxv v2, 0(r30) ; CHECK-NEXT: stxv v2, 0(r30)
; CHECK-NEXT: addi r1, r1, 48 ; CHECK-NEXT: addi r1, r1, 48
; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: ld r0, 16(r1)
; CHECK-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: mtlr r0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: sdwConv2qp_01: ; CHECK-P8-LABEL: sdwConv2qp_01:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: mr r3, r4 ; CHECK-P8-NEXT: mr r3, r4
; CHECK-P8-NEXT: mr r4, r5 ; CHECK-P8-NEXT: mr r4, r5
; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: bl __floattikf ; CHECK-P8-NEXT: bl __floattikf
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
Show All 18 Lines
; ;
; CHECK-P8-LABEL: sdwConv2qp_02: ; CHECK-P8-LABEL: sdwConv2qp_02:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-P8-NEXT: ld r4, 16(r4) ; CHECK-P8-NEXT: ld r4, 16(r4)
; CHECK-P8-NEXT: mr r3, r4 ; CHECK-P8-NEXT: mr r3, r4
; CHECK-P8-NEXT: bl __floatdikf ; CHECK-P8-NEXT: bl __floatdikf
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
Show All 22 Lines
; ;
; CHECK-P8-LABEL: sdwConv2qp_03: ; CHECK-P8-LABEL: sdwConv2qp_03:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: ld r4, 0(r4) ; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: ld r4, 0(r4)
; CHECK-P8-NEXT: mr r3, r4 ; CHECK-P8-NEXT: mr r3, r4
; CHECK-P8-NEXT: bl __floatdikf ; CHECK-P8-NEXT: bl __floatdikf
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
Show All 22 Lines
; ;
; CHECK-P8-LABEL: sdwConv2qp_04: ; CHECK-P8-LABEL: sdwConv2qp_04:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: andi. r3, r4, 1 ; CHECK-P8-NEXT: andi. r3, r4, 1
; CHECK-P8-NEXT: li r4, -1 ; CHECK-P8-NEXT: li r4, -1
; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: li r3, 0 ; CHECK-P8-NEXT: li r3, 0
; CHECK-P8-NEXT: iselgt r3, r4, r3 ; CHECK-P8-NEXT: iselgt r3, r4, r3
; CHECK-P8-NEXT: bl __floatsikf ; CHECK-P8-NEXT: bl __floatsikf
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
Show All 18 Lines
; ;
; CHECK-P8-LABEL: udwConv2qp: ; CHECK-P8-LABEL: udwConv2qp:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: mr r3, r4 ; CHECK-P8-NEXT: mr r3, r4
; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: bl __floatundikf ; CHECK-P8-NEXT: bl __floatundikf
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
Show All 9 Lines
define void @udwConv2qp_01(ptr nocapture %a, i128 %b) { define void @udwConv2qp_01(ptr nocapture %a, i128 %b) {
; CHECK-LABEL: udwConv2qp_01: ; CHECK-LABEL: udwConv2qp_01:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr r0 ; CHECK-NEXT: mflr r0
; CHECK-NEXT: .cfi_def_cfa_offset 48 ; CHECK-NEXT: .cfi_def_cfa_offset 48
; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: .cfi_offset r30, -16 ; CHECK-NEXT: .cfi_offset r30, -16
; CHECK-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-NEXT: std r0, 16(r1)
; CHECK-NEXT: stdu r1, -48(r1) ; CHECK-NEXT: stdu r1, -48(r1)
; CHECK-NEXT: mr r30, r3 ; CHECK-NEXT: mr r30, r3
; CHECK-NEXT: mr r3, r4 ; CHECK-NEXT: mr r3, r4
; CHECK-NEXT: mr r4, r5 ; CHECK-NEXT: mr r4, r5
; CHECK-NEXT: std r0, 64(r1)
; CHECK-NEXT: bl __floatuntikf ; CHECK-NEXT: bl __floatuntikf
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: stxv v2, 0(r30) ; CHECK-NEXT: stxv v2, 0(r30)
; CHECK-NEXT: addi r1, r1, 48 ; CHECK-NEXT: addi r1, r1, 48
; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: ld r0, 16(r1)
; CHECK-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: mtlr r0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: udwConv2qp_01: ; CHECK-P8-LABEL: udwConv2qp_01:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: mr r3, r4 ; CHECK-P8-NEXT: mr r3, r4
; CHECK-P8-NEXT: mr r4, r5 ; CHECK-P8-NEXT: mr r4, r5
; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: bl __floatuntikf ; CHECK-P8-NEXT: bl __floatuntikf
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
Show All 18 Lines
; ;
; CHECK-P8-LABEL: udwConv2qp_02: ; CHECK-P8-LABEL: udwConv2qp_02:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: addis r4, r2, .LC1@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LC1@toc@ha
; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: ld r4, .LC1@toc@l(r4) ; CHECK-P8-NEXT: ld r4, .LC1@toc@l(r4)
; CHECK-P8-NEXT: ld r4, 32(r4) ; CHECK-P8-NEXT: ld r4, 32(r4)
; CHECK-P8-NEXT: mr r3, r4 ; CHECK-P8-NEXT: mr r3, r4
; CHECK-P8-NEXT: bl __floatundikf ; CHECK-P8-NEXT: bl __floatundikf
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
Show All 22 Lines
; ;
; CHECK-P8-LABEL: udwConv2qp_03: ; CHECK-P8-LABEL: udwConv2qp_03:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: ld r4, 0(r4) ; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: ld r4, 0(r4)
; CHECK-P8-NEXT: mr r3, r4 ; CHECK-P8-NEXT: mr r3, r4
; CHECK-P8-NEXT: bl __floatundikf ; CHECK-P8-NEXT: bl __floatundikf
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
Show All 19 Lines
; ;
; CHECK-P8-LABEL: udwConv2qp_04: ; CHECK-P8-LABEL: udwConv2qp_04:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: clrldi r3, r4, 63 ; CHECK-P8-NEXT: clrldi r3, r4, 63
; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: bl __floatsikf ; CHECK-P8-NEXT: bl __floatsikf
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
Show All 18 Lines
; ;
; CHECK-P8-LABEL: sdwConv2qp_testXForm: ; CHECK-P8-LABEL: sdwConv2qp_testXForm:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: lis r5, 1 ; CHECK-P8-NEXT: lis r5, 1
; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: ori r5, r5, 7797 ; CHECK-P8-NEXT: ori r5, r5, 7797
; CHECK-P8-NEXT: ldx r4, r4, r5 ; CHECK-P8-NEXT: ldx r4, r4, r5
; CHECK-P8-NEXT: mr r3, r4 ; CHECK-P8-NEXT: mr r3, r4
; CHECK-P8-NEXT: bl __floatdikf ; CHECK-P8-NEXT: bl __floatdikf
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: mr r3, r30 ; CHECK-P8-NEXT: mr r3, r30
Show All 26 Lines
; ;
; CHECK-P8-LABEL: udwConv2qp_testXForm: ; CHECK-P8-LABEL: udwConv2qp_testXForm:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: lis r5, 1 ; CHECK-P8-NEXT: lis r5, 1
; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: ori r5, r5, 7797 ; CHECK-P8-NEXT: ori r5, r5, 7797
; CHECK-P8-NEXT: ldx r4, r4, r5 ; CHECK-P8-NEXT: ldx r4, r4, r5
; CHECK-P8-NEXT: mr r3, r4 ; CHECK-P8-NEXT: mr r3, r4
; CHECK-P8-NEXT: bl __floatundikf ; CHECK-P8-NEXT: bl __floatundikf
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: mr r3, r30 ; CHECK-P8-NEXT: mr r3, r30
Show All 24 Lines
; ;
; CHECK-P8-LABEL: swConv2qp: ; CHECK-P8-LABEL: swConv2qp:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: mr r3, r4 ; CHECK-P8-NEXT: mr r3, r4
; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: bl __floatsikf ; CHECK-P8-NEXT: bl __floatsikf
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
Show All 16 Lines
; ;
; CHECK-P8-LABEL: swConv2qp_02: ; CHECK-P8-LABEL: swConv2qp_02:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: lwa r4, 0(r4) ; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: lwa r4, 0(r4)
; CHECK-P8-NEXT: mr r3, r4 ; CHECK-P8-NEXT: mr r3, r4
; CHECK-P8-NEXT: bl __floatsikf ; CHECK-P8-NEXT: bl __floatsikf
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
Show All 21 Lines
; ;
; CHECK-P8-LABEL: swConv2qp_03: ; CHECK-P8-LABEL: swConv2qp_03:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: addis r4, r2, .LC2@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LC2@toc@ha
; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: ld r4, .LC2@toc@l(r4) ; CHECK-P8-NEXT: ld r4, .LC2@toc@l(r4)
; CHECK-P8-NEXT: lwa r4, 12(r4) ; CHECK-P8-NEXT: lwa r4, 12(r4)
; CHECK-P8-NEXT: mr r3, r4 ; CHECK-P8-NEXT: mr r3, r4
; CHECK-P8-NEXT: bl __floatsikf ; CHECK-P8-NEXT: bl __floatsikf
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
Show All 22 Lines
; ;
; CHECK-P8-LABEL: uwConv2qp: ; CHECK-P8-LABEL: uwConv2qp:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: mr r3, r4 ; CHECK-P8-NEXT: mr r3, r4
; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: bl __floatunsikf ; CHECK-P8-NEXT: bl __floatunsikf
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
Show All 16 Lines
; ;
; CHECK-P8-LABEL: uwConv2qp_02: ; CHECK-P8-LABEL: uwConv2qp_02:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: lwz r4, 0(r4) ; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: lwz r4, 0(r4)
; CHECK-P8-NEXT: mr r3, r4 ; CHECK-P8-NEXT: mr r3, r4
; CHECK-P8-NEXT: bl __floatunsikf ; CHECK-P8-NEXT: bl __floatunsikf
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
Show All 21 Lines
; ;
; CHECK-P8-LABEL: uwConv2qp_03: ; CHECK-P8-LABEL: uwConv2qp_03:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: addis r4, r2, .LC3@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LC3@toc@ha
; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: ld r4, .LC3@toc@l(r4) ; CHECK-P8-NEXT: ld r4, .LC3@toc@l(r4)
; CHECK-P8-NEXT: lwz r4, 12(r4) ; CHECK-P8-NEXT: lwz r4, 12(r4)
; CHECK-P8-NEXT: mr r3, r4 ; CHECK-P8-NEXT: mr r3, r4
; CHECK-P8-NEXT: bl __floatunsikf ; CHECK-P8-NEXT: bl __floatunsikf
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
Show All 24 Lines
; ;
; CHECK-P8-LABEL: uwConv2qp_04: ; CHECK-P8-LABEL: uwConv2qp_04:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: lwz r3, 0(r5) ; CHECK-P8-NEXT: lwz r3, 0(r5)
; CHECK-P8-NEXT: add r3, r3, r4 ; CHECK-P8-NEXT: add r3, r3, r4
; CHECK-P8-NEXT: clrldi r3, r3, 32 ; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: bl __floatunsikf ; CHECK-P8-NEXT: bl __floatunsikf
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
Show All 23 Lines
; ;
; CHECK-P8-LABEL: uhwConv2qp: ; CHECK-P8-LABEL: uhwConv2qp:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: mr r3, r4 ; CHECK-P8-NEXT: mr r3, r4
; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: bl __floatunsikf ; CHECK-P8-NEXT: bl __floatunsikf
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
Show All 17 Lines
; ;
; CHECK-P8-LABEL: uhwConv2qp_02: ; CHECK-P8-LABEL: uhwConv2qp_02:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: lhz r4, 0(r4) ; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: lhz r4, 0(r4)
; CHECK-P8-NEXT: mr r3, r4 ; CHECK-P8-NEXT: mr r3, r4
; CHECK-P8-NEXT: bl __floatunsikf ; CHECK-P8-NEXT: bl __floatunsikf
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
Show All 21 Lines
; ;
; CHECK-P8-LABEL: uhwConv2qp_03: ; CHECK-P8-LABEL: uhwConv2qp_03:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: addis r4, r2, .LC4@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LC4@toc@ha
; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: ld r4, .LC4@toc@l(r4) ; CHECK-P8-NEXT: ld r4, .LC4@toc@l(r4)
; CHECK-P8-NEXT: lhz r4, 6(r4) ; CHECK-P8-NEXT: lhz r4, 6(r4)
; CHECK-P8-NEXT: mr r3, r4 ; CHECK-P8-NEXT: mr r3, r4
; CHECK-P8-NEXT: bl __floatunsikf ; CHECK-P8-NEXT: bl __floatunsikf
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
Show All 24 Lines
; ;
; CHECK-P8-LABEL: uhwConv2qp_04: ; CHECK-P8-LABEL: uhwConv2qp_04:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: lhz r3, 0(r5) ; CHECK-P8-NEXT: lhz r3, 0(r5)
; CHECK-P8-NEXT: add r3, r3, r4 ; CHECK-P8-NEXT: add r3, r3, r4
; CHECK-P8-NEXT: clrldi r3, r3, 32 ; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: bl __floatsikf ; CHECK-P8-NEXT: bl __floatsikf
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
Show All 25 Lines
; ;
; CHECK-P8-LABEL: ubConv2qp: ; CHECK-P8-LABEL: ubConv2qp:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: mr r3, r4 ; CHECK-P8-NEXT: mr r3, r4
; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: bl __floatunsikf ; CHECK-P8-NEXT: bl __floatunsikf
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
Show All 16 Lines
; ;
; CHECK-P8-LABEL: ubConv2qp_02: ; CHECK-P8-LABEL: ubConv2qp_02:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: lbz r4, 0(r4) ; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: lbz r4, 0(r4)
; CHECK-P8-NEXT: mr r3, r4 ; CHECK-P8-NEXT: mr r3, r4
; CHECK-P8-NEXT: bl __floatunsikf ; CHECK-P8-NEXT: bl __floatunsikf
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
Show All 21 Lines
; ;
; CHECK-P8-LABEL: ubConv2qp_03: ; CHECK-P8-LABEL: ubConv2qp_03:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: addis r4, r2, .LC5@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LC5@toc@ha
; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: ld r4, .LC5@toc@l(r4) ; CHECK-P8-NEXT: ld r4, .LC5@toc@l(r4)
; CHECK-P8-NEXT: lbz r4, 2(r4) ; CHECK-P8-NEXT: lbz r4, 2(r4)
; CHECK-P8-NEXT: mr r3, r4 ; CHECK-P8-NEXT: mr r3, r4
; CHECK-P8-NEXT: bl __floatunsikf ; CHECK-P8-NEXT: bl __floatunsikf
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
Show All 24 Lines
; ;
; CHECK-P8-LABEL: ubConv2qp_04: ; CHECK-P8-LABEL: ubConv2qp_04:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: lbz r3, 0(r5) ; CHECK-P8-NEXT: lbz r3, 0(r5)
; CHECK-P8-NEXT: add r3, r3, r4 ; CHECK-P8-NEXT: add r3, r3, r4
; CHECK-P8-NEXT: clrldi r3, r3, 32 ; CHECK-P8-NEXT: clrldi r3, r3, 32
; CHECK-P8-NEXT: bl __floatsikf ; CHECK-P8-NEXT: bl __floatsikf
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
Show All 30 Lines
; CHECK-NEXT: lxv v2, 0(r3) ; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: xscvqpdp v2, v2 ; CHECK-NEXT: xscvqpdp v2, v2
; CHECK-NEXT: xscpsgndp f1, v2, v2 ; CHECK-NEXT: xscpsgndp f1, v2, v2
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: qpConv2dp: ; CHECK-P8-LABEL: qpConv2dp:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: std r0, 48(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl __trunckfdf2 ; CHECK-P8-NEXT: bl __trunckfdf2
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addi r1, r1, 32 ; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
Show All 18 Lines
; ;
; CHECK-P8-LABEL: qpConv2dp_02: ; CHECK-P8-LABEL: qpConv2dp_02:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: addis r4, r2, .LC6@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LC6@toc@ha
; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: ld r4, .LC6@toc@l(r4) ; CHECK-P8-NEXT: ld r4, .LC6@toc@l(r4)
; CHECK-P8-NEXT: lxvd2x vs0, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl __trunckfdf2 ; CHECK-P8-NEXT: bl __trunckfdf2
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stfd f1, 0(r30) ; CHECK-P8-NEXT: stfd f1, 0(r30)
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
Show All 24 Lines
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 64 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 64
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r29, -24 ; CHECK-P8-NEXT: .cfi_offset r29, -24
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r29, -24(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r29, -24(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -64(r1) ; CHECK-P8-NEXT: stdu r1, -64(r1)
; CHECK-P8-NEXT: mr r30, r4 ; CHECK-P8-NEXT: mr r30, r4
; CHECK-P8-NEXT: addis r4, r2, .LC7@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LC7@toc@ha
; CHECK-P8-NEXT: std r0, 80(r1)
; CHECK-P8-NEXT: mr r29, r3 ; CHECK-P8-NEXT: mr r29, r3
; CHECK-P8-NEXT: ld r4, .LC7@toc@l(r4) ; CHECK-P8-NEXT: ld r4, .LC7@toc@l(r4)
; CHECK-P8-NEXT: lxvd2x vs0, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl __trunckfdf2 ; CHECK-P8-NEXT: bl __trunckfdf2
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: sldi r3, r30, 3 ; CHECK-P8-NEXT: sldi r3, r30, 3
; CHECK-P8-NEXT: stfdx f1, r29, r3 ; CHECK-P8-NEXT: stfdx f1, r29, r3
Show All 25 Lines
; ;
; CHECK-P8-LABEL: qpConv2dp_04: ; CHECK-P8-LABEL: qpConv2dp_04:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: mr r30, r5
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: lxvd2x vs1, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: mr r30, r5
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxswapd v3, vs1 ; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: bl __addkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: bl __trunckfdf2 ; CHECK-P8-NEXT: bl __trunckfdf2
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stfd f1, 0(r30) ; CHECK-P8-NEXT: stfd f1, 0(r30)
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
Show All 19 Lines
; CHECK-NEXT: lxv v2, 0(r3) ; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: xscvqpdpo v2, v2 ; CHECK-NEXT: xscvqpdpo v2, v2
; CHECK-NEXT: xsrsp f1, v2 ; CHECK-NEXT: xsrsp f1, v2
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: qpConv2sp: ; CHECK-P8-LABEL: qpConv2sp:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: std r0, 48(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl __trunckfsf2 ; CHECK-P8-NEXT: bl __trunckfsf2
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addi r1, r1, 32 ; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
Show All 19 Lines
; ;
; CHECK-P8-LABEL: qpConv2sp_02: ; CHECK-P8-LABEL: qpConv2sp_02:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: addis r4, r2, .LC6@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LC6@toc@ha
; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: ld r4, .LC6@toc@l(r4) ; CHECK-P8-NEXT: ld r4, .LC6@toc@l(r4)
; CHECK-P8-NEXT: lxvd2x vs0, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl __trunckfsf2 ; CHECK-P8-NEXT: bl __trunckfsf2
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stfs f1, 0(r30) ; CHECK-P8-NEXT: stfs f1, 0(r30)
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
Show All 25 Lines
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 64 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 64
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r29, -24 ; CHECK-P8-NEXT: .cfi_offset r29, -24
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r29, -24(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r29, -24(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -64(r1) ; CHECK-P8-NEXT: stdu r1, -64(r1)
; CHECK-P8-NEXT: mr r30, r4 ; CHECK-P8-NEXT: mr r30, r4
; CHECK-P8-NEXT: addis r4, r2, .LC7@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LC7@toc@ha
; CHECK-P8-NEXT: std r0, 80(r1)
; CHECK-P8-NEXT: mr r29, r3 ; CHECK-P8-NEXT: mr r29, r3
; CHECK-P8-NEXT: ld r4, .LC7@toc@l(r4) ; CHECK-P8-NEXT: ld r4, .LC7@toc@l(r4)
; CHECK-P8-NEXT: addi r4, r4, 48 ; CHECK-P8-NEXT: addi r4, r4, 48
; CHECK-P8-NEXT: lxvd2x vs0, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl __trunckfsf2 ; CHECK-P8-NEXT: bl __trunckfsf2
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: sldi r3, r30, 2 ; CHECK-P8-NEXT: sldi r3, r30, 2
Show All 27 Lines
; ;
; CHECK-P8-LABEL: qpConv2sp_04: ; CHECK-P8-LABEL: qpConv2sp_04:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: mr r30, r5
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: lxvd2x vs1, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: mr r30, r5
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxswapd v3, vs1 ; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: bl __addkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: bl __trunckfsf2 ; CHECK-P8-NEXT: bl __trunckfsf2
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stfs f1, 0(r30) ; CHECK-P8-NEXT: stfs f1, 0(r30)
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
Show All 18 Lines
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xscpsgndp v2, f1, f1 ; CHECK-NEXT: xscpsgndp v2, f1, f1
; CHECK-NEXT: xscvdpqp v2, v2 ; CHECK-NEXT: xscvdpqp v2, v2
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: dpConv2qp: ; CHECK-P8-LABEL: dpConv2qp:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: std r0, 48(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: bl __extenddfkf2 ; CHECK-P8-NEXT: bl __extenddfkf2
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addi r1, r1, 32 ; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
Show All 11 Lines
; CHECK-NEXT: ld r3, .LC8@toc@l(r3) ; CHECK-NEXT: ld r3, .LC8@toc@l(r3)
; CHECK-NEXT: xscvdpqp v2, v2 ; CHECK-NEXT: xscvdpqp v2, v2
; CHECK-NEXT: stxv v2, 0(r3) ; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: dpConv2qp_02: ; CHECK-P8-LABEL: dpConv2qp_02:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: std r0, 48(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: lfd f1, 0(r3) ; CHECK-P8-NEXT: lfd f1, 0(r3)
; CHECK-P8-NEXT: bl __extenddfkf2 ; CHECK-P8-NEXT: bl __extenddfkf2
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addis r3, r2, .LC8@toc@ha ; CHECK-P8-NEXT: addis r3, r2, .LC8@toc@ha
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: ld r3, .LC8@toc@l(r3) ; CHECK-P8-NEXT: ld r3, .LC8@toc@l(r3)
Show All 19 Lines
; CHECK-NEXT: ld r3, .LC8@toc@l(r3) ; CHECK-NEXT: ld r3, .LC8@toc@l(r3)
; CHECK-NEXT: xscvdpqp v2, v2 ; CHECK-NEXT: xscvdpqp v2, v2
; CHECK-NEXT: stxv v2, 0(r3) ; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: dpConv2qp_02b: ; CHECK-P8-LABEL: dpConv2qp_02b:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: std r0, 48(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: sldi r4, r4, 3 ; CHECK-P8-NEXT: sldi r4, r4, 3
; CHECK-P8-NEXT: lfdx f1, r3, r4 ; CHECK-P8-NEXT: lfdx f1, r3, r4
; CHECK-P8-NEXT: bl __extenddfkf2 ; CHECK-P8-NEXT: bl __extenddfkf2
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addis r3, r2, .LC8@toc@ha ; CHECK-P8-NEXT: addis r3, r2, .LC8@toc@ha
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
Show All 26 Lines
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 64 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 64
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r29, -24 ; CHECK-P8-NEXT: .cfi_offset r29, -24
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r29, -24(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r29, -24(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -64(r1) ; CHECK-P8-NEXT: stdu r1, -64(r1)
; CHECK-P8-NEXT: std r0, 80(r1)
; CHECK-P8-NEXT: mr r30, r4 ; CHECK-P8-NEXT: mr r30, r4
; CHECK-P8-NEXT: mr r29, r3 ; CHECK-P8-NEXT: mr r29, r3
; CHECK-P8-NEXT: bl __extenddfkf2 ; CHECK-P8-NEXT: bl __extenddfkf2
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: sldi r3, r30, 4 ; CHECK-P8-NEXT: sldi r3, r30, 4
; CHECK-P8-NEXT: stxvd2x vs0, r29, r3 ; CHECK-P8-NEXT: stxvd2x vs0, r29, r3
; CHECK-P8-NEXT: addi r1, r1, 64 ; CHECK-P8-NEXT: addi r1, r1, 64
Show All 21 Lines
; ;
; CHECK-P8-LABEL: dpConv2qp_04: ; CHECK-P8-LABEL: dpConv2qp_04:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: mr r30, r4 ; CHECK-P8-NEXT: mr r30, r4
; CHECK-P8-NEXT: bl __extenddfkf2 ; CHECK-P8-NEXT: bl __extenddfkf2
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
Show All 11 Lines
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xscpsgndp v2, f1, f1 ; CHECK-NEXT: xscpsgndp v2, f1, f1
; CHECK-NEXT: xscvdpqp v2, v2 ; CHECK-NEXT: xscvdpqp v2, v2
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: spConv2qp: ; CHECK-P8-LABEL: spConv2qp:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: std r0, 48(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: bl __extendsfkf2 ; CHECK-P8-NEXT: bl __extendsfkf2
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addi r1, r1, 32 ; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
Show All 11 Lines
; CHECK-NEXT: ld r3, .LC8@toc@l(r3) ; CHECK-NEXT: ld r3, .LC8@toc@l(r3)
; CHECK-NEXT: xscvdpqp v2, v2 ; CHECK-NEXT: xscvdpqp v2, v2
; CHECK-NEXT: stxv v2, 0(r3) ; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: spConv2qp_02: ; CHECK-P8-LABEL: spConv2qp_02:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: std r0, 48(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: lfs f1, 0(r3) ; CHECK-P8-NEXT: lfs f1, 0(r3)
; CHECK-P8-NEXT: bl __extendsfkf2 ; CHECK-P8-NEXT: bl __extendsfkf2
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addis r3, r2, .LC8@toc@ha ; CHECK-P8-NEXT: addis r3, r2, .LC8@toc@ha
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: ld r3, .LC8@toc@l(r3) ; CHECK-P8-NEXT: ld r3, .LC8@toc@l(r3)
Show All 19 Lines
; CHECK-NEXT: ld r3, .LC8@toc@l(r3) ; CHECK-NEXT: ld r3, .LC8@toc@l(r3)
; CHECK-NEXT: xscvdpqp v2, v2 ; CHECK-NEXT: xscvdpqp v2, v2
; CHECK-NEXT: stxv v2, 0(r3) ; CHECK-NEXT: stxv v2, 0(r3)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: spConv2qp_02b: ; CHECK-P8-LABEL: spConv2qp_02b:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: std r0, 48(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: sldi r4, r4, 2 ; CHECK-P8-NEXT: sldi r4, r4, 2
; CHECK-P8-NEXT: lfsx f1, r3, r4 ; CHECK-P8-NEXT: lfsx f1, r3, r4
; CHECK-P8-NEXT: bl __extendsfkf2 ; CHECK-P8-NEXT: bl __extendsfkf2
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addis r3, r2, .LC8@toc@ha ; CHECK-P8-NEXT: addis r3, r2, .LC8@toc@ha
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
Show All 26 Lines
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 64 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 64
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r29, -24 ; CHECK-P8-NEXT: .cfi_offset r29, -24
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r29, -24(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r29, -24(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -64(r1) ; CHECK-P8-NEXT: stdu r1, -64(r1)
; CHECK-P8-NEXT: std r0, 80(r1)
; CHECK-P8-NEXT: mr r30, r4 ; CHECK-P8-NEXT: mr r30, r4
; CHECK-P8-NEXT: mr r29, r3 ; CHECK-P8-NEXT: mr r29, r3
; CHECK-P8-NEXT: bl __extendsfkf2 ; CHECK-P8-NEXT: bl __extendsfkf2
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: sldi r3, r30, 4 ; CHECK-P8-NEXT: sldi r3, r30, 4
; CHECK-P8-NEXT: stxvd2x vs0, r29, r3 ; CHECK-P8-NEXT: stxvd2x vs0, r29, r3
; CHECK-P8-NEXT: addi r1, r1, 64 ; CHECK-P8-NEXT: addi r1, r1, 64
Show All 21 Lines
; ;
; CHECK-P8-LABEL: spConv2qp_04: ; CHECK-P8-LABEL: spConv2qp_04:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: mr r30, r4 ; CHECK-P8-NEXT: mr r30, r4
; CHECK-P8-NEXT: bl __extendsfkf2 ; CHECK-P8-NEXT: bl __extendsfkf2
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
Show All 18 Lines
; ;
; CHECK-P8-LABEL: cvdp2sw2qp: ; CHECK-P8-LABEL: cvdp2sw2qp:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: xscvdpsxws f0, f1 ; CHECK-P8-NEXT: xscvdpsxws f0, f1
; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: mr r30, r4 ; CHECK-P8-NEXT: mr r30, r4
; CHECK-P8-NEXT: mffprwz r3, f0 ; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: extsw r3, r3 ; CHECK-P8-NEXT: extsw r3, r3
; CHECK-P8-NEXT: bl __floatsikf ; CHECK-P8-NEXT: bl __floatsikf
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
Show All 19 Lines
; ;
; CHECK-P8-LABEL: cvdp2sdw2qp: ; CHECK-P8-LABEL: cvdp2sdw2qp:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: xscvdpsxds f0, f1 ; CHECK-P8-NEXT: xscvdpsxds f0, f1
; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: mr r30, r4 ; CHECK-P8-NEXT: mr r30, r4
; CHECK-P8-NEXT: mffprd r3, f0 ; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: bl __floatdikf ; CHECK-P8-NEXT: bl __floatdikf
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
Show All 19 Lines
; ;
; CHECK-P8-LABEL: cvsp2sw2qp: ; CHECK-P8-LABEL: cvsp2sw2qp:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: xscvdpsxws f0, f1 ; CHECK-P8-NEXT: xscvdpsxws f0, f1
; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: mr r30, r4 ; CHECK-P8-NEXT: mr r30, r4
; CHECK-P8-NEXT: mffprwz r3, f0 ; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: extsw r3, r3 ; CHECK-P8-NEXT: extsw r3, r3
; CHECK-P8-NEXT: bl __floatsikf ; CHECK-P8-NEXT: bl __floatsikf
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
Show All 19 Lines
; ;
; CHECK-P8-LABEL: cvsp2sdw2qp: ; CHECK-P8-LABEL: cvsp2sdw2qp:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: xscvdpsxds f0, f1 ; CHECK-P8-NEXT: xscvdpsxds f0, f1
; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: mr r30, r4 ; CHECK-P8-NEXT: mr r30, r4
; CHECK-P8-NEXT: mffprd r3, f0 ; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: bl __floatdikf ; CHECK-P8-NEXT: bl __floatdikf
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
Show All 19 Lines
; ;
; CHECK-P8-LABEL: cvdp2uw2qp: ; CHECK-P8-LABEL: cvdp2uw2qp:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: xscvdpuxws f0, f1 ; CHECK-P8-NEXT: xscvdpuxws f0, f1
; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: mr r30, r4 ; CHECK-P8-NEXT: mr r30, r4
; CHECK-P8-NEXT: mffprwz r3, f0 ; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: bl __floatunsikf ; CHECK-P8-NEXT: bl __floatunsikf
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
Show All 18 Lines
; ;
; CHECK-P8-LABEL: cvdp2udw2qp: ; CHECK-P8-LABEL: cvdp2udw2qp:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: xscvdpuxds f0, f1 ; CHECK-P8-NEXT: xscvdpuxds f0, f1
; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: mr r30, r4 ; CHECK-P8-NEXT: mr r30, r4
; CHECK-P8-NEXT: mffprd r3, f0 ; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: bl __floatundikf ; CHECK-P8-NEXT: bl __floatundikf
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
Show All 19 Lines
; ;
; CHECK-P8-LABEL: cvsp2uw2qp: ; CHECK-P8-LABEL: cvsp2uw2qp:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: xscvdpuxws f0, f1 ; CHECK-P8-NEXT: xscvdpuxws f0, f1
; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: mr r30, r4 ; CHECK-P8-NEXT: mr r30, r4
; CHECK-P8-NEXT: mffprwz r3, f0 ; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: bl __floatunsikf ; CHECK-P8-NEXT: bl __floatunsikf
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
Show All 18 Lines
; ;
; CHECK-P8-LABEL: cvsp2udw2qp: ; CHECK-P8-LABEL: cvsp2udw2qp:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: xscvdpuxds f0, f1 ; CHECK-P8-NEXT: xscvdpuxds f0, f1
; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: mr r30, r4 ; CHECK-P8-NEXT: mr r30, r4
; CHECK-P8-NEXT: mffprd r3, f0 ; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: bl __floatundikf ; CHECK-P8-NEXT: bl __floatundikf
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%conv = fptoui float %val to i64 %conv = fptoui float %val to i64
%conv1 = uitofp i64 %conv to fp128 %conv1 = uitofp i64 %conv to fp128
store fp128 %conv1, ptr %res, align 16 store fp128 %conv1, ptr %res, align 16
ret void ret void
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define i128 @qpConv2i128(ptr nocapture readonly %a) { define i128 @qpConv2i128(ptr nocapture readonly %a) {
; CHECK-LABEL: qpConv2i128: ; CHECK-LABEL: qpConv2i128:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr r0 ; CHECK-NEXT: mflr r0
; CHECK-NEXT: std r0, 16(r1)
; CHECK-NEXT: stdu r1, -32(r1) ; CHECK-NEXT: stdu r1, -32(r1)
; CHECK-NEXT: std r0, 48(r1)
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: lxv v2, 0(r3) ; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: bl __fixkfti ; CHECK-NEXT: bl __fixkfti
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: addi r1, r1, 32 ; CHECK-NEXT: addi r1, r1, 32
; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: ld r0, 16(r1)
; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: mtlr r0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: qpConv2i128: ; CHECK-P8-LABEL: qpConv2i128:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: std r0, 48(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl __fixkfti ; CHECK-P8-NEXT: bl __fixkfti
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addi r1, r1, 32 ; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%0 = load fp128, ptr %a, align 16 %0 = load fp128, ptr %a, align 16
%conv = fptosi fp128 %0 to i128 %conv = fptosi fp128 %0 to i128
ret i128 %conv ret i128 %conv
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define i128 @qpConv2ui128(ptr nocapture readonly %a) { define i128 @qpConv2ui128(ptr nocapture readonly %a) {
; CHECK-LABEL: qpConv2ui128: ; CHECK-LABEL: qpConv2ui128:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr r0 ; CHECK-NEXT: mflr r0
; CHECK-NEXT: std r0, 16(r1)
; CHECK-NEXT: stdu r1, -32(r1) ; CHECK-NEXT: stdu r1, -32(r1)
; CHECK-NEXT: std r0, 48(r1)
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: lxv v2, 0(r3) ; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: bl __fixunskfti ; CHECK-NEXT: bl __fixunskfti
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: addi r1, r1, 32 ; CHECK-NEXT: addi r1, r1, 32
; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: ld r0, 16(r1)
; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: mtlr r0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: qpConv2ui128: ; CHECK-P8-LABEL: qpConv2ui128:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: std r0, 48(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl __fixunskfti ; CHECK-P8-NEXT: bl __fixunskfti
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addi r1, r1, 32 ; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
Show All 12 Lines
; CHECK-NEXT: lxv v2, 0(r3) ; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: xscvqpswz v2, v2 ; CHECK-NEXT: xscvqpswz v2, v2
; CHECK-NEXT: mfvsrwz r3, v2 ; CHECK-NEXT: mfvsrwz r3, v2
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: qpConv2ui1: ; CHECK-P8-LABEL: qpConv2ui1:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: std r0, 48(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl __fixkfsi ; CHECK-P8-NEXT: bl __fixkfsi
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addi r1, r1, 32 ; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
Show All 12 Lines
; CHECK-NEXT: lxv v2, 0(r3) ; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: xscvqpswz v2, v2 ; CHECK-NEXT: xscvqpswz v2, v2
; CHECK-NEXT: mfvsrwz r3, v2 ; CHECK-NEXT: mfvsrwz r3, v2
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: qpConv2si1: ; CHECK-P8-LABEL: qpConv2si1:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: std r0, 48(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl __fixkfsi ; CHECK-P8-NEXT: bl __fixkfsi
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addi r1, r1, 32 ; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%0 = load fp128, ptr %a, align 16 %0 = load fp128, ptr %a, align 16
%conv = fptosi fp128 %0 to i1 %conv = fptosi fp128 %0 to i1
ret i1 %conv ret i1 %conv
} }

llvm/test/CodeGen/PowerPC/f128-fma.ll

Show All 12 Lines
; CHECK-NEXT: lxv v4, 0(r5) ; CHECK-NEXT: lxv v4, 0(r5)
; CHECK-NEXT: xsmaddqp v4, v2, v3 ; CHECK-NEXT: xsmaddqp v4, v2, v3
; CHECK-NEXT: stxv v4, 0(r6) ; CHECK-NEXT: stxv v4, 0(r6)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: qpFmadd: ; CHECK-P8-LABEL: qpFmadd:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -80(r1) ; CHECK-P8-NEXT: stdu r1, -80(r1)
; CHECK-P8-NEXT: std r0, 96(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 80 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 80
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: .cfi_offset v31, -32 ; CHECK-P8-NEXT: .cfi_offset v31, -32
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: lxvd2x vs1, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: li r7, 48 ; CHECK-P8-NEXT: li r7, 48
; CHECK-P8-NEXT: std r30, 64(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, 64(r1) # 8-byte Folded Spill
Show All 37 Lines
; CHECK-NEXT: lxv v4, 0(r5) ; CHECK-NEXT: lxv v4, 0(r5)
; CHECK-NEXT: xsmaddqp v2, v3, v4 ; CHECK-NEXT: xsmaddqp v2, v3, v4
; CHECK-NEXT: stxv v2, 0(r6) ; CHECK-NEXT: stxv v2, 0(r6)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: qpFmadd_02: ; CHECK-P8-LABEL: qpFmadd_02:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -80(r1) ; CHECK-P8-NEXT: stdu r1, -80(r1)
; CHECK-P8-NEXT: std r0, 96(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 80 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 80
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: .cfi_offset v31, -32 ; CHECK-P8-NEXT: .cfi_offset v31, -32
; CHECK-P8-NEXT: lxvd2x vs1, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: lxvd2x vs2, 0, r5 ; CHECK-P8-NEXT: lxvd2x vs2, 0, r5
; CHECK-P8-NEXT: li r7, 48 ; CHECK-P8-NEXT: li r7, 48
; CHECK-P8-NEXT: std r30, 64(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, 64(r1) # 8-byte Folded Spill
▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Lines
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 64 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 64
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r29, -24 ; CHECK-P8-NEXT: .cfi_offset r29, -24
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r29, -24(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r29, -24(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -64(r1) ; CHECK-P8-NEXT: stdu r1, -64(r1)
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: std r0, 80(r1)
; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: mr r30, r6 ; CHECK-P8-NEXT: mr r30, r6
; CHECK-P8-NEXT: mr r29, r5 ; CHECK-P8-NEXT: mr r29, r5
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxswapd v3, vs1 ; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: bl __mulkf3 ; CHECK-P8-NEXT: bl __mulkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: lxvd2x vs0, 0, r29 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r29
; CHECK-P8-NEXT: xxswapd v3, vs0 ; CHECK-P8-NEXT: xxswapd v3, vs0
; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: bl __addkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
Show All 26 Lines
; CHECK-NEXT: lxv v4, 0(r5) ; CHECK-NEXT: lxv v4, 0(r5)
; CHECK-NEXT: xsnmaddqp v2, v3, v4 ; CHECK-NEXT: xsnmaddqp v2, v3, v4
; CHECK-NEXT: stxv v2, 0(r6) ; CHECK-NEXT: stxv v2, 0(r6)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: qpFnmadd: ; CHECK-P8-LABEL: qpFnmadd:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -96(r1) ; CHECK-P8-NEXT: stdu r1, -96(r1)
; CHECK-P8-NEXT: std r0, 112(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 96 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 96
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: .cfi_offset v31, -32 ; CHECK-P8-NEXT: .cfi_offset v31, -32
; CHECK-P8-NEXT: lxvd2x vs1, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: lxvd2x vs2, 0, r5 ; CHECK-P8-NEXT: lxvd2x vs2, 0, r5
; CHECK-P8-NEXT: li r7, 64 ; CHECK-P8-NEXT: li r7, 64
; CHECK-P8-NEXT: std r30, 80(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, 80(r1) # 8-byte Folded Spill
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Lines
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 80 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 80
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r29, -24 ; CHECK-P8-NEXT: .cfi_offset r29, -24
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r29, -24(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r29, -24(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -80(r1) ; CHECK-P8-NEXT: stdu r1, -80(r1)
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: std r0, 96(r1)
; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: mr r30, r6 ; CHECK-P8-NEXT: mr r30, r6
; CHECK-P8-NEXT: mr r29, r5 ; CHECK-P8-NEXT: mr r29, r5
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxswapd v3, vs1 ; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: bl __mulkf3 ; CHECK-P8-NEXT: bl __mulkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: lxvd2x vs0, 0, r29 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r29
; CHECK-P8-NEXT: xxswapd v3, vs0 ; CHECK-P8-NEXT: xxswapd v3, vs0
; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: bl __addkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
Show All 33 Lines
; CHECK-NEXT: lxv v4, 0(r5) ; CHECK-NEXT: lxv v4, 0(r5)
; CHECK-NEXT: xsnmsubqp v2, v3, v4 ; CHECK-NEXT: xsnmsubqp v2, v3, v4
; CHECK-NEXT: stxv v2, 0(r6) ; CHECK-NEXT: stxv v2, 0(r6)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: qpFmsub: ; CHECK-P8-LABEL: qpFmsub:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -80(r1) ; CHECK-P8-NEXT: stdu r1, -80(r1)
; CHECK-P8-NEXT: std r0, 96(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 80 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 80
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: .cfi_offset v31, -32 ; CHECK-P8-NEXT: .cfi_offset v31, -32
; CHECK-P8-NEXT: lxvd2x vs1, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: lxvd2x vs2, 0, r5 ; CHECK-P8-NEXT: lxvd2x vs2, 0, r5
; CHECK-P8-NEXT: li r7, 48 ; CHECK-P8-NEXT: li r7, 48
; CHECK-P8-NEXT: std r30, 64(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, 64(r1) # 8-byte Folded Spill
▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Lines
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 64 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 64
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r29, -24 ; CHECK-P8-NEXT: .cfi_offset r29, -24
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r29, -24(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r29, -24(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -64(r1) ; CHECK-P8-NEXT: stdu r1, -64(r1)
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: std r0, 80(r1)
; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: mr r30, r6 ; CHECK-P8-NEXT: mr r30, r6
; CHECK-P8-NEXT: mr r29, r5 ; CHECK-P8-NEXT: mr r29, r5
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxswapd v3, vs1 ; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: bl __mulkf3 ; CHECK-P8-NEXT: bl __mulkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: lxvd2x vs0, 0, r29 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r29
; CHECK-P8-NEXT: xxswapd v3, vs0 ; CHECK-P8-NEXT: xxswapd v3, vs0
; CHECK-P8-NEXT: bl __subkf3 ; CHECK-P8-NEXT: bl __subkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
Show All 27 Lines
; CHECK-NEXT: xsnegqp v3, v3 ; CHECK-NEXT: xsnegqp v3, v3
; CHECK-NEXT: xsnmaddqp v2, v3, v4 ; CHECK-NEXT: xsnmaddqp v2, v3, v4
; CHECK-NEXT: stxv v2, 0(r6) ; CHECK-NEXT: stxv v2, 0(r6)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: qpFnmsub: ; CHECK-P8-LABEL: qpFnmsub:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -96(r1) ; CHECK-P8-NEXT: stdu r1, -96(r1)
; CHECK-P8-NEXT: std r0, 112(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 96 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 96
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: .cfi_offset v31, -32 ; CHECK-P8-NEXT: .cfi_offset v31, -32
; CHECK-P8-NEXT: lxvd2x vs1, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: lxvd2x vs2, 0, r5 ; CHECK-P8-NEXT: lxvd2x vs2, 0, r5
; CHECK-P8-NEXT: li r7, 64 ; CHECK-P8-NEXT: li r7, 64
; CHECK-P8-NEXT: std r30, 80(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, 80(r1) # 8-byte Folded Spill
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Lines
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 80 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 80
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r29, -24 ; CHECK-P8-NEXT: .cfi_offset r29, -24
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r29, -24(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r29, -24(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -80(r1) ; CHECK-P8-NEXT: stdu r1, -80(r1)
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: std r0, 96(r1)
; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: mr r30, r6 ; CHECK-P8-NEXT: mr r30, r6
; CHECK-P8-NEXT: mr r29, r5 ; CHECK-P8-NEXT: mr r29, r5
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxswapd v3, vs1 ; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: bl __mulkf3 ; CHECK-P8-NEXT: bl __mulkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: lxvd2x vs0, 0, r29 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r29
; CHECK-P8-NEXT: xxswapd v3, vs0 ; CHECK-P8-NEXT: xxswapd v3, vs0
; CHECK-P8-NEXT: bl __subkf3 ; CHECK-P8-NEXT: bl __subkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
Show All 26 Lines

llvm/test/CodeGen/PowerPC/f128-passByValue.ll

Show All 33 Lines
; CHECK-NEXT: addi r3, r3, .LCPI1_0@toc@l ; CHECK-NEXT: addi r3, r3, .LCPI1_0@toc@l
; CHECK-NEXT: lxv v3, 0(r3) ; CHECK-NEXT: lxv v3, 0(r3)
; CHECK-NEXT: xsaddqp v2, v2, v3 ; CHECK-NEXT: xsaddqp v2, v2, v3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: loadConstant2: ; CHECK-P8-LABEL: loadConstant2:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: std r0, 48(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: bl __addkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addis r3, r2, .LCPI1_0@toc@ha ; CHECK-P8-NEXT: addis r3, r2, .LCPI1_0@toc@ha
; CHECK-P8-NEXT: addi r3, r3, .LCPI1_0@toc@l ; CHECK-P8-NEXT: addi r3, r3, .LCPI1_0@toc@l
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v3, vs0 ; CHECK-P8-NEXT: xxswapd v3, vs0
Show All 17 Lines
; CHECK-NEXT: xscvqpswz v2, v2 ; CHECK-NEXT: xscvqpswz v2, v2
; CHECK-NEXT: mfvsrwz r3, v2 ; CHECK-NEXT: mfvsrwz r3, v2
; CHECK-NEXT: extsw r3, r3 ; CHECK-NEXT: extsw r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: fp128Param: ; CHECK-P8-LABEL: fp128Param:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: std r0, 48(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: bl __fixkfsi ; CHECK-P8-NEXT: bl __fixkfsi
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: extsw r3, r3 ; CHECK-P8-NEXT: extsw r3, r3
; CHECK-P8-NEXT: addi r1, r1, 32 ; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
Show All 9 Lines
; CHECK-LABEL: fp128Return: ; CHECK-LABEL: fp128Return:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xsaddqp v2, v2, v3 ; CHECK-NEXT: xsaddqp v2, v2, v3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: fp128Return: ; CHECK-P8-LABEL: fp128Return:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: std r0, 48(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: bl __addkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addi r1, r1, 32 ; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
Show All 12 Lines
; CHECK-NEXT: add r3, r3, r4 ; CHECK-NEXT: add r3, r3, r4
; CHECK-NEXT: lxv v3, -16(r3) ; CHECK-NEXT: lxv v3, -16(r3)
; CHECK-NEXT: xsaddqp v2, v2, v3 ; CHECK-NEXT: xsaddqp v2, v2, v3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: fp128Array: ; CHECK-P8-LABEL: fp128Array:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: std r0, 48(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: sldi r4, r4, 4 ; CHECK-P8-NEXT: sldi r4, r4, 4
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: add r4, r3, r4 ; CHECK-P8-NEXT: add r4, r3, r4
; CHECK-P8-NEXT: addi r4, r4, -16 ; CHECK-P8-NEXT: addi r4, r4, -16
; CHECK-P8-NEXT: lxvd2x vs1, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
Show All 34 Lines
; CHECK-NEXT: xsaddqp v2, v2, v12 ; CHECK-NEXT: xsaddqp v2, v2, v12
; CHECK-NEXT: xsaddqp v2, v2, v13 ; CHECK-NEXT: xsaddqp v2, v2, v13
; CHECK-NEXT: xssubqp v2, v2, v0 ; CHECK-NEXT: xssubqp v2, v2, v0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: maxVecParam: ; CHECK-P8-LABEL: maxVecParam:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -224(r1) ; CHECK-P8-NEXT: stdu r1, -224(r1)
; CHECK-P8-NEXT: std r0, 240(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 224 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 224
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset v21, -176 ; CHECK-P8-NEXT: .cfi_offset v21, -176
; CHECK-P8-NEXT: .cfi_offset v22, -160 ; CHECK-P8-NEXT: .cfi_offset v22, -160
; CHECK-P8-NEXT: .cfi_offset v23, -144 ; CHECK-P8-NEXT: .cfi_offset v23, -144
; CHECK-P8-NEXT: .cfi_offset v24, -128 ; CHECK-P8-NEXT: .cfi_offset v24, -128
; CHECK-P8-NEXT: .cfi_offset v25, -112 ; CHECK-P8-NEXT: .cfi_offset v25, -112
; CHECK-P8-NEXT: .cfi_offset v26, -96 ; CHECK-P8-NEXT: .cfi_offset v26, -96
▲ Show 20 Lines • Show All 125 Lines • ▼ Show 20 Lines
; CHECK-NEXT: mtvsrwa v3, r5 ; CHECK-NEXT: mtvsrwa v3, r5
; CHECK-NEXT: xscvsdqp v3, v3 ; CHECK-NEXT: xscvsdqp v3, v3
; CHECK-NEXT: xsaddqp v2, v2, v3 ; CHECK-NEXT: xsaddqp v2, v2, v3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: mixParam_01: ; CHECK-P8-LABEL: mixParam_01:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -80(r1) ; CHECK-P8-NEXT: stdu r1, -80(r1)
; CHECK-P8-NEXT: std r0, 96(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 80 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 80
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: .cfi_offset v31, -32 ; CHECK-P8-NEXT: .cfi_offset v31, -32
; CHECK-P8-NEXT: li r3, 48 ; CHECK-P8-NEXT: li r3, 48
; CHECK-P8-NEXT: std r30, 64(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, 64(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: mr r30, r5 ; CHECK-P8-NEXT: mr r30, r5
; CHECK-P8-NEXT: stvx v31, r1, r3 # 16-byte Folded Spill ; CHECK-P8-NEXT: stvx v31, r1, r3 # 16-byte Folded Spill
Show All 28 Lines
; CHECK-NEXT: mtvsrwa v3, r3 ; CHECK-NEXT: mtvsrwa v3, r3
; CHECK-NEXT: xscvsdqp v3, v3 ; CHECK-NEXT: xscvsdqp v3, v3
; CHECK-NEXT: xsaddqp v2, v2, v3 ; CHECK-NEXT: xsaddqp v2, v2, v3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: mixParam_01f: ; CHECK-P8-LABEL: mixParam_01f:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -80(r1) ; CHECK-P8-NEXT: stdu r1, -80(r1)
; CHECK-P8-NEXT: std r0, 96(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 80 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 80
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: .cfi_offset v31, -32 ; CHECK-P8-NEXT: .cfi_offset v31, -32
; CHECK-P8-NEXT: li r4, 48 ; CHECK-P8-NEXT: li r4, 48
; CHECK-P8-NEXT: std r30, 64(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, 64(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: stvx v31, r1, r4 # 16-byte Folded Spill ; CHECK-P8-NEXT: stvx v31, r1, r4 # 16-byte Folded Spill
Show All 36 Lines
; CHECK-NEXT: lxv v4, 0(r8) ; CHECK-NEXT: lxv v4, 0(r8)
; CHECK-NEXT: xsaddqp v2, v4, v2 ; CHECK-NEXT: xsaddqp v2, v4, v2
; CHECK-NEXT: xsaddqp v2, v2, v3 ; CHECK-NEXT: xsaddqp v2, v2, v3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: mixParam_02: ; CHECK-P8-LABEL: mixParam_02:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -80(r1) ; CHECK-P8-NEXT: stdu r1, -80(r1)
; CHECK-P8-NEXT: std r0, 96(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 80 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 80
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset f31, -8 ; CHECK-P8-NEXT: .cfi_offset f31, -8
; CHECK-P8-NEXT: .cfi_offset v31, -32 ; CHECK-P8-NEXT: .cfi_offset v31, -32
; CHECK-P8-NEXT: li r3, 48 ; CHECK-P8-NEXT: li r3, 48
; CHECK-P8-NEXT: add r4, r7, r9 ; CHECK-P8-NEXT: add r4, r7, r9
; CHECK-P8-NEXT: vmr v3, v2 ; CHECK-P8-NEXT: vmr v3, v2
; CHECK-P8-NEXT: stfd f31, 72(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: stfd f31, 72(r1) # 8-byte Folded Spill
▲ Show 20 Lines • Show All 55 Lines • ▼ Show 20 Lines
; CHECK-NEXT: lxv v4, 0(r5) ; CHECK-NEXT: lxv v4, 0(r5)
; CHECK-NEXT: xsaddqp v2, v4, v2 ; CHECK-NEXT: xsaddqp v2, v4, v2
; CHECK-NEXT: xsaddqp v2, v2, v3 ; CHECK-NEXT: xsaddqp v2, v2, v3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: mixParam_02f: ; CHECK-P8-LABEL: mixParam_02f:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -80(r1) ; CHECK-P8-NEXT: stdu r1, -80(r1)
; CHECK-P8-NEXT: std r0, 96(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 80 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 80
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset f31, -8 ; CHECK-P8-NEXT: .cfi_offset f31, -8
; CHECK-P8-NEXT: .cfi_offset v31, -32 ; CHECK-P8-NEXT: .cfi_offset v31, -32
; CHECK-P8-NEXT: add r4, r4, r6 ; CHECK-P8-NEXT: add r4, r4, r6
; CHECK-P8-NEXT: vmr v3, v2 ; CHECK-P8-NEXT: vmr v3, v2
; CHECK-P8-NEXT: li r9, 48 ; CHECK-P8-NEXT: li r9, 48
; CHECK-P8-NEXT: stfd f31, 72(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: stfd f31, 72(r1) # 8-byte Folded Spill
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
; CHECK-NEXT: xsaddqp v2, v2, v3 ; CHECK-NEXT: xsaddqp v2, v2, v3
; CHECK-NEXT: xscvqpdp v2, v2 ; CHECK-NEXT: xscvqpdp v2, v2
; CHECK-NEXT: stxsd v2, 0(r5) ; CHECK-NEXT: stxsd v2, 0(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: mixParam_03: ; CHECK-P8-LABEL: mixParam_03:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -80(r1) ; CHECK-P8-NEXT: stdu r1, -80(r1)
; CHECK-P8-NEXT: std r0, 96(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 80 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 80
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: .cfi_offset v31, -32 ; CHECK-P8-NEXT: .cfi_offset v31, -32
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: xxswapd vs1, v3 ; CHECK-P8-NEXT: xxswapd vs1, v3
; CHECK-P8-NEXT: ld r4, 184(r1) ; CHECK-P8-NEXT: ld r4, 184(r1)
; CHECK-P8-NEXT: li r3, 48 ; CHECK-P8-NEXT: li r3, 48
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
; CHECK-NEXT: xsaddqp v2, v2, v3 ; CHECK-NEXT: xsaddqp v2, v2, v3
; CHECK-NEXT: xscvqpdp v2, v2 ; CHECK-NEXT: xscvqpdp v2, v2
; CHECK-NEXT: stxsd v2, 0(r3) ; CHECK-NEXT: stxsd v2, 0(r3)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: mixParam_03f: ; CHECK-P8-LABEL: mixParam_03f:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -80(r1) ; CHECK-P8-NEXT: stdu r1, -80(r1)
; CHECK-P8-NEXT: std r0, 96(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 80 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 80
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: .cfi_offset v31, -32 ; CHECK-P8-NEXT: .cfi_offset v31, -32
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: xxswapd vs1, v3 ; CHECK-P8-NEXT: xxswapd vs1, v3
; CHECK-P8-NEXT: li r6, 48 ; CHECK-P8-NEXT: li r6, 48
; CHECK-P8-NEXT: std r30, 64(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, 64(r1) # 8-byte Folded Spill
Show All 33 Linesentry:
ret void ret void
} }
; Function Attrs: noinline optnone ; Function Attrs: noinline optnone
define signext i32 @noopt_call_crash() #0 { define signext i32 @noopt_call_crash() #0 {
; CHECK-LABEL: noopt_call_crash: ; CHECK-LABEL: noopt_call_crash:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr r0 ; CHECK-NEXT: mflr r0
; CHECK-NEXT: std r0, 16(r1)
; CHECK-NEXT: stdu r1, -96(r1) ; CHECK-NEXT: stdu r1, -96(r1)
; CHECK-NEXT: std r0, 112(r1)
; CHECK-NEXT: .cfi_def_cfa_offset 96 ; CHECK-NEXT: .cfi_def_cfa_offset 96
; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: bl in ; CHECK-NEXT: bl in
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: bl out ; CHECK-NEXT: bl out
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: li r3, 0 ; CHECK-NEXT: li r3, 0
; CHECK-NEXT: addi r1, r1, 96 ; CHECK-NEXT: addi r1, r1, 96
; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: ld r0, 16(r1)
; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: mtlr r0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: noopt_call_crash: ; CHECK-P8-LABEL: noopt_call_crash:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -96(r1) ; CHECK-P8-NEXT: stdu r1, -96(r1)
; CHECK-P8-NEXT: std r0, 112(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 96 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 96
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: bl in ; CHECK-P8-NEXT: bl in
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: bl out ; CHECK-P8-NEXT: bl out
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: li r3, 0 ; CHECK-P8-NEXT: li r3, 0
; CHECK-P8-NEXT: addi r1, r1, 96 ; CHECK-P8-NEXT: addi r1, r1, 96
Show All 13 Lines

llvm/test/CodeGen/PowerPC/f128-rounding.ll

Show All 14 Lines
; ;
; CHECK-P8-LABEL: qp_trunc: ; CHECK-P8-LABEL: qp_trunc:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: mr r30, r4 ; CHECK-P8-NEXT: mr r30, r4
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl truncf128 ; CHECK-P8-NEXT: bl truncf128
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
Show All 17 Lines
; ;
; CHECK-P8-LABEL: qp_rint: ; CHECK-P8-LABEL: qp_rint:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: mr r30, r4 ; CHECK-P8-NEXT: mr r30, r4
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl rintf128 ; CHECK-P8-NEXT: bl rintf128
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
Show All 17 Lines
; ;
; CHECK-P8-LABEL: qp_nearbyint: ; CHECK-P8-LABEL: qp_nearbyint:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: mr r30, r4 ; CHECK-P8-NEXT: mr r30, r4
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl nearbyintf128 ; CHECK-P8-NEXT: bl nearbyintf128
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
Show All 17 Lines
; ;
; CHECK-P8-LABEL: qp_round: ; CHECK-P8-LABEL: qp_round:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: mr r30, r4 ; CHECK-P8-NEXT: mr r30, r4
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl roundf128 ; CHECK-P8-NEXT: bl roundf128
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
Show All 17 Lines
; ;
; CHECK-P8-LABEL: qp_floor: ; CHECK-P8-LABEL: qp_floor:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: mr r30, r4 ; CHECK-P8-NEXT: mr r30, r4
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl floorf128 ; CHECK-P8-NEXT: bl floorf128
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
Show All 17 Lines
; ;
; CHECK-P8-LABEL: qp_ceil: ; CHECK-P8-LABEL: qp_ceil:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: mr r30, r4 ; CHECK-P8-NEXT: mr r30, r4
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl ceilf128 ; CHECK-P8-NEXT: bl ceilf128
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
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llvm/test/CodeGen/PowerPC/f128-truncateNconv.ll

Show All 18 Lines
; CHECK-NEXT: lxv v2, 0(r3) ; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: xscvqpsdz v2, v2 ; CHECK-NEXT: xscvqpsdz v2, v2
; CHECK-NEXT: mfvsrd r3, v2 ; CHECK-NEXT: mfvsrd r3, v2
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: qpConv2sdw: ; CHECK-P8-LABEL: qpConv2sdw:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: std r0, 48(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl __fixkfdi ; CHECK-P8-NEXT: bl __fixkfdi
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addi r1, r1, 32 ; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
Show All 19 Lines
; ;
; CHECK-P8-LABEL: qpConv2sdw_02: ; CHECK-P8-LABEL: qpConv2sdw_02:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-P8-NEXT: addi r4, r4, 32 ; CHECK-P8-NEXT: addi r4, r4, 32
; CHECK-P8-NEXT: lxvd2x vs0, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl __fixkfdi ; CHECK-P8-NEXT: bl __fixkfdi
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: std r3, 0(r30) ; CHECK-P8-NEXT: std r3, 0(r30)
Show All 23 Lines
; CHECK-NEXT: xsaddqp v2, v2, v3 ; CHECK-NEXT: xsaddqp v2, v2, v3
; CHECK-NEXT: xscvqpsdz v2, v2 ; CHECK-NEXT: xscvqpsdz v2, v2
; CHECK-NEXT: mfvsrd r3, v2 ; CHECK-NEXT: mfvsrd r3, v2
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: qpConv2sdw_03: ; CHECK-P8-LABEL: qpConv2sdw_03:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: std r0, 48(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: addi r4, r4, 16 ; CHECK-P8-NEXT: addi r4, r4, 16
; CHECK-P8-NEXT: lxvd2x vs1, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
Show All 30 Lines
; ;
; CHECK-P8-LABEL: qpConv2sdw_04: ; CHECK-P8-LABEL: qpConv2sdw_04:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: mr r30, r5
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: lxvd2x vs1, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: mr r30, r5
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxswapd v3, vs1 ; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: bl __addkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: bl __fixkfdi ; CHECK-P8-NEXT: bl __fixkfdi
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: std r3, 0(r30) ; CHECK-P8-NEXT: std r3, 0(r30)
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
Show All 28 Lines
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 64 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 64
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r29, -24 ; CHECK-P8-NEXT: .cfi_offset r29, -24
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r29, -24(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r29, -24(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -64(r1) ; CHECK-P8-NEXT: stdu r1, -64(r1)
; CHECK-P8-NEXT: mr r30, r4 ; CHECK-P8-NEXT: mr r30, r4
; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-P8-NEXT: std r0, 80(r1)
; CHECK-P8-NEXT: mr r29, r3 ; CHECK-P8-NEXT: mr r29, r3
; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-P8-NEXT: addi r4, r4, 32 ; CHECK-P8-NEXT: addi r4, r4, 32
; CHECK-P8-NEXT: lxvd2x vs0, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl __fixkfdi ; CHECK-P8-NEXT: bl __fixkfdi
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: sldi r4, r30, 3 ; CHECK-P8-NEXT: sldi r4, r30, 3
Show All 23 Lines
; CHECK-NEXT: lxv v2, 0(r3) ; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: xscvqpudz v2, v2 ; CHECK-NEXT: xscvqpudz v2, v2
; CHECK-NEXT: mfvsrd r3, v2 ; CHECK-NEXT: mfvsrd r3, v2
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: qpConv2udw: ; CHECK-P8-LABEL: qpConv2udw:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: std r0, 48(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl __fixunskfdi ; CHECK-P8-NEXT: bl __fixunskfdi
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addi r1, r1, 32 ; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
Show All 19 Lines
; ;
; CHECK-P8-LABEL: qpConv2udw_02: ; CHECK-P8-LABEL: qpConv2udw_02:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-P8-NEXT: addi r4, r4, 32 ; CHECK-P8-NEXT: addi r4, r4, 32
; CHECK-P8-NEXT: lxvd2x vs0, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl __fixunskfdi ; CHECK-P8-NEXT: bl __fixunskfdi
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: std r3, 0(r30) ; CHECK-P8-NEXT: std r3, 0(r30)
Show All 23 Lines
; CHECK-NEXT: xsaddqp v2, v2, v3 ; CHECK-NEXT: xsaddqp v2, v2, v3
; CHECK-NEXT: xscvqpudz v2, v2 ; CHECK-NEXT: xscvqpudz v2, v2
; CHECK-NEXT: mfvsrd r3, v2 ; CHECK-NEXT: mfvsrd r3, v2
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: qpConv2udw_03: ; CHECK-P8-LABEL: qpConv2udw_03:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: std r0, 48(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: addi r4, r4, 16 ; CHECK-P8-NEXT: addi r4, r4, 16
; CHECK-P8-NEXT: lxvd2x vs1, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
Show All 30 Lines
; ;
; CHECK-P8-LABEL: qpConv2udw_04: ; CHECK-P8-LABEL: qpConv2udw_04:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: mr r30, r5
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: lxvd2x vs1, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: mr r30, r5
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxswapd v3, vs1 ; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: bl __addkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: bl __fixunskfdi ; CHECK-P8-NEXT: bl __fixunskfdi
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: std r3, 0(r30) ; CHECK-P8-NEXT: std r3, 0(r30)
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
Show All 28 Lines
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 64 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 64
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r29, -24 ; CHECK-P8-NEXT: .cfi_offset r29, -24
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r29, -24(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r29, -24(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -64(r1) ; CHECK-P8-NEXT: stdu r1, -64(r1)
; CHECK-P8-NEXT: mr r30, r4 ; CHECK-P8-NEXT: mr r30, r4
; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-P8-NEXT: std r0, 80(r1)
; CHECK-P8-NEXT: mr r29, r3 ; CHECK-P8-NEXT: mr r29, r3
; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-P8-NEXT: lxvd2x vs0, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl __fixunskfdi ; CHECK-P8-NEXT: bl __fixunskfdi
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: sldi r4, r30, 3 ; CHECK-P8-NEXT: sldi r4, r30, 3
; CHECK-P8-NEXT: stdx r3, r29, r4 ; CHECK-P8-NEXT: stdx r3, r29, r4
Show All 21 Lines
; CHECK-NEXT: xscvqpswz v2, v2 ; CHECK-NEXT: xscvqpswz v2, v2
; CHECK-NEXT: mfvsrwz r3, v2 ; CHECK-NEXT: mfvsrwz r3, v2
; CHECK-NEXT: extsw r3, r3 ; CHECK-NEXT: extsw r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: qpConv2sw: ; CHECK-P8-LABEL: qpConv2sw:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: std r0, 48(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl __fixkfsi ; CHECK-P8-NEXT: bl __fixkfsi
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: extsw r3, r3 ; CHECK-P8-NEXT: extsw r3, r3
; CHECK-P8-NEXT: addi r1, r1, 32 ; CHECK-P8-NEXT: addi r1, r1, 32
Show All 20 Lines
; ;
; CHECK-P8-LABEL: qpConv2sw_02: ; CHECK-P8-LABEL: qpConv2sw_02:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-P8-NEXT: addi r4, r4, 32 ; CHECK-P8-NEXT: addi r4, r4, 32
; CHECK-P8-NEXT: lxvd2x vs0, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl __fixkfsi ; CHECK-P8-NEXT: bl __fixkfsi
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stw r3, 0(r30) ; CHECK-P8-NEXT: stw r3, 0(r30)
Show All 24 Lines
; CHECK-NEXT: xscvqpswz v2, v2 ; CHECK-NEXT: xscvqpswz v2, v2
; CHECK-NEXT: mfvsrwz r3, v2 ; CHECK-NEXT: mfvsrwz r3, v2
; CHECK-NEXT: extsw r3, r3 ; CHECK-NEXT: extsw r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: qpConv2sw_03: ; CHECK-P8-LABEL: qpConv2sw_03:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: std r0, 48(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: addi r4, r4, 16 ; CHECK-P8-NEXT: addi r4, r4, 16
; CHECK-P8-NEXT: lxvd2x vs1, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
Show All 31 Lines
; ;
; CHECK-P8-LABEL: qpConv2sw_04: ; CHECK-P8-LABEL: qpConv2sw_04:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: mr r30, r5
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: lxvd2x vs1, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: mr r30, r5
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxswapd v3, vs1 ; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: bl __addkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: bl __fixkfsi ; CHECK-P8-NEXT: bl __fixkfsi
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stw r3, 0(r30) ; CHECK-P8-NEXT: stw r3, 0(r30)
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
Show All 19 Lines
; CHECK-NEXT: lxv v2, 0(r3) ; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: xscvqpuwz v2, v2 ; CHECK-NEXT: xscvqpuwz v2, v2
; CHECK-NEXT: mfvsrwz r3, v2 ; CHECK-NEXT: mfvsrwz r3, v2
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: qpConv2uw: ; CHECK-P8-LABEL: qpConv2uw:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: std r0, 48(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl __fixunskfsi ; CHECK-P8-NEXT: bl __fixunskfsi
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addi r1, r1, 32 ; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
Show All 19 Lines
; ;
; CHECK-P8-LABEL: qpConv2uw_02: ; CHECK-P8-LABEL: qpConv2uw_02:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-P8-NEXT: addi r4, r4, 32 ; CHECK-P8-NEXT: addi r4, r4, 32
; CHECK-P8-NEXT: lxvd2x vs0, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl __fixunskfsi ; CHECK-P8-NEXT: bl __fixunskfsi
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stw r3, 0(r30) ; CHECK-P8-NEXT: stw r3, 0(r30)
Show All 23 Lines
; CHECK-NEXT: xsaddqp v2, v2, v3 ; CHECK-NEXT: xsaddqp v2, v2, v3
; CHECK-NEXT: xscvqpuwz v2, v2 ; CHECK-NEXT: xscvqpuwz v2, v2
; CHECK-NEXT: mfvsrwz r3, v2 ; CHECK-NEXT: mfvsrwz r3, v2
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: qpConv2uw_03: ; CHECK-P8-LABEL: qpConv2uw_03:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: std r0, 48(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: addi r4, r4, 16 ; CHECK-P8-NEXT: addi r4, r4, 16
; CHECK-P8-NEXT: lxvd2x vs1, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
Show All 30 Lines
; ;
; CHECK-P8-LABEL: qpConv2uw_04: ; CHECK-P8-LABEL: qpConv2uw_04:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: mr r30, r5
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: lxvd2x vs1, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: mr r30, r5
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxswapd v3, vs1 ; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: bl __addkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: bl __fixunskfsi ; CHECK-P8-NEXT: bl __fixunskfsi
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stw r3, 0(r30) ; CHECK-P8-NEXT: stw r3, 0(r30)
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
Show All 21 Lines
; CHECK-NEXT: xscvqpswz v2, v2 ; CHECK-NEXT: xscvqpswz v2, v2
; CHECK-NEXT: mfvsrwz r3, v2 ; CHECK-NEXT: mfvsrwz r3, v2
; CHECK-NEXT: extsw r3, r3 ; CHECK-NEXT: extsw r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: qpConv2shw: ; CHECK-P8-LABEL: qpConv2shw:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: std r0, 48(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl __fixkfsi ; CHECK-P8-NEXT: bl __fixkfsi
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: extsw r3, r3 ; CHECK-P8-NEXT: extsw r3, r3
; CHECK-P8-NEXT: addi r1, r1, 32 ; CHECK-P8-NEXT: addi r1, r1, 32
Show All 19 Lines
; ;
; CHECK-P8-LABEL: qpConv2shw_02: ; CHECK-P8-LABEL: qpConv2shw_02:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-P8-NEXT: addi r4, r4, 32 ; CHECK-P8-NEXT: addi r4, r4, 32
; CHECK-P8-NEXT: lxvd2x vs0, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl __fixkfsi ; CHECK-P8-NEXT: bl __fixkfsi
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: sth r3, 0(r30) ; CHECK-P8-NEXT: sth r3, 0(r30)
Show All 23 Lines
; CHECK-NEXT: xscvqpswz v2, v2 ; CHECK-NEXT: xscvqpswz v2, v2
; CHECK-NEXT: mfvsrwz r3, v2 ; CHECK-NEXT: mfvsrwz r3, v2
; CHECK-NEXT: extsw r3, r3 ; CHECK-NEXT: extsw r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: qpConv2shw_03: ; CHECK-P8-LABEL: qpConv2shw_03:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: std r0, 48(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: addi r4, r4, 16 ; CHECK-P8-NEXT: addi r4, r4, 16
; CHECK-P8-NEXT: lxvd2x vs1, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
Show All 30 Lines
; ;
; CHECK-P8-LABEL: qpConv2shw_04: ; CHECK-P8-LABEL: qpConv2shw_04:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: mr r30, r5
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: lxvd2x vs1, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: mr r30, r5
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxswapd v3, vs1 ; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: bl __addkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: bl __fixkfsi ; CHECK-P8-NEXT: bl __fixkfsi
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: sth r3, 0(r30) ; CHECK-P8-NEXT: sth r3, 0(r30)
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
Show All 18 Lines
; CHECK-NEXT: lxv v2, 0(r3) ; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: xscvqpswz v2, v2 ; CHECK-NEXT: xscvqpswz v2, v2
; CHECK-NEXT: mfvsrwz r3, v2 ; CHECK-NEXT: mfvsrwz r3, v2
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: qpConv2uhw: ; CHECK-P8-LABEL: qpConv2uhw:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: std r0, 48(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl __fixkfsi ; CHECK-P8-NEXT: bl __fixkfsi
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addi r1, r1, 32 ; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
Show All 18 Lines
; ;
; CHECK-P8-LABEL: qpConv2uhw_02: ; CHECK-P8-LABEL: qpConv2uhw_02:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-P8-NEXT: addi r4, r4, 32 ; CHECK-P8-NEXT: addi r4, r4, 32
; CHECK-P8-NEXT: lxvd2x vs0, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl __fixkfsi ; CHECK-P8-NEXT: bl __fixkfsi
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: sth r3, 0(r30) ; CHECK-P8-NEXT: sth r3, 0(r30)
Show All 22 Lines
; CHECK-NEXT: xsaddqp v2, v2, v3 ; CHECK-NEXT: xsaddqp v2, v2, v3
; CHECK-NEXT: xscvqpswz v2, v2 ; CHECK-NEXT: xscvqpswz v2, v2
; CHECK-NEXT: mfvsrwz r3, v2 ; CHECK-NEXT: mfvsrwz r3, v2
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: qpConv2uhw_03: ; CHECK-P8-LABEL: qpConv2uhw_03:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: std r0, 48(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: addi r4, r4, 16 ; CHECK-P8-NEXT: addi r4, r4, 16
; CHECK-P8-NEXT: lxvd2x vs1, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
Show All 29 Lines
; ;
; CHECK-P8-LABEL: qpConv2uhw_04: ; CHECK-P8-LABEL: qpConv2uhw_04:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: mr r30, r5
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: lxvd2x vs1, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: mr r30, r5
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxswapd v3, vs1 ; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: bl __addkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: bl __fixkfsi ; CHECK-P8-NEXT: bl __fixkfsi
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: sth r3, 0(r30) ; CHECK-P8-NEXT: sth r3, 0(r30)
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
Show All 19 Lines
; CHECK-NEXT: xscvqpswz v2, v2 ; CHECK-NEXT: xscvqpswz v2, v2
; CHECK-NEXT: mfvsrwz r3, v2 ; CHECK-NEXT: mfvsrwz r3, v2
; CHECK-NEXT: extsw r3, r3 ; CHECK-NEXT: extsw r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: qpConv2sb: ; CHECK-P8-LABEL: qpConv2sb:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: std r0, 48(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl __fixkfsi ; CHECK-P8-NEXT: bl __fixkfsi
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: extsw r3, r3 ; CHECK-P8-NEXT: extsw r3, r3
; CHECK-P8-NEXT: addi r1, r1, 32 ; CHECK-P8-NEXT: addi r1, r1, 32
Show All 19 Lines
; ;
; CHECK-P8-LABEL: qpConv2sb_02: ; CHECK-P8-LABEL: qpConv2sb_02:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-P8-NEXT: addi r4, r4, 32 ; CHECK-P8-NEXT: addi r4, r4, 32
; CHECK-P8-NEXT: lxvd2x vs0, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl __fixkfsi ; CHECK-P8-NEXT: bl __fixkfsi
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stb r3, 0(r30) ; CHECK-P8-NEXT: stb r3, 0(r30)
Show All 23 Lines
; CHECK-NEXT: xscvqpswz v2, v2 ; CHECK-NEXT: xscvqpswz v2, v2
; CHECK-NEXT: mfvsrwz r3, v2 ; CHECK-NEXT: mfvsrwz r3, v2
; CHECK-NEXT: extsw r3, r3 ; CHECK-NEXT: extsw r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: qpConv2sb_03: ; CHECK-P8-LABEL: qpConv2sb_03:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: std r0, 48(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: addi r4, r4, 16 ; CHECK-P8-NEXT: addi r4, r4, 16
; CHECK-P8-NEXT: lxvd2x vs1, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
Show All 30 Lines
; ;
; CHECK-P8-LABEL: qpConv2sb_04: ; CHECK-P8-LABEL: qpConv2sb_04:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: mr r30, r5
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: lxvd2x vs1, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: mr r30, r5
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxswapd v3, vs1 ; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: bl __addkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: bl __fixkfsi ; CHECK-P8-NEXT: bl __fixkfsi
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stb r3, 0(r30) ; CHECK-P8-NEXT: stb r3, 0(r30)
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
Show All 18 Lines
; CHECK-NEXT: lxv v2, 0(r3) ; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: xscvqpswz v2, v2 ; CHECK-NEXT: xscvqpswz v2, v2
; CHECK-NEXT: mfvsrwz r3, v2 ; CHECK-NEXT: mfvsrwz r3, v2
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: qpConv2ub: ; CHECK-P8-LABEL: qpConv2ub:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: std r0, 48(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl __fixkfsi ; CHECK-P8-NEXT: bl __fixkfsi
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addi r1, r1, 32 ; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
Show All 18 Lines
; ;
; CHECK-P8-LABEL: qpConv2ub_02: ; CHECK-P8-LABEL: qpConv2ub_02:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: mr r30, r3 ; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-P8-NEXT: addi r4, r4, 32 ; CHECK-P8-NEXT: addi r4, r4, 32
; CHECK-P8-NEXT: lxvd2x vs0, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: bl __fixkfsi ; CHECK-P8-NEXT: bl __fixkfsi
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stb r3, 0(r30) ; CHECK-P8-NEXT: stb r3, 0(r30)
Show All 22 Lines
; CHECK-NEXT: xsaddqp v2, v2, v3 ; CHECK-NEXT: xsaddqp v2, v2, v3
; CHECK-NEXT: xscvqpswz v2, v2 ; CHECK-NEXT: xscvqpswz v2, v2
; CHECK-NEXT: mfvsrwz r3, v2 ; CHECK-NEXT: mfvsrwz r3, v2
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: qpConv2ub_03: ; CHECK-P8-LABEL: qpConv2ub_03:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: std r0, 48(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: addi r4, r4, 16 ; CHECK-P8-NEXT: addi r4, r4, 16
; CHECK-P8-NEXT: lxvd2x vs1, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
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; ;
; CHECK-P8-LABEL: qpConv2ub_04: ; CHECK-P8-LABEL: qpConv2ub_04:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: mr r30, r5
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: lxvd2x vs1, 0, r4 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
; CHECK-P8-NEXT: mr r30, r5
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxswapd v3, vs1 ; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: bl __addkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: bl __fixkfsi ; CHECK-P8-NEXT: bl __fixkfsi
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stb r3, 0(r30) ; CHECK-P8-NEXT: stb r3, 0(r30)
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
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define void @qpConvppcf128(fp128 %src, ptr %dst) { define void @qpConvppcf128(fp128 %src, ptr %dst) {
; CHECK-LABEL: qpConvppcf128: ; CHECK-LABEL: qpConvppcf128:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr r0 ; CHECK-NEXT: mflr r0
; CHECK-NEXT: .cfi_def_cfa_offset 48 ; CHECK-NEXT: .cfi_def_cfa_offset 48
; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: .cfi_offset r30, -16 ; CHECK-NEXT: .cfi_offset r30, -16
; CHECK-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-NEXT: std r0, 16(r1)
; CHECK-NEXT: stdu r1, -48(r1) ; CHECK-NEXT: stdu r1, -48(r1)
; CHECK-NEXT: std r0, 64(r1)
; CHECK-NEXT: mr r30, r5 ; CHECK-NEXT: mr r30, r5
; CHECK-NEXT: bl __extendkftf2 ; CHECK-NEXT: bl __extendkftf2
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: stfd f2, 8(r30) ; CHECK-NEXT: stfd f2, 8(r30)
; CHECK-NEXT: stfd f1, 0(r30) ; CHECK-NEXT: stfd f1, 0(r30)
; CHECK-NEXT: addi r1, r1, 48 ; CHECK-NEXT: addi r1, r1, 48
; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: ld r0, 16(r1)
; CHECK-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: mtlr r0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: qpConvppcf128: ; CHECK-P8-LABEL: qpConvppcf128:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: mr r30, r5 ; CHECK-P8-NEXT: mr r30, r5
; CHECK-P8-NEXT: bl __extendkftf2 ; CHECK-P8-NEXT: bl __extendkftf2
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stfd f2, 8(r30) ; CHECK-P8-NEXT: stfd f2, 8(r30)
; CHECK-P8-NEXT: stfd f1, 0(r30) ; CHECK-P8-NEXT: stfd f1, 0(r30)
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
entry: entry:
%res = call ppc_fp128 @llvm.ppc.convert.f128.to.ppcf128(fp128 %src) %res = call ppc_fp128 @llvm.ppc.convert.f128.to.ppcf128(fp128 %src)
store ppc_fp128 %res, ptr %dst, align 16 store ppc_fp128 %res, ptr %dst, align 16
ret void ret void
} }
define void @ppcf128Convqp(ppc_fp128 %src, ptr %dst) { define void @ppcf128Convqp(ppc_fp128 %src, ptr %dst) {
; CHECK-LABEL: ppcf128Convqp: ; CHECK-LABEL: ppcf128Convqp:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr r0 ; CHECK-NEXT: mflr r0
; CHECK-NEXT: .cfi_def_cfa_offset 48 ; CHECK-NEXT: .cfi_def_cfa_offset 48
; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: .cfi_offset r30, -16 ; CHECK-NEXT: .cfi_offset r30, -16
; CHECK-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-NEXT: std r0, 16(r1)
; CHECK-NEXT: stdu r1, -48(r1) ; CHECK-NEXT: stdu r1, -48(r1)
; CHECK-NEXT: std r0, 64(r1)
; CHECK-NEXT: mr r30, r5 ; CHECK-NEXT: mr r30, r5
; CHECK-NEXT: bl __trunctfkf2 ; CHECK-NEXT: bl __trunctfkf2
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: stxv v2, 0(r30) ; CHECK-NEXT: stxv v2, 0(r30)
; CHECK-NEXT: addi r1, r1, 48 ; CHECK-NEXT: addi r1, r1, 48
; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: ld r0, 16(r1)
; CHECK-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: mtlr r0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: ppcf128Convqp: ; CHECK-P8-LABEL: ppcf128Convqp:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16 ; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: mr r30, r5 ; CHECK-P8-NEXT: mr r30, r5
; CHECK-P8-NEXT: bl __trunctfkf2 ; CHECK-P8-NEXT: bl __trunctfkf2
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
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llvm/test/CodeGen/PowerPC/fast-isel-branch.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s -check-prefix=ELF64 ; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s -check-prefix=ELF64
; RUN: llc -mtriple=powerpc64-ibm-aix-xcoff < %s | FileCheck %s -check-prefix=AIX64 ; RUN: llc -mtriple=powerpc64-ibm-aix-xcoff < %s | FileCheck %s -check-prefix=AIX64
@x = global i32 1000, align 4 @x = global i32 1000, align 4
define signext i32 @bar() #0 { define signext i32 @bar() #0 {
; ELF64-LABEL: bar: ; ELF64-LABEL: bar:
; ELF64: # %bb.0: # %entry ; ELF64: # %bb.0: # %entry
; ELF64-NEXT: mflr 0 ; ELF64-NEXT: mflr 0
; ELF64-NEXT: std 0, 16(1)
; ELF64-NEXT: stdu 1, -48(1) ; ELF64-NEXT: stdu 1, -48(1)
; ELF64-NEXT: std 0, 64(1)
; ELF64-NEXT: .cfi_def_cfa_offset 48 ; ELF64-NEXT: .cfi_def_cfa_offset 48
; ELF64-NEXT: .cfi_offset lr, 16 ; ELF64-NEXT: .cfi_offset lr, 16
; ELF64-NEXT: li 3, 0 ; ELF64-NEXT: li 3, 0
; ELF64-NEXT: stw 3, 44(1) ; ELF64-NEXT: stw 3, 44(1)
; ELF64-NEXT: li 3, 0 ; ELF64-NEXT: li 3, 0
; ELF64-NEXT: stw 3, 40(1) ; ELF64-NEXT: stw 3, 40(1)
; ELF64-NEXT: .LBB0_1: # %for.cond ; ELF64-NEXT: .LBB0_1: # %for.cond
; ELF64-NEXT: # ; ELF64-NEXT: #
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; ELF64-NEXT: addi 1, 1, 48 ; ELF64-NEXT: addi 1, 1, 48
; ELF64-NEXT: ld 0, 16(1) ; ELF64-NEXT: ld 0, 16(1)
; ELF64-NEXT: mtlr 0 ; ELF64-NEXT: mtlr 0
; ELF64-NEXT: blr ; ELF64-NEXT: blr
; ;
; AIX64-LABEL: bar: ; AIX64-LABEL: bar:
; AIX64: # %bb.0: # %entry ; AIX64: # %bb.0: # %entry
; AIX64-NEXT: mflr 0 ; AIX64-NEXT: mflr 0
; AIX64-NEXT: std 0, 16(1)
; AIX64-NEXT: stdu 1, -128(1) ; AIX64-NEXT: stdu 1, -128(1)
; AIX64-NEXT: std 0, 144(1)
; AIX64-NEXT: li 3, 0 ; AIX64-NEXT: li 3, 0
; AIX64-NEXT: stw 3, 124(1) ; AIX64-NEXT: stw 3, 124(1)
; AIX64-NEXT: li 3, 0 ; AIX64-NEXT: li 3, 0
; AIX64-NEXT: stw 3, 120(1) ; AIX64-NEXT: stw 3, 120(1)
; AIX64-NEXT: L..BB0_1: # %for.cond ; AIX64-NEXT: L..BB0_1: # %for.cond
; AIX64-NEXT: # ; AIX64-NEXT: #
; AIX64-NEXT: lwz 3, 120(1) ; AIX64-NEXT: lwz 3, 120(1)
; AIX64-NEXT: ld 4, L..C0(2) ; AIX64-NEXT: ld 4, L..C0(2) # @x
; AIX64-NEXT: lwz 4, 0(4) ; AIX64-NEXT: lwz 4, 0(4)
; AIX64-NEXT: cmpw 3, 4 ; AIX64-NEXT: cmpw 3, 4
; AIX64-NEXT: bge 0, L..BB0_4 ; AIX64-NEXT: bge 0, L..BB0_4
; AIX64-NEXT: # %bb.2: # %for.body ; AIX64-NEXT: # %bb.2: # %for.body
; AIX64-NEXT: # ; AIX64-NEXT: #
; AIX64-NEXT: bl .foo[PR] ; AIX64-NEXT: bl .foo[PR]
; AIX64-NEXT: nop ; AIX64-NEXT: nop
; AIX64-NEXT: # %bb.3: # %for.inc ; AIX64-NEXT: # %bb.3: # %for.inc
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llvm/test/CodeGen/PowerPC/float-load-store-pair.ll

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@a17 = dso_local local_unnamed_addr global fp128 0xL00000000000000000000000000000000, align 16 @a17 = dso_local local_unnamed_addr global fp128 0xL00000000000000000000000000000000, align 16
; Because this test function is trying to pass float argument by stack, ; Because this test function is trying to pass float argument by stack,
; so the fpr is only used to load/store float argument ; so the fpr is only used to load/store float argument
define dso_local signext i32 @test() nounwind { define dso_local signext i32 @test() nounwind {
; CHECK-LABEL: test: ; CHECK-LABEL: test:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; CHECK-NEXT: std 0, 16(1)
; CHECK-NEXT: stdu 1, -192(1) ; CHECK-NEXT: stdu 1, -192(1)
; CHECK-NEXT: addis 3, 2, a1@toc@ha ; CHECK-NEXT: addis 3, 2, a1@toc@ha
; CHECK-NEXT: std 0, 208(1)
; CHECK-NEXT: addis 5, 2, a16@toc@ha ; CHECK-NEXT: addis 5, 2, a16@toc@ha
; CHECK-NEXT: addis 6, 2, a17@toc@ha ; CHECK-NEXT: addis 6, 2, a17@toc@ha
; CHECK-NEXT: addis 4, 2, a15@toc@ha ; CHECK-NEXT: addis 4, 2, a15@toc@ha
; CHECK-NEXT: lfd 1, a1@toc@l(3) ; CHECK-NEXT: lfd 1, a1@toc@l(3)
; CHECK-NEXT: addis 3, 2, a2@toc@ha ; CHECK-NEXT: addis 3, 2, a2@toc@ha
; CHECK-NEXT: addi 5, 5, a16@toc@l ; CHECK-NEXT: addi 5, 5, a16@toc@l
; CHECK-NEXT: addi 6, 6, a17@toc@l ; CHECK-NEXT: addi 6, 6, a17@toc@l
; CHECK-NEXT: ld 4, a15@toc@l(4) ; CHECK-NEXT: ld 4, a15@toc@l(4)
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llvm/test/CodeGen/PowerPC/fmf-propagation.ll

Show First 20 Lines • Show All 587 Lines • ▼ Show 20 Lines
; GLOBALDEBUG: f64,ch,glue = CopyFromReg t16, Register:f64 $f1, t16:1 ; GLOBALDEBUG: f64,ch,glue = CopyFromReg t16, Register:f64 $f1, t16:1
; GLOBALDEBUG: Type-legalized selection DAG: %bb.0 'log2_approx:' ; GLOBALDEBUG: Type-legalized selection DAG: %bb.0 'log2_approx:'
declare double @log2(double) declare double @log2(double)
define double @log2_approx(double %x) nounwind { define double @log2_approx(double %x) nounwind {
; FMF-LABEL: log2_approx: ; FMF-LABEL: log2_approx:
; FMF: # %bb.0: ; FMF: # %bb.0:
; FMF-NEXT: mflr 0 ; FMF-NEXT: mflr 0
; FMF-NEXT: std 0, 16(1)
; FMF-NEXT: stdu 1, -32(1) ; FMF-NEXT: stdu 1, -32(1)
; FMF-NEXT: std 0, 48(1)
; FMF-NEXT: bl log2 ; FMF-NEXT: bl log2
; FMF-NEXT: nop ; FMF-NEXT: nop
; FMF-NEXT: addi 1, 1, 32 ; FMF-NEXT: addi 1, 1, 32
; FMF-NEXT: ld 0, 16(1) ; FMF-NEXT: ld 0, 16(1)
; FMF-NEXT: mtlr 0 ; FMF-NEXT: mtlr 0
; FMF-NEXT: blr ; FMF-NEXT: blr
; ;
; GLOBAL-LABEL: log2_approx: ; GLOBAL-LABEL: log2_approx:
; GLOBAL: # %bb.0: ; GLOBAL: # %bb.0:
; GLOBAL-NEXT: mflr 0 ; GLOBAL-NEXT: mflr 0
; GLOBAL-NEXT: std 0, 16(1)
; GLOBAL-NEXT: stdu 1, -32(1) ; GLOBAL-NEXT: stdu 1, -32(1)
; GLOBAL-NEXT: std 0, 48(1)
; GLOBAL-NEXT: bl log2 ; GLOBAL-NEXT: bl log2
; GLOBAL-NEXT: nop ; GLOBAL-NEXT: nop
; GLOBAL-NEXT: addi 1, 1, 32 ; GLOBAL-NEXT: addi 1, 1, 32
; GLOBAL-NEXT: ld 0, 16(1) ; GLOBAL-NEXT: ld 0, 16(1)
; GLOBAL-NEXT: mtlr 0 ; GLOBAL-NEXT: mtlr 0
; GLOBAL-NEXT: blr ; GLOBAL-NEXT: blr
%r = call afn double @log2(double %x) %r = call afn double @log2(double %x)
ret double %r ret double %r
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; GLOBAL-NEXT: blr ; GLOBAL-NEXT: blr
%neg = fsub float %x, %y %neg = fsub float %x, %y
%add = fsub nsz float 0.0, %neg %add = fsub nsz float 0.0, %neg
ret float %add ret float %add
} }
attributes #0 = { "denormal-fp-math"="ieee,ieee" } attributes #0 = { "denormal-fp-math"="ieee,ieee" }
attributes #1 = { "denormal-fp-math"="preserve-sign,preserve-sign" } attributes #1 = { "denormal-fp-math"="preserve-sign,preserve-sign" }
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; FMFDEBUG: {{.*}}
; GLOBALDEBUG: {{.*}}

llvm/test/CodeGen/PowerPC/fminnum.ll

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declare <2 x float> @llvm.minnum.v2f32(<2 x float>, <2 x float>) declare <2 x float> @llvm.minnum.v2f32(<2 x float>, <2 x float>)
declare <4 x float> @llvm.minnum.v4f32(<4 x float>, <4 x float>) declare <4 x float> @llvm.minnum.v4f32(<4 x float>, <4 x float>)
declare <8 x float> @llvm.minnum.v8f32(<8 x float>, <8 x float>) declare <8 x float> @llvm.minnum.v8f32(<8 x float>, <8 x float>)
define float @test_fminf(float %x, float %y) { define float @test_fminf(float %x, float %y) {
; CHECK-LABEL: test_fminf: ; CHECK-LABEL: test_fminf:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; CHECK-NEXT: stw 0, 4(1)
; CHECK-NEXT: stwu 1, -16(1) ; CHECK-NEXT: stwu 1, -16(1)
; CHECK-NEXT: stw 0, 20(1)
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset lr, 4 ; CHECK-NEXT: .cfi_offset lr, 4
; CHECK-NEXT: bl fminf ; CHECK-NEXT: bl fminf
; CHECK-NEXT: lwz 0, 20(1) ; CHECK-NEXT: lwz 0, 20(1)
; CHECK-NEXT: addi 1, 1, 16 ; CHECK-NEXT: addi 1, 1, 16
; CHECK-NEXT: mtlr 0 ; CHECK-NEXT: mtlr 0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%z = call float @fminf(float %x, float %y) readnone %z = call float @fminf(float %x, float %y) readnone
ret float %z ret float %z
} }
define double @test_fmin(double %x, double %y) { define double @test_fmin(double %x, double %y) {
; CHECK-LABEL: test_fmin: ; CHECK-LABEL: test_fmin:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; CHECK-NEXT: stw 0, 4(1)
; CHECK-NEXT: stwu 1, -16(1) ; CHECK-NEXT: stwu 1, -16(1)
; CHECK-NEXT: stw 0, 20(1)
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset lr, 4 ; CHECK-NEXT: .cfi_offset lr, 4
; CHECK-NEXT: bl fmin ; CHECK-NEXT: bl fmin
; CHECK-NEXT: lwz 0, 20(1) ; CHECK-NEXT: lwz 0, 20(1)
; CHECK-NEXT: addi 1, 1, 16 ; CHECK-NEXT: addi 1, 1, 16
; CHECK-NEXT: mtlr 0 ; CHECK-NEXT: mtlr 0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%z = call double @fmin(double %x, double %y) readnone %z = call double @fmin(double %x, double %y) readnone
ret double %z ret double %z
} }
define ppc_fp128 @test_fminl(ppc_fp128 %x, ppc_fp128 %y) { define ppc_fp128 @test_fminl(ppc_fp128 %x, ppc_fp128 %y) {
; CHECK-LABEL: test_fminl: ; CHECK-LABEL: test_fminl:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; CHECK-NEXT: stw 0, 4(1)
; CHECK-NEXT: stwu 1, -112(1) ; CHECK-NEXT: stwu 1, -112(1)
; CHECK-NEXT: stw 0, 116(1)
; CHECK-NEXT: .cfi_def_cfa_offset 112 ; CHECK-NEXT: .cfi_def_cfa_offset 112
; CHECK-NEXT: .cfi_offset lr, 4 ; CHECK-NEXT: .cfi_offset lr, 4
; CHECK-NEXT: stfd 1, 40(1) ; CHECK-NEXT: stfd 1, 40(1)
; CHECK-NEXT: lwz 3, 44(1) ; CHECK-NEXT: lwz 3, 44(1)
; CHECK-NEXT: stfd 2, 32(1) ; CHECK-NEXT: stfd 2, 32(1)
; CHECK-NEXT: stw 3, 60(1) ; CHECK-NEXT: stw 3, 60(1)
; CHECK-NEXT: lwz 3, 40(1) ; CHECK-NEXT: lwz 3, 40(1)
; CHECK-NEXT: stfd 3, 72(1) ; CHECK-NEXT: stfd 3, 72(1)
Show All 35 Lines; CHECK-NEXT: blr
%z = call ppc_fp128 @fminl(ppc_fp128 %x, ppc_fp128 %y) readnone %z = call ppc_fp128 @fminl(ppc_fp128 %x, ppc_fp128 %y) readnone
ret ppc_fp128 %z ret ppc_fp128 %z
} }
define float @test_intrinsic_fmin_f32(float %x, float %y) { define float @test_intrinsic_fmin_f32(float %x, float %y) {
; CHECK-LABEL: test_intrinsic_fmin_f32: ; CHECK-LABEL: test_intrinsic_fmin_f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; CHECK-NEXT: stw 0, 4(1)
; CHECK-NEXT: stwu 1, -16(1) ; CHECK-NEXT: stwu 1, -16(1)
; CHECK-NEXT: stw 0, 20(1)
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset lr, 4 ; CHECK-NEXT: .cfi_offset lr, 4
; CHECK-NEXT: bl fminf ; CHECK-NEXT: bl fminf
; CHECK-NEXT: lwz 0, 20(1) ; CHECK-NEXT: lwz 0, 20(1)
; CHECK-NEXT: addi 1, 1, 16 ; CHECK-NEXT: addi 1, 1, 16
; CHECK-NEXT: mtlr 0 ; CHECK-NEXT: mtlr 0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%z = call float @llvm.minnum.f32(float %x, float %y) readnone %z = call float @llvm.minnum.f32(float %x, float %y) readnone
ret float %z ret float %z
} }
define double @test_intrinsic_fmin_f64(double %x, double %y) { define double @test_intrinsic_fmin_f64(double %x, double %y) {
; CHECK-LABEL: test_intrinsic_fmin_f64: ; CHECK-LABEL: test_intrinsic_fmin_f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; CHECK-NEXT: stw 0, 4(1)
; CHECK-NEXT: stwu 1, -16(1) ; CHECK-NEXT: stwu 1, -16(1)
; CHECK-NEXT: stw 0, 20(1)
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset lr, 4 ; CHECK-NEXT: .cfi_offset lr, 4
; CHECK-NEXT: bl fmin ; CHECK-NEXT: bl fmin
; CHECK-NEXT: lwz 0, 20(1) ; CHECK-NEXT: lwz 0, 20(1)
; CHECK-NEXT: addi 1, 1, 16 ; CHECK-NEXT: addi 1, 1, 16
; CHECK-NEXT: mtlr 0 ; CHECK-NEXT: mtlr 0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%z = call double @llvm.minnum.f64(double %x, double %y) readnone %z = call double @llvm.minnum.f64(double %x, double %y) readnone
ret double %z ret double %z
} }
define ppc_fp128 @test_intrinsic_fmin_f128(ppc_fp128 %x, ppc_fp128 %y) { define ppc_fp128 @test_intrinsic_fmin_f128(ppc_fp128 %x, ppc_fp128 %y) {
; CHECK-LABEL: test_intrinsic_fmin_f128: ; CHECK-LABEL: test_intrinsic_fmin_f128:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; CHECK-NEXT: stw 0, 4(1)
; CHECK-NEXT: stwu 1, -112(1) ; CHECK-NEXT: stwu 1, -112(1)
; CHECK-NEXT: stw 0, 116(1)
; CHECK-NEXT: .cfi_def_cfa_offset 112 ; CHECK-NEXT: .cfi_def_cfa_offset 112
; CHECK-NEXT: .cfi_offset lr, 4 ; CHECK-NEXT: .cfi_offset lr, 4
; CHECK-NEXT: stfd 1, 40(1) ; CHECK-NEXT: stfd 1, 40(1)
; CHECK-NEXT: lwz 3, 44(1) ; CHECK-NEXT: lwz 3, 44(1)
; CHECK-NEXT: stfd 2, 32(1) ; CHECK-NEXT: stfd 2, 32(1)
; CHECK-NEXT: stw 3, 60(1) ; CHECK-NEXT: stw 3, 60(1)
; CHECK-NEXT: lwz 3, 40(1) ; CHECK-NEXT: lwz 3, 40(1)
; CHECK-NEXT: stfd 3, 72(1) ; CHECK-NEXT: stfd 3, 72(1)
Show All 35 Lines; CHECK-NEXT: blr
%z = call ppc_fp128 @llvm.minnum.ppcf128(ppc_fp128 %x, ppc_fp128 %y) readnone %z = call ppc_fp128 @llvm.minnum.ppcf128(ppc_fp128 %x, ppc_fp128 %y) readnone
ret ppc_fp128 %z ret ppc_fp128 %z
} }
define <2 x float> @test_intrinsic_fminf_v2f32(<2 x float> %x, <2 x float> %y) { define <2 x float> @test_intrinsic_fminf_v2f32(<2 x float> %x, <2 x float> %y) {
; CHECK-LABEL: test_intrinsic_fminf_v2f32: ; CHECK-LABEL: test_intrinsic_fminf_v2f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; CHECK-NEXT: stw 0, 4(1)
; CHECK-NEXT: stwu 1, -32(1) ; CHECK-NEXT: stwu 1, -32(1)
; CHECK-NEXT: stw 0, 36(1)
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset lr, 4 ; CHECK-NEXT: .cfi_offset lr, 4
; CHECK-NEXT: .cfi_offset f29, -24 ; CHECK-NEXT: .cfi_offset f29, -24
; CHECK-NEXT: .cfi_offset f30, -16 ; CHECK-NEXT: .cfi_offset f30, -16
; CHECK-NEXT: .cfi_offset f31, -8 ; CHECK-NEXT: .cfi_offset f31, -8
; CHECK-NEXT: stfd 30, 16(1) # 8-byte Folded Spill ; CHECK-NEXT: stfd 30, 16(1) # 8-byte Folded Spill
; CHECK-NEXT: fmr 30, 2 ; CHECK-NEXT: fmr 30, 2
; CHECK-NEXT: fmr 2, 3 ; CHECK-NEXT: fmr 2, 3
Show All 17 Lines; CHECK-NEXT: blr
%z = call <2 x float> @llvm.minnum.v2f32(<2 x float> %x, <2 x float> %y) readnone %z = call <2 x float> @llvm.minnum.v2f32(<2 x float> %x, <2 x float> %y) readnone
ret <2 x float> %z ret <2 x float> %z
} }
define <4 x float> @test_intrinsic_fmin_v4f32(<4 x float> %x, <4 x float> %y) { define <4 x float> @test_intrinsic_fmin_v4f32(<4 x float> %x, <4 x float> %y) {
; CHECK-LABEL: test_intrinsic_fmin_v4f32: ; CHECK-LABEL: test_intrinsic_fmin_v4f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; CHECK-NEXT: stw 0, 4(1)
; CHECK-NEXT: stwu 1, -64(1) ; CHECK-NEXT: stwu 1, -64(1)
; CHECK-NEXT: stw 0, 68(1)
; CHECK-NEXT: .cfi_def_cfa_offset 64 ; CHECK-NEXT: .cfi_def_cfa_offset 64
; CHECK-NEXT: .cfi_offset lr, 4 ; CHECK-NEXT: .cfi_offset lr, 4
; CHECK-NEXT: .cfi_offset f25, -56 ; CHECK-NEXT: .cfi_offset f25, -56
; CHECK-NEXT: .cfi_offset f26, -48 ; CHECK-NEXT: .cfi_offset f26, -48
; CHECK-NEXT: .cfi_offset f27, -40 ; CHECK-NEXT: .cfi_offset f27, -40
; CHECK-NEXT: .cfi_offset f28, -32 ; CHECK-NEXT: .cfi_offset f28, -32
; CHECK-NEXT: .cfi_offset f29, -24 ; CHECK-NEXT: .cfi_offset f29, -24
; CHECK-NEXT: .cfi_offset f30, -16 ; CHECK-NEXT: .cfi_offset f30, -16
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines; CHECK-NEXT: blr
%z = call <4 x float> @llvm.minnum.v4f32(<4 x float> %x, <4 x float> %y) readnone %z = call <4 x float> @llvm.minnum.v4f32(<4 x float> %x, <4 x float> %y) readnone
ret <4 x float> %z ret <4 x float> %z
} }
define <8 x float> @test_intrinsic_fmin_v8f32(<8 x float> %x, <8 x float> %y) { define <8 x float> @test_intrinsic_fmin_v8f32(<8 x float> %x, <8 x float> %y) {
; CHECK-LABEL: test_intrinsic_fmin_v8f32: ; CHECK-LABEL: test_intrinsic_fmin_v8f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; CHECK-NEXT: stw 0, 4(1)
; CHECK-NEXT: stwu 1, -128(1) ; CHECK-NEXT: stwu 1, -128(1)
; CHECK-NEXT: stw 0, 132(1)
; CHECK-NEXT: .cfi_def_cfa_offset 128 ; CHECK-NEXT: .cfi_def_cfa_offset 128
; CHECK-NEXT: .cfi_offset lr, 4 ; CHECK-NEXT: .cfi_offset lr, 4
; CHECK-NEXT: .cfi_offset f17, -120 ; CHECK-NEXT: .cfi_offset f17, -120
; CHECK-NEXT: .cfi_offset f18, -112 ; CHECK-NEXT: .cfi_offset f18, -112
; CHECK-NEXT: .cfi_offset f19, -104 ; CHECK-NEXT: .cfi_offset f19, -104
; CHECK-NEXT: .cfi_offset f20, -96 ; CHECK-NEXT: .cfi_offset f20, -96
; CHECK-NEXT: .cfi_offset f21, -88 ; CHECK-NEXT: .cfi_offset f21, -88
; CHECK-NEXT: .cfi_offset f22, -80 ; CHECK-NEXT: .cfi_offset f22, -80
▲ Show 20 Lines • Show All 95 Lines • ▼ Show 20 Lines; CHECK-NEXT: blr
%z = call <8 x float> @llvm.minnum.v8f32(<8 x float> %x, <8 x float> %y) readnone %z = call <8 x float> @llvm.minnum.v8f32(<8 x float> %x, <8 x float> %y) readnone
ret <8 x float> %z ret <8 x float> %z
} }
define ppc_fp128 @fminnum_const(ppc_fp128 %0) { define ppc_fp128 @fminnum_const(ppc_fp128 %0) {
; CHECK-LABEL: fminnum_const: ; CHECK-LABEL: fminnum_const:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; CHECK-NEXT: stw 0, 4(1)
; CHECK-NEXT: stwu 1, -96(1) ; CHECK-NEXT: stwu 1, -96(1)
; CHECK-NEXT: stw 0, 100(1)
; CHECK-NEXT: .cfi_def_cfa_offset 96 ; CHECK-NEXT: .cfi_def_cfa_offset 96
; CHECK-NEXT: .cfi_offset lr, 4 ; CHECK-NEXT: .cfi_offset lr, 4
; CHECK-NEXT: stfd 1, 40(1) ; CHECK-NEXT: stfd 1, 40(1)
; CHECK-NEXT: li 3, 0 ; CHECK-NEXT: li 3, 0
; CHECK-NEXT: stw 3, 76(1) ; CHECK-NEXT: stw 3, 76(1)
; CHECK-NEXT: lis 4, 16368 ; CHECK-NEXT: lis 4, 16368
; CHECK-NEXT: stw 3, 68(1) ; CHECK-NEXT: stw 3, 68(1)
; CHECK-NEXT: stw 3, 64(1) ; CHECK-NEXT: stw 3, 64(1)
Show All 35 Lines

llvm/test/CodeGen/PowerPC/fp-int128-fp-combine.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -O0 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s ; RUN: llc -O0 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
; xscvdpsxds should NOT be emitted, since it saturates the result down to i64. ; xscvdpsxds should NOT be emitted, since it saturates the result down to i64.
; We can't use friz here because it may return -0.0 where the original code doesn't. ; We can't use friz here because it may return -0.0 where the original code doesn't.
define float @f_i128_f(float %v) nounwind { define float @f_i128_f(float %v) nounwind {
; CHECK-LABEL: f_i128_f: ; CHECK-LABEL: f_i128_f:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; CHECK-NEXT: std 0, 16(1)
; CHECK-NEXT: stdu 1, -32(1) ; CHECK-NEXT: stdu 1, -32(1)
; CHECK-NEXT: std 0, 48(1)
; CHECK-NEXT: bl __fixsfti ; CHECK-NEXT: bl __fixsfti
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: bl __floattisf ; CHECK-NEXT: bl __floattisf
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: addi 1, 1, 32 ; CHECK-NEXT: addi 1, 1, 32
; CHECK-NEXT: ld 0, 16(1) ; CHECK-NEXT: ld 0, 16(1)
; CHECK-NEXT: mtlr 0 ; CHECK-NEXT: mtlr 0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
Show All 21 Lines

llvm/test/CodeGen/PowerPC/fp-strict-conv-f128.ll

Show All 40 Lines
declare ppc_fp128 @llvm.experimental.constrained.uitofp.ppcf128.i1(i1, metadata, metadata) declare ppc_fp128 @llvm.experimental.constrained.uitofp.ppcf128.i1(i1, metadata, metadata)
declare ppc_fp128 @llvm.experimental.constrained.uitofp.ppcf128.i32(i32, metadata, metadata) declare ppc_fp128 @llvm.experimental.constrained.uitofp.ppcf128.i32(i32, metadata, metadata)
declare ppc_fp128 @llvm.experimental.constrained.uitofp.ppcf128.i64(i64, metadata, metadata) declare ppc_fp128 @llvm.experimental.constrained.uitofp.ppcf128.i64(i64, metadata, metadata)
define i128 @q_to_i128(fp128 %m) #0 { define i128 @q_to_i128(fp128 %m) #0 {
; P8-LABEL: q_to_i128: ; P8-LABEL: q_to_i128:
; P8: # %bb.0: # %entry ; P8: # %bb.0: # %entry
; P8-NEXT: mflr r0 ; P8-NEXT: mflr r0
; P8-NEXT: std r0, 16(r1)
; P8-NEXT: stdu r1, -112(r1) ; P8-NEXT: stdu r1, -112(r1)
; P8-NEXT: std r0, 128(r1)
; P8-NEXT: .cfi_def_cfa_offset 112 ; P8-NEXT: .cfi_def_cfa_offset 112
; P8-NEXT: .cfi_offset lr, 16 ; P8-NEXT: .cfi_offset lr, 16
; P8-NEXT: bl __fixkfti ; P8-NEXT: bl __fixkfti
; P8-NEXT: nop ; P8-NEXT: nop
; P8-NEXT: addi r1, r1, 112 ; P8-NEXT: addi r1, r1, 112
; P8-NEXT: ld r0, 16(r1) ; P8-NEXT: ld r0, 16(r1)
; P8-NEXT: mtlr r0 ; P8-NEXT: mtlr r0
; P8-NEXT: blr ; P8-NEXT: blr
; ;
; P9-LABEL: q_to_i128: ; P9-LABEL: q_to_i128:
; P9: # %bb.0: # %entry ; P9: # %bb.0: # %entry
; P9-NEXT: mflr r0 ; P9-NEXT: mflr r0
; P9-NEXT: std r0, 16(r1)
; P9-NEXT: stdu r1, -32(r1) ; P9-NEXT: stdu r1, -32(r1)
; P9-NEXT: std r0, 48(r1)
; P9-NEXT: .cfi_def_cfa_offset 32 ; P9-NEXT: .cfi_def_cfa_offset 32
; P9-NEXT: .cfi_offset lr, 16 ; P9-NEXT: .cfi_offset lr, 16
; P9-NEXT: bl __fixkfti ; P9-NEXT: bl __fixkfti
; P9-NEXT: nop ; P9-NEXT: nop
; P9-NEXT: addi r1, r1, 32 ; P9-NEXT: addi r1, r1, 32
; P9-NEXT: ld r0, 16(r1) ; P9-NEXT: ld r0, 16(r1)
; P9-NEXT: mtlr r0 ; P9-NEXT: mtlr r0
; P9-NEXT: blr ; P9-NEXT: blr
; ;
; NOVSX-LABEL: q_to_i128: ; NOVSX-LABEL: q_to_i128:
; NOVSX: # %bb.0: # %entry ; NOVSX: # %bb.0: # %entry
; NOVSX-NEXT: mflr r0 ; NOVSX-NEXT: mflr r0
; NOVSX-NEXT: std r0, 16(r1)
; NOVSX-NEXT: stdu r1, -32(r1) ; NOVSX-NEXT: stdu r1, -32(r1)
; NOVSX-NEXT: std r0, 48(r1)
; NOVSX-NEXT: .cfi_def_cfa_offset 32 ; NOVSX-NEXT: .cfi_def_cfa_offset 32
; NOVSX-NEXT: .cfi_offset lr, 16 ; NOVSX-NEXT: .cfi_offset lr, 16
; NOVSX-NEXT: bl __fixkfti ; NOVSX-NEXT: bl __fixkfti
; NOVSX-NEXT: nop ; NOVSX-NEXT: nop
; NOVSX-NEXT: addi r1, r1, 32 ; NOVSX-NEXT: addi r1, r1, 32
; NOVSX-NEXT: ld r0, 16(r1) ; NOVSX-NEXT: ld r0, 16(r1)
; NOVSX-NEXT: mtlr r0 ; NOVSX-NEXT: mtlr r0
; NOVSX-NEXT: blr ; NOVSX-NEXT: blr
entry: entry:
%conv = tail call i128 @llvm.experimental.constrained.fptosi.i128.f128(fp128 %m, metadata !"fpexcept.strict") #0 %conv = tail call i128 @llvm.experimental.constrained.fptosi.i128.f128(fp128 %m, metadata !"fpexcept.strict") #0
ret i128 %conv ret i128 %conv
} }
define i128 @q_to_u128(fp128 %m) #0 { define i128 @q_to_u128(fp128 %m) #0 {
; P8-LABEL: q_to_u128: ; P8-LABEL: q_to_u128:
; P8: # %bb.0: # %entry ; P8: # %bb.0: # %entry
; P8-NEXT: mflr r0 ; P8-NEXT: mflr r0
; P8-NEXT: std r0, 16(r1)
; P8-NEXT: stdu r1, -112(r1) ; P8-NEXT: stdu r1, -112(r1)
; P8-NEXT: std r0, 128(r1)
; P8-NEXT: .cfi_def_cfa_offset 112 ; P8-NEXT: .cfi_def_cfa_offset 112
; P8-NEXT: .cfi_offset lr, 16 ; P8-NEXT: .cfi_offset lr, 16
; P8-NEXT: bl __fixunskfti ; P8-NEXT: bl __fixunskfti
; P8-NEXT: nop ; P8-NEXT: nop
; P8-NEXT: addi r1, r1, 112 ; P8-NEXT: addi r1, r1, 112
; P8-NEXT: ld r0, 16(r1) ; P8-NEXT: ld r0, 16(r1)
; P8-NEXT: mtlr r0 ; P8-NEXT: mtlr r0
; P8-NEXT: blr ; P8-NEXT: blr
; ;
; P9-LABEL: q_to_u128: ; P9-LABEL: q_to_u128:
; P9: # %bb.0: # %entry ; P9: # %bb.0: # %entry
; P9-NEXT: mflr r0 ; P9-NEXT: mflr r0
; P9-NEXT: std r0, 16(r1)
; P9-NEXT: stdu r1, -32(r1) ; P9-NEXT: stdu r1, -32(r1)
; P9-NEXT: std r0, 48(r1)
; P9-NEXT: .cfi_def_cfa_offset 32 ; P9-NEXT: .cfi_def_cfa_offset 32
; P9-NEXT: .cfi_offset lr, 16 ; P9-NEXT: .cfi_offset lr, 16
; P9-NEXT: bl __fixunskfti ; P9-NEXT: bl __fixunskfti
; P9-NEXT: nop ; P9-NEXT: nop
; P9-NEXT: addi r1, r1, 32 ; P9-NEXT: addi r1, r1, 32
; P9-NEXT: ld r0, 16(r1) ; P9-NEXT: ld r0, 16(r1)
; P9-NEXT: mtlr r0 ; P9-NEXT: mtlr r0
; P9-NEXT: blr ; P9-NEXT: blr
; ;
; NOVSX-LABEL: q_to_u128: ; NOVSX-LABEL: q_to_u128:
; NOVSX: # %bb.0: # %entry ; NOVSX: # %bb.0: # %entry
; NOVSX-NEXT: mflr r0 ; NOVSX-NEXT: mflr r0
; NOVSX-NEXT: std r0, 16(r1)
; NOVSX-NEXT: stdu r1, -32(r1) ; NOVSX-NEXT: stdu r1, -32(r1)
; NOVSX-NEXT: std r0, 48(r1)
; NOVSX-NEXT: .cfi_def_cfa_offset 32 ; NOVSX-NEXT: .cfi_def_cfa_offset 32
; NOVSX-NEXT: .cfi_offset lr, 16 ; NOVSX-NEXT: .cfi_offset lr, 16
; NOVSX-NEXT: bl __fixunskfti ; NOVSX-NEXT: bl __fixunskfti
; NOVSX-NEXT: nop ; NOVSX-NEXT: nop
; NOVSX-NEXT: addi r1, r1, 32 ; NOVSX-NEXT: addi r1, r1, 32
; NOVSX-NEXT: ld r0, 16(r1) ; NOVSX-NEXT: ld r0, 16(r1)
; NOVSX-NEXT: mtlr r0 ; NOVSX-NEXT: mtlr r0
; NOVSX-NEXT: blr ; NOVSX-NEXT: blr
entry: entry:
%conv = tail call i128 @llvm.experimental.constrained.fptoui.i128.f128(fp128 %m, metadata !"fpexcept.strict") #0 %conv = tail call i128 @llvm.experimental.constrained.fptoui.i128.f128(fp128 %m, metadata !"fpexcept.strict") #0
ret i128 %conv ret i128 %conv
} }
define i1 @q_to_s1(fp128 %m) #0 { define i1 @q_to_s1(fp128 %m) #0 {
; P8-LABEL: q_to_s1: ; P8-LABEL: q_to_s1:
; P8: # %bb.0: # %entry ; P8: # %bb.0: # %entry
; P8-NEXT: mflr r0 ; P8-NEXT: mflr r0
; P8-NEXT: std r0, 16(r1)
; P8-NEXT: stdu r1, -112(r1) ; P8-NEXT: stdu r1, -112(r1)
; P8-NEXT: std r0, 128(r1)
; P8-NEXT: .cfi_def_cfa_offset 112 ; P8-NEXT: .cfi_def_cfa_offset 112
; P8-NEXT: .cfi_offset lr, 16 ; P8-NEXT: .cfi_offset lr, 16
; P8-NEXT: bl __fixkfsi ; P8-NEXT: bl __fixkfsi
; P8-NEXT: nop ; P8-NEXT: nop
; P8-NEXT: addi r1, r1, 112 ; P8-NEXT: addi r1, r1, 112
; P8-NEXT: ld r0, 16(r1) ; P8-NEXT: ld r0, 16(r1)
; P8-NEXT: mtlr r0 ; P8-NEXT: mtlr r0
; P8-NEXT: blr ; P8-NEXT: blr
; ;
; P9-LABEL: q_to_s1: ; P9-LABEL: q_to_s1:
; P9: # %bb.0: # %entry ; P9: # %bb.0: # %entry
; P9-NEXT: xscvqpswz v2, v2 ; P9-NEXT: xscvqpswz v2, v2
; P9-NEXT: mfvsrwz r3, v2 ; P9-NEXT: mfvsrwz r3, v2
; P9-NEXT: blr ; P9-NEXT: blr
; ;
; NOVSX-LABEL: q_to_s1: ; NOVSX-LABEL: q_to_s1:
; NOVSX: # %bb.0: # %entry ; NOVSX: # %bb.0: # %entry
; NOVSX-NEXT: mflr r0 ; NOVSX-NEXT: mflr r0
; NOVSX-NEXT: std r0, 16(r1)
; NOVSX-NEXT: stdu r1, -32(r1) ; NOVSX-NEXT: stdu r1, -32(r1)
; NOVSX-NEXT: std r0, 48(r1)
; NOVSX-NEXT: .cfi_def_cfa_offset 32 ; NOVSX-NEXT: .cfi_def_cfa_offset 32
; NOVSX-NEXT: .cfi_offset lr, 16 ; NOVSX-NEXT: .cfi_offset lr, 16
; NOVSX-NEXT: bl __fixkfsi ; NOVSX-NEXT: bl __fixkfsi
; NOVSX-NEXT: nop ; NOVSX-NEXT: nop
; NOVSX-NEXT: addi r1, r1, 32 ; NOVSX-NEXT: addi r1, r1, 32
; NOVSX-NEXT: ld r0, 16(r1) ; NOVSX-NEXT: ld r0, 16(r1)
; NOVSX-NEXT: mtlr r0 ; NOVSX-NEXT: mtlr r0
; NOVSX-NEXT: blr ; NOVSX-NEXT: blr
entry: entry:
%conv = tail call i1 @llvm.experimental.constrained.fptosi.i1.f128(fp128 %m, metadata !"fpexcept.strict") #0 %conv = tail call i1 @llvm.experimental.constrained.fptosi.i1.f128(fp128 %m, metadata !"fpexcept.strict") #0
ret i1 %conv ret i1 %conv
} }
define i1 @q_to_u1(fp128 %m) #0 { define i1 @q_to_u1(fp128 %m) #0 {
; P8-LABEL: q_to_u1: ; P8-LABEL: q_to_u1:
; P8: # %bb.0: # %entry ; P8: # %bb.0: # %entry
; P8-NEXT: mflr r0 ; P8-NEXT: mflr r0
; P8-NEXT: std r0, 16(r1)
; P8-NEXT: stdu r1, -112(r1) ; P8-NEXT: stdu r1, -112(r1)
; P8-NEXT: std r0, 128(r1)
; P8-NEXT: .cfi_def_cfa_offset 112 ; P8-NEXT: .cfi_def_cfa_offset 112
; P8-NEXT: .cfi_offset lr, 16 ; P8-NEXT: .cfi_offset lr, 16
; P8-NEXT: bl __fixkfsi ; P8-NEXT: bl __fixkfsi
; P8-NEXT: nop ; P8-NEXT: nop
; P8-NEXT: addi r1, r1, 112 ; P8-NEXT: addi r1, r1, 112
; P8-NEXT: ld r0, 16(r1) ; P8-NEXT: ld r0, 16(r1)
; P8-NEXT: mtlr r0 ; P8-NEXT: mtlr r0
; P8-NEXT: blr ; P8-NEXT: blr
; ;
; P9-LABEL: q_to_u1: ; P9-LABEL: q_to_u1:
; P9: # %bb.0: # %entry ; P9: # %bb.0: # %entry
; P9-NEXT: xscvqpswz v2, v2 ; P9-NEXT: xscvqpswz v2, v2
; P9-NEXT: mfvsrwz r3, v2 ; P9-NEXT: mfvsrwz r3, v2
; P9-NEXT: blr ; P9-NEXT: blr
; ;
; NOVSX-LABEL: q_to_u1: ; NOVSX-LABEL: q_to_u1:
; NOVSX: # %bb.0: # %entry ; NOVSX: # %bb.0: # %entry
; NOVSX-NEXT: mflr r0 ; NOVSX-NEXT: mflr r0
; NOVSX-NEXT: std r0, 16(r1)
; NOVSX-NEXT: stdu r1, -32(r1) ; NOVSX-NEXT: stdu r1, -32(r1)
; NOVSX-NEXT: std r0, 48(r1)
; NOVSX-NEXT: .cfi_def_cfa_offset 32 ; NOVSX-NEXT: .cfi_def_cfa_offset 32
; NOVSX-NEXT: .cfi_offset lr, 16 ; NOVSX-NEXT: .cfi_offset lr, 16
; NOVSX-NEXT: bl __fixunskfsi ; NOVSX-NEXT: bl __fixunskfsi
; NOVSX-NEXT: nop ; NOVSX-NEXT: nop
; NOVSX-NEXT: addi r1, r1, 32 ; NOVSX-NEXT: addi r1, r1, 32
; NOVSX-NEXT: ld r0, 16(r1) ; NOVSX-NEXT: ld r0, 16(r1)
; NOVSX-NEXT: mtlr r0 ; NOVSX-NEXT: mtlr r0
; NOVSX-NEXT: blr ; NOVSX-NEXT: blr
entry: entry:
%conv = tail call i1 @llvm.experimental.constrained.fptoui.i1.f128(fp128 %m, metadata !"fpexcept.strict") #0 %conv = tail call i1 @llvm.experimental.constrained.fptoui.i1.f128(fp128 %m, metadata !"fpexcept.strict") #0
ret i1 %conv ret i1 %conv
} }
define i128 @ppcq_to_i128(ppc_fp128 %m) #0 { define i128 @ppcq_to_i128(ppc_fp128 %m) #0 {
; P8-LABEL: ppcq_to_i128: ; P8-LABEL: ppcq_to_i128:
; P8: # %bb.0: # %entry ; P8: # %bb.0: # %entry
; P8-NEXT: mflr r0 ; P8-NEXT: mflr r0
; P8-NEXT: std r0, 16(r1)
; P8-NEXT: stdu r1, -112(r1) ; P8-NEXT: stdu r1, -112(r1)
; P8-NEXT: std r0, 128(r1)
; P8-NEXT: .cfi_def_cfa_offset 112 ; P8-NEXT: .cfi_def_cfa_offset 112
; P8-NEXT: .cfi_offset lr, 16 ; P8-NEXT: .cfi_offset lr, 16
; P8-NEXT: bl __fixtfti ; P8-NEXT: bl __fixtfti
; P8-NEXT: nop ; P8-NEXT: nop
; P8-NEXT: addi r1, r1, 112 ; P8-NEXT: addi r1, r1, 112
; P8-NEXT: ld r0, 16(r1) ; P8-NEXT: ld r0, 16(r1)
; P8-NEXT: mtlr r0 ; P8-NEXT: mtlr r0
; P8-NEXT: blr ; P8-NEXT: blr
; ;
; P9-LABEL: ppcq_to_i128: ; P9-LABEL: ppcq_to_i128:
; P9: # %bb.0: # %entry ; P9: # %bb.0: # %entry
; P9-NEXT: mflr r0 ; P9-NEXT: mflr r0
; P9-NEXT: std r0, 16(r1)
; P9-NEXT: stdu r1, -32(r1) ; P9-NEXT: stdu r1, -32(r1)
; P9-NEXT: std r0, 48(r1)
; P9-NEXT: .cfi_def_cfa_offset 32 ; P9-NEXT: .cfi_def_cfa_offset 32
; P9-NEXT: .cfi_offset lr, 16 ; P9-NEXT: .cfi_offset lr, 16
; P9-NEXT: bl __fixtfti ; P9-NEXT: bl __fixtfti
; P9-NEXT: nop ; P9-NEXT: nop
; P9-NEXT: addi r1, r1, 32 ; P9-NEXT: addi r1, r1, 32
; P9-NEXT: ld r0, 16(r1) ; P9-NEXT: ld r0, 16(r1)
; P9-NEXT: mtlr r0 ; P9-NEXT: mtlr r0
; P9-NEXT: blr ; P9-NEXT: blr
; ;
; NOVSX-LABEL: ppcq_to_i128: ; NOVSX-LABEL: ppcq_to_i128:
; NOVSX: # %bb.0: # %entry ; NOVSX: # %bb.0: # %entry
; NOVSX-NEXT: mflr r0 ; NOVSX-NEXT: mflr r0
; NOVSX-NEXT: std r0, 16(r1)
; NOVSX-NEXT: stdu r1, -32(r1) ; NOVSX-NEXT: stdu r1, -32(r1)
; NOVSX-NEXT: std r0, 48(r1)
; NOVSX-NEXT: .cfi_def_cfa_offset 32 ; NOVSX-NEXT: .cfi_def_cfa_offset 32
; NOVSX-NEXT: .cfi_offset lr, 16 ; NOVSX-NEXT: .cfi_offset lr, 16
; NOVSX-NEXT: bl __fixtfti ; NOVSX-NEXT: bl __fixtfti
; NOVSX-NEXT: nop ; NOVSX-NEXT: nop
; NOVSX-NEXT: addi r1, r1, 32 ; NOVSX-NEXT: addi r1, r1, 32
; NOVSX-NEXT: ld r0, 16(r1) ; NOVSX-NEXT: ld r0, 16(r1)
; NOVSX-NEXT: mtlr r0 ; NOVSX-NEXT: mtlr r0
; NOVSX-NEXT: blr ; NOVSX-NEXT: blr
entry: entry:
%conv = tail call i128 @llvm.experimental.constrained.fptosi.i128.ppcf128(ppc_fp128 %m, metadata !"fpexcept.strict") #0 %conv = tail call i128 @llvm.experimental.constrained.fptosi.i128.ppcf128(ppc_fp128 %m, metadata !"fpexcept.strict") #0
ret i128 %conv ret i128 %conv
} }
define i128 @ppcq_to_u128(ppc_fp128 %m) #0 { define i128 @ppcq_to_u128(ppc_fp128 %m) #0 {
; P8-LABEL: ppcq_to_u128: ; P8-LABEL: ppcq_to_u128:
; P8: # %bb.0: # %entry ; P8: # %bb.0: # %entry
; P8-NEXT: mflr r0 ; P8-NEXT: mflr r0
; P8-NEXT: std r0, 16(r1)
; P8-NEXT: stdu r1, -112(r1) ; P8-NEXT: stdu r1, -112(r1)
; P8-NEXT: std r0, 128(r1)
; P8-NEXT: .cfi_def_cfa_offset 112 ; P8-NEXT: .cfi_def_cfa_offset 112
; P8-NEXT: .cfi_offset lr, 16 ; P8-NEXT: .cfi_offset lr, 16
; P8-NEXT: bl __fixtfti ; P8-NEXT: bl __fixtfti
; P8-NEXT: nop ; P8-NEXT: nop
; P8-NEXT: addi r1, r1, 112 ; P8-NEXT: addi r1, r1, 112
; P8-NEXT: ld r0, 16(r1) ; P8-NEXT: ld r0, 16(r1)
; P8-NEXT: mtlr r0 ; P8-NEXT: mtlr r0
; P8-NEXT: blr ; P8-NEXT: blr
; ;
; P9-LABEL: ppcq_to_u128: ; P9-LABEL: ppcq_to_u128:
; P9: # %bb.0: # %entry ; P9: # %bb.0: # %entry
; P9-NEXT: mflr r0 ; P9-NEXT: mflr r0
; P9-NEXT: std r0, 16(r1)
; P9-NEXT: stdu r1, -32(r1) ; P9-NEXT: stdu r1, -32(r1)
; P9-NEXT: std r0, 48(r1)
; P9-NEXT: .cfi_def_cfa_offset 32 ; P9-NEXT: .cfi_def_cfa_offset 32
; P9-NEXT: .cfi_offset lr, 16 ; P9-NEXT: .cfi_offset lr, 16
; P9-NEXT: bl __fixtfti ; P9-NEXT: bl __fixtfti
; P9-NEXT: nop ; P9-NEXT: nop
; P9-NEXT: addi r1, r1, 32 ; P9-NEXT: addi r1, r1, 32
; P9-NEXT: ld r0, 16(r1) ; P9-NEXT: ld r0, 16(r1)
; P9-NEXT: mtlr r0 ; P9-NEXT: mtlr r0
; P9-NEXT: blr ; P9-NEXT: blr
; ;
; NOVSX-LABEL: ppcq_to_u128: ; NOVSX-LABEL: ppcq_to_u128:
; NOVSX: # %bb.0: # %entry ; NOVSX: # %bb.0: # %entry
; NOVSX-NEXT: mflr r0 ; NOVSX-NEXT: mflr r0
; NOVSX-NEXT: std r0, 16(r1)
; NOVSX-NEXT: stdu r1, -32(r1) ; NOVSX-NEXT: stdu r1, -32(r1)
; NOVSX-NEXT: std r0, 48(r1)
; NOVSX-NEXT: .cfi_def_cfa_offset 32 ; NOVSX-NEXT: .cfi_def_cfa_offset 32
; NOVSX-NEXT: .cfi_offset lr, 16 ; NOVSX-NEXT: .cfi_offset lr, 16
; NOVSX-NEXT: bl __fixtfti ; NOVSX-NEXT: bl __fixtfti
; NOVSX-NEXT: nop ; NOVSX-NEXT: nop
; NOVSX-NEXT: addi r1, r1, 32 ; NOVSX-NEXT: addi r1, r1, 32
; NOVSX-NEXT: ld r0, 16(r1) ; NOVSX-NEXT: ld r0, 16(r1)
; NOVSX-NEXT: mtlr r0 ; NOVSX-NEXT: mtlr r0
; NOVSX-NEXT: blr ; NOVSX-NEXT: blr
entry: entry:
%conv = tail call i128 @llvm.experimental.constrained.fptosi.i128.ppcf128(ppc_fp128 %m, metadata !"fpexcept.strict") #0 %conv = tail call i128 @llvm.experimental.constrained.fptosi.i128.ppcf128(ppc_fp128 %m, metadata !"fpexcept.strict") #0
ret i128 %conv ret i128 %conv
} }
define signext i32 @q_to_i32(fp128 %m) #0 { define signext i32 @q_to_i32(fp128 %m) #0 {
; P8-LABEL: q_to_i32: ; P8-LABEL: q_to_i32:
; P8: # %bb.0: # %entry ; P8: # %bb.0: # %entry
; P8-NEXT: mflr r0 ; P8-NEXT: mflr r0
; P8-NEXT: std r0, 16(r1)
; P8-NEXT: stdu r1, -112(r1) ; P8-NEXT: stdu r1, -112(r1)
; P8-NEXT: std r0, 128(r1)
; P8-NEXT: .cfi_def_cfa_offset 112 ; P8-NEXT: .cfi_def_cfa_offset 112
; P8-NEXT: .cfi_offset lr, 16 ; P8-NEXT: .cfi_offset lr, 16
; P8-NEXT: bl __fixkfsi ; P8-NEXT: bl __fixkfsi
; P8-NEXT: nop ; P8-NEXT: nop
; P8-NEXT: extsw r3, r3 ; P8-NEXT: extsw r3, r3
; P8-NEXT: addi r1, r1, 112 ; P8-NEXT: addi r1, r1, 112
; P8-NEXT: ld r0, 16(r1) ; P8-NEXT: ld r0, 16(r1)
; P8-NEXT: mtlr r0 ; P8-NEXT: mtlr r0
; P8-NEXT: blr ; P8-NEXT: blr
; ;
; P9-LABEL: q_to_i32: ; P9-LABEL: q_to_i32:
; P9: # %bb.0: # %entry ; P9: # %bb.0: # %entry
; P9-NEXT: xscvqpswz v2, v2 ; P9-NEXT: xscvqpswz v2, v2
; P9-NEXT: mfvsrwz r3, v2 ; P9-NEXT: mfvsrwz r3, v2
; P9-NEXT: extsw r3, r3 ; P9-NEXT: extsw r3, r3
; P9-NEXT: blr ; P9-NEXT: blr
; ;
; NOVSX-LABEL: q_to_i32: ; NOVSX-LABEL: q_to_i32:
; NOVSX: # %bb.0: # %entry ; NOVSX: # %bb.0: # %entry
; NOVSX-NEXT: mflr r0 ; NOVSX-NEXT: mflr r0
; NOVSX-NEXT: std r0, 16(r1)
; NOVSX-NEXT: stdu r1, -32(r1) ; NOVSX-NEXT: stdu r1, -32(r1)
; NOVSX-NEXT: std r0, 48(r1)
; NOVSX-NEXT: .cfi_def_cfa_offset 32 ; NOVSX-NEXT: .cfi_def_cfa_offset 32
; NOVSX-NEXT: .cfi_offset lr, 16 ; NOVSX-NEXT: .cfi_offset lr, 16
; NOVSX-NEXT: bl __fixkfsi ; NOVSX-NEXT: bl __fixkfsi
; NOVSX-NEXT: nop ; NOVSX-NEXT: nop
; NOVSX-NEXT: extsw r3, r3 ; NOVSX-NEXT: extsw r3, r3
; NOVSX-NEXT: addi r1, r1, 32 ; NOVSX-NEXT: addi r1, r1, 32
; NOVSX-NEXT: ld r0, 16(r1) ; NOVSX-NEXT: ld r0, 16(r1)
; NOVSX-NEXT: mtlr r0 ; NOVSX-NEXT: mtlr r0
; NOVSX-NEXT: blr ; NOVSX-NEXT: blr
entry: entry:
%conv = tail call i32 @llvm.experimental.constrained.fptosi.i32.f128(fp128 %m, metadata !"fpexcept.strict") #0 %conv = tail call i32 @llvm.experimental.constrained.fptosi.i32.f128(fp128 %m, metadata !"fpexcept.strict") #0
ret i32 %conv ret i32 %conv
} }
define i64 @q_to_i64(fp128 %m) #0 { define i64 @q_to_i64(fp128 %m) #0 {
; P8-LABEL: q_to_i64: ; P8-LABEL: q_to_i64:
; P8: # %bb.0: # %entry ; P8: # %bb.0: # %entry
; P8-NEXT: mflr r0 ; P8-NEXT: mflr r0
; P8-NEXT: std r0, 16(r1)
; P8-NEXT: stdu r1, -112(r1) ; P8-NEXT: stdu r1, -112(r1)
; P8-NEXT: std r0, 128(r1)
; P8-NEXT: .cfi_def_cfa_offset 112 ; P8-NEXT: .cfi_def_cfa_offset 112
; P8-NEXT: .cfi_offset lr, 16 ; P8-NEXT: .cfi_offset lr, 16
; P8-NEXT: bl __fixkfdi ; P8-NEXT: bl __fixkfdi
; P8-NEXT: nop ; P8-NEXT: nop
; P8-NEXT: addi r1, r1, 112 ; P8-NEXT: addi r1, r1, 112
; P8-NEXT: ld r0, 16(r1) ; P8-NEXT: ld r0, 16(r1)
; P8-NEXT: mtlr r0 ; P8-NEXT: mtlr r0
; P8-NEXT: blr ; P8-NEXT: blr
; ;
; P9-LABEL: q_to_i64: ; P9-LABEL: q_to_i64:
; P9: # %bb.0: # %entry ; P9: # %bb.0: # %entry
; P9-NEXT: xscvqpsdz v2, v2 ; P9-NEXT: xscvqpsdz v2, v2
; P9-NEXT: mfvsrd r3, v2 ; P9-NEXT: mfvsrd r3, v2
; P9-NEXT: blr ; P9-NEXT: blr
; ;
; NOVSX-LABEL: q_to_i64: ; NOVSX-LABEL: q_to_i64:
; NOVSX: # %bb.0: # %entry ; NOVSX: # %bb.0: # %entry
; NOVSX-NEXT: mflr r0 ; NOVSX-NEXT: mflr r0
; NOVSX-NEXT: std r0, 16(r1)
; NOVSX-NEXT: stdu r1, -32(r1) ; NOVSX-NEXT: stdu r1, -32(r1)
; NOVSX-NEXT: std r0, 48(r1)
; NOVSX-NEXT: .cfi_def_cfa_offset 32 ; NOVSX-NEXT: .cfi_def_cfa_offset 32
; NOVSX-NEXT: .cfi_offset lr, 16 ; NOVSX-NEXT: .cfi_offset lr, 16
; NOVSX-NEXT: bl __fixkfdi ; NOVSX-NEXT: bl __fixkfdi
; NOVSX-NEXT: nop ; NOVSX-NEXT: nop
; NOVSX-NEXT: addi r1, r1, 32 ; NOVSX-NEXT: addi r1, r1, 32
; NOVSX-NEXT: ld r0, 16(r1) ; NOVSX-NEXT: ld r0, 16(r1)
; NOVSX-NEXT: mtlr r0 ; NOVSX-NEXT: mtlr r0
; NOVSX-NEXT: blr ; NOVSX-NEXT: blr
entry: entry:
%conv = tail call i64 @llvm.experimental.constrained.fptosi.i64.f128(fp128 %m, metadata !"fpexcept.strict") #0 %conv = tail call i64 @llvm.experimental.constrained.fptosi.i64.f128(fp128 %m, metadata !"fpexcept.strict") #0
ret i64 %conv ret i64 %conv
} }
define i64 @q_to_u64(fp128 %m) #0 { define i64 @q_to_u64(fp128 %m) #0 {
; P8-LABEL: q_to_u64: ; P8-LABEL: q_to_u64:
; P8: # %bb.0: # %entry ; P8: # %bb.0: # %entry
; P8-NEXT: mflr r0 ; P8-NEXT: mflr r0
; P8-NEXT: std r0, 16(r1)
; P8-NEXT: stdu r1, -112(r1) ; P8-NEXT: stdu r1, -112(r1)
; P8-NEXT: std r0, 128(r1)
; P8-NEXT: .cfi_def_cfa_offset 112 ; P8-NEXT: .cfi_def_cfa_offset 112
; P8-NEXT: .cfi_offset lr, 16 ; P8-NEXT: .cfi_offset lr, 16
; P8-NEXT: bl __fixunskfdi ; P8-NEXT: bl __fixunskfdi
; P8-NEXT: nop ; P8-NEXT: nop
; P8-NEXT: addi r1, r1, 112 ; P8-NEXT: addi r1, r1, 112
; P8-NEXT: ld r0, 16(r1) ; P8-NEXT: ld r0, 16(r1)
; P8-NEXT: mtlr r0 ; P8-NEXT: mtlr r0
; P8-NEXT: blr ; P8-NEXT: blr
; ;
; P9-LABEL: q_to_u64: ; P9-LABEL: q_to_u64:
; P9: # %bb.0: # %entry ; P9: # %bb.0: # %entry
; P9-NEXT: xscvqpudz v2, v2 ; P9-NEXT: xscvqpudz v2, v2
; P9-NEXT: mfvsrd r3, v2 ; P9-NEXT: mfvsrd r3, v2
; P9-NEXT: blr ; P9-NEXT: blr
; ;
; NOVSX-LABEL: q_to_u64: ; NOVSX-LABEL: q_to_u64:
; NOVSX: # %bb.0: # %entry ; NOVSX: # %bb.0: # %entry
; NOVSX-NEXT: mflr r0 ; NOVSX-NEXT: mflr r0
; NOVSX-NEXT: std r0, 16(r1)
; NOVSX-NEXT: stdu r1, -32(r1) ; NOVSX-NEXT: stdu r1, -32(r1)
; NOVSX-NEXT: std r0, 48(r1)
; NOVSX-NEXT: .cfi_def_cfa_offset 32 ; NOVSX-NEXT: .cfi_def_cfa_offset 32
; NOVSX-NEXT: .cfi_offset lr, 16 ; NOVSX-NEXT: .cfi_offset lr, 16
; NOVSX-NEXT: bl __fixunskfdi ; NOVSX-NEXT: bl __fixunskfdi
; NOVSX-NEXT: nop ; NOVSX-NEXT: nop
; NOVSX-NEXT: addi r1, r1, 32 ; NOVSX-NEXT: addi r1, r1, 32
; NOVSX-NEXT: ld r0, 16(r1) ; NOVSX-NEXT: ld r0, 16(r1)
; NOVSX-NEXT: mtlr r0 ; NOVSX-NEXT: mtlr r0
; NOVSX-NEXT: blr ; NOVSX-NEXT: blr
entry: entry:
%conv = tail call i64 @llvm.experimental.constrained.fptoui.i64.f128(fp128 %m, metadata !"fpexcept.strict") #0 %conv = tail call i64 @llvm.experimental.constrained.fptoui.i64.f128(fp128 %m, metadata !"fpexcept.strict") #0
ret i64 %conv ret i64 %conv
} }
define zeroext i32 @q_to_u32(fp128 %m) #0 { define zeroext i32 @q_to_u32(fp128 %m) #0 {
; P8-LABEL: q_to_u32: ; P8-LABEL: q_to_u32:
; P8: # %bb.0: # %entry ; P8: # %bb.0: # %entry
; P8-NEXT: mflr r0 ; P8-NEXT: mflr r0
; P8-NEXT: std r0, 16(r1)
; P8-NEXT: stdu r1, -112(r1) ; P8-NEXT: stdu r1, -112(r1)
; P8-NEXT: std r0, 128(r1)
; P8-NEXT: .cfi_def_cfa_offset 112 ; P8-NEXT: .cfi_def_cfa_offset 112
; P8-NEXT: .cfi_offset lr, 16 ; P8-NEXT: .cfi_offset lr, 16
; P8-NEXT: bl __fixunskfsi ; P8-NEXT: bl __fixunskfsi
; P8-NEXT: nop ; P8-NEXT: nop
; P8-NEXT: addi r1, r1, 112 ; P8-NEXT: addi r1, r1, 112
; P8-NEXT: ld r0, 16(r1) ; P8-NEXT: ld r0, 16(r1)
; P8-NEXT: mtlr r0 ; P8-NEXT: mtlr r0
; P8-NEXT: blr ; P8-NEXT: blr
; ;
; P9-LABEL: q_to_u32: ; P9-LABEL: q_to_u32:
; P9: # %bb.0: # %entry ; P9: # %bb.0: # %entry
; P9-NEXT: xscvqpuwz v2, v2 ; P9-NEXT: xscvqpuwz v2, v2
; P9-NEXT: mfvsrwz r3, v2 ; P9-NEXT: mfvsrwz r3, v2
; P9-NEXT: blr ; P9-NEXT: blr
; ;
; NOVSX-LABEL: q_to_u32: ; NOVSX-LABEL: q_to_u32:
; NOVSX: # %bb.0: # %entry ; NOVSX: # %bb.0: # %entry
; NOVSX-NEXT: mflr r0 ; NOVSX-NEXT: mflr r0
; NOVSX-NEXT: std r0, 16(r1)
; NOVSX-NEXT: stdu r1, -32(r1) ; NOVSX-NEXT: stdu r1, -32(r1)
; NOVSX-NEXT: std r0, 48(r1)
; NOVSX-NEXT: .cfi_def_cfa_offset 32 ; NOVSX-NEXT: .cfi_def_cfa_offset 32
; NOVSX-NEXT: .cfi_offset lr, 16 ; NOVSX-NEXT: .cfi_offset lr, 16
; NOVSX-NEXT: bl __fixunskfsi ; NOVSX-NEXT: bl __fixunskfsi
; NOVSX-NEXT: nop ; NOVSX-NEXT: nop
; NOVSX-NEXT: addi r1, r1, 32 ; NOVSX-NEXT: addi r1, r1, 32
; NOVSX-NEXT: ld r0, 16(r1) ; NOVSX-NEXT: ld r0, 16(r1)
; NOVSX-NEXT: mtlr r0 ; NOVSX-NEXT: mtlr r0
; NOVSX-NEXT: blr ; NOVSX-NEXT: blr
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Linesentry:
%conv = tail call i32 @llvm.experimental.constrained.fptosi.i32.ppcf128(ppc_fp128 %m, metadata !"fpexcept.strict") #0 %conv = tail call i32 @llvm.experimental.constrained.fptosi.i32.ppcf128(ppc_fp128 %m, metadata !"fpexcept.strict") #0
ret i32 %conv ret i32 %conv
} }
define i64 @ppcq_to_i64(ppc_fp128 %m) #0 { define i64 @ppcq_to_i64(ppc_fp128 %m) #0 {
; P8-LABEL: ppcq_to_i64: ; P8-LABEL: ppcq_to_i64:
; P8: # %bb.0: # %entry ; P8: # %bb.0: # %entry
; P8-NEXT: mflr r0 ; P8-NEXT: mflr r0
; P8-NEXT: std r0, 16(r1)
; P8-NEXT: stdu r1, -112(r1) ; P8-NEXT: stdu r1, -112(r1)
; P8-NEXT: std r0, 128(r1)
; P8-NEXT: .cfi_def_cfa_offset 112 ; P8-NEXT: .cfi_def_cfa_offset 112
; P8-NEXT: .cfi_offset lr, 16 ; P8-NEXT: .cfi_offset lr, 16
; P8-NEXT: bl __fixtfdi ; P8-NEXT: bl __fixtfdi
; P8-NEXT: nop ; P8-NEXT: nop
; P8-NEXT: addi r1, r1, 112 ; P8-NEXT: addi r1, r1, 112
; P8-NEXT: ld r0, 16(r1) ; P8-NEXT: ld r0, 16(r1)
; P8-NEXT: mtlr r0 ; P8-NEXT: mtlr r0
; P8-NEXT: blr ; P8-NEXT: blr
; ;
; P9-LABEL: ppcq_to_i64: ; P9-LABEL: ppcq_to_i64:
; P9: # %bb.0: # %entry ; P9: # %bb.0: # %entry
; P9-NEXT: mflr r0 ; P9-NEXT: mflr r0
; P9-NEXT: std r0, 16(r1)
; P9-NEXT: stdu r1, -32(r1) ; P9-NEXT: stdu r1, -32(r1)
; P9-NEXT: std r0, 48(r1)
; P9-NEXT: .cfi_def_cfa_offset 32 ; P9-NEXT: .cfi_def_cfa_offset 32
; P9-NEXT: .cfi_offset lr, 16 ; P9-NEXT: .cfi_offset lr, 16
; P9-NEXT: bl __fixtfdi ; P9-NEXT: bl __fixtfdi
; P9-NEXT: nop ; P9-NEXT: nop
; P9-NEXT: addi r1, r1, 32 ; P9-NEXT: addi r1, r1, 32
; P9-NEXT: ld r0, 16(r1) ; P9-NEXT: ld r0, 16(r1)
; P9-NEXT: mtlr r0 ; P9-NEXT: mtlr r0
; P9-NEXT: blr ; P9-NEXT: blr
; ;
; NOVSX-LABEL: ppcq_to_i64: ; NOVSX-LABEL: ppcq_to_i64:
; NOVSX: # %bb.0: # %entry ; NOVSX: # %bb.0: # %entry
; NOVSX-NEXT: mflr r0 ; NOVSX-NEXT: mflr r0
; NOVSX-NEXT: std r0, 16(r1)
; NOVSX-NEXT: stdu r1, -32(r1) ; NOVSX-NEXT: stdu r1, -32(r1)
; NOVSX-NEXT: std r0, 48(r1)
; NOVSX-NEXT: .cfi_def_cfa_offset 32 ; NOVSX-NEXT: .cfi_def_cfa_offset 32
; NOVSX-NEXT: .cfi_offset lr, 16 ; NOVSX-NEXT: .cfi_offset lr, 16
; NOVSX-NEXT: bl __fixtfdi ; NOVSX-NEXT: bl __fixtfdi
; NOVSX-NEXT: nop ; NOVSX-NEXT: nop
; NOVSX-NEXT: addi r1, r1, 32 ; NOVSX-NEXT: addi r1, r1, 32
; NOVSX-NEXT: ld r0, 16(r1) ; NOVSX-NEXT: ld r0, 16(r1)
; NOVSX-NEXT: mtlr r0 ; NOVSX-NEXT: mtlr r0
; NOVSX-NEXT: blr ; NOVSX-NEXT: blr
entry: entry:
%conv = tail call i64 @llvm.experimental.constrained.fptosi.i64.ppcf128(ppc_fp128 %m, metadata !"fpexcept.strict") #0 %conv = tail call i64 @llvm.experimental.constrained.fptosi.i64.ppcf128(ppc_fp128 %m, metadata !"fpexcept.strict") #0
ret i64 %conv ret i64 %conv
} }
define i64 @ppcq_to_u64(ppc_fp128 %m) #0 { define i64 @ppcq_to_u64(ppc_fp128 %m) #0 {
; P8-LABEL: ppcq_to_u64: ; P8-LABEL: ppcq_to_u64:
; P8: # %bb.0: # %entry ; P8: # %bb.0: # %entry
; P8-NEXT: mflr r0 ; P8-NEXT: mflr r0
; P8-NEXT: std r0, 16(r1)
; P8-NEXT: stdu r1, -112(r1) ; P8-NEXT: stdu r1, -112(r1)
; P8-NEXT: std r0, 128(r1)
; P8-NEXT: .cfi_def_cfa_offset 112 ; P8-NEXT: .cfi_def_cfa_offset 112
; P8-NEXT: .cfi_offset lr, 16 ; P8-NEXT: .cfi_offset lr, 16
; P8-NEXT: bl __fixunstfdi ; P8-NEXT: bl __fixunstfdi
; P8-NEXT: nop ; P8-NEXT: nop
; P8-NEXT: addi r1, r1, 112 ; P8-NEXT: addi r1, r1, 112
; P8-NEXT: ld r0, 16(r1) ; P8-NEXT: ld r0, 16(r1)
; P8-NEXT: mtlr r0 ; P8-NEXT: mtlr r0
; P8-NEXT: blr ; P8-NEXT: blr
; ;
; P9-LABEL: ppcq_to_u64: ; P9-LABEL: ppcq_to_u64:
; P9: # %bb.0: # %entry ; P9: # %bb.0: # %entry
; P9-NEXT: mflr r0 ; P9-NEXT: mflr r0
; P9-NEXT: std r0, 16(r1)
; P9-NEXT: stdu r1, -32(r1) ; P9-NEXT: stdu r1, -32(r1)
; P9-NEXT: std r0, 48(r1)
; P9-NEXT: .cfi_def_cfa_offset 32 ; P9-NEXT: .cfi_def_cfa_offset 32
; P9-NEXT: .cfi_offset lr, 16 ; P9-NEXT: .cfi_offset lr, 16
; P9-NEXT: bl __fixunstfdi ; P9-NEXT: bl __fixunstfdi
; P9-NEXT: nop ; P9-NEXT: nop
; P9-NEXT: addi r1, r1, 32 ; P9-NEXT: addi r1, r1, 32
; P9-NEXT: ld r0, 16(r1) ; P9-NEXT: ld r0, 16(r1)
; P9-NEXT: mtlr r0 ; P9-NEXT: mtlr r0
; P9-NEXT: blr ; P9-NEXT: blr
; ;
; NOVSX-LABEL: ppcq_to_u64: ; NOVSX-LABEL: ppcq_to_u64:
; NOVSX: # %bb.0: # %entry ; NOVSX: # %bb.0: # %entry
; NOVSX-NEXT: mflr r0 ; NOVSX-NEXT: mflr r0
; NOVSX-NEXT: std r0, 16(r1)
; NOVSX-NEXT: stdu r1, -32(r1) ; NOVSX-NEXT: stdu r1, -32(r1)
; NOVSX-NEXT: std r0, 48(r1)
; NOVSX-NEXT: .cfi_def_cfa_offset 32 ; NOVSX-NEXT: .cfi_def_cfa_offset 32
; NOVSX-NEXT: .cfi_offset lr, 16 ; NOVSX-NEXT: .cfi_offset lr, 16
; NOVSX-NEXT: bl __fixunstfdi ; NOVSX-NEXT: bl __fixunstfdi
; NOVSX-NEXT: nop ; NOVSX-NEXT: nop
; NOVSX-NEXT: addi r1, r1, 32 ; NOVSX-NEXT: addi r1, r1, 32
; NOVSX-NEXT: ld r0, 16(r1) ; NOVSX-NEXT: ld r0, 16(r1)
; NOVSX-NEXT: mtlr r0 ; NOVSX-NEXT: mtlr r0
; NOVSX-NEXT: blr ; NOVSX-NEXT: blr
entry: entry:
%conv = tail call i64 @llvm.experimental.constrained.fptoui.i64.ppcf128(ppc_fp128 %m, metadata !"fpexcept.strict") #0 %conv = tail call i64 @llvm.experimental.constrained.fptoui.i64.ppcf128(ppc_fp128 %m, metadata !"fpexcept.strict") #0
ret i64 %conv ret i64 %conv
} }
define zeroext i32 @ppcq_to_u32(ppc_fp128 %m) #0 { define zeroext i32 @ppcq_to_u32(ppc_fp128 %m) #0 {
; P8-LABEL: ppcq_to_u32: ; P8-LABEL: ppcq_to_u32:
; P8: # %bb.0: # %entry ; P8: # %bb.0: # %entry
; P8-NEXT: mflr r0 ; P8-NEXT: mflr r0
; P8-NEXT: std r0, 16(r1)
; P8-NEXT: stdu r1, -128(r1) ; P8-NEXT: stdu r1, -128(r1)
; P8-NEXT: std r0, 144(r1)
; P8-NEXT: .cfi_def_cfa_offset 128 ; P8-NEXT: .cfi_def_cfa_offset 128
; P8-NEXT: .cfi_offset lr, 16 ; P8-NEXT: .cfi_offset lr, 16
; P8-NEXT: .cfi_offset r30, -16 ; P8-NEXT: .cfi_offset r30, -16
; P8-NEXT: addis r3, r2, .LCPI13_0@toc@ha ; P8-NEXT: addis r3, r2, .LCPI13_0@toc@ha
; P8-NEXT: xxlxor f3, f3, f3 ; P8-NEXT: xxlxor f3, f3, f3
; P8-NEXT: std r30, 112(r1) # 8-byte Folded Spill ; P8-NEXT: std r30, 112(r1) # 8-byte Folded Spill
; P8-NEXT: lfs f0, .LCPI13_0@toc@l(r3) ; P8-NEXT: lfs f0, .LCPI13_0@toc@l(r3)
; P8-NEXT: lis r3, -32768 ; P8-NEXT: lis r3, -32768
Show All 28 Lines
; ;
; P9-LABEL: ppcq_to_u32: ; P9-LABEL: ppcq_to_u32:
; P9: # %bb.0: # %entry ; P9: # %bb.0: # %entry
; P9-NEXT: mflr r0 ; P9-NEXT: mflr r0
; P9-NEXT: .cfi_def_cfa_offset 48 ; P9-NEXT: .cfi_def_cfa_offset 48
; P9-NEXT: .cfi_offset lr, 16 ; P9-NEXT: .cfi_offset lr, 16
; P9-NEXT: .cfi_offset r30, -16 ; P9-NEXT: .cfi_offset r30, -16
; P9-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; P9-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; P9-NEXT: std r0, 16(r1)
; P9-NEXT: stdu r1, -48(r1) ; P9-NEXT: stdu r1, -48(r1)
; P9-NEXT: addis r3, r2, .LCPI13_0@toc@ha ; P9-NEXT: addis r3, r2, .LCPI13_0@toc@ha
; P9-NEXT: xxlxor f3, f3, f3 ; P9-NEXT: xxlxor f3, f3, f3
; P9-NEXT: std r0, 64(r1)
; P9-NEXT: lfs f0, .LCPI13_0@toc@l(r3) ; P9-NEXT: lfs f0, .LCPI13_0@toc@l(r3)
; P9-NEXT: fcmpo cr1, f2, f3 ; P9-NEXT: fcmpo cr1, f2, f3
; P9-NEXT: lis r3, -32768 ; P9-NEXT: lis r3, -32768
; P9-NEXT: fcmpo cr0, f1, f0
; P9-NEXT: xxlxor f3, f3, f3 ; P9-NEXT: xxlxor f3, f3, f3
; P9-NEXT: fcmpo cr0, f1, f0
; P9-NEXT: crand 4*cr5+lt, eq, 4*cr1+lt ; P9-NEXT: crand 4*cr5+lt, eq, 4*cr1+lt
; P9-NEXT: crandc 4*cr5+gt, lt, eq ; P9-NEXT: crandc 4*cr5+gt, lt, eq
; P9-NEXT: cror 4*cr5+lt, 4*cr5+gt, 4*cr5+lt ; P9-NEXT: cror 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
; P9-NEXT: isel r30, 0, r3, 4*cr5+lt ; P9-NEXT: isel r30, 0, r3, 4*cr5+lt
; P9-NEXT: bc 12, 4*cr5+lt, .LBB13_2 ; P9-NEXT: bc 12, 4*cr5+lt, .LBB13_2
; P9-NEXT: # %bb.1: # %entry ; P9-NEXT: # %bb.1: # %entry
; P9-NEXT: fmr f3, f0 ; P9-NEXT: fmr f3, f0
; P9-NEXT: .LBB13_2: # %entry ; P9-NEXT: .LBB13_2: # %entry
Show All 14 Lines
; P9-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; P9-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; P9-NEXT: mtlr r0 ; P9-NEXT: mtlr r0
; P9-NEXT: blr ; P9-NEXT: blr
; ;
; NOVSX-LABEL: ppcq_to_u32: ; NOVSX-LABEL: ppcq_to_u32:
; NOVSX: # %bb.0: # %entry ; NOVSX: # %bb.0: # %entry
; NOVSX-NEXT: mfocrf r12, 32 ; NOVSX-NEXT: mfocrf r12, 32
; NOVSX-NEXT: mflr r0 ; NOVSX-NEXT: mflr r0
; NOVSX-NEXT: std r0, 16(r1)
; NOVSX-NEXT: stw r12, 8(r1) ; NOVSX-NEXT: stw r12, 8(r1)
; NOVSX-NEXT: stdu r1, -48(r1) ; NOVSX-NEXT: stdu r1, -48(r1)
; NOVSX-NEXT: std r0, 64(r1)
; NOVSX-NEXT: .cfi_def_cfa_offset 48 ; NOVSX-NEXT: .cfi_def_cfa_offset 48
; NOVSX-NEXT: .cfi_offset lr, 16 ; NOVSX-NEXT: .cfi_offset lr, 16
; NOVSX-NEXT: .cfi_offset cr2, 8 ; NOVSX-NEXT: .cfi_offset cr2, 8
; NOVSX-NEXT: addis r3, r2, .LCPI13_0@toc@ha ; NOVSX-NEXT: addis r3, r2, .LCPI13_0@toc@ha
; NOVSX-NEXT: addis r4, r2, .LCPI13_1@toc@ha ; NOVSX-NEXT: addis r4, r2, .LCPI13_1@toc@ha
; NOVSX-NEXT: lfs f0, .LCPI13_0@toc@l(r3) ; NOVSX-NEXT: lfs f0, .LCPI13_0@toc@l(r3)
; NOVSX-NEXT: lfs f4, .LCPI13_1@toc@l(r4) ; NOVSX-NEXT: lfs f4, .LCPI13_1@toc@l(r4)
; NOVSX-NEXT: fcmpo cr0, f1, f0 ; NOVSX-NEXT: fcmpo cr0, f1, f0
Show All 31 Linesentry:
%conv = tail call i32 @llvm.experimental.constrained.fptoui.i32.ppcf128(ppc_fp128 %m, metadata !"fpexcept.strict") #0 %conv = tail call i32 @llvm.experimental.constrained.fptoui.i32.ppcf128(ppc_fp128 %m, metadata !"fpexcept.strict") #0
ret i32 %conv ret i32 %conv
} }
define fp128 @i1_to_q(i1 signext %m) #0 { define fp128 @i1_to_q(i1 signext %m) #0 {
; P8-LABEL: i1_to_q: ; P8-LABEL: i1_to_q:
; P8: # %bb.0: # %entry ; P8: # %bb.0: # %entry
; P8-NEXT: mflr r0 ; P8-NEXT: mflr r0
; P8-NEXT: std r0, 16(r1)
; P8-NEXT: stdu r1, -112(r1) ; P8-NEXT: stdu r1, -112(r1)
; P8-NEXT: std r0, 128(r1)
; P8-NEXT: .cfi_def_cfa_offset 112 ; P8-NEXT: .cfi_def_cfa_offset 112
; P8-NEXT: .cfi_offset lr, 16 ; P8-NEXT: .cfi_offset lr, 16
; P8-NEXT: bl __floatsikf ; P8-NEXT: bl __floatsikf
; P8-NEXT: nop ; P8-NEXT: nop
; P8-NEXT: addi r1, r1, 112 ; P8-NEXT: addi r1, r1, 112
; P8-NEXT: ld r0, 16(r1) ; P8-NEXT: ld r0, 16(r1)
; P8-NEXT: mtlr r0 ; P8-NEXT: mtlr r0
; P8-NEXT: blr ; P8-NEXT: blr
; ;
; P9-LABEL: i1_to_q: ; P9-LABEL: i1_to_q:
; P9: # %bb.0: # %entry ; P9: # %bb.0: # %entry
; P9-NEXT: mtvsrwa v2, r3 ; P9-NEXT: mtvsrwa v2, r3
; P9-NEXT: xscvsdqp v2, v2 ; P9-NEXT: xscvsdqp v2, v2
; P9-NEXT: blr ; P9-NEXT: blr
; ;
; NOVSX-LABEL: i1_to_q: ; NOVSX-LABEL: i1_to_q:
; NOVSX: # %bb.0: # %entry ; NOVSX: # %bb.0: # %entry
; NOVSX-NEXT: mflr r0 ; NOVSX-NEXT: mflr r0
; NOVSX-NEXT: std r0, 16(r1)
; NOVSX-NEXT: stdu r1, -32(r1) ; NOVSX-NEXT: stdu r1, -32(r1)
; NOVSX-NEXT: std r0, 48(r1)
; NOVSX-NEXT: .cfi_def_cfa_offset 32 ; NOVSX-NEXT: .cfi_def_cfa_offset 32
; NOVSX-NEXT: .cfi_offset lr, 16 ; NOVSX-NEXT: .cfi_offset lr, 16
; NOVSX-NEXT: bl __floatsikf ; NOVSX-NEXT: bl __floatsikf
; NOVSX-NEXT: nop ; NOVSX-NEXT: nop
; NOVSX-NEXT: addi r1, r1, 32 ; NOVSX-NEXT: addi r1, r1, 32
; NOVSX-NEXT: ld r0, 16(r1) ; NOVSX-NEXT: ld r0, 16(r1)
; NOVSX-NEXT: mtlr r0 ; NOVSX-NEXT: mtlr r0
; NOVSX-NEXT: blr ; NOVSX-NEXT: blr
entry: entry:
%conv = tail call fp128 @llvm.experimental.constrained.sitofp.f128.i1(i1 %m, metadata !"round.dynamic", metadata !"fpexcept.strict") #0 %conv = tail call fp128 @llvm.experimental.constrained.sitofp.f128.i1(i1 %m, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
ret fp128 %conv ret fp128 %conv
} }
define fp128 @u1_to_q(i1 zeroext %m) #0 { define fp128 @u1_to_q(i1 zeroext %m) #0 {
; P8-LABEL: u1_to_q: ; P8-LABEL: u1_to_q:
; P8: # %bb.0: # %entry ; P8: # %bb.0: # %entry
; P8-NEXT: mflr r0 ; P8-NEXT: mflr r0
; P8-NEXT: std r0, 16(r1)
; P8-NEXT: stdu r1, -112(r1) ; P8-NEXT: stdu r1, -112(r1)
; P8-NEXT: std r0, 128(r1)
; P8-NEXT: .cfi_def_cfa_offset 112 ; P8-NEXT: .cfi_def_cfa_offset 112
; P8-NEXT: .cfi_offset lr, 16 ; P8-NEXT: .cfi_offset lr, 16
; P8-NEXT: bl __floatsikf ; P8-NEXT: bl __floatsikf
; P8-NEXT: nop ; P8-NEXT: nop
; P8-NEXT: addi r1, r1, 112 ; P8-NEXT: addi r1, r1, 112
; P8-NEXT: ld r0, 16(r1) ; P8-NEXT: ld r0, 16(r1)
; P8-NEXT: mtlr r0 ; P8-NEXT: mtlr r0
; P8-NEXT: blr ; P8-NEXT: blr
; ;
; P9-LABEL: u1_to_q: ; P9-LABEL: u1_to_q:
; P9: # %bb.0: # %entry ; P9: # %bb.0: # %entry
; P9-NEXT: mtvsrwa v2, r3 ; P9-NEXT: mtvsrwa v2, r3
; P9-NEXT: xscvsdqp v2, v2 ; P9-NEXT: xscvsdqp v2, v2
; P9-NEXT: blr ; P9-NEXT: blr
; ;
; NOVSX-LABEL: u1_to_q: ; NOVSX-LABEL: u1_to_q:
; NOVSX: # %bb.0: # %entry ; NOVSX: # %bb.0: # %entry
; NOVSX-NEXT: mflr r0 ; NOVSX-NEXT: mflr r0
; NOVSX-NEXT: std r0, 16(r1)
; NOVSX-NEXT: stdu r1, -32(r1) ; NOVSX-NEXT: stdu r1, -32(r1)
; NOVSX-NEXT: std r0, 48(r1)
; NOVSX-NEXT: .cfi_def_cfa_offset 32 ; NOVSX-NEXT: .cfi_def_cfa_offset 32
; NOVSX-NEXT: .cfi_offset lr, 16 ; NOVSX-NEXT: .cfi_offset lr, 16
; NOVSX-NEXT: bl __floatunsikf ; NOVSX-NEXT: bl __floatunsikf
; NOVSX-NEXT: nop ; NOVSX-NEXT: nop
; NOVSX-NEXT: addi r1, r1, 32 ; NOVSX-NEXT: addi r1, r1, 32
; NOVSX-NEXT: ld r0, 16(r1) ; NOVSX-NEXT: ld r0, 16(r1)
; NOVSX-NEXT: mtlr r0 ; NOVSX-NEXT: mtlr r0
; NOVSX-NEXT: blr ; NOVSX-NEXT: blr
▲ Show 20 Lines • Show All 59 Lines • ▼ Show 20 Linesentry:
%conv = tail call ppc_fp128 @llvm.experimental.constrained.uitofp.ppcf128.i1(i1 %m, metadata !"round.dynamic", metadata !"fpexcept.strict") #0 %conv = tail call ppc_fp128 @llvm.experimental.constrained.uitofp.ppcf128.i1(i1 %m, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
ret ppc_fp128 %conv ret ppc_fp128 %conv
} }
define fp128 @i32_to_q(i32 signext %m) #0 { define fp128 @i32_to_q(i32 signext %m) #0 {
; P8-LABEL: i32_to_q: ; P8-LABEL: i32_to_q:
; P8: # %bb.0: # %entry ; P8: # %bb.0: # %entry
; P8-NEXT: mflr r0 ; P8-NEXT: mflr r0
; P8-NEXT: std r0, 16(r1)
; P8-NEXT: stdu r1, -112(r1) ; P8-NEXT: stdu r1, -112(r1)
; P8-NEXT: std r0, 128(r1)
; P8-NEXT: .cfi_def_cfa_offset 112 ; P8-NEXT: .cfi_def_cfa_offset 112
; P8-NEXT: .cfi_offset lr, 16 ; P8-NEXT: .cfi_offset lr, 16
; P8-NEXT: bl __floatsikf ; P8-NEXT: bl __floatsikf
; P8-NEXT: nop ; P8-NEXT: nop
; P8-NEXT: addi r1, r1, 112 ; P8-NEXT: addi r1, r1, 112
; P8-NEXT: ld r0, 16(r1) ; P8-NEXT: ld r0, 16(r1)
; P8-NEXT: mtlr r0 ; P8-NEXT: mtlr r0
; P8-NEXT: blr ; P8-NEXT: blr
; ;
; P9-LABEL: i32_to_q: ; P9-LABEL: i32_to_q:
; P9: # %bb.0: # %entry ; P9: # %bb.0: # %entry
; P9-NEXT: mtvsrwa v2, r3 ; P9-NEXT: mtvsrwa v2, r3
; P9-NEXT: xscvsdqp v2, v2 ; P9-NEXT: xscvsdqp v2, v2
; P9-NEXT: blr ; P9-NEXT: blr
; ;
; NOVSX-LABEL: i32_to_q: ; NOVSX-LABEL: i32_to_q:
; NOVSX: # %bb.0: # %entry ; NOVSX: # %bb.0: # %entry
; NOVSX-NEXT: mflr r0 ; NOVSX-NEXT: mflr r0
; NOVSX-NEXT: std r0, 16(r1)
; NOVSX-NEXT: stdu r1, -32(r1) ; NOVSX-NEXT: stdu r1, -32(r1)
; NOVSX-NEXT: std r0, 48(r1)
; NOVSX-NEXT: .cfi_def_cfa_offset 32 ; NOVSX-NEXT: .cfi_def_cfa_offset 32
; NOVSX-NEXT: .cfi_offset lr, 16 ; NOVSX-NEXT: .cfi_offset lr, 16
; NOVSX-NEXT: bl __floatsikf ; NOVSX-NEXT: bl __floatsikf
; NOVSX-NEXT: nop ; NOVSX-NEXT: nop
; NOVSX-NEXT: addi r1, r1, 32 ; NOVSX-NEXT: addi r1, r1, 32
; NOVSX-NEXT: ld r0, 16(r1) ; NOVSX-NEXT: ld r0, 16(r1)
; NOVSX-NEXT: mtlr r0 ; NOVSX-NEXT: mtlr r0
; NOVSX-NEXT: blr ; NOVSX-NEXT: blr
entry: entry:
%conv = tail call fp128 @llvm.experimental.constrained.sitofp.f128.i32(i32 %m, metadata !"round.dynamic", metadata !"fpexcept.strict") #0 %conv = tail call fp128 @llvm.experimental.constrained.sitofp.f128.i32(i32 %m, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
ret fp128 %conv ret fp128 %conv
} }
define fp128 @i64_to_q(i64 %m) #0 { define fp128 @i64_to_q(i64 %m) #0 {
; P8-LABEL: i64_to_q: ; P8-LABEL: i64_to_q:
; P8: # %bb.0: # %entry ; P8: # %bb.0: # %entry
; P8-NEXT: mflr r0 ; P8-NEXT: mflr r0
; P8-NEXT: std r0, 16(r1)
; P8-NEXT: stdu r1, -112(r1) ; P8-NEXT: stdu r1, -112(r1)
; P8-NEXT: std r0, 128(r1)
; P8-NEXT: .cfi_def_cfa_offset 112 ; P8-NEXT: .cfi_def_cfa_offset 112
; P8-NEXT: .cfi_offset lr, 16 ; P8-NEXT: .cfi_offset lr, 16
; P8-NEXT: bl __floatdikf ; P8-NEXT: bl __floatdikf
; P8-NEXT: nop ; P8-NEXT: nop
; P8-NEXT: addi r1, r1, 112 ; P8-NEXT: addi r1, r1, 112
; P8-NEXT: ld r0, 16(r1) ; P8-NEXT: ld r0, 16(r1)
; P8-NEXT: mtlr r0 ; P8-NEXT: mtlr r0
; P8-NEXT: blr ; P8-NEXT: blr
; ;
; P9-LABEL: i64_to_q: ; P9-LABEL: i64_to_q:
; P9: # %bb.0: # %entry ; P9: # %bb.0: # %entry
; P9-NEXT: mtvsrd v2, r3 ; P9-NEXT: mtvsrd v2, r3
; P9-NEXT: xscvsdqp v2, v2 ; P9-NEXT: xscvsdqp v2, v2
; P9-NEXT: blr ; P9-NEXT: blr
; ;
; NOVSX-LABEL: i64_to_q: ; NOVSX-LABEL: i64_to_q:
; NOVSX: # %bb.0: # %entry ; NOVSX: # %bb.0: # %entry
; NOVSX-NEXT: mflr r0 ; NOVSX-NEXT: mflr r0
; NOVSX-NEXT: std r0, 16(r1)
; NOVSX-NEXT: stdu r1, -32(r1) ; NOVSX-NEXT: stdu r1, -32(r1)
; NOVSX-NEXT: std r0, 48(r1)
; NOVSX-NEXT: .cfi_def_cfa_offset 32 ; NOVSX-NEXT: .cfi_def_cfa_offset 32
; NOVSX-NEXT: .cfi_offset lr, 16 ; NOVSX-NEXT: .cfi_offset lr, 16
; NOVSX-NEXT: bl __floatdikf ; NOVSX-NEXT: bl __floatdikf
; NOVSX-NEXT: nop ; NOVSX-NEXT: nop
; NOVSX-NEXT: addi r1, r1, 32 ; NOVSX-NEXT: addi r1, r1, 32
; NOVSX-NEXT: ld r0, 16(r1) ; NOVSX-NEXT: ld r0, 16(r1)
; NOVSX-NEXT: mtlr r0 ; NOVSX-NEXT: mtlr r0
; NOVSX-NEXT: blr ; NOVSX-NEXT: blr
entry: entry:
%conv = tail call fp128 @llvm.experimental.constrained.sitofp.f128.i64(i64 %m, metadata !"round.dynamic", metadata !"fpexcept.strict") #0 %conv = tail call fp128 @llvm.experimental.constrained.sitofp.f128.i64(i64 %m, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
ret fp128 %conv ret fp128 %conv
} }
define fp128 @u32_to_q(i32 zeroext %m) #0 { define fp128 @u32_to_q(i32 zeroext %m) #0 {
; P8-LABEL: u32_to_q: ; P8-LABEL: u32_to_q:
; P8: # %bb.0: # %entry ; P8: # %bb.0: # %entry
; P8-NEXT: mflr r0 ; P8-NEXT: mflr r0
; P8-NEXT: std r0, 16(r1)
; P8-NEXT: stdu r1, -112(r1) ; P8-NEXT: stdu r1, -112(r1)
; P8-NEXT: std r0, 128(r1)
; P8-NEXT: .cfi_def_cfa_offset 112 ; P8-NEXT: .cfi_def_cfa_offset 112
; P8-NEXT: .cfi_offset lr, 16 ; P8-NEXT: .cfi_offset lr, 16
; P8-NEXT: bl __floatunsikf ; P8-NEXT: bl __floatunsikf
; P8-NEXT: nop ; P8-NEXT: nop
; P8-NEXT: addi r1, r1, 112 ; P8-NEXT: addi r1, r1, 112
; P8-NEXT: ld r0, 16(r1) ; P8-NEXT: ld r0, 16(r1)
; P8-NEXT: mtlr r0 ; P8-NEXT: mtlr r0
; P8-NEXT: blr ; P8-NEXT: blr
; ;
; P9-LABEL: u32_to_q: ; P9-LABEL: u32_to_q:
; P9: # %bb.0: # %entry ; P9: # %bb.0: # %entry
; P9-NEXT: mtvsrwz v2, r3 ; P9-NEXT: mtvsrwz v2, r3
; P9-NEXT: xscvudqp v2, v2 ; P9-NEXT: xscvudqp v2, v2
; P9-NEXT: blr ; P9-NEXT: blr
; ;
; NOVSX-LABEL: u32_to_q: ; NOVSX-LABEL: u32_to_q:
; NOVSX: # %bb.0: # %entry ; NOVSX: # %bb.0: # %entry
; NOVSX-NEXT: mflr r0 ; NOVSX-NEXT: mflr r0
; NOVSX-NEXT: std r0, 16(r1)
; NOVSX-NEXT: stdu r1, -32(r1) ; NOVSX-NEXT: stdu r1, -32(r1)
; NOVSX-NEXT: std r0, 48(r1)
; NOVSX-NEXT: .cfi_def_cfa_offset 32 ; NOVSX-NEXT: .cfi_def_cfa_offset 32
; NOVSX-NEXT: .cfi_offset lr, 16 ; NOVSX-NEXT: .cfi_offset lr, 16
; NOVSX-NEXT: bl __floatunsikf ; NOVSX-NEXT: bl __floatunsikf
; NOVSX-NEXT: nop ; NOVSX-NEXT: nop
; NOVSX-NEXT: addi r1, r1, 32 ; NOVSX-NEXT: addi r1, r1, 32
; NOVSX-NEXT: ld r0, 16(r1) ; NOVSX-NEXT: ld r0, 16(r1)
; NOVSX-NEXT: mtlr r0 ; NOVSX-NEXT: mtlr r0
; NOVSX-NEXT: blr ; NOVSX-NEXT: blr
entry: entry:
%conv = tail call fp128 @llvm.experimental.constrained.uitofp.f128.i32(i32 %m, metadata !"round.dynamic", metadata !"fpexcept.strict") #0 %conv = tail call fp128 @llvm.experimental.constrained.uitofp.f128.i32(i32 %m, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
ret fp128 %conv ret fp128 %conv
} }
define fp128 @u64_to_q(i64 %m) #0 { define fp128 @u64_to_q(i64 %m) #0 {
; P8-LABEL: u64_to_q: ; P8-LABEL: u64_to_q:
; P8: # %bb.0: # %entry ; P8: # %bb.0: # %entry
; P8-NEXT: mflr r0 ; P8-NEXT: mflr r0
; P8-NEXT: std r0, 16(r1)
; P8-NEXT: stdu r1, -112(r1) ; P8-NEXT: stdu r1, -112(r1)
; P8-NEXT: std r0, 128(r1)
; P8-NEXT: .cfi_def_cfa_offset 112 ; P8-NEXT: .cfi_def_cfa_offset 112
; P8-NEXT: .cfi_offset lr, 16 ; P8-NEXT: .cfi_offset lr, 16
; P8-NEXT: bl __floatundikf ; P8-NEXT: bl __floatundikf
; P8-NEXT: nop ; P8-NEXT: nop
; P8-NEXT: addi r1, r1, 112 ; P8-NEXT: addi r1, r1, 112
; P8-NEXT: ld r0, 16(r1) ; P8-NEXT: ld r0, 16(r1)
; P8-NEXT: mtlr r0 ; P8-NEXT: mtlr r0
; P8-NEXT: blr ; P8-NEXT: blr
; ;
; P9-LABEL: u64_to_q: ; P9-LABEL: u64_to_q:
; P9: # %bb.0: # %entry ; P9: # %bb.0: # %entry
; P9-NEXT: mtvsrd v2, r3 ; P9-NEXT: mtvsrd v2, r3
; P9-NEXT: xscvudqp v2, v2 ; P9-NEXT: xscvudqp v2, v2
; P9-NEXT: blr ; P9-NEXT: blr
; ;
; NOVSX-LABEL: u64_to_q: ; NOVSX-LABEL: u64_to_q:
; NOVSX: # %bb.0: # %entry ; NOVSX: # %bb.0: # %entry
; NOVSX-NEXT: mflr r0 ; NOVSX-NEXT: mflr r0
; NOVSX-NEXT: std r0, 16(r1)
; NOVSX-NEXT: stdu r1, -32(r1) ; NOVSX-NEXT: stdu r1, -32(r1)
; NOVSX-NEXT: std r0, 48(r1)
; NOVSX-NEXT: .cfi_def_cfa_offset 32 ; NOVSX-NEXT: .cfi_def_cfa_offset 32
; NOVSX-NEXT: .cfi_offset lr, 16 ; NOVSX-NEXT: .cfi_offset lr, 16
; NOVSX-NEXT: bl __floatundikf ; NOVSX-NEXT: bl __floatundikf
; NOVSX-NEXT: nop ; NOVSX-NEXT: nop
; NOVSX-NEXT: addi r1, r1, 32 ; NOVSX-NEXT: addi r1, r1, 32
; NOVSX-NEXT: ld r0, 16(r1) ; NOVSX-NEXT: ld r0, 16(r1)
; NOVSX-NEXT: mtlr r0 ; NOVSX-NEXT: mtlr r0
; NOVSX-NEXT: blr ; NOVSX-NEXT: blr
entry: entry:
%conv = tail call fp128 @llvm.experimental.constrained.uitofp.f128.i64(i64 %m, metadata !"round.dynamic", metadata !"fpexcept.strict") #0 %conv = tail call fp128 @llvm.experimental.constrained.uitofp.f128.i64(i64 %m, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
ret fp128 %conv ret fp128 %conv
} }
attributes #0 = { strictfp } attributes #0 = { strictfp }

llvm/test/CodeGen/PowerPC/fp-strict-conv-spe.ll

Show All 32 Linesentry:
%conv = call i32 @llvm.experimental.constrained.fptosi.i32.f64(double %m, metadata !"fpexcept.strict") #0 %conv = call i32 @llvm.experimental.constrained.fptosi.i32.f64(double %m, metadata !"fpexcept.strict") #0
ret i32 %conv ret i32 %conv
} }
define i64 @d_to_i64(double %m) #0 { define i64 @d_to_i64(double %m) #0 {
; SPE-LABEL: d_to_i64: ; SPE-LABEL: d_to_i64:
; SPE: # %bb.0: # %entry ; SPE: # %bb.0: # %entry
; SPE-NEXT: mflr r0 ; SPE-NEXT: mflr r0
; SPE-NEXT: stw r0, 4(r1)
; SPE-NEXT: stwu r1, -16(r1) ; SPE-NEXT: stwu r1, -16(r1)
; SPE-NEXT: stw r0, 20(r1)
; SPE-NEXT: .cfi_def_cfa_offset 16 ; SPE-NEXT: .cfi_def_cfa_offset 16
; SPE-NEXT: .cfi_offset lr, 4 ; SPE-NEXT: .cfi_offset lr, 4
; SPE-NEXT: evmergelo r4, r3, r4 ; SPE-NEXT: evmergelo r4, r3, r4
; SPE-NEXT: evmergehi r3, r4, r4 ; SPE-NEXT: evmergehi r3, r4, r4
; SPE-NEXT: # kill: def $r4 killed $r4 killed $s4 ; SPE-NEXT: # kill: def $r4 killed $r4 killed $s4
; SPE-NEXT: # kill: def $r3 killed $r3 killed $s3 ; SPE-NEXT: # kill: def $r3 killed $r3 killed $s3
; SPE-NEXT: bl __fixdfdi ; SPE-NEXT: bl __fixdfdi
; SPE-NEXT: lwz r0, 20(r1) ; SPE-NEXT: lwz r0, 20(r1)
; SPE-NEXT: addi r1, r1, 16 ; SPE-NEXT: addi r1, r1, 16
; SPE-NEXT: mtlr r0 ; SPE-NEXT: mtlr r0
; SPE-NEXT: blr ; SPE-NEXT: blr
entry: entry:
%conv = call i64 @llvm.experimental.constrained.fptosi.i64.f64(double %m, metadata !"fpexcept.strict") #0 %conv = call i64 @llvm.experimental.constrained.fptosi.i64.f64(double %m, metadata !"fpexcept.strict") #0
ret i64 %conv ret i64 %conv
} }
define i64 @d_to_u64(double %m) #0 { define i64 @d_to_u64(double %m) #0 {
; SPE-LABEL: d_to_u64: ; SPE-LABEL: d_to_u64:
; SPE: # %bb.0: # %entry ; SPE: # %bb.0: # %entry
; SPE-NEXT: mflr r0 ; SPE-NEXT: mflr r0
; SPE-NEXT: stw r0, 4(r1)
; SPE-NEXT: stwu r1, -16(r1) ; SPE-NEXT: stwu r1, -16(r1)
; SPE-NEXT: stw r0, 20(r1)
; SPE-NEXT: .cfi_def_cfa_offset 16 ; SPE-NEXT: .cfi_def_cfa_offset 16
; SPE-NEXT: .cfi_offset lr, 4 ; SPE-NEXT: .cfi_offset lr, 4
; SPE-NEXT: evmergelo r4, r3, r4 ; SPE-NEXT: evmergelo r4, r3, r4
; SPE-NEXT: evmergehi r3, r4, r4 ; SPE-NEXT: evmergehi r3, r4, r4
; SPE-NEXT: # kill: def $r4 killed $r4 killed $s4 ; SPE-NEXT: # kill: def $r4 killed $r4 killed $s4
; SPE-NEXT: # kill: def $r3 killed $r3 killed $s3 ; SPE-NEXT: # kill: def $r3 killed $r3 killed $s3
; SPE-NEXT: bl __fixunsdfdi ; SPE-NEXT: bl __fixunsdfdi
; SPE-NEXT: lwz r0, 20(r1) ; SPE-NEXT: lwz r0, 20(r1)
Show All 25 Linesentry:
%conv = call i32 @llvm.experimental.constrained.fptosi.i32.f32(float %m, metadata !"fpexcept.strict") #0 %conv = call i32 @llvm.experimental.constrained.fptosi.i32.f32(float %m, metadata !"fpexcept.strict") #0
ret i32 %conv ret i32 %conv
} }
define i64 @f_to_i64(float %m) #0 { define i64 @f_to_i64(float %m) #0 {
; SPE-LABEL: f_to_i64: ; SPE-LABEL: f_to_i64:
; SPE: # %bb.0: # %entry ; SPE: # %bb.0: # %entry
; SPE-NEXT: mflr r0 ; SPE-NEXT: mflr r0
; SPE-NEXT: stw r0, 4(r1)
; SPE-NEXT: stwu r1, -16(r1) ; SPE-NEXT: stwu r1, -16(r1)
; SPE-NEXT: stw r0, 20(r1)
; SPE-NEXT: .cfi_def_cfa_offset 16 ; SPE-NEXT: .cfi_def_cfa_offset 16
; SPE-NEXT: .cfi_offset lr, 4 ; SPE-NEXT: .cfi_offset lr, 4
; SPE-NEXT: bl __fixsfdi ; SPE-NEXT: bl __fixsfdi
; SPE-NEXT: lwz r0, 20(r1) ; SPE-NEXT: lwz r0, 20(r1)
; SPE-NEXT: addi r1, r1, 16 ; SPE-NEXT: addi r1, r1, 16
; SPE-NEXT: mtlr r0 ; SPE-NEXT: mtlr r0
; SPE-NEXT: blr ; SPE-NEXT: blr
entry: entry:
%conv = call i64 @llvm.experimental.constrained.fptosi.i64.f32(float %m, metadata !"fpexcept.strict") #0 %conv = call i64 @llvm.experimental.constrained.fptosi.i64.f32(float %m, metadata !"fpexcept.strict") #0
ret i64 %conv ret i64 %conv
} }
define i64 @f_to_u64(float %m) #0 { define i64 @f_to_u64(float %m) #0 {
; SPE-LABEL: f_to_u64: ; SPE-LABEL: f_to_u64:
; SPE: # %bb.0: # %entry ; SPE: # %bb.0: # %entry
; SPE-NEXT: mflr r0 ; SPE-NEXT: mflr r0
; SPE-NEXT: stw r0, 4(r1)
; SPE-NEXT: stwu r1, -16(r1) ; SPE-NEXT: stwu r1, -16(r1)
; SPE-NEXT: stw r0, 20(r1)
; SPE-NEXT: .cfi_def_cfa_offset 16 ; SPE-NEXT: .cfi_def_cfa_offset 16
; SPE-NEXT: .cfi_offset lr, 4 ; SPE-NEXT: .cfi_offset lr, 4
; SPE-NEXT: bl __fixunssfdi ; SPE-NEXT: bl __fixunssfdi
; SPE-NEXT: lwz r0, 20(r1) ; SPE-NEXT: lwz r0, 20(r1)
; SPE-NEXT: addi r1, r1, 16 ; SPE-NEXT: addi r1, r1, 16
; SPE-NEXT: mtlr r0 ; SPE-NEXT: mtlr r0
; SPE-NEXT: blr ; SPE-NEXT: blr
entry: entry:
Show All 23 Linesentry:
%conv = tail call double @llvm.experimental.constrained.sitofp.f64.i32(i32 %m, metadata !"round.dynamic", metadata !"fpexcept.strict") #0 %conv = tail call double @llvm.experimental.constrained.sitofp.f64.i32(i32 %m, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
ret double %conv ret double %conv
} }
define double @i64_to_d(i64 %m) #0 { define double @i64_to_d(i64 %m) #0 {
; SPE-LABEL: i64_to_d: ; SPE-LABEL: i64_to_d:
; SPE: # %bb.0: # %entry ; SPE: # %bb.0: # %entry
; SPE-NEXT: mflr r0 ; SPE-NEXT: mflr r0
; SPE-NEXT: stw r0, 4(r1)
; SPE-NEXT: stwu r1, -16(r1) ; SPE-NEXT: stwu r1, -16(r1)
; SPE-NEXT: stw r0, 20(r1)
; SPE-NEXT: .cfi_def_cfa_offset 16 ; SPE-NEXT: .cfi_def_cfa_offset 16
; SPE-NEXT: .cfi_offset lr, 4 ; SPE-NEXT: .cfi_offset lr, 4
; SPE-NEXT: bl __floatdidf ; SPE-NEXT: bl __floatdidf
; SPE-NEXT: evmergelo r4, r3, r4 ; SPE-NEXT: evmergelo r4, r3, r4
; SPE-NEXT: evmergehi r3, r4, r4 ; SPE-NEXT: evmergehi r3, r4, r4
; SPE-NEXT: lwz r0, 20(r1) ; SPE-NEXT: lwz r0, 20(r1)
; SPE-NEXT: # kill: def $r3 killed $r3 killed $s3 ; SPE-NEXT: # kill: def $r3 killed $r3 killed $s3
; SPE-NEXT: # kill: def $r4 killed $r4 killed $s4 ; SPE-NEXT: # kill: def $r4 killed $r4 killed $s4
Show All 17 Linesentry:
%conv = tail call double @llvm.experimental.constrained.uitofp.f64.i32(i32 %m, metadata !"round.dynamic", metadata !"fpexcept.strict") #0 %conv = tail call double @llvm.experimental.constrained.uitofp.f64.i32(i32 %m, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
ret double %conv ret double %conv
} }
define double @u64_to_d(i64 %m) #0 { define double @u64_to_d(i64 %m) #0 {
; SPE-LABEL: u64_to_d: ; SPE-LABEL: u64_to_d:
; SPE: # %bb.0: # %entry ; SPE: # %bb.0: # %entry
; SPE-NEXT: mflr r0 ; SPE-NEXT: mflr r0
; SPE-NEXT: stw r0, 4(r1)
; SPE-NEXT: stwu r1, -16(r1) ; SPE-NEXT: stwu r1, -16(r1)
; SPE-NEXT: stw r0, 20(r1)
; SPE-NEXT: .cfi_def_cfa_offset 16 ; SPE-NEXT: .cfi_def_cfa_offset 16
; SPE-NEXT: .cfi_offset lr, 4 ; SPE-NEXT: .cfi_offset lr, 4
; SPE-NEXT: bl __floatundidf ; SPE-NEXT: bl __floatundidf
; SPE-NEXT: evmergelo r4, r3, r4 ; SPE-NEXT: evmergelo r4, r3, r4
; SPE-NEXT: evmergehi r3, r4, r4 ; SPE-NEXT: evmergehi r3, r4, r4
; SPE-NEXT: lwz r0, 20(r1) ; SPE-NEXT: lwz r0, 20(r1)
; SPE-NEXT: # kill: def $r3 killed $r3 killed $s3 ; SPE-NEXT: # kill: def $r3 killed $r3 killed $s3
; SPE-NEXT: # kill: def $r4 killed $r4 killed $s4 ; SPE-NEXT: # kill: def $r4 killed $r4 killed $s4
Show All 14 Linesentry:
%conv = tail call float @llvm.experimental.constrained.sitofp.f32.i32(i32 %m, metadata !"round.dynamic", metadata !"fpexcept.strict") #0 %conv = tail call float @llvm.experimental.constrained.sitofp.f32.i32(i32 %m, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
ret float %conv ret float %conv
} }
define float @i64_to_f(i64 %m) #0 { define float @i64_to_f(i64 %m) #0 {
; SPE-LABEL: i64_to_f: ; SPE-LABEL: i64_to_f:
; SPE: # %bb.0: # %entry ; SPE: # %bb.0: # %entry
; SPE-NEXT: mflr r0 ; SPE-NEXT: mflr r0
; SPE-NEXT: stw r0, 4(r1)
; SPE-NEXT: stwu r1, -16(r1) ; SPE-NEXT: stwu r1, -16(r1)
; SPE-NEXT: stw r0, 20(r1)
; SPE-NEXT: .cfi_def_cfa_offset 16 ; SPE-NEXT: .cfi_def_cfa_offset 16
; SPE-NEXT: .cfi_offset lr, 4 ; SPE-NEXT: .cfi_offset lr, 4
; SPE-NEXT: bl __floatdisf ; SPE-NEXT: bl __floatdisf
; SPE-NEXT: lwz r0, 20(r1) ; SPE-NEXT: lwz r0, 20(r1)
; SPE-NEXT: addi r1, r1, 16 ; SPE-NEXT: addi r1, r1, 16
; SPE-NEXT: mtlr r0 ; SPE-NEXT: mtlr r0
; SPE-NEXT: blr ; SPE-NEXT: blr
entry: entry:
Show All 10 Linesentry:
%conv = tail call float @llvm.experimental.constrained.uitofp.f32.i32(i32 %m, metadata !"round.dynamic", metadata !"fpexcept.strict") #0 %conv = tail call float @llvm.experimental.constrained.uitofp.f32.i32(i32 %m, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
ret float %conv ret float %conv
} }
define float @u64_to_f(i64 %m) #0 { define float @u64_to_f(i64 %m) #0 {
; SPE-LABEL: u64_to_f: ; SPE-LABEL: u64_to_f:
; SPE: # %bb.0: # %entry ; SPE: # %bb.0: # %entry
; SPE-NEXT: mflr r0 ; SPE-NEXT: mflr r0
; SPE-NEXT: stw r0, 4(r1)
; SPE-NEXT: stwu r1, -16(r1) ; SPE-NEXT: stwu r1, -16(r1)
; SPE-NEXT: stw r0, 20(r1)
; SPE-NEXT: .cfi_def_cfa_offset 16 ; SPE-NEXT: .cfi_def_cfa_offset 16
; SPE-NEXT: .cfi_offset lr, 4 ; SPE-NEXT: .cfi_offset lr, 4
; SPE-NEXT: bl __floatundisf ; SPE-NEXT: bl __floatundisf
; SPE-NEXT: lwz r0, 20(r1) ; SPE-NEXT: lwz r0, 20(r1)
; SPE-NEXT: addi r1, r1, 16 ; SPE-NEXT: addi r1, r1, 16
; SPE-NEXT: mtlr r0 ; SPE-NEXT: mtlr r0
; SPE-NEXT: blr ; SPE-NEXT: blr
entry: entry:
%conv = tail call float @llvm.experimental.constrained.uitofp.f32.i64(i64 %m, metadata !"round.dynamic", metadata !"fpexcept.strict") #0 %conv = tail call float @llvm.experimental.constrained.uitofp.f32.i64(i64 %m, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
ret float %conv ret float %conv
} }
attributes #0 = { strictfp } attributes #0 = { strictfp }

llvm/test/CodeGen/PowerPC/fp-strict-f128.ll

Show All 15 Lines
; CHECK-LABEL: fadd_f128: ; CHECK-LABEL: fadd_f128:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: xsaddqp v2, v2, v3 ; CHECK-NEXT: xsaddqp v2, v2, v3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: fadd_f128: ; CHECK-P8-LABEL: fadd_f128:
; CHECK-P8: # %bb.0: ; CHECK-P8: # %bb.0:
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: std r0, 48(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: bl __addkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addi r1, r1, 32 ; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
%res = call fp128 @llvm.experimental.constrained.fadd.f128( %res = call fp128 @llvm.experimental.constrained.fadd.f128(
fp128 %f1, fp128 %f2, fp128 %f1, fp128 %f2,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #0 metadata !"fpexcept.strict") #0
ret fp128 %res ret fp128 %res
} }
define fp128 @fsub_f128(fp128 %f1, fp128 %f2) #0 { define fp128 @fsub_f128(fp128 %f1, fp128 %f2) #0 {
; CHECK-LABEL: fsub_f128: ; CHECK-LABEL: fsub_f128:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: xssubqp v2, v2, v3 ; CHECK-NEXT: xssubqp v2, v2, v3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: fsub_f128: ; CHECK-P8-LABEL: fsub_f128:
; CHECK-P8: # %bb.0: ; CHECK-P8: # %bb.0:
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: std r0, 48(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: bl __subkf3 ; CHECK-P8-NEXT: bl __subkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addi r1, r1, 32 ; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
%res = call fp128 @llvm.experimental.constrained.fsub.f128( %res = call fp128 @llvm.experimental.constrained.fsub.f128(
fp128 %f1, fp128 %f2, fp128 %f1, fp128 %f2,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #0 metadata !"fpexcept.strict") #0
ret fp128 %res ret fp128 %res
} }
define fp128 @fmul_f128(fp128 %f1, fp128 %f2) #0 { define fp128 @fmul_f128(fp128 %f1, fp128 %f2) #0 {
; CHECK-LABEL: fmul_f128: ; CHECK-LABEL: fmul_f128:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: xsmulqp v2, v2, v3 ; CHECK-NEXT: xsmulqp v2, v2, v3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: fmul_f128: ; CHECK-P8-LABEL: fmul_f128:
; CHECK-P8: # %bb.0: ; CHECK-P8: # %bb.0:
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: std r0, 48(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: bl __mulkf3 ; CHECK-P8-NEXT: bl __mulkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addi r1, r1, 32 ; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
%res = call fp128 @llvm.experimental.constrained.fmul.f128( %res = call fp128 @llvm.experimental.constrained.fmul.f128(
fp128 %f1, fp128 %f2, fp128 %f1, fp128 %f2,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #0 metadata !"fpexcept.strict") #0
ret fp128 %res ret fp128 %res
} }
define fp128 @fdiv_f128(fp128 %f1, fp128 %f2) #0 { define fp128 @fdiv_f128(fp128 %f1, fp128 %f2) #0 {
; CHECK-LABEL: fdiv_f128: ; CHECK-LABEL: fdiv_f128:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: xsdivqp v2, v2, v3 ; CHECK-NEXT: xsdivqp v2, v2, v3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: fdiv_f128: ; CHECK-P8-LABEL: fdiv_f128:
; CHECK-P8: # %bb.0: ; CHECK-P8: # %bb.0:
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: std r0, 48(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: bl __divkf3 ; CHECK-P8-NEXT: bl __divkf3
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addi r1, r1, 32 ; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
Show All 9 Lines
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: xsmaddqp v4, v2, v3 ; CHECK-NEXT: xsmaddqp v4, v2, v3
; CHECK-NEXT: vmr v2, v4 ; CHECK-NEXT: vmr v2, v4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: fmadd_f128: ; CHECK-P8-LABEL: fmadd_f128:
; CHECK-P8: # %bb.0: ; CHECK-P8: # %bb.0:
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: std r0, 48(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: bl fmaf128 ; CHECK-P8-NEXT: bl fmaf128
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addi r1, r1, 32 ; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
Show All 9 Lines
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: xsmsubqp v4, v2, v3 ; CHECK-NEXT: xsmsubqp v4, v2, v3
; CHECK-NEXT: vmr v2, v4 ; CHECK-NEXT: vmr v2, v4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: fmsub_f128: ; CHECK-P8-LABEL: fmsub_f128:
; CHECK-P8: # %bb.0: ; CHECK-P8: # %bb.0:
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: xxswapd vs0, v4 ; CHECK-P8-NEXT: xxswapd vs0, v4
; CHECK-P8-NEXT: addi r3, r1, 32 ; CHECK-P8-NEXT: addi r3, r1, 32
; CHECK-P8-NEXT: stxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
; CHECK-P8-NEXT: lbz r4, 47(r1) ; CHECK-P8-NEXT: lbz r4, 47(r1)
; CHECK-P8-NEXT: xori r4, r4, 128 ; CHECK-P8-NEXT: xori r4, r4, 128
; CHECK-P8-NEXT: stb r4, 47(r1) ; CHECK-P8-NEXT: stb r4, 47(r1)
Show All 18 Lines
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: xsnmaddqp v4, v2, v3 ; CHECK-NEXT: xsnmaddqp v4, v2, v3
; CHECK-NEXT: vmr v2, v4 ; CHECK-NEXT: vmr v2, v4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: fnmadd_f128: ; CHECK-P8-LABEL: fnmadd_f128:
; CHECK-P8: # %bb.0: ; CHECK-P8: # %bb.0:
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: std r0, 64(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: bl fmaf128 ; CHECK-P8-NEXT: bl fmaf128
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: addi r3, r1, 32 ; CHECK-P8-NEXT: addi r3, r1, 32
; CHECK-P8-NEXT: stxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
; CHECK-P8-NEXT: lbz r4, 47(r1) ; CHECK-P8-NEXT: lbz r4, 47(r1)
Show All 18 Lines
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: xsnmsubqp v4, v2, v3 ; CHECK-NEXT: xsnmsubqp v4, v2, v3
; CHECK-NEXT: vmr v2, v4 ; CHECK-NEXT: vmr v2, v4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: fnmsub_f128: ; CHECK-P8-LABEL: fnmsub_f128:
; CHECK-P8: # %bb.0: ; CHECK-P8: # %bb.0:
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -64(r1) ; CHECK-P8-NEXT: stdu r1, -64(r1)
; CHECK-P8-NEXT: std r0, 80(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 64 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 64
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: xxswapd vs0, v4 ; CHECK-P8-NEXT: xxswapd vs0, v4
; CHECK-P8-NEXT: addi r3, r1, 32 ; CHECK-P8-NEXT: addi r3, r1, 32
; CHECK-P8-NEXT: stxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
; CHECK-P8-NEXT: lbz r4, 47(r1) ; CHECK-P8-NEXT: lbz r4, 47(r1)
; CHECK-P8-NEXT: xori r4, r4, 128 ; CHECK-P8-NEXT: xori r4, r4, 128
; CHECK-P8-NEXT: stb r4, 47(r1) ; CHECK-P8-NEXT: stb r4, 47(r1)
Show All 27 Lines
; CHECK-LABEL: fsqrt_f128: ; CHECK-LABEL: fsqrt_f128:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: xssqrtqp v2, v2 ; CHECK-NEXT: xssqrtqp v2, v2
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-P8-LABEL: fsqrt_f128: ; CHECK-P8-LABEL: fsqrt_f128:
; CHECK-P8: # %bb.0: ; CHECK-P8: # %bb.0:
; CHECK-P8-NEXT: mflr r0 ; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: std r0, 48(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16 ; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: bl sqrtf128 ; CHECK-P8-NEXT: bl sqrtf128
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addi r1, r1, 32 ; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
%res = call fp128 @llvm.experimental.constrained.sqrt.f128( %res = call fp128 @llvm.experimental.constrained.sqrt.f128(
fp128 %f1, fp128 %f1,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #0 metadata !"fpexcept.strict") #0
ret fp128 %res ret fp128 %res
} }
attributes #0 = { strictfp } attributes #0 = { strictfp }

llvm/test/CodeGen/PowerPC/fp-strict-fcmp.ll

Show First 20 Lines • Show All 1,479 Lines • ▼ Show 20 Lines; NOVSX-NEXT: blr
%res = select i1 %cond, i32 %a, i32 %b %res = select i1 %cond, i32 %a, i32 %b
ret i32 %res ret i32 %res
} }
define i32 @fcmp_olt_f128(fp128 %a, fp128 %b) #0 { define i32 @fcmp_olt_f128(fp128 %a, fp128 %b) #0 {
; P8-LABEL: fcmp_olt_f128: ; P8-LABEL: fcmp_olt_f128:
; P8: # %bb.0: ; P8: # %bb.0:
; P8-NEXT: mflr r0 ; P8-NEXT: mflr r0
; P8-NEXT: std r0, 16(r1)
; P8-NEXT: stdu r1, -112(r1) ; P8-NEXT: stdu r1, -112(r1)
; P8-NEXT: std r0, 128(r1)
; P8-NEXT: bl __ltkf2 ; P8-NEXT: bl __ltkf2
; P8-NEXT: nop ; P8-NEXT: nop
; P8-NEXT: rlwinm r3, r3, 1, 31, 31 ; P8-NEXT: rlwinm r3, r3, 1, 31, 31
; P8-NEXT: addi r1, r1, 112 ; P8-NEXT: addi r1, r1, 112
; P8-NEXT: ld r0, 16(r1) ; P8-NEXT: ld r0, 16(r1)
; P8-NEXT: mtlr r0 ; P8-NEXT: mtlr r0
; P8-NEXT: blr ; P8-NEXT: blr
; ;
; P9-LABEL: fcmp_olt_f128: ; P9-LABEL: fcmp_olt_f128:
; P9: # %bb.0: ; P9: # %bb.0:
; P9-NEXT: xscmpuqp cr0, v2, v3 ; P9-NEXT: xscmpuqp cr0, v2, v3
; P9-NEXT: li r3, 0 ; P9-NEXT: li r3, 0
; P9-NEXT: li r4, 1 ; P9-NEXT: li r4, 1
; P9-NEXT: isellt r3, r4, r3 ; P9-NEXT: isellt r3, r4, r3
; P9-NEXT: blr ; P9-NEXT: blr
; ;
; NOVSX-LABEL: fcmp_olt_f128: ; NOVSX-LABEL: fcmp_olt_f128:
; NOVSX: # %bb.0: ; NOVSX: # %bb.0:
; NOVSX-NEXT: mflr r0 ; NOVSX-NEXT: mflr r0
; NOVSX-NEXT: std r0, 16(r1)
; NOVSX-NEXT: stdu r1, -32(r1) ; NOVSX-NEXT: stdu r1, -32(r1)
; NOVSX-NEXT: std r0, 48(r1)
; NOVSX-NEXT: bl __ltkf2 ; NOVSX-NEXT: bl __ltkf2
; NOVSX-NEXT: nop ; NOVSX-NEXT: nop
; NOVSX-NEXT: rlwinm r3, r3, 1, 31, 31 ; NOVSX-NEXT: rlwinm r3, r3, 1, 31, 31
; NOVSX-NEXT: addi r1, r1, 32 ; NOVSX-NEXT: addi r1, r1, 32
; NOVSX-NEXT: ld r0, 16(r1) ; NOVSX-NEXT: ld r0, 16(r1)
; NOVSX-NEXT: mtlr r0 ; NOVSX-NEXT: mtlr r0
; NOVSX-NEXT: blr ; NOVSX-NEXT: blr
%cmp = call i1 @llvm.experimental.constrained.fcmp.f128(fp128 %a, fp128 %b, metadata !"olt", metadata !"fpexcept.strict") #0 %cmp = call i1 @llvm.experimental.constrained.fcmp.f128(fp128 %a, fp128 %b, metadata !"olt", metadata !"fpexcept.strict") #0
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
ret i32 %conv ret i32 %conv
} }
define i32 @fcmp_ole_f128(fp128 %a, fp128 %b) #0 { define i32 @fcmp_ole_f128(fp128 %a, fp128 %b) #0 {
; P8-LABEL: fcmp_ole_f128: ; P8-LABEL: fcmp_ole_f128:
; P8: # %bb.0: ; P8: # %bb.0:
; P8-NEXT: mflr r0 ; P8-NEXT: mflr r0
; P8-NEXT: std r0, 16(r1)
; P8-NEXT: stdu r1, -112(r1) ; P8-NEXT: stdu r1, -112(r1)
; P8-NEXT: std r0, 128(r1)
; P8-NEXT: bl __lekf2 ; P8-NEXT: bl __lekf2
; P8-NEXT: nop ; P8-NEXT: nop
; P8-NEXT: extsw r3, r3 ; P8-NEXT: extsw r3, r3
; P8-NEXT: neg r3, r3 ; P8-NEXT: neg r3, r3
; P8-NEXT: rldicl r3, r3, 1, 63 ; P8-NEXT: rldicl r3, r3, 1, 63
; P8-NEXT: xori r3, r3, 1 ; P8-NEXT: xori r3, r3, 1
; P8-NEXT: addi r1, r1, 112 ; P8-NEXT: addi r1, r1, 112
; P8-NEXT: ld r0, 16(r1) ; P8-NEXT: ld r0, 16(r1)
; P8-NEXT: mtlr r0 ; P8-NEXT: mtlr r0
; P8-NEXT: blr ; P8-NEXT: blr
; ;
; P9-LABEL: fcmp_ole_f128: ; P9-LABEL: fcmp_ole_f128:
; P9: # %bb.0: ; P9: # %bb.0:
; P9-NEXT: xscmpuqp cr0, v2, v3 ; P9-NEXT: xscmpuqp cr0, v2, v3
; P9-NEXT: li r3, 1 ; P9-NEXT: li r3, 1
; P9-NEXT: cror 4*cr5+lt, un, gt ; P9-NEXT: cror 4*cr5+lt, un, gt
; P9-NEXT: isel r3, 0, r3, 4*cr5+lt ; P9-NEXT: isel r3, 0, r3, 4*cr5+lt
; P9-NEXT: blr ; P9-NEXT: blr
; ;
; NOVSX-LABEL: fcmp_ole_f128: ; NOVSX-LABEL: fcmp_ole_f128:
; NOVSX: # %bb.0: ; NOVSX: # %bb.0:
; NOVSX-NEXT: mflr r0 ; NOVSX-NEXT: mflr r0
; NOVSX-NEXT: std r0, 16(r1)
; NOVSX-NEXT: stdu r1, -32(r1) ; NOVSX-NEXT: stdu r1, -32(r1)
; NOVSX-NEXT: std r0, 48(r1)
; NOVSX-NEXT: bl __lekf2 ; NOVSX-NEXT: bl __lekf2
; NOVSX-NEXT: nop ; NOVSX-NEXT: nop
; NOVSX-NEXT: extsw r3, r3 ; NOVSX-NEXT: extsw r3, r3
; NOVSX-NEXT: neg r3, r3 ; NOVSX-NEXT: neg r3, r3
; NOVSX-NEXT: rldicl r3, r3, 1, 63 ; NOVSX-NEXT: rldicl r3, r3, 1, 63
; NOVSX-NEXT: xori r3, r3, 1 ; NOVSX-NEXT: xori r3, r3, 1
; NOVSX-NEXT: addi r1, r1, 32 ; NOVSX-NEXT: addi r1, r1, 32
; NOVSX-NEXT: ld r0, 16(r1) ; NOVSX-NEXT: ld r0, 16(r1)
; NOVSX-NEXT: mtlr r0 ; NOVSX-NEXT: mtlr r0
; NOVSX-NEXT: blr ; NOVSX-NEXT: blr
%cmp = call i1 @llvm.experimental.constrained.fcmp.f128(fp128 %a, fp128 %b, metadata !"ole", metadata !"fpexcept.strict") #0 %cmp = call i1 @llvm.experimental.constrained.fcmp.f128(fp128 %a, fp128 %b, metadata !"ole", metadata !"fpexcept.strict") #0
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
ret i32 %conv ret i32 %conv
} }
define i32 @fcmp_ogt_f128(fp128 %a, fp128 %b) #0 { define i32 @fcmp_ogt_f128(fp128 %a, fp128 %b) #0 {
; P8-LABEL: fcmp_ogt_f128: ; P8-LABEL: fcmp_ogt_f128:
; P8: # %bb.0: ; P8: # %bb.0:
; P8-NEXT: mflr r0 ; P8-NEXT: mflr r0
; P8-NEXT: std r0, 16(r1)
; P8-NEXT: stdu r1, -112(r1) ; P8-NEXT: stdu r1, -112(r1)
; P8-NEXT: std r0, 128(r1)
; P8-NEXT: bl __gtkf2 ; P8-NEXT: bl __gtkf2
; P8-NEXT: nop ; P8-NEXT: nop
; P8-NEXT: extsw r3, r3 ; P8-NEXT: extsw r3, r3
; P8-NEXT: neg r3, r3 ; P8-NEXT: neg r3, r3
; P8-NEXT: rldicl r3, r3, 1, 63 ; P8-NEXT: rldicl r3, r3, 1, 63
; P8-NEXT: addi r1, r1, 112 ; P8-NEXT: addi r1, r1, 112
; P8-NEXT: ld r0, 16(r1) ; P8-NEXT: ld r0, 16(r1)
; P8-NEXT: mtlr r0 ; P8-NEXT: mtlr r0
; P8-NEXT: blr ; P8-NEXT: blr
; ;
; P9-LABEL: fcmp_ogt_f128: ; P9-LABEL: fcmp_ogt_f128:
; P9: # %bb.0: ; P9: # %bb.0:
; P9-NEXT: xscmpuqp cr0, v2, v3 ; P9-NEXT: xscmpuqp cr0, v2, v3
; P9-NEXT: li r3, 0 ; P9-NEXT: li r3, 0
; P9-NEXT: li r4, 1 ; P9-NEXT: li r4, 1
; P9-NEXT: iselgt r3, r4, r3 ; P9-NEXT: iselgt r3, r4, r3
; P9-NEXT: blr ; P9-NEXT: blr
; ;
; NOVSX-LABEL: fcmp_ogt_f128: ; NOVSX-LABEL: fcmp_ogt_f128:
; NOVSX: # %bb.0: ; NOVSX: # %bb.0:
; NOVSX-NEXT: mflr r0 ; NOVSX-NEXT: mflr r0
; NOVSX-NEXT: std r0, 16(r1)
; NOVSX-NEXT: stdu r1, -32(r1) ; NOVSX-NEXT: stdu r1, -32(r1)
; NOVSX-NEXT: std r0, 48(r1)
; NOVSX-NEXT: bl __gtkf2 ; NOVSX-NEXT: bl __gtkf2
; NOVSX-NEXT: nop ; NOVSX-NEXT: nop
; NOVSX-NEXT: extsw r3, r3 ; NOVSX-NEXT: extsw r3, r3
; NOVSX-NEXT: neg r3, r3 ; NOVSX-NEXT: neg r3, r3
; NOVSX-NEXT: rldicl r3, r3, 1, 63 ; NOVSX-NEXT: rldicl r3, r3, 1, 63
; NOVSX-NEXT: addi r1, r1, 32 ; NOVSX-NEXT: addi r1, r1, 32
; NOVSX-NEXT: ld r0, 16(r1) ; NOVSX-NEXT: ld r0, 16(r1)
; NOVSX-NEXT: mtlr r0 ; NOVSX-NEXT: mtlr r0
; NOVSX-NEXT: blr ; NOVSX-NEXT: blr
%cmp = call i1 @llvm.experimental.constrained.fcmp.f128(fp128 %a, fp128 %b, metadata !"ogt", metadata !"fpexcept.strict") #0 %cmp = call i1 @llvm.experimental.constrained.fcmp.f128(fp128 %a, fp128 %b, metadata !"ogt", metadata !"fpexcept.strict") #0
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
ret i32 %conv ret i32 %conv
} }
define i32 @fcmp_oge_f128(fp128 %a, fp128 %b) #0 { define i32 @fcmp_oge_f128(fp128 %a, fp128 %b) #0 {
; P8-LABEL: fcmp_oge_f128: ; P8-LABEL: fcmp_oge_f128:
; P8: # %bb.0: ; P8: # %bb.0:
; P8-NEXT: mflr r0 ; P8-NEXT: mflr r0
; P8-NEXT: std r0, 16(r1)
; P8-NEXT: stdu r1, -112(r1) ; P8-NEXT: stdu r1, -112(r1)
; P8-NEXT: std r0, 128(r1)
; P8-NEXT: bl __gekf2 ; P8-NEXT: bl __gekf2
; P8-NEXT: nop ; P8-NEXT: nop
; P8-NEXT: rlwinm r3, r3, 1, 31, 31 ; P8-NEXT: rlwinm r3, r3, 1, 31, 31
; P8-NEXT: xori r3, r3, 1 ; P8-NEXT: xori r3, r3, 1
; P8-NEXT: addi r1, r1, 112 ; P8-NEXT: addi r1, r1, 112
; P8-NEXT: ld r0, 16(r1) ; P8-NEXT: ld r0, 16(r1)
; P8-NEXT: mtlr r0 ; P8-NEXT: mtlr r0
; P8-NEXT: blr ; P8-NEXT: blr
; ;
; P9-LABEL: fcmp_oge_f128: ; P9-LABEL: fcmp_oge_f128:
; P9: # %bb.0: ; P9: # %bb.0:
; P9-NEXT: xscmpuqp cr0, v2, v3 ; P9-NEXT: xscmpuqp cr0, v2, v3
; P9-NEXT: li r3, 1 ; P9-NEXT: li r3, 1
; P9-NEXT: cror 4*cr5+lt, un, lt ; P9-NEXT: cror 4*cr5+lt, un, lt
; P9-NEXT: isel r3, 0, r3, 4*cr5+lt ; P9-NEXT: isel r3, 0, r3, 4*cr5+lt
; P9-NEXT: blr ; P9-NEXT: blr
; ;
; NOVSX-LABEL: fcmp_oge_f128: ; NOVSX-LABEL: fcmp_oge_f128:
; NOVSX: # %bb.0: ; NOVSX: # %bb.0:
; NOVSX-NEXT: mflr r0 ; NOVSX-NEXT: mflr r0
; NOVSX-NEXT: std r0, 16(r1)
; NOVSX-NEXT: stdu r1, -32(r1) ; NOVSX-NEXT: stdu r1, -32(r1)
; NOVSX-NEXT: std r0, 48(r1)
; NOVSX-NEXT: bl __gekf2 ; NOVSX-NEXT: bl __gekf2
; NOVSX-NEXT: nop ; NOVSX-NEXT: nop
; NOVSX-NEXT: rlwinm r3, r3, 1, 31, 31 ; NOVSX-NEXT: rlwinm r3, r3, 1, 31, 31
; NOVSX-NEXT: xori r3, r3, 1 ; NOVSX-NEXT: xori r3, r3, 1
; NOVSX-NEXT: addi r1, r1, 32 ; NOVSX-NEXT: addi r1, r1, 32
; NOVSX-NEXT: ld r0, 16(r1) ; NOVSX-NEXT: ld r0, 16(r1)
; NOVSX-NEXT: mtlr r0 ; NOVSX-NEXT: mtlr r0
; NOVSX-NEXT: blr ; NOVSX-NEXT: blr
%cmp = call i1 @llvm.experimental.constrained.fcmp.f128(fp128 %a, fp128 %b, metadata !"oge", metadata !"fpexcept.strict") #0 %cmp = call i1 @llvm.experimental.constrained.fcmp.f128(fp128 %a, fp128 %b, metadata !"oge", metadata !"fpexcept.strict") #0
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
ret i32 %conv ret i32 %conv
} }
define i32 @fcmp_oeq_f128(fp128 %a, fp128 %b) #0 { define i32 @fcmp_oeq_f128(fp128 %a, fp128 %b) #0 {
; P8-LABEL: fcmp_oeq_f128: ; P8-LABEL: fcmp_oeq_f128:
; P8: # %bb.0: ; P8: # %bb.0:
; P8-NEXT: mflr r0 ; P8-NEXT: mflr r0
; P8-NEXT: std r0, 16(r1)
; P8-NEXT: stdu r1, -112(r1) ; P8-NEXT: stdu r1, -112(r1)
; P8-NEXT: std r0, 128(r1)
; P8-NEXT: bl __eqkf2 ; P8-NEXT: bl __eqkf2
; P8-NEXT: nop ; P8-NEXT: nop
; P8-NEXT: cntlzw r3, r3 ; P8-NEXT: cntlzw r3, r3
; P8-NEXT: srwi r3, r3, 5 ; P8-NEXT: srwi r3, r3, 5
; P8-NEXT: addi r1, r1, 112 ; P8-NEXT: addi r1, r1, 112
; P8-NEXT: ld r0, 16(r1) ; P8-NEXT: ld r0, 16(r1)
; P8-NEXT: mtlr r0 ; P8-NEXT: mtlr r0
; P8-NEXT: blr ; P8-NEXT: blr
; ;
; P9-LABEL: fcmp_oeq_f128: ; P9-LABEL: fcmp_oeq_f128:
; P9: # %bb.0: ; P9: # %bb.0:
; P9-NEXT: xscmpuqp cr0, v2, v3 ; P9-NEXT: xscmpuqp cr0, v2, v3
; P9-NEXT: li r3, 0 ; P9-NEXT: li r3, 0
; P9-NEXT: li r4, 1 ; P9-NEXT: li r4, 1
; P9-NEXT: iseleq r3, r4, r3 ; P9-NEXT: iseleq r3, r4, r3
; P9-NEXT: blr ; P9-NEXT: blr
; ;
; NOVSX-LABEL: fcmp_oeq_f128: ; NOVSX-LABEL: fcmp_oeq_f128:
; NOVSX: # %bb.0: ; NOVSX: # %bb.0:
; NOVSX-NEXT: mflr r0 ; NOVSX-NEXT: mflr r0
; NOVSX-NEXT: std r0, 16(r1)
; NOVSX-NEXT: stdu r1, -32(r1) ; NOVSX-NEXT: stdu r1, -32(r1)
; NOVSX-NEXT: std r0, 48(r1)
; NOVSX-NEXT: bl __eqkf2 ; NOVSX-NEXT: bl __eqkf2
; NOVSX-NEXT: nop ; NOVSX-NEXT: nop
; NOVSX-NEXT: cntlzw r3, r3 ; NOVSX-NEXT: cntlzw r3, r3
; NOVSX-NEXT: srwi r3, r3, 5 ; NOVSX-NEXT: srwi r3, r3, 5
; NOVSX-NEXT: addi r1, r1, 32 ; NOVSX-NEXT: addi r1, r1, 32
; NOVSX-NEXT: ld r0, 16(r1) ; NOVSX-NEXT: ld r0, 16(r1)
; NOVSX-NEXT: mtlr r0 ; NOVSX-NEXT: mtlr r0
; NOVSX-NEXT: blr ; NOVSX-NEXT: blr
%cmp = call i1 @llvm.experimental.constrained.fcmp.f128(fp128 %a, fp128 %b, metadata !"oeq", metadata !"fpexcept.strict") #0 %cmp = call i1 @llvm.experimental.constrained.fcmp.f128(fp128 %a, fp128 %b, metadata !"oeq", metadata !"fpexcept.strict") #0
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
ret i32 %conv ret i32 %conv
} }
define i32 @fcmp_one_f128(fp128 %a, fp128 %b) #0 { define i32 @fcmp_one_f128(fp128 %a, fp128 %b) #0 {
; P8-LABEL: fcmp_one_f128: ; P8-LABEL: fcmp_one_f128:
; P8: # %bb.0: ; P8: # %bb.0:
; P8-NEXT: mflr r0 ; P8-NEXT: mflr r0
; P8-NEXT: std r0, 16(r1)
; P8-NEXT: stdu r1, -176(r1) ; P8-NEXT: stdu r1, -176(r1)
; P8-NEXT: li r3, 128 ; P8-NEXT: li r3, 128
; P8-NEXT: std r0, 192(r1)
; P8-NEXT: std r30, 160(r1) # 8-byte Folded Spill ; P8-NEXT: std r30, 160(r1) # 8-byte Folded Spill
; P8-NEXT: stxvd2x v30, r1, r3 # 16-byte Folded Spill ; P8-NEXT: stxvd2x v30, r1, r3 # 16-byte Folded Spill
; P8-NEXT: li r3, 144 ; P8-NEXT: li r3, 144
; P8-NEXT: vmr v30, v2 ; P8-NEXT: vmr v30, v2
; P8-NEXT: stxvd2x v31, r1, r3 # 16-byte Folded Spill ; P8-NEXT: stxvd2x v31, r1, r3 # 16-byte Folded Spill
; P8-NEXT: vmr v31, v3 ; P8-NEXT: vmr v31, v3
; P8-NEXT: bl __unordkf2 ; P8-NEXT: bl __unordkf2
; P8-NEXT: nop ; P8-NEXT: nop
Show All 28 Lines
; NOVSX-LABEL: fcmp_one_f128: ; NOVSX-LABEL: fcmp_one_f128:
; NOVSX: # %bb.0: ; NOVSX: # %bb.0:
; NOVSX-NEXT: mflr r0 ; NOVSX-NEXT: mflr r0
; NOVSX-NEXT: std r26, -48(r1) # 8-byte Folded Spill ; NOVSX-NEXT: std r26, -48(r1) # 8-byte Folded Spill
; NOVSX-NEXT: std r27, -40(r1) # 8-byte Folded Spill ; NOVSX-NEXT: std r27, -40(r1) # 8-byte Folded Spill
; NOVSX-NEXT: std r28, -32(r1) # 8-byte Folded Spill ; NOVSX-NEXT: std r28, -32(r1) # 8-byte Folded Spill
; NOVSX-NEXT: std r29, -24(r1) # 8-byte Folded Spill ; NOVSX-NEXT: std r29, -24(r1) # 8-byte Folded Spill
; NOVSX-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; NOVSX-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; NOVSX-NEXT: std r0, 16(r1)
; NOVSX-NEXT: stdu r1, -80(r1) ; NOVSX-NEXT: stdu r1, -80(r1)
; NOVSX-NEXT: std r0, 96(r1)
; NOVSX-NEXT: mr r30, r6 ; NOVSX-NEXT: mr r30, r6
; NOVSX-NEXT: mr r29, r5 ; NOVSX-NEXT: mr r29, r5
; NOVSX-NEXT: mr r28, r4 ; NOVSX-NEXT: mr r28, r4
; NOVSX-NEXT: mr r27, r3 ; NOVSX-NEXT: mr r27, r3
; NOVSX-NEXT: bl __unordkf2 ; NOVSX-NEXT: bl __unordkf2
; NOVSX-NEXT: nop ; NOVSX-NEXT: nop
; NOVSX-NEXT: cntlzw r3, r3 ; NOVSX-NEXT: cntlzw r3, r3
; NOVSX-NEXT: mr r4, r28 ; NOVSX-NEXT: mr r4, r28
Show All 20 Lines; NOVSX-NEXT: blr
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
ret i32 %conv ret i32 %conv
} }
define i32 @fcmp_ult_f128(fp128 %a, fp128 %b) #0 { define i32 @fcmp_ult_f128(fp128 %a, fp128 %b) #0 {
; P8-LABEL: fcmp_ult_f128: ; P8-LABEL: fcmp_ult_f128:
; P8: # %bb.0: ; P8: # %bb.0:
; P8-NEXT: mflr r0 ; P8-NEXT: mflr r0
; P8-NEXT: std r0, 16(r1)
; P8-NEXT: stdu r1, -112(r1) ; P8-NEXT: stdu r1, -112(r1)
; P8-NEXT: std r0, 128(r1)
; P8-NEXT: bl __gekf2 ; P8-NEXT: bl __gekf2
; P8-NEXT: nop ; P8-NEXT: nop
; P8-NEXT: rlwinm r3, r3, 1, 31, 31 ; P8-NEXT: rlwinm r3, r3, 1, 31, 31
; P8-NEXT: addi r1, r1, 112 ; P8-NEXT: addi r1, r1, 112
; P8-NEXT: ld r0, 16(r1) ; P8-NEXT: ld r0, 16(r1)
; P8-NEXT: mtlr r0 ; P8-NEXT: mtlr r0
; P8-NEXT: blr ; P8-NEXT: blr
; ;
; P9-LABEL: fcmp_ult_f128: ; P9-LABEL: fcmp_ult_f128:
; P9: # %bb.0: ; P9: # %bb.0:
; P9-NEXT: xscmpuqp cr0, v2, v3 ; P9-NEXT: xscmpuqp cr0, v2, v3
; P9-NEXT: li r3, 1 ; P9-NEXT: li r3, 1
; P9-NEXT: crnor 4*cr5+lt, lt, un ; P9-NEXT: crnor 4*cr5+lt, lt, un
; P9-NEXT: isel r3, 0, r3, 4*cr5+lt ; P9-NEXT: isel r3, 0, r3, 4*cr5+lt
; P9-NEXT: blr ; P9-NEXT: blr
; ;
; NOVSX-LABEL: fcmp_ult_f128: ; NOVSX-LABEL: fcmp_ult_f128:
; NOVSX: # %bb.0: ; NOVSX: # %bb.0:
; NOVSX-NEXT: mflr r0 ; NOVSX-NEXT: mflr r0
; NOVSX-NEXT: std r0, 16(r1)
; NOVSX-NEXT: stdu r1, -32(r1) ; NOVSX-NEXT: stdu r1, -32(r1)
; NOVSX-NEXT: std r0, 48(r1)
; NOVSX-NEXT: bl __gekf2 ; NOVSX-NEXT: bl __gekf2
; NOVSX-NEXT: nop ; NOVSX-NEXT: nop
; NOVSX-NEXT: rlwinm r3, r3, 1, 31, 31 ; NOVSX-NEXT: rlwinm r3, r3, 1, 31, 31
; NOVSX-NEXT: addi r1, r1, 32 ; NOVSX-NEXT: addi r1, r1, 32
; NOVSX-NEXT: ld r0, 16(r1) ; NOVSX-NEXT: ld r0, 16(r1)
; NOVSX-NEXT: mtlr r0 ; NOVSX-NEXT: mtlr r0
; NOVSX-NEXT: blr ; NOVSX-NEXT: blr
%cmp = call i1 @llvm.experimental.constrained.fcmp.f128(fp128 %a, fp128 %b, metadata !"ult", metadata !"fpexcept.strict") #0 %cmp = call i1 @llvm.experimental.constrained.fcmp.f128(fp128 %a, fp128 %b, metadata !"ult", metadata !"fpexcept.strict") #0
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
ret i32 %conv ret i32 %conv
} }
define i32 @fcmp_ule_f128(fp128 %a, fp128 %b) #0 { define i32 @fcmp_ule_f128(fp128 %a, fp128 %b) #0 {
; P8-LABEL: fcmp_ule_f128: ; P8-LABEL: fcmp_ule_f128:
; P8: # %bb.0: ; P8: # %bb.0:
; P8-NEXT: mflr r0 ; P8-NEXT: mflr r0
; P8-NEXT: std r0, 16(r1)
; P8-NEXT: stdu r1, -112(r1) ; P8-NEXT: stdu r1, -112(r1)
; P8-NEXT: std r0, 128(r1)
; P8-NEXT: bl __gtkf2 ; P8-NEXT: bl __gtkf2
; P8-NEXT: nop ; P8-NEXT: nop
; P8-NEXT: extsw r3, r3 ; P8-NEXT: extsw r3, r3
; P8-NEXT: neg r3, r3 ; P8-NEXT: neg r3, r3
; P8-NEXT: rldicl r3, r3, 1, 63 ; P8-NEXT: rldicl r3, r3, 1, 63
; P8-NEXT: xori r3, r3, 1 ; P8-NEXT: xori r3, r3, 1
; P8-NEXT: addi r1, r1, 112 ; P8-NEXT: addi r1, r1, 112
; P8-NEXT: ld r0, 16(r1) ; P8-NEXT: ld r0, 16(r1)
; P8-NEXT: mtlr r0 ; P8-NEXT: mtlr r0
; P8-NEXT: blr ; P8-NEXT: blr
; ;
; P9-LABEL: fcmp_ule_f128: ; P9-LABEL: fcmp_ule_f128:
; P9: # %bb.0: ; P9: # %bb.0:
; P9-NEXT: xscmpuqp cr0, v2, v3 ; P9-NEXT: xscmpuqp cr0, v2, v3
; P9-NEXT: li r3, 1 ; P9-NEXT: li r3, 1
; P9-NEXT: iselgt r3, 0, r3 ; P9-NEXT: iselgt r3, 0, r3
; P9-NEXT: blr ; P9-NEXT: blr
; ;
; NOVSX-LABEL: fcmp_ule_f128: ; NOVSX-LABEL: fcmp_ule_f128:
; NOVSX: # %bb.0: ; NOVSX: # %bb.0:
; NOVSX-NEXT: mflr r0 ; NOVSX-NEXT: mflr r0
; NOVSX-NEXT: std r0, 16(r1)
; NOVSX-NEXT: stdu r1, -32(r1) ; NOVSX-NEXT: stdu r1, -32(r1)
; NOVSX-NEXT: std r0, 48(r1)
; NOVSX-NEXT: bl __gtkf2 ; NOVSX-NEXT: bl __gtkf2
; NOVSX-NEXT: nop ; NOVSX-NEXT: nop
; NOVSX-NEXT: extsw r3, r3 ; NOVSX-NEXT: extsw r3, r3
; NOVSX-NEXT: neg r3, r3 ; NOVSX-NEXT: neg r3, r3
; NOVSX-NEXT: rldicl r3, r3, 1, 63 ; NOVSX-NEXT: rldicl r3, r3, 1, 63
; NOVSX-NEXT: xori r3, r3, 1 ; NOVSX-NEXT: xori r3, r3, 1
; NOVSX-NEXT: addi r1, r1, 32 ; NOVSX-NEXT: addi r1, r1, 32
; NOVSX-NEXT: ld r0, 16(r1) ; NOVSX-NEXT: ld r0, 16(r1)
; NOVSX-NEXT: mtlr r0 ; NOVSX-NEXT: mtlr r0
; NOVSX-NEXT: blr ; NOVSX-NEXT: blr
%cmp = call i1 @llvm.experimental.constrained.fcmp.f128(fp128 %a, fp128 %b, metadata !"ule", metadata !"fpexcept.strict") #0 %cmp = call i1 @llvm.experimental.constrained.fcmp.f128(fp128 %a, fp128 %b, metadata !"ule", metadata !"fpexcept.strict") #0
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
ret i32 %conv ret i32 %conv
} }
define i32 @fcmp_ugt_f128(fp128 %a, fp128 %b) #0 { define i32 @fcmp_ugt_f128(fp128 %a, fp128 %b) #0 {
; P8-LABEL: fcmp_ugt_f128: ; P8-LABEL: fcmp_ugt_f128:
; P8: # %bb.0: ; P8: # %bb.0:
; P8-NEXT: mflr r0 ; P8-NEXT: mflr r0
; P8-NEXT: std r0, 16(r1)
; P8-NEXT: stdu r1, -112(r1) ; P8-NEXT: stdu r1, -112(r1)
; P8-NEXT: std r0, 128(r1)
; P8-NEXT: bl __lekf2 ; P8-NEXT: bl __lekf2
; P8-NEXT: nop ; P8-NEXT: nop
; P8-NEXT: extsw r3, r3 ; P8-NEXT: extsw r3, r3
; P8-NEXT: neg r3, r3 ; P8-NEXT: neg r3, r3
; P8-NEXT: rldicl r3, r3, 1, 63 ; P8-NEXT: rldicl r3, r3, 1, 63
; P8-NEXT: addi r1, r1, 112 ; P8-NEXT: addi r1, r1, 112
; P8-NEXT: ld r0, 16(r1) ; P8-NEXT: ld r0, 16(r1)
; P8-NEXT: mtlr r0 ; P8-NEXT: mtlr r0
; P8-NEXT: blr ; P8-NEXT: blr
; ;
; P9-LABEL: fcmp_ugt_f128: ; P9-LABEL: fcmp_ugt_f128:
; P9: # %bb.0: ; P9: # %bb.0:
; P9-NEXT: xscmpuqp cr0, v2, v3 ; P9-NEXT: xscmpuqp cr0, v2, v3
; P9-NEXT: li r3, 1 ; P9-NEXT: li r3, 1
; P9-NEXT: crnor 4*cr5+lt, gt, un ; P9-NEXT: crnor 4*cr5+lt, gt, un
; P9-NEXT: isel r3, 0, r3, 4*cr5+lt ; P9-NEXT: isel r3, 0, r3, 4*cr5+lt
; P9-NEXT: blr ; P9-NEXT: blr
; ;
; NOVSX-LABEL: fcmp_ugt_f128: ; NOVSX-LABEL: fcmp_ugt_f128:
; NOVSX: # %bb.0: ; NOVSX: # %bb.0:
; NOVSX-NEXT: mflr r0 ; NOVSX-NEXT: mflr r0
; NOVSX-NEXT: std r0, 16(r1)
; NOVSX-NEXT: stdu r1, -32(r1) ; NOVSX-NEXT: stdu r1, -32(r1)
; NOVSX-NEXT: std r0, 48(r1)
; NOVSX-NEXT: bl __lekf2 ; NOVSX-NEXT: bl __lekf2
; NOVSX-NEXT: nop ; NOVSX-NEXT: nop
; NOVSX-NEXT: extsw r3, r3 ; NOVSX-NEXT: extsw r3, r3
; NOVSX-NEXT: neg r3, r3 ; NOVSX-NEXT: neg r3, r3
; NOVSX-NEXT: rldicl r3, r3, 1, 63 ; NOVSX-NEXT: rldicl r3, r3, 1, 63
; NOVSX-NEXT: addi r1, r1, 32 ; NOVSX-NEXT: addi r1, r1, 32
; NOVSX-NEXT: ld r0, 16(r1) ; NOVSX-NEXT: ld r0, 16(r1)
; NOVSX-NEXT: mtlr r0 ; NOVSX-NEXT: mtlr r0
; NOVSX-NEXT: blr ; NOVSX-NEXT: blr
%cmp = call i1 @llvm.experimental.constrained.fcmp.f128(fp128 %a, fp128 %b, metadata !"ugt", metadata !"fpexcept.strict") #0 %cmp = call i1 @llvm.experimental.constrained.fcmp.f128(fp128 %a, fp128 %b, metadata !"ugt", metadata !"fpexcept.strict") #0
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
ret i32 %conv ret i32 %conv
} }
define i32 @fcmp_uge_f128(fp128 %a, fp128 %b) #0 { define i32 @fcmp_uge_f128(fp128 %a, fp128 %b) #0 {
; P8-LABEL: fcmp_uge_f128: ; P8-LABEL: fcmp_uge_f128:
; P8: # %bb.0: ; P8: # %bb.0:
; P8-NEXT: mflr r0 ; P8-NEXT: mflr r0
; P8-NEXT: std r0, 16(r1)
; P8-NEXT: stdu r1, -112(r1) ; P8-NEXT: stdu r1, -112(r1)
; P8-NEXT: std r0, 128(r1)
; P8-NEXT: bl __ltkf2 ; P8-NEXT: bl __ltkf2
; P8-NEXT: nop ; P8-NEXT: nop
; P8-NEXT: rlwinm r3, r3, 1, 31, 31 ; P8-NEXT: rlwinm r3, r3, 1, 31, 31
; P8-NEXT: xori r3, r3, 1 ; P8-NEXT: xori r3, r3, 1
; P8-NEXT: addi r1, r1, 112 ; P8-NEXT: addi r1, r1, 112
; P8-NEXT: ld r0, 16(r1) ; P8-NEXT: ld r0, 16(r1)
; P8-NEXT: mtlr r0 ; P8-NEXT: mtlr r0
; P8-NEXT: blr ; P8-NEXT: blr
; ;
; P9-LABEL: fcmp_uge_f128: ; P9-LABEL: fcmp_uge_f128:
; P9: # %bb.0: ; P9: # %bb.0:
; P9-NEXT: xscmpuqp cr0, v2, v3 ; P9-NEXT: xscmpuqp cr0, v2, v3
; P9-NEXT: li r3, 1 ; P9-NEXT: li r3, 1
; P9-NEXT: isellt r3, 0, r3 ; P9-NEXT: isellt r3, 0, r3
; P9-NEXT: blr ; P9-NEXT: blr
; ;
; NOVSX-LABEL: fcmp_uge_f128: ; NOVSX-LABEL: fcmp_uge_f128:
; NOVSX: # %bb.0: ; NOVSX: # %bb.0:
; NOVSX-NEXT: mflr r0 ; NOVSX-NEXT: mflr r0
; NOVSX-NEXT: std r0, 16(r1)
; NOVSX-NEXT: stdu r1, -32(r1) ; NOVSX-NEXT: stdu r1, -32(r1)
; NOVSX-NEXT: std r0, 48(r1)
; NOVSX-NEXT: bl __ltkf2 ; NOVSX-NEXT: bl __ltkf2
; NOVSX-NEXT: nop ; NOVSX-NEXT: nop
; NOVSX-NEXT: rlwinm r3, r3, 1, 31, 31 ; NOVSX-NEXT: rlwinm r3, r3, 1, 31, 31
; NOVSX-NEXT: xori r3, r3, 1 ; NOVSX-NEXT: xori r3, r3, 1
; NOVSX-NEXT: addi r1, r1, 32 ; NOVSX-NEXT: addi r1, r1, 32
; NOVSX-NEXT: ld r0, 16(r1) ; NOVSX-NEXT: ld r0, 16(r1)
; NOVSX-NEXT: mtlr r0 ; NOVSX-NEXT: mtlr r0
; NOVSX-NEXT: blr ; NOVSX-NEXT: blr
%cmp = call i1 @llvm.experimental.constrained.fcmp.f128(fp128 %a, fp128 %b, metadata !"uge", metadata !"fpexcept.strict") #0 %cmp = call i1 @llvm.experimental.constrained.fcmp.f128(fp128 %a, fp128 %b, metadata !"uge", metadata !"fpexcept.strict") #0
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
ret i32 %conv ret i32 %conv
} }
define i32 @fcmp_ueq_f128(fp128 %a, fp128 %b) #0 { define i32 @fcmp_ueq_f128(fp128 %a, fp128 %b) #0 {
; P8-LABEL: fcmp_ueq_f128: ; P8-LABEL: fcmp_ueq_f128:
; P8: # %bb.0: ; P8: # %bb.0:
; P8-NEXT: mflr r0 ; P8-NEXT: mflr r0
; P8-NEXT: std r0, 16(r1)
; P8-NEXT: stdu r1, -176(r1) ; P8-NEXT: stdu r1, -176(r1)
; P8-NEXT: li r3, 128 ; P8-NEXT: li r3, 128
; P8-NEXT: std r0, 192(r1)
; P8-NEXT: std r30, 160(r1) # 8-byte Folded Spill ; P8-NEXT: std r30, 160(r1) # 8-byte Folded Spill
; P8-NEXT: stxvd2x v30, r1, r3 # 16-byte Folded Spill ; P8-NEXT: stxvd2x v30, r1, r3 # 16-byte Folded Spill
; P8-NEXT: li r3, 144 ; P8-NEXT: li r3, 144
; P8-NEXT: vmr v30, v2 ; P8-NEXT: vmr v30, v2
; P8-NEXT: stxvd2x v31, r1, r3 # 16-byte Folded Spill ; P8-NEXT: stxvd2x v31, r1, r3 # 16-byte Folded Spill
; P8-NEXT: vmr v31, v3 ; P8-NEXT: vmr v31, v3
; P8-NEXT: bl __eqkf2 ; P8-NEXT: bl __eqkf2
; P8-NEXT: nop ; P8-NEXT: nop
Show All 28 Lines
; NOVSX-LABEL: fcmp_ueq_f128: ; NOVSX-LABEL: fcmp_ueq_f128:
; NOVSX: # %bb.0: ; NOVSX: # %bb.0:
; NOVSX-NEXT: mflr r0 ; NOVSX-NEXT: mflr r0
; NOVSX-NEXT: std r26, -48(r1) # 8-byte Folded Spill ; NOVSX-NEXT: std r26, -48(r1) # 8-byte Folded Spill
; NOVSX-NEXT: std r27, -40(r1) # 8-byte Folded Spill ; NOVSX-NEXT: std r27, -40(r1) # 8-byte Folded Spill
; NOVSX-NEXT: std r28, -32(r1) # 8-byte Folded Spill ; NOVSX-NEXT: std r28, -32(r1) # 8-byte Folded Spill
; NOVSX-NEXT: std r29, -24(r1) # 8-byte Folded Spill ; NOVSX-NEXT: std r29, -24(r1) # 8-byte Folded Spill
; NOVSX-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; NOVSX-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; NOVSX-NEXT: std r0, 16(r1)
; NOVSX-NEXT: stdu r1, -80(r1) ; NOVSX-NEXT: stdu r1, -80(r1)
; NOVSX-NEXT: std r0, 96(r1)
; NOVSX-NEXT: mr r30, r6 ; NOVSX-NEXT: mr r30, r6
; NOVSX-NEXT: mr r29, r5 ; NOVSX-NEXT: mr r29, r5
; NOVSX-NEXT: mr r28, r4 ; NOVSX-NEXT: mr r28, r4
; NOVSX-NEXT: mr r27, r3 ; NOVSX-NEXT: mr r27, r3
; NOVSX-NEXT: bl __eqkf2 ; NOVSX-NEXT: bl __eqkf2
; NOVSX-NEXT: nop ; NOVSX-NEXT: nop
; NOVSX-NEXT: cntlzw r3, r3 ; NOVSX-NEXT: cntlzw r3, r3
; NOVSX-NEXT: mr r4, r28 ; NOVSX-NEXT: mr r4, r28
Show All 20 Lines; NOVSX-NEXT: blr
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
ret i32 %conv ret i32 %conv
} }
define i32 @fcmp_une_f128(fp128 %a, fp128 %b) #0 { define i32 @fcmp_une_f128(fp128 %a, fp128 %b) #0 {
; P8-LABEL: fcmp_une_f128: ; P8-LABEL: fcmp_une_f128:
; P8: # %bb.0: ; P8: # %bb.0:
; P8-NEXT: mflr r0 ; P8-NEXT: mflr r0
; P8-NEXT: std r0, 16(r1)
; P8-NEXT: stdu r1, -112(r1) ; P8-NEXT: stdu r1, -112(r1)
; P8-NEXT: std r0, 128(r1)
; P8-NEXT: bl __nekf2 ; P8-NEXT: bl __nekf2
; P8-NEXT: nop ; P8-NEXT: nop
; P8-NEXT: cntlzw r3, r3 ; P8-NEXT: cntlzw r3, r3
; P8-NEXT: srwi r3, r3, 5 ; P8-NEXT: srwi r3, r3, 5
; P8-NEXT: xori r3, r3, 1 ; P8-NEXT: xori r3, r3, 1
; P8-NEXT: addi r1, r1, 112 ; P8-NEXT: addi r1, r1, 112
; P8-NEXT: ld r0, 16(r1) ; P8-NEXT: ld r0, 16(r1)
; P8-NEXT: mtlr r0 ; P8-NEXT: mtlr r0
; P8-NEXT: blr ; P8-NEXT: blr
; ;
; P9-LABEL: fcmp_une_f128: ; P9-LABEL: fcmp_une_f128:
; P9: # %bb.0: ; P9: # %bb.0:
; P9-NEXT: xscmpuqp cr0, v2, v3 ; P9-NEXT: xscmpuqp cr0, v2, v3
; P9-NEXT: li r3, 1 ; P9-NEXT: li r3, 1
; P9-NEXT: iseleq r3, 0, r3 ; P9-NEXT: iseleq r3, 0, r3
; P9-NEXT: blr ; P9-NEXT: blr
; ;
; NOVSX-LABEL: fcmp_une_f128: ; NOVSX-LABEL: fcmp_une_f128:
; NOVSX: # %bb.0: ; NOVSX: # %bb.0:
; NOVSX-NEXT: mflr r0 ; NOVSX-NEXT: mflr r0
; NOVSX-NEXT: std r0, 16(r1)
; NOVSX-NEXT: stdu r1, -32(r1) ; NOVSX-NEXT: stdu r1, -32(r1)
; NOVSX-NEXT: std r0, 48(r1)
; NOVSX-NEXT: bl __nekf2 ; NOVSX-NEXT: bl __nekf2
; NOVSX-NEXT: nop ; NOVSX-NEXT: nop
; NOVSX-NEXT: cntlzw r3, r3 ; NOVSX-NEXT: cntlzw r3, r3
; NOVSX-NEXT: srwi r3, r3, 5 ; NOVSX-NEXT: srwi r3, r3, 5
; NOVSX-NEXT: xori r3, r3, 1 ; NOVSX-NEXT: xori r3, r3, 1
; NOVSX-NEXT: addi r1, r1, 32 ; NOVSX-NEXT: addi r1, r1, 32
; NOVSX-NEXT: ld r0, 16(r1) ; NOVSX-NEXT: ld r0, 16(r1)
; NOVSX-NEXT: mtlr r0 ; NOVSX-NEXT: mtlr r0
; NOVSX-NEXT: blr ; NOVSX-NEXT: blr
%cmp = call i1 @llvm.experimental.constrained.fcmp.f128(fp128 %a, fp128 %b, metadata !"une", metadata !"fpexcept.strict") #0 %cmp = call i1 @llvm.experimental.constrained.fcmp.f128(fp128 %a, fp128 %b, metadata !"une", metadata !"fpexcept.strict") #0
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
ret i32 %conv ret i32 %conv
} }
define i32 @fcmps_olt_f128(fp128 %a, fp128 %b) #0 { define i32 @fcmps_olt_f128(fp128 %a, fp128 %b) #0 {
; P8-LABEL: fcmps_olt_f128: ; P8-LABEL: fcmps_olt_f128:
; P8: # %bb.0: ; P8: # %bb.0:
; P8-NEXT: mflr r0 ; P8-NEXT: mflr r0
; P8-NEXT: std r0, 16(r1)
; P8-NEXT: stdu r1, -112(r1) ; P8-NEXT: stdu r1, -112(r1)
; P8-NEXT: std r0, 128(r1)
; P8-NEXT: bl __ltkf2 ; P8-NEXT: bl __ltkf2
; P8-NEXT: nop ; P8-NEXT: nop
; P8-NEXT: rlwinm r3, r3, 1, 31, 31 ; P8-NEXT: rlwinm r3, r3, 1, 31, 31
; P8-NEXT: addi r1, r1, 112 ; P8-NEXT: addi r1, r1, 112
; P8-NEXT: ld r0, 16(r1) ; P8-NEXT: ld r0, 16(r1)
; P8-NEXT: mtlr r0 ; P8-NEXT: mtlr r0
; P8-NEXT: blr ; P8-NEXT: blr
; ;
; P9-LABEL: fcmps_olt_f128: ; P9-LABEL: fcmps_olt_f128:
; P9: # %bb.0: ; P9: # %bb.0:
; P9-NEXT: xscmpoqp cr0, v2, v3 ; P9-NEXT: xscmpoqp cr0, v2, v3
; P9-NEXT: li r3, 0 ; P9-NEXT: li r3, 0
; P9-NEXT: li r4, 1 ; P9-NEXT: li r4, 1
; P9-NEXT: isellt r3, r4, r3 ; P9-NEXT: isellt r3, r4, r3
; P9-NEXT: blr ; P9-NEXT: blr
; ;
; NOVSX-LABEL: fcmps_olt_f128: ; NOVSX-LABEL: fcmps_olt_f128:
; NOVSX: # %bb.0: ; NOVSX: # %bb.0:
; NOVSX-NEXT: mflr r0 ; NOVSX-NEXT: mflr r0
; NOVSX-NEXT: std r0, 16(r1)
; NOVSX-NEXT: stdu r1, -32(r1) ; NOVSX-NEXT: stdu r1, -32(r1)
; NOVSX-NEXT: std r0, 48(r1)
; NOVSX-NEXT: bl __ltkf2 ; NOVSX-NEXT: bl __ltkf2
; NOVSX-NEXT: nop ; NOVSX-NEXT: nop
; NOVSX-NEXT: rlwinm r3, r3, 1, 31, 31 ; NOVSX-NEXT: rlwinm r3, r3, 1, 31, 31
; NOVSX-NEXT: addi r1, r1, 32 ; NOVSX-NEXT: addi r1, r1, 32
; NOVSX-NEXT: ld r0, 16(r1) ; NOVSX-NEXT: ld r0, 16(r1)
; NOVSX-NEXT: mtlr r0 ; NOVSX-NEXT: mtlr r0
; NOVSX-NEXT: blr ; NOVSX-NEXT: blr
%cmp = call i1 @llvm.experimental.constrained.fcmps.f128(fp128 %a, fp128 %b, metadata !"olt", metadata !"fpexcept.strict") #0 %cmp = call i1 @llvm.experimental.constrained.fcmps.f128(fp128 %a, fp128 %b, metadata !"olt", metadata !"fpexcept.strict") #0
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
ret i32 %conv ret i32 %conv
} }
define i32 @fcmps_ole_f128(fp128 %a, fp128 %b) #0 { define i32 @fcmps_ole_f128(fp128 %a, fp128 %b) #0 {
; P8-LABEL: fcmps_ole_f128: ; P8-LABEL: fcmps_ole_f128:
; P8: # %bb.0: ; P8: # %bb.0:
; P8-NEXT: mflr r0 ; P8-NEXT: mflr r0
; P8-NEXT: std r0, 16(r1)
; P8-NEXT: stdu r1, -112(r1) ; P8-NEXT: stdu r1, -112(r1)
; P8-NEXT: std r0, 128(r1)
; P8-NEXT: bl __lekf2 ; P8-NEXT: bl __lekf2
; P8-NEXT: nop ; P8-NEXT: nop
; P8-NEXT: extsw r3, r3 ; P8-NEXT: extsw r3, r3
; P8-NEXT: neg r3, r3 ; P8-NEXT: neg r3, r3
; P8-NEXT: rldicl r3, r3, 1, 63 ; P8-NEXT: rldicl r3, r3, 1, 63
; P8-NEXT: xori r3, r3, 1 ; P8-NEXT: xori r3, r3, 1
; P8-NEXT: addi r1, r1, 112 ; P8-NEXT: addi r1, r1, 112
; P8-NEXT: ld r0, 16(r1) ; P8-NEXT: ld r0, 16(r1)
; P8-NEXT: mtlr r0 ; P8-NEXT: mtlr r0
; P8-NEXT: blr ; P8-NEXT: blr
; ;
; P9-LABEL: fcmps_ole_f128: ; P9-LABEL: fcmps_ole_f128:
; P9: # %bb.0: ; P9: # %bb.0:
; P9-NEXT: xscmpoqp cr0, v2, v3 ; P9-NEXT: xscmpoqp cr0, v2, v3
; P9-NEXT: li r3, 1 ; P9-NEXT: li r3, 1
; P9-NEXT: cror 4*cr5+lt, un, gt ; P9-NEXT: cror 4*cr5+lt, un, gt
; P9-NEXT: isel r3, 0, r3, 4*cr5+lt ; P9-NEXT: isel r3, 0, r3, 4*cr5+lt
; P9-NEXT: blr ; P9-NEXT: blr
; ;
; NOVSX-LABEL: fcmps_ole_f128: ; NOVSX-LABEL: fcmps_ole_f128:
; NOVSX: # %bb.0: ; NOVSX: # %bb.0:
; NOVSX-NEXT: mflr r0 ; NOVSX-NEXT: mflr r0
; NOVSX-NEXT: std r0, 16(r1)
; NOVSX-NEXT: stdu r1, -32(r1) ; NOVSX-NEXT: stdu r1, -32(r1)
; NOVSX-NEXT: std r0, 48(r1)
; NOVSX-NEXT: bl __lekf2 ; NOVSX-NEXT: bl __lekf2
; NOVSX-NEXT: nop ; NOVSX-NEXT: nop
; NOVSX-NEXT: extsw r3, r3 ; NOVSX-NEXT: extsw r3, r3
; NOVSX-NEXT: neg r3, r3 ; NOVSX-NEXT: neg r3, r3
; NOVSX-NEXT: rldicl r3, r3, 1, 63 ; NOVSX-NEXT: rldicl r3, r3, 1, 63
; NOVSX-NEXT: xori r3, r3, 1 ; NOVSX-NEXT: xori r3, r3, 1
; NOVSX-NEXT: addi r1, r1, 32 ; NOVSX-NEXT: addi r1, r1, 32
; NOVSX-NEXT: ld r0, 16(r1) ; NOVSX-NEXT: ld r0, 16(r1)
; NOVSX-NEXT: mtlr r0 ; NOVSX-NEXT: mtlr r0
; NOVSX-NEXT: blr ; NOVSX-NEXT: blr
%cmp = call i1 @llvm.experimental.constrained.fcmps.f128(fp128 %a, fp128 %b, metadata !"ole", metadata !"fpexcept.strict") #0 %cmp = call i1 @llvm.experimental.constrained.fcmps.f128(fp128 %a, fp128 %b, metadata !"ole", metadata !"fpexcept.strict") #0
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
ret i32 %conv ret i32 %conv
} }
define i32 @fcmps_ogt_f128(fp128 %a, fp128 %b) #0 { define i32 @fcmps_ogt_f128(fp128 %a, fp128 %b) #0 {
; P8-LABEL: fcmps_ogt_f128: ; P8-LABEL: fcmps_ogt_f128:
; P8: # %bb.0: ; P8: # %bb.0:
; P8-NEXT: mflr r0 ; P8-NEXT: mflr r0
; P8-NEXT: std r0, 16(r1)
; P8-NEXT: stdu r1, -112(r1) ; P8-NEXT: stdu r1, -112(r1)
; P8-NEXT: std r0, 128(r1)
; P8-NEXT: bl __gtkf2 ; P8-NEXT: bl __gtkf2
; P8-NEXT: nop ; P8-NEXT: nop
; P8-NEXT: extsw r3, r3 ; P8-NEXT: extsw r3, r3
; P8-NEXT: neg r3, r3 ; P8-NEXT: neg r3, r3
; P8-NEXT: rldicl r3, r3, 1, 63 ; P8-NEXT: rldicl r3, r3, 1, 63
; P8-NEXT: addi r1, r1, 112 ; P8-NEXT: addi r1, r1, 112
; P8-NEXT: ld r0, 16(r1) ; P8-NEXT: ld r0, 16(r1)
; P8-NEXT: mtlr r0 ; P8-NEXT: mtlr r0
; P8-NEXT: blr ; P8-NEXT: blr
; ;
; P9-LABEL: fcmps_ogt_f128: ; P9-LABEL: fcmps_ogt_f128:
; P9: # %bb.0: ; P9: # %bb.0:
; P9-NEXT: xscmpoqp cr0, v2, v3 ; P9-NEXT: xscmpoqp cr0, v2, v3
; P9-NEXT: li r3, 0 ; P9-NEXT: li r3, 0
; P9-NEXT: li r4, 1 ; P9-NEXT: li r4, 1
; P9-NEXT: iselgt r3, r4, r3 ; P9-NEXT: iselgt r3, r4, r3
; P9-NEXT: blr ; P9-NEXT: blr
; ;
; NOVSX-LABEL: fcmps_ogt_f128: ; NOVSX-LABEL: fcmps_ogt_f128:
; NOVSX: # %bb.0: ; NOVSX: # %bb.0:
; NOVSX-NEXT: mflr r0 ; NOVSX-NEXT: mflr r0
; NOVSX-NEXT: std r0, 16(r1)
; NOVSX-NEXT: stdu r1, -32(r1) ; NOVSX-NEXT: stdu r1, -32(r1)
; NOVSX-NEXT: std r0, 48(r1)
; NOVSX-NEXT: bl __gtkf2 ; NOVSX-NEXT: bl __gtkf2
; NOVSX-NEXT: nop ; NOVSX-NEXT: nop
; NOVSX-NEXT: extsw r3, r3 ; NOVSX-NEXT: extsw r3, r3
; NOVSX-NEXT: neg r3, r3 ; NOVSX-NEXT: neg r3, r3
; NOVSX-NEXT: rldicl r3, r3, 1, 63 ; NOVSX-NEXT: rldicl r3, r3, 1, 63
; NOVSX-NEXT: addi r1, r1, 32 ; NOVSX-NEXT: addi r1, r1, 32
; NOVSX-NEXT: ld r0, 16(r1) ; NOVSX-NEXT: ld r0, 16(r1)
; NOVSX-NEXT: mtlr r0 ; NOVSX-NEXT: mtlr r0
; NOVSX-NEXT: blr ; NOVSX-NEXT: blr
%cmp = call i1 @llvm.experimental.constrained.fcmps.f128(fp128 %a, fp128 %b, metadata !"ogt", metadata !"fpexcept.strict") #0 %cmp = call i1 @llvm.experimental.constrained.fcmps.f128(fp128 %a, fp128 %b, metadata !"ogt", metadata !"fpexcept.strict") #0
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
ret i32 %conv ret i32 %conv
} }
define i32 @fcmps_oge_f128(fp128 %a, fp128 %b) #0 { define i32 @fcmps_oge_f128(fp128 %a, fp128 %b) #0 {
; P8-LABEL: fcmps_oge_f128: ; P8-LABEL: fcmps_oge_f128:
; P8: # %bb.0: ; P8: # %bb.0:
; P8-NEXT: mflr r0 ; P8-NEXT: mflr r0
; P8-NEXT: std r0, 16(r1)
; P8-NEXT: stdu r1, -112(r1) ; P8-NEXT: stdu r1, -112(r1)
; P8-NEXT: std r0, 128(r1)
; P8-NEXT: bl __gekf2 ; P8-NEXT: bl __gekf2
; P8-NEXT: nop ; P8-NEXT: nop
; P8-NEXT: rlwinm r3, r3, 1, 31, 31 ; P8-NEXT: rlwinm r3, r3, 1, 31, 31
; P8-NEXT: xori r3, r3, 1 ; P8-NEXT: xori r3, r3, 1
; P8-NEXT: addi r1, r1, 112 ; P8-NEXT: addi r1, r1, 112
; P8-NEXT: ld r0, 16(r1) ; P8-NEXT: ld r0, 16(r1)
; P8-NEXT: mtlr r0 ; P8-NEXT: mtlr r0
; P8-NEXT: blr ; P8-NEXT: blr
; ;
; P9-LABEL: fcmps_oge_f128: ; P9-LABEL: fcmps_oge_f128:
; P9: # %bb.0: ; P9: # %bb.0:
; P9-NEXT: xscmpoqp cr0, v2, v3 ; P9-NEXT: xscmpoqp cr0, v2, v3
; P9-NEXT: li r3, 1 ; P9-NEXT: li r3, 1
; P9-NEXT: cror 4*cr5+lt, un, lt ; P9-NEXT: cror 4*cr5+lt, un, lt
; P9-NEXT: isel r3, 0, r3, 4*cr5+lt ; P9-NEXT: isel r3, 0, r3, 4*cr5+lt
; P9-NEXT: blr ; P9-NEXT: blr
; ;
; NOVSX-LABEL: fcmps_oge_f128: ; NOVSX-LABEL: fcmps_oge_f128:
; NOVSX: # %bb.0: ; NOVSX: # %bb.0:
; NOVSX-NEXT: mflr r0 ; NOVSX-NEXT: mflr r0
; NOVSX-NEXT: std r0, 16(r1)
; NOVSX-NEXT: stdu r1, -32(r1) ; NOVSX-NEXT: stdu r1, -32(r1)
; NOVSX-NEXT: std r0, 48(r1)
; NOVSX-NEXT: bl __gekf2 ; NOVSX-NEXT: bl __gekf2
; NOVSX-NEXT: nop ; NOVSX-NEXT: nop
; NOVSX-NEXT: rlwinm r3, r3, 1, 31, 31 ; NOVSX-NEXT: rlwinm r3, r3, 1, 31, 31
; NOVSX-NEXT: xori r3, r3, 1 ; NOVSX-NEXT: xori r3, r3, 1
; NOVSX-NEXT: addi r1, r1, 32 ; NOVSX-NEXT: addi r1, r1, 32
; NOVSX-NEXT: ld r0, 16(r1) ; NOVSX-NEXT: ld r0, 16(r1)
; NOVSX-NEXT: mtlr r0 ; NOVSX-NEXT: mtlr r0
; NOVSX-NEXT: blr ; NOVSX-NEXT: blr
%cmp = call i1 @llvm.experimental.constrained.fcmps.f128(fp128 %a, fp128 %b, metadata !"oge", metadata !"fpexcept.strict") #0 %cmp = call i1 @llvm.experimental.constrained.fcmps.f128(fp128 %a, fp128 %b, metadata !"oge", metadata !"fpexcept.strict") #0
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
ret i32 %conv ret i32 %conv
} }
define i32 @fcmps_oeq_f128(fp128 %a, fp128 %b) #0 { define i32 @fcmps_oeq_f128(fp128 %a, fp128 %b) #0 {
; P8-LABEL: fcmps_oeq_f128: ; P8-LABEL: fcmps_oeq_f128:
; P8: # %bb.0: ; P8: # %bb.0:
; P8-NEXT: mflr r0 ; P8-NEXT: mflr r0
; P8-NEXT: std r0, 16(r1)
; P8-NEXT: stdu r1, -112(r1) ; P8-NEXT: stdu r1, -112(r1)
; P8-NEXT: std r0, 128(r1)
; P8-NEXT: bl __eqkf2 ; P8-NEXT: bl __eqkf2
; P8-NEXT: nop ; P8-NEXT: nop
; P8-NEXT: cntlzw r3, r3 ; P8-NEXT: cntlzw r3, r3
; P8-NEXT: srwi r3, r3, 5 ; P8-NEXT: srwi r3, r3, 5
; P8-NEXT: addi r1, r1, 112 ; P8-NEXT: addi r1, r1, 112
; P8-NEXT: ld r0, 16(r1) ; P8-NEXT: ld r0, 16(r1)
; P8-NEXT: mtlr r0 ; P8-NEXT: mtlr r0
; P8-NEXT: blr ; P8-NEXT: blr
; ;
; P9-LABEL: fcmps_oeq_f128: ; P9-LABEL: fcmps_oeq_f128:
; P9: # %bb.0: ; P9: # %bb.0:
; P9-NEXT: xscmpoqp cr0, v2, v3 ; P9-NEXT: xscmpoqp cr0, v2, v3
; P9-NEXT: li r3, 0 ; P9-NEXT: li r3, 0
; P9-NEXT: li r4, 1 ; P9-NEXT: li r4, 1
; P9-NEXT: iseleq r3, r4, r3 ; P9-NEXT: iseleq r3, r4, r3
; P9-NEXT: blr ; P9-NEXT: blr
; ;
; NOVSX-LABEL: fcmps_oeq_f128: ; NOVSX-LABEL: fcmps_oeq_f128:
; NOVSX: # %bb.0: ; NOVSX: # %bb.0:
; NOVSX-NEXT: mflr r0 ; NOVSX-NEXT: mflr r0
; NOVSX-NEXT: std r0, 16(r1)
; NOVSX-NEXT: stdu r1, -32(r1) ; NOVSX-NEXT: stdu r1, -32(r1)
; NOVSX-NEXT: std r0, 48(r1)
; NOVSX-NEXT: bl __eqkf2 ; NOVSX-NEXT: bl __eqkf2
; NOVSX-NEXT: nop ; NOVSX-NEXT: nop
; NOVSX-NEXT: cntlzw r3, r3 ; NOVSX-NEXT: cntlzw r3, r3
; NOVSX-NEXT: srwi r3, r3, 5 ; NOVSX-NEXT: srwi r3, r3, 5
; NOVSX-NEXT: addi r1, r1, 32 ; NOVSX-NEXT: addi r1, r1, 32
; NOVSX-NEXT: ld r0, 16(r1) ; NOVSX-NEXT: ld r0, 16(r1)
; NOVSX-NEXT: mtlr r0 ; NOVSX-NEXT: mtlr r0
; NOVSX-NEXT: blr ; NOVSX-NEXT: blr
%cmp = call i1 @llvm.experimental.constrained.fcmps.f128(fp128 %a, fp128 %b, metadata !"oeq", metadata !"fpexcept.strict") #0 %cmp = call i1 @llvm.experimental.constrained.fcmps.f128(fp128 %a, fp128 %b, metadata !"oeq", metadata !"fpexcept.strict") #0
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
ret i32 %conv ret i32 %conv
} }
define i32 @fcmps_one_f128(fp128 %a, fp128 %b) #0 { define i32 @fcmps_one_f128(fp128 %a, fp128 %b) #0 {
; P8-LABEL: fcmps_one_f128: ; P8-LABEL: fcmps_one_f128:
; P8: # %bb.0: ; P8: # %bb.0:
; P8-NEXT: mflr r0 ; P8-NEXT: mflr r0
; P8-NEXT: std r0, 16(r1)
; P8-NEXT: stdu r1, -176(r1) ; P8-NEXT: stdu r1, -176(r1)
; P8-NEXT: li r3, 128 ; P8-NEXT: li r3, 128
; P8-NEXT: std r0, 192(r1)
; P8-NEXT: std r30, 160(r1) # 8-byte Folded Spill ; P8-NEXT: std r30, 160(r1) # 8-byte Folded Spill
; P8-NEXT: stxvd2x v30, r1, r3 # 16-byte Folded Spill ; P8-NEXT: stxvd2x v30, r1, r3 # 16-byte Folded Spill
; P8-NEXT: li r3, 144 ; P8-NEXT: li r3, 144
; P8-NEXT: vmr v30, v2 ; P8-NEXT: vmr v30, v2
; P8-NEXT: stxvd2x v31, r1, r3 # 16-byte Folded Spill ; P8-NEXT: stxvd2x v31, r1, r3 # 16-byte Folded Spill
; P8-NEXT: vmr v31, v3 ; P8-NEXT: vmr v31, v3
; P8-NEXT: bl __unordkf2 ; P8-NEXT: bl __unordkf2
; P8-NEXT: nop ; P8-NEXT: nop
Show All 28 Lines
; NOVSX-LABEL: fcmps_one_f128: ; NOVSX-LABEL: fcmps_one_f128:
; NOVSX: # %bb.0: ; NOVSX: # %bb.0:
; NOVSX-NEXT: mflr r0 ; NOVSX-NEXT: mflr r0
; NOVSX-NEXT: std r26, -48(r1) # 8-byte Folded Spill ; NOVSX-NEXT: std r26, -48(r1) # 8-byte Folded Spill
; NOVSX-NEXT: std r27, -40(r1) # 8-byte Folded Spill ; NOVSX-NEXT: std r27, -40(r1) # 8-byte Folded Spill
; NOVSX-NEXT: std r28, -32(r1) # 8-byte Folded Spill ; NOVSX-NEXT: std r28, -32(r1) # 8-byte Folded Spill
; NOVSX-NEXT: std r29, -24(r1) # 8-byte Folded Spill ; NOVSX-NEXT: std r29, -24(r1) # 8-byte Folded Spill
; NOVSX-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; NOVSX-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; NOVSX-NEXT: std r0, 16(r1)
; NOVSX-NEXT: stdu r1, -80(r1) ; NOVSX-NEXT: stdu r1, -80(r1)
; NOVSX-NEXT: std r0, 96(r1)
; NOVSX-NEXT: mr r30, r6 ; NOVSX-NEXT: mr r30, r6
; NOVSX-NEXT: mr r29, r5 ; NOVSX-NEXT: mr r29, r5
; NOVSX-NEXT: mr r28, r4 ; NOVSX-NEXT: mr r28, r4
; NOVSX-NEXT: mr r27, r3 ; NOVSX-NEXT: mr r27, r3
; NOVSX-NEXT: bl __unordkf2 ; NOVSX-NEXT: bl __unordkf2
; NOVSX-NEXT: nop ; NOVSX-NEXT: nop
; NOVSX-NEXT: cntlzw r3, r3 ; NOVSX-NEXT: cntlzw r3, r3
; NOVSX-NEXT: mr r4, r28 ; NOVSX-NEXT: mr r4, r28
Show All 20 Lines; NOVSX-NEXT: blr
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
ret i32 %conv ret i32 %conv
} }
define i32 @fcmps_ult_f128(fp128 %a, fp128 %b) #0 { define i32 @fcmps_ult_f128(fp128 %a, fp128 %b) #0 {
; P8-LABEL: fcmps_ult_f128: ; P8-LABEL: fcmps_ult_f128:
; P8: # %bb.0: ; P8: # %bb.0:
; P8-NEXT: mflr r0 ; P8-NEXT: mflr r0
; P8-NEXT: std r0, 16(r1)
; P8-NEXT: stdu r1, -112(r1) ; P8-NEXT: stdu r1, -112(r1)
; P8-NEXT: std r0, 128(r1)
; P8-NEXT: bl __gekf2 ; P8-NEXT: bl __gekf2
; P8-NEXT: nop ; P8-NEXT: nop
; P8-NEXT: rlwinm r3, r3, 1, 31, 31 ; P8-NEXT: rlwinm r3, r3, 1, 31, 31
; P8-NEXT: addi r1, r1, 112 ; P8-NEXT: addi r1, r1, 112
; P8-NEXT: ld r0, 16(r1) ; P8-NEXT: ld r0, 16(r1)
; P8-NEXT: mtlr r0 ; P8-NEXT: mtlr r0
; P8-NEXT: blr ; P8-NEXT: blr
; ;
; P9-LABEL: fcmps_ult_f128: ; P9-LABEL: fcmps_ult_f128:
; P9: # %bb.0: ; P9: # %bb.0:
; P9-NEXT: xscmpoqp cr0, v2, v3 ; P9-NEXT: xscmpoqp cr0, v2, v3
; P9-NEXT: li r3, 1 ; P9-NEXT: li r3, 1
; P9-NEXT: crnor 4*cr5+lt, lt, un ; P9-NEXT: crnor 4*cr5+lt, lt, un
; P9-NEXT: isel r3, 0, r3, 4*cr5+lt ; P9-NEXT: isel r3, 0, r3, 4*cr5+lt
; P9-NEXT: blr ; P9-NEXT: blr
; ;
; NOVSX-LABEL: fcmps_ult_f128: ; NOVSX-LABEL: fcmps_ult_f128:
; NOVSX: # %bb.0: ; NOVSX: # %bb.0:
; NOVSX-NEXT: mflr r0 ; NOVSX-NEXT: mflr r0
; NOVSX-NEXT: std r0, 16(r1)
; NOVSX-NEXT: stdu r1, -32(r1) ; NOVSX-NEXT: stdu r1, -32(r1)
; NOVSX-NEXT: std r0, 48(r1)
; NOVSX-NEXT: bl __gekf2 ; NOVSX-NEXT: bl __gekf2
; NOVSX-NEXT: nop ; NOVSX-NEXT: nop
; NOVSX-NEXT: rlwinm r3, r3, 1, 31, 31 ; NOVSX-NEXT: rlwinm r3, r3, 1, 31, 31
; NOVSX-NEXT: addi r1, r1, 32 ; NOVSX-NEXT: addi r1, r1, 32
; NOVSX-NEXT: ld r0, 16(r1) ; NOVSX-NEXT: ld r0, 16(r1)
; NOVSX-NEXT: mtlr r0 ; NOVSX-NEXT: mtlr r0
; NOVSX-NEXT: blr ; NOVSX-NEXT: blr
%cmp = call i1 @llvm.experimental.constrained.fcmps.f128(fp128 %a, fp128 %b, metadata !"ult", metadata !"fpexcept.strict") #0 %cmp = call i1 @llvm.experimental.constrained.fcmps.f128(fp128 %a, fp128 %b, metadata !"ult", metadata !"fpexcept.strict") #0
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
ret i32 %conv ret i32 %conv
} }
define i32 @fcmps_ule_f128(fp128 %a, fp128 %b) #0 { define i32 @fcmps_ule_f128(fp128 %a, fp128 %b) #0 {
; P8-LABEL: fcmps_ule_f128: ; P8-LABEL: fcmps_ule_f128:
; P8: # %bb.0: ; P8: # %bb.0:
; P8-NEXT: mflr r0 ; P8-NEXT: mflr r0
; P8-NEXT: std r0, 16(r1)
; P8-NEXT: stdu r1, -112(r1) ; P8-NEXT: stdu r1, -112(r1)
; P8-NEXT: std r0, 128(r1)
; P8-NEXT: bl __gtkf2 ; P8-NEXT: bl __gtkf2
; P8-NEXT: nop ; P8-NEXT: nop
; P8-NEXT: extsw r3, r3 ; P8-NEXT: extsw r3, r3
; P8-NEXT: neg r3, r3 ; P8-NEXT: neg r3, r3
; P8-NEXT: rldicl r3, r3, 1, 63 ; P8-NEXT: rldicl r3, r3, 1, 63
; P8-NEXT: xori r3, r3, 1 ; P8-NEXT: xori r3, r3, 1
; P8-NEXT: addi r1, r1, 112 ; P8-NEXT: addi r1, r1, 112
; P8-NEXT: ld r0, 16(r1) ; P8-NEXT: ld r0, 16(r1)
; P8-NEXT: mtlr r0 ; P8-NEXT: mtlr r0
; P8-NEXT: blr ; P8-NEXT: blr
; ;
; P9-LABEL: fcmps_ule_f128: ; P9-LABEL: fcmps_ule_f128:
; P9: # %bb.0: ; P9: # %bb.0:
; P9-NEXT: xscmpoqp cr0, v2, v3 ; P9-NEXT: xscmpoqp cr0, v2, v3
; P9-NEXT: li r3, 1 ; P9-NEXT: li r3, 1
; P9-NEXT: iselgt r3, 0, r3 ; P9-NEXT: iselgt r3, 0, r3
; P9-NEXT: blr ; P9-NEXT: blr
; ;
; NOVSX-LABEL: fcmps_ule_f128: ; NOVSX-LABEL: fcmps_ule_f128:
; NOVSX: # %bb.0: ; NOVSX: # %bb.0:
; NOVSX-NEXT: mflr r0 ; NOVSX-NEXT: mflr r0
; NOVSX-NEXT: std r0, 16(r1)
; NOVSX-NEXT: stdu r1, -32(r1) ; NOVSX-NEXT: stdu r1, -32(r1)
; NOVSX-NEXT: std r0, 48(r1)
; NOVSX-NEXT: bl __gtkf2 ; NOVSX-NEXT: bl __gtkf2
; NOVSX-NEXT: nop ; NOVSX-NEXT: nop
; NOVSX-NEXT: extsw r3, r3 ; NOVSX-NEXT: extsw r3, r3
; NOVSX-NEXT: neg r3, r3 ; NOVSX-NEXT: neg r3, r3
; NOVSX-NEXT: rldicl r3, r3, 1, 63 ; NOVSX-NEXT: rldicl r3, r3, 1, 63
; NOVSX-NEXT: xori r3, r3, 1 ; NOVSX-NEXT: xori r3, r3, 1
; NOVSX-NEXT: addi r1, r1, 32 ; NOVSX-NEXT: addi r1, r1, 32
; NOVSX-NEXT: ld r0, 16(r1) ; NOVSX-NEXT: ld r0, 16(r1)
; NOVSX-NEXT: mtlr r0 ; NOVSX-NEXT: mtlr r0
; NOVSX-NEXT: blr ; NOVSX-NEXT: blr
%cmp = call i1 @llvm.experimental.constrained.fcmps.f128(fp128 %a, fp128 %b, metadata !"ule", metadata !"fpexcept.strict") #0 %cmp = call i1 @llvm.experimental.constrained.fcmps.f128(fp128 %a, fp128 %b, metadata !"ule", metadata !"fpexcept.strict") #0
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
ret i32 %conv ret i32 %conv
} }
define i32 @fcmps_ugt_f128(fp128 %a, fp128 %b) #0 { define i32 @fcmps_ugt_f128(fp128 %a, fp128 %b) #0 {
; P8-LABEL: fcmps_ugt_f128: ; P8-LABEL: fcmps_ugt_f128:
; P8: # %bb.0: ; P8: # %bb.0:
; P8-NEXT: mflr r0 ; P8-NEXT: mflr r0
; P8-NEXT: std r0, 16(r1)
; P8-NEXT: stdu r1, -112(r1) ; P8-NEXT: stdu r1, -112(r1)
; P8-NEXT: std r0, 128(r1)
; P8-NEXT: bl __lekf2 ; P8-NEXT: bl __lekf2
; P8-NEXT: nop ; P8-NEXT: nop
; P8-NEXT: extsw r3, r3 ; P8-NEXT: extsw r3, r3
; P8-NEXT: neg r3, r3 ; P8-NEXT: neg r3, r3
; P8-NEXT: rldicl r3, r3, 1, 63 ; P8-NEXT: rldicl r3, r3, 1, 63
; P8-NEXT: addi r1, r1, 112 ; P8-NEXT: addi r1, r1, 112
; P8-NEXT: ld r0, 16(r1) ; P8-NEXT: ld r0, 16(r1)
; P8-NEXT: mtlr r0 ; P8-NEXT: mtlr r0
; P8-NEXT: blr ; P8-NEXT: blr
; ;
; P9-LABEL: fcmps_ugt_f128: ; P9-LABEL: fcmps_ugt_f128:
; P9: # %bb.0: ; P9: # %bb.0:
; P9-NEXT: xscmpoqp cr0, v2, v3 ; P9-NEXT: xscmpoqp cr0, v2, v3
; P9-NEXT: li r3, 1 ; P9-NEXT: li r3, 1
; P9-NEXT: crnor 4*cr5+lt, gt, un ; P9-NEXT: crnor 4*cr5+lt, gt, un
; P9-NEXT: isel r3, 0, r3, 4*cr5+lt ; P9-NEXT: isel r3, 0, r3, 4*cr5+lt
; P9-NEXT: blr ; P9-NEXT: blr
; ;
; NOVSX-LABEL: fcmps_ugt_f128: ; NOVSX-LABEL: fcmps_ugt_f128:
; NOVSX: # %bb.0: ; NOVSX: # %bb.0:
; NOVSX-NEXT: mflr r0 ; NOVSX-NEXT: mflr r0
; NOVSX-NEXT: std r0, 16(r1)
; NOVSX-NEXT: stdu r1, -32(r1) ; NOVSX-NEXT: stdu r1, -32(r1)
; NOVSX-NEXT: std r0, 48(r1)
; NOVSX-NEXT: bl __lekf2 ; NOVSX-NEXT: bl __lekf2
; NOVSX-NEXT: nop ; NOVSX-NEXT: nop
; NOVSX-NEXT: extsw r3, r3 ; NOVSX-NEXT: extsw r3, r3
; NOVSX-NEXT: neg r3, r3 ; NOVSX-NEXT: neg r3, r3
; NOVSX-NEXT: rldicl r3, r3, 1, 63 ; NOVSX-NEXT: rldicl r3, r3, 1, 63
; NOVSX-NEXT: addi r1, r1, 32 ; NOVSX-NEXT: addi r1, r1, 32
; NOVSX-NEXT: ld r0, 16(r1) ; NOVSX-NEXT: ld r0, 16(r1)
; NOVSX-NEXT: mtlr r0 ; NOVSX-NEXT: mtlr r0
; NOVSX-NEXT: blr ; NOVSX-NEXT: blr
%cmp = call i1 @llvm.experimental.constrained.fcmps.f128(fp128 %a, fp128 %b, metadata !"ugt", metadata !"fpexcept.strict") #0 %cmp = call i1 @llvm.experimental.constrained.fcmps.f128(fp128 %a, fp128 %b, metadata !"ugt", metadata !"fpexcept.strict") #0
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
ret i32 %conv ret i32 %conv
} }
define i32 @fcmps_uge_f128(fp128 %a, fp128 %b) #0 { define i32 @fcmps_uge_f128(fp128 %a, fp128 %b) #0 {
; P8-LABEL: fcmps_uge_f128: ; P8-LABEL: fcmps_uge_f128:
; P8: # %bb.0: ; P8: # %bb.0:
; P8-NEXT: mflr r0 ; P8-NEXT: mflr r0
; P8-NEXT: std r0, 16(r1)
; P8-NEXT: stdu r1, -112(r1) ; P8-NEXT: stdu r1, -112(r1)
; P8-NEXT: std r0, 128(r1)
; P8-NEXT: bl __ltkf2 ; P8-NEXT: bl __ltkf2
; P8-NEXT: nop ; P8-NEXT: nop
; P8-NEXT: rlwinm r3, r3, 1, 31, 31 ; P8-NEXT: rlwinm r3, r3, 1, 31, 31
; P8-NEXT: xori r3, r3, 1 ; P8-NEXT: xori r3, r3, 1
; P8-NEXT: addi r1, r1, 112 ; P8-NEXT: addi r1, r1, 112
; P8-NEXT: ld r0, 16(r1) ; P8-NEXT: ld r0, 16(r1)
; P8-NEXT: mtlr r0 ; P8-NEXT: mtlr r0
; P8-NEXT: blr ; P8-NEXT: blr
; ;
; P9-LABEL: fcmps_uge_f128: ; P9-LABEL: fcmps_uge_f128:
; P9: # %bb.0: ; P9: # %bb.0:
; P9-NEXT: xscmpoqp cr0, v2, v3 ; P9-NEXT: xscmpoqp cr0, v2, v3
; P9-NEXT: li r3, 1 ; P9-NEXT: li r3, 1
; P9-NEXT: isellt r3, 0, r3 ; P9-NEXT: isellt r3, 0, r3
; P9-NEXT: blr ; P9-NEXT: blr
; ;
; NOVSX-LABEL: fcmps_uge_f128: ; NOVSX-LABEL: fcmps_uge_f128:
; NOVSX: # %bb.0: ; NOVSX: # %bb.0:
; NOVSX-NEXT: mflr r0 ; NOVSX-NEXT: mflr r0
; NOVSX-NEXT: std r0, 16(r1)
; NOVSX-NEXT: stdu r1, -32(r1) ; NOVSX-NEXT: stdu r1, -32(r1)
; NOVSX-NEXT: std r0, 48(r1)
; NOVSX-NEXT: bl __ltkf2 ; NOVSX-NEXT: bl __ltkf2
; NOVSX-NEXT: nop ; NOVSX-NEXT: nop
; NOVSX-NEXT: rlwinm r3, r3, 1, 31, 31 ; NOVSX-NEXT: rlwinm r3, r3, 1, 31, 31
; NOVSX-NEXT: xori r3, r3, 1 ; NOVSX-NEXT: xori r3, r3, 1
; NOVSX-NEXT: addi r1, r1, 32 ; NOVSX-NEXT: addi r1, r1, 32
; NOVSX-NEXT: ld r0, 16(r1) ; NOVSX-NEXT: ld r0, 16(r1)
; NOVSX-NEXT: mtlr r0 ; NOVSX-NEXT: mtlr r0
; NOVSX-NEXT: blr ; NOVSX-NEXT: blr
%cmp = call i1 @llvm.experimental.constrained.fcmps.f128(fp128 %a, fp128 %b, metadata !"uge", metadata !"fpexcept.strict") #0 %cmp = call i1 @llvm.experimental.constrained.fcmps.f128(fp128 %a, fp128 %b, metadata !"uge", metadata !"fpexcept.strict") #0
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
ret i32 %conv ret i32 %conv
} }
define i32 @fcmps_ueq_f128(fp128 %a, fp128 %b) #0 { define i32 @fcmps_ueq_f128(fp128 %a, fp128 %b) #0 {
; P8-LABEL: fcmps_ueq_f128: ; P8-LABEL: fcmps_ueq_f128:
; P8: # %bb.0: ; P8: # %bb.0:
; P8-NEXT: mflr r0 ; P8-NEXT: mflr r0
; P8-NEXT: std r0, 16(r1)
; P8-NEXT: stdu r1, -176(r1) ; P8-NEXT: stdu r1, -176(r1)
; P8-NEXT: li r3, 128 ; P8-NEXT: li r3, 128
; P8-NEXT: std r0, 192(r1)
; P8-NEXT: std r30, 160(r1) # 8-byte Folded Spill ; P8-NEXT: std r30, 160(r1) # 8-byte Folded Spill
; P8-NEXT: stxvd2x v30, r1, r3 # 16-byte Folded Spill ; P8-NEXT: stxvd2x v30, r1, r3 # 16-byte Folded Spill
; P8-NEXT: li r3, 144 ; P8-NEXT: li r3, 144
; P8-NEXT: vmr v30, v2 ; P8-NEXT: vmr v30, v2
; P8-NEXT: stxvd2x v31, r1, r3 # 16-byte Folded Spill ; P8-NEXT: stxvd2x v31, r1, r3 # 16-byte Folded Spill
; P8-NEXT: vmr v31, v3 ; P8-NEXT: vmr v31, v3
; P8-NEXT: bl __eqkf2 ; P8-NEXT: bl __eqkf2
; P8-NEXT: nop ; P8-NEXT: nop
Show All 28 Lines
; NOVSX-LABEL: fcmps_ueq_f128: ; NOVSX-LABEL: fcmps_ueq_f128:
; NOVSX: # %bb.0: ; NOVSX: # %bb.0:
; NOVSX-NEXT: mflr r0 ; NOVSX-NEXT: mflr r0
; NOVSX-NEXT: std r26, -48(r1) # 8-byte Folded Spill ; NOVSX-NEXT: std r26, -48(r1) # 8-byte Folded Spill
; NOVSX-NEXT: std r27, -40(r1) # 8-byte Folded Spill ; NOVSX-NEXT: std r27, -40(r1) # 8-byte Folded Spill
; NOVSX-NEXT: std r28, -32(r1) # 8-byte Folded Spill ; NOVSX-NEXT: std r28, -32(r1) # 8-byte Folded Spill
; NOVSX-NEXT: std r29, -24(r1) # 8-byte Folded Spill ; NOVSX-NEXT: std r29, -24(r1) # 8-byte Folded Spill
; NOVSX-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; NOVSX-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; NOVSX-NEXT: std r0, 16(r1)
; NOVSX-NEXT: stdu r1, -80(r1) ; NOVSX-NEXT: stdu r1, -80(r1)
; NOVSX-NEXT: std r0, 96(r1)
; NOVSX-NEXT: mr r30, r6 ; NOVSX-NEXT: mr r30, r6
; NOVSX-NEXT: mr r29, r5 ; NOVSX-NEXT: mr r29, r5
; NOVSX-NEXT: mr r28, r4 ; NOVSX-NEXT: mr r28, r4
; NOVSX-NEXT: mr r27, r3 ; NOVSX-NEXT: mr r27, r3
; NOVSX-NEXT: bl __eqkf2 ; NOVSX-NEXT: bl __eqkf2
; NOVSX-NEXT: nop ; NOVSX-NEXT: nop
; NOVSX-NEXT: cntlzw r3, r3 ; NOVSX-NEXT: cntlzw r3, r3
; NOVSX-NEXT: mr r4, r28 ; NOVSX-NEXT: mr r4, r28
Show All 20 Lines; NOVSX-NEXT: blr
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
ret i32 %conv ret i32 %conv
} }
define i32 @fcmps_une_f128(fp128 %a, fp128 %b) #0 { define i32 @fcmps_une_f128(fp128 %a, fp128 %b) #0 {
; P8-LABEL: fcmps_une_f128: ; P8-LABEL: fcmps_une_f128:
; P8: # %bb.0: ; P8: # %bb.0:
; P8-NEXT: mflr r0 ; P8-NEXT: mflr r0
; P8-NEXT: std r0, 16(r1)
; P8-NEXT: stdu r1, -112(r1) ; P8-NEXT: stdu r1, -112(r1)
; P8-NEXT: std r0, 128(r1)
; P8-NEXT: bl __nekf2 ; P8-NEXT: bl __nekf2
; P8-NEXT: nop ; P8-NEXT: nop
; P8-NEXT: cntlzw r3, r3 ; P8-NEXT: cntlzw r3, r3
; P8-NEXT: srwi r3, r3, 5 ; P8-NEXT: srwi r3, r3, 5
; P8-NEXT: xori r3, r3, 1 ; P8-NEXT: xori r3, r3, 1
; P8-NEXT: addi r1, r1, 112 ; P8-NEXT: addi r1, r1, 112
; P8-NEXT: ld r0, 16(r1) ; P8-NEXT: ld r0, 16(r1)
; P8-NEXT: mtlr r0 ; P8-NEXT: mtlr r0
; P8-NEXT: blr ; P8-NEXT: blr
; ;
; P9-LABEL: fcmps_une_f128: ; P9-LABEL: fcmps_une_f128:
; P9: # %bb.0: ; P9: # %bb.0:
; P9-NEXT: xscmpoqp cr0, v2, v3 ; P9-NEXT: xscmpoqp cr0, v2, v3
; P9-NEXT: li r3, 1 ; P9-NEXT: li r3, 1
; P9-NEXT: iseleq r3, 0, r3 ; P9-NEXT: iseleq r3, 0, r3
; P9-NEXT: blr ; P9-NEXT: blr
; ;
; NOVSX-LABEL: fcmps_une_f128: ; NOVSX-LABEL: fcmps_une_f128:
; NOVSX: # %bb.0: ; NOVSX: # %bb.0:
; NOVSX-NEXT: mflr r0 ; NOVSX-NEXT: mflr r0
; NOVSX-NEXT: std r0, 16(r1)
; NOVSX-NEXT: stdu r1, -32(r1) ; NOVSX-NEXT: stdu r1, -32(r1)
; NOVSX-NEXT: std r0, 48(r1)
; NOVSX-NEXT: bl __nekf2 ; NOVSX-NEXT: bl __nekf2
; NOVSX-NEXT: nop ; NOVSX-NEXT: nop
; NOVSX-NEXT: cntlzw r3, r3 ; NOVSX-NEXT: cntlzw r3, r3
; NOVSX-NEXT: srwi r3, r3, 5 ; NOVSX-NEXT: srwi r3, r3, 5
; NOVSX-NEXT: xori r3, r3, 1 ; NOVSX-NEXT: xori r3, r3, 1
; NOVSX-NEXT: addi r1, r1, 32 ; NOVSX-NEXT: addi r1, r1, 32
; NOVSX-NEXT: ld r0, 16(r1) ; NOVSX-NEXT: ld r0, 16(r1)
; NOVSX-NEXT: mtlr r0 ; NOVSX-NEXT: mtlr r0
▲ Show 20 Lines • Show All 994 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/fp-strict-round.ll

Show First 20 Lines • Show All 165 Lines • ▼ Show 20 Lines %res = call <2 x double> @llvm.experimental.constrained.floor.v2f64(
metadata !"fpexcept.strict") metadata !"fpexcept.strict")
ret <2 x double> %res; ret <2 x double> %res;
} }
define double @nearbyint_f64(double %f1, double %f2) { define double @nearbyint_f64(double %f1, double %f2) {
; P8-LABEL: nearbyint_f64: ; P8-LABEL: nearbyint_f64:
; P8: # %bb.0: ; P8: # %bb.0:
; P8-NEXT: mflr r0 ; P8-NEXT: mflr r0
; P8-NEXT: std r0, 16(r1)
; P8-NEXT: stdu r1, -112(r1) ; P8-NEXT: stdu r1, -112(r1)
; P8-NEXT: std r0, 128(r1)
; P8-NEXT: .cfi_def_cfa_offset 112 ; P8-NEXT: .cfi_def_cfa_offset 112
; P8-NEXT: .cfi_offset lr, 16 ; P8-NEXT: .cfi_offset lr, 16
; P8-NEXT: bl nearbyint ; P8-NEXT: bl nearbyint
; P8-NEXT: nop ; P8-NEXT: nop
; P8-NEXT: addi r1, r1, 112 ; P8-NEXT: addi r1, r1, 112
; P8-NEXT: ld r0, 16(r1) ; P8-NEXT: ld r0, 16(r1)
; P8-NEXT: mtlr r0 ; P8-NEXT: mtlr r0
; P8-NEXT: blr ; P8-NEXT: blr
; ;
; P9-LABEL: nearbyint_f64: ; P9-LABEL: nearbyint_f64:
; P9: # %bb.0: ; P9: # %bb.0:
; P9-NEXT: mflr r0 ; P9-NEXT: mflr r0
; P9-NEXT: std r0, 16(r1)
; P9-NEXT: stdu r1, -32(r1) ; P9-NEXT: stdu r1, -32(r1)
; P9-NEXT: std r0, 48(r1)
; P9-NEXT: .cfi_def_cfa_offset 32 ; P9-NEXT: .cfi_def_cfa_offset 32
; P9-NEXT: .cfi_offset lr, 16 ; P9-NEXT: .cfi_offset lr, 16
; P9-NEXT: bl nearbyint ; P9-NEXT: bl nearbyint
; P9-NEXT: nop ; P9-NEXT: nop
; P9-NEXT: addi r1, r1, 32 ; P9-NEXT: addi r1, r1, 32
; P9-NEXT: ld r0, 16(r1) ; P9-NEXT: ld r0, 16(r1)
; P9-NEXT: mtlr r0 ; P9-NEXT: mtlr r0
; P9-NEXT: blr ; P9-NEXT: blr
%res = call double @llvm.experimental.constrained.nearbyint.f64( %res = call double @llvm.experimental.constrained.nearbyint.f64(
double %f1, double %f1,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") metadata !"fpexcept.strict")
ret double %res ret double %res
} }
define <4 x float> @nearbyint_v4f32(<4 x float> %vf1, <4 x float> %vf2) { define <4 x float> @nearbyint_v4f32(<4 x float> %vf1, <4 x float> %vf2) {
; P8-LABEL: nearbyint_v4f32: ; P8-LABEL: nearbyint_v4f32:
; P8: # %bb.0: ; P8: # %bb.0:
; P8-NEXT: mflr r0 ; P8-NEXT: mflr r0
; P8-NEXT: std r0, 16(r1)
; P8-NEXT: stdu r1, -176(r1) ; P8-NEXT: stdu r1, -176(r1)
; P8-NEXT: std r0, 192(r1)
; P8-NEXT: .cfi_def_cfa_offset 176 ; P8-NEXT: .cfi_def_cfa_offset 176
; P8-NEXT: .cfi_offset lr, 16 ; P8-NEXT: .cfi_offset lr, 16
; P8-NEXT: .cfi_offset v29, -48 ; P8-NEXT: .cfi_offset v29, -48
; P8-NEXT: .cfi_offset v30, -32 ; P8-NEXT: .cfi_offset v30, -32
; P8-NEXT: .cfi_offset v31, -16 ; P8-NEXT: .cfi_offset v31, -16
; P8-NEXT: xxsldwi vs0, v2, v2, 3 ; P8-NEXT: xxsldwi vs0, v2, v2, 3
; P8-NEXT: li r3, 128 ; P8-NEXT: li r3, 128
; P8-NEXT: stxvd2x v29, r1, r3 # 16-byte Folded Spill ; P8-NEXT: stxvd2x v29, r1, r3 # 16-byte Folded Spill
Show All 34 Lines
; P8-NEXT: addi r1, r1, 176 ; P8-NEXT: addi r1, r1, 176
; P8-NEXT: ld r0, 16(r1) ; P8-NEXT: ld r0, 16(r1)
; P8-NEXT: mtlr r0 ; P8-NEXT: mtlr r0
; P8-NEXT: blr ; P8-NEXT: blr
; ;
; P9-LABEL: nearbyint_v4f32: ; P9-LABEL: nearbyint_v4f32:
; P9: # %bb.0: ; P9: # %bb.0:
; P9-NEXT: mflr r0 ; P9-NEXT: mflr r0
; P9-NEXT: std r0, 16(r1)
; P9-NEXT: stdu r1, -80(r1) ; P9-NEXT: stdu r1, -80(r1)
; P9-NEXT: std r0, 96(r1)
; P9-NEXT: .cfi_def_cfa_offset 80 ; P9-NEXT: .cfi_def_cfa_offset 80
; P9-NEXT: .cfi_offset lr, 16 ; P9-NEXT: .cfi_offset lr, 16
; P9-NEXT: .cfi_offset v29, -48 ; P9-NEXT: .cfi_offset v29, -48
; P9-NEXT: .cfi_offset v30, -32 ; P9-NEXT: .cfi_offset v30, -32
; P9-NEXT: .cfi_offset v31, -16 ; P9-NEXT: .cfi_offset v31, -16
; P9-NEXT: xxsldwi vs0, v2, v2, 3 ; P9-NEXT: xxsldwi vs0, v2, v2, 3
; P9-NEXT: stxv v29, 32(r1) # 16-byte Folded Spill ; P9-NEXT: stxv v29, 32(r1) # 16-byte Folded Spill
; P9-NEXT: xscvspdpn f1, vs0 ; P9-NEXT: xscvspdpn f1, vs0
Show All 35 Lines %res = call <4 x float> @llvm.experimental.constrained.nearbyint.v4f32(
metadata !"fpexcept.strict") metadata !"fpexcept.strict")
ret <4 x float> %res ret <4 x float> %res
} }
define <2 x double> @nearbyint_v2f64(<2 x double> %vf1, <2 x double> %vf2) { define <2 x double> @nearbyint_v2f64(<2 x double> %vf1, <2 x double> %vf2) {
; P8-LABEL: nearbyint_v2f64: ; P8-LABEL: nearbyint_v2f64:
; P8: # %bb.0: ; P8: # %bb.0:
; P8-NEXT: mflr r0 ; P8-NEXT: mflr r0
; P8-NEXT: std r0, 16(r1)
; P8-NEXT: stdu r1, -160(r1) ; P8-NEXT: stdu r1, -160(r1)
; P8-NEXT: std r0, 176(r1)
; P8-NEXT: .cfi_def_cfa_offset 160 ; P8-NEXT: .cfi_def_cfa_offset 160
; P8-NEXT: .cfi_offset lr, 16 ; P8-NEXT: .cfi_offset lr, 16
; P8-NEXT: .cfi_offset v30, -32 ; P8-NEXT: .cfi_offset v30, -32
; P8-NEXT: .cfi_offset v31, -16 ; P8-NEXT: .cfi_offset v31, -16
; P8-NEXT: li r3, 128 ; P8-NEXT: li r3, 128
; P8-NEXT: stxvd2x v30, r1, r3 # 16-byte Folded Spill ; P8-NEXT: stxvd2x v30, r1, r3 # 16-byte Folded Spill
; P8-NEXT: li r3, 144 ; P8-NEXT: li r3, 144
; P8-NEXT: stxvd2x v31, r1, r3 # 16-byte Folded Spill ; P8-NEXT: stxvd2x v31, r1, r3 # 16-byte Folded Spill
Show All 15 Lines
; P8-NEXT: addi r1, r1, 160 ; P8-NEXT: addi r1, r1, 160
; P8-NEXT: ld r0, 16(r1) ; P8-NEXT: ld r0, 16(r1)
; P8-NEXT: mtlr r0 ; P8-NEXT: mtlr r0
; P8-NEXT: blr ; P8-NEXT: blr
; ;
; P9-LABEL: nearbyint_v2f64: ; P9-LABEL: nearbyint_v2f64:
; P9: # %bb.0: ; P9: # %bb.0:
; P9-NEXT: mflr r0 ; P9-NEXT: mflr r0
; P9-NEXT: std r0, 16(r1)
; P9-NEXT: stdu r1, -64(r1) ; P9-NEXT: stdu r1, -64(r1)
; P9-NEXT: std r0, 80(r1)
; P9-NEXT: .cfi_def_cfa_offset 64 ; P9-NEXT: .cfi_def_cfa_offset 64
; P9-NEXT: .cfi_offset lr, 16 ; P9-NEXT: .cfi_offset lr, 16
; P9-NEXT: .cfi_offset v30, -32 ; P9-NEXT: .cfi_offset v30, -32
; P9-NEXT: .cfi_offset v31, -16 ; P9-NEXT: .cfi_offset v31, -16
; P9-NEXT: stxv v31, 48(r1) # 16-byte Folded Spill ; P9-NEXT: stxv v31, 48(r1) # 16-byte Folded Spill
; P9-NEXT: vmr v31, v2 ; P9-NEXT: vmr v31, v2
; P9-NEXT: xscpsgndp f1, v31, v31 ; P9-NEXT: xscpsgndp f1, v31, v31
; P9-NEXT: stxv v30, 32(r1) # 16-byte Folded Spill ; P9-NEXT: stxv v30, 32(r1) # 16-byte Folded Spill
▲ Show 20 Lines • Show All 274 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/fp-strict.ll

Show First 20 Lines • Show All 588 Lines • ▼ Show 20 Lines
; NOVSX-LABEL: fmadd_f32: ; NOVSX-LABEL: fmadd_f32:
; NOVSX: # %bb.0: ; NOVSX: # %bb.0:
; NOVSX-NEXT: fmadds f1, f1, f2, f3 ; NOVSX-NEXT: fmadds f1, f1, f2, f3
; NOVSX-NEXT: blr ; NOVSX-NEXT: blr
; ;
; SPE-LABEL: fmadd_f32: ; SPE-LABEL: fmadd_f32:
; SPE: # %bb.0: ; SPE: # %bb.0:
; SPE-NEXT: mflr r0 ; SPE-NEXT: mflr r0
; SPE-NEXT: stw r0, 4(r1)
; SPE-NEXT: stwu r1, -16(r1) ; SPE-NEXT: stwu r1, -16(r1)
; SPE-NEXT: stw r0, 20(r1)
; SPE-NEXT: .cfi_def_cfa_offset 16 ; SPE-NEXT: .cfi_def_cfa_offset 16
; SPE-NEXT: .cfi_offset lr, 4 ; SPE-NEXT: .cfi_offset lr, 4
; SPE-NEXT: bl fmaf ; SPE-NEXT: bl fmaf
; SPE-NEXT: lwz r0, 20(r1) ; SPE-NEXT: lwz r0, 20(r1)
; SPE-NEXT: addi r1, r1, 16 ; SPE-NEXT: addi r1, r1, 16
; SPE-NEXT: mtlr r0 ; SPE-NEXT: mtlr r0
; SPE-NEXT: blr ; SPE-NEXT: blr
%res = call float @llvm.experimental.constrained.fma.f32( %res = call float @llvm.experimental.constrained.fma.f32(
Show All 13 Lines
; NOVSX-LABEL: fmadd_f64: ; NOVSX-LABEL: fmadd_f64:
; NOVSX: # %bb.0: ; NOVSX: # %bb.0:
; NOVSX-NEXT: fmadd f1, f1, f2, f3 ; NOVSX-NEXT: fmadd f1, f1, f2, f3
; NOVSX-NEXT: blr ; NOVSX-NEXT: blr
; ;
; SPE-LABEL: fmadd_f64: ; SPE-LABEL: fmadd_f64:
; SPE: # %bb.0: ; SPE: # %bb.0:
; SPE-NEXT: mflr r0 ; SPE-NEXT: mflr r0
; SPE-NEXT: stw r0, 4(r1)
; SPE-NEXT: stwu r1, -16(r1) ; SPE-NEXT: stwu r1, -16(r1)
; SPE-NEXT: stw r0, 20(r1)
; SPE-NEXT: .cfi_def_cfa_offset 16 ; SPE-NEXT: .cfi_def_cfa_offset 16
; SPE-NEXT: .cfi_offset lr, 4 ; SPE-NEXT: .cfi_offset lr, 4
; SPE-NEXT: evmergelo r8, r7, r8 ; SPE-NEXT: evmergelo r8, r7, r8
; SPE-NEXT: evmergelo r6, r5, r6 ; SPE-NEXT: evmergelo r6, r5, r6
; SPE-NEXT: evmergelo r4, r3, r4 ; SPE-NEXT: evmergelo r4, r3, r4
; SPE-NEXT: evmergehi r3, r4, r4 ; SPE-NEXT: evmergehi r3, r4, r4
; SPE-NEXT: evmergehi r5, r6, r6 ; SPE-NEXT: evmergehi r5, r6, r6
; SPE-NEXT: evmergehi r7, r8, r8 ; SPE-NEXT: evmergehi r7, r8, r8
▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines
; NOVSX-NEXT: fmadds f0, f2, f1, f0 ; NOVSX-NEXT: fmadds f0, f2, f1, f0
; NOVSX-NEXT: stfs f0, -16(r1) ; NOVSX-NEXT: stfs f0, -16(r1)
; NOVSX-NEXT: lvx v2, 0, r3 ; NOVSX-NEXT: lvx v2, 0, r3
; NOVSX-NEXT: blr ; NOVSX-NEXT: blr
; ;
; SPE-LABEL: fmadd_v4f32: ; SPE-LABEL: fmadd_v4f32:
; SPE: # %bb.0: ; SPE: # %bb.0:
; SPE-NEXT: mflr r0 ; SPE-NEXT: mflr r0
; SPE-NEXT: stw r0, 4(r1)
; SPE-NEXT: stwu r1, -96(r1) ; SPE-NEXT: stwu r1, -96(r1)
; SPE-NEXT: stw r0, 100(r1)
; SPE-NEXT: .cfi_def_cfa_offset 96 ; SPE-NEXT: .cfi_def_cfa_offset 96
; SPE-NEXT: .cfi_offset lr, 4 ; SPE-NEXT: .cfi_offset lr, 4
; SPE-NEXT: .cfi_offset r21, -88 ; SPE-NEXT: .cfi_offset r21, -88
; SPE-NEXT: .cfi_offset r22, -80 ; SPE-NEXT: .cfi_offset r22, -80
; SPE-NEXT: .cfi_offset r23, -72 ; SPE-NEXT: .cfi_offset r23, -72
; SPE-NEXT: .cfi_offset r24, -64 ; SPE-NEXT: .cfi_offset r24, -64
; SPE-NEXT: .cfi_offset r25, -56 ; SPE-NEXT: .cfi_offset r25, -56
; SPE-NEXT: .cfi_offset r26, -48 ; SPE-NEXT: .cfi_offset r26, -48
▲ Show 20 Lines • Show All 74 Lines • ▼ Show 20 Lines
; NOVSX: # %bb.0: ; NOVSX: # %bb.0:
; NOVSX-NEXT: fmadd f2, f2, f4, f6 ; NOVSX-NEXT: fmadd f2, f2, f4, f6
; NOVSX-NEXT: fmadd f1, f1, f3, f5 ; NOVSX-NEXT: fmadd f1, f1, f3, f5
; NOVSX-NEXT: blr ; NOVSX-NEXT: blr
; ;
; SPE-LABEL: fmadd_v2f64: ; SPE-LABEL: fmadd_v2f64:
; SPE: # %bb.0: ; SPE: # %bb.0:
; SPE-NEXT: mflr r0 ; SPE-NEXT: mflr r0
; SPE-NEXT: stw r0, 4(r1)
; SPE-NEXT: stwu r1, -64(r1) ; SPE-NEXT: stwu r1, -64(r1)
; SPE-NEXT: stw r0, 68(r1)
; SPE-NEXT: .cfi_def_cfa_offset 64 ; SPE-NEXT: .cfi_def_cfa_offset 64
; SPE-NEXT: .cfi_offset lr, 4 ; SPE-NEXT: .cfi_offset lr, 4
; SPE-NEXT: .cfi_offset r26, -48 ; SPE-NEXT: .cfi_offset r26, -48
; SPE-NEXT: .cfi_offset r27, -40 ; SPE-NEXT: .cfi_offset r27, -40
; SPE-NEXT: .cfi_offset r28, -32 ; SPE-NEXT: .cfi_offset r28, -32
; SPE-NEXT: .cfi_offset r29, -24 ; SPE-NEXT: .cfi_offset r29, -24
; SPE-NEXT: .cfi_offset r30, -16 ; SPE-NEXT: .cfi_offset r30, -16
; SPE-NEXT: evstdd r26, 16(r1) # 8-byte Folded Spill ; SPE-NEXT: evstdd r26, 16(r1) # 8-byte Folded Spill
▲ Show 20 Lines • Show All 59 Lines • ▼ Show 20 Lines
; NOVSX-LABEL: fmsub_f32: ; NOVSX-LABEL: fmsub_f32:
; NOVSX: # %bb.0: ; NOVSX: # %bb.0:
; NOVSX-NEXT: fmsubs f1, f1, f2, f3 ; NOVSX-NEXT: fmsubs f1, f1, f2, f3
; NOVSX-NEXT: blr ; NOVSX-NEXT: blr
; ;
; SPE-LABEL: fmsub_f32: ; SPE-LABEL: fmsub_f32:
; SPE: # %bb.0: ; SPE: # %bb.0:
; SPE-NEXT: mflr r0 ; SPE-NEXT: mflr r0
; SPE-NEXT: stw r0, 4(r1)
; SPE-NEXT: stwu r1, -16(r1) ; SPE-NEXT: stwu r1, -16(r1)
; SPE-NEXT: stw r0, 20(r1)
; SPE-NEXT: .cfi_def_cfa_offset 16 ; SPE-NEXT: .cfi_def_cfa_offset 16
; SPE-NEXT: .cfi_offset lr, 4 ; SPE-NEXT: .cfi_offset lr, 4
; SPE-NEXT: efsneg r5, r5 ; SPE-NEXT: efsneg r5, r5
; SPE-NEXT: bl fmaf ; SPE-NEXT: bl fmaf
; SPE-NEXT: lwz r0, 20(r1) ; SPE-NEXT: lwz r0, 20(r1)
; SPE-NEXT: addi r1, r1, 16 ; SPE-NEXT: addi r1, r1, 16
; SPE-NEXT: mtlr r0 ; SPE-NEXT: mtlr r0
; SPE-NEXT: blr ; SPE-NEXT: blr
Show All 15 Lines
; NOVSX-LABEL: fmsub_f64: ; NOVSX-LABEL: fmsub_f64:
; NOVSX: # %bb.0: ; NOVSX: # %bb.0:
; NOVSX-NEXT: fmsub f1, f1, f2, f3 ; NOVSX-NEXT: fmsub f1, f1, f2, f3
; NOVSX-NEXT: blr ; NOVSX-NEXT: blr
; ;
; SPE-LABEL: fmsub_f64: ; SPE-LABEL: fmsub_f64:
; SPE: # %bb.0: ; SPE: # %bb.0:
; SPE-NEXT: mflr r0 ; SPE-NEXT: mflr r0
; SPE-NEXT: stw r0, 4(r1)
; SPE-NEXT: stwu r1, -16(r1) ; SPE-NEXT: stwu r1, -16(r1)
; SPE-NEXT: stw r0, 20(r1)
; SPE-NEXT: .cfi_def_cfa_offset 16 ; SPE-NEXT: .cfi_def_cfa_offset 16
; SPE-NEXT: .cfi_offset lr, 4 ; SPE-NEXT: .cfi_offset lr, 4
; SPE-NEXT: evmergelo r6, r5, r6 ; SPE-NEXT: evmergelo r6, r5, r6
; SPE-NEXT: evmergelo r4, r3, r4 ; SPE-NEXT: evmergelo r4, r3, r4
; SPE-NEXT: evmergelo r3, r7, r8 ; SPE-NEXT: evmergelo r3, r7, r8
; SPE-NEXT: efdneg r8, r3 ; SPE-NEXT: efdneg r8, r3
; SPE-NEXT: evmergehi r3, r4, r4 ; SPE-NEXT: evmergehi r3, r4, r4
; SPE-NEXT: evmergehi r5, r6, r6 ; SPE-NEXT: evmergehi r5, r6, r6
▲ Show 20 Lines • Show All 61 Lines • ▼ Show 20 Lines
; NOVSX-NEXT: fmadds f0, f1, f0, f2 ; NOVSX-NEXT: fmadds f0, f1, f0, f2
; NOVSX-NEXT: stfs f0, -16(r1) ; NOVSX-NEXT: stfs f0, -16(r1)
; NOVSX-NEXT: lvx v2, 0, r3 ; NOVSX-NEXT: lvx v2, 0, r3
; NOVSX-NEXT: blr ; NOVSX-NEXT: blr
; ;
; SPE-LABEL: fmsub_v4f32: ; SPE-LABEL: fmsub_v4f32:
; SPE: # %bb.0: ; SPE: # %bb.0:
; SPE-NEXT: mflr r0 ; SPE-NEXT: mflr r0
; SPE-NEXT: stw r0, 4(r1)
; SPE-NEXT: stwu r1, -96(r1) ; SPE-NEXT: stwu r1, -96(r1)
; SPE-NEXT: stw r0, 100(r1)
; SPE-NEXT: .cfi_def_cfa_offset 96 ; SPE-NEXT: .cfi_def_cfa_offset 96
; SPE-NEXT: .cfi_offset lr, 4 ; SPE-NEXT: .cfi_offset lr, 4
; SPE-NEXT: .cfi_offset r21, -88 ; SPE-NEXT: .cfi_offset r21, -88
; SPE-NEXT: .cfi_offset r22, -80 ; SPE-NEXT: .cfi_offset r22, -80
; SPE-NEXT: .cfi_offset r23, -72 ; SPE-NEXT: .cfi_offset r23, -72
; SPE-NEXT: .cfi_offset r24, -64 ; SPE-NEXT: .cfi_offset r24, -64
; SPE-NEXT: .cfi_offset r25, -56 ; SPE-NEXT: .cfi_offset r25, -56
; SPE-NEXT: .cfi_offset r26, -48 ; SPE-NEXT: .cfi_offset r26, -48
▲ Show 20 Lines • Show All 79 Lines • ▼ Show 20 Lines
; NOVSX: # %bb.0: ; NOVSX: # %bb.0:
; NOVSX-NEXT: fmsub f2, f2, f4, f6 ; NOVSX-NEXT: fmsub f2, f2, f4, f6
; NOVSX-NEXT: fmsub f1, f1, f3, f5 ; NOVSX-NEXT: fmsub f1, f1, f3, f5
; NOVSX-NEXT: blr ; NOVSX-NEXT: blr
; ;
; SPE-LABEL: fmsub_v2f64: ; SPE-LABEL: fmsub_v2f64:
; SPE: # %bb.0: ; SPE: # %bb.0:
; SPE-NEXT: mflr r0 ; SPE-NEXT: mflr r0
; SPE-NEXT: stw r0, 4(r1)
; SPE-NEXT: stwu r1, -64(r1) ; SPE-NEXT: stwu r1, -64(r1)
; SPE-NEXT: stw r0, 68(r1)
; SPE-NEXT: .cfi_def_cfa_offset 64 ; SPE-NEXT: .cfi_def_cfa_offset 64
; SPE-NEXT: .cfi_offset lr, 4 ; SPE-NEXT: .cfi_offset lr, 4
; SPE-NEXT: .cfi_offset r26, -48 ; SPE-NEXT: .cfi_offset r26, -48
; SPE-NEXT: .cfi_offset r27, -40 ; SPE-NEXT: .cfi_offset r27, -40
; SPE-NEXT: .cfi_offset r28, -32 ; SPE-NEXT: .cfi_offset r28, -32
; SPE-NEXT: .cfi_offset r29, -24 ; SPE-NEXT: .cfi_offset r29, -24
; SPE-NEXT: .cfi_offset r30, -16 ; SPE-NEXT: .cfi_offset r30, -16
; SPE-NEXT: evstdd r30, 48(r1) # 8-byte Folded Spill ; SPE-NEXT: evstdd r30, 48(r1) # 8-byte Folded Spill
▲ Show 20 Lines • Show All 62 Lines • ▼ Show 20 Lines
; NOVSX-LABEL: fnmadd_f32: ; NOVSX-LABEL: fnmadd_f32:
; NOVSX: # %bb.0: ; NOVSX: # %bb.0:
; NOVSX-NEXT: fnmadds f1, f1, f2, f3 ; NOVSX-NEXT: fnmadds f1, f1, f2, f3
; NOVSX-NEXT: blr ; NOVSX-NEXT: blr
; ;
; SPE-LABEL: fnmadd_f32: ; SPE-LABEL: fnmadd_f32:
; SPE: # %bb.0: ; SPE: # %bb.0:
; SPE-NEXT: mflr r0 ; SPE-NEXT: mflr r0
; SPE-NEXT: stw r0, 4(r1)
; SPE-NEXT: stwu r1, -16(r1) ; SPE-NEXT: stwu r1, -16(r1)
; SPE-NEXT: stw r0, 20(r1)
; SPE-NEXT: .cfi_def_cfa_offset 16 ; SPE-NEXT: .cfi_def_cfa_offset 16
; SPE-NEXT: .cfi_offset lr, 4 ; SPE-NEXT: .cfi_offset lr, 4
; SPE-NEXT: bl fmaf ; SPE-NEXT: bl fmaf
; SPE-NEXT: efsneg r3, r3 ; SPE-NEXT: efsneg r3, r3
; SPE-NEXT: lwz r0, 20(r1) ; SPE-NEXT: lwz r0, 20(r1)
; SPE-NEXT: addi r1, r1, 16 ; SPE-NEXT: addi r1, r1, 16
; SPE-NEXT: mtlr r0 ; SPE-NEXT: mtlr r0
; SPE-NEXT: blr ; SPE-NEXT: blr
Show All 15 Lines
; NOVSX-LABEL: fnmadd_f64: ; NOVSX-LABEL: fnmadd_f64:
; NOVSX: # %bb.0: ; NOVSX: # %bb.0:
; NOVSX-NEXT: fnmadd f1, f1, f2, f3 ; NOVSX-NEXT: fnmadd f1, f1, f2, f3
; NOVSX-NEXT: blr ; NOVSX-NEXT: blr
; ;
; SPE-LABEL: fnmadd_f64: ; SPE-LABEL: fnmadd_f64:
; SPE: # %bb.0: ; SPE: # %bb.0:
; SPE-NEXT: mflr r0 ; SPE-NEXT: mflr r0
; SPE-NEXT: stw r0, 4(r1)
; SPE-NEXT: stwu r1, -16(r1) ; SPE-NEXT: stwu r1, -16(r1)
; SPE-NEXT: stw r0, 20(r1)
; SPE-NEXT: .cfi_def_cfa_offset 16 ; SPE-NEXT: .cfi_def_cfa_offset 16
; SPE-NEXT: .cfi_offset lr, 4 ; SPE-NEXT: .cfi_offset lr, 4
; SPE-NEXT: evmergelo r8, r7, r8 ; SPE-NEXT: evmergelo r8, r7, r8
; SPE-NEXT: evmergelo r6, r5, r6 ; SPE-NEXT: evmergelo r6, r5, r6
; SPE-NEXT: evmergelo r4, r3, r4 ; SPE-NEXT: evmergelo r4, r3, r4
; SPE-NEXT: evmergehi r3, r4, r4 ; SPE-NEXT: evmergehi r3, r4, r4
; SPE-NEXT: evmergehi r5, r6, r6 ; SPE-NEXT: evmergehi r5, r6, r6
; SPE-NEXT: evmergehi r7, r8, r8 ; SPE-NEXT: evmergehi r7, r8, r8
▲ Show 20 Lines • Show All 61 Lines • ▼ Show 20 Lines
; NOVSX-NEXT: stfs f0, -16(r1) ; NOVSX-NEXT: stfs f0, -16(r1)
; NOVSX-NEXT: lvx v3, 0, r3 ; NOVSX-NEXT: lvx v3, 0, r3
; NOVSX-NEXT: vsubfp v2, v2, v3 ; NOVSX-NEXT: vsubfp v2, v2, v3
; NOVSX-NEXT: blr ; NOVSX-NEXT: blr
; ;
; SPE-LABEL: fnmadd_v4f32: ; SPE-LABEL: fnmadd_v4f32:
; SPE: # %bb.0: ; SPE: # %bb.0:
; SPE-NEXT: mflr r0 ; SPE-NEXT: mflr r0
; SPE-NEXT: stw r0, 4(r1)
; SPE-NEXT: stwu r1, -96(r1) ; SPE-NEXT: stwu r1, -96(r1)
; SPE-NEXT: stw r0, 100(r1)
; SPE-NEXT: .cfi_def_cfa_offset 96 ; SPE-NEXT: .cfi_def_cfa_offset 96
; SPE-NEXT: .cfi_offset lr, 4 ; SPE-NEXT: .cfi_offset lr, 4
; SPE-NEXT: .cfi_offset r21, -88 ; SPE-NEXT: .cfi_offset r21, -88
; SPE-NEXT: .cfi_offset r22, -80 ; SPE-NEXT: .cfi_offset r22, -80
; SPE-NEXT: .cfi_offset r23, -72 ; SPE-NEXT: .cfi_offset r23, -72
; SPE-NEXT: .cfi_offset r24, -64 ; SPE-NEXT: .cfi_offset r24, -64
; SPE-NEXT: .cfi_offset r25, -56 ; SPE-NEXT: .cfi_offset r25, -56
; SPE-NEXT: .cfi_offset r26, -48 ; SPE-NEXT: .cfi_offset r26, -48
▲ Show 20 Lines • Show All 76 Lines • ▼ Show 20 Lines
; NOVSX: # %bb.0: ; NOVSX: # %bb.0:
; NOVSX-NEXT: fnmadd f2, f2, f4, f6 ; NOVSX-NEXT: fnmadd f2, f2, f4, f6
; NOVSX-NEXT: fnmadd f1, f1, f3, f5 ; NOVSX-NEXT: fnmadd f1, f1, f3, f5
; NOVSX-NEXT: blr ; NOVSX-NEXT: blr
; ;
; SPE-LABEL: fnmadd_v2f64: ; SPE-LABEL: fnmadd_v2f64:
; SPE: # %bb.0: ; SPE: # %bb.0:
; SPE-NEXT: mflr r0 ; SPE-NEXT: mflr r0
; SPE-NEXT: stw r0, 4(r1)
; SPE-NEXT: stwu r1, -64(r1) ; SPE-NEXT: stwu r1, -64(r1)
; SPE-NEXT: stw r0, 68(r1)
; SPE-NEXT: .cfi_def_cfa_offset 64 ; SPE-NEXT: .cfi_def_cfa_offset 64
; SPE-NEXT: .cfi_offset lr, 4 ; SPE-NEXT: .cfi_offset lr, 4
; SPE-NEXT: .cfi_offset r26, -48 ; SPE-NEXT: .cfi_offset r26, -48
; SPE-NEXT: .cfi_offset r27, -40 ; SPE-NEXT: .cfi_offset r27, -40
; SPE-NEXT: .cfi_offset r28, -32 ; SPE-NEXT: .cfi_offset r28, -32
; SPE-NEXT: .cfi_offset r29, -24 ; SPE-NEXT: .cfi_offset r29, -24
; SPE-NEXT: .cfi_offset r30, -16 ; SPE-NEXT: .cfi_offset r30, -16
; SPE-NEXT: evstdd r26, 16(r1) # 8-byte Folded Spill ; SPE-NEXT: evstdd r26, 16(r1) # 8-byte Folded Spill
▲ Show 20 Lines • Show All 62 Lines • ▼ Show 20 Lines
; NOVSX-LABEL: fnmsub_f32: ; NOVSX-LABEL: fnmsub_f32:
; NOVSX: # %bb.0: ; NOVSX: # %bb.0:
; NOVSX-NEXT: fnmsubs f1, f1, f2, f3 ; NOVSX-NEXT: fnmsubs f1, f1, f2, f3
; NOVSX-NEXT: blr ; NOVSX-NEXT: blr
; ;
; SPE-LABEL: fnmsub_f32: ; SPE-LABEL: fnmsub_f32:
; SPE: # %bb.0: ; SPE: # %bb.0:
; SPE-NEXT: mflr r0 ; SPE-NEXT: mflr r0
; SPE-NEXT: stw r0, 4(r1)
; SPE-NEXT: stwu r1, -16(r1) ; SPE-NEXT: stwu r1, -16(r1)
; SPE-NEXT: stw r0, 20(r1)
; SPE-NEXT: .cfi_def_cfa_offset 16 ; SPE-NEXT: .cfi_def_cfa_offset 16
; SPE-NEXT: .cfi_offset lr, 4 ; SPE-NEXT: .cfi_offset lr, 4
; SPE-NEXT: efsneg r5, r5 ; SPE-NEXT: efsneg r5, r5
; SPE-NEXT: bl fmaf ; SPE-NEXT: bl fmaf
; SPE-NEXT: efsneg r3, r3 ; SPE-NEXT: efsneg r3, r3
; SPE-NEXT: lwz r0, 20(r1) ; SPE-NEXT: lwz r0, 20(r1)
; SPE-NEXT: addi r1, r1, 16 ; SPE-NEXT: addi r1, r1, 16
; SPE-NEXT: mtlr r0 ; SPE-NEXT: mtlr r0
Show All 17 Lines
; NOVSX-LABEL: fnmsub_f64: ; NOVSX-LABEL: fnmsub_f64:
; NOVSX: # %bb.0: ; NOVSX: # %bb.0:
; NOVSX-NEXT: fnmsub f1, f1, f2, f3 ; NOVSX-NEXT: fnmsub f1, f1, f2, f3
; NOVSX-NEXT: blr ; NOVSX-NEXT: blr
; ;
; SPE-LABEL: fnmsub_f64: ; SPE-LABEL: fnmsub_f64:
; SPE: # %bb.0: ; SPE: # %bb.0:
; SPE-NEXT: mflr r0 ; SPE-NEXT: mflr r0
; SPE-NEXT: stw r0, 4(r1)
; SPE-NEXT: stwu r1, -16(r1) ; SPE-NEXT: stwu r1, -16(r1)
; SPE-NEXT: stw r0, 20(r1)
; SPE-NEXT: .cfi_def_cfa_offset 16 ; SPE-NEXT: .cfi_def_cfa_offset 16
; SPE-NEXT: .cfi_offset lr, 4 ; SPE-NEXT: .cfi_offset lr, 4
; SPE-NEXT: evmergelo r6, r5, r6 ; SPE-NEXT: evmergelo r6, r5, r6
; SPE-NEXT: evmergelo r4, r3, r4 ; SPE-NEXT: evmergelo r4, r3, r4
; SPE-NEXT: evmergelo r3, r7, r8 ; SPE-NEXT: evmergelo r3, r7, r8
; SPE-NEXT: efdneg r8, r3 ; SPE-NEXT: efdneg r8, r3
; SPE-NEXT: evmergehi r3, r4, r4 ; SPE-NEXT: evmergehi r3, r4, r4
; SPE-NEXT: evmergehi r5, r6, r6 ; SPE-NEXT: evmergehi r5, r6, r6
▲ Show 20 Lines • Show All 64 Lines • ▼ Show 20 Lines
; NOVSX-NEXT: stfs f0, -16(r1) ; NOVSX-NEXT: stfs f0, -16(r1)
; NOVSX-NEXT: lvx v2, 0, r3 ; NOVSX-NEXT: lvx v2, 0, r3
; NOVSX-NEXT: vsubfp v2, v5, v2 ; NOVSX-NEXT: vsubfp v2, v5, v2
; NOVSX-NEXT: blr ; NOVSX-NEXT: blr
; ;
; SPE-LABEL: fnmsub_v4f32: ; SPE-LABEL: fnmsub_v4f32:
; SPE: # %bb.0: ; SPE: # %bb.0:
; SPE-NEXT: mflr r0 ; SPE-NEXT: mflr r0
; SPE-NEXT: stw r0, 4(r1)
; SPE-NEXT: stwu r1, -96(r1) ; SPE-NEXT: stwu r1, -96(r1)
; SPE-NEXT: stw r0, 100(r1)
; SPE-NEXT: .cfi_def_cfa_offset 96 ; SPE-NEXT: .cfi_def_cfa_offset 96
; SPE-NEXT: .cfi_offset lr, 4 ; SPE-NEXT: .cfi_offset lr, 4
; SPE-NEXT: .cfi_offset r21, -88 ; SPE-NEXT: .cfi_offset r21, -88
; SPE-NEXT: .cfi_offset r22, -80 ; SPE-NEXT: .cfi_offset r22, -80
; SPE-NEXT: .cfi_offset r23, -72 ; SPE-NEXT: .cfi_offset r23, -72
; SPE-NEXT: .cfi_offset r24, -64 ; SPE-NEXT: .cfi_offset r24, -64
; SPE-NEXT: .cfi_offset r25, -56 ; SPE-NEXT: .cfi_offset r25, -56
; SPE-NEXT: .cfi_offset r26, -48 ; SPE-NEXT: .cfi_offset r26, -48
▲ Show 20 Lines • Show All 81 Lines • ▼ Show 20 Lines
; NOVSX: # %bb.0: ; NOVSX: # %bb.0:
; NOVSX-NEXT: fnmsub f2, f2, f4, f6 ; NOVSX-NEXT: fnmsub f2, f2, f4, f6
; NOVSX-NEXT: fnmsub f1, f1, f3, f5 ; NOVSX-NEXT: fnmsub f1, f1, f3, f5
; NOVSX-NEXT: blr ; NOVSX-NEXT: blr
; ;
; SPE-LABEL: fnmsub_v2f64: ; SPE-LABEL: fnmsub_v2f64:
; SPE: # %bb.0: ; SPE: # %bb.0:
; SPE-NEXT: mflr r0 ; SPE-NEXT: mflr r0
; SPE-NEXT: stw r0, 4(r1)
; SPE-NEXT: stwu r1, -64(r1) ; SPE-NEXT: stwu r1, -64(r1)
; SPE-NEXT: stw r0, 68(r1)
; SPE-NEXT: .cfi_def_cfa_offset 64 ; SPE-NEXT: .cfi_def_cfa_offset 64
; SPE-NEXT: .cfi_offset lr, 4 ; SPE-NEXT: .cfi_offset lr, 4
; SPE-NEXT: .cfi_offset r26, -48 ; SPE-NEXT: .cfi_offset r26, -48
; SPE-NEXT: .cfi_offset r27, -40 ; SPE-NEXT: .cfi_offset r27, -40
; SPE-NEXT: .cfi_offset r28, -32 ; SPE-NEXT: .cfi_offset r28, -32
; SPE-NEXT: .cfi_offset r29, -24 ; SPE-NEXT: .cfi_offset r29, -24
; SPE-NEXT: .cfi_offset r30, -16 ; SPE-NEXT: .cfi_offset r30, -16
; SPE-NEXT: evstdd r30, 48(r1) # 8-byte Folded Spill ; SPE-NEXT: evstdd r30, 48(r1) # 8-byte Folded Spill
▲ Show 20 Lines • Show All 64 Lines • ▼ Show 20 Lines
; NOVSX-LABEL: fsqrt_f32: ; NOVSX-LABEL: fsqrt_f32:
; NOVSX: # %bb.0: ; NOVSX: # %bb.0:
; NOVSX-NEXT: fsqrts f1, f1 ; NOVSX-NEXT: fsqrts f1, f1
; NOVSX-NEXT: blr ; NOVSX-NEXT: blr
; ;
; SPE-LABEL: fsqrt_f32: ; SPE-LABEL: fsqrt_f32:
; SPE: # %bb.0: ; SPE: # %bb.0:
; SPE-NEXT: mflr r0 ; SPE-NEXT: mflr r0
; SPE-NEXT: stw r0, 4(r1)
; SPE-NEXT: stwu r1, -16(r1) ; SPE-NEXT: stwu r1, -16(r1)
; SPE-NEXT: stw r0, 20(r1)
; SPE-NEXT: .cfi_def_cfa_offset 16 ; SPE-NEXT: .cfi_def_cfa_offset 16
; SPE-NEXT: .cfi_offset lr, 4 ; SPE-NEXT: .cfi_offset lr, 4
; SPE-NEXT: bl sqrtf ; SPE-NEXT: bl sqrtf
; SPE-NEXT: lwz r0, 20(r1) ; SPE-NEXT: lwz r0, 20(r1)
; SPE-NEXT: addi r1, r1, 16 ; SPE-NEXT: addi r1, r1, 16
; SPE-NEXT: mtlr r0 ; SPE-NEXT: mtlr r0
; SPE-NEXT: blr ; SPE-NEXT: blr
%res = call float @llvm.experimental.constrained.sqrt.f32( %res = call float @llvm.experimental.constrained.sqrt.f32(
Show All 12 Lines
; NOVSX-LABEL: fsqrt_f64: ; NOVSX-LABEL: fsqrt_f64:
; NOVSX: # %bb.0: ; NOVSX: # %bb.0:
; NOVSX-NEXT: fsqrt f1, f1 ; NOVSX-NEXT: fsqrt f1, f1
; NOVSX-NEXT: blr ; NOVSX-NEXT: blr
; ;
; SPE-LABEL: fsqrt_f64: ; SPE-LABEL: fsqrt_f64:
; SPE: # %bb.0: ; SPE: # %bb.0:
; SPE-NEXT: mflr r0 ; SPE-NEXT: mflr r0
; SPE-NEXT: stw r0, 4(r1)
; SPE-NEXT: stwu r1, -16(r1) ; SPE-NEXT: stwu r1, -16(r1)
; SPE-NEXT: stw r0, 20(r1)
; SPE-NEXT: .cfi_def_cfa_offset 16 ; SPE-NEXT: .cfi_def_cfa_offset 16
; SPE-NEXT: .cfi_offset lr, 4 ; SPE-NEXT: .cfi_offset lr, 4
; SPE-NEXT: evmergelo r4, r3, r4 ; SPE-NEXT: evmergelo r4, r3, r4
; SPE-NEXT: evmergehi r3, r4, r4 ; SPE-NEXT: evmergehi r3, r4, r4
; SPE-NEXT: # kill: def $r4 killed $r4 killed $s4 ; SPE-NEXT: # kill: def $r4 killed $r4 killed $s4
; SPE-NEXT: # kill: def $r3 killed $r3 killed $s3 ; SPE-NEXT: # kill: def $r3 killed $r3 killed $s3
; SPE-NEXT: bl sqrt ; SPE-NEXT: bl sqrt
; SPE-NEXT: evmergelo r4, r3, r4 ; SPE-NEXT: evmergelo r4, r3, r4
Show All 35 Lines
; NOVSX-NEXT: fsqrts f0, f0 ; NOVSX-NEXT: fsqrts f0, f0
; NOVSX-NEXT: stfs f0, -16(r1) ; NOVSX-NEXT: stfs f0, -16(r1)
; NOVSX-NEXT: lvx v2, 0, r3 ; NOVSX-NEXT: lvx v2, 0, r3
; NOVSX-NEXT: blr ; NOVSX-NEXT: blr
; ;
; SPE-LABEL: fsqrt_v4f32: ; SPE-LABEL: fsqrt_v4f32:
; SPE: # %bb.0: ; SPE: # %bb.0:
; SPE-NEXT: mflr r0 ; SPE-NEXT: mflr r0
; SPE-NEXT: stw r0, 4(r1)
; SPE-NEXT: stwu r1, -48(r1) ; SPE-NEXT: stwu r1, -48(r1)
; SPE-NEXT: stw r0, 52(r1)
; SPE-NEXT: .cfi_def_cfa_offset 48 ; SPE-NEXT: .cfi_def_cfa_offset 48
; SPE-NEXT: .cfi_offset lr, 4 ; SPE-NEXT: .cfi_offset lr, 4
; SPE-NEXT: .cfi_offset r27, -40 ; SPE-NEXT: .cfi_offset r27, -40
; SPE-NEXT: .cfi_offset r28, -32 ; SPE-NEXT: .cfi_offset r28, -32
; SPE-NEXT: .cfi_offset r29, -24 ; SPE-NEXT: .cfi_offset r29, -24
; SPE-NEXT: .cfi_offset r30, -16 ; SPE-NEXT: .cfi_offset r30, -16
; SPE-NEXT: evstdd r28, 16(r1) # 8-byte Folded Spill ; SPE-NEXT: evstdd r28, 16(r1) # 8-byte Folded Spill
; SPE-NEXT: mr r28, r3 ; SPE-NEXT: mr r28, r3
▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Lines
; NOVSX: # %bb.0: ; NOVSX: # %bb.0:
; NOVSX-NEXT: fsqrt f2, f2 ; NOVSX-NEXT: fsqrt f2, f2
; NOVSX-NEXT: fsqrt f1, f1 ; NOVSX-NEXT: fsqrt f1, f1
; NOVSX-NEXT: blr ; NOVSX-NEXT: blr
; ;
; SPE-LABEL: fsqrt_v2f64: ; SPE-LABEL: fsqrt_v2f64:
; SPE: # %bb.0: ; SPE: # %bb.0:
; SPE-NEXT: mflr r0 ; SPE-NEXT: mflr r0
; SPE-NEXT: stw r0, 4(r1)
; SPE-NEXT: stwu r1, -48(r1) ; SPE-NEXT: stwu r1, -48(r1)
; SPE-NEXT: stw r0, 52(r1)
; SPE-NEXT: .cfi_def_cfa_offset 48 ; SPE-NEXT: .cfi_def_cfa_offset 48
; SPE-NEXT: .cfi_offset lr, 4 ; SPE-NEXT: .cfi_offset lr, 4
; SPE-NEXT: .cfi_offset r28, -32 ; SPE-NEXT: .cfi_offset r28, -32
; SPE-NEXT: .cfi_offset r29, -24 ; SPE-NEXT: .cfi_offset r29, -24
; SPE-NEXT: .cfi_offset r30, -16 ; SPE-NEXT: .cfi_offset r30, -16
; SPE-NEXT: evstdd r28, 16(r1) # 8-byte Folded Spill ; SPE-NEXT: evstdd r28, 16(r1) # 8-byte Folded Spill
; SPE-NEXT: evstdd r29, 24(r1) # 8-byte Folded Spill ; SPE-NEXT: evstdd r29, 24(r1) # 8-byte Folded Spill
; SPE-NEXT: evstdd r30, 32(r1) # 8-byte Folded Spill ; SPE-NEXT: evstdd r30, 32(r1) # 8-byte Folded Spill
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llvm/test/CodeGen/PowerPC/fp128-bitcast-after-operation.ll

Show First 20 Lines • Show All 86 Lines • ▼ Show 20 Linesentry:
%1 = bitcast ppc_fp128 %0 to i128 %1 = bitcast ppc_fp128 %0 to i128
ret i128 %1 ret i128 %1
} }
define i128 @test_copysign(ppc_fp128 %x, ppc_fp128 %y) nounwind { define i128 @test_copysign(ppc_fp128 %x, ppc_fp128 %y) nounwind {
; PPC64-P8-LE-LABEL: test_copysign: ; PPC64-P8-LE-LABEL: test_copysign:
; PPC64-P8-LE: # %bb.0: # %entry ; PPC64-P8-LE: # %bb.0: # %entry
; PPC64-P8-LE-NEXT: mflr 0 ; PPC64-P8-LE-NEXT: mflr 0
; PPC64-P8-LE-NEXT: std 0, 16(1)
; PPC64-P8-LE-NEXT: stdu 1, -32(1) ; PPC64-P8-LE-NEXT: stdu 1, -32(1)
; PPC64-P8-LE-NEXT: std 0, 48(1)
; PPC64-P8-LE-NEXT: bl copysignl ; PPC64-P8-LE-NEXT: bl copysignl
; PPC64-P8-LE-NEXT: nop ; PPC64-P8-LE-NEXT: nop
; PPC64-P8-LE-NEXT: mffprd 3, 1 ; PPC64-P8-LE-NEXT: mffprd 3, 1
; PPC64-P8-LE-NEXT: mffprd 4, 2 ; PPC64-P8-LE-NEXT: mffprd 4, 2
; PPC64-P8-LE-NEXT: addi 1, 1, 32 ; PPC64-P8-LE-NEXT: addi 1, 1, 32
; PPC64-P8-LE-NEXT: ld 0, 16(1) ; PPC64-P8-LE-NEXT: ld 0, 16(1)
; PPC64-P8-LE-NEXT: mtlr 0 ; PPC64-P8-LE-NEXT: mtlr 0
; PPC64-P8-LE-NEXT: blr ; PPC64-P8-LE-NEXT: blr
; ;
; PPC64-LE-LABEL: test_copysign: ; PPC64-LE-LABEL: test_copysign:
; PPC64-LE: # %bb.0: # %entry ; PPC64-LE: # %bb.0: # %entry
; PPC64-LE-NEXT: mflr 0 ; PPC64-LE-NEXT: mflr 0
; PPC64-LE-NEXT: std 0, 16(1)
; PPC64-LE-NEXT: stdu 1, -48(1) ; PPC64-LE-NEXT: stdu 1, -48(1)
; PPC64-LE-NEXT: std 0, 64(1)
; PPC64-LE-NEXT: bl copysignl ; PPC64-LE-NEXT: bl copysignl
; PPC64-LE-NEXT: nop ; PPC64-LE-NEXT: nop
; PPC64-LE-NEXT: stfd 1, 32(1) ; PPC64-LE-NEXT: stfd 1, 32(1)
; PPC64-LE-NEXT: stfd 2, 40(1) ; PPC64-LE-NEXT: stfd 2, 40(1)
; PPC64-LE-NEXT: ld 3, 32(1) ; PPC64-LE-NEXT: ld 3, 32(1)
; PPC64-LE-NEXT: ld 4, 40(1) ; PPC64-LE-NEXT: ld 4, 40(1)
; PPC64-LE-NEXT: addi 1, 1, 48 ; PPC64-LE-NEXT: addi 1, 1, 48
; PPC64-LE-NEXT: ld 0, 16(1) ; PPC64-LE-NEXT: ld 0, 16(1)
; PPC64-LE-NEXT: mtlr 0 ; PPC64-LE-NEXT: mtlr 0
; PPC64-LE-NEXT: blr ; PPC64-LE-NEXT: blr
; ;
; PPC64-P8-BE-LABEL: test_copysign: ; PPC64-P8-BE-LABEL: test_copysign:
; PPC64-P8-BE: # %bb.0: # %entry ; PPC64-P8-BE: # %bb.0: # %entry
; PPC64-P8-BE-NEXT: mflr 0 ; PPC64-P8-BE-NEXT: mflr 0
; PPC64-P8-BE-NEXT: std 0, 16(1)
; PPC64-P8-BE-NEXT: stdu 1, -112(1) ; PPC64-P8-BE-NEXT: stdu 1, -112(1)
; PPC64-P8-BE-NEXT: std 0, 128(1)
; PPC64-P8-BE-NEXT: bl copysignl ; PPC64-P8-BE-NEXT: bl copysignl
; PPC64-P8-BE-NEXT: nop ; PPC64-P8-BE-NEXT: nop
; PPC64-P8-BE-NEXT: mffprd 3, 1 ; PPC64-P8-BE-NEXT: mffprd 3, 1
; PPC64-P8-BE-NEXT: mffprd 4, 2 ; PPC64-P8-BE-NEXT: mffprd 4, 2
; PPC64-P8-BE-NEXT: addi 1, 1, 112 ; PPC64-P8-BE-NEXT: addi 1, 1, 112
; PPC64-P8-BE-NEXT: ld 0, 16(1) ; PPC64-P8-BE-NEXT: ld 0, 16(1)
; PPC64-P8-BE-NEXT: mtlr 0 ; PPC64-P8-BE-NEXT: mtlr 0
; PPC64-P8-BE-NEXT: blr ; PPC64-P8-BE-NEXT: blr
; ;
; PPC64-BE-LABEL: test_copysign: ; PPC64-BE-LABEL: test_copysign:
; PPC64-BE: # %bb.0: # %entry ; PPC64-BE: # %bb.0: # %entry
; PPC64-BE-NEXT: mflr 0 ; PPC64-BE-NEXT: mflr 0
; PPC64-BE-NEXT: std 0, 16(1)
; PPC64-BE-NEXT: stdu 1, -128(1) ; PPC64-BE-NEXT: stdu 1, -128(1)
; PPC64-BE-NEXT: std 0, 144(1)
; PPC64-BE-NEXT: bl copysignl ; PPC64-BE-NEXT: bl copysignl
; PPC64-BE-NEXT: nop ; PPC64-BE-NEXT: nop
; PPC64-BE-NEXT: stfd 1, 112(1) ; PPC64-BE-NEXT: stfd 1, 112(1)
; PPC64-BE-NEXT: stfd 2, 120(1) ; PPC64-BE-NEXT: stfd 2, 120(1)
; PPC64-BE-NEXT: ld 3, 112(1) ; PPC64-BE-NEXT: ld 3, 112(1)
; PPC64-BE-NEXT: ld 4, 120(1) ; PPC64-BE-NEXT: ld 4, 120(1)
; PPC64-BE-NEXT: addi 1, 1, 128 ; PPC64-BE-NEXT: addi 1, 1, 128
; PPC64-BE-NEXT: ld 0, 16(1) ; PPC64-BE-NEXT: ld 0, 16(1)
; PPC64-BE-NEXT: mtlr 0 ; PPC64-BE-NEXT: mtlr 0
; PPC64-BE-NEXT: blr ; PPC64-BE-NEXT: blr
; ;
; PPC32-LABEL: test_copysign: ; PPC32-LABEL: test_copysign:
; PPC32: # %bb.0: # %entry ; PPC32: # %bb.0: # %entry
; PPC32-NEXT: mflr 0 ; PPC32-NEXT: mflr 0
; PPC32-NEXT: stw 0, 4(1)
; PPC32-NEXT: stwu 1, -96(1) ; PPC32-NEXT: stwu 1, -96(1)
; PPC32-NEXT: stw 0, 100(1)
; PPC32-NEXT: stfd 1, 40(1) ; PPC32-NEXT: stfd 1, 40(1)
; PPC32-NEXT: lwz 3, 44(1) ; PPC32-NEXT: lwz 3, 44(1)
; PPC32-NEXT: stfd 2, 32(1) ; PPC32-NEXT: stfd 2, 32(1)
; PPC32-NEXT: stw 3, 60(1) ; PPC32-NEXT: stw 3, 60(1)
; PPC32-NEXT: lwz 3, 40(1) ; PPC32-NEXT: lwz 3, 40(1)
; PPC32-NEXT: stfd 3, 72(1) ; PPC32-NEXT: stfd 3, 72(1)
; PPC32-NEXT: stw 3, 56(1) ; PPC32-NEXT: stw 3, 56(1)
; PPC32-NEXT: lwz 3, 36(1) ; PPC32-NEXT: lwz 3, 36(1)
▲ Show 20 Lines • Show All 79 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/frem.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=powerpc64le -mcpu=pwr9 < %s | FileCheck %s ; RUN: llc -mtriple=powerpc64le -mcpu=pwr9 < %s | FileCheck %s
define float @frem32(float %a, float %b) { define float @frem32(float %a, float %b) {
; CHECK-LABEL: frem32: ; CHECK-LABEL: frem32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; CHECK-NEXT: std 0, 16(1)
; CHECK-NEXT: stdu 1, -32(1) ; CHECK-NEXT: stdu 1, -32(1)
; CHECK-NEXT: std 0, 48(1)
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: bl fmodf ; CHECK-NEXT: bl fmodf
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: addi 1, 1, 32 ; CHECK-NEXT: addi 1, 1, 32
; CHECK-NEXT: ld 0, 16(1) ; CHECK-NEXT: ld 0, 16(1)
; CHECK-NEXT: mtlr 0 ; CHECK-NEXT: mtlr 0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%rem = frem fast float %a, %b %rem = frem fast float %a, %b
ret float %rem ret float %rem
} }
define double @frem64(double %a, double %b) { define double @frem64(double %a, double %b) {
; CHECK-LABEL: frem64: ; CHECK-LABEL: frem64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; CHECK-NEXT: std 0, 16(1)
; CHECK-NEXT: stdu 1, -32(1) ; CHECK-NEXT: stdu 1, -32(1)
; CHECK-NEXT: std 0, 48(1)
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: bl fmod ; CHECK-NEXT: bl fmod
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: addi 1, 1, 32 ; CHECK-NEXT: addi 1, 1, 32
; CHECK-NEXT: ld 0, 16(1) ; CHECK-NEXT: ld 0, 16(1)
; CHECK-NEXT: mtlr 0 ; CHECK-NEXT: mtlr 0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%rem = frem fast double %a, %b %rem = frem fast double %a, %b
ret double %rem ret double %rem
} }
define <4 x float> @frem4x32(<4 x float> %a, <4 x float> %b) { define <4 x float> @frem4x32(<4 x float> %a, <4 x float> %b) {
; CHECK-LABEL: frem4x32: ; CHECK-LABEL: frem4x32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; CHECK-NEXT: std 0, 16(1)
; CHECK-NEXT: stdu 1, -96(1) ; CHECK-NEXT: stdu 1, -96(1)
; CHECK-NEXT: std 0, 112(1)
; CHECK-NEXT: .cfi_def_cfa_offset 96 ; CHECK-NEXT: .cfi_def_cfa_offset 96
; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: .cfi_offset v28, -64 ; CHECK-NEXT: .cfi_offset v28, -64
; CHECK-NEXT: .cfi_offset v29, -48 ; CHECK-NEXT: .cfi_offset v29, -48
; CHECK-NEXT: .cfi_offset v30, -32 ; CHECK-NEXT: .cfi_offset v30, -32
; CHECK-NEXT: .cfi_offset v31, -16 ; CHECK-NEXT: .cfi_offset v31, -16
; CHECK-NEXT: xxsldwi 0, 34, 34, 3 ; CHECK-NEXT: xxsldwi 0, 34, 34, 3
; CHECK-NEXT: stxv 60, 32(1) # 16-byte Folded Spill ; CHECK-NEXT: stxv 60, 32(1) # 16-byte Folded Spill
▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Linesentry:
%rem = frem fast <4 x float> %a, %b %rem = frem fast <4 x float> %a, %b
ret <4 x float> %rem ret <4 x float> %rem
} }
define <2 x double> @frem2x64(<2 x double> %a, <2 x double> %b) { define <2 x double> @frem2x64(<2 x double> %a, <2 x double> %b) {
; CHECK-LABEL: frem2x64: ; CHECK-LABEL: frem2x64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; CHECK-NEXT: std 0, 16(1)
; CHECK-NEXT: stdu 1, -80(1) ; CHECK-NEXT: stdu 1, -80(1)
; CHECK-NEXT: std 0, 96(1)
; CHECK-NEXT: .cfi_def_cfa_offset 80 ; CHECK-NEXT: .cfi_def_cfa_offset 80
; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: .cfi_offset v29, -48 ; CHECK-NEXT: .cfi_offset v29, -48
; CHECK-NEXT: .cfi_offset v30, -32 ; CHECK-NEXT: .cfi_offset v30, -32
; CHECK-NEXT: .cfi_offset v31, -16 ; CHECK-NEXT: .cfi_offset v31, -16
; CHECK-NEXT: stxv 62, 48(1) # 16-byte Folded Spill ; CHECK-NEXT: stxv 62, 48(1) # 16-byte Folded Spill
; CHECK-NEXT: stxv 63, 64(1) # 16-byte Folded Spill ; CHECK-NEXT: stxv 63, 64(1) # 16-byte Folded Spill
; CHECK-NEXT: vmr 31, 3 ; CHECK-NEXT: vmr 31, 3
Show All 26 Lines

llvm/test/CodeGen/PowerPC/funnel-shift.ll

Show First 20 Lines • Show All 228 Lines • ▼ Show 20 Lines
} }
; Verify that weird types are minimally supported. ; Verify that weird types are minimally supported.
declare i37 @llvm.fshl.i37(i37, i37, i37) declare i37 @llvm.fshl.i37(i37, i37, i37)
define i37 @fshl_i37(i37 %x, i37 %y, i37 %z) { define i37 @fshl_i37(i37 %x, i37 %y, i37 %z) {
; CHECK32_32-LABEL: fshl_i37: ; CHECK32_32-LABEL: fshl_i37:
; CHECK32_32: # %bb.0: ; CHECK32_32: # %bb.0:
; CHECK32_32-NEXT: mflr 0 ; CHECK32_32-NEXT: mflr 0
; CHECK32_32-NEXT: stw 0, 4(1)
; CHECK32_32-NEXT: stwu 1, -32(1) ; CHECK32_32-NEXT: stwu 1, -32(1)
; CHECK32_32-NEXT: stw 0, 36(1)
; CHECK32_32-NEXT: .cfi_def_cfa_offset 32 ; CHECK32_32-NEXT: .cfi_def_cfa_offset 32
; CHECK32_32-NEXT: .cfi_offset lr, 4 ; CHECK32_32-NEXT: .cfi_offset lr, 4
; CHECK32_32-NEXT: .cfi_offset r27, -20 ; CHECK32_32-NEXT: .cfi_offset r27, -20
; CHECK32_32-NEXT: .cfi_offset r28, -16 ; CHECK32_32-NEXT: .cfi_offset r28, -16
; CHECK32_32-NEXT: .cfi_offset r29, -12 ; CHECK32_32-NEXT: .cfi_offset r29, -12
; CHECK32_32-NEXT: .cfi_offset r30, -8 ; CHECK32_32-NEXT: .cfi_offset r30, -8
; CHECK32_32-NEXT: stw 27, 12(1) # 4-byte Folded Spill ; CHECK32_32-NEXT: stw 27, 12(1) # 4-byte Folded Spill
; CHECK32_32-NEXT: mr 27, 3 ; CHECK32_32-NEXT: mr 27, 3
Show All 37 Lines
; CHECK32_32-NEXT: lwz 0, 36(1) ; CHECK32_32-NEXT: lwz 0, 36(1)
; CHECK32_32-NEXT: addi 1, 1, 32 ; CHECK32_32-NEXT: addi 1, 1, 32
; CHECK32_32-NEXT: mtlr 0 ; CHECK32_32-NEXT: mtlr 0
; CHECK32_32-NEXT: blr ; CHECK32_32-NEXT: blr
; ;
; CHECK32_64-LABEL: fshl_i37: ; CHECK32_64-LABEL: fshl_i37:
; CHECK32_64: # %bb.0: ; CHECK32_64: # %bb.0:
; CHECK32_64-NEXT: mflr 0 ; CHECK32_64-NEXT: mflr 0
; CHECK32_64-NEXT: stw 0, 4(1)
; CHECK32_64-NEXT: stwu 1, -32(1) ; CHECK32_64-NEXT: stwu 1, -32(1)
; CHECK32_64-NEXT: stw 0, 36(1)
; CHECK32_64-NEXT: .cfi_def_cfa_offset 32 ; CHECK32_64-NEXT: .cfi_def_cfa_offset 32
; CHECK32_64-NEXT: .cfi_offset lr, 4 ; CHECK32_64-NEXT: .cfi_offset lr, 4
; CHECK32_64-NEXT: .cfi_offset r27, -20 ; CHECK32_64-NEXT: .cfi_offset r27, -20
; CHECK32_64-NEXT: .cfi_offset r28, -16 ; CHECK32_64-NEXT: .cfi_offset r28, -16
; CHECK32_64-NEXT: .cfi_offset r29, -12 ; CHECK32_64-NEXT: .cfi_offset r29, -12
; CHECK32_64-NEXT: .cfi_offset r30, -8 ; CHECK32_64-NEXT: .cfi_offset r30, -8
; CHECK32_64-NEXT: stw 27, 12(1) # 4-byte Folded Spill ; CHECK32_64-NEXT: stw 27, 12(1) # 4-byte Folded Spill
; CHECK32_64-NEXT: mr 27, 3 ; CHECK32_64-NEXT: mr 27, 3
▲ Show 20 Lines • Show All 227 Lines • ▼ Show 20 Lines
} }
; Verify that weird types are minimally supported. ; Verify that weird types are minimally supported.
declare i37 @llvm.fshr.i37(i37, i37, i37) declare i37 @llvm.fshr.i37(i37, i37, i37)
define i37 @fshr_i37(i37 %x, i37 %y, i37 %z) { define i37 @fshr_i37(i37 %x, i37 %y, i37 %z) {
; CHECK32_32-LABEL: fshr_i37: ; CHECK32_32-LABEL: fshr_i37:
; CHECK32_32: # %bb.0: ; CHECK32_32: # %bb.0:
; CHECK32_32-NEXT: mflr 0 ; CHECK32_32-NEXT: mflr 0
; CHECK32_32-NEXT: stw 0, 4(1)
; CHECK32_32-NEXT: stwu 1, -32(1) ; CHECK32_32-NEXT: stwu 1, -32(1)
; CHECK32_32-NEXT: stw 0, 36(1)
; CHECK32_32-NEXT: .cfi_def_cfa_offset 32 ; CHECK32_32-NEXT: .cfi_def_cfa_offset 32
; CHECK32_32-NEXT: .cfi_offset lr, 4 ; CHECK32_32-NEXT: .cfi_offset lr, 4
; CHECK32_32-NEXT: .cfi_offset r27, -20 ; CHECK32_32-NEXT: .cfi_offset r27, -20
; CHECK32_32-NEXT: .cfi_offset r28, -16 ; CHECK32_32-NEXT: .cfi_offset r28, -16
; CHECK32_32-NEXT: .cfi_offset r29, -12 ; CHECK32_32-NEXT: .cfi_offset r29, -12
; CHECK32_32-NEXT: .cfi_offset r30, -8 ; CHECK32_32-NEXT: .cfi_offset r30, -8
; CHECK32_32-NEXT: stw 27, 12(1) # 4-byte Folded Spill ; CHECK32_32-NEXT: stw 27, 12(1) # 4-byte Folded Spill
; CHECK32_32-NEXT: mr 27, 3 ; CHECK32_32-NEXT: mr 27, 3
Show All 38 Lines
; CHECK32_32-NEXT: lwz 0, 36(1) ; CHECK32_32-NEXT: lwz 0, 36(1)
; CHECK32_32-NEXT: addi 1, 1, 32 ; CHECK32_32-NEXT: addi 1, 1, 32
; CHECK32_32-NEXT: mtlr 0 ; CHECK32_32-NEXT: mtlr 0
; CHECK32_32-NEXT: blr ; CHECK32_32-NEXT: blr
; ;
; CHECK32_64-LABEL: fshr_i37: ; CHECK32_64-LABEL: fshr_i37:
; CHECK32_64: # %bb.0: ; CHECK32_64: # %bb.0:
; CHECK32_64-NEXT: mflr 0 ; CHECK32_64-NEXT: mflr 0
; CHECK32_64-NEXT: stw 0, 4(1)
; CHECK32_64-NEXT: stwu 1, -32(1) ; CHECK32_64-NEXT: stwu 1, -32(1)
; CHECK32_64-NEXT: stw 0, 36(1)
; CHECK32_64-NEXT: .cfi_def_cfa_offset 32 ; CHECK32_64-NEXT: .cfi_def_cfa_offset 32
; CHECK32_64-NEXT: .cfi_offset lr, 4 ; CHECK32_64-NEXT: .cfi_offset lr, 4
; CHECK32_64-NEXT: .cfi_offset r27, -20 ; CHECK32_64-NEXT: .cfi_offset r27, -20
; CHECK32_64-NEXT: .cfi_offset r28, -16 ; CHECK32_64-NEXT: .cfi_offset r28, -16
; CHECK32_64-NEXT: .cfi_offset r29, -12 ; CHECK32_64-NEXT: .cfi_offset r29, -12
; CHECK32_64-NEXT: .cfi_offset r30, -8 ; CHECK32_64-NEXT: .cfi_offset r30, -8
; CHECK32_64-NEXT: stw 27, 12(1) # 4-byte Folded Spill ; CHECK32_64-NEXT: stw 27, 12(1) # 4-byte Folded Spill
; CHECK32_64-NEXT: mr 27, 3 ; CHECK32_64-NEXT: mr 27, 3
▲ Show 20 Lines • Show All 190 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/handle-f16-storage-type.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown \ ; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown \
; RUN: -verify-machineinstrs -ppc-asm-full-reg-names < %s | FileCheck %s \ ; RUN: -verify-machineinstrs -ppc-asm-full-reg-names < %s | FileCheck %s \
; RUN: --check-prefix=P8 ; RUN: --check-prefix=P8
; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \ ; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
; RUN: -verify-machineinstrs -ppc-asm-full-reg-names < %s | FileCheck %s ; RUN: -verify-machineinstrs -ppc-asm-full-reg-names < %s | FileCheck %s
; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown -mattr=-hard-float \ ; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown -mattr=-hard-float \
; RUN: -verify-machineinstrs -ppc-asm-full-reg-names < %s | FileCheck %s \ ; RUN: -verify-machineinstrs -ppc-asm-full-reg-names < %s | FileCheck %s \
; RUN: --check-prefix=SOFT ; RUN: --check-prefix=SOFT
; Tests for various operations on half precison float. Much of the test is ; Tests for various operations on half precison float. Much of the test is
; copied from test/CodeGen/X86/half.ll. ; copied from test/CodeGen/X86/half.ll.
define dso_local double @loadd(ptr nocapture readonly %a) local_unnamed_addr #0 { define dso_local double @loadd(ptr nocapture readonly %a) local_unnamed_addr #0 {
; P8-LABEL: loadd: ; P8-LABEL: loadd:
; P8: # %bb.0: # %entry ; P8: # %bb.0: # %entry
; P8-NEXT: mflr r0 ; P8-NEXT: mflr r0
; P8-NEXT: std r0, 16(r1)
; P8-NEXT: stdu r1, -32(r1) ; P8-NEXT: stdu r1, -32(r1)
; P8-NEXT: std r0, 48(r1)
; P8-NEXT: lhz r3, 2(r3) ; P8-NEXT: lhz r3, 2(r3)
; P8-NEXT: bl __gnu_h2f_ieee ; P8-NEXT: bl __gnu_h2f_ieee
; P8-NEXT: nop ; P8-NEXT: nop
; P8-NEXT: addi r1, r1, 32 ; P8-NEXT: addi r1, r1, 32
; P8-NEXT: ld r0, 16(r1) ; P8-NEXT: ld r0, 16(r1)
; P8-NEXT: mtlr r0 ; P8-NEXT: mtlr r0
; P8-NEXT: blr ; P8-NEXT: blr
; ;
; CHECK-LABEL: loadd: ; CHECK-LABEL: loadd:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi r3, r3, 2 ; CHECK-NEXT: addi r3, r3, 2
; CHECK-NEXT: lxsihzx f0, 0, r3 ; CHECK-NEXT: lxsihzx f0, 0, r3
; CHECK-NEXT: xscvhpdp f1, f0 ; CHECK-NEXT: xscvhpdp f1, f0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; SOFT-LABEL: loadd: ; SOFT-LABEL: loadd:
; SOFT: # %bb.0: # %entry ; SOFT: # %bb.0: # %entry
; SOFT-NEXT: mflr r0 ; SOFT-NEXT: mflr r0
; SOFT-NEXT: std r0, 16(r1)
; SOFT-NEXT: stdu r1, -32(r1) ; SOFT-NEXT: stdu r1, -32(r1)
; SOFT-NEXT: std r0, 48(r1)
; SOFT-NEXT: lhz r3, 2(r3) ; SOFT-NEXT: lhz r3, 2(r3)
; SOFT-NEXT: bl __gnu_h2f_ieee ; SOFT-NEXT: bl __gnu_h2f_ieee
; SOFT-NEXT: nop ; SOFT-NEXT: nop
; SOFT-NEXT: bl __extendsfdf2 ; SOFT-NEXT: bl __extendsfdf2
; SOFT-NEXT: nop ; SOFT-NEXT: nop
; SOFT-NEXT: addi r1, r1, 32 ; SOFT-NEXT: addi r1, r1, 32
; SOFT-NEXT: ld r0, 16(r1) ; SOFT-NEXT: ld r0, 16(r1)
; SOFT-NEXT: mtlr r0 ; SOFT-NEXT: mtlr r0
; SOFT-NEXT: blr ; SOFT-NEXT: blr
entry: entry:
%arrayidx = getelementptr inbounds i16, ptr %a, i64 1 %arrayidx = getelementptr inbounds i16, ptr %a, i64 1
%0 = load i16, ptr %arrayidx, align 2 %0 = load i16, ptr %arrayidx, align 2
%1 = tail call double @llvm.convert.from.fp16.f64(i16 %0) %1 = tail call double @llvm.convert.from.fp16.f64(i16 %0)
ret double %1 ret double %1
} }
declare double @llvm.convert.from.fp16.f64(i16) declare double @llvm.convert.from.fp16.f64(i16)
define dso_local float @loadf(ptr nocapture readonly %a) local_unnamed_addr #0 { define dso_local float @loadf(ptr nocapture readonly %a) local_unnamed_addr #0 {
; P8-LABEL: loadf: ; P8-LABEL: loadf:
; P8: # %bb.0: # %entry ; P8: # %bb.0: # %entry
; P8-NEXT: mflr r0 ; P8-NEXT: mflr r0
; P8-NEXT: std r0, 16(r1)
; P8-NEXT: stdu r1, -32(r1) ; P8-NEXT: stdu r1, -32(r1)
; P8-NEXT: std r0, 48(r1)
; P8-NEXT: lhz r3, 2(r3) ; P8-NEXT: lhz r3, 2(r3)
; P8-NEXT: bl __gnu_h2f_ieee ; P8-NEXT: bl __gnu_h2f_ieee
; P8-NEXT: nop ; P8-NEXT: nop
; P8-NEXT: addi r1, r1, 32 ; P8-NEXT: addi r1, r1, 32
; P8-NEXT: ld r0, 16(r1) ; P8-NEXT: ld r0, 16(r1)
; P8-NEXT: mtlr r0 ; P8-NEXT: mtlr r0
; P8-NEXT: blr ; P8-NEXT: blr
; ;
; CHECK-LABEL: loadf: ; CHECK-LABEL: loadf:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi r3, r3, 2 ; CHECK-NEXT: addi r3, r3, 2
; CHECK-NEXT: lxsihzx f0, 0, r3 ; CHECK-NEXT: lxsihzx f0, 0, r3
; CHECK-NEXT: xscvhpdp f1, f0 ; CHECK-NEXT: xscvhpdp f1, f0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; SOFT-LABEL: loadf: ; SOFT-LABEL: loadf:
; SOFT: # %bb.0: # %entry ; SOFT: # %bb.0: # %entry
; SOFT-NEXT: mflr r0 ; SOFT-NEXT: mflr r0
; SOFT-NEXT: std r0, 16(r1)
; SOFT-NEXT: stdu r1, -32(r1) ; SOFT-NEXT: stdu r1, -32(r1)
; SOFT-NEXT: std r0, 48(r1)
; SOFT-NEXT: lhz r3, 2(r3) ; SOFT-NEXT: lhz r3, 2(r3)
; SOFT-NEXT: bl __gnu_h2f_ieee ; SOFT-NEXT: bl __gnu_h2f_ieee
; SOFT-NEXT: nop ; SOFT-NEXT: nop
; SOFT-NEXT: addi r1, r1, 32 ; SOFT-NEXT: addi r1, r1, 32
; SOFT-NEXT: ld r0, 16(r1) ; SOFT-NEXT: ld r0, 16(r1)
; SOFT-NEXT: mtlr r0 ; SOFT-NEXT: mtlr r0
; SOFT-NEXT: blr ; SOFT-NEXT: blr
entry: entry:
%arrayidx = getelementptr inbounds i16, ptr %a, i64 1 %arrayidx = getelementptr inbounds i16, ptr %a, i64 1
%0 = load i16, ptr %arrayidx, align 2 %0 = load i16, ptr %arrayidx, align 2
%1 = tail call float @llvm.convert.from.fp16.f32(i16 %0) %1 = tail call float @llvm.convert.from.fp16.f32(i16 %0)
ret float %1 ret float %1
} }
declare float @llvm.convert.from.fp16.f32(i16) declare float @llvm.convert.from.fp16.f32(i16)
define dso_local void @stored(ptr nocapture %a, double %b) local_unnamed_addr #0 { define dso_local void @stored(ptr nocapture %a, double %b) local_unnamed_addr #0 {
; P8-LABEL: stored: ; P8-LABEL: stored:
; P8: # %bb.0: # %entry ; P8: # %bb.0: # %entry
; P8-NEXT: mflr r0 ; P8-NEXT: mflr r0
; P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; P8-NEXT: std r0, 16(r1)
; P8-NEXT: stdu r1, -48(r1) ; P8-NEXT: stdu r1, -48(r1)
; P8-NEXT: std r0, 64(r1)
; P8-NEXT: mr r30, r3 ; P8-NEXT: mr r30, r3
; P8-NEXT: bl __truncdfhf2 ; P8-NEXT: bl __truncdfhf2
; P8-NEXT: nop ; P8-NEXT: nop
; P8-NEXT: sth r3, 0(r30) ; P8-NEXT: sth r3, 0(r30)
; P8-NEXT: addi r1, r1, 48 ; P8-NEXT: addi r1, r1, 48
; P8-NEXT: ld r0, 16(r1) ; P8-NEXT: ld r0, 16(r1)
; P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; P8-NEXT: mtlr r0 ; P8-NEXT: mtlr r0
; P8-NEXT: blr ; P8-NEXT: blr
; ;
; CHECK-LABEL: stored: ; CHECK-LABEL: stored:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xscvdphp f0, f1 ; CHECK-NEXT: xscvdphp f0, f1
; CHECK-NEXT: stxsihx f0, 0, r3 ; CHECK-NEXT: stxsihx f0, 0, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; SOFT-LABEL: stored: ; SOFT-LABEL: stored:
; SOFT: # %bb.0: # %entry ; SOFT: # %bb.0: # %entry
; SOFT-NEXT: mflr r0 ; SOFT-NEXT: mflr r0
; SOFT-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; SOFT-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; SOFT-NEXT: std r0, 16(r1)
; SOFT-NEXT: stdu r1, -48(r1) ; SOFT-NEXT: stdu r1, -48(r1)
; SOFT-NEXT: mr r30, r3 ; SOFT-NEXT: mr r30, r3
; SOFT-NEXT: mr r3, r4 ; SOFT-NEXT: mr r3, r4
; SOFT-NEXT: std r0, 64(r1)
; SOFT-NEXT: bl __truncdfhf2 ; SOFT-NEXT: bl __truncdfhf2
; SOFT-NEXT: nop ; SOFT-NEXT: nop
; SOFT-NEXT: clrldi r3, r3, 48 ; SOFT-NEXT: clrldi r3, r3, 48
; SOFT-NEXT: bl __gnu_h2f_ieee ; SOFT-NEXT: bl __gnu_h2f_ieee
; SOFT-NEXT: nop ; SOFT-NEXT: nop
; SOFT-NEXT: bl __gnu_f2h_ieee ; SOFT-NEXT: bl __gnu_f2h_ieee
; SOFT-NEXT: nop ; SOFT-NEXT: nop
; SOFT-NEXT: sth r3, 0(r30) ; SOFT-NEXT: sth r3, 0(r30)
Show All 10 Lines
declare i16 @llvm.convert.to.fp16.f64(double) declare i16 @llvm.convert.to.fp16.f64(double)
define dso_local void @storef(ptr nocapture %a, float %b) local_unnamed_addr #0 { define dso_local void @storef(ptr nocapture %a, float %b) local_unnamed_addr #0 {
; P8-LABEL: storef: ; P8-LABEL: storef:
; P8: # %bb.0: # %entry ; P8: # %bb.0: # %entry
; P8-NEXT: mflr r0 ; P8-NEXT: mflr r0
; P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; P8-NEXT: std r0, 16(r1)
; P8-NEXT: stdu r1, -48(r1) ; P8-NEXT: stdu r1, -48(r1)
; P8-NEXT: std r0, 64(r1)
; P8-NEXT: mr r30, r3 ; P8-NEXT: mr r30, r3
; P8-NEXT: bl __gnu_f2h_ieee ; P8-NEXT: bl __gnu_f2h_ieee
; P8-NEXT: nop ; P8-NEXT: nop
; P8-NEXT: sth r3, 0(r30) ; P8-NEXT: sth r3, 0(r30)
; P8-NEXT: addi r1, r1, 48 ; P8-NEXT: addi r1, r1, 48
; P8-NEXT: ld r0, 16(r1) ; P8-NEXT: ld r0, 16(r1)
; P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; P8-NEXT: mtlr r0 ; P8-NEXT: mtlr r0
; P8-NEXT: blr ; P8-NEXT: blr
; ;
; CHECK-LABEL: storef: ; CHECK-LABEL: storef:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xscvdphp f0, f1 ; CHECK-NEXT: xscvdphp f0, f1
; CHECK-NEXT: stxsihx f0, 0, r3 ; CHECK-NEXT: stxsihx f0, 0, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; SOFT-LABEL: storef: ; SOFT-LABEL: storef:
; SOFT: # %bb.0: # %entry ; SOFT: # %bb.0: # %entry
; SOFT-NEXT: mflr r0 ; SOFT-NEXT: mflr r0
; SOFT-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; SOFT-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; SOFT-NEXT: std r0, 16(r1)
; SOFT-NEXT: stdu r1, -48(r1) ; SOFT-NEXT: stdu r1, -48(r1)
; SOFT-NEXT: mr r30, r3 ; SOFT-NEXT: mr r30, r3
; SOFT-NEXT: clrldi r3, r4, 32 ; SOFT-NEXT: clrldi r3, r4, 32
; SOFT-NEXT: std r0, 64(r1)
; SOFT-NEXT: bl __gnu_f2h_ieee ; SOFT-NEXT: bl __gnu_f2h_ieee
; SOFT-NEXT: nop ; SOFT-NEXT: nop
; SOFT-NEXT: clrldi r3, r3, 48 ; SOFT-NEXT: clrldi r3, r3, 48
; SOFT-NEXT: bl __gnu_h2f_ieee ; SOFT-NEXT: bl __gnu_h2f_ieee
; SOFT-NEXT: nop ; SOFT-NEXT: nop
; SOFT-NEXT: bl __gnu_f2h_ieee ; SOFT-NEXT: bl __gnu_f2h_ieee
; SOFT-NEXT: nop ; SOFT-NEXT: nop
; SOFT-NEXT: sth r3, 0(r30) ; SOFT-NEXT: sth r3, 0(r30)
Show All 21 Lines
; CHECK-NEXT: lhz r3, 0(r3) ; CHECK-NEXT: lhz r3, 0(r3)
; CHECK-NEXT: sth r3, 0(r4) ; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; SOFT-LABEL: test_load_store: ; SOFT-LABEL: test_load_store:
; SOFT: # %bb.0: ; SOFT: # %bb.0:
; SOFT-NEXT: mflr r0 ; SOFT-NEXT: mflr r0
; SOFT-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; SOFT-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; SOFT-NEXT: std r0, 16(r1)
; SOFT-NEXT: stdu r1, -48(r1) ; SOFT-NEXT: stdu r1, -48(r1)
; SOFT-NEXT: lhz r3, 0(r3) ; SOFT-NEXT: std r0, 64(r1)
; SOFT-NEXT: mr r30, r4 ; SOFT-NEXT: mr r30, r4
; SOFT-NEXT: lhz r3, 0(r3)
; SOFT-NEXT: bl __gnu_h2f_ieee ; SOFT-NEXT: bl __gnu_h2f_ieee
; SOFT-NEXT: nop ; SOFT-NEXT: nop
; SOFT-NEXT: bl __gnu_f2h_ieee ; SOFT-NEXT: bl __gnu_f2h_ieee
; SOFT-NEXT: nop ; SOFT-NEXT: nop
; SOFT-NEXT: sth r3, 0(r30) ; SOFT-NEXT: sth r3, 0(r30)
; SOFT-NEXT: addi r1, r1, 48 ; SOFT-NEXT: addi r1, r1, 48
; SOFT-NEXT: ld r0, 16(r1) ; SOFT-NEXT: ld r0, 16(r1)
; SOFT-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; SOFT-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
Show All 40 Lines; SOFT-NEXT: blr
%val_fp = bitcast i16 %in to half %val_fp = bitcast i16 %in to half
store half %val_fp, ptr %addr store half %val_fp, ptr %addr
ret void ret void
} }
define float @test_extend32(ptr %addr) #0 { define float @test_extend32(ptr %addr) #0 {
; P8-LABEL: test_extend32: ; P8-LABEL: test_extend32:
; P8: # %bb.0: ; P8: # %bb.0:
; P8-NEXT: mflr r0 ; P8-NEXT: mflr r0
; P8-NEXT: std r0, 16(r1)
; P8-NEXT: stdu r1, -32(r1) ; P8-NEXT: stdu r1, -32(r1)
; P8-NEXT: std r0, 48(r1)
; P8-NEXT: lhz r3, 0(r3) ; P8-NEXT: lhz r3, 0(r3)
; P8-NEXT: bl __gnu_h2f_ieee ; P8-NEXT: bl __gnu_h2f_ieee
; P8-NEXT: nop ; P8-NEXT: nop
; P8-NEXT: addi r1, r1, 32 ; P8-NEXT: addi r1, r1, 32
; P8-NEXT: ld r0, 16(r1) ; P8-NEXT: ld r0, 16(r1)
; P8-NEXT: mtlr r0 ; P8-NEXT: mtlr r0
; P8-NEXT: blr ; P8-NEXT: blr
; ;
; CHECK-LABEL: test_extend32: ; CHECK-LABEL: test_extend32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lxsihzx f0, 0, r3 ; CHECK-NEXT: lxsihzx f0, 0, r3
; CHECK-NEXT: xscvhpdp f1, f0 ; CHECK-NEXT: xscvhpdp f1, f0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; SOFT-LABEL: test_extend32: ; SOFT-LABEL: test_extend32:
; SOFT: # %bb.0: ; SOFT: # %bb.0:
; SOFT-NEXT: mflr r0 ; SOFT-NEXT: mflr r0
; SOFT-NEXT: std r0, 16(r1)
; SOFT-NEXT: stdu r1, -32(r1) ; SOFT-NEXT: stdu r1, -32(r1)
; SOFT-NEXT: std r0, 48(r1)
; SOFT-NEXT: lhz r3, 0(r3) ; SOFT-NEXT: lhz r3, 0(r3)
; SOFT-NEXT: bl __gnu_h2f_ieee ; SOFT-NEXT: bl __gnu_h2f_ieee
; SOFT-NEXT: nop ; SOFT-NEXT: nop
; SOFT-NEXT: addi r1, r1, 32 ; SOFT-NEXT: addi r1, r1, 32
; SOFT-NEXT: ld r0, 16(r1) ; SOFT-NEXT: ld r0, 16(r1)
; SOFT-NEXT: mtlr r0 ; SOFT-NEXT: mtlr r0
; SOFT-NEXT: blr ; SOFT-NEXT: blr
%val16 = load half, ptr %addr %val16 = load half, ptr %addr
%val32 = fpext half %val16 to float %val32 = fpext half %val16 to float
ret float %val32 ret float %val32
} }
define double @test_extend64(ptr %addr) #0 { define double @test_extend64(ptr %addr) #0 {
; P8-LABEL: test_extend64: ; P8-LABEL: test_extend64:
; P8: # %bb.0: ; P8: # %bb.0:
; P8-NEXT: mflr r0 ; P8-NEXT: mflr r0
; P8-NEXT: std r0, 16(r1)
; P8-NEXT: stdu r1, -32(r1) ; P8-NEXT: stdu r1, -32(r1)
; P8-NEXT: std r0, 48(r1)
; P8-NEXT: lhz r3, 0(r3) ; P8-NEXT: lhz r3, 0(r3)
; P8-NEXT: bl __gnu_h2f_ieee ; P8-NEXT: bl __gnu_h2f_ieee
; P8-NEXT: nop ; P8-NEXT: nop
; P8-NEXT: addi r1, r1, 32 ; P8-NEXT: addi r1, r1, 32
; P8-NEXT: ld r0, 16(r1) ; P8-NEXT: ld r0, 16(r1)
; P8-NEXT: mtlr r0 ; P8-NEXT: mtlr r0
; P8-NEXT: blr ; P8-NEXT: blr
; ;
; CHECK-LABEL: test_extend64: ; CHECK-LABEL: test_extend64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lxsihzx f0, 0, r3 ; CHECK-NEXT: lxsihzx f0, 0, r3
; CHECK-NEXT: xscvhpdp f1, f0 ; CHECK-NEXT: xscvhpdp f1, f0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; SOFT-LABEL: test_extend64: ; SOFT-LABEL: test_extend64:
; SOFT: # %bb.0: ; SOFT: # %bb.0:
; SOFT-NEXT: mflr r0 ; SOFT-NEXT: mflr r0
; SOFT-NEXT: std r0, 16(r1)
; SOFT-NEXT: stdu r1, -32(r1) ; SOFT-NEXT: stdu r1, -32(r1)
; SOFT-NEXT: std r0, 48(r1)
; SOFT-NEXT: lhz r3, 0(r3) ; SOFT-NEXT: lhz r3, 0(r3)
; SOFT-NEXT: bl __gnu_h2f_ieee ; SOFT-NEXT: bl __gnu_h2f_ieee
; SOFT-NEXT: nop ; SOFT-NEXT: nop
; SOFT-NEXT: bl __extendsfdf2 ; SOFT-NEXT: bl __extendsfdf2
; SOFT-NEXT: nop ; SOFT-NEXT: nop
; SOFT-NEXT: addi r1, r1, 32 ; SOFT-NEXT: addi r1, r1, 32
; SOFT-NEXT: ld r0, 16(r1) ; SOFT-NEXT: ld r0, 16(r1)
; SOFT-NEXT: mtlr r0 ; SOFT-NEXT: mtlr r0
; SOFT-NEXT: blr ; SOFT-NEXT: blr
%val16 = load half, ptr %addr %val16 = load half, ptr %addr
%val32 = fpext half %val16 to double %val32 = fpext half %val16 to double
ret double %val32 ret double %val32
} }
define void @test_trunc32(float %in, ptr %addr) #0 { define void @test_trunc32(float %in, ptr %addr) #0 {
; P8-LABEL: test_trunc32: ; P8-LABEL: test_trunc32:
; P8: # %bb.0: ; P8: # %bb.0:
; P8-NEXT: mflr r0 ; P8-NEXT: mflr r0
; P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; P8-NEXT: std r0, 16(r1)
; P8-NEXT: stdu r1, -48(r1) ; P8-NEXT: stdu r1, -48(r1)
; P8-NEXT: std r0, 64(r1)
; P8-NEXT: mr r30, r4 ; P8-NEXT: mr r30, r4
; P8-NEXT: bl __gnu_f2h_ieee ; P8-NEXT: bl __gnu_f2h_ieee
; P8-NEXT: nop ; P8-NEXT: nop
; P8-NEXT: sth r3, 0(r30) ; P8-NEXT: sth r3, 0(r30)
; P8-NEXT: addi r1, r1, 48 ; P8-NEXT: addi r1, r1, 48
; P8-NEXT: ld r0, 16(r1) ; P8-NEXT: ld r0, 16(r1)
; P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; P8-NEXT: mtlr r0 ; P8-NEXT: mtlr r0
; P8-NEXT: blr ; P8-NEXT: blr
; ;
; CHECK-LABEL: test_trunc32: ; CHECK-LABEL: test_trunc32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: xscvdphp f0, f1 ; CHECK-NEXT: xscvdphp f0, f1
; CHECK-NEXT: stxsihx f0, 0, r4 ; CHECK-NEXT: stxsihx f0, 0, r4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; SOFT-LABEL: test_trunc32: ; SOFT-LABEL: test_trunc32:
; SOFT: # %bb.0: ; SOFT: # %bb.0:
; SOFT-NEXT: mflr r0 ; SOFT-NEXT: mflr r0
; SOFT-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; SOFT-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; SOFT-NEXT: std r0, 16(r1)
; SOFT-NEXT: stdu r1, -48(r1) ; SOFT-NEXT: stdu r1, -48(r1)
; SOFT-NEXT: clrldi r3, r3, 32 ; SOFT-NEXT: clrldi r3, r3, 32
; SOFT-NEXT: std r0, 64(r1)
; SOFT-NEXT: mr r30, r4 ; SOFT-NEXT: mr r30, r4
; SOFT-NEXT: bl __gnu_f2h_ieee ; SOFT-NEXT: bl __gnu_f2h_ieee
; SOFT-NEXT: nop ; SOFT-NEXT: nop
; SOFT-NEXT: clrldi r3, r3, 48 ; SOFT-NEXT: clrldi r3, r3, 48
; SOFT-NEXT: bl __gnu_h2f_ieee ; SOFT-NEXT: bl __gnu_h2f_ieee
; SOFT-NEXT: nop ; SOFT-NEXT: nop
; SOFT-NEXT: bl __gnu_f2h_ieee ; SOFT-NEXT: bl __gnu_f2h_ieee
; SOFT-NEXT: nop ; SOFT-NEXT: nop
; SOFT-NEXT: sth r3, 0(r30) ; SOFT-NEXT: sth r3, 0(r30)
; SOFT-NEXT: addi r1, r1, 48 ; SOFT-NEXT: addi r1, r1, 48
; SOFT-NEXT: ld r0, 16(r1) ; SOFT-NEXT: ld r0, 16(r1)
; SOFT-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; SOFT-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; SOFT-NEXT: mtlr r0 ; SOFT-NEXT: mtlr r0
; SOFT-NEXT: blr ; SOFT-NEXT: blr
%val16 = fptrunc float %in to half %val16 = fptrunc float %in to half
store half %val16, ptr %addr store half %val16, ptr %addr
ret void ret void
} }
define void @test_trunc64(double %in, ptr %addr) #0 { define void @test_trunc64(double %in, ptr %addr) #0 {
; P8-LABEL: test_trunc64: ; P8-LABEL: test_trunc64:
; P8: # %bb.0: ; P8: # %bb.0:
; P8-NEXT: mflr r0 ; P8-NEXT: mflr r0
; P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; P8-NEXT: std r0, 16(r1)
; P8-NEXT: stdu r1, -48(r1) ; P8-NEXT: stdu r1, -48(r1)
; P8-NEXT: std r0, 64(r1)
; P8-NEXT: mr r30, r4 ; P8-NEXT: mr r30, r4
; P8-NEXT: bl __truncdfhf2 ; P8-NEXT: bl __truncdfhf2
; P8-NEXT: nop ; P8-NEXT: nop
; P8-NEXT: sth r3, 0(r30) ; P8-NEXT: sth r3, 0(r30)
; P8-NEXT: addi r1, r1, 48 ; P8-NEXT: addi r1, r1, 48
; P8-NEXT: ld r0, 16(r1) ; P8-NEXT: ld r0, 16(r1)
; P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; P8-NEXT: mtlr r0 ; P8-NEXT: mtlr r0
; P8-NEXT: blr ; P8-NEXT: blr
; ;
; CHECK-LABEL: test_trunc64: ; CHECK-LABEL: test_trunc64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: xscvdphp f0, f1 ; CHECK-NEXT: xscvdphp f0, f1
; CHECK-NEXT: stxsihx f0, 0, r4 ; CHECK-NEXT: stxsihx f0, 0, r4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; SOFT-LABEL: test_trunc64: ; SOFT-LABEL: test_trunc64:
; SOFT: # %bb.0: ; SOFT: # %bb.0:
; SOFT-NEXT: mflr r0 ; SOFT-NEXT: mflr r0
; SOFT-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; SOFT-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; SOFT-NEXT: std r0, 16(r1)
; SOFT-NEXT: stdu r1, -48(r1) ; SOFT-NEXT: stdu r1, -48(r1)
; SOFT-NEXT: std r0, 64(r1)
; SOFT-NEXT: mr r30, r4 ; SOFT-NEXT: mr r30, r4
; SOFT-NEXT: bl __truncdfhf2 ; SOFT-NEXT: bl __truncdfhf2
; SOFT-NEXT: nop ; SOFT-NEXT: nop
; SOFT-NEXT: clrldi r3, r3, 48 ; SOFT-NEXT: clrldi r3, r3, 48
; SOFT-NEXT: bl __gnu_h2f_ieee ; SOFT-NEXT: bl __gnu_h2f_ieee
; SOFT-NEXT: nop ; SOFT-NEXT: nop
; SOFT-NEXT: bl __gnu_f2h_ieee ; SOFT-NEXT: bl __gnu_f2h_ieee
; SOFT-NEXT: nop ; SOFT-NEXT: nop
; SOFT-NEXT: sth r3, 0(r30) ; SOFT-NEXT: sth r3, 0(r30)
; SOFT-NEXT: addi r1, r1, 48 ; SOFT-NEXT: addi r1, r1, 48
; SOFT-NEXT: ld r0, 16(r1) ; SOFT-NEXT: ld r0, 16(r1)
; SOFT-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; SOFT-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; SOFT-NEXT: mtlr r0 ; SOFT-NEXT: mtlr r0
; SOFT-NEXT: blr ; SOFT-NEXT: blr
%val16 = fptrunc double %in to half %val16 = fptrunc double %in to half
store half %val16, ptr %addr store half %val16, ptr %addr
ret void ret void
} }
define i64 @test_fptosi_i64(ptr %p) #0 { define i64 @test_fptosi_i64(ptr %p) #0 {
; P8-LABEL: test_fptosi_i64: ; P8-LABEL: test_fptosi_i64:
; P8: # %bb.0: ; P8: # %bb.0:
; P8-NEXT: mflr r0 ; P8-NEXT: mflr r0
; P8-NEXT: std r0, 16(r1)
; P8-NEXT: stdu r1, -32(r1) ; P8-NEXT: stdu r1, -32(r1)
; P8-NEXT: std r0, 48(r1)
; P8-NEXT: lhz r3, 0(r3) ; P8-NEXT: lhz r3, 0(r3)
; P8-NEXT: bl __gnu_h2f_ieee ; P8-NEXT: bl __gnu_h2f_ieee
; P8-NEXT: nop ; P8-NEXT: nop
; P8-NEXT: xscvdpsxds f0, f1 ; P8-NEXT: xscvdpsxds f0, f1
; P8-NEXT: mffprd r3, f0 ; P8-NEXT: mffprd r3, f0
; P8-NEXT: addi r1, r1, 32 ; P8-NEXT: addi r1, r1, 32
; P8-NEXT: ld r0, 16(r1) ; P8-NEXT: ld r0, 16(r1)
; P8-NEXT: mtlr r0 ; P8-NEXT: mtlr r0
; P8-NEXT: blr ; P8-NEXT: blr
; ;
; CHECK-LABEL: test_fptosi_i64: ; CHECK-LABEL: test_fptosi_i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lhz r3, 0(r3) ; CHECK-NEXT: lhz r3, 0(r3)
; CHECK-NEXT: mtfprwz f0, r3 ; CHECK-NEXT: mtfprwz f0, r3
; CHECK-NEXT: xscvhpdp f0, f0 ; CHECK-NEXT: xscvhpdp f0, f0
; CHECK-NEXT: xscvdpsxds f0, f0 ; CHECK-NEXT: xscvdpsxds f0, f0
; CHECK-NEXT: mffprd r3, f0 ; CHECK-NEXT: mffprd r3, f0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; SOFT-LABEL: test_fptosi_i64: ; SOFT-LABEL: test_fptosi_i64:
; SOFT: # %bb.0: ; SOFT: # %bb.0:
; SOFT-NEXT: mflr r0 ; SOFT-NEXT: mflr r0
; SOFT-NEXT: std r0, 16(r1)
; SOFT-NEXT: stdu r1, -32(r1) ; SOFT-NEXT: stdu r1, -32(r1)
; SOFT-NEXT: std r0, 48(r1)
; SOFT-NEXT: lhz r3, 0(r3) ; SOFT-NEXT: lhz r3, 0(r3)
; SOFT-NEXT: bl __gnu_h2f_ieee ; SOFT-NEXT: bl __gnu_h2f_ieee
; SOFT-NEXT: nop ; SOFT-NEXT: nop
; SOFT-NEXT: bl __fixsfdi ; SOFT-NEXT: bl __fixsfdi
; SOFT-NEXT: nop ; SOFT-NEXT: nop
; SOFT-NEXT: addi r1, r1, 32 ; SOFT-NEXT: addi r1, r1, 32
; SOFT-NEXT: ld r0, 16(r1) ; SOFT-NEXT: ld r0, 16(r1)
; SOFT-NEXT: mtlr r0 ; SOFT-NEXT: mtlr r0
; SOFT-NEXT: blr ; SOFT-NEXT: blr
%a = load half, ptr %p, align 2 %a = load half, ptr %p, align 2
%r = fptosi half %a to i64 %r = fptosi half %a to i64
ret i64 %r ret i64 %r
} }
define void @test_sitofp_i64(i64 %a, ptr %p) #0 { define void @test_sitofp_i64(i64 %a, ptr %p) #0 {
; P8-LABEL: test_sitofp_i64: ; P8-LABEL: test_sitofp_i64:
; P8: # %bb.0: ; P8: # %bb.0:
; P8-NEXT: mflr r0 ; P8-NEXT: mflr r0
; P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; P8-NEXT: std r0, 16(r1)
; P8-NEXT: stdu r1, -48(r1) ; P8-NEXT: stdu r1, -48(r1)
; P8-NEXT: mtfprd f0, r3 ; P8-NEXT: mtfprd f0, r3
; P8-NEXT: std r0, 64(r1)
; P8-NEXT: mr r30, r4 ; P8-NEXT: mr r30, r4
; P8-NEXT: xscvsxdsp f1, f0 ; P8-NEXT: xscvsxdsp f1, f0
; P8-NEXT: bl __gnu_f2h_ieee ; P8-NEXT: bl __gnu_f2h_ieee
; P8-NEXT: nop ; P8-NEXT: nop
; P8-NEXT: sth r3, 0(r30) ; P8-NEXT: sth r3, 0(r30)
; P8-NEXT: addi r1, r1, 48 ; P8-NEXT: addi r1, r1, 48
; P8-NEXT: ld r0, 16(r1) ; P8-NEXT: ld r0, 16(r1)
; P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; P8-NEXT: mtlr r0 ; P8-NEXT: mtlr r0
; P8-NEXT: blr ; P8-NEXT: blr
; ;
; CHECK-LABEL: test_sitofp_i64: ; CHECK-LABEL: test_sitofp_i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: mtfprd f0, r3 ; CHECK-NEXT: mtfprd f0, r3
; CHECK-NEXT: xscvsxdsp f0, f0 ; CHECK-NEXT: xscvsxdsp f0, f0
; CHECK-NEXT: xscvdphp f0, f0 ; CHECK-NEXT: xscvdphp f0, f0
; CHECK-NEXT: mffprwz r3, f0 ; CHECK-NEXT: mffprwz r3, f0
; CHECK-NEXT: sth r3, 0(r4) ; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; SOFT-LABEL: test_sitofp_i64: ; SOFT-LABEL: test_sitofp_i64:
; SOFT: # %bb.0: ; SOFT: # %bb.0:
; SOFT-NEXT: mflr r0 ; SOFT-NEXT: mflr r0
; SOFT-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; SOFT-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; SOFT-NEXT: std r0, 16(r1)
; SOFT-NEXT: stdu r1, -48(r1) ; SOFT-NEXT: stdu r1, -48(r1)
; SOFT-NEXT: std r0, 64(r1)
; SOFT-NEXT: mr r30, r4 ; SOFT-NEXT: mr r30, r4
; SOFT-NEXT: bl __floatdisf ; SOFT-NEXT: bl __floatdisf
; SOFT-NEXT: nop ; SOFT-NEXT: nop
; SOFT-NEXT: clrldi r3, r3, 32 ; SOFT-NEXT: clrldi r3, r3, 32
; SOFT-NEXT: bl __gnu_f2h_ieee ; SOFT-NEXT: bl __gnu_f2h_ieee
; SOFT-NEXT: nop ; SOFT-NEXT: nop
; SOFT-NEXT: clrldi r3, r3, 48 ; SOFT-NEXT: clrldi r3, r3, 48
; SOFT-NEXT: bl __gnu_h2f_ieee ; SOFT-NEXT: bl __gnu_h2f_ieee
Show All 9 Lines; SOFT-NEXT: blr
%r = sitofp i64 %a to half %r = sitofp i64 %a to half
store half %r, ptr %p store half %r, ptr %p
ret void ret void
} }
define i64 @test_fptoui_i64(ptr %p) #0 { define i64 @test_fptoui_i64(ptr %p) #0 {
; P8-LABEL: test_fptoui_i64: ; P8-LABEL: test_fptoui_i64:
; P8: # %bb.0: ; P8: # %bb.0:
; P8-NEXT: mflr r0 ; P8-NEXT: mflr r0
; P8-NEXT: std r0, 16(r1)
; P8-NEXT: stdu r1, -32(r1) ; P8-NEXT: stdu r1, -32(r1)
; P8-NEXT: std r0, 48(r1)
; P8-NEXT: lhz r3, 0(r3) ; P8-NEXT: lhz r3, 0(r3)
; P8-NEXT: bl __gnu_h2f_ieee ; P8-NEXT: bl __gnu_h2f_ieee
; P8-NEXT: nop ; P8-NEXT: nop
; P8-NEXT: xscvdpuxds f0, f1 ; P8-NEXT: xscvdpuxds f0, f1
; P8-NEXT: mffprd r3, f0 ; P8-NEXT: mffprd r3, f0
; P8-NEXT: addi r1, r1, 32 ; P8-NEXT: addi r1, r1, 32
; P8-NEXT: ld r0, 16(r1) ; P8-NEXT: ld r0, 16(r1)
; P8-NEXT: mtlr r0 ; P8-NEXT: mtlr r0
; P8-NEXT: blr ; P8-NEXT: blr
; ;
; CHECK-LABEL: test_fptoui_i64: ; CHECK-LABEL: test_fptoui_i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lhz r3, 0(r3) ; CHECK-NEXT: lhz r3, 0(r3)
; CHECK-NEXT: mtfprwz f0, r3 ; CHECK-NEXT: mtfprwz f0, r3
; CHECK-NEXT: xscvhpdp f0, f0 ; CHECK-NEXT: xscvhpdp f0, f0
; CHECK-NEXT: xscvdpuxds f0, f0 ; CHECK-NEXT: xscvdpuxds f0, f0
; CHECK-NEXT: mffprd r3, f0 ; CHECK-NEXT: mffprd r3, f0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; SOFT-LABEL: test_fptoui_i64: ; SOFT-LABEL: test_fptoui_i64:
; SOFT: # %bb.0: ; SOFT: # %bb.0:
; SOFT-NEXT: mflr r0 ; SOFT-NEXT: mflr r0
; SOFT-NEXT: std r0, 16(r1)
; SOFT-NEXT: stdu r1, -32(r1) ; SOFT-NEXT: stdu r1, -32(r1)
; SOFT-NEXT: std r0, 48(r1)
; SOFT-NEXT: lhz r3, 0(r3) ; SOFT-NEXT: lhz r3, 0(r3)
; SOFT-NEXT: bl __gnu_h2f_ieee ; SOFT-NEXT: bl __gnu_h2f_ieee
; SOFT-NEXT: nop ; SOFT-NEXT: nop
; SOFT-NEXT: bl __fixunssfdi ; SOFT-NEXT: bl __fixunssfdi
; SOFT-NEXT: nop ; SOFT-NEXT: nop
; SOFT-NEXT: addi r1, r1, 32 ; SOFT-NEXT: addi r1, r1, 32
; SOFT-NEXT: ld r0, 16(r1) ; SOFT-NEXT: ld r0, 16(r1)
; SOFT-NEXT: mtlr r0 ; SOFT-NEXT: mtlr r0
; SOFT-NEXT: blr ; SOFT-NEXT: blr
%a = load half, ptr %p, align 2 %a = load half, ptr %p, align 2
%r = fptoui half %a to i64 %r = fptoui half %a to i64
ret i64 %r ret i64 %r
} }
define void @test_uitofp_i64(i64 %a, ptr %p) #0 { define void @test_uitofp_i64(i64 %a, ptr %p) #0 {
; P8-LABEL: test_uitofp_i64: ; P8-LABEL: test_uitofp_i64:
; P8: # %bb.0: ; P8: # %bb.0:
; P8-NEXT: mflr r0 ; P8-NEXT: mflr r0
; P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; P8-NEXT: std r0, 16(r1)
; P8-NEXT: stdu r1, -48(r1) ; P8-NEXT: stdu r1, -48(r1)
; P8-NEXT: mtfprd f0, r3 ; P8-NEXT: mtfprd f0, r3
; P8-NEXT: std r0, 64(r1)
; P8-NEXT: mr r30, r4 ; P8-NEXT: mr r30, r4
; P8-NEXT: xscvuxdsp f1, f0 ; P8-NEXT: xscvuxdsp f1, f0
; P8-NEXT: bl __gnu_f2h_ieee ; P8-NEXT: bl __gnu_f2h_ieee
; P8-NEXT: nop ; P8-NEXT: nop
; P8-NEXT: sth r3, 0(r30) ; P8-NEXT: sth r3, 0(r30)
; P8-NEXT: addi r1, r1, 48 ; P8-NEXT: addi r1, r1, 48
; P8-NEXT: ld r0, 16(r1) ; P8-NEXT: ld r0, 16(r1)
; P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; P8-NEXT: mtlr r0 ; P8-NEXT: mtlr r0
; P8-NEXT: blr ; P8-NEXT: blr
; ;
; CHECK-LABEL: test_uitofp_i64: ; CHECK-LABEL: test_uitofp_i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: mtfprd f0, r3 ; CHECK-NEXT: mtfprd f0, r3
; CHECK-NEXT: xscvuxdsp f0, f0 ; CHECK-NEXT: xscvuxdsp f0, f0
; CHECK-NEXT: xscvdphp f0, f0 ; CHECK-NEXT: xscvdphp f0, f0
; CHECK-NEXT: mffprwz r3, f0 ; CHECK-NEXT: mffprwz r3, f0
; CHECK-NEXT: sth r3, 0(r4) ; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; SOFT-LABEL: test_uitofp_i64: ; SOFT-LABEL: test_uitofp_i64:
; SOFT: # %bb.0: ; SOFT: # %bb.0:
; SOFT-NEXT: mflr r0 ; SOFT-NEXT: mflr r0
; SOFT-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; SOFT-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; SOFT-NEXT: std r0, 16(r1)
; SOFT-NEXT: stdu r1, -48(r1) ; SOFT-NEXT: stdu r1, -48(r1)
; SOFT-NEXT: std r0, 64(r1)
; SOFT-NEXT: mr r30, r4 ; SOFT-NEXT: mr r30, r4
; SOFT-NEXT: bl __floatundisf ; SOFT-NEXT: bl __floatundisf
; SOFT-NEXT: nop ; SOFT-NEXT: nop
; SOFT-NEXT: bl __gnu_f2h_ieee ; SOFT-NEXT: bl __gnu_f2h_ieee
; SOFT-NEXT: nop ; SOFT-NEXT: nop
; SOFT-NEXT: clrldi r3, r3, 48 ; SOFT-NEXT: clrldi r3, r3, 48
; SOFT-NEXT: bl __gnu_h2f_ieee ; SOFT-NEXT: bl __gnu_h2f_ieee
; SOFT-NEXT: nop ; SOFT-NEXT: nop
; SOFT-NEXT: bl __gnu_f2h_ieee ; SOFT-NEXT: bl __gnu_f2h_ieee
; SOFT-NEXT: nop ; SOFT-NEXT: nop
; SOFT-NEXT: sth r3, 0(r30) ; SOFT-NEXT: sth r3, 0(r30)
; SOFT-NEXT: addi r1, r1, 48 ; SOFT-NEXT: addi r1, r1, 48
; SOFT-NEXT: ld r0, 16(r1) ; SOFT-NEXT: ld r0, 16(r1)
; SOFT-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; SOFT-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; SOFT-NEXT: mtlr r0 ; SOFT-NEXT: mtlr r0
; SOFT-NEXT: blr ; SOFT-NEXT: blr
%r = uitofp i64 %a to half %r = uitofp i64 %a to half
store half %r, ptr %p store half %r, ptr %p
ret void ret void
} }
define <4 x float> @test_extend32_vec4(ptr %p) #0 { define <4 x float> @test_extend32_vec4(ptr %p) #0 {
; P8-LABEL: test_extend32_vec4: ; P8-LABEL: test_extend32_vec4:
; P8: # %bb.0: ; P8: # %bb.0:
; P8-NEXT: mflr r0 ; P8-NEXT: mflr r0
; P8-NEXT: std r0, 16(r1)
; P8-NEXT: stdu r1, -112(r1) ; P8-NEXT: stdu r1, -112(r1)
; P8-NEXT: std r0, 128(r1)
; P8-NEXT: li r4, 48 ; P8-NEXT: li r4, 48
; P8-NEXT: std r30, 96(r1) # 8-byte Folded Spill ; P8-NEXT: std r30, 96(r1) # 8-byte Folded Spill
; P8-NEXT: mr r30, r3 ; P8-NEXT: mr r30, r3
; P8-NEXT: lhz r3, 6(r3) ; P8-NEXT: lhz r3, 6(r3)
; P8-NEXT: stxvd2x vs61, r1, r4 # 16-byte Folded Spill ; P8-NEXT: stxvd2x vs61, r1, r4 # 16-byte Folded Spill
; P8-NEXT: li r4, 64 ; P8-NEXT: li r4, 64
; P8-NEXT: stxvd2x vs62, r1, r4 # 16-byte Folded Spill ; P8-NEXT: stxvd2x vs62, r1, r4 # 16-byte Folded Spill
; P8-NEXT: li r4, 80 ; P8-NEXT: li r4, 80
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Lines
; ;
; SOFT-LABEL: test_extend32_vec4: ; SOFT-LABEL: test_extend32_vec4:
; SOFT: # %bb.0: ; SOFT: # %bb.0:
; SOFT-NEXT: mflr r0 ; SOFT-NEXT: mflr r0
; SOFT-NEXT: std r27, -40(r1) # 8-byte Folded Spill ; SOFT-NEXT: std r27, -40(r1) # 8-byte Folded Spill
; SOFT-NEXT: std r28, -32(r1) # 8-byte Folded Spill ; SOFT-NEXT: std r28, -32(r1) # 8-byte Folded Spill
; SOFT-NEXT: std r29, -24(r1) # 8-byte Folded Spill ; SOFT-NEXT: std r29, -24(r1) # 8-byte Folded Spill
; SOFT-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; SOFT-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; SOFT-NEXT: std r0, 16(r1)
; SOFT-NEXT: stdu r1, -80(r1) ; SOFT-NEXT: stdu r1, -80(r1)
; SOFT-NEXT: std r0, 96(r1)
; SOFT-NEXT: mr r30, r3 ; SOFT-NEXT: mr r30, r3
; SOFT-NEXT: lhz r3, 0(r3) ; SOFT-NEXT: lhz r3, 0(r3)
; SOFT-NEXT: bl __gnu_h2f_ieee ; SOFT-NEXT: bl __gnu_h2f_ieee
; SOFT-NEXT: nop ; SOFT-NEXT: nop
; SOFT-NEXT: mr r29, r3 ; SOFT-NEXT: mr r29, r3
; SOFT-NEXT: lhz r3, 2(r30) ; SOFT-NEXT: lhz r3, 2(r30)
; SOFT-NEXT: bl __gnu_h2f_ieee ; SOFT-NEXT: bl __gnu_h2f_ieee
; SOFT-NEXT: nop ; SOFT-NEXT: nop
Show All 20 Lines; SOFT-NEXT: blr
%a = load <4 x half>, ptr %p, align 8 %a = load <4 x half>, ptr %p, align 8
%b = fpext <4 x half> %a to <4 x float> %b = fpext <4 x half> %a to <4 x float>
ret <4 x float> %b ret <4 x float> %b
} }
define <4 x double> @test_extend64_vec4(ptr %p) #0 { define <4 x double> @test_extend64_vec4(ptr %p) #0 {
; P8-LABEL: test_extend64_vec4: ; P8-LABEL: test_extend64_vec4:
; P8: # %bb.0: ; P8: # %bb.0:
; P8-NEXT: mflr r0 ; P8-NEXT: mflr r0
; P8-NEXT: std r0, 16(r1)
; P8-NEXT: stdu r1, -112(r1) ; P8-NEXT: stdu r1, -112(r1)
; P8-NEXT: std r0, 128(r1)
; P8-NEXT: li r4, 48 ; P8-NEXT: li r4, 48
; P8-NEXT: std r30, 96(r1) # 8-byte Folded Spill ; P8-NEXT: std r30, 96(r1) # 8-byte Folded Spill
; P8-NEXT: mr r30, r3 ; P8-NEXT: mr r30, r3
; P8-NEXT: lhz r3, 6(r3) ; P8-NEXT: lhz r3, 6(r3)
; P8-NEXT: stxvd2x vs61, r1, r4 # 16-byte Folded Spill ; P8-NEXT: stxvd2x vs61, r1, r4 # 16-byte Folded Spill
; P8-NEXT: li r4, 64 ; P8-NEXT: li r4, 64
; P8-NEXT: stxvd2x vs62, r1, r4 # 16-byte Folded Spill ; P8-NEXT: stxvd2x vs62, r1, r4 # 16-byte Folded Spill
; P8-NEXT: li r4, 80 ; P8-NEXT: li r4, 80
▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
; ;
; SOFT-LABEL: test_extend64_vec4: ; SOFT-LABEL: test_extend64_vec4:
; SOFT: # %bb.0: ; SOFT: # %bb.0:
; SOFT-NEXT: mflr r0 ; SOFT-NEXT: mflr r0
; SOFT-NEXT: std r27, -40(r1) # 8-byte Folded Spill ; SOFT-NEXT: std r27, -40(r1) # 8-byte Folded Spill
; SOFT-NEXT: std r28, -32(r1) # 8-byte Folded Spill ; SOFT-NEXT: std r28, -32(r1) # 8-byte Folded Spill
; SOFT-NEXT: std r29, -24(r1) # 8-byte Folded Spill ; SOFT-NEXT: std r29, -24(r1) # 8-byte Folded Spill
; SOFT-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; SOFT-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; SOFT-NEXT: std r0, 16(r1)
; SOFT-NEXT: stdu r1, -80(r1) ; SOFT-NEXT: stdu r1, -80(r1)
; SOFT-NEXT: std r0, 96(r1)
; SOFT-NEXT: mr r30, r3 ; SOFT-NEXT: mr r30, r3
; SOFT-NEXT: lhz r3, 0(r3) ; SOFT-NEXT: lhz r3, 0(r3)
; SOFT-NEXT: bl __gnu_h2f_ieee ; SOFT-NEXT: bl __gnu_h2f_ieee
; SOFT-NEXT: nop ; SOFT-NEXT: nop
; SOFT-NEXT: bl __extendsfdf2 ; SOFT-NEXT: bl __extendsfdf2
; SOFT-NEXT: nop ; SOFT-NEXT: nop
; SOFT-NEXT: mr r29, r3 ; SOFT-NEXT: mr r29, r3
; SOFT-NEXT: lhz r3, 2(r30) ; SOFT-NEXT: lhz r3, 2(r30)
Show All 28 Lines; SOFT-NEXT: blr
%a = load <4 x half>, ptr %p, align 8 %a = load <4 x half>, ptr %p, align 8
%b = fpext <4 x half> %a to <4 x double> %b = fpext <4 x half> %a to <4 x double>
ret <4 x double> %b ret <4 x double> %b
} }
define void @test_trunc32_vec4(<4 x float> %a, ptr %p) #0 { define void @test_trunc32_vec4(<4 x float> %a, ptr %p) #0 {
; P8-LABEL: test_trunc32_vec4: ; P8-LABEL: test_trunc32_vec4:
; P8: # %bb.0: ; P8: # %bb.0:
; P8-NEXT: mflr r0 ; P8-NEXT: mflr r0
; P8-NEXT: std r0, 16(r1)
; P8-NEXT: stdu r1, -112(r1) ; P8-NEXT: stdu r1, -112(r1)
; P8-NEXT: xxsldwi vs0, vs34, vs34, 3 ; P8-NEXT: xxsldwi vs0, vs34, vs34, 3
; P8-NEXT: li r3, 48 ; P8-NEXT: li r3, 48
; P8-NEXT: std r0, 128(r1)
; P8-NEXT: std r27, 72(r1) # 8-byte Folded Spill ; P8-NEXT: std r27, 72(r1) # 8-byte Folded Spill
; P8-NEXT: std r28, 80(r1) # 8-byte Folded Spill ; P8-NEXT: std r28, 80(r1) # 8-byte Folded Spill
; P8-NEXT: std r29, 88(r1) # 8-byte Folded Spill ; P8-NEXT: std r29, 88(r1) # 8-byte Folded Spill
; P8-NEXT: std r30, 96(r1) # 8-byte Folded Spill
; P8-NEXT: mr r30, r5
; P8-NEXT: xscvspdpn f1, vs0 ; P8-NEXT: xscvspdpn f1, vs0
; P8-NEXT: std r30, 96(r1) # 8-byte Folded Spill
; P8-NEXT: stxvd2x vs63, r1, r3 # 16-byte Folded Spill ; P8-NEXT: stxvd2x vs63, r1, r3 # 16-byte Folded Spill
; P8-NEXT: mr r30, r5
; P8-NEXT: vmr v31, v2 ; P8-NEXT: vmr v31, v2
; P8-NEXT: bl __gnu_f2h_ieee ; P8-NEXT: bl __gnu_f2h_ieee
; P8-NEXT: nop ; P8-NEXT: nop
; P8-NEXT: xxswapd vs0, vs63 ; P8-NEXT: xxswapd vs0, vs63
; P8-NEXT: mr r29, r3 ; P8-NEXT: mr r29, r3
; P8-NEXT: xscvspdpn f1, vs0 ; P8-NEXT: xscvspdpn f1, vs0
; P8-NEXT: bl __gnu_f2h_ieee ; P8-NEXT: bl __gnu_f2h_ieee
; P8-NEXT: nop ; P8-NEXT: nop
▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
; SOFT-LABEL: test_trunc32_vec4: ; SOFT-LABEL: test_trunc32_vec4:
; SOFT: # %bb.0: ; SOFT: # %bb.0:
; SOFT-NEXT: mflr r0 ; SOFT-NEXT: mflr r0
; SOFT-NEXT: std r26, -48(r1) # 8-byte Folded Spill ; SOFT-NEXT: std r26, -48(r1) # 8-byte Folded Spill
; SOFT-NEXT: std r27, -40(r1) # 8-byte Folded Spill ; SOFT-NEXT: std r27, -40(r1) # 8-byte Folded Spill
; SOFT-NEXT: std r28, -32(r1) # 8-byte Folded Spill ; SOFT-NEXT: std r28, -32(r1) # 8-byte Folded Spill
; SOFT-NEXT: std r29, -24(r1) # 8-byte Folded Spill ; SOFT-NEXT: std r29, -24(r1) # 8-byte Folded Spill
; SOFT-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; SOFT-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; SOFT-NEXT: std r0, 16(r1)
; SOFT-NEXT: stdu r1, -80(r1) ; SOFT-NEXT: stdu r1, -80(r1)
; SOFT-NEXT: mr r27, r3 ; SOFT-NEXT: mr r27, r3
; SOFT-NEXT: clrldi r3, r6, 32 ; SOFT-NEXT: clrldi r3, r6, 32
; SOFT-NEXT: std r0, 96(r1)
; SOFT-NEXT: mr r30, r7 ; SOFT-NEXT: mr r30, r7
; SOFT-NEXT: mr r29, r5 ; SOFT-NEXT: mr r29, r5
; SOFT-NEXT: mr r28, r4 ; SOFT-NEXT: mr r28, r4
; SOFT-NEXT: bl __gnu_f2h_ieee ; SOFT-NEXT: bl __gnu_f2h_ieee
; SOFT-NEXT: nop ; SOFT-NEXT: nop
; SOFT-NEXT: mr r26, r3 ; SOFT-NEXT: mr r26, r3
; SOFT-NEXT: clrldi r3, r29, 32 ; SOFT-NEXT: clrldi r3, r29, 32
; SOFT-NEXT: bl __gnu_f2h_ieee ; SOFT-NEXT: bl __gnu_f2h_ieee
▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Lines; SOFT-NEXT: blr
%v = fptrunc <4 x float> %a to <4 x half> %v = fptrunc <4 x float> %a to <4 x half>
store <4 x half> %v, ptr %p store <4 x half> %v, ptr %p
ret void ret void
} }
define void @test_trunc64_vec4(<4 x double> %a, ptr %p) #0 { define void @test_trunc64_vec4(<4 x double> %a, ptr %p) #0 {
; P8-LABEL: test_trunc64_vec4: ; P8-LABEL: test_trunc64_vec4:
; P8: # %bb.0: ; P8: # %bb.0:
; P8-NEXT: mflr r0 ; P8-NEXT: mflr r0
; P8-NEXT: std r0, 16(r1)
; P8-NEXT: stdu r1, -128(r1) ; P8-NEXT: stdu r1, -128(r1)
; P8-NEXT: li r3, 48 ; P8-NEXT: li r3, 48
; P8-NEXT: std r0, 144(r1)
; P8-NEXT: xxswapd vs1, vs34 ; P8-NEXT: xxswapd vs1, vs34
; P8-NEXT: std r27, 88(r1) # 8-byte Folded Spill ; P8-NEXT: std r27, 88(r1) # 8-byte Folded Spill
; P8-NEXT: std r28, 96(r1) # 8-byte Folded Spill ; P8-NEXT: std r28, 96(r1) # 8-byte Folded Spill
; P8-NEXT: std r29, 104(r1) # 8-byte Folded Spill ; P8-NEXT: std r29, 104(r1) # 8-byte Folded Spill
; P8-NEXT: std r30, 112(r1) # 8-byte Folded Spill
; P8-NEXT: mr r30, r7
; P8-NEXT: # kill: def $f1 killed $f1 killed $vsl1 ; P8-NEXT: # kill: def $f1 killed $f1 killed $vsl1
; P8-NEXT: stxvd2x vs62, r1, r3 # 16-byte Folded Spill ; P8-NEXT: stxvd2x vs62, r1, r3 # 16-byte Folded Spill
; P8-NEXT: li r3, 64 ; P8-NEXT: li r3, 64
; P8-NEXT: std r30, 112(r1) # 8-byte Folded Spill
; P8-NEXT: mr r30, r7
; P8-NEXT: vmr v30, v2 ; P8-NEXT: vmr v30, v2
; P8-NEXT: stxvd2x vs63, r1, r3 # 16-byte Folded Spill ; P8-NEXT: stxvd2x vs63, r1, r3 # 16-byte Folded Spill
; P8-NEXT: vmr v31, v3 ; P8-NEXT: vmr v31, v3
; P8-NEXT: bl __truncdfhf2 ; P8-NEXT: bl __truncdfhf2
; P8-NEXT: nop ; P8-NEXT: nop
; P8-NEXT: xxswapd vs1, vs63 ; P8-NEXT: xxswapd vs1, vs63
; P8-NEXT: mr r29, r3 ; P8-NEXT: mr r29, r3
; P8-NEXT: # kill: def $f1 killed $f1 killed $vsl1 ; P8-NEXT: # kill: def $f1 killed $f1 killed $vsl1
▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Lines
; SOFT-LABEL: test_trunc64_vec4: ; SOFT-LABEL: test_trunc64_vec4:
; SOFT: # %bb.0: ; SOFT: # %bb.0:
; SOFT-NEXT: mflr r0 ; SOFT-NEXT: mflr r0
; SOFT-NEXT: std r26, -48(r1) # 8-byte Folded Spill ; SOFT-NEXT: std r26, -48(r1) # 8-byte Folded Spill
; SOFT-NEXT: std r27, -40(r1) # 8-byte Folded Spill ; SOFT-NEXT: std r27, -40(r1) # 8-byte Folded Spill
; SOFT-NEXT: std r28, -32(r1) # 8-byte Folded Spill ; SOFT-NEXT: std r28, -32(r1) # 8-byte Folded Spill
; SOFT-NEXT: std r29, -24(r1) # 8-byte Folded Spill ; SOFT-NEXT: std r29, -24(r1) # 8-byte Folded Spill
; SOFT-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; SOFT-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; SOFT-NEXT: std r0, 16(r1)
; SOFT-NEXT: stdu r1, -80(r1) ; SOFT-NEXT: stdu r1, -80(r1)
; SOFT-NEXT: mr r27, r3 ; SOFT-NEXT: mr r27, r3
; SOFT-NEXT: mr r3, r6 ; SOFT-NEXT: mr r3, r6
; SOFT-NEXT: std r0, 96(r1)
; SOFT-NEXT: mr r30, r7 ; SOFT-NEXT: mr r30, r7
; SOFT-NEXT: mr r29, r5 ; SOFT-NEXT: mr r29, r5
; SOFT-NEXT: mr r28, r4 ; SOFT-NEXT: mr r28, r4
; SOFT-NEXT: bl __truncdfhf2 ; SOFT-NEXT: bl __truncdfhf2
; SOFT-NEXT: nop ; SOFT-NEXT: nop
; SOFT-NEXT: mr r26, r3 ; SOFT-NEXT: mr r26, r3
; SOFT-NEXT: mr r3, r29 ; SOFT-NEXT: mr r3, r29
; SOFT-NEXT: bl __truncdfhf2 ; SOFT-NEXT: bl __truncdfhf2
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines; SOFT-NEXT: blr
ret void ret void
} }
define float @test_sitofp_fadd_i32(i32 %a, ptr %b) #0 { define float @test_sitofp_fadd_i32(i32 %a, ptr %b) #0 {
; P8-LABEL: test_sitofp_fadd_i32: ; P8-LABEL: test_sitofp_fadd_i32:
; P8: # %bb.0: ; P8: # %bb.0:
; P8-NEXT: mflr r0 ; P8-NEXT: mflr r0
; P8-NEXT: std r30, -24(r1) # 8-byte Folded Spill ; P8-NEXT: std r30, -24(r1) # 8-byte Folded Spill
; P8-NEXT: stfd f31, -8(r1) # 8-byte Folded Spill ; P8-NEXT: stfd f31, -8(r1) # 8-byte Folded Spill
; P8-NEXT: std r0, 16(r1)
; P8-NEXT: stdu r1, -64(r1) ; P8-NEXT: stdu r1, -64(r1)
; P8-NEXT: std r0, 80(r1)
; P8-NEXT: mr r30, r3 ; P8-NEXT: mr r30, r3
; P8-NEXT: lhz r3, 0(r4) ; P8-NEXT: lhz r3, 0(r4)
; P8-NEXT: bl __gnu_h2f_ieee ; P8-NEXT: bl __gnu_h2f_ieee
; P8-NEXT: nop ; P8-NEXT: nop
; P8-NEXT: mtfprwa f0, r30 ; P8-NEXT: mtfprwa f0, r30
; P8-NEXT: fmr f31, f1 ; P8-NEXT: fmr f31, f1
; P8-NEXT: xscvsxdsp f1, f0 ; P8-NEXT: xscvsxdsp f1, f0
; P8-NEXT: bl __gnu_f2h_ieee ; P8-NEXT: bl __gnu_f2h_ieee
Show All 24 Lines
; CHECK-NEXT: xsaddsp f1, f0, f1 ; CHECK-NEXT: xsaddsp f1, f0, f1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; SOFT-LABEL: test_sitofp_fadd_i32: ; SOFT-LABEL: test_sitofp_fadd_i32:
; SOFT: # %bb.0: ; SOFT: # %bb.0:
; SOFT-NEXT: mflr r0 ; SOFT-NEXT: mflr r0
; SOFT-NEXT: std r29, -24(r1) # 8-byte Folded Spill ; SOFT-NEXT: std r29, -24(r1) # 8-byte Folded Spill
; SOFT-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; SOFT-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; SOFT-NEXT: std r0, 16(r1)
; SOFT-NEXT: stdu r1, -64(r1) ; SOFT-NEXT: stdu r1, -64(r1)
; SOFT-NEXT: std r0, 80(r1)
; SOFT-NEXT: mr r30, r3 ; SOFT-NEXT: mr r30, r3
; SOFT-NEXT: lhz r3, 0(r4) ; SOFT-NEXT: lhz r3, 0(r4)
; SOFT-NEXT: bl __gnu_h2f_ieee ; SOFT-NEXT: bl __gnu_h2f_ieee
; SOFT-NEXT: nop ; SOFT-NEXT: nop
; SOFT-NEXT: mr r29, r3 ; SOFT-NEXT: mr r29, r3
; SOFT-NEXT: extsw r3, r30 ; SOFT-NEXT: extsw r3, r30
; SOFT-NEXT: bl __floatsisf ; SOFT-NEXT: bl __floatsisf
; SOFT-NEXT: nop ; SOFT-NEXT: nop
Show All 18 Lines; SOFT-NEXT: blr
%tmp2 = fadd half %tmp0, %tmp1 %tmp2 = fadd half %tmp0, %tmp1
%tmp3 = fpext half %tmp2 to float %tmp3 = fpext half %tmp2 to float
ret float %tmp3 ret float %tmp3
} }
define half @PR40273(half) #0 { define half @PR40273(half) #0 {
; P8-LABEL: PR40273: ; P8-LABEL: PR40273:
; P8: # %bb.0: ; P8: # %bb.0:
; P8-NEXT: mflr r0 ; P8-NEXT: mflr r0
; P8-NEXT: std r0, 16(r1)
; P8-NEXT: stdu r1, -32(r1) ; P8-NEXT: stdu r1, -32(r1)
; P8-NEXT: std r0, 48(r1)
; P8-NEXT: bl __gnu_f2h_ieee ; P8-NEXT: bl __gnu_f2h_ieee
; P8-NEXT: nop ; P8-NEXT: nop
; P8-NEXT: clrldi r3, r3, 48 ; P8-NEXT: clrldi r3, r3, 48
; P8-NEXT: bl __gnu_h2f_ieee ; P8-NEXT: bl __gnu_h2f_ieee
; P8-NEXT: nop ; P8-NEXT: nop
; P8-NEXT: xxlxor f0, f0, f0 ; P8-NEXT: xxlxor f0, f0, f0
; P8-NEXT: fcmpu cr0, f1, f0 ; P8-NEXT: fcmpu cr0, f1, f0
; P8-NEXT: beq cr0, .LBB20_2 ; P8-NEXT: beq cr0, .LBB20_2
Show All 20 Lines
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: addis r3, r2, .LCPI20_0@toc@ha ; CHECK-NEXT: addis r3, r2, .LCPI20_0@toc@ha
; CHECK-NEXT: lfs f1, .LCPI20_0@toc@l(r3) ; CHECK-NEXT: lfs f1, .LCPI20_0@toc@l(r3)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; SOFT-LABEL: PR40273: ; SOFT-LABEL: PR40273:
; SOFT: # %bb.0: ; SOFT: # %bb.0:
; SOFT-NEXT: mflr r0 ; SOFT-NEXT: mflr r0
; SOFT-NEXT: std r0, 16(r1)
; SOFT-NEXT: stdu r1, -32(r1) ; SOFT-NEXT: stdu r1, -32(r1)
; SOFT-NEXT: clrldi r3, r3, 48 ; SOFT-NEXT: clrldi r3, r3, 48
; SOFT-NEXT: std r0, 48(r1)
; SOFT-NEXT: bl __gnu_h2f_ieee ; SOFT-NEXT: bl __gnu_h2f_ieee
; SOFT-NEXT: nop ; SOFT-NEXT: nop
; SOFT-NEXT: li r4, 0 ; SOFT-NEXT: li r4, 0
; SOFT-NEXT: bl __nesf2 ; SOFT-NEXT: bl __nesf2
; SOFT-NEXT: nop ; SOFT-NEXT: nop
; SOFT-NEXT: cmplwi r3, 0 ; SOFT-NEXT: cmplwi r3, 0
; SOFT-NEXT: lis r3, 16256 ; SOFT-NEXT: lis r3, 16256
; SOFT-NEXT: iseleq r3, 0, r3 ; SOFT-NEXT: iseleq r3, 0, r3
Show All 11 Lines

llvm/test/CodeGen/PowerPC/inlineasm-i64-reg.ll

Show First 20 Lines • Show All 67 Lines • ▼ Show 20 Linesentry:
%0 = call { i64, i64 } asm sideeffect "sc", "={r0},={r3},{r0},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{cr0},~{memory}"(i64 1076) %0 = call { i64, i64 } asm sideeffect "sc", "={r0},={r3},{r0},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{cr0},~{memory}"(i64 1076)
%asmresult1.i = extractvalue { i64, i64 } %0, 1 %asmresult1.i = extractvalue { i64, i64 } %0, 1
%conv.i = trunc i64 %asmresult1.i to i32 %conv.i = trunc i64 %asmresult1.i to i32
%cmp = icmp eq i32 %conv.i, 0 %cmp = icmp eq i32 %conv.i, 0
br i1 %cmp, label %if.then, label %if.end br i1 %cmp, label %if.then, label %if.end
; CHECK-LABEL: @main ; CHECK-LABEL: @main
; CHECK-DAG: mr [[REG:[0-9]+]], 3 ; CHECK: mr [[REG:[0-9]+]], 3
; CHECK-DAG: li 0, 1076 ; CHECK: std 0,
; CHECK: stw [[REG]], ; CHECK: stw [[REG]],
; CHECK: #APP ; CHECK: #APP
; CHECK: sc ; CHECK: sc
; CHECK: #NO_APP ; CHECK: #NO_APP
; CHECK: cmpwi [[REG]], 1 ; CHECK: cmpwi [[REG]], 1
; CHECK: blr ; CHECK: blr
Show All 22 Lines

llvm/test/CodeGen/PowerPC/jump-tables-collapse-rotate.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -o - \ ; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -o - \
; RUN: -ppc-asm-full-reg-names -verify-machineinstrs %s | FileCheck %s ; RUN: -ppc-asm-full-reg-names -verify-machineinstrs %s | FileCheck %s
; Function Attrs: nounwind ; Function Attrs: nounwind
define dso_local zeroext i32 @test(i32 signext %l) nounwind { define dso_local zeroext i32 @test(i32 signext %l) nounwind {
; CHECK-LABEL: test: ; CHECK-LABEL: test:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr r0 ; CHECK-NEXT: mflr r0
; CHECK-NEXT: std r0, 16(r1)
; CHECK-NEXT: stdu r1, -32(r1) ; CHECK-NEXT: stdu r1, -32(r1)
; CHECK-NEXT: addi r3, r3, -1 ; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: std r0, 48(r1)
; CHECK-NEXT: cmplwi r3, 5 ; CHECK-NEXT: cmplwi r3, 5
; CHECK-NEXT: bgt cr0, .LBB0_3 ; CHECK-NEXT: bgt cr0, .LBB0_3
; CHECK-NEXT: # %bb.1: # %entry ; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: rldic r3, r3, 2, 30 ; CHECK-NEXT: rldic r3, r3, 2, 30
; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: lwax r3, r3, r4 ; CHECK-NEXT: lwax r3, r3, r4
; CHECK-NEXT: add r3, r3, r4 ; CHECK-NEXT: add r3, r3, r4
▲ Show 20 Lines • Show All 100 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/larger-than-red-zone.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \ ; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s ; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s
define dso_local signext i32 @caller(i32 signext %a, i32 signext %b) local_unnamed_addr { define dso_local signext i32 @caller(i32 signext %a, i32 signext %b) local_unnamed_addr {
; CHECK-LABEL: caller: ; CHECK-LABEL: caller:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr r0 ; CHECK-NEXT: mflr r0
; CHECK-NEXT: std r0, 16(r1)
; CHECK-NEXT: stdu r1, -320(r1) ; CHECK-NEXT: stdu r1, -320(r1)
; CHECK-NEXT: std r0, 336(r1)
; CHECK-NEXT: .cfi_def_cfa_offset 320 ; CHECK-NEXT: .cfi_def_cfa_offset 320
; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: .cfi_offset r14, -288 ; CHECK-NEXT: .cfi_offset r14, -288
; CHECK-NEXT: .cfi_offset r15, -280 ; CHECK-NEXT: .cfi_offset r15, -280
; CHECK-NEXT: .cfi_offset r16, -272 ; CHECK-NEXT: .cfi_offset r16, -272
; CHECK-NEXT: .cfi_offset r17, -264 ; CHECK-NEXT: .cfi_offset r17, -264
; CHECK-NEXT: .cfi_offset r18, -256 ; CHECK-NEXT: .cfi_offset r18, -256
; CHECK-NEXT: .cfi_offset r19, -248 ; CHECK-NEXT: .cfi_offset r19, -248
▲ Show 20 Lines • Show All 70 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/lower-intrinsics-afn-mass_notail.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -enable-ppc-gen-scalar-mass -O3 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck --check-prefix=CHECK-LNX %s ; RUN: llc -enable-ppc-gen-scalar-mass -O3 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck --check-prefix=CHECK-LNX %s
; RUN: llc -enable-ppc-gen-scalar-mass -O3 -mtriple=powerpc-ibm-aix-xcoff < %s | FileCheck --check-prefix=CHECK-AIX %s ; RUN: llc -enable-ppc-gen-scalar-mass -O3 -mtriple=powerpc-ibm-aix-xcoff < %s | FileCheck --check-prefix=CHECK-AIX %s
define void @cos_f64(ptr %arg) { define void @cos_f64(ptr %arg) {
; CHECK-LNX-LABEL: cos_f64: ; CHECK-LNX-LABEL: cos_f64:
; CHECK-LNX: # %bb.0: # %bb ; CHECK-LNX: # %bb.0: # %bb
; CHECK-LNX-NEXT: mflr 0 ; CHECK-LNX-NEXT: mflr 0
; CHECK-LNX-NEXT: .cfi_def_cfa_offset 48 ; CHECK-LNX-NEXT: .cfi_def_cfa_offset 48
; CHECK-LNX-NEXT: .cfi_offset lr, 16 ; CHECK-LNX-NEXT: .cfi_offset lr, 16
; CHECK-LNX-NEXT: .cfi_offset f31, -8 ; CHECK-LNX-NEXT: .cfi_offset f31, -8
; CHECK-LNX-NEXT: stfd 31, -8(1) # 8-byte Folded Spill ; CHECK-LNX-NEXT: stfd 31, -8(1) # 8-byte Folded Spill
; CHECK-LNX-NEXT: std 0, 16(1)
; CHECK-LNX-NEXT: stdu 1, -48(1) ; CHECK-LNX-NEXT: stdu 1, -48(1)
; CHECK-LNX-NEXT: addis 3, 2, .LCPI0_0@toc@ha ; CHECK-LNX-NEXT: addis 3, 2, .LCPI0_0@toc@ha
; CHECK-LNX-NEXT: std 0, 64(1)
; CHECK-LNX-NEXT: xssqrtdp 31, 0 ; CHECK-LNX-NEXT: xssqrtdp 31, 0
; CHECK-LNX-NEXT: lfs 1, .LCPI0_0@toc@l(3) ; CHECK-LNX-NEXT: lfs 1, .LCPI0_0@toc@l(3)
; CHECK-LNX-NEXT: bl __xl_cos ; CHECK-LNX-NEXT: bl __xl_cos
; CHECK-LNX-NEXT: nop ; CHECK-LNX-NEXT: nop
; CHECK-LNX-NEXT: xsmuldp 0, 31, 1 ; CHECK-LNX-NEXT: xsmuldp 0, 31, 1
; CHECK-LNX-NEXT: .p2align 4 ; CHECK-LNX-NEXT: .p2align 4
; CHECK-LNX-NEXT: .LBB0_1: # %bb2 ; CHECK-LNX-NEXT: .LBB0_1: # %bb2
; CHECK-LNX-NEXT: # ; CHECK-LNX-NEXT: #
; CHECK-LNX-NEXT: stfd 0, 0(3) ; CHECK-LNX-NEXT: stfd 0, 0(3)
; CHECK-LNX-NEXT: b .LBB0_1 ; CHECK-LNX-NEXT: b .LBB0_1
; ;
; CHECK-AIX-LABEL: cos_f64: ; CHECK-AIX-LABEL: cos_f64:
; CHECK-AIX: # %bb.0: # %bb ; CHECK-AIX: # %bb.0: # %bb
; CHECK-AIX-NEXT: mflr 0 ; CHECK-AIX-NEXT: mflr 0
; CHECK-AIX-NEXT: stw 0, 8(1)
; CHECK-AIX-NEXT: stwu 1, -64(1) ; CHECK-AIX-NEXT: stwu 1, -64(1)
; CHECK-AIX-NEXT: stw 0, 72(1)
; CHECK-AIX-NEXT: stfd 31, 56(1) # 8-byte Folded Spill ; CHECK-AIX-NEXT: stfd 31, 56(1) # 8-byte Folded Spill
; CHECK-AIX-NEXT: bl .sqrt[PR] ; CHECK-AIX-NEXT: bl .sqrt[PR]
; CHECK-AIX-NEXT: nop ; CHECK-AIX-NEXT: nop
; CHECK-AIX-NEXT: lwz 3, L..C0(2) # %const.0 ; CHECK-AIX-NEXT: lwz 3, L..C0(2) # %const.0
; CHECK-AIX-NEXT: fmr 31, 1 ; CHECK-AIX-NEXT: fmr 31, 1
; CHECK-AIX-NEXT: lfs 0, 0(3) ; CHECK-AIX-NEXT: lfs 0, 0(3)
; CHECK-AIX-NEXT: fmr 1, 0 ; CHECK-AIX-NEXT: fmr 1, 0
; CHECK-AIX-NEXT: bl .__xl_cos[PR] ; CHECK-AIX-NEXT: bl .__xl_cos[PR]
Show All 21 Lines
define void @log_f64(ptr %arg) { define void @log_f64(ptr %arg) {
; CHECK-LNX-LABEL: log_f64: ; CHECK-LNX-LABEL: log_f64:
; CHECK-LNX: # %bb.0: # %bb ; CHECK-LNX: # %bb.0: # %bb
; CHECK-LNX-NEXT: mflr 0 ; CHECK-LNX-NEXT: mflr 0
; CHECK-LNX-NEXT: .cfi_def_cfa_offset 48 ; CHECK-LNX-NEXT: .cfi_def_cfa_offset 48
; CHECK-LNX-NEXT: .cfi_offset lr, 16 ; CHECK-LNX-NEXT: .cfi_offset lr, 16
; CHECK-LNX-NEXT: .cfi_offset f31, -8 ; CHECK-LNX-NEXT: .cfi_offset f31, -8
; CHECK-LNX-NEXT: stfd 31, -8(1) # 8-byte Folded Spill ; CHECK-LNX-NEXT: stfd 31, -8(1) # 8-byte Folded Spill
; CHECK-LNX-NEXT: std 0, 16(1)
; CHECK-LNX-NEXT: stdu 1, -48(1) ; CHECK-LNX-NEXT: stdu 1, -48(1)
; CHECK-LNX-NEXT: addis 3, 2, .LCPI1_0@toc@ha ; CHECK-LNX-NEXT: addis 3, 2, .LCPI1_0@toc@ha
; CHECK-LNX-NEXT: std 0, 64(1)
; CHECK-LNX-NEXT: xssqrtdp 31, 0 ; CHECK-LNX-NEXT: xssqrtdp 31, 0
; CHECK-LNX-NEXT: lfs 1, .LCPI1_0@toc@l(3) ; CHECK-LNX-NEXT: lfs 1, .LCPI1_0@toc@l(3)
; CHECK-LNX-NEXT: bl __xl_log ; CHECK-LNX-NEXT: bl __xl_log
; CHECK-LNX-NEXT: nop ; CHECK-LNX-NEXT: nop
; CHECK-LNX-NEXT: xsmuldp 0, 31, 1 ; CHECK-LNX-NEXT: xsmuldp 0, 31, 1
; CHECK-LNX-NEXT: .p2align 4 ; CHECK-LNX-NEXT: .p2align 4
; CHECK-LNX-NEXT: .LBB1_1: # %bb2 ; CHECK-LNX-NEXT: .LBB1_1: # %bb2
; CHECK-LNX-NEXT: # ; CHECK-LNX-NEXT: #
; CHECK-LNX-NEXT: stfd 0, 0(3) ; CHECK-LNX-NEXT: stfd 0, 0(3)
; CHECK-LNX-NEXT: b .LBB1_1 ; CHECK-LNX-NEXT: b .LBB1_1
; ;
; CHECK-AIX-LABEL: log_f64: ; CHECK-AIX-LABEL: log_f64:
; CHECK-AIX: # %bb.0: # %bb ; CHECK-AIX: # %bb.0: # %bb
; CHECK-AIX-NEXT: mflr 0 ; CHECK-AIX-NEXT: mflr 0
; CHECK-AIX-NEXT: stw 0, 8(1)
; CHECK-AIX-NEXT: stwu 1, -64(1) ; CHECK-AIX-NEXT: stwu 1, -64(1)
; CHECK-AIX-NEXT: stw 0, 72(1)
; CHECK-AIX-NEXT: stfd 31, 56(1) # 8-byte Folded Spill ; CHECK-AIX-NEXT: stfd 31, 56(1) # 8-byte Folded Spill
; CHECK-AIX-NEXT: bl .sqrt[PR] ; CHECK-AIX-NEXT: bl .sqrt[PR]
; CHECK-AIX-NEXT: nop ; CHECK-AIX-NEXT: nop
; CHECK-AIX-NEXT: lwz 3, L..C1(2) # %const.0 ; CHECK-AIX-NEXT: lwz 3, L..C1(2) # %const.0
; CHECK-AIX-NEXT: fmr 31, 1 ; CHECK-AIX-NEXT: fmr 31, 1
; CHECK-AIX-NEXT: lfs 0, 0(3) ; CHECK-AIX-NEXT: lfs 0, 0(3)
; CHECK-AIX-NEXT: fmr 1, 0 ; CHECK-AIX-NEXT: fmr 1, 0
; CHECK-AIX-NEXT: bl .__xl_log[PR] ; CHECK-AIX-NEXT: bl .__xl_log[PR]
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llvm/test/CodeGen/PowerPC/lower-intrinsics-fast-mass_notail.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -enable-ppc-gen-scalar-mass -O3 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck --check-prefix=CHECK-LNX %s ; RUN: llc -enable-ppc-gen-scalar-mass -O3 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck --check-prefix=CHECK-LNX %s
; RUN: llc -enable-ppc-gen-scalar-mass -O3 -mtriple=powerpc-ibm-aix-xcoff < %s | FileCheck --check-prefix=CHECK-AIX %s ; RUN: llc -enable-ppc-gen-scalar-mass -O3 -mtriple=powerpc-ibm-aix-xcoff < %s | FileCheck --check-prefix=CHECK-AIX %s
define void @cos_f64(ptr %arg) { define void @cos_f64(ptr %arg) {
; CHECK-LNX-LABEL: cos_f64: ; CHECK-LNX-LABEL: cos_f64:
; CHECK-LNX: # %bb.0: # %bb ; CHECK-LNX: # %bb.0: # %bb
; CHECK-LNX-NEXT: mflr 0 ; CHECK-LNX-NEXT: mflr 0
; CHECK-LNX-NEXT: std 0, 16(1)
; CHECK-LNX-NEXT: stdu 1, -32(1) ; CHECK-LNX-NEXT: stdu 1, -32(1)
; CHECK-LNX-NEXT: std 0, 48(1)
; CHECK-LNX-NEXT: .cfi_def_cfa_offset 32 ; CHECK-LNX-NEXT: .cfi_def_cfa_offset 32
; CHECK-LNX-NEXT: .cfi_offset lr, 16 ; CHECK-LNX-NEXT: .cfi_offset lr, 16
; CHECK-LNX-NEXT: addis 3, 2, .LCPI0_0@toc@ha ; CHECK-LNX-NEXT: addis 3, 2, .LCPI0_0@toc@ha
; CHECK-LNX-NEXT: lfs 1, .LCPI0_0@toc@l(3) ; CHECK-LNX-NEXT: lfs 1, .LCPI0_0@toc@l(3)
; CHECK-LNX-NEXT: bl __xl_cos_finite ; CHECK-LNX-NEXT: bl __xl_cos_finite
; CHECK-LNX-NEXT: nop ; CHECK-LNX-NEXT: nop
; CHECK-LNX-NEXT: xssqrtdp 0, 0 ; CHECK-LNX-NEXT: xssqrtdp 0, 0
; CHECK-LNX-NEXT: xsmuldp 0, 0, 1 ; CHECK-LNX-NEXT: xsmuldp 0, 0, 1
; CHECK-LNX-NEXT: .p2align 4 ; CHECK-LNX-NEXT: .p2align 4
; CHECK-LNX-NEXT: .LBB0_1: # %bb2 ; CHECK-LNX-NEXT: .LBB0_1: # %bb2
; CHECK-LNX-NEXT: # ; CHECK-LNX-NEXT: #
; CHECK-LNX-NEXT: stfd 0, 0(3) ; CHECK-LNX-NEXT: stfd 0, 0(3)
; CHECK-LNX-NEXT: b .LBB0_1 ; CHECK-LNX-NEXT: b .LBB0_1
; ;
; CHECK-AIX-LABEL: cos_f64: ; CHECK-AIX-LABEL: cos_f64:
; CHECK-AIX: # %bb.0: # %bb ; CHECK-AIX: # %bb.0: # %bb
; CHECK-AIX-NEXT: mflr 0 ; CHECK-AIX-NEXT: mflr 0
; CHECK-AIX-NEXT: stw 0, 8(1)
; CHECK-AIX-NEXT: stwu 1, -64(1) ; CHECK-AIX-NEXT: stwu 1, -64(1)
; CHECK-AIX-NEXT: stw 0, 72(1)
; CHECK-AIX-NEXT: stfd 31, 56(1) # 8-byte Folded Spill ; CHECK-AIX-NEXT: stfd 31, 56(1) # 8-byte Folded Spill
; CHECK-AIX-NEXT: bl .sqrt[PR] ; CHECK-AIX-NEXT: bl .sqrt[PR]
; CHECK-AIX-NEXT: nop ; CHECK-AIX-NEXT: nop
; CHECK-AIX-NEXT: lwz 3, L..C0(2) # %const.0 ; CHECK-AIX-NEXT: lwz 3, L..C0(2) # %const.0
; CHECK-AIX-NEXT: fmr 31, 1 ; CHECK-AIX-NEXT: fmr 31, 1
; CHECK-AIX-NEXT: lfs 0, 0(3) ; CHECK-AIX-NEXT: lfs 0, 0(3)
; CHECK-AIX-NEXT: fmr 1, 0 ; CHECK-AIX-NEXT: fmr 1, 0
; CHECK-AIX-NEXT: bl .__xl_cos_finite[PR] ; CHECK-AIX-NEXT: bl .__xl_cos_finite[PR]
Show All 17 Linesbb2:
store double %i10, ptr %i1, align 8 store double %i10, ptr %i1, align 8
br label %bb2 br label %bb2
} }
define void @log_f64(ptr %arg) { define void @log_f64(ptr %arg) {
; CHECK-LNX-LABEL: log_f64: ; CHECK-LNX-LABEL: log_f64:
; CHECK-LNX: # %bb.0: # %bb ; CHECK-LNX: # %bb.0: # %bb
; CHECK-LNX-NEXT: mflr 0 ; CHECK-LNX-NEXT: mflr 0
; CHECK-LNX-NEXT: std 0, 16(1)
; CHECK-LNX-NEXT: stdu 1, -32(1) ; CHECK-LNX-NEXT: stdu 1, -32(1)
; CHECK-LNX-NEXT: std 0, 48(1)
; CHECK-LNX-NEXT: .cfi_def_cfa_offset 32 ; CHECK-LNX-NEXT: .cfi_def_cfa_offset 32
; CHECK-LNX-NEXT: .cfi_offset lr, 16 ; CHECK-LNX-NEXT: .cfi_offset lr, 16
; CHECK-LNX-NEXT: addis 3, 2, .LCPI1_0@toc@ha ; CHECK-LNX-NEXT: addis 3, 2, .LCPI1_0@toc@ha
; CHECK-LNX-NEXT: lfs 1, .LCPI1_0@toc@l(3) ; CHECK-LNX-NEXT: lfs 1, .LCPI1_0@toc@l(3)
; CHECK-LNX-NEXT: bl __xl_log_finite ; CHECK-LNX-NEXT: bl __xl_log_finite
; CHECK-LNX-NEXT: nop ; CHECK-LNX-NEXT: nop
; CHECK-LNX-NEXT: xssqrtdp 0, 0 ; CHECK-LNX-NEXT: xssqrtdp 0, 0
; CHECK-LNX-NEXT: xsmuldp 0, 0, 1 ; CHECK-LNX-NEXT: xsmuldp 0, 0, 1
; CHECK-LNX-NEXT: .p2align 4 ; CHECK-LNX-NEXT: .p2align 4
; CHECK-LNX-NEXT: .LBB1_1: # %bb2 ; CHECK-LNX-NEXT: .LBB1_1: # %bb2
; CHECK-LNX-NEXT: # ; CHECK-LNX-NEXT: #
; CHECK-LNX-NEXT: stfd 0, 0(3) ; CHECK-LNX-NEXT: stfd 0, 0(3)
; CHECK-LNX-NEXT: b .LBB1_1 ; CHECK-LNX-NEXT: b .LBB1_1
; ;
; CHECK-AIX-LABEL: log_f64: ; CHECK-AIX-LABEL: log_f64:
; CHECK-AIX: # %bb.0: # %bb ; CHECK-AIX: # %bb.0: # %bb
; CHECK-AIX-NEXT: mflr 0 ; CHECK-AIX-NEXT: mflr 0
; CHECK-AIX-NEXT: stw 0, 8(1)
; CHECK-AIX-NEXT: stwu 1, -64(1) ; CHECK-AIX-NEXT: stwu 1, -64(1)
; CHECK-AIX-NEXT: stw 0, 72(1)
; CHECK-AIX-NEXT: stfd 31, 56(1) # 8-byte Folded Spill ; CHECK-AIX-NEXT: stfd 31, 56(1) # 8-byte Folded Spill
; CHECK-AIX-NEXT: bl .sqrt[PR] ; CHECK-AIX-NEXT: bl .sqrt[PR]
; CHECK-AIX-NEXT: nop ; CHECK-AIX-NEXT: nop
; CHECK-AIX-NEXT: lwz 3, L..C1(2) # %const.0 ; CHECK-AIX-NEXT: lwz 3, L..C1(2) # %const.0
; CHECK-AIX-NEXT: fmr 31, 1 ; CHECK-AIX-NEXT: fmr 31, 1
; CHECK-AIX-NEXT: lfs 0, 0(3) ; CHECK-AIX-NEXT: lfs 0, 0(3)
; CHECK-AIX-NEXT: fmr 1, 0 ; CHECK-AIX-NEXT: fmr 1, 0
; CHECK-AIX-NEXT: bl .__xl_log_finite[PR] ; CHECK-AIX-NEXT: bl .__xl_log_finite[PR]
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llvm/test/CodeGen/PowerPC/machine-pre.ll

Show First 20 Lines • Show All 56 Lines • ▼ Show 20 Lines
define dso_local signext i32 @foo(i32 signext %x, i32 signext %y) nounwind { define dso_local signext i32 @foo(i32 signext %x, i32 signext %y) nounwind {
; CHECK-P9-LABEL: foo: ; CHECK-P9-LABEL: foo:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mflr r0 ; CHECK-P9-NEXT: mflr r0
; CHECK-P9-NEXT: std r27, -40(r1) # 8-byte Folded Spill ; CHECK-P9-NEXT: std r27, -40(r1) # 8-byte Folded Spill
; CHECK-P9-NEXT: std r28, -32(r1) # 8-byte Folded Spill ; CHECK-P9-NEXT: std r28, -32(r1) # 8-byte Folded Spill
; CHECK-P9-NEXT: std r29, -24(r1) # 8-byte Folded Spill ; CHECK-P9-NEXT: std r29, -24(r1) # 8-byte Folded Spill
; CHECK-P9-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P9-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P9-NEXT: std r0, 16(r1)
; CHECK-P9-NEXT: stdu r1, -80(r1) ; CHECK-P9-NEXT: stdu r1, -80(r1)
; CHECK-P9-NEXT: mr r30, r4 ; CHECK-P9-NEXT: mr r30, r4
; CHECK-P9-NEXT: mr r29, r3 ; CHECK-P9-NEXT: mr r29, r3
; CHECK-P9-NEXT: lis r3, 21845 ; CHECK-P9-NEXT: lis r3, 21845
; CHECK-P9-NEXT: std r0, 96(r1)
; CHECK-P9-NEXT: add r28, r30, r29 ; CHECK-P9-NEXT: add r28, r30, r29
; CHECK-P9-NEXT: ori r27, r3, 21846 ; CHECK-P9-NEXT: ori r27, r3, 21846
; CHECK-P9-NEXT: b .LBB1_4 ; CHECK-P9-NEXT: b .LBB1_4
; CHECK-P9-NEXT: .p2align 4 ; CHECK-P9-NEXT: .p2align 4
; CHECK-P9-NEXT: .LBB1_1: # %sw.bb3 ; CHECK-P9-NEXT: .LBB1_1: # %sw.bb3
; CHECK-P9-NEXT: # ; CHECK-P9-NEXT: #
; CHECK-P9-NEXT: mulli r3, r30, 23 ; CHECK-P9-NEXT: mulli r3, r30, 23
; CHECK-P9-NEXT: .LBB1_2: # %sw.epilog ; CHECK-P9-NEXT: .LBB1_2: # %sw.epilog
▲ Show 20 Lines • Show All 113 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll

Show First 20 Lines • Show All 144 Lines • ▼ Show 20 Lines; CHECK-NEXT: blr
%cond = zext i1 %not.tobool to i32 %cond = zext i1 %not.tobool to i32
ret i32 %cond ret i32 %cond
} }
define i1 @length2_eq_nobuiltin_attr(ptr %X, ptr %Y) nounwind { define i1 @length2_eq_nobuiltin_attr(ptr %X, ptr %Y) nounwind {
; CHECK-LABEL: length2_eq_nobuiltin_attr: ; CHECK-LABEL: length2_eq_nobuiltin_attr:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; CHECK-NEXT: std 0, 16(1)
; CHECK-NEXT: stdu 1, -32(1) ; CHECK-NEXT: stdu 1, -32(1)
; CHECK-NEXT: li 5, 2 ; CHECK-NEXT: li 5, 2
; CHECK-NEXT: std 0, 48(1)
; CHECK-NEXT: bl memcmp ; CHECK-NEXT: bl memcmp
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: cntlzw 3, 3 ; CHECK-NEXT: cntlzw 3, 3
; CHECK-NEXT: rlwinm 3, 3, 27, 31, 31 ; CHECK-NEXT: rlwinm 3, 3, 27, 31, 31
; CHECK-NEXT: addi 1, 1, 32 ; CHECK-NEXT: addi 1, 1, 32
; CHECK-NEXT: ld 0, 16(1) ; CHECK-NEXT: ld 0, 16(1)
; CHECK-NEXT: mtlr 0 ; CHECK-NEXT: mtlr 0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%m = tail call signext i32 @memcmp(ptr %X, ptr %Y, i64 2) nobuiltin %m = tail call signext i32 @memcmp(ptr %X, ptr %Y, i64 2) nobuiltin
%c = icmp eq i32 %m, 0 %c = icmp eq i32 %m, 0
ret i1 %c ret i1 %c
} }

llvm/test/CodeGen/PowerPC/no-duplicate.ll

; RUN: llc -O2 < %s | FileCheck %s ; RUN: llc -O2 < %s | FileCheck %s
target triple = "powerpc64le-grtev4-linux-gnu" target triple = "powerpc64le-grtev4-linux-gnu"
; No duplication of loop header into entry block. ; No duplication of loop header into entry block.
define void @no_duplicate1(i64 %a) { define void @no_duplicate1(i64 %a) {
; CHECK-LABEL: no_duplicate1 ; CHECK-LABEL: no_duplicate1
; CHECK: mr 30, 3 ; CHECK: mr 30, 3
; CHECK-NEXT: std 0, 64(1)
; CHECK-NEXT: b .LBB0_2 ; CHECK-NEXT: b .LBB0_2
; CHECK: .LBB0_2: ; CHECK: .LBB0_2:
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: cmpldi 30, 100 ; CHECK-NEXT: cmpldi 30, 100
; CHECK-NEXT: bne 0, .LBB0_1 ; CHECK-NEXT: bne 0, .LBB0_1
entry: entry:
br label %header br label %header
Show All 17 Lines
end: end:
ret void ret void
} }
; No duplication of loop header into latches. ; No duplication of loop header into latches.
define void @no_duplicate2(i64 %a) { define void @no_duplicate2(i64 %a) {
; CHECK-LABEL: no_duplicate2 ; CHECK-LABEL: no_duplicate2
; CHECK: mr 30, 3 ; CHECK: mr 30, 3
; CHECK-NEXT: std 0, 64(1)
; CHECK-NEXT: b .LBB1_2 ; CHECK-NEXT: b .LBB1_2
; CHECK: .LBB1_2: ; CHECK: .LBB1_2:
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: cmpldi 30, 100 ; CHECK-NEXT: cmpldi 30, 100
; CHECK-NEXT: bne 0, .LBB1_1 ; CHECK-NEXT: bne 0, .LBB1_1
; CHECK: %latch2 ; CHECK: %latch2
▲ Show 20 Lines • Show All 42 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/not-fixed-frame-object.ll

Show All 38 Lines
; CHECK-NEXT: std r24, -64(r1) # 8-byte Folded Spill ; CHECK-NEXT: std r24, -64(r1) # 8-byte Folded Spill
; CHECK-NEXT: std r25, -56(r1) # 8-byte Folded Spill ; CHECK-NEXT: std r25, -56(r1) # 8-byte Folded Spill
; CHECK-NEXT: std r26, -48(r1) # 8-byte Folded Spill ; CHECK-NEXT: std r26, -48(r1) # 8-byte Folded Spill
; CHECK-NEXT: std r27, -40(r1) # 8-byte Folded Spill ; CHECK-NEXT: std r27, -40(r1) # 8-byte Folded Spill
; CHECK-NEXT: std r28, -32(r1) # 8-byte Folded Spill ; CHECK-NEXT: std r28, -32(r1) # 8-byte Folded Spill
; CHECK-NEXT: std r29, -24(r1) # 8-byte Folded Spill ; CHECK-NEXT: std r29, -24(r1) # 8-byte Folded Spill
; CHECK-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-NEXT: std r31, -8(r1) # 8-byte Folded Spill ; CHECK-NEXT: std r31, -8(r1) # 8-byte Folded Spill
; CHECK-NEXT: std r0, 16(r1)
; CHECK-NEXT: stdu r1, -192(r1) ; CHECK-NEXT: stdu r1, -192(r1)
; CHECK-NEXT: std r0, 208(r1)
; CHECK-NEXT: std r5, 32(r1) # 8-byte Folded Spill ; CHECK-NEXT: std r5, 32(r1) # 8-byte Folded Spill
; CHECK-NEXT: std r3, 40(r1) # 8-byte Folded Spill
; CHECK-NEXT: mr r0, r4 ; CHECK-NEXT: mr r0, r4
; CHECK-NEXT: std r3, 40(r1) # 8-byte Folded Spill
; CHECK-NEXT: ld r3, 40(r1) # 8-byte Folded Reload ; CHECK-NEXT: ld r3, 40(r1) # 8-byte Folded Reload
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: add r3, r3, r0 ; CHECK-NEXT: add r3, r3, r0
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: ld r4, 40(r1) # 8-byte Folded Reload ; CHECK-NEXT: ld r4, 40(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r6, 32(r1) # 8-byte Folded Reload ; CHECK-NEXT: ld r6, 32(r1) # 8-byte Folded Reload
; CHECK-NEXT: extsw r3, r3 ; CHECK-NEXT: extsw r3, r3
; CHECK-NEXT: mr r5, r0 ; CHECK-NEXT: mr r5, r0
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llvm/test/CodeGen/PowerPC/out-of-range-dform.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ ; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s \ ; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s \
; RUN: -check-prefix=CHECK-P9 ; RUN: -check-prefix=CHECK-P9
@_ZL3num = external dso_local unnamed_addr global float, align 4 @_ZL3num = external dso_local unnamed_addr global float, align 4
define dso_local void @main() local_unnamed_addr personality ptr @__gxx_personality_v0 { define dso_local void @main() local_unnamed_addr personality ptr @__gxx_personality_v0 {
; CHECK-P9-LABEL: main: ; CHECK-P9-LABEL: main:
; CHECK-P9: # %bb.0: # %bb ; CHECK-P9: # %bb.0: # %bb
; CHECK-P9-NEXT: mflr r0 ; CHECK-P9-NEXT: mflr r0
; CHECK-P9-NEXT: std r0, 16(r1)
; CHECK-P9-NEXT: stdu r1, -32(r1) ; CHECK-P9-NEXT: stdu r1, -32(r1)
; CHECK-P9-NEXT: std r0, 48(r1)
; CHECK-P9-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P9-NEXT: .cfi_def_cfa_offset 32
; CHECK-P9-NEXT: .cfi_offset lr, 16 ; CHECK-P9-NEXT: .cfi_offset lr, 16
; CHECK-P9-NEXT: bl malloc ; CHECK-P9-NEXT: bl malloc
; CHECK-P9-NEXT: nop ; CHECK-P9-NEXT: nop
; CHECK-P9-NEXT: addis r4, r2, _ZL3num@toc@ha ; CHECK-P9-NEXT: addis r4, r2, _ZL3num@toc@ha
; CHECK-P9-NEXT: addi r3, r3, -25400 ; CHECK-P9-NEXT: addi r3, r3, -25400
; CHECK-P9-NEXT: lfs f0, _ZL3num@toc@l(r4) ; CHECK-P9-NEXT: lfs f0, _ZL3num@toc@l(r4)
; CHECK-P9-NEXT: addis r4, r2, .LCPI0_0@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI0_0@toc@ha
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llvm/test/CodeGen/PowerPC/pcrel_ldst.ll

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; CHECK-P9-NEXT: addis r3, r2, GlobF128@toc@ha ; CHECK-P9-NEXT: addis r3, r2, GlobF128@toc@ha
; CHECK-P9-NEXT: addi r3, r3, GlobF128@toc@l ; CHECK-P9-NEXT: addi r3, r3, GlobF128@toc@l
; CHECK-P9-NEXT: stxsd v2, 0(r3) ; CHECK-P9-NEXT: stxsd v2, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: store_f128_to_uint: ; CHECK-P8-LE-LABEL: store_f128_to_uint:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: mflr r0 ; CHECK-P8-LE-NEXT: mflr r0
; CHECK-P8-LE-NEXT: std r0, 16(r1)
; CHECK-P8-LE-NEXT: stdu r1, -32(r1) ; CHECK-P8-LE-NEXT: stdu r1, -32(r1)
; CHECK-P8-LE-NEXT: std r0, 48(r1)
; CHECK-P8-LE-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-LE-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-LE-NEXT: .cfi_offset lr, 16 ; CHECK-P8-LE-NEXT: .cfi_offset lr, 16
; CHECK-P8-LE-NEXT: bl __fixunskfdi ; CHECK-P8-LE-NEXT: bl __fixunskfdi
; CHECK-P8-LE-NEXT: nop ; CHECK-P8-LE-NEXT: nop
; CHECK-P8-LE-NEXT: addis r4, r2, GlobF128@toc@ha ; CHECK-P8-LE-NEXT: addis r4, r2, GlobF128@toc@ha
; CHECK-P8-LE-NEXT: std r3, GlobF128@toc@l(r4) ; CHECK-P8-LE-NEXT: std r3, GlobF128@toc@l(r4)
; CHECK-P8-LE-NEXT: addi r1, r1, 32 ; CHECK-P8-LE-NEXT: addi r1, r1, 32
; CHECK-P8-LE-NEXT: ld r0, 16(r1) ; CHECK-P8-LE-NEXT: ld r0, 16(r1)
; CHECK-P8-LE-NEXT: mtlr r0 ; CHECK-P8-LE-NEXT: mtlr r0
; CHECK-P8-LE-NEXT: blr ; CHECK-P8-LE-NEXT: blr
; ;
; CHECK-P8-BE-LABEL: store_f128_to_uint: ; CHECK-P8-BE-LABEL: store_f128_to_uint:
; CHECK-P8-BE: # %bb.0: # %entry ; CHECK-P8-BE: # %bb.0: # %entry
; CHECK-P8-BE-NEXT: mflr r0 ; CHECK-P8-BE-NEXT: mflr r0
; CHECK-P8-BE-NEXT: std r0, 16(r1)
; CHECK-P8-BE-NEXT: stdu r1, -112(r1) ; CHECK-P8-BE-NEXT: stdu r1, -112(r1)
; CHECK-P8-BE-NEXT: std r0, 128(r1)
; CHECK-P8-BE-NEXT: .cfi_def_cfa_offset 112 ; CHECK-P8-BE-NEXT: .cfi_def_cfa_offset 112
; CHECK-P8-BE-NEXT: .cfi_offset lr, 16 ; CHECK-P8-BE-NEXT: .cfi_offset lr, 16
; CHECK-P8-BE-NEXT: bl __fixunskfdi ; CHECK-P8-BE-NEXT: bl __fixunskfdi
; CHECK-P8-BE-NEXT: nop ; CHECK-P8-BE-NEXT: nop
; CHECK-P8-BE-NEXT: addis r4, r2, GlobF128@toc@ha ; CHECK-P8-BE-NEXT: addis r4, r2, GlobF128@toc@ha
; CHECK-P8-BE-NEXT: std r3, GlobF128@toc@l(r4) ; CHECK-P8-BE-NEXT: std r3, GlobF128@toc@l(r4)
; CHECK-P8-BE-NEXT: addi r1, r1, 112 ; CHECK-P8-BE-NEXT: addi r1, r1, 112
; CHECK-P8-BE-NEXT: ld r0, 16(r1) ; CHECK-P8-BE-NEXT: ld r0, 16(r1)
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; CHECK-P9-NEXT: addis r3, r2, GlobF128@toc@ha ; CHECK-P9-NEXT: addis r3, r2, GlobF128@toc@ha
; CHECK-P9-NEXT: addi r3, r3, GlobF128@toc@l ; CHECK-P9-NEXT: addi r3, r3, GlobF128@toc@l
; CHECK-P9-NEXT: stxsd v2, 0(r3) ; CHECK-P9-NEXT: stxsd v2, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P8-LE-LABEL: store_f128_to_sint: ; CHECK-P8-LE-LABEL: store_f128_to_sint:
; CHECK-P8-LE: # %bb.0: # %entry ; CHECK-P8-LE: # %bb.0: # %entry
; CHECK-P8-LE-NEXT: mflr r0 ; CHECK-P8-LE-NEXT: mflr r0
; CHECK-P8-LE-NEXT: std r0, 16(r1)
; CHECK-P8-LE-NEXT: stdu r1, -32(r1) ; CHECK-P8-LE-NEXT: stdu r1, -32(r1)
; CHECK-P8-LE-NEXT: std r0, 48(r1)
; CHECK-P8-LE-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-LE-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-LE-NEXT: .cfi_offset lr, 16 ; CHECK-P8-LE-NEXT: .cfi_offset lr, 16
; CHECK-P8-LE-NEXT: bl __fixkfdi ; CHECK-P8-LE-NEXT: bl __fixkfdi
; CHECK-P8-LE-NEXT: nop ; CHECK-P8-LE-NEXT: nop
; CHECK-P8-LE-NEXT: addis r4, r2, GlobF128@toc@ha ; CHECK-P8-LE-NEXT: addis r4, r2, GlobF128@toc@ha
; CHECK-P8-LE-NEXT: std r3, GlobF128@toc@l(r4) ; CHECK-P8-LE-NEXT: std r3, GlobF128@toc@l(r4)
; CHECK-P8-LE-NEXT: addi r1, r1, 32 ; CHECK-P8-LE-NEXT: addi r1, r1, 32
; CHECK-P8-LE-NEXT: ld r0, 16(r1) ; CHECK-P8-LE-NEXT: ld r0, 16(r1)
; CHECK-P8-LE-NEXT: mtlr r0 ; CHECK-P8-LE-NEXT: mtlr r0
; CHECK-P8-LE-NEXT: blr ; CHECK-P8-LE-NEXT: blr
; ;
; CHECK-P8-BE-LABEL: store_f128_to_sint: ; CHECK-P8-BE-LABEL: store_f128_to_sint:
; CHECK-P8-BE: # %bb.0: # %entry ; CHECK-P8-BE: # %bb.0: # %entry
; CHECK-P8-BE-NEXT: mflr r0 ; CHECK-P8-BE-NEXT: mflr r0
; CHECK-P8-BE-NEXT: std r0, 16(r1)
; CHECK-P8-BE-NEXT: stdu r1, -112(r1) ; CHECK-P8-BE-NEXT: stdu r1, -112(r1)
; CHECK-P8-BE-NEXT: std r0, 128(r1)
; CHECK-P8-BE-NEXT: .cfi_def_cfa_offset 112 ; CHECK-P8-BE-NEXT: .cfi_def_cfa_offset 112
; CHECK-P8-BE-NEXT: .cfi_offset lr, 16 ; CHECK-P8-BE-NEXT: .cfi_offset lr, 16
; CHECK-P8-BE-NEXT: bl __fixkfdi ; CHECK-P8-BE-NEXT: bl __fixkfdi
; CHECK-P8-BE-NEXT: nop ; CHECK-P8-BE-NEXT: nop
; CHECK-P8-BE-NEXT: addis r4, r2, GlobF128@toc@ha ; CHECK-P8-BE-NEXT: addis r4, r2, GlobF128@toc@ha
; CHECK-P8-BE-NEXT: std r3, GlobF128@toc@l(r4) ; CHECK-P8-BE-NEXT: std r3, GlobF128@toc@l(r4)
; CHECK-P8-BE-NEXT: addi r1, r1, 112 ; CHECK-P8-BE-NEXT: addi r1, r1, 112
; CHECK-P8-BE-NEXT: ld r0, 16(r1) ; CHECK-P8-BE-NEXT: ld r0, 16(r1)
; CHECK-P8-BE-NEXT: mtlr r0 ; CHECK-P8-BE-NEXT: mtlr r0
; CHECK-P8-BE-NEXT: blr ; CHECK-P8-BE-NEXT: blr
entry: entry:
%conv = fptosi fp128 %str to i64 %conv = fptosi fp128 %str to i64
store i64 %conv, ptr @GlobF128, align 16 store i64 %conv, ptr @GlobF128, align 16
ret void ret void
} }

llvm/test/CodeGen/PowerPC/pow-025-075-intrinsic-scalar-mass-fast.ll

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; CHECK-LNX-NEXT: xsaddsp 1, 1, 4 ; CHECK-LNX-NEXT: xsaddsp 1, 1, 4
; CHECK-LNX-NEXT: xsmulsp 1, 3, 1 ; CHECK-LNX-NEXT: xsmulsp 1, 3, 1
; CHECK-LNX-NEXT: fsel 1, 0, 1, 2 ; CHECK-LNX-NEXT: fsel 1, 0, 1, 2
; CHECK-LNX-NEXT: blr ; CHECK-LNX-NEXT: blr
; ;
; CHECK-AIX-LABEL: llvmintr_powf_f32_fast025: ; CHECK-AIX-LABEL: llvmintr_powf_f32_fast025:
; CHECK-AIX: # %bb.0: # %entry ; CHECK-AIX: # %bb.0: # %entry
; CHECK-AIX-NEXT: mflr 0 ; CHECK-AIX-NEXT: mflr 0
; CHECK-AIX-NEXT: stw 0, 8(1)
; CHECK-AIX-NEXT: stwu 1, -64(1) ; CHECK-AIX-NEXT: stwu 1, -64(1)
; CHECK-AIX-NEXT: lwz 3, L..C0(2) # %const.0 ; CHECK-AIX-NEXT: lwz 3, L..C0(2) # %const.0
; CHECK-AIX-NEXT: stw 0, 72(1)
; CHECK-AIX-NEXT: lfs 2, 0(3) ; CHECK-AIX-NEXT: lfs 2, 0(3)
; CHECK-AIX-NEXT: bl .__xl_powf_finite[PR] ; CHECK-AIX-NEXT: bl .__xl_powf_finite[PR]
; CHECK-AIX-NEXT: nop ; CHECK-AIX-NEXT: nop
; CHECK-AIX-NEXT: addi 1, 1, 64 ; CHECK-AIX-NEXT: addi 1, 1, 64
; CHECK-AIX-NEXT: lwz 0, 8(1) ; CHECK-AIX-NEXT: lwz 0, 8(1)
; CHECK-AIX-NEXT: mtlr 0 ; CHECK-AIX-NEXT: mtlr 0
; CHECK-AIX-NEXT: blr ; CHECK-AIX-NEXT: blr
entry: entry:
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; CHECK-LNX-NEXT: xsmuldp 0, 1, 0 ; CHECK-LNX-NEXT: xsmuldp 0, 1, 0
; CHECK-LNX-NEXT: xsadddp 2, 3, 2 ; CHECK-LNX-NEXT: xsadddp 2, 3, 2
; CHECK-LNX-NEXT: xsmuldp 1, 0, 2 ; CHECK-LNX-NEXT: xsmuldp 1, 0, 2
; CHECK-LNX-NEXT: blr ; CHECK-LNX-NEXT: blr
; ;
; CHECK-AIX-LABEL: llvmintr_pow_f64_fast025: ; CHECK-AIX-LABEL: llvmintr_pow_f64_fast025:
; CHECK-AIX: # %bb.0: # %entry ; CHECK-AIX: # %bb.0: # %entry
; CHECK-AIX-NEXT: mflr 0 ; CHECK-AIX-NEXT: mflr 0
; CHECK-AIX-NEXT: stw 0, 8(1)
; CHECK-AIX-NEXT: stwu 1, -64(1) ; CHECK-AIX-NEXT: stwu 1, -64(1)
; CHECK-AIX-NEXT: lwz 3, L..C1(2) # %const.0 ; CHECK-AIX-NEXT: lwz 3, L..C1(2) # %const.0
; CHECK-AIX-NEXT: stw 0, 72(1)
; CHECK-AIX-NEXT: lfs 2, 0(3) ; CHECK-AIX-NEXT: lfs 2, 0(3)
; CHECK-AIX-NEXT: bl .__xl_pow_finite[PR] ; CHECK-AIX-NEXT: bl .__xl_pow_finite[PR]
; CHECK-AIX-NEXT: nop ; CHECK-AIX-NEXT: nop
; CHECK-AIX-NEXT: addi 1, 1, 64 ; CHECK-AIX-NEXT: addi 1, 1, 64
; CHECK-AIX-NEXT: lwz 0, 8(1) ; CHECK-AIX-NEXT: lwz 0, 8(1)
; CHECK-AIX-NEXT: mtlr 0 ; CHECK-AIX-NEXT: mtlr 0
; CHECK-AIX-NEXT: blr ; CHECK-AIX-NEXT: blr
entry: entry:
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; CHECK-LNX-NEXT: xssubsp 3, 4, 5 ; CHECK-LNX-NEXT: xssubsp 3, 4, 5
; CHECK-LNX-NEXT: fsel 1, 3, 1, 2 ; CHECK-LNX-NEXT: fsel 1, 3, 1, 2
; CHECK-LNX-NEXT: xsmulsp 1, 0, 1 ; CHECK-LNX-NEXT: xsmulsp 1, 0, 1
; CHECK-LNX-NEXT: blr ; CHECK-LNX-NEXT: blr
; ;
; CHECK-AIX-LABEL: llvmintr_powf_f32_fast075: ; CHECK-AIX-LABEL: llvmintr_powf_f32_fast075:
; CHECK-AIX: # %bb.0: # %entry ; CHECK-AIX: # %bb.0: # %entry
; CHECK-AIX-NEXT: mflr 0 ; CHECK-AIX-NEXT: mflr 0
; CHECK-AIX-NEXT: stw 0, 8(1)
; CHECK-AIX-NEXT: stwu 1, -64(1) ; CHECK-AIX-NEXT: stwu 1, -64(1)
; CHECK-AIX-NEXT: lwz 3, L..C2(2) # %const.0 ; CHECK-AIX-NEXT: lwz 3, L..C2(2) # %const.0
; CHECK-AIX-NEXT: stw 0, 72(1)
; CHECK-AIX-NEXT: lfs 2, 0(3) ; CHECK-AIX-NEXT: lfs 2, 0(3)
; CHECK-AIX-NEXT: bl .__xl_powf_finite[PR] ; CHECK-AIX-NEXT: bl .__xl_powf_finite[PR]
; CHECK-AIX-NEXT: nop ; CHECK-AIX-NEXT: nop
; CHECK-AIX-NEXT: addi 1, 1, 64 ; CHECK-AIX-NEXT: addi 1, 1, 64
; CHECK-AIX-NEXT: lwz 0, 8(1) ; CHECK-AIX-NEXT: lwz 0, 8(1)
; CHECK-AIX-NEXT: mtlr 0 ; CHECK-AIX-NEXT: mtlr 0
; CHECK-AIX-NEXT: blr ; CHECK-AIX-NEXT: blr
entry: entry:
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; CHECK-LNX-NEXT: xsadddp 2, 3, 2 ; CHECK-LNX-NEXT: xsadddp 2, 3, 2
; CHECK-LNX-NEXT: xsmuldp 0, 0, 2 ; CHECK-LNX-NEXT: xsmuldp 0, 0, 2
; CHECK-LNX-NEXT: xsmuldp 1, 1, 0 ; CHECK-LNX-NEXT: xsmuldp 1, 1, 0
; CHECK-LNX-NEXT: blr ; CHECK-LNX-NEXT: blr
; ;
; CHECK-AIX-LABEL: llvmintr_pow_f64_fast075: ; CHECK-AIX-LABEL: llvmintr_pow_f64_fast075:
; CHECK-AIX: # %bb.0: # %entry ; CHECK-AIX: # %bb.0: # %entry
; CHECK-AIX-NEXT: mflr 0 ; CHECK-AIX-NEXT: mflr 0
; CHECK-AIX-NEXT: stw 0, 8(1)
; CHECK-AIX-NEXT: stwu 1, -64(1) ; CHECK-AIX-NEXT: stwu 1, -64(1)
; CHECK-AIX-NEXT: lwz 3, L..C3(2) # %const.0 ; CHECK-AIX-NEXT: lwz 3, L..C3(2) # %const.0
; CHECK-AIX-NEXT: stw 0, 72(1)
; CHECK-AIX-NEXT: lfs 2, 0(3) ; CHECK-AIX-NEXT: lfs 2, 0(3)
; CHECK-AIX-NEXT: bl .__xl_pow_finite[PR] ; CHECK-AIX-NEXT: bl .__xl_pow_finite[PR]
; CHECK-AIX-NEXT: nop ; CHECK-AIX-NEXT: nop
; CHECK-AIX-NEXT: addi 1, 1, 64 ; CHECK-AIX-NEXT: addi 1, 1, 64
; CHECK-AIX-NEXT: lwz 0, 8(1) ; CHECK-AIX-NEXT: lwz 0, 8(1)
; CHECK-AIX-NEXT: mtlr 0 ; CHECK-AIX-NEXT: mtlr 0
; CHECK-AIX-NEXT: blr ; CHECK-AIX-NEXT: blr
entry: entry:
%call = tail call nnan ninf afn nsz double @llvm.pow.f64(double %a, double 7.500000e-01) %call = tail call nnan ninf afn nsz double @llvm.pow.f64(double %a, double 7.500000e-01)
ret double %call ret double %call
} }
; fast-math powf with 0.50 ; fast-math powf with 0.50
; TODO: pow->sqrt conversion for LinuxLE and AIX ; TODO: pow->sqrt conversion for LinuxLE and AIX
define float @llvmintr_powf_f32_fast050(float %a) #1 { define float @llvmintr_powf_f32_fast050(float %a) #1 {
; CHECK-LNX-LABEL: llvmintr_powf_f32_fast050: ; CHECK-LNX-LABEL: llvmintr_powf_f32_fast050:
; CHECK-LNX: # %bb.0: # %entry ; CHECK-LNX: # %bb.0: # %entry
; CHECK-LNX-NEXT: mflr 0 ; CHECK-LNX-NEXT: mflr 0
; CHECK-LNX-NEXT: std 0, 16(1)
; CHECK-LNX-NEXT: stdu 1, -32(1) ; CHECK-LNX-NEXT: stdu 1, -32(1)
; CHECK-LNX-NEXT: std 0, 48(1)
; CHECK-LNX-NEXT: .cfi_def_cfa_offset 32 ; CHECK-LNX-NEXT: .cfi_def_cfa_offset 32
; CHECK-LNX-NEXT: .cfi_offset lr, 16 ; CHECK-LNX-NEXT: .cfi_offset lr, 16
; CHECK-LNX-NEXT: addis 3, 2, .LCPI4_0@toc@ha ; CHECK-LNX-NEXT: addis 3, 2, .LCPI4_0@toc@ha
; CHECK-LNX-NEXT: lfs 2, .LCPI4_0@toc@l(3) ; CHECK-LNX-NEXT: lfs 2, .LCPI4_0@toc@l(3)
; CHECK-LNX-NEXT: bl __xl_powf_finite ; CHECK-LNX-NEXT: bl __xl_powf_finite
; CHECK-LNX-NEXT: nop ; CHECK-LNX-NEXT: nop
; CHECK-LNX-NEXT: addi 1, 1, 32 ; CHECK-LNX-NEXT: addi 1, 1, 32
; CHECK-LNX-NEXT: ld 0, 16(1) ; CHECK-LNX-NEXT: ld 0, 16(1)
; CHECK-LNX-NEXT: mtlr 0 ; CHECK-LNX-NEXT: mtlr 0
; CHECK-LNX-NEXT: blr ; CHECK-LNX-NEXT: blr
; ;
; CHECK-AIX-LABEL: llvmintr_powf_f32_fast050: ; CHECK-AIX-LABEL: llvmintr_powf_f32_fast050:
; CHECK-AIX: # %bb.0: # %entry ; CHECK-AIX: # %bb.0: # %entry
; CHECK-AIX-NEXT: mflr 0 ; CHECK-AIX-NEXT: mflr 0
; CHECK-AIX-NEXT: stw 0, 8(1)
; CHECK-AIX-NEXT: stwu 1, -64(1) ; CHECK-AIX-NEXT: stwu 1, -64(1)
; CHECK-AIX-NEXT: lwz 3, L..C4(2) # %const.0 ; CHECK-AIX-NEXT: lwz 3, L..C4(2) # %const.0
; CHECK-AIX-NEXT: stw 0, 72(1)
; CHECK-AIX-NEXT: lfs 2, 0(3) ; CHECK-AIX-NEXT: lfs 2, 0(3)
; CHECK-AIX-NEXT: bl .__xl_powf_finite[PR] ; CHECK-AIX-NEXT: bl .__xl_powf_finite[PR]
; CHECK-AIX-NEXT: nop ; CHECK-AIX-NEXT: nop
; CHECK-AIX-NEXT: addi 1, 1, 64 ; CHECK-AIX-NEXT: addi 1, 1, 64
; CHECK-AIX-NEXT: lwz 0, 8(1) ; CHECK-AIX-NEXT: lwz 0, 8(1)
; CHECK-AIX-NEXT: mtlr 0 ; CHECK-AIX-NEXT: mtlr 0
; CHECK-AIX-NEXT: blr ; CHECK-AIX-NEXT: blr
entry: entry:
%call = tail call nnan ninf afn nsz float @llvm.pow.f32(float %a, float 5.000000e-01) %call = tail call nnan ninf afn nsz float @llvm.pow.f32(float %a, float 5.000000e-01)
ret float %call ret float %call
} }
; fast-math pow with 0.50 ; fast-math pow with 0.50
; TODO: pow->sqrt conversion for LinuxLE and AIX ; TODO: pow->sqrt conversion for LinuxLE and AIX
define double @llvmintr_pow_f64_fast050(double %a) #1 { define double @llvmintr_pow_f64_fast050(double %a) #1 {
; CHECK-LNX-LABEL: llvmintr_pow_f64_fast050: ; CHECK-LNX-LABEL: llvmintr_pow_f64_fast050:
; CHECK-LNX: # %bb.0: # %entry ; CHECK-LNX: # %bb.0: # %entry
; CHECK-LNX-NEXT: mflr 0 ; CHECK-LNX-NEXT: mflr 0
; CHECK-LNX-NEXT: std 0, 16(1)
; CHECK-LNX-NEXT: stdu 1, -32(1) ; CHECK-LNX-NEXT: stdu 1, -32(1)
; CHECK-LNX-NEXT: std 0, 48(1)
; CHECK-LNX-NEXT: .cfi_def_cfa_offset 32 ; CHECK-LNX-NEXT: .cfi_def_cfa_offset 32
; CHECK-LNX-NEXT: .cfi_offset lr, 16 ; CHECK-LNX-NEXT: .cfi_offset lr, 16
; CHECK-LNX-NEXT: addis 3, 2, .LCPI5_0@toc@ha ; CHECK-LNX-NEXT: addis 3, 2, .LCPI5_0@toc@ha
; CHECK-LNX-NEXT: lfs 2, .LCPI5_0@toc@l(3) ; CHECK-LNX-NEXT: lfs 2, .LCPI5_0@toc@l(3)
; CHECK-LNX-NEXT: bl __xl_pow_finite ; CHECK-LNX-NEXT: bl __xl_pow_finite
; CHECK-LNX-NEXT: nop ; CHECK-LNX-NEXT: nop
; CHECK-LNX-NEXT: addi 1, 1, 32 ; CHECK-LNX-NEXT: addi 1, 1, 32
; CHECK-LNX-NEXT: ld 0, 16(1) ; CHECK-LNX-NEXT: ld 0, 16(1)
; CHECK-LNX-NEXT: mtlr 0 ; CHECK-LNX-NEXT: mtlr 0
; CHECK-LNX-NEXT: blr ; CHECK-LNX-NEXT: blr
; ;
; CHECK-AIX-LABEL: llvmintr_pow_f64_fast050: ; CHECK-AIX-LABEL: llvmintr_pow_f64_fast050:
; CHECK-AIX: # %bb.0: # %entry ; CHECK-AIX: # %bb.0: # %entry
; CHECK-AIX-NEXT: mflr 0 ; CHECK-AIX-NEXT: mflr 0
; CHECK-AIX-NEXT: stw 0, 8(1)
; CHECK-AIX-NEXT: stwu 1, -64(1) ; CHECK-AIX-NEXT: stwu 1, -64(1)
; CHECK-AIX-NEXT: lwz 3, L..C5(2) # %const.0 ; CHECK-AIX-NEXT: lwz 3, L..C5(2) # %const.0
; CHECK-AIX-NEXT: stw 0, 72(1)
; CHECK-AIX-NEXT: lfs 2, 0(3) ; CHECK-AIX-NEXT: lfs 2, 0(3)
; CHECK-AIX-NEXT: bl .__xl_pow_finite[PR] ; CHECK-AIX-NEXT: bl .__xl_pow_finite[PR]
; CHECK-AIX-NEXT: nop ; CHECK-AIX-NEXT: nop
; CHECK-AIX-NEXT: addi 1, 1, 64 ; CHECK-AIX-NEXT: addi 1, 1, 64
; CHECK-AIX-NEXT: lwz 0, 8(1) ; CHECK-AIX-NEXT: lwz 0, 8(1)
; CHECK-AIX-NEXT: mtlr 0 ; CHECK-AIX-NEXT: mtlr 0
; CHECK-AIX-NEXT: blr ; CHECK-AIX-NEXT: blr
entry: entry:
%call = tail call nnan ninf afn nsz double @llvm.pow.f64(double %a, double 5.000000e-01) %call = tail call nnan ninf afn nsz double @llvm.pow.f64(double %a, double 5.000000e-01)
ret double %call ret double %call
} }
attributes #1 = { "no-infs-fp-math"="true" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "approx-func-fp-math"="true" } attributes #1 = { "no-infs-fp-math"="true" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "approx-func-fp-math"="true" }

llvm/test/CodeGen/PowerPC/pow-025-075-nointrinsic-scalar-mass-fast.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -enable-ppc-gen-scalar-mass -verify-machineinstrs -O3 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck --check-prefix=CHECK-LNX %s ; RUN: llc -enable-ppc-gen-scalar-mass -verify-machineinstrs -O3 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck --check-prefix=CHECK-LNX %s
; RUN: llc -enable-ppc-gen-scalar-mass -verify-machineinstrs -O3 -mtriple=powerpc-ibm-aix-xcoff < %s | FileCheck --check-prefix=CHECK-AIX %s ; RUN: llc -enable-ppc-gen-scalar-mass -verify-machineinstrs -O3 -mtriple=powerpc-ibm-aix-xcoff < %s | FileCheck --check-prefix=CHECK-AIX %s
declare float @powf (float, float); declare float @powf (float, float);
declare double @pow (double, double); declare double @pow (double, double);
declare float @__powf_finite (float, float); declare float @__powf_finite (float, float);
declare double @__pow_finite (double, double); declare double @__pow_finite (double, double);
; fast-math powf with 0.25 ; fast-math powf with 0.25
define float @powf_f32_fast025(float %a) #1 { define float @powf_f32_fast025(float %a) #1 {
; ;
; CHECK-LNX-LABEL: powf_f32_fast025: ; CHECK-LNX-LABEL: powf_f32_fast025:
; CHECK-LNX: # %bb.0: # %entry ; CHECK-LNX: # %bb.0: # %entry
; CHECK-LNX-NEXT: mflr 0 ; CHECK-LNX-NEXT: mflr 0
; CHECK-LNX-NEXT: std 0, 16(1)
; CHECK-LNX-NEXT: stdu 1, -32(1) ; CHECK-LNX-NEXT: stdu 1, -32(1)
; CHECK-LNX-NEXT: std 0, 48(1)
; CHECK-LNX-NEXT: .cfi_def_cfa_offset 32 ; CHECK-LNX-NEXT: .cfi_def_cfa_offset 32
; CHECK-LNX-NEXT: .cfi_offset lr, 16 ; CHECK-LNX-NEXT: .cfi_offset lr, 16
; CHECK-LNX-NEXT: addis 3, 2, .LCPI0_0@toc@ha ; CHECK-LNX-NEXT: addis 3, 2, .LCPI0_0@toc@ha
; CHECK-LNX-NEXT: lfs 2, .LCPI0_0@toc@l(3) ; CHECK-LNX-NEXT: lfs 2, .LCPI0_0@toc@l(3)
; CHECK-LNX-NEXT: bl __xl_powf_finite ; CHECK-LNX-NEXT: bl __xl_powf_finite
; CHECK-LNX-NEXT: nop ; CHECK-LNX-NEXT: nop
; CHECK-LNX-NEXT: addi 1, 1, 32 ; CHECK-LNX-NEXT: addi 1, 1, 32
; CHECK-LNX-NEXT: ld 0, 16(1) ; CHECK-LNX-NEXT: ld 0, 16(1)
; CHECK-LNX-NEXT: mtlr 0 ; CHECK-LNX-NEXT: mtlr 0
; CHECK-LNX-NEXT: blr ; CHECK-LNX-NEXT: blr
; ;
; CHECK-AIX-LABEL: powf_f32_fast025: ; CHECK-AIX-LABEL: powf_f32_fast025:
; CHECK-AIX: # %bb.0: # %entry ; CHECK-AIX: # %bb.0: # %entry
; CHECK-AIX-NEXT: mflr 0 ; CHECK-AIX-NEXT: mflr 0
; CHECK-AIX-NEXT: stw 0, 8(1)
; CHECK-AIX-NEXT: stwu 1, -64(1) ; CHECK-AIX-NEXT: stwu 1, -64(1)
; CHECK-AIX-NEXT: lwz 3, L..C0(2) # %const.0 ; CHECK-AIX-NEXT: lwz 3, L..C0(2) # %const.0
; CHECK-AIX-NEXT: stw 0, 72(1)
; CHECK-AIX-NEXT: lfs 2, 0(3) ; CHECK-AIX-NEXT: lfs 2, 0(3)
; CHECK-AIX-NEXT: bl .__xl_powf_finite[PR] ; CHECK-AIX-NEXT: bl .__xl_powf_finite[PR]
; CHECK-AIX-NEXT: nop ; CHECK-AIX-NEXT: nop
; CHECK-AIX-NEXT: addi 1, 1, 64 ; CHECK-AIX-NEXT: addi 1, 1, 64
; CHECK-AIX-NEXT: lwz 0, 8(1) ; CHECK-AIX-NEXT: lwz 0, 8(1)
; CHECK-AIX-NEXT: mtlr 0 ; CHECK-AIX-NEXT: mtlr 0
; CHECK-AIX-NEXT: blr ; CHECK-AIX-NEXT: blr
entry: entry:
%call = tail call nnan ninf afn nsz float @powf(float %a, float 2.500000e-01) %call = tail call nnan ninf afn nsz float @powf(float %a, float 2.500000e-01)
ret float %call ret float %call
} }
; fast-math pow with 0.25 ; fast-math pow with 0.25
define double @pow_f64_fast025(double %a) #1 { define double @pow_f64_fast025(double %a) #1 {
; ;
; CHECK-LNX-LABEL: pow_f64_fast025: ; CHECK-LNX-LABEL: pow_f64_fast025:
; CHECK-LNX: # %bb.0: # %entry ; CHECK-LNX: # %bb.0: # %entry
; CHECK-LNX-NEXT: mflr 0 ; CHECK-LNX-NEXT: mflr 0
; CHECK-LNX-NEXT: std 0, 16(1)
; CHECK-LNX-NEXT: stdu 1, -32(1) ; CHECK-LNX-NEXT: stdu 1, -32(1)
; CHECK-LNX-NEXT: std 0, 48(1)
; CHECK-LNX-NEXT: .cfi_def_cfa_offset 32 ; CHECK-LNX-NEXT: .cfi_def_cfa_offset 32
; CHECK-LNX-NEXT: .cfi_offset lr, 16 ; CHECK-LNX-NEXT: .cfi_offset lr, 16
; CHECK-LNX-NEXT: addis 3, 2, .LCPI1_0@toc@ha ; CHECK-LNX-NEXT: addis 3, 2, .LCPI1_0@toc@ha
; CHECK-LNX-NEXT: lfs 2, .LCPI1_0@toc@l(3) ; CHECK-LNX-NEXT: lfs 2, .LCPI1_0@toc@l(3)
; CHECK-LNX-NEXT: bl __xl_pow_finite ; CHECK-LNX-NEXT: bl __xl_pow_finite
; CHECK-LNX-NEXT: nop ; CHECK-LNX-NEXT: nop
; CHECK-LNX-NEXT: addi 1, 1, 32 ; CHECK-LNX-NEXT: addi 1, 1, 32
; CHECK-LNX-NEXT: ld 0, 16(1) ; CHECK-LNX-NEXT: ld 0, 16(1)
; CHECK-LNX-NEXT: mtlr 0 ; CHECK-LNX-NEXT: mtlr 0
; CHECK-LNX-NEXT: blr ; CHECK-LNX-NEXT: blr
; ;
; CHECK-AIX-LABEL: pow_f64_fast025: ; CHECK-AIX-LABEL: pow_f64_fast025:
; CHECK-AIX: # %bb.0: # %entry ; CHECK-AIX: # %bb.0: # %entry
; CHECK-AIX-NEXT: mflr 0 ; CHECK-AIX-NEXT: mflr 0
; CHECK-AIX-NEXT: stw 0, 8(1)
; CHECK-AIX-NEXT: stwu 1, -64(1) ; CHECK-AIX-NEXT: stwu 1, -64(1)
; CHECK-AIX-NEXT: lwz 3, L..C1(2) # %const.0 ; CHECK-AIX-NEXT: lwz 3, L..C1(2) # %const.0
; CHECK-AIX-NEXT: stw 0, 72(1)
; CHECK-AIX-NEXT: lfs 2, 0(3) ; CHECK-AIX-NEXT: lfs 2, 0(3)
; CHECK-AIX-NEXT: bl .__xl_pow_finite[PR] ; CHECK-AIX-NEXT: bl .__xl_pow_finite[PR]
; CHECK-AIX-NEXT: nop ; CHECK-AIX-NEXT: nop
; CHECK-AIX-NEXT: addi 1, 1, 64 ; CHECK-AIX-NEXT: addi 1, 1, 64
; CHECK-AIX-NEXT: lwz 0, 8(1) ; CHECK-AIX-NEXT: lwz 0, 8(1)
; CHECK-AIX-NEXT: mtlr 0 ; CHECK-AIX-NEXT: mtlr 0
; CHECK-AIX-NEXT: blr ; CHECK-AIX-NEXT: blr
entry: entry:
%call = tail call nnan ninf afn nsz double @pow(double %a, double 2.500000e-01) %call = tail call nnan ninf afn nsz double @pow(double %a, double 2.500000e-01)
ret double %call ret double %call
} }
; fast-math powf with 0.75 ; fast-math powf with 0.75
define float @powf_f32_fast075(float %a) #1 { define float @powf_f32_fast075(float %a) #1 {
; ;
; CHECK-LNX-LABEL: powf_f32_fast075: ; CHECK-LNX-LABEL: powf_f32_fast075:
; CHECK-LNX: # %bb.0: # %entry ; CHECK-LNX: # %bb.0: # %entry
; CHECK-LNX-NEXT: mflr 0 ; CHECK-LNX-NEXT: mflr 0
; CHECK-LNX-NEXT: std 0, 16(1)
; CHECK-LNX-NEXT: stdu 1, -32(1) ; CHECK-LNX-NEXT: stdu 1, -32(1)
; CHECK-LNX-NEXT: std 0, 48(1)
; CHECK-LNX-NEXT: .cfi_def_cfa_offset 32 ; CHECK-LNX-NEXT: .cfi_def_cfa_offset 32
; CHECK-LNX-NEXT: .cfi_offset lr, 16 ; CHECK-LNX-NEXT: .cfi_offset lr, 16
; CHECK-LNX-NEXT: addis 3, 2, .LCPI2_0@toc@ha ; CHECK-LNX-NEXT: addis 3, 2, .LCPI2_0@toc@ha
; CHECK-LNX-NEXT: lfs 2, .LCPI2_0@toc@l(3) ; CHECK-LNX-NEXT: lfs 2, .LCPI2_0@toc@l(3)
; CHECK-LNX-NEXT: bl __xl_powf_finite ; CHECK-LNX-NEXT: bl __xl_powf_finite
; CHECK-LNX-NEXT: nop ; CHECK-LNX-NEXT: nop
; CHECK-LNX-NEXT: addi 1, 1, 32 ; CHECK-LNX-NEXT: addi 1, 1, 32
; CHECK-LNX-NEXT: ld 0, 16(1) ; CHECK-LNX-NEXT: ld 0, 16(1)
; CHECK-LNX-NEXT: mtlr 0 ; CHECK-LNX-NEXT: mtlr 0
; CHECK-LNX-NEXT: blr ; CHECK-LNX-NEXT: blr
; ;
; CHECK-AIX-LABEL: powf_f32_fast075: ; CHECK-AIX-LABEL: powf_f32_fast075:
; CHECK-AIX: # %bb.0: # %entry ; CHECK-AIX: # %bb.0: # %entry
; CHECK-AIX-NEXT: mflr 0 ; CHECK-AIX-NEXT: mflr 0
; CHECK-AIX-NEXT: stw 0, 8(1)
; CHECK-AIX-NEXT: stwu 1, -64(1) ; CHECK-AIX-NEXT: stwu 1, -64(1)
; CHECK-AIX-NEXT: lwz 3, L..C2(2) # %const.0 ; CHECK-AIX-NEXT: lwz 3, L..C2(2) # %const.0
; CHECK-AIX-NEXT: stw 0, 72(1)
; CHECK-AIX-NEXT: lfs 2, 0(3) ; CHECK-AIX-NEXT: lfs 2, 0(3)
; CHECK-AIX-NEXT: bl .__xl_powf_finite[PR] ; CHECK-AIX-NEXT: bl .__xl_powf_finite[PR]
; CHECK-AIX-NEXT: nop ; CHECK-AIX-NEXT: nop
; CHECK-AIX-NEXT: addi 1, 1, 64 ; CHECK-AIX-NEXT: addi 1, 1, 64
; CHECK-AIX-NEXT: lwz 0, 8(1) ; CHECK-AIX-NEXT: lwz 0, 8(1)
; CHECK-AIX-NEXT: mtlr 0 ; CHECK-AIX-NEXT: mtlr 0
; CHECK-AIX-NEXT: blr ; CHECK-AIX-NEXT: blr
entry: entry:
%call = tail call nnan ninf afn nsz float @powf(float %a, float 7.500000e-01) %call = tail call nnan ninf afn nsz float @powf(float %a, float 7.500000e-01)
ret float %call ret float %call
} }
; fast-math pow with 0.75 ; fast-math pow with 0.75
define double @pow_f64_fast075(double %a) #1 { define double @pow_f64_fast075(double %a) #1 {
; ;
; CHECK-LNX-LABEL: pow_f64_fast075: ; CHECK-LNX-LABEL: pow_f64_fast075:
; CHECK-LNX: # %bb.0: # %entry ; CHECK-LNX: # %bb.0: # %entry
; CHECK-LNX-NEXT: mflr 0 ; CHECK-LNX-NEXT: mflr 0
; CHECK-LNX-NEXT: std 0, 16(1)
; CHECK-LNX-NEXT: stdu 1, -32(1) ; CHECK-LNX-NEXT: stdu 1, -32(1)
; CHECK-LNX-NEXT: std 0, 48(1)
; CHECK-LNX-NEXT: .cfi_def_cfa_offset 32 ; CHECK-LNX-NEXT: .cfi_def_cfa_offset 32
; CHECK-LNX-NEXT: .cfi_offset lr, 16 ; CHECK-LNX-NEXT: .cfi_offset lr, 16
; CHECK-LNX-NEXT: addis 3, 2, .LCPI3_0@toc@ha ; CHECK-LNX-NEXT: addis 3, 2, .LCPI3_0@toc@ha
; CHECK-LNX-NEXT: lfs 2, .LCPI3_0@toc@l(3) ; CHECK-LNX-NEXT: lfs 2, .LCPI3_0@toc@l(3)
; CHECK-LNX-NEXT: bl __xl_pow_finite ; CHECK-LNX-NEXT: bl __xl_pow_finite
; CHECK-LNX-NEXT: nop ; CHECK-LNX-NEXT: nop
; CHECK-LNX-NEXT: addi 1, 1, 32 ; CHECK-LNX-NEXT: addi 1, 1, 32
; CHECK-LNX-NEXT: ld 0, 16(1) ; CHECK-LNX-NEXT: ld 0, 16(1)
; CHECK-LNX-NEXT: mtlr 0 ; CHECK-LNX-NEXT: mtlr 0
; CHECK-LNX-NEXT: blr ; CHECK-LNX-NEXT: blr
; ;
; CHECK-AIX-LABEL: pow_f64_fast075: ; CHECK-AIX-LABEL: pow_f64_fast075:
; CHECK-AIX: # %bb.0: # %entry ; CHECK-AIX: # %bb.0: # %entry
; CHECK-AIX-NEXT: mflr 0 ; CHECK-AIX-NEXT: mflr 0
; CHECK-AIX-NEXT: stw 0, 8(1)
; CHECK-AIX-NEXT: stwu 1, -64(1) ; CHECK-AIX-NEXT: stwu 1, -64(1)
; CHECK-AIX-NEXT: lwz 3, L..C3(2) # %const.0 ; CHECK-AIX-NEXT: lwz 3, L..C3(2) # %const.0
; CHECK-AIX-NEXT: stw 0, 72(1)
; CHECK-AIX-NEXT: lfs 2, 0(3) ; CHECK-AIX-NEXT: lfs 2, 0(3)
; CHECK-AIX-NEXT: bl .__xl_pow_finite[PR] ; CHECK-AIX-NEXT: bl .__xl_pow_finite[PR]
; CHECK-AIX-NEXT: nop ; CHECK-AIX-NEXT: nop
; CHECK-AIX-NEXT: addi 1, 1, 64 ; CHECK-AIX-NEXT: addi 1, 1, 64
; CHECK-AIX-NEXT: lwz 0, 8(1) ; CHECK-AIX-NEXT: lwz 0, 8(1)
; CHECK-AIX-NEXT: mtlr 0 ; CHECK-AIX-NEXT: mtlr 0
; CHECK-AIX-NEXT: blr ; CHECK-AIX-NEXT: blr
entry: entry:
%call = tail call nnan ninf afn nsz double @pow(double %a, double 7.500000e-01) %call = tail call nnan ninf afn nsz double @pow(double %a, double 7.500000e-01)
ret double %call ret double %call
} }
; fast-math powf with 0.50 ; fast-math powf with 0.50
define float @powf_f32_fast050(float %a) #1 { define float @powf_f32_fast050(float %a) #1 {
; ;
; CHECK-LNX-LABEL: powf_f32_fast050: ; CHECK-LNX-LABEL: powf_f32_fast050:
; CHECK-LNX: # %bb.0: # %entry ; CHECK-LNX: # %bb.0: # %entry
; CHECK-LNX-NEXT: mflr 0 ; CHECK-LNX-NEXT: mflr 0
; CHECK-LNX-NEXT: std 0, 16(1)
; CHECK-LNX-NEXT: stdu 1, -32(1) ; CHECK-LNX-NEXT: stdu 1, -32(1)
; CHECK-LNX-NEXT: std 0, 48(1)
; CHECK-LNX-NEXT: .cfi_def_cfa_offset 32 ; CHECK-LNX-NEXT: .cfi_def_cfa_offset 32
; CHECK-LNX-NEXT: .cfi_offset lr, 16 ; CHECK-LNX-NEXT: .cfi_offset lr, 16
; CHECK-LNX-NEXT: addis 3, 2, .LCPI4_0@toc@ha ; CHECK-LNX-NEXT: addis 3, 2, .LCPI4_0@toc@ha
; CHECK-LNX-NEXT: lfs 2, .LCPI4_0@toc@l(3) ; CHECK-LNX-NEXT: lfs 2, .LCPI4_0@toc@l(3)
; CHECK-LNX-NEXT: bl __xl_powf_finite ; CHECK-LNX-NEXT: bl __xl_powf_finite
; CHECK-LNX-NEXT: nop ; CHECK-LNX-NEXT: nop
; CHECK-LNX-NEXT: addi 1, 1, 32 ; CHECK-LNX-NEXT: addi 1, 1, 32
; CHECK-LNX-NEXT: ld 0, 16(1) ; CHECK-LNX-NEXT: ld 0, 16(1)
; CHECK-LNX-NEXT: mtlr 0 ; CHECK-LNX-NEXT: mtlr 0
; CHECK-LNX-NEXT: blr ; CHECK-LNX-NEXT: blr
; ;
; CHECK-AIX-LABEL: powf_f32_fast050: ; CHECK-AIX-LABEL: powf_f32_fast050:
; CHECK-AIX: # %bb.0: # %entry ; CHECK-AIX: # %bb.0: # %entry
; CHECK-AIX-NEXT: mflr 0 ; CHECK-AIX-NEXT: mflr 0
; CHECK-AIX-NEXT: stw 0, 8(1)
; CHECK-AIX-NEXT: stwu 1, -64(1) ; CHECK-AIX-NEXT: stwu 1, -64(1)
; CHECK-AIX-NEXT: lwz 3, L..C4(2) # %const.0 ; CHECK-AIX-NEXT: lwz 3, L..C4(2) # %const.0
; CHECK-AIX-NEXT: stw 0, 72(1)
; CHECK-AIX-NEXT: lfs 2, 0(3) ; CHECK-AIX-NEXT: lfs 2, 0(3)
; CHECK-AIX-NEXT: bl .__xl_powf_finite[PR] ; CHECK-AIX-NEXT: bl .__xl_powf_finite[PR]
; CHECK-AIX-NEXT: nop ; CHECK-AIX-NEXT: nop
; CHECK-AIX-NEXT: addi 1, 1, 64 ; CHECK-AIX-NEXT: addi 1, 1, 64
; CHECK-AIX-NEXT: lwz 0, 8(1) ; CHECK-AIX-NEXT: lwz 0, 8(1)
; CHECK-AIX-NEXT: mtlr 0 ; CHECK-AIX-NEXT: mtlr 0
; CHECK-AIX-NEXT: blr ; CHECK-AIX-NEXT: blr
entry: entry:
%call = tail call nnan ninf afn nsz float @powf(float %a, float 5.000000e-01) %call = tail call nnan ninf afn nsz float @powf(float %a, float 5.000000e-01)
ret float %call ret float %call
} }
; fast-math pow with 0.50 ; fast-math pow with 0.50
define double @pow_f64_fast050(double %a) #1 { define double @pow_f64_fast050(double %a) #1 {
; ;
; CHECK-LNX-LABEL: pow_f64_fast050: ; CHECK-LNX-LABEL: pow_f64_fast050:
; CHECK-LNX: # %bb.0: # %entry ; CHECK-LNX: # %bb.0: # %entry
; CHECK-LNX-NEXT: mflr 0 ; CHECK-LNX-NEXT: mflr 0
; CHECK-LNX-NEXT: std 0, 16(1)
; CHECK-LNX-NEXT: stdu 1, -32(1) ; CHECK-LNX-NEXT: stdu 1, -32(1)
; CHECK-LNX-NEXT: std 0, 48(1)
; CHECK-LNX-NEXT: .cfi_def_cfa_offset 32 ; CHECK-LNX-NEXT: .cfi_def_cfa_offset 32
; CHECK-LNX-NEXT: .cfi_offset lr, 16 ; CHECK-LNX-NEXT: .cfi_offset lr, 16
; CHECK-LNX-NEXT: addis 3, 2, .LCPI5_0@toc@ha ; CHECK-LNX-NEXT: addis 3, 2, .LCPI5_0@toc@ha
; CHECK-LNX-NEXT: lfs 2, .LCPI5_0@toc@l(3) ; CHECK-LNX-NEXT: lfs 2, .LCPI5_0@toc@l(3)
; CHECK-LNX-NEXT: bl __xl_pow_finite ; CHECK-LNX-NEXT: bl __xl_pow_finite
; CHECK-LNX-NEXT: nop ; CHECK-LNX-NEXT: nop
; CHECK-LNX-NEXT: addi 1, 1, 32 ; CHECK-LNX-NEXT: addi 1, 1, 32
; CHECK-LNX-NEXT: ld 0, 16(1) ; CHECK-LNX-NEXT: ld 0, 16(1)
; CHECK-LNX-NEXT: mtlr 0 ; CHECK-LNX-NEXT: mtlr 0
; CHECK-LNX-NEXT: blr ; CHECK-LNX-NEXT: blr
; ;
; CHECK-AIX-LABEL: pow_f64_fast050: ; CHECK-AIX-LABEL: pow_f64_fast050:
; CHECK-AIX: # %bb.0: # %entry ; CHECK-AIX: # %bb.0: # %entry
; CHECK-AIX-NEXT: mflr 0 ; CHECK-AIX-NEXT: mflr 0
; CHECK-AIX-NEXT: stw 0, 8(1)
; CHECK-AIX-NEXT: stwu 1, -64(1) ; CHECK-AIX-NEXT: stwu 1, -64(1)
; CHECK-AIX-NEXT: lwz 3, L..C5(2) # %const.0 ; CHECK-AIX-NEXT: lwz 3, L..C5(2) # %const.0
; CHECK-AIX-NEXT: stw 0, 72(1)
; CHECK-AIX-NEXT: lfs 2, 0(3) ; CHECK-AIX-NEXT: lfs 2, 0(3)
; CHECK-AIX-NEXT: bl .__xl_pow_finite[PR] ; CHECK-AIX-NEXT: bl .__xl_pow_finite[PR]
; CHECK-AIX-NEXT: nop ; CHECK-AIX-NEXT: nop
; CHECK-AIX-NEXT: addi 1, 1, 64 ; CHECK-AIX-NEXT: addi 1, 1, 64
; CHECK-AIX-NEXT: lwz 0, 8(1) ; CHECK-AIX-NEXT: lwz 0, 8(1)
; CHECK-AIX-NEXT: mtlr 0 ; CHECK-AIX-NEXT: mtlr 0
; CHECK-AIX-NEXT: blr ; CHECK-AIX-NEXT: blr
entry: entry:
%call = tail call nnan ninf afn nsz double @pow(double %a, double 5.000000e-01) %call = tail call nnan ninf afn nsz double @pow(double %a, double 5.000000e-01)
ret double %call ret double %call
} }
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; fast-math __powf_finite with 0.25 ; fast-math __powf_finite with 0.25
define float @__powf_finite_f32_fast025(float %a) #1 { define float @__powf_finite_f32_fast025(float %a) #1 {
; ;
; CHECK-LNX-LABEL: __powf_finite_f32_fast025: ; CHECK-LNX-LABEL: __powf_finite_f32_fast025:
; CHECK-LNX: # %bb.0: # %entry ; CHECK-LNX: # %bb.0: # %entry
; CHECK-LNX-NEXT: mflr 0 ; CHECK-LNX-NEXT: mflr 0
; CHECK-LNX-NEXT: std 0, 16(1)
; CHECK-LNX-NEXT: stdu 1, -32(1) ; CHECK-LNX-NEXT: stdu 1, -32(1)
; CHECK-LNX-NEXT: std 0, 48(1)
; CHECK-LNX-NEXT: .cfi_def_cfa_offset 32 ; CHECK-LNX-NEXT: .cfi_def_cfa_offset 32
; CHECK-LNX-NEXT: .cfi_offset lr, 16 ; CHECK-LNX-NEXT: .cfi_offset lr, 16
; CHECK-LNX-NEXT: addis 3, 2, .LCPI6_0@toc@ha ; CHECK-LNX-NEXT: addis 3, 2, .LCPI6_0@toc@ha
; CHECK-LNX-NEXT: lfs 2, .LCPI6_0@toc@l(3) ; CHECK-LNX-NEXT: lfs 2, .LCPI6_0@toc@l(3)
; CHECK-LNX-NEXT: bl __xl_powf_finite ; CHECK-LNX-NEXT: bl __xl_powf_finite
; CHECK-LNX-NEXT: nop ; CHECK-LNX-NEXT: nop
; CHECK-LNX-NEXT: addi 1, 1, 32 ; CHECK-LNX-NEXT: addi 1, 1, 32
; CHECK-LNX-NEXT: ld 0, 16(1) ; CHECK-LNX-NEXT: ld 0, 16(1)
; CHECK-LNX-NEXT: mtlr 0 ; CHECK-LNX-NEXT: mtlr 0
; CHECK-LNX-NEXT: blr ; CHECK-LNX-NEXT: blr
; ;
; CHECK-AIX-LABEL: __powf_finite_f32_fast025: ; CHECK-AIX-LABEL: __powf_finite_f32_fast025:
; CHECK-AIX: # %bb.0: # %entry ; CHECK-AIX: # %bb.0: # %entry
; CHECK-AIX-NEXT: mflr 0 ; CHECK-AIX-NEXT: mflr 0
; CHECK-AIX-NEXT: stw 0, 8(1)
; CHECK-AIX-NEXT: stwu 1, -64(1) ; CHECK-AIX-NEXT: stwu 1, -64(1)
; CHECK-AIX-NEXT: lwz 3, L..C6(2) # %const.0 ; CHECK-AIX-NEXT: lwz 3, L..C6(2) # %const.0
; CHECK-AIX-NEXT: stw 0, 72(1)
; CHECK-AIX-NEXT: lfs 2, 0(3) ; CHECK-AIX-NEXT: lfs 2, 0(3)
; CHECK-AIX-NEXT: bl .__xl_powf_finite[PR] ; CHECK-AIX-NEXT: bl .__xl_powf_finite[PR]
; CHECK-AIX-NEXT: nop ; CHECK-AIX-NEXT: nop
; CHECK-AIX-NEXT: addi 1, 1, 64 ; CHECK-AIX-NEXT: addi 1, 1, 64
; CHECK-AIX-NEXT: lwz 0, 8(1) ; CHECK-AIX-NEXT: lwz 0, 8(1)
; CHECK-AIX-NEXT: mtlr 0 ; CHECK-AIX-NEXT: mtlr 0
; CHECK-AIX-NEXT: blr ; CHECK-AIX-NEXT: blr
entry: entry:
%call = tail call nnan ninf afn nsz float @__powf_finite(float %a, float 2.500000e-01) %call = tail call nnan ninf afn nsz float @__powf_finite(float %a, float 2.500000e-01)
ret float %call ret float %call
} }
; fast-math __pow_finite with 0.25 ; fast-math __pow_finite with 0.25
define double @__pow_finite_f64_fast025(double %a) #1 { define double @__pow_finite_f64_fast025(double %a) #1 {
; ;
; CHECK-LNX-LABEL: __pow_finite_f64_fast025: ; CHECK-LNX-LABEL: __pow_finite_f64_fast025:
; CHECK-LNX: # %bb.0: # %entry ; CHECK-LNX: # %bb.0: # %entry
; CHECK-LNX-NEXT: mflr 0 ; CHECK-LNX-NEXT: mflr 0
; CHECK-LNX-NEXT: std 0, 16(1)
; CHECK-LNX-NEXT: stdu 1, -32(1) ; CHECK-LNX-NEXT: stdu 1, -32(1)
; CHECK-LNX-NEXT: std 0, 48(1)
; CHECK-LNX-NEXT: .cfi_def_cfa_offset 32 ; CHECK-LNX-NEXT: .cfi_def_cfa_offset 32
; CHECK-LNX-NEXT: .cfi_offset lr, 16 ; CHECK-LNX-NEXT: .cfi_offset lr, 16
; CHECK-LNX-NEXT: addis 3, 2, .LCPI7_0@toc@ha ; CHECK-LNX-NEXT: addis 3, 2, .LCPI7_0@toc@ha
; CHECK-LNX-NEXT: lfs 2, .LCPI7_0@toc@l(3) ; CHECK-LNX-NEXT: lfs 2, .LCPI7_0@toc@l(3)
; CHECK-LNX-NEXT: bl __xl_pow_finite ; CHECK-LNX-NEXT: bl __xl_pow_finite
; CHECK-LNX-NEXT: nop ; CHECK-LNX-NEXT: nop
; CHECK-LNX-NEXT: addi 1, 1, 32 ; CHECK-LNX-NEXT: addi 1, 1, 32
; CHECK-LNX-NEXT: ld 0, 16(1) ; CHECK-LNX-NEXT: ld 0, 16(1)
; CHECK-LNX-NEXT: mtlr 0 ; CHECK-LNX-NEXT: mtlr 0
; CHECK-LNX-NEXT: blr ; CHECK-LNX-NEXT: blr
; ;
; CHECK-AIX-LABEL: __pow_finite_f64_fast025: ; CHECK-AIX-LABEL: __pow_finite_f64_fast025:
; CHECK-AIX: # %bb.0: # %entry ; CHECK-AIX: # %bb.0: # %entry
; CHECK-AIX-NEXT: mflr 0 ; CHECK-AIX-NEXT: mflr 0
; CHECK-AIX-NEXT: stw 0, 8(1)
; CHECK-AIX-NEXT: stwu 1, -64(1) ; CHECK-AIX-NEXT: stwu 1, -64(1)
; CHECK-AIX-NEXT: lwz 3, L..C7(2) # %const.0 ; CHECK-AIX-NEXT: lwz 3, L..C7(2) # %const.0
; CHECK-AIX-NEXT: stw 0, 72(1)
; CHECK-AIX-NEXT: lfs 2, 0(3) ; CHECK-AIX-NEXT: lfs 2, 0(3)
; CHECK-AIX-NEXT: bl .__xl_pow_finite[PR] ; CHECK-AIX-NEXT: bl .__xl_pow_finite[PR]
; CHECK-AIX-NEXT: nop ; CHECK-AIX-NEXT: nop
; CHECK-AIX-NEXT: addi 1, 1, 64 ; CHECK-AIX-NEXT: addi 1, 1, 64
; CHECK-AIX-NEXT: lwz 0, 8(1) ; CHECK-AIX-NEXT: lwz 0, 8(1)
; CHECK-AIX-NEXT: mtlr 0 ; CHECK-AIX-NEXT: mtlr 0
; CHECK-AIX-NEXT: blr ; CHECK-AIX-NEXT: blr
entry: entry:
%call = tail call nnan ninf afn nsz double @__pow_finite(double %a, double 2.500000e-01) %call = tail call nnan ninf afn nsz double @__pow_finite(double %a, double 2.500000e-01)
ret double %call ret double %call
} }
; fast-math __powf_finite with 0.75 ; fast-math __powf_finite with 0.75
define float @__powf_finite_f32_fast075(float %a) #1 { define float @__powf_finite_f32_fast075(float %a) #1 {
; ;
; CHECK-LNX-LABEL: __powf_finite_f32_fast075: ; CHECK-LNX-LABEL: __powf_finite_f32_fast075:
; CHECK-LNX: # %bb.0: # %entry ; CHECK-LNX: # %bb.0: # %entry
; CHECK-LNX-NEXT: mflr 0 ; CHECK-LNX-NEXT: mflr 0
; CHECK-LNX-NEXT: std 0, 16(1)
; CHECK-LNX-NEXT: stdu 1, -32(1) ; CHECK-LNX-NEXT: stdu 1, -32(1)
; CHECK-LNX-NEXT: std 0, 48(1)
; CHECK-LNX-NEXT: .cfi_def_cfa_offset 32 ; CHECK-LNX-NEXT: .cfi_def_cfa_offset 32
; CHECK-LNX-NEXT: .cfi_offset lr, 16 ; CHECK-LNX-NEXT: .cfi_offset lr, 16
; CHECK-LNX-NEXT: addis 3, 2, .LCPI8_0@toc@ha ; CHECK-LNX-NEXT: addis 3, 2, .LCPI8_0@toc@ha
; CHECK-LNX-NEXT: lfs 2, .LCPI8_0@toc@l(3) ; CHECK-LNX-NEXT: lfs 2, .LCPI8_0@toc@l(3)
; CHECK-LNX-NEXT: bl __xl_powf_finite ; CHECK-LNX-NEXT: bl __xl_powf_finite
; CHECK-LNX-NEXT: nop ; CHECK-LNX-NEXT: nop
; CHECK-LNX-NEXT: addi 1, 1, 32 ; CHECK-LNX-NEXT: addi 1, 1, 32
; CHECK-LNX-NEXT: ld 0, 16(1) ; CHECK-LNX-NEXT: ld 0, 16(1)
; CHECK-LNX-NEXT: mtlr 0 ; CHECK-LNX-NEXT: mtlr 0
; CHECK-LNX-NEXT: blr ; CHECK-LNX-NEXT: blr
; ;
; CHECK-AIX-LABEL: __powf_finite_f32_fast075: ; CHECK-AIX-LABEL: __powf_finite_f32_fast075:
; CHECK-AIX: # %bb.0: # %entry ; CHECK-AIX: # %bb.0: # %entry
; CHECK-AIX-NEXT: mflr 0 ; CHECK-AIX-NEXT: mflr 0
; CHECK-AIX-NEXT: stw 0, 8(1)
; CHECK-AIX-NEXT: stwu 1, -64(1) ; CHECK-AIX-NEXT: stwu 1, -64(1)
; CHECK-AIX-NEXT: lwz 3, L..C8(2) # %const.0 ; CHECK-AIX-NEXT: lwz 3, L..C8(2) # %const.0
; CHECK-AIX-NEXT: stw 0, 72(1)
; CHECK-AIX-NEXT: lfs 2, 0(3) ; CHECK-AIX-NEXT: lfs 2, 0(3)
; CHECK-AIX-NEXT: bl .__xl_powf_finite[PR] ; CHECK-AIX-NEXT: bl .__xl_powf_finite[PR]
; CHECK-AIX-NEXT: nop ; CHECK-AIX-NEXT: nop
; CHECK-AIX-NEXT: addi 1, 1, 64 ; CHECK-AIX-NEXT: addi 1, 1, 64
; CHECK-AIX-NEXT: lwz 0, 8(1) ; CHECK-AIX-NEXT: lwz 0, 8(1)
; CHECK-AIX-NEXT: mtlr 0 ; CHECK-AIX-NEXT: mtlr 0
; CHECK-AIX-NEXT: blr ; CHECK-AIX-NEXT: blr
entry: entry:
%call = tail call nnan ninf afn nsz float @__powf_finite(float %a, float 7.500000e-01) %call = tail call nnan ninf afn nsz float @__powf_finite(float %a, float 7.500000e-01)
ret float %call ret float %call
} }
; fast-math __pow_finite with 0.75 ; fast-math __pow_finite with 0.75
define double @__pow_finite_f64_fast075(double %a) #1 { define double @__pow_finite_f64_fast075(double %a) #1 {
; ;
; CHECK-LNX-LABEL: __pow_finite_f64_fast075: ; CHECK-LNX-LABEL: __pow_finite_f64_fast075:
; CHECK-LNX: # %bb.0: # %entry ; CHECK-LNX: # %bb.0: # %entry
; CHECK-LNX-NEXT: mflr 0 ; CHECK-LNX-NEXT: mflr 0
; CHECK-LNX-NEXT: std 0, 16(1)
; CHECK-LNX-NEXT: stdu 1, -32(1) ; CHECK-LNX-NEXT: stdu 1, -32(1)
; CHECK-LNX-NEXT: std 0, 48(1)
; CHECK-LNX-NEXT: .cfi_def_cfa_offset 32 ; CHECK-LNX-NEXT: .cfi_def_cfa_offset 32
; CHECK-LNX-NEXT: .cfi_offset lr, 16 ; CHECK-LNX-NEXT: .cfi_offset lr, 16
; CHECK-LNX-NEXT: addis 3, 2, .LCPI9_0@toc@ha ; CHECK-LNX-NEXT: addis 3, 2, .LCPI9_0@toc@ha
; CHECK-LNX-NEXT: lfs 2, .LCPI9_0@toc@l(3) ; CHECK-LNX-NEXT: lfs 2, .LCPI9_0@toc@l(3)
; CHECK-LNX-NEXT: bl __xl_pow_finite ; CHECK-LNX-NEXT: bl __xl_pow_finite
; CHECK-LNX-NEXT: nop ; CHECK-LNX-NEXT: nop
; CHECK-LNX-NEXT: addi 1, 1, 32 ; CHECK-LNX-NEXT: addi 1, 1, 32
; CHECK-LNX-NEXT: ld 0, 16(1) ; CHECK-LNX-NEXT: ld 0, 16(1)
; CHECK-LNX-NEXT: mtlr 0 ; CHECK-LNX-NEXT: mtlr 0
; CHECK-LNX-NEXT: blr ; CHECK-LNX-NEXT: blr
; ;
; CHECK-AIX-LABEL: __pow_finite_f64_fast075: ; CHECK-AIX-LABEL: __pow_finite_f64_fast075:
; CHECK-AIX: # %bb.0: # %entry ; CHECK-AIX: # %bb.0: # %entry
; CHECK-AIX-NEXT: mflr 0 ; CHECK-AIX-NEXT: mflr 0
; CHECK-AIX-NEXT: stw 0, 8(1)
; CHECK-AIX-NEXT: stwu 1, -64(1) ; CHECK-AIX-NEXT: stwu 1, -64(1)
; CHECK-AIX-NEXT: lwz 3, L..C9(2) # %const.0 ; CHECK-AIX-NEXT: lwz 3, L..C9(2) # %const.0
; CHECK-AIX-NEXT: stw 0, 72(1)
; CHECK-AIX-NEXT: lfs 2, 0(3) ; CHECK-AIX-NEXT: lfs 2, 0(3)
; CHECK-AIX-NEXT: bl .__xl_pow_finite[PR] ; CHECK-AIX-NEXT: bl .__xl_pow_finite[PR]
; CHECK-AIX-NEXT: nop ; CHECK-AIX-NEXT: nop
; CHECK-AIX-NEXT: addi 1, 1, 64 ; CHECK-AIX-NEXT: addi 1, 1, 64
; CHECK-AIX-NEXT: lwz 0, 8(1) ; CHECK-AIX-NEXT: lwz 0, 8(1)
; CHECK-AIX-NEXT: mtlr 0 ; CHECK-AIX-NEXT: mtlr 0
; CHECK-AIX-NEXT: blr ; CHECK-AIX-NEXT: blr
entry: entry:
%call = tail call nnan ninf afn nsz double @__pow_finite(double %a, double 7.500000e-01) %call = tail call nnan ninf afn nsz double @__pow_finite(double %a, double 7.500000e-01)
ret double %call ret double %call
} }
; fast-math __powf_finite with 0.50 ; fast-math __powf_finite with 0.50
define float @__powf_finite_f32_fast050(float %a) #1 { define float @__powf_finite_f32_fast050(float %a) #1 {
; ;
; CHECK-LNX-LABEL: __powf_finite_f32_fast050: ; CHECK-LNX-LABEL: __powf_finite_f32_fast050:
; CHECK-LNX: # %bb.0: # %entry ; CHECK-LNX: # %bb.0: # %entry
; CHECK-LNX-NEXT: mflr 0 ; CHECK-LNX-NEXT: mflr 0
; CHECK-LNX-NEXT: std 0, 16(1)
; CHECK-LNX-NEXT: stdu 1, -32(1) ; CHECK-LNX-NEXT: stdu 1, -32(1)
; CHECK-LNX-NEXT: std 0, 48(1)
; CHECK-LNX-NEXT: .cfi_def_cfa_offset 32 ; CHECK-LNX-NEXT: .cfi_def_cfa_offset 32
; CHECK-LNX-NEXT: .cfi_offset lr, 16 ; CHECK-LNX-NEXT: .cfi_offset lr, 16
; CHECK-LNX-NEXT: addis 3, 2, .LCPI10_0@toc@ha ; CHECK-LNX-NEXT: addis 3, 2, .LCPI10_0@toc@ha
; CHECK-LNX-NEXT: lfs 2, .LCPI10_0@toc@l(3) ; CHECK-LNX-NEXT: lfs 2, .LCPI10_0@toc@l(3)
; CHECK-LNX-NEXT: bl __xl_powf_finite ; CHECK-LNX-NEXT: bl __xl_powf_finite
; CHECK-LNX-NEXT: nop ; CHECK-LNX-NEXT: nop
; CHECK-LNX-NEXT: addi 1, 1, 32 ; CHECK-LNX-NEXT: addi 1, 1, 32
; CHECK-LNX-NEXT: ld 0, 16(1) ; CHECK-LNX-NEXT: ld 0, 16(1)
; CHECK-LNX-NEXT: mtlr 0 ; CHECK-LNX-NEXT: mtlr 0
; CHECK-LNX-NEXT: blr ; CHECK-LNX-NEXT: blr
; ;
; CHECK-AIX-LABEL: __powf_finite_f32_fast050: ; CHECK-AIX-LABEL: __powf_finite_f32_fast050:
; CHECK-AIX: # %bb.0: # %entry ; CHECK-AIX: # %bb.0: # %entry
; CHECK-AIX-NEXT: mflr 0 ; CHECK-AIX-NEXT: mflr 0
; CHECK-AIX-NEXT: stw 0, 8(1)
; CHECK-AIX-NEXT: stwu 1, -64(1) ; CHECK-AIX-NEXT: stwu 1, -64(1)
; CHECK-AIX-NEXT: lwz 3, L..C10(2) # %const.0 ; CHECK-AIX-NEXT: lwz 3, L..C10(2) # %const.0
; CHECK-AIX-NEXT: stw 0, 72(1)
; CHECK-AIX-NEXT: lfs 2, 0(3) ; CHECK-AIX-NEXT: lfs 2, 0(3)
; CHECK-AIX-NEXT: bl .__xl_powf_finite[PR] ; CHECK-AIX-NEXT: bl .__xl_powf_finite[PR]
; CHECK-AIX-NEXT: nop ; CHECK-AIX-NEXT: nop
; CHECK-AIX-NEXT: addi 1, 1, 64 ; CHECK-AIX-NEXT: addi 1, 1, 64
; CHECK-AIX-NEXT: lwz 0, 8(1) ; CHECK-AIX-NEXT: lwz 0, 8(1)
; CHECK-AIX-NEXT: mtlr 0 ; CHECK-AIX-NEXT: mtlr 0
; CHECK-AIX-NEXT: blr ; CHECK-AIX-NEXT: blr
entry: entry:
%call = tail call nnan ninf afn nsz float @__powf_finite(float %a, float 5.000000e-01) %call = tail call nnan ninf afn nsz float @__powf_finite(float %a, float 5.000000e-01)
ret float %call ret float %call
} }
; fast-math __pow_finite with 0.50 ; fast-math __pow_finite with 0.50
define double @__pow_finite_f64_fast050(double %a) #1 { define double @__pow_finite_f64_fast050(double %a) #1 {
; ;
; CHECK-LNX-LABEL: __pow_finite_f64_fast050: ; CHECK-LNX-LABEL: __pow_finite_f64_fast050:
; CHECK-LNX: # %bb.0: # %entry ; CHECK-LNX: # %bb.0: # %entry
; CHECK-LNX-NEXT: mflr 0 ; CHECK-LNX-NEXT: mflr 0
; CHECK-LNX-NEXT: std 0, 16(1)
; CHECK-LNX-NEXT: stdu 1, -32(1) ; CHECK-LNX-NEXT: stdu 1, -32(1)
; CHECK-LNX-NEXT: std 0, 48(1)
; CHECK-LNX-NEXT: .cfi_def_cfa_offset 32 ; CHECK-LNX-NEXT: .cfi_def_cfa_offset 32
; CHECK-LNX-NEXT: .cfi_offset lr, 16 ; CHECK-LNX-NEXT: .cfi_offset lr, 16
; CHECK-LNX-NEXT: addis 3, 2, .LCPI11_0@toc@ha ; CHECK-LNX-NEXT: addis 3, 2, .LCPI11_0@toc@ha
; CHECK-LNX-NEXT: lfs 2, .LCPI11_0@toc@l(3) ; CHECK-LNX-NEXT: lfs 2, .LCPI11_0@toc@l(3)
; CHECK-LNX-NEXT: bl __xl_pow_finite ; CHECK-LNX-NEXT: bl __xl_pow_finite
; CHECK-LNX-NEXT: nop ; CHECK-LNX-NEXT: nop
; CHECK-LNX-NEXT: addi 1, 1, 32 ; CHECK-LNX-NEXT: addi 1, 1, 32
; CHECK-LNX-NEXT: ld 0, 16(1) ; CHECK-LNX-NEXT: ld 0, 16(1)
; CHECK-LNX-NEXT: mtlr 0 ; CHECK-LNX-NEXT: mtlr 0
; CHECK-LNX-NEXT: blr ; CHECK-LNX-NEXT: blr
; ;
; CHECK-AIX-LABEL: __pow_finite_f64_fast050: ; CHECK-AIX-LABEL: __pow_finite_f64_fast050:
; CHECK-AIX: # %bb.0: # %entry ; CHECK-AIX: # %bb.0: # %entry
; CHECK-AIX-NEXT: mflr 0 ; CHECK-AIX-NEXT: mflr 0
; CHECK-AIX-NEXT: stw 0, 8(1)
; CHECK-AIX-NEXT: stwu 1, -64(1) ; CHECK-AIX-NEXT: stwu 1, -64(1)
; CHECK-AIX-NEXT: lwz 3, L..C11(2) # %const.0 ; CHECK-AIX-NEXT: lwz 3, L..C11(2) # %const.0
; CHECK-AIX-NEXT: stw 0, 72(1)
; CHECK-AIX-NEXT: lfs 2, 0(3) ; CHECK-AIX-NEXT: lfs 2, 0(3)
; CHECK-AIX-NEXT: bl .__xl_pow_finite[PR] ; CHECK-AIX-NEXT: bl .__xl_pow_finite[PR]
; CHECK-AIX-NEXT: nop ; CHECK-AIX-NEXT: nop
; CHECK-AIX-NEXT: addi 1, 1, 64 ; CHECK-AIX-NEXT: addi 1, 1, 64
; CHECK-AIX-NEXT: lwz 0, 8(1) ; CHECK-AIX-NEXT: lwz 0, 8(1)
; CHECK-AIX-NEXT: mtlr 0 ; CHECK-AIX-NEXT: mtlr 0
; CHECK-AIX-NEXT: blr ; CHECK-AIX-NEXT: blr
entry: entry:
%call = tail call nnan ninf afn nsz double @__pow_finite(double %a, double 5.000000e-01) %call = tail call nnan ninf afn nsz double @__pow_finite(double %a, double 5.000000e-01)
ret double %call ret double %call
} }
attributes #1 = { "approx-func-fp-math"="true" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" } attributes #1 = { "approx-func-fp-math"="true" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" }

llvm/test/CodeGen/PowerPC/ppc-prologue.ll

; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu -frame-pointer=all | FileCheck %s ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu -frame-pointer=all | FileCheck %s
define i32 @_Z4funci(i32 %a) ssp { define i32 @_Z4funci(i32 %a) ssp {
; CHECK: mflr 0 ; CHECK: mflr 0
; CHECK-NEXT: stw 0, 4(1)
; CHECK-NEXT: stwu 1, -32(1) ; CHECK-NEXT: stwu 1, -32(1)
; CHECK-NEXT: stw 31, 28(1) ; CHECK-NEXT: stw 31, 28(1)
; CHECK-NEXT: stw 0, 36(1)
; CHECK: mr 31, 1 ; CHECK: mr 31, 1
entry: entry:
%a_addr = alloca i32 ; <ptr> [#uses=2] %a_addr = alloca i32 ; <ptr> [#uses=2]
%retval = alloca i32 ; <ptr> [#uses=2] %retval = alloca i32 ; <ptr> [#uses=2]
%0 = alloca i32 ; <ptr> [#uses=2] %0 = alloca i32 ; <ptr> [#uses=2]
%"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
store i32 %a, ptr %a_addr store i32 %a, ptr %a_addr
%1 = call i32 @_Z3barPi(ptr %a_addr) ; <i32> [#uses=1] %1 = call i32 @_Z3barPi(ptr %a_addr) ; <i32> [#uses=1]
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llvm/test/CodeGen/PowerPC/ppc-shrink-wrapping.ll

; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 %s -o - -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,ENABLE,CHECK-64,ENABLE-64 ; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 %s -o - -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,ENABLE,CHECK-64,ENABLE-64
; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu %s -o - -enable-shrink-wrap=false -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,DISABLE,CHECK-64,DISABLE-64 ; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu %s -o - -enable-shrink-wrap=false -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,DISABLE,CHECK-64,DISABLE-64
; RUN: llc -mtriple=powerpc-ibm-aix-xcoff -mattr=-altivec -mcpu=pwr8 %s -o - -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,ENABLE,CHECK-32,ENABLE-32 ; RUN: llc -mtriple=powerpc-ibm-aix-xcoff -mattr=-altivec -mcpu=pwr8 %s -o - -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,ENABLE,CHECK-32,ENABLE-32
; RUN: llc -mtriple=powerpc-ibm-aix-xcoff %s -o - -enable-shrink-wrap=false -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,DISABLE,CHECK-32,DISABLE-32 ; RUN: llc -mtriple=powerpc-ibm-aix-xcoff %s -o - -enable-shrink-wrap=false -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,DISABLE,CHECK-32,DISABLE-32
; RUN: llc -mtriple=powerpc64-ibm-aix-xcoff -mattr=-altivec -mcpu=pwr8 %s -o - -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,ENABLE,CHECK-64,ENABLE-64 ; RUN: llc -mtriple=powerpc64-ibm-aix-xcoff -mattr=-altivec -mcpu=pwr8 %s -o - -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,ENABLE,CHECK-64,ENABLE-64
; RUN: llc -mtriple=powerpc64-ibm-aix-xcoff %s -o - -enable-shrink-wrap=false -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,DISABLE,CHECK-64,DISABLE-64 ; RUN: llc -mtriple=powerpc64-ibm-aix-xcoff %s -o - -enable-shrink-wrap=false -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,DISABLE,CHECK-64,DISABLE-64,DISABLE-64-AIX
; ;
; ;
; Note: Lots of tests use inline asm instead of regular calls. ; Note: Lots of tests use inline asm instead of regular calls.
; This allows to have a better control on what the allocation will do. ; This allows to have a better control on what the allocation will do.
; Otherwise, we may have spill right in the entry block, defeating ; Otherwise, we may have spill right in the entry block, defeating
; shrink-wrapping. Moreover, some of the inline asm statement (nop) ; shrink-wrapping. Moreover, some of the inline asm statement (nop)
; are here to ensure that the related paths do not end up as critical ; are here to ensure that the related paths do not end up as critical
; edges. ; edges.
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; Prologue code. ; Prologue code.
; At a minimum, we save/restore the link register. Other registers may be saved ; At a minimum, we save/restore the link register. Other registers may be saved
; as well. ; as well.
; CHECK: mflr ; CHECK: mflr
; ;
; Compare the arguments and jump to exit. ; Compare the arguments and jump to exit.
; After the prologue is set. ; After the prologue is set.
; DISABLE: cmpw 3, 4 ; DISABLE: cmpw 3, 4
; DISABLE-32: stw 0,
; DISABLE-64-AIX: std 0,
; DISABLE-NEXT: bge 0, {{.*}}[[EXIT_LABEL:BB[0-9_]+]] ; DISABLE-NEXT: bge 0, {{.*}}[[EXIT_LABEL:BB[0-9_]+]]
; ;
; Store %a on the stack ; Store %a on the stack
; CHECK: stw 3, {{[0-9]+([0-9]+)}} ; CHECK: stw 3, {{[0-9]+([0-9]+)}}
; Set the alloca address in the second argument. ; Set the alloca address in the second argument.
; CHECK-NEXT: addi 4, 1, {{[0-9]+}} ; CHECK-NEXT: addi 4, 1, {{[0-9]+}}
; Set the first argument to zero. ; Set the first argument to zero.
; CHECK-NEXT: li 3, 0 ; CHECK-NEXT: li 3, 0
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; ;
; ENABLE: cmplwi 3, 0 ; ENABLE: cmplwi 3, 0
; ENABLE-NEXT: beq 0, {{.*}}[[ELSE_LABEL:BB[0-9_]+]] ; ENABLE-NEXT: beq 0, {{.*}}[[ELSE_LABEL:BB[0-9_]+]]
; ;
; Prologue code. ; Prologue code.
; CHECK: mflr {{[0-9]+}} ; CHECK: mflr {{[0-9]+}}
; ;
; DISABLE: cmplwi 3, 0 ; DISABLE: cmplwi 3, 0
; DISABLE-32: stw 0, 72(1)
; DISABLE-64-AIX: std 0,
; DISABLE-NEXT: beq 0, {{.*}}[[ELSE_LABEL:BB[0-9_]+]] ; DISABLE-NEXT: beq 0, {{.*}}[[ELSE_LABEL:BB[0-9_]+]]
; ;
; Setup of the varags. ; Setup of the varags.
; CHECK-64: mr 4, 3 ; CHECK-64: mr 4, 3
; CHECK-64-NEXT: mr 5, 3 ; CHECK-64-NEXT: mr 5, 3
; CHECK-64-NEXT: mr 6, 3 ; CHECK-64-NEXT: mr 6, 3
; CHECK-64-NEXT: mr 7, 3 ; CHECK-64-NEXT: mr 7, 3
; CHECK-64-NEXT: mr 8, 3 ; CHECK-64-NEXT: mr 8, 3
; CHECK-64-NEXT: mr 9, 3 ; CHECK-64-NEXT: mr 9, 3
; ;
; CHECK-32: mr 3, 4 ; CHECK-32: mr 3, 4
; CHECK-32-NEXT: mr 5, 4 ; CHECK-32-NEXT: mr 5, 4
; CHECK-32-NEXT: mr 6, 4 ; CHECK-32-NEXT: mr 6, 4
; CHECK-32-NEXT: mr 7, 4 ; CHECK-32-NEXT: mr 7, 4
; CHECK-32-NEXT: mr 8, 4 ; CHECK-32-NEXT: mr 8, 4
; CHECK-32-NEXT: mr 9, 4 ; CHECK-32-NEXT: mr 9, 4
; ENABLE-32-NEXT: stw 0, 72(1)
; ;
; CHECK-NEXT: bl {{.*}}someVariadicFunc ; CHECK-NEXT: bl {{.*}}someVariadicFunc
; CHECK: slwi 3, 3, 3 ; CHECK: slwi 3, 3, 3
; DISABLE: b {{.*}}[[EPILOGUE_BB:BB[0-9_]+]] ; DISABLE: b {{.*}}[[EPILOGUE_BB:BB[0-9_]+]]
; ;
; ENABLE: mtlr {{[0-9]+}} ; ENABLE: mtlr {{[0-9]+}}
; ENABLE-NEXT: blr ; ENABLE-NEXT: blr
; ;
Show All 29 Lines
; Make sure we do not insert unreachable code after noreturn function. ; Make sure we do not insert unreachable code after noreturn function.
; Although this is not incorrect to insert such code, it is useless ; Although this is not incorrect to insert such code, it is useless
; and it hurts the binary size. ; and it hurts the binary size.
; ;
; CHECK-LABEL: {{.*}}noreturn: ; CHECK-LABEL: {{.*}}noreturn:
; DISABLE: mflr {{[0-9]+}} ; DISABLE: mflr {{[0-9]+}}
; ;
; CHECK: cmplwi 3, 0 ; CHECK: cmplwi 3, 0
; DISABLE-32: stw 0, 72(1)
; DISABLE-64-AIX: std 0,
; CHECK-NEXT: bne{{[-]?}} 0, {{.*}}[[ABORT:BB[0-9_]+]] ; CHECK-NEXT: bne{{[-]?}} 0, {{.*}}[[ABORT:BB[0-9_]+]]
; ;
; CHECK: li 3, 42 ; CHECK: li 3, 42
; ;
; DISABLE: mtlr {{[0-9]+}} ; DISABLE: mtlr {{[0-9]+}}
; ;
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
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llvm/test/CodeGen/PowerPC/ppc32-nest.ll

Show All 11 Lines
; CHECK-NEXT: blr ; CHECK-NEXT: blr
ret ptr %arg ret ptr %arg
} }
define ptr @nest_caller(ptr %arg) nounwind { define ptr @nest_caller(ptr %arg) nounwind {
; CHECK-LABEL: nest_caller: ; CHECK-LABEL: nest_caller:
; CHECK: mr 11, 3 ; CHECK: mr 11, 3
; CHECK: stw 0, 20(1)
; CHECK-NEXT: bl nest_receiver ; CHECK-NEXT: bl nest_receiver
; CHECK: blr ; CHECK: blr
%result = call ptr @nest_receiver(ptr nest %arg) %result = call ptr @nest_receiver(ptr nest %arg)
ret ptr %result ret ptr %result
} }

llvm/test/CodeGen/PowerPC/ppc64-P9-setb.ll

Show First 20 Lines • Show All 1,237 Lines • ▼ Show 20 Lines
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: xscmpuqp cr0, v2, v3 ; CHECK-NEXT: xscmpuqp cr0, v2, v3
; CHECK-NEXT: setb r3, cr0 ; CHECK-NEXT: setb r3, cr0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-PWR8-LABEL: setbf128: ; CHECK-PWR8-LABEL: setbf128:
; CHECK-PWR8: # %bb.0: ; CHECK-PWR8: # %bb.0:
; CHECK-PWR8-NEXT: mflr r0 ; CHECK-PWR8-NEXT: mflr r0
; CHECK-PWR8-NEXT: std r0, 16(r1)
; CHECK-PWR8-NEXT: stdu r1, -96(r1) ; CHECK-PWR8-NEXT: stdu r1, -96(r1)
; CHECK-PWR8-NEXT: std r0, 112(r1)
; CHECK-PWR8-NEXT: .cfi_def_cfa_offset 96 ; CHECK-PWR8-NEXT: .cfi_def_cfa_offset 96
; CHECK-PWR8-NEXT: .cfi_offset lr, 16 ; CHECK-PWR8-NEXT: .cfi_offset lr, 16
; CHECK-PWR8-NEXT: .cfi_offset r30, -16 ; CHECK-PWR8-NEXT: .cfi_offset r30, -16
; CHECK-PWR8-NEXT: .cfi_offset v30, -48 ; CHECK-PWR8-NEXT: .cfi_offset v30, -48
; CHECK-PWR8-NEXT: .cfi_offset v31, -32 ; CHECK-PWR8-NEXT: .cfi_offset v31, -32
; CHECK-PWR8-NEXT: li r3, 48 ; CHECK-PWR8-NEXT: li r3, 48
; CHECK-PWR8-NEXT: std r30, 80(r1) # 8-byte Folded Spill ; CHECK-PWR8-NEXT: std r30, 80(r1) # 8-byte Folded Spill
; CHECK-PWR8-NEXT: stvx v30, r1, r3 # 16-byte Folded Spill ; CHECK-PWR8-NEXT: stvx v30, r1, r3 # 16-byte Folded Spill
▲ Show 20 Lines • Show All 158 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/ppc64-byval-larger-struct.ll

Show All 10 Lines
; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names < %s | FileCheck %s --check-prefix=P9BE ; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names < %s | FileCheck %s --check-prefix=P9BE
; RUN: llc -verify-machineinstrs --mtriple powerpc64-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs --mtriple powerpc64-unknown-linux-gnu \
; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names < %s | FileCheck %s --check-prefix=P10BE ; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names < %s | FileCheck %s --check-prefix=P10BE
define signext i8 @caller_9(ptr nocapture readonly byval([9 x i8]) %data) #0 { define signext i8 @caller_9(ptr nocapture readonly byval([9 x i8]) %data) #0 {
; P8LE-LABEL: caller_9: ; P8LE-LABEL: caller_9:
; P8LE: # %bb.0: # %entry ; P8LE: # %bb.0: # %entry
; P8LE-NEXT: mflr r0 ; P8LE-NEXT: mflr r0
; P8LE-NEXT: std r0, 16(r1)
; P8LE-NEXT: stdu r1, -80(r1) ; P8LE-NEXT: stdu r1, -80(r1)
; P8LE-NEXT: std r0, 96(r1)
; P8LE-NEXT: stb r4, 56(r1) ; P8LE-NEXT: stb r4, 56(r1)
; P8LE-NEXT: addi r5, r1, 71 ; P8LE-NEXT: addi r5, r1, 71
; P8LE-NEXT: std r3, 48(r1) ; P8LE-NEXT: std r3, 48(r1)
; P8LE-NEXT: lbz r4, 56(r1) ; P8LE-NEXT: lbz r4, 56(r1)
; P8LE-NEXT: stdx r3, 0, r5 ; P8LE-NEXT: stdx r3, 0, r5
; P8LE-NEXT: mr r3, r5 ; P8LE-NEXT: mr r3, r5
; P8LE-NEXT: stb r4, 79(r1) ; P8LE-NEXT: stb r4, 79(r1)
; P8LE-NEXT: bl callee ; P8LE-NEXT: bl callee
; P8LE-NEXT: nop ; P8LE-NEXT: nop
; P8LE-NEXT: li r3, 0 ; P8LE-NEXT: li r3, 0
; P8LE-NEXT: addi r1, r1, 80 ; P8LE-NEXT: addi r1, r1, 80
; P8LE-NEXT: ld r0, 16(r1) ; P8LE-NEXT: ld r0, 16(r1)
; P8LE-NEXT: mtlr r0 ; P8LE-NEXT: mtlr r0
; P8LE-NEXT: blr ; P8LE-NEXT: blr
; ;
; P9LE-LABEL: caller_9: ; P9LE-LABEL: caller_9:
; P9LE: # %bb.0: # %entry ; P9LE: # %bb.0: # %entry
; P9LE-NEXT: mflr r0 ; P9LE-NEXT: mflr r0
; P9LE-NEXT: std r0, 16(r1)
; P9LE-NEXT: stdu r1, -80(r1) ; P9LE-NEXT: stdu r1, -80(r1)
; P9LE-NEXT: std r0, 96(r1)
; P9LE-NEXT: stb r4, 56(r1) ; P9LE-NEXT: stb r4, 56(r1)
; P9LE-NEXT: addi r4, r1, 71 ; P9LE-NEXT: addi r4, r1, 71
; P9LE-NEXT: std r3, 48(r1)
; P9LE-NEXT: lbz r5, 56(r1) ; P9LE-NEXT: lbz r5, 56(r1)
; P9LE-NEXT: std r3, 48(r1)
; P9LE-NEXT: stdx r3, 0, r4 ; P9LE-NEXT: stdx r3, 0, r4
; P9LE-NEXT: mr r3, r4 ; P9LE-NEXT: mr r3, r4
; P9LE-NEXT: stb r5, 79(r1) ; P9LE-NEXT: stb r5, 79(r1)
; P9LE-NEXT: bl callee ; P9LE-NEXT: bl callee
; P9LE-NEXT: nop ; P9LE-NEXT: nop
; P9LE-NEXT: li r3, 0 ; P9LE-NEXT: li r3, 0
; P9LE-NEXT: addi r1, r1, 80 ; P9LE-NEXT: addi r1, r1, 80
; P9LE-NEXT: ld r0, 16(r1) ; P9LE-NEXT: ld r0, 16(r1)
Show All 17 Lines
; P10LE-NEXT: addi r1, r1, 80 ; P10LE-NEXT: addi r1, r1, 80
; P10LE-NEXT: ld r0, 16(r1) ; P10LE-NEXT: ld r0, 16(r1)
; P10LE-NEXT: mtlr r0 ; P10LE-NEXT: mtlr r0
; P10LE-NEXT: blr ; P10LE-NEXT: blr
; ;
; P8BE-LABEL: caller_9: ; P8BE-LABEL: caller_9:
; P8BE: # %bb.0: # %entry ; P8BE: # %bb.0: # %entry
; P8BE-NEXT: mflr r0 ; P8BE-NEXT: mflr r0
; P8BE-NEXT: std r0, 16(r1)
; P8BE-NEXT: stdu r1, -144(r1) ; P8BE-NEXT: stdu r1, -144(r1)
; P8BE-NEXT: std r0, 160(r1)
; P8BE-NEXT: stb r4, 200(r1) ; P8BE-NEXT: stb r4, 200(r1)
; P8BE-NEXT: addi r5, r1, 135 ; P8BE-NEXT: addi r5, r1, 135
; P8BE-NEXT: std r3, 192(r1) ; P8BE-NEXT: std r3, 192(r1)
; P8BE-NEXT: lbz r4, 200(r1) ; P8BE-NEXT: lbz r4, 200(r1)
; P8BE-NEXT: stdx r3, 0, r5 ; P8BE-NEXT: stdx r3, 0, r5
; P8BE-NEXT: mr r3, r5 ; P8BE-NEXT: mr r3, r5
; P8BE-NEXT: stb r4, 143(r1) ; P8BE-NEXT: stb r4, 143(r1)
; P8BE-NEXT: bl callee ; P8BE-NEXT: bl callee
; P8BE-NEXT: nop ; P8BE-NEXT: nop
; P8BE-NEXT: li r3, 0 ; P8BE-NEXT: li r3, 0
; P8BE-NEXT: addi r1, r1, 144 ; P8BE-NEXT: addi r1, r1, 144
; P8BE-NEXT: ld r0, 16(r1) ; P8BE-NEXT: ld r0, 16(r1)
; P8BE-NEXT: mtlr r0 ; P8BE-NEXT: mtlr r0
; P8BE-NEXT: blr ; P8BE-NEXT: blr
; ;
; P9BE-LABEL: caller_9: ; P9BE-LABEL: caller_9:
; P9BE: # %bb.0: # %entry ; P9BE: # %bb.0: # %entry
; P9BE-NEXT: mflr r0 ; P9BE-NEXT: mflr r0
; P9BE-NEXT: std r0, 16(r1)
; P9BE-NEXT: stdu r1, -144(r1) ; P9BE-NEXT: stdu r1, -144(r1)
; P9BE-NEXT: std r0, 160(r1)
; P9BE-NEXT: stb r4, 200(r1) ; P9BE-NEXT: stb r4, 200(r1)
; P9BE-NEXT: addi r4, r1, 135 ; P9BE-NEXT: addi r4, r1, 135
; P9BE-NEXT: std r3, 192(r1)
; P9BE-NEXT: lbz r5, 200(r1) ; P9BE-NEXT: lbz r5, 200(r1)
; P9BE-NEXT: std r3, 192(r1)
; P9BE-NEXT: stdx r3, 0, r4 ; P9BE-NEXT: stdx r3, 0, r4
; P9BE-NEXT: mr r3, r4 ; P9BE-NEXT: mr r3, r4
; P9BE-NEXT: stb r5, 143(r1) ; P9BE-NEXT: stb r5, 143(r1)
; P9BE-NEXT: bl callee ; P9BE-NEXT: bl callee
; P9BE-NEXT: nop ; P9BE-NEXT: nop
; P9BE-NEXT: li r3, 0 ; P9BE-NEXT: li r3, 0
; P9BE-NEXT: addi r1, r1, 144 ; P9BE-NEXT: addi r1, r1, 144
; P9BE-NEXT: ld r0, 16(r1) ; P9BE-NEXT: ld r0, 16(r1)
▲ Show 20 Lines • Show All 58 Lines • ▼ Show 20 Linesentry:
call void @callee(ptr nonnull %_param_data) call void @callee(ptr nonnull %_param_data)
ret i8 0 ret i8 0
} }
define signext i8 @caller_9_callee_9(ptr nocapture readonly byval([9 x i8]) %data) #0 { define signext i8 @caller_9_callee_9(ptr nocapture readonly byval([9 x i8]) %data) #0 {
; P8LE-LABEL: caller_9_callee_9: ; P8LE-LABEL: caller_9_callee_9:
; P8LE: # %bb.0: # %entry ; P8LE: # %bb.0: # %entry
; P8LE-NEXT: mflr r0 ; P8LE-NEXT: mflr r0
; P8LE-NEXT: std r0, 16(r1)
; P8LE-NEXT: stdu r1, -80(r1) ; P8LE-NEXT: stdu r1, -80(r1)
; P8LE-NEXT: std r0, 96(r1)
; P8LE-NEXT: stb r4, 56(r1) ; P8LE-NEXT: stb r4, 56(r1)
; P8LE-NEXT: addi r5, r1, 71 ; P8LE-NEXT: addi r5, r1, 71
; P8LE-NEXT: std r3, 48(r1) ; P8LE-NEXT: std r3, 48(r1)
; P8LE-NEXT: lbz r4, 56(r1) ; P8LE-NEXT: lbz r4, 56(r1)
; P8LE-NEXT: stdx r3, 0, r5 ; P8LE-NEXT: stdx r3, 0, r5
; P8LE-NEXT: ld r3, 48(r1)
; P8LE-NEXT: stb r4, 79(r1) ; P8LE-NEXT: stb r4, 79(r1)
; P8LE-NEXT: lbz r4, 56(r1) ; P8LE-NEXT: lbz r4, 56(r1)
; P8LE-NEXT: ld r3, 48(r1)
; P8LE-NEXT: bl callee_9 ; P8LE-NEXT: bl callee_9
; P8LE-NEXT: nop ; P8LE-NEXT: nop
; P8LE-NEXT: li r3, 0 ; P8LE-NEXT: li r3, 0
; P8LE-NEXT: addi r1, r1, 80 ; P8LE-NEXT: addi r1, r1, 80
; P8LE-NEXT: ld r0, 16(r1) ; P8LE-NEXT: ld r0, 16(r1)
; P8LE-NEXT: mtlr r0 ; P8LE-NEXT: mtlr r0
; P8LE-NEXT: blr ; P8LE-NEXT: blr
; ;
; P9LE-LABEL: caller_9_callee_9: ; P9LE-LABEL: caller_9_callee_9:
; P9LE: # %bb.0: # %entry ; P9LE: # %bb.0: # %entry
; P9LE-NEXT: mflr r0 ; P9LE-NEXT: mflr r0
; P9LE-NEXT: std r0, 16(r1)
; P9LE-NEXT: stdu r1, -80(r1) ; P9LE-NEXT: stdu r1, -80(r1)
; P9LE-NEXT: std r0, 96(r1)
; P9LE-NEXT: stb r4, 56(r1) ; P9LE-NEXT: stb r4, 56(r1)
; P9LE-NEXT: addi r4, r1, 71 ; P9LE-NEXT: addi r4, r1, 71
; P9LE-NEXT: std r3, 48(r1)
; P9LE-NEXT: lbz r5, 56(r1) ; P9LE-NEXT: lbz r5, 56(r1)
; P9LE-NEXT: std r3, 48(r1)
; P9LE-NEXT: stdx r3, 0, r4 ; P9LE-NEXT: stdx r3, 0, r4
; P9LE-NEXT: lbz r4, 56(r1) ; P9LE-NEXT: lbz r4, 56(r1)
; P9LE-NEXT: ld r3, 48(r1) ; P9LE-NEXT: ld r3, 48(r1)
; P9LE-NEXT: stb r5, 79(r1) ; P9LE-NEXT: stb r5, 79(r1)
; P9LE-NEXT: bl callee_9 ; P9LE-NEXT: bl callee_9
; P9LE-NEXT: nop ; P9LE-NEXT: nop
; P9LE-NEXT: li r3, 0 ; P9LE-NEXT: li r3, 0
; P9LE-NEXT: addi r1, r1, 80 ; P9LE-NEXT: addi r1, r1, 80
Show All 19 Lines
; P10LE-NEXT: addi r1, r1, 80 ; P10LE-NEXT: addi r1, r1, 80
; P10LE-NEXT: ld r0, 16(r1) ; P10LE-NEXT: ld r0, 16(r1)
; P10LE-NEXT: mtlr r0 ; P10LE-NEXT: mtlr r0
; P10LE-NEXT: blr ; P10LE-NEXT: blr
; ;
; P8BE-LABEL: caller_9_callee_9: ; P8BE-LABEL: caller_9_callee_9:
; P8BE: # %bb.0: # %entry ; P8BE: # %bb.0: # %entry
; P8BE-NEXT: mflr r0 ; P8BE-NEXT: mflr r0
; P8BE-NEXT: std r0, 16(r1)
; P8BE-NEXT: stdu r1, -144(r1) ; P8BE-NEXT: stdu r1, -144(r1)
; P8BE-NEXT: std r0, 160(r1)
; P8BE-NEXT: stb r4, 200(r1) ; P8BE-NEXT: stb r4, 200(r1)
; P8BE-NEXT: addi r5, r1, 135 ; P8BE-NEXT: addi r5, r1, 135
; P8BE-NEXT: std r3, 192(r1) ; P8BE-NEXT: std r3, 192(r1)
; P8BE-NEXT: lbz r4, 200(r1) ; P8BE-NEXT: lbz r4, 200(r1)
; P8BE-NEXT: stdx r3, 0, r5 ; P8BE-NEXT: stdx r3, 0, r5
; P8BE-NEXT: ld r3, 192(r1)
; P8BE-NEXT: stb r4, 143(r1) ; P8BE-NEXT: stb r4, 143(r1)
; P8BE-NEXT: lbz r4, 200(r1) ; P8BE-NEXT: lbz r4, 200(r1)
; P8BE-NEXT: ld r3, 192(r1)
; P8BE-NEXT: bl callee_9 ; P8BE-NEXT: bl callee_9
; P8BE-NEXT: nop ; P8BE-NEXT: nop
; P8BE-NEXT: li r3, 0 ; P8BE-NEXT: li r3, 0
; P8BE-NEXT: addi r1, r1, 144 ; P8BE-NEXT: addi r1, r1, 144
; P8BE-NEXT: ld r0, 16(r1) ; P8BE-NEXT: ld r0, 16(r1)
; P8BE-NEXT: mtlr r0 ; P8BE-NEXT: mtlr r0
; P8BE-NEXT: blr ; P8BE-NEXT: blr
; ;
; P9BE-LABEL: caller_9_callee_9: ; P9BE-LABEL: caller_9_callee_9:
; P9BE: # %bb.0: # %entry ; P9BE: # %bb.0: # %entry
; P9BE-NEXT: mflr r0 ; P9BE-NEXT: mflr r0
; P9BE-NEXT: std r0, 16(r1)
; P9BE-NEXT: stdu r1, -144(r1) ; P9BE-NEXT: stdu r1, -144(r1)
; P9BE-NEXT: std r0, 160(r1)
; P9BE-NEXT: stb r4, 200(r1) ; P9BE-NEXT: stb r4, 200(r1)
; P9BE-NEXT: addi r4, r1, 135 ; P9BE-NEXT: addi r4, r1, 135
; P9BE-NEXT: std r3, 192(r1)
; P9BE-NEXT: lbz r5, 200(r1) ; P9BE-NEXT: lbz r5, 200(r1)
; P9BE-NEXT: std r3, 192(r1)
; P9BE-NEXT: stdx r3, 0, r4 ; P9BE-NEXT: stdx r3, 0, r4
; P9BE-NEXT: lbz r4, 200(r1) ; P9BE-NEXT: lbz r4, 200(r1)
; P9BE-NEXT: ld r3, 192(r1) ; P9BE-NEXT: ld r3, 192(r1)
; P9BE-NEXT: stb r5, 143(r1) ; P9BE-NEXT: stb r5, 143(r1)
; P9BE-NEXT: bl callee_9 ; P9BE-NEXT: bl callee_9
; P9BE-NEXT: nop ; P9BE-NEXT: nop
; P9BE-NEXT: li r3, 0 ; P9BE-NEXT: li r3, 0
; P9BE-NEXT: addi r1, r1, 144 ; P9BE-NEXT: addi r1, r1, 144
▲ Show 20 Lines • Show All 60 Lines • ▼ Show 20 Linesentry:
call void @callee_9(ptr nocapture readonly byval([9 x i8]) %data) call void @callee_9(ptr nocapture readonly byval([9 x i8]) %data)
ret i8 0 ret i8 0
} }
define signext i8 @caller_10(ptr nocapture readonly byval([10 x i8]) %data) #0 { define signext i8 @caller_10(ptr nocapture readonly byval([10 x i8]) %data) #0 {
; P8LE-LABEL: caller_10: ; P8LE-LABEL: caller_10:
; P8LE: # %bb.0: # %entry ; P8LE: # %bb.0: # %entry
; P8LE-NEXT: mflr r0 ; P8LE-NEXT: mflr r0
; P8LE-NEXT: std r0, 16(r1)
; P8LE-NEXT: stdu r1, -80(r1) ; P8LE-NEXT: stdu r1, -80(r1)
; P8LE-NEXT: std r0, 96(r1)
; P8LE-NEXT: sth r4, 56(r1) ; P8LE-NEXT: sth r4, 56(r1)
; P8LE-NEXT: addi r5, r1, 70 ; P8LE-NEXT: addi r5, r1, 70
; P8LE-NEXT: std r3, 48(r1) ; P8LE-NEXT: std r3, 48(r1)
; P8LE-NEXT: lhz r4, 56(r1) ; P8LE-NEXT: lhz r4, 56(r1)
; P8LE-NEXT: stdx r3, 0, r5 ; P8LE-NEXT: stdx r3, 0, r5
; P8LE-NEXT: mr r3, r5 ; P8LE-NEXT: mr r3, r5
; P8LE-NEXT: sth r4, 78(r1) ; P8LE-NEXT: sth r4, 78(r1)
; P8LE-NEXT: bl callee ; P8LE-NEXT: bl callee
; P8LE-NEXT: nop ; P8LE-NEXT: nop
; P8LE-NEXT: li r3, 0 ; P8LE-NEXT: li r3, 0
; P8LE-NEXT: addi r1, r1, 80 ; P8LE-NEXT: addi r1, r1, 80
; P8LE-NEXT: ld r0, 16(r1) ; P8LE-NEXT: ld r0, 16(r1)
; P8LE-NEXT: mtlr r0 ; P8LE-NEXT: mtlr r0
; P8LE-NEXT: blr ; P8LE-NEXT: blr
; ;
; P9LE-LABEL: caller_10: ; P9LE-LABEL: caller_10:
; P9LE: # %bb.0: # %entry ; P9LE: # %bb.0: # %entry
; P9LE-NEXT: mflr r0 ; P9LE-NEXT: mflr r0
; P9LE-NEXT: std r0, 16(r1)
; P9LE-NEXT: stdu r1, -80(r1) ; P9LE-NEXT: stdu r1, -80(r1)
; P9LE-NEXT: std r0, 96(r1)
; P9LE-NEXT: sth r4, 56(r1) ; P9LE-NEXT: sth r4, 56(r1)
; P9LE-NEXT: addi r4, r1, 70 ; P9LE-NEXT: addi r4, r1, 70
; P9LE-NEXT: std r3, 48(r1)
; P9LE-NEXT: lhz r5, 56(r1) ; P9LE-NEXT: lhz r5, 56(r1)
; P9LE-NEXT: std r3, 48(r1)
; P9LE-NEXT: stdx r3, 0, r4 ; P9LE-NEXT: stdx r3, 0, r4
; P9LE-NEXT: mr r3, r4 ; P9LE-NEXT: mr r3, r4
; P9LE-NEXT: sth r5, 78(r1) ; P9LE-NEXT: sth r5, 78(r1)
; P9LE-NEXT: bl callee ; P9LE-NEXT: bl callee
; P9LE-NEXT: nop ; P9LE-NEXT: nop
; P9LE-NEXT: li r3, 0 ; P9LE-NEXT: li r3, 0
; P9LE-NEXT: addi r1, r1, 80 ; P9LE-NEXT: addi r1, r1, 80
; P9LE-NEXT: ld r0, 16(r1) ; P9LE-NEXT: ld r0, 16(r1)
Show All 17 Lines
; P10LE-NEXT: addi r1, r1, 80 ; P10LE-NEXT: addi r1, r1, 80
; P10LE-NEXT: ld r0, 16(r1) ; P10LE-NEXT: ld r0, 16(r1)
; P10LE-NEXT: mtlr r0 ; P10LE-NEXT: mtlr r0
; P10LE-NEXT: blr ; P10LE-NEXT: blr
; ;
; P8BE-LABEL: caller_10: ; P8BE-LABEL: caller_10:
; P8BE: # %bb.0: # %entry ; P8BE: # %bb.0: # %entry
; P8BE-NEXT: mflr r0 ; P8BE-NEXT: mflr r0
; P8BE-NEXT: std r0, 16(r1)
; P8BE-NEXT: stdu r1, -144(r1) ; P8BE-NEXT: stdu r1, -144(r1)
; P8BE-NEXT: std r0, 160(r1)
; P8BE-NEXT: sth r4, 200(r1) ; P8BE-NEXT: sth r4, 200(r1)
; P8BE-NEXT: addi r5, r1, 134 ; P8BE-NEXT: addi r5, r1, 134
; P8BE-NEXT: std r3, 192(r1) ; P8BE-NEXT: std r3, 192(r1)
; P8BE-NEXT: lhz r4, 200(r1) ; P8BE-NEXT: lhz r4, 200(r1)
; P8BE-NEXT: stdx r3, 0, r5 ; P8BE-NEXT: stdx r3, 0, r5
; P8BE-NEXT: mr r3, r5 ; P8BE-NEXT: mr r3, r5
; P8BE-NEXT: sth r4, 142(r1) ; P8BE-NEXT: sth r4, 142(r1)
; P8BE-NEXT: bl callee ; P8BE-NEXT: bl callee
; P8BE-NEXT: nop ; P8BE-NEXT: nop
; P8BE-NEXT: li r3, 0 ; P8BE-NEXT: li r3, 0
; P8BE-NEXT: addi r1, r1, 144 ; P8BE-NEXT: addi r1, r1, 144
; P8BE-NEXT: ld r0, 16(r1) ; P8BE-NEXT: ld r0, 16(r1)
; P8BE-NEXT: mtlr r0 ; P8BE-NEXT: mtlr r0
; P8BE-NEXT: blr ; P8BE-NEXT: blr
; ;
; P9BE-LABEL: caller_10: ; P9BE-LABEL: caller_10:
; P9BE: # %bb.0: # %entry ; P9BE: # %bb.0: # %entry
; P9BE-NEXT: mflr r0 ; P9BE-NEXT: mflr r0
; P9BE-NEXT: std r0, 16(r1)
; P9BE-NEXT: stdu r1, -144(r1) ; P9BE-NEXT: stdu r1, -144(r1)
; P9BE-NEXT: std r0, 160(r1)
; P9BE-NEXT: sth r4, 200(r1) ; P9BE-NEXT: sth r4, 200(r1)
; P9BE-NEXT: addi r4, r1, 134 ; P9BE-NEXT: addi r4, r1, 134
; P9BE-NEXT: std r3, 192(r1)
; P9BE-NEXT: lhz r5, 200(r1) ; P9BE-NEXT: lhz r5, 200(r1)
; P9BE-NEXT: std r3, 192(r1)
; P9BE-NEXT: stdx r3, 0, r4 ; P9BE-NEXT: stdx r3, 0, r4
; P9BE-NEXT: mr r3, r4 ; P9BE-NEXT: mr r3, r4
; P9BE-NEXT: sth r5, 142(r1) ; P9BE-NEXT: sth r5, 142(r1)
; P9BE-NEXT: bl callee ; P9BE-NEXT: bl callee
; P9BE-NEXT: nop ; P9BE-NEXT: nop
; P9BE-NEXT: li r3, 0 ; P9BE-NEXT: li r3, 0
; P9BE-NEXT: addi r1, r1, 144 ; P9BE-NEXT: addi r1, r1, 144
; P9BE-NEXT: ld r0, 16(r1) ; P9BE-NEXT: ld r0, 16(r1)
▲ Show 20 Lines • Show All 62 Lines • ▼ Show 20 Linesentry:
call void @callee(ptr nonnull %_param_data) call void @callee(ptr nonnull %_param_data)
ret i8 0 ret i8 0
} }
define signext i8 @caller_12(ptr nocapture readonly byval([12 x i8]) %data) #0 { define signext i8 @caller_12(ptr nocapture readonly byval([12 x i8]) %data) #0 {
; P8LE-LABEL: caller_12: ; P8LE-LABEL: caller_12:
; P8LE: # %bb.0: # %entry ; P8LE: # %bb.0: # %entry
; P8LE-NEXT: mflr r0 ; P8LE-NEXT: mflr r0
; P8LE-NEXT: std r0, 16(r1)
; P8LE-NEXT: stdu r1, -80(r1) ; P8LE-NEXT: stdu r1, -80(r1)
; P8LE-NEXT: std r0, 96(r1)
; P8LE-NEXT: stw r4, 56(r1) ; P8LE-NEXT: stw r4, 56(r1)
; P8LE-NEXT: addi r5, r1, 68 ; P8LE-NEXT: addi r5, r1, 68
; P8LE-NEXT: std r3, 48(r1) ; P8LE-NEXT: std r3, 48(r1)
; P8LE-NEXT: lwz r4, 56(r1) ; P8LE-NEXT: lwz r4, 56(r1)
; P8LE-NEXT: std r3, 68(r1) ; P8LE-NEXT: std r3, 68(r1)
; P8LE-NEXT: mr r3, r5 ; P8LE-NEXT: mr r3, r5
; P8LE-NEXT: stw r4, 76(r1) ; P8LE-NEXT: stw r4, 76(r1)
; P8LE-NEXT: bl callee ; P8LE-NEXT: bl callee
; P8LE-NEXT: nop ; P8LE-NEXT: nop
; P8LE-NEXT: li r3, 0 ; P8LE-NEXT: li r3, 0
; P8LE-NEXT: addi r1, r1, 80 ; P8LE-NEXT: addi r1, r1, 80
; P8LE-NEXT: ld r0, 16(r1) ; P8LE-NEXT: ld r0, 16(r1)
; P8LE-NEXT: mtlr r0 ; P8LE-NEXT: mtlr r0
; P8LE-NEXT: blr ; P8LE-NEXT: blr
; ;
; P9LE-LABEL: caller_12: ; P9LE-LABEL: caller_12:
; P9LE: # %bb.0: # %entry ; P9LE: # %bb.0: # %entry
; P9LE-NEXT: mflr r0 ; P9LE-NEXT: mflr r0
; P9LE-NEXT: std r0, 16(r1)
; P9LE-NEXT: stdu r1, -80(r1) ; P9LE-NEXT: stdu r1, -80(r1)
; P9LE-NEXT: std r0, 96(r1)
; P9LE-NEXT: stw r4, 56(r1) ; P9LE-NEXT: stw r4, 56(r1)
; P9LE-NEXT: addi r4, r1, 68 ; P9LE-NEXT: addi r4, r1, 68
; P9LE-NEXT: std r3, 48(r1)
; P9LE-NEXT: lwz r5, 56(r1) ; P9LE-NEXT: lwz r5, 56(r1)
; P9LE-NEXT: std r3, 48(r1)
; P9LE-NEXT: std r3, 68(r1) ; P9LE-NEXT: std r3, 68(r1)
; P9LE-NEXT: mr r3, r4 ; P9LE-NEXT: mr r3, r4
; P9LE-NEXT: stw r5, 76(r1) ; P9LE-NEXT: stw r5, 76(r1)
; P9LE-NEXT: bl callee ; P9LE-NEXT: bl callee
; P9LE-NEXT: nop ; P9LE-NEXT: nop
; P9LE-NEXT: li r3, 0 ; P9LE-NEXT: li r3, 0
; P9LE-NEXT: addi r1, r1, 80 ; P9LE-NEXT: addi r1, r1, 80
; P9LE-NEXT: ld r0, 16(r1) ; P9LE-NEXT: ld r0, 16(r1)
Show All 17 Lines
; P10LE-NEXT: addi r1, r1, 80 ; P10LE-NEXT: addi r1, r1, 80
; P10LE-NEXT: ld r0, 16(r1) ; P10LE-NEXT: ld r0, 16(r1)
; P10LE-NEXT: mtlr r0 ; P10LE-NEXT: mtlr r0
; P10LE-NEXT: blr ; P10LE-NEXT: blr
; ;
; P8BE-LABEL: caller_12: ; P8BE-LABEL: caller_12:
; P8BE: # %bb.0: # %entry ; P8BE: # %bb.0: # %entry
; P8BE-NEXT: mflr r0 ; P8BE-NEXT: mflr r0
; P8BE-NEXT: std r0, 16(r1)
; P8BE-NEXT: stdu r1, -144(r1) ; P8BE-NEXT: stdu r1, -144(r1)
; P8BE-NEXT: std r0, 160(r1)
; P8BE-NEXT: stw r4, 200(r1) ; P8BE-NEXT: stw r4, 200(r1)
; P8BE-NEXT: addi r5, r1, 132 ; P8BE-NEXT: addi r5, r1, 132
; P8BE-NEXT: std r3, 192(r1) ; P8BE-NEXT: std r3, 192(r1)
; P8BE-NEXT: lwz r4, 200(r1) ; P8BE-NEXT: lwz r4, 200(r1)
; P8BE-NEXT: std r3, 132(r1) ; P8BE-NEXT: std r3, 132(r1)
; P8BE-NEXT: mr r3, r5 ; P8BE-NEXT: mr r3, r5
; P8BE-NEXT: stw r4, 140(r1) ; P8BE-NEXT: stw r4, 140(r1)
; P8BE-NEXT: bl callee ; P8BE-NEXT: bl callee
; P8BE-NEXT: nop ; P8BE-NEXT: nop
; P8BE-NEXT: li r3, 0 ; P8BE-NEXT: li r3, 0
; P8BE-NEXT: addi r1, r1, 144 ; P8BE-NEXT: addi r1, r1, 144
; P8BE-NEXT: ld r0, 16(r1) ; P8BE-NEXT: ld r0, 16(r1)
; P8BE-NEXT: mtlr r0 ; P8BE-NEXT: mtlr r0
; P8BE-NEXT: blr ; P8BE-NEXT: blr
; ;
; P9BE-LABEL: caller_12: ; P9BE-LABEL: caller_12:
; P9BE: # %bb.0: # %entry ; P9BE: # %bb.0: # %entry
; P9BE-NEXT: mflr r0 ; P9BE-NEXT: mflr r0
; P9BE-NEXT: std r0, 16(r1)
; P9BE-NEXT: stdu r1, -144(r1) ; P9BE-NEXT: stdu r1, -144(r1)
; P9BE-NEXT: std r0, 160(r1)
; P9BE-NEXT: stw r4, 200(r1) ; P9BE-NEXT: stw r4, 200(r1)
; P9BE-NEXT: addi r4, r1, 132 ; P9BE-NEXT: addi r4, r1, 132
; P9BE-NEXT: std r3, 192(r1)
; P9BE-NEXT: lwz r5, 200(r1) ; P9BE-NEXT: lwz r5, 200(r1)
; P9BE-NEXT: std r3, 192(r1)
; P9BE-NEXT: std r3, 132(r1) ; P9BE-NEXT: std r3, 132(r1)
; P9BE-NEXT: mr r3, r4 ; P9BE-NEXT: mr r3, r4
; P9BE-NEXT: stw r5, 140(r1) ; P9BE-NEXT: stw r5, 140(r1)
; P9BE-NEXT: bl callee ; P9BE-NEXT: bl callee
; P9BE-NEXT: nop ; P9BE-NEXT: nop
; P9BE-NEXT: li r3, 0 ; P9BE-NEXT: li r3, 0
; P9BE-NEXT: addi r1, r1, 144 ; P9BE-NEXT: addi r1, r1, 144
; P9BE-NEXT: ld r0, 16(r1) ; P9BE-NEXT: ld r0, 16(r1)
▲ Show 20 Lines • Show All 70 Lines • ▼ Show 20 Linesentry:
call void @callee(ptr nonnull %_param_data) call void @callee(ptr nonnull %_param_data)
ret i8 0 ret i8 0
} }
define signext i8 @caller_14(ptr nocapture readonly byval([14 x i8]) %data) #0 { define signext i8 @caller_14(ptr nocapture readonly byval([14 x i8]) %data) #0 {
; P8LE-LABEL: caller_14: ; P8LE-LABEL: caller_14:
; P8LE: # %bb.0: # %entry ; P8LE: # %bb.0: # %entry
; P8LE-NEXT: mflr r0 ; P8LE-NEXT: mflr r0
; P8LE-NEXT: std r0, 16(r1)
; P8LE-NEXT: stdu r1, -80(r1) ; P8LE-NEXT: stdu r1, -80(r1)
; P8LE-NEXT: std r0, 96(r1)
; P8LE-NEXT: stw r4, 56(r1) ; P8LE-NEXT: stw r4, 56(r1)
; P8LE-NEXT: addi r5, r1, 66 ; P8LE-NEXT: addi r5, r1, 66
; P8LE-NEXT: rldicl r4, r4, 32, 32 ; P8LE-NEXT: rldicl r4, r4, 32, 32
; P8LE-NEXT: std r3, 48(r1) ; P8LE-NEXT: std r3, 48(r1)
; P8LE-NEXT: lwz r6, 56(r1) ; P8LE-NEXT: lwz r6, 56(r1)
; P8LE-NEXT: stdx r3, 0, r5 ; P8LE-NEXT: stdx r3, 0, r5
; P8LE-NEXT: mr r3, r5 ; P8LE-NEXT: mr r3, r5
; P8LE-NEXT: sth r4, 60(r1) ; P8LE-NEXT: sth r4, 60(r1)
; P8LE-NEXT: stw r6, 74(r1) ; P8LE-NEXT: stw r6, 74(r1)
; P8LE-NEXT: bl callee ; P8LE-NEXT: bl callee
; P8LE-NEXT: nop ; P8LE-NEXT: nop
; P8LE-NEXT: li r3, 0 ; P8LE-NEXT: li r3, 0
; P8LE-NEXT: addi r1, r1, 80 ; P8LE-NEXT: addi r1, r1, 80
; P8LE-NEXT: ld r0, 16(r1) ; P8LE-NEXT: ld r0, 16(r1)
; P8LE-NEXT: mtlr r0 ; P8LE-NEXT: mtlr r0
; P8LE-NEXT: blr ; P8LE-NEXT: blr
; ;
; P9LE-LABEL: caller_14: ; P9LE-LABEL: caller_14:
; P9LE: # %bb.0: # %entry ; P9LE: # %bb.0: # %entry
; P9LE-NEXT: mflr r0 ; P9LE-NEXT: mflr r0
; P9LE-NEXT: std r0, 16(r1)
; P9LE-NEXT: stdu r1, -80(r1) ; P9LE-NEXT: stdu r1, -80(r1)
; P9LE-NEXT: std r0, 96(r1)
; P9LE-NEXT: stw r4, 56(r1) ; P9LE-NEXT: stw r4, 56(r1)
; P9LE-NEXT: rldicl r4, r4, 32, 32
; P9LE-NEXT: lwz r5, 56(r1) ; P9LE-NEXT: lwz r5, 56(r1)
; P9LE-NEXT: rldicl r4, r4, 32, 32
; P9LE-NEXT: std r3, 48(r1) ; P9LE-NEXT: std r3, 48(r1)
; P9LE-NEXT: sth r4, 60(r1) ; P9LE-NEXT: sth r4, 60(r1)
; P9LE-NEXT: addi r4, r1, 66 ; P9LE-NEXT: addi r4, r1, 66
; P9LE-NEXT: stdx r3, 0, r4 ; P9LE-NEXT: stdx r3, 0, r4
; P9LE-NEXT: mr r3, r4 ; P9LE-NEXT: mr r3, r4
; P9LE-NEXT: stw r5, 74(r1) ; P9LE-NEXT: stw r5, 74(r1)
; P9LE-NEXT: bl callee ; P9LE-NEXT: bl callee
; P9LE-NEXT: nop ; P9LE-NEXT: nop
Show All 22 Lines
; P10LE-NEXT: addi r1, r1, 80 ; P10LE-NEXT: addi r1, r1, 80
; P10LE-NEXT: ld r0, 16(r1) ; P10LE-NEXT: ld r0, 16(r1)
; P10LE-NEXT: mtlr r0 ; P10LE-NEXT: mtlr r0
; P10LE-NEXT: blr ; P10LE-NEXT: blr
; ;
; P8BE-LABEL: caller_14: ; P8BE-LABEL: caller_14:
; P8BE: # %bb.0: # %entry ; P8BE: # %bb.0: # %entry
; P8BE-NEXT: mflr r0 ; P8BE-NEXT: mflr r0
; P8BE-NEXT: std r0, 16(r1)
; P8BE-NEXT: stdu r1, -144(r1) ; P8BE-NEXT: stdu r1, -144(r1)
; P8BE-NEXT: rldicl r6, r4, 48, 16 ; P8BE-NEXT: rldicl r6, r4, 48, 16
; P8BE-NEXT: std r0, 160(r1)
; P8BE-NEXT: addi r5, r1, 130 ; P8BE-NEXT: addi r5, r1, 130
; P8BE-NEXT: std r3, 192(r1) ; P8BE-NEXT: std r3, 192(r1)
; P8BE-NEXT: sth r4, 204(r1)
; P8BE-NEXT: stw r6, 200(r1)
; P8BE-NEXT: stdx r3, 0, r5 ; P8BE-NEXT: stdx r3, 0, r5
; P8BE-NEXT: mr r3, r5 ; P8BE-NEXT: mr r3, r5
; P8BE-NEXT: stw r6, 200(r1)
; P8BE-NEXT: lwz r6, 200(r1) ; P8BE-NEXT: lwz r6, 200(r1)
; P8BE-NEXT: sth r4, 204(r1)
; P8BE-NEXT: stw r6, 138(r1) ; P8BE-NEXT: stw r6, 138(r1)
; P8BE-NEXT: bl callee ; P8BE-NEXT: bl callee
; P8BE-NEXT: nop ; P8BE-NEXT: nop
; P8BE-NEXT: li r3, 0 ; P8BE-NEXT: li r3, 0
; P8BE-NEXT: addi r1, r1, 144 ; P8BE-NEXT: addi r1, r1, 144
; P8BE-NEXT: ld r0, 16(r1) ; P8BE-NEXT: ld r0, 16(r1)
; P8BE-NEXT: mtlr r0 ; P8BE-NEXT: mtlr r0
; P8BE-NEXT: blr ; P8BE-NEXT: blr
; ;
; P9BE-LABEL: caller_14: ; P9BE-LABEL: caller_14:
; P9BE: # %bb.0: # %entry ; P9BE: # %bb.0: # %entry
; P9BE-NEXT: mflr r0 ; P9BE-NEXT: mflr r0
; P9BE-NEXT: std r0, 16(r1)
; P9BE-NEXT: stdu r1, -144(r1) ; P9BE-NEXT: stdu r1, -144(r1)
; P9BE-NEXT: rldicl r5, r4, 48, 16 ; P9BE-NEXT: rldicl r5, r4, 48, 16
; P9BE-NEXT: std r0, 160(r1)
; P9BE-NEXT: sth r4, 204(r1) ; P9BE-NEXT: sth r4, 204(r1)
; P9BE-NEXT: addi r4, r1, 130 ; P9BE-NEXT: addi r4, r1, 130
; P9BE-NEXT: std r3, 192(r1) ; P9BE-NEXT: std r3, 192(r1)
; P9BE-NEXT: stw r5, 200(r1) ; P9BE-NEXT: stw r5, 200(r1)
; P9BE-NEXT: stdx r3, 0, r4 ; P9BE-NEXT: stdx r3, 0, r4
; P9BE-NEXT: mr r3, r4 ; P9BE-NEXT: mr r3, r4
; P9BE-NEXT: lwz r5, 200(r1) ; P9BE-NEXT: lwz r5, 200(r1)
; P9BE-NEXT: stw r5, 138(r1) ; P9BE-NEXT: stw r5, 138(r1)
▲ Show 20 Lines • Show All 77 Lines • ▼ Show 20 Linesentry:
call void @callee(ptr nonnull %_param_data) call void @callee(ptr nonnull %_param_data)
ret i8 0 ret i8 0
} }
define signext i8 @caller_16(ptr nocapture readonly byval([16 x i8]) %data) #0 { define signext i8 @caller_16(ptr nocapture readonly byval([16 x i8]) %data) #0 {
; P8LE-LABEL: caller_16: ; P8LE-LABEL: caller_16:
; P8LE: # %bb.0: # %entry ; P8LE: # %bb.0: # %entry
; P8LE-NEXT: mflr r0 ; P8LE-NEXT: mflr r0
; P8LE-NEXT: std r0, 16(r1)
; P8LE-NEXT: stdu r1, -80(r1) ; P8LE-NEXT: stdu r1, -80(r1)
; P8LE-NEXT: addi r5, r1, 64 ; P8LE-NEXT: addi r5, r1, 64
; P8LE-NEXT: std r0, 96(r1)
; P8LE-NEXT: std r3, 48(r1) ; P8LE-NEXT: std r3, 48(r1)
; P8LE-NEXT: std r4, 56(r1) ; P8LE-NEXT: std r4, 56(r1)
; P8LE-NEXT: std r3, 64(r1) ; P8LE-NEXT: std r3, 64(r1)
; P8LE-NEXT: mr r3, r5 ; P8LE-NEXT: mr r3, r5
; P8LE-NEXT: stw r4, 72(r1) ; P8LE-NEXT: stw r4, 72(r1)
; P8LE-NEXT: bl callee ; P8LE-NEXT: bl callee
; P8LE-NEXT: nop ; P8LE-NEXT: nop
; P8LE-NEXT: li r3, 0 ; P8LE-NEXT: li r3, 0
; P8LE-NEXT: addi r1, r1, 80 ; P8LE-NEXT: addi r1, r1, 80
; P8LE-NEXT: ld r0, 16(r1) ; P8LE-NEXT: ld r0, 16(r1)
; P8LE-NEXT: mtlr r0 ; P8LE-NEXT: mtlr r0
; P8LE-NEXT: blr ; P8LE-NEXT: blr
; ;
; P9LE-LABEL: caller_16: ; P9LE-LABEL: caller_16:
; P9LE: # %bb.0: # %entry ; P9LE: # %bb.0: # %entry
; P9LE-NEXT: mflr r0 ; P9LE-NEXT: mflr r0
; P9LE-NEXT: std r0, 16(r1)
; P9LE-NEXT: stdu r1, -80(r1) ; P9LE-NEXT: stdu r1, -80(r1)
; P9LE-NEXT: addi r5, r1, 64 ; P9LE-NEXT: addi r5, r1, 64
; P9LE-NEXT: std r0, 96(r1)
; P9LE-NEXT: std r3, 48(r1) ; P9LE-NEXT: std r3, 48(r1)
; P9LE-NEXT: std r4, 56(r1) ; P9LE-NEXT: std r4, 56(r1)
; P9LE-NEXT: stw r4, 72(r1) ; P9LE-NEXT: stw r4, 72(r1)
; P9LE-NEXT: std r3, 64(r1) ; P9LE-NEXT: std r3, 64(r1)
; P9LE-NEXT: mr r3, r5 ; P9LE-NEXT: mr r3, r5
; P9LE-NEXT: bl callee ; P9LE-NEXT: bl callee
; P9LE-NEXT: nop ; P9LE-NEXT: nop
; P9LE-NEXT: li r3, 0 ; P9LE-NEXT: li r3, 0
Show All 18 Lines
; P10LE-NEXT: addi r1, r1, 80 ; P10LE-NEXT: addi r1, r1, 80
; P10LE-NEXT: ld r0, 16(r1) ; P10LE-NEXT: ld r0, 16(r1)
; P10LE-NEXT: mtlr r0 ; P10LE-NEXT: mtlr r0
; P10LE-NEXT: blr ; P10LE-NEXT: blr
; ;
; P8BE-LABEL: caller_16: ; P8BE-LABEL: caller_16:
; P8BE: # %bb.0: # %entry ; P8BE: # %bb.0: # %entry
; P8BE-NEXT: mflr r0 ; P8BE-NEXT: mflr r0
; P8BE-NEXT: std r0, 16(r1)
; P8BE-NEXT: stdu r1, -144(r1) ; P8BE-NEXT: stdu r1, -144(r1)
; P8BE-NEXT: addi r5, r1, 128 ; P8BE-NEXT: addi r5, r1, 128
; P8BE-NEXT: std r0, 160(r1)
; P8BE-NEXT: rldicl r6, r4, 32, 32 ; P8BE-NEXT: rldicl r6, r4, 32, 32
; P8BE-NEXT: std r3, 192(r1) ; P8BE-NEXT: std r3, 192(r1)
; P8BE-NEXT: std r4, 200(r1) ; P8BE-NEXT: std r4, 200(r1)
; P8BE-NEXT: std r3, 128(r1) ; P8BE-NEXT: std r3, 128(r1)
; P8BE-NEXT: mr r3, r5 ; P8BE-NEXT: mr r3, r5
; P8BE-NEXT: stw r6, 136(r1) ; P8BE-NEXT: stw r6, 136(r1)
; P8BE-NEXT: bl callee ; P8BE-NEXT: bl callee
; P8BE-NEXT: nop ; P8BE-NEXT: nop
; P8BE-NEXT: li r3, 0 ; P8BE-NEXT: li r3, 0
; P8BE-NEXT: addi r1, r1, 144 ; P8BE-NEXT: addi r1, r1, 144
; P8BE-NEXT: ld r0, 16(r1) ; P8BE-NEXT: ld r0, 16(r1)
; P8BE-NEXT: mtlr r0 ; P8BE-NEXT: mtlr r0
; P8BE-NEXT: blr ; P8BE-NEXT: blr
; ;
; P9BE-LABEL: caller_16: ; P9BE-LABEL: caller_16:
; P9BE: # %bb.0: # %entry ; P9BE: # %bb.0: # %entry
; P9BE-NEXT: mflr r0 ; P9BE-NEXT: mflr r0
; P9BE-NEXT: std r0, 16(r1)
; P9BE-NEXT: stdu r1, -144(r1) ; P9BE-NEXT: stdu r1, -144(r1)
; P9BE-NEXT: std r0, 160(r1)
; P9BE-NEXT: std r4, 200(r1) ; P9BE-NEXT: std r4, 200(r1)
; P9BE-NEXT: rldicl r5, r4, 32, 32 ; P9BE-NEXT: rldicl r5, r4, 32, 32
; P9BE-NEXT: addi r4, r1, 128 ; P9BE-NEXT: addi r4, r1, 128
; P9BE-NEXT: std r3, 192(r1) ; P9BE-NEXT: std r3, 192(r1)
; P9BE-NEXT: std r3, 128(r1) ; P9BE-NEXT: std r3, 128(r1)
; P9BE-NEXT: mr r3, r4 ; P9BE-NEXT: mr r3, r4
; P9BE-NEXT: stw r5, 136(r1) ; P9BE-NEXT: stw r5, 136(r1)
; P9BE-NEXT: bl callee ; P9BE-NEXT: bl callee
▲ Show 20 Lines • Show All 74 Lines • ▼ Show 20 Linesentry:
call void @callee(ptr nonnull %_param_data) call void @callee(ptr nonnull %_param_data)
ret i8 0 ret i8 0
} }
define signext i8 @caller_18(ptr nocapture readonly byval([18 x i8]) %data) #0 { define signext i8 @caller_18(ptr nocapture readonly byval([18 x i8]) %data) #0 {
; P8LE-LABEL: caller_18: ; P8LE-LABEL: caller_18:
; P8LE: # %bb.0: # %entry ; P8LE: # %bb.0: # %entry
; P8LE-NEXT: mflr r0 ; P8LE-NEXT: mflr r0
; P8LE-NEXT: std r0, 16(r1)
; P8LE-NEXT: stdu r1, -96(r1) ; P8LE-NEXT: stdu r1, -96(r1)
; P8LE-NEXT: addi r6, r1, 78 ; P8LE-NEXT: addi r6, r1, 78
; P8LE-NEXT: std r0, 112(r1)
; P8LE-NEXT: std r3, 48(r1) ; P8LE-NEXT: std r3, 48(r1)
; P8LE-NEXT: sth r5, 64(r1)
; P8LE-NEXT: std r4, 56(r1) ; P8LE-NEXT: std r4, 56(r1)
; P8LE-NEXT: stdx r3, 0, r6 ; P8LE-NEXT: stdx r3, 0, r6
; P8LE-NEXT: mr r3, r6 ; P8LE-NEXT: mr r3, r6
; P8LE-NEXT: sth r5, 64(r1)
; P8LE-NEXT: stw r4, 86(r1) ; P8LE-NEXT: stw r4, 86(r1)
; P8LE-NEXT: bl callee ; P8LE-NEXT: bl callee
; P8LE-NEXT: nop ; P8LE-NEXT: nop
; P8LE-NEXT: li r3, 0 ; P8LE-NEXT: li r3, 0
; P8LE-NEXT: addi r1, r1, 96 ; P8LE-NEXT: addi r1, r1, 96
; P8LE-NEXT: ld r0, 16(r1) ; P8LE-NEXT: ld r0, 16(r1)
; P8LE-NEXT: mtlr r0 ; P8LE-NEXT: mtlr r0
; P8LE-NEXT: blr ; P8LE-NEXT: blr
; ;
; P9LE-LABEL: caller_18: ; P9LE-LABEL: caller_18:
; P9LE: # %bb.0: # %entry ; P9LE: # %bb.0: # %entry
; P9LE-NEXT: mflr r0 ; P9LE-NEXT: mflr r0
; P9LE-NEXT: std r0, 16(r1)
; P9LE-NEXT: stdu r1, -96(r1) ; P9LE-NEXT: stdu r1, -96(r1)
; P9LE-NEXT: std r0, 112(r1)
; P9LE-NEXT: sth r5, 64(r1) ; P9LE-NEXT: sth r5, 64(r1)
; P9LE-NEXT: addi r5, r1, 78 ; P9LE-NEXT: addi r5, r1, 78
; P9LE-NEXT: std r3, 48(r1) ; P9LE-NEXT: std r3, 48(r1)
; P9LE-NEXT: std r4, 56(r1) ; P9LE-NEXT: std r4, 56(r1)
; P9LE-NEXT: stw r4, 86(r1) ; P9LE-NEXT: stw r4, 86(r1)
; P9LE-NEXT: stdx r3, 0, r5 ; P9LE-NEXT: stdx r3, 0, r5
; P9LE-NEXT: mr r3, r5 ; P9LE-NEXT: mr r3, r5
; P9LE-NEXT: bl callee ; P9LE-NEXT: bl callee
Show All 21 Lines
; P10LE-NEXT: addi r1, r1, 96 ; P10LE-NEXT: addi r1, r1, 96
; P10LE-NEXT: ld r0, 16(r1) ; P10LE-NEXT: ld r0, 16(r1)
; P10LE-NEXT: mtlr r0 ; P10LE-NEXT: mtlr r0
; P10LE-NEXT: blr ; P10LE-NEXT: blr
; ;
; P8BE-LABEL: caller_18: ; P8BE-LABEL: caller_18:
; P8BE: # %bb.0: # %entry ; P8BE: # %bb.0: # %entry
; P8BE-NEXT: mflr r0 ; P8BE-NEXT: mflr r0
; P8BE-NEXT: std r0, 16(r1)
; P8BE-NEXT: stdu r1, -144(r1) ; P8BE-NEXT: stdu r1, -144(r1)
; P8BE-NEXT: addi r6, r1, 126 ; P8BE-NEXT: addi r6, r1, 126
; P8BE-NEXT: std r0, 160(r1)
; P8BE-NEXT: sth r5, 208(r1) ; P8BE-NEXT: sth r5, 208(r1)
; P8BE-NEXT: rldicl r5, r4, 32, 32 ; P8BE-NEXT: rldicl r5, r4, 32, 32
; P8BE-NEXT: std r3, 192(r1) ; P8BE-NEXT: std r3, 192(r1)
; P8BE-NEXT: std r4, 200(r1) ; P8BE-NEXT: std r4, 200(r1)
; P8BE-NEXT: stdx r3, 0, r6 ; P8BE-NEXT: stdx r3, 0, r6
; P8BE-NEXT: mr r3, r6 ; P8BE-NEXT: mr r3, r6
; P8BE-NEXT: stw r5, 134(r1) ; P8BE-NEXT: stw r5, 134(r1)
; P8BE-NEXT: bl callee ; P8BE-NEXT: bl callee
; P8BE-NEXT: nop ; P8BE-NEXT: nop
; P8BE-NEXT: li r3, 0 ; P8BE-NEXT: li r3, 0
; P8BE-NEXT: addi r1, r1, 144 ; P8BE-NEXT: addi r1, r1, 144
; P8BE-NEXT: ld r0, 16(r1) ; P8BE-NEXT: ld r0, 16(r1)
; P8BE-NEXT: mtlr r0 ; P8BE-NEXT: mtlr r0
; P8BE-NEXT: blr ; P8BE-NEXT: blr
; ;
; P9BE-LABEL: caller_18: ; P9BE-LABEL: caller_18:
; P9BE: # %bb.0: # %entry ; P9BE: # %bb.0: # %entry
; P9BE-NEXT: mflr r0 ; P9BE-NEXT: mflr r0
; P9BE-NEXT: std r0, 16(r1)
; P9BE-NEXT: stdu r1, -144(r1) ; P9BE-NEXT: stdu r1, -144(r1)
; P9BE-NEXT: std r0, 160(r1)
; P9BE-NEXT: std r4, 200(r1) ; P9BE-NEXT: std r4, 200(r1)
; P9BE-NEXT: sth r5, 208(r1) ; P9BE-NEXT: sth r5, 208(r1)
; P9BE-NEXT: rldicl r5, r4, 32, 32 ; P9BE-NEXT: rldicl r5, r4, 32, 32
; P9BE-NEXT: addi r4, r1, 126 ; P9BE-NEXT: addi r4, r1, 126
; P9BE-NEXT: std r3, 192(r1) ; P9BE-NEXT: std r3, 192(r1)
; P9BE-NEXT: stdx r3, 0, r4 ; P9BE-NEXT: stdx r3, 0, r4
; P9BE-NEXT: mr r3, r4 ; P9BE-NEXT: mr r3, r4
; P9BE-NEXT: stw r5, 134(r1) ; P9BE-NEXT: stw r5, 134(r1)
▲ Show 20 Lines • Show All 87 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/ppc64-byval-multi-store.ll

Show All 10 Lines
; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names < %s | FileCheck %s --check-prefix=P9BE ; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names < %s | FileCheck %s --check-prefix=P9BE
; RUN: llc -verify-machineinstrs --mtriple powerpc64-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs --mtriple powerpc64-unknown-linux-gnu \
; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names < %s | FileCheck %s --check-prefix=P10BE ; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names < %s | FileCheck %s --check-prefix=P10BE
define signext i8 @caller_1(ptr nocapture readonly byval([1 x i8]) %data) #0 { define signext i8 @caller_1(ptr nocapture readonly byval([1 x i8]) %data) #0 {
; P8LE-LABEL: caller_1: ; P8LE-LABEL: caller_1:
; P8LE: # %bb.0: # %entry ; P8LE: # %bb.0: # %entry
; P8LE-NEXT: mflr r0 ; P8LE-NEXT: mflr r0
; P8LE-NEXT: std r0, 16(r1)
; P8LE-NEXT: stdu r1, -64(r1) ; P8LE-NEXT: stdu r1, -64(r1)
; P8LE-NEXT: std r0, 80(r1)
; P8LE-NEXT: stb r3, 48(r1) ; P8LE-NEXT: stb r3, 48(r1)
; P8LE-NEXT: lbz r3, 48(r1) ; P8LE-NEXT: lbz r3, 48(r1)
; P8LE-NEXT: stb r3, 63(r1) ; P8LE-NEXT: stb r3, 63(r1)
; P8LE-NEXT: addi r3, r1, 63 ; P8LE-NEXT: addi r3, r1, 63
; P8LE-NEXT: bl callee ; P8LE-NEXT: bl callee
; P8LE-NEXT: nop ; P8LE-NEXT: nop
; P8LE-NEXT: li r3, 0 ; P8LE-NEXT: li r3, 0
; P8LE-NEXT: addi r1, r1, 64 ; P8LE-NEXT: addi r1, r1, 64
; P8LE-NEXT: ld r0, 16(r1) ; P8LE-NEXT: ld r0, 16(r1)
; P8LE-NEXT: mtlr r0 ; P8LE-NEXT: mtlr r0
; P8LE-NEXT: blr ; P8LE-NEXT: blr
; ;
; P9LE-LABEL: caller_1: ; P9LE-LABEL: caller_1:
; P9LE: # %bb.0: # %entry ; P9LE: # %bb.0: # %entry
; P9LE-NEXT: mflr r0 ; P9LE-NEXT: mflr r0
; P9LE-NEXT: std r0, 16(r1)
; P9LE-NEXT: stdu r1, -64(r1) ; P9LE-NEXT: stdu r1, -64(r1)
; P9LE-NEXT: std r0, 80(r1)
; P9LE-NEXT: stb r3, 48(r1) ; P9LE-NEXT: stb r3, 48(r1)
; P9LE-NEXT: lbz r3, 48(r1) ; P9LE-NEXT: lbz r3, 48(r1)
; P9LE-NEXT: stb r3, 63(r1) ; P9LE-NEXT: stb r3, 63(r1)
; P9LE-NEXT: addi r3, r1, 63 ; P9LE-NEXT: addi r3, r1, 63
; P9LE-NEXT: bl callee ; P9LE-NEXT: bl callee
; P9LE-NEXT: nop ; P9LE-NEXT: nop
; P9LE-NEXT: li r3, 0 ; P9LE-NEXT: li r3, 0
; P9LE-NEXT: addi r1, r1, 64 ; P9LE-NEXT: addi r1, r1, 64
Show All 15 Lines
; P10LE-NEXT: addi r1, r1, 64 ; P10LE-NEXT: addi r1, r1, 64
; P10LE-NEXT: ld r0, 16(r1) ; P10LE-NEXT: ld r0, 16(r1)
; P10LE-NEXT: mtlr r0 ; P10LE-NEXT: mtlr r0
; P10LE-NEXT: blr ; P10LE-NEXT: blr
; ;
; P8BE-LABEL: caller_1: ; P8BE-LABEL: caller_1:
; P8BE: # %bb.0: # %entry ; P8BE: # %bb.0: # %entry
; P8BE-NEXT: mflr r0 ; P8BE-NEXT: mflr r0
; P8BE-NEXT: std r0, 16(r1)
; P8BE-NEXT: stdu r1, -128(r1) ; P8BE-NEXT: stdu r1, -128(r1)
; P8BE-NEXT: std r0, 144(r1)
; P8BE-NEXT: stb r3, 183(r1) ; P8BE-NEXT: stb r3, 183(r1)
; P8BE-NEXT: lbz r3, 183(r1) ; P8BE-NEXT: lbz r3, 183(r1)
; P8BE-NEXT: stb r3, 127(r1) ; P8BE-NEXT: stb r3, 127(r1)
; P8BE-NEXT: addi r3, r1, 127 ; P8BE-NEXT: addi r3, r1, 127
; P8BE-NEXT: bl callee ; P8BE-NEXT: bl callee
; P8BE-NEXT: nop ; P8BE-NEXT: nop
; P8BE-NEXT: li r3, 0 ; P8BE-NEXT: li r3, 0
; P8BE-NEXT: addi r1, r1, 128 ; P8BE-NEXT: addi r1, r1, 128
; P8BE-NEXT: ld r0, 16(r1) ; P8BE-NEXT: ld r0, 16(r1)
; P8BE-NEXT: mtlr r0 ; P8BE-NEXT: mtlr r0
; P8BE-NEXT: blr ; P8BE-NEXT: blr
; ;
; P9BE-LABEL: caller_1: ; P9BE-LABEL: caller_1:
; P9BE: # %bb.0: # %entry ; P9BE: # %bb.0: # %entry
; P9BE-NEXT: mflr r0 ; P9BE-NEXT: mflr r0
; P9BE-NEXT: std r0, 16(r1)
; P9BE-NEXT: stdu r1, -128(r1) ; P9BE-NEXT: stdu r1, -128(r1)
; P9BE-NEXT: std r0, 144(r1)
; P9BE-NEXT: stb r3, 183(r1) ; P9BE-NEXT: stb r3, 183(r1)
; P9BE-NEXT: lbz r3, 183(r1) ; P9BE-NEXT: lbz r3, 183(r1)
; P9BE-NEXT: stb r3, 127(r1) ; P9BE-NEXT: stb r3, 127(r1)
; P9BE-NEXT: addi r3, r1, 127 ; P9BE-NEXT: addi r3, r1, 127
; P9BE-NEXT: bl callee ; P9BE-NEXT: bl callee
; P9BE-NEXT: nop ; P9BE-NEXT: nop
; P9BE-NEXT: li r3, 0 ; P9BE-NEXT: li r3, 0
; P9BE-NEXT: addi r1, r1, 128 ; P9BE-NEXT: addi r1, r1, 128
Show All 24 Linesentry:
call void @callee(ptr nonnull %_param_data) call void @callee(ptr nonnull %_param_data)
ret i8 0 ret i8 0
} }
define signext i8 @caller_2(ptr nocapture readonly byval([2 x i8]) %data) #0 { define signext i8 @caller_2(ptr nocapture readonly byval([2 x i8]) %data) #0 {
; P8LE-LABEL: caller_2: ; P8LE-LABEL: caller_2:
; P8LE: # %bb.0: # %entry ; P8LE: # %bb.0: # %entry
; P8LE-NEXT: mflr r0 ; P8LE-NEXT: mflr r0
; P8LE-NEXT: std r0, 16(r1)
; P8LE-NEXT: stdu r1, -64(r1) ; P8LE-NEXT: stdu r1, -64(r1)
; P8LE-NEXT: std r0, 80(r1)
; P8LE-NEXT: sth r3, 48(r1) ; P8LE-NEXT: sth r3, 48(r1)
; P8LE-NEXT: lhz r3, 48(r1) ; P8LE-NEXT: lhz r3, 48(r1)
; P8LE-NEXT: sth r3, 62(r1) ; P8LE-NEXT: sth r3, 62(r1)
; P8LE-NEXT: addi r3, r1, 62 ; P8LE-NEXT: addi r3, r1, 62
; P8LE-NEXT: bl callee ; P8LE-NEXT: bl callee
; P8LE-NEXT: nop ; P8LE-NEXT: nop
; P8LE-NEXT: li r3, 0 ; P8LE-NEXT: li r3, 0
; P8LE-NEXT: addi r1, r1, 64 ; P8LE-NEXT: addi r1, r1, 64
; P8LE-NEXT: ld r0, 16(r1) ; P8LE-NEXT: ld r0, 16(r1)
; P8LE-NEXT: mtlr r0 ; P8LE-NEXT: mtlr r0
; P8LE-NEXT: blr ; P8LE-NEXT: blr
; ;
; P9LE-LABEL: caller_2: ; P9LE-LABEL: caller_2:
; P9LE: # %bb.0: # %entry ; P9LE: # %bb.0: # %entry
; P9LE-NEXT: mflr r0 ; P9LE-NEXT: mflr r0
; P9LE-NEXT: std r0, 16(r1)
; P9LE-NEXT: stdu r1, -64(r1) ; P9LE-NEXT: stdu r1, -64(r1)
; P9LE-NEXT: std r0, 80(r1)
; P9LE-NEXT: sth r3, 48(r1) ; P9LE-NEXT: sth r3, 48(r1)
; P9LE-NEXT: lhz r3, 48(r1) ; P9LE-NEXT: lhz r3, 48(r1)
; P9LE-NEXT: sth r3, 62(r1) ; P9LE-NEXT: sth r3, 62(r1)
; P9LE-NEXT: addi r3, r1, 62 ; P9LE-NEXT: addi r3, r1, 62
; P9LE-NEXT: bl callee ; P9LE-NEXT: bl callee
; P9LE-NEXT: nop ; P9LE-NEXT: nop
; P9LE-NEXT: li r3, 0 ; P9LE-NEXT: li r3, 0
; P9LE-NEXT: addi r1, r1, 64 ; P9LE-NEXT: addi r1, r1, 64
Show All 15 Lines
; P10LE-NEXT: addi r1, r1, 64 ; P10LE-NEXT: addi r1, r1, 64
; P10LE-NEXT: ld r0, 16(r1) ; P10LE-NEXT: ld r0, 16(r1)
; P10LE-NEXT: mtlr r0 ; P10LE-NEXT: mtlr r0
; P10LE-NEXT: blr ; P10LE-NEXT: blr
; ;
; P8BE-LABEL: caller_2: ; P8BE-LABEL: caller_2:
; P8BE: # %bb.0: # %entry ; P8BE: # %bb.0: # %entry
; P8BE-NEXT: mflr r0 ; P8BE-NEXT: mflr r0
; P8BE-NEXT: std r0, 16(r1)
; P8BE-NEXT: stdu r1, -128(r1) ; P8BE-NEXT: stdu r1, -128(r1)
; P8BE-NEXT: std r0, 144(r1)
; P8BE-NEXT: sth r3, 182(r1) ; P8BE-NEXT: sth r3, 182(r1)
; P8BE-NEXT: lhz r3, 182(r1) ; P8BE-NEXT: lhz r3, 182(r1)
; P8BE-NEXT: sth r3, 126(r1) ; P8BE-NEXT: sth r3, 126(r1)
; P8BE-NEXT: addi r3, r1, 126 ; P8BE-NEXT: addi r3, r1, 126
; P8BE-NEXT: bl callee ; P8BE-NEXT: bl callee
; P8BE-NEXT: nop ; P8BE-NEXT: nop
; P8BE-NEXT: li r3, 0 ; P8BE-NEXT: li r3, 0
; P8BE-NEXT: addi r1, r1, 128 ; P8BE-NEXT: addi r1, r1, 128
; P8BE-NEXT: ld r0, 16(r1) ; P8BE-NEXT: ld r0, 16(r1)
; P8BE-NEXT: mtlr r0 ; P8BE-NEXT: mtlr r0
; P8BE-NEXT: blr ; P8BE-NEXT: blr
; ;
; P9BE-LABEL: caller_2: ; P9BE-LABEL: caller_2:
; P9BE: # %bb.0: # %entry ; P9BE: # %bb.0: # %entry
; P9BE-NEXT: mflr r0 ; P9BE-NEXT: mflr r0
; P9BE-NEXT: std r0, 16(r1)
; P9BE-NEXT: stdu r1, -128(r1) ; P9BE-NEXT: stdu r1, -128(r1)
; P9BE-NEXT: std r0, 144(r1)
; P9BE-NEXT: sth r3, 182(r1) ; P9BE-NEXT: sth r3, 182(r1)
; P9BE-NEXT: lhz r3, 182(r1) ; P9BE-NEXT: lhz r3, 182(r1)
; P9BE-NEXT: sth r3, 126(r1) ; P9BE-NEXT: sth r3, 126(r1)
; P9BE-NEXT: addi r3, r1, 126 ; P9BE-NEXT: addi r3, r1, 126
; P9BE-NEXT: bl callee ; P9BE-NEXT: bl callee
; P9BE-NEXT: nop ; P9BE-NEXT: nop
; P9BE-NEXT: li r3, 0 ; P9BE-NEXT: li r3, 0
; P9BE-NEXT: addi r1, r1, 128 ; P9BE-NEXT: addi r1, r1, 128
Show All 28 Linesentry:
call void @callee(ptr nonnull %_param_data) call void @callee(ptr nonnull %_param_data)
ret i8 0 ret i8 0
} }
define signext i8 @caller_3(ptr nocapture readonly byval([3 x i8]) %data) #0 { define signext i8 @caller_3(ptr nocapture readonly byval([3 x i8]) %data) #0 {
; P8LE-LABEL: caller_3: ; P8LE-LABEL: caller_3:
; P8LE: # %bb.0: # %entry ; P8LE: # %bb.0: # %entry
; P8LE-NEXT: mflr r0 ; P8LE-NEXT: mflr r0
; P8LE-NEXT: std r0, 16(r1)
; P8LE-NEXT: stdu r1, -64(r1) ; P8LE-NEXT: stdu r1, -64(r1)
; P8LE-NEXT: std r0, 80(r1)
; P8LE-NEXT: rldicl r4, r3, 48, 16 ; P8LE-NEXT: rldicl r4, r3, 48, 16
; P8LE-NEXT: sth r3, 48(r1) ; P8LE-NEXT: sth r3, 48(r1)
; P8LE-NEXT: stb r4, 50(r1) ; P8LE-NEXT: stb r4, 50(r1)
; P8LE-NEXT: lhz r3, 48(r1) ; P8LE-NEXT: lhz r3, 48(r1)
; P8LE-NEXT: lbz r4, 50(r1) ; P8LE-NEXT: lbz r4, 50(r1)
; P8LE-NEXT: sth r3, 61(r1) ; P8LE-NEXT: sth r3, 61(r1)
; P8LE-NEXT: addi r3, r1, 61 ; P8LE-NEXT: addi r3, r1, 61
; P8LE-NEXT: stb r4, 63(r1) ; P8LE-NEXT: stb r4, 63(r1)
; P8LE-NEXT: bl callee ; P8LE-NEXT: bl callee
; P8LE-NEXT: nop ; P8LE-NEXT: nop
; P8LE-NEXT: li r3, 0 ; P8LE-NEXT: li r3, 0
; P8LE-NEXT: addi r1, r1, 64 ; P8LE-NEXT: addi r1, r1, 64
; P8LE-NEXT: ld r0, 16(r1) ; P8LE-NEXT: ld r0, 16(r1)
; P8LE-NEXT: mtlr r0 ; P8LE-NEXT: mtlr r0
; P8LE-NEXT: blr ; P8LE-NEXT: blr
; ;
; P9LE-LABEL: caller_3: ; P9LE-LABEL: caller_3:
; P9LE: # %bb.0: # %entry ; P9LE: # %bb.0: # %entry
; P9LE-NEXT: mflr r0 ; P9LE-NEXT: mflr r0
; P9LE-NEXT: std r0, 16(r1)
; P9LE-NEXT: stdu r1, -64(r1) ; P9LE-NEXT: stdu r1, -64(r1)
; P9LE-NEXT: std r0, 80(r1)
; P9LE-NEXT: sth r3, 48(r1) ; P9LE-NEXT: sth r3, 48(r1)
; P9LE-NEXT: rldicl r3, r3, 48, 16 ; P9LE-NEXT: rldicl r3, r3, 48, 16
; P9LE-NEXT: stb r3, 50(r1) ; P9LE-NEXT: stb r3, 50(r1)
; P9LE-NEXT: lhz r3, 48(r1) ; P9LE-NEXT: lhz r3, 48(r1)
; P9LE-NEXT: lbz r4, 50(r1) ; P9LE-NEXT: lbz r4, 50(r1)
; P9LE-NEXT: sth r3, 61(r1) ; P9LE-NEXT: sth r3, 61(r1)
; P9LE-NEXT: addi r3, r1, 61 ; P9LE-NEXT: addi r3, r1, 61
; P9LE-NEXT: stb r4, 63(r1) ; P9LE-NEXT: stb r4, 63(r1)
Show All 23 Lines
; P10LE-NEXT: addi r1, r1, 64 ; P10LE-NEXT: addi r1, r1, 64
; P10LE-NEXT: ld r0, 16(r1) ; P10LE-NEXT: ld r0, 16(r1)
; P10LE-NEXT: mtlr r0 ; P10LE-NEXT: mtlr r0
; P10LE-NEXT: blr ; P10LE-NEXT: blr
; ;
; P8BE-LABEL: caller_3: ; P8BE-LABEL: caller_3:
; P8BE: # %bb.0: # %entry ; P8BE: # %bb.0: # %entry
; P8BE-NEXT: mflr r0 ; P8BE-NEXT: mflr r0
; P8BE-NEXT: std r0, 16(r1)
; P8BE-NEXT: stdu r1, -128(r1) ; P8BE-NEXT: stdu r1, -128(r1)
; P8BE-NEXT: rldicl r4, r3, 56, 8 ; P8BE-NEXT: rldicl r4, r3, 56, 8
; P8BE-NEXT: std r0, 144(r1)
; P8BE-NEXT: stb r3, 183(r1) ; P8BE-NEXT: stb r3, 183(r1)
; P8BE-NEXT: sth r4, 181(r1) ; P8BE-NEXT: sth r4, 181(r1)
; P8BE-NEXT: lbz r4, 183(r1) ; P8BE-NEXT: lbz r4, 183(r1)
; P8BE-NEXT: lhz r3, 181(r1) ; P8BE-NEXT: lhz r3, 181(r1)
; P8BE-NEXT: stb r4, 127(r1) ; P8BE-NEXT: stb r4, 127(r1)
; P8BE-NEXT: sth r3, 125(r1) ; P8BE-NEXT: sth r3, 125(r1)
; P8BE-NEXT: addi r3, r1, 125 ; P8BE-NEXT: addi r3, r1, 125
; P8BE-NEXT: bl callee ; P8BE-NEXT: bl callee
; P8BE-NEXT: nop ; P8BE-NEXT: nop
; P8BE-NEXT: li r3, 0 ; P8BE-NEXT: li r3, 0
; P8BE-NEXT: addi r1, r1, 128 ; P8BE-NEXT: addi r1, r1, 128
; P8BE-NEXT: ld r0, 16(r1) ; P8BE-NEXT: ld r0, 16(r1)
; P8BE-NEXT: mtlr r0 ; P8BE-NEXT: mtlr r0
; P8BE-NEXT: blr ; P8BE-NEXT: blr
; ;
; P9BE-LABEL: caller_3: ; P9BE-LABEL: caller_3:
; P9BE: # %bb.0: # %entry ; P9BE: # %bb.0: # %entry
; P9BE-NEXT: mflr r0 ; P9BE-NEXT: mflr r0
; P9BE-NEXT: std r0, 16(r1)
; P9BE-NEXT: stdu r1, -128(r1) ; P9BE-NEXT: stdu r1, -128(r1)
; P9BE-NEXT: rldicl r4, r3, 56, 8 ; P9BE-NEXT: rldicl r4, r3, 56, 8
; P9BE-NEXT: std r0, 144(r1)
; P9BE-NEXT: stb r3, 183(r1) ; P9BE-NEXT: stb r3, 183(r1)
; P9BE-NEXT: sth r4, 181(r1) ; P9BE-NEXT: sth r4, 181(r1)
; P9BE-NEXT: lbz r4, 183(r1) ; P9BE-NEXT: lbz r4, 183(r1)
; P9BE-NEXT: lhz r3, 181(r1) ; P9BE-NEXT: lhz r3, 181(r1)
; P9BE-NEXT: stb r4, 127(r1) ; P9BE-NEXT: stb r4, 127(r1)
; P9BE-NEXT: sth r3, 125(r1) ; P9BE-NEXT: sth r3, 125(r1)
; P9BE-NEXT: addi r3, r1, 125 ; P9BE-NEXT: addi r3, r1, 125
; P9BE-NEXT: bl callee ; P9BE-NEXT: bl callee
Show All 39 Linesentry:
call void @callee(ptr nonnull %_param_data) call void @callee(ptr nonnull %_param_data)
ret i8 0 ret i8 0
} }
define signext i8 @caller_4(ptr nocapture readonly byval([4 x i8]) %data) #0 { define signext i8 @caller_4(ptr nocapture readonly byval([4 x i8]) %data) #0 {
; P8LE-LABEL: caller_4: ; P8LE-LABEL: caller_4:
; P8LE: # %bb.0: # %entry ; P8LE: # %bb.0: # %entry
; P8LE-NEXT: mflr r0 ; P8LE-NEXT: mflr r0
; P8LE-NEXT: std r0, 16(r1)
; P8LE-NEXT: stdu r1, -64(r1) ; P8LE-NEXT: stdu r1, -64(r1)
; P8LE-NEXT: std r0, 80(r1)
; P8LE-NEXT: stw r3, 48(r1) ; P8LE-NEXT: stw r3, 48(r1)
; P8LE-NEXT: lwz r3, 48(r1) ; P8LE-NEXT: lwz r3, 48(r1)
; P8LE-NEXT: stw r3, 60(r1) ; P8LE-NEXT: stw r3, 60(r1)
; P8LE-NEXT: addi r3, r1, 60 ; P8LE-NEXT: addi r3, r1, 60
; P8LE-NEXT: bl callee ; P8LE-NEXT: bl callee
; P8LE-NEXT: nop ; P8LE-NEXT: nop
; P8LE-NEXT: li r3, 0 ; P8LE-NEXT: li r3, 0
; P8LE-NEXT: addi r1, r1, 64 ; P8LE-NEXT: addi r1, r1, 64
; P8LE-NEXT: ld r0, 16(r1) ; P8LE-NEXT: ld r0, 16(r1)
; P8LE-NEXT: mtlr r0 ; P8LE-NEXT: mtlr r0
; P8LE-NEXT: blr ; P8LE-NEXT: blr
; ;
; P9LE-LABEL: caller_4: ; P9LE-LABEL: caller_4:
; P9LE: # %bb.0: # %entry ; P9LE: # %bb.0: # %entry
; P9LE-NEXT: mflr r0 ; P9LE-NEXT: mflr r0
; P9LE-NEXT: std r0, 16(r1)
; P9LE-NEXT: stdu r1, -64(r1) ; P9LE-NEXT: stdu r1, -64(r1)
; P9LE-NEXT: std r0, 80(r1)
; P9LE-NEXT: stw r3, 48(r1) ; P9LE-NEXT: stw r3, 48(r1)
; P9LE-NEXT: lwz r3, 48(r1) ; P9LE-NEXT: lwz r3, 48(r1)
; P9LE-NEXT: stw r3, 60(r1) ; P9LE-NEXT: stw r3, 60(r1)
; P9LE-NEXT: addi r3, r1, 60 ; P9LE-NEXT: addi r3, r1, 60
; P9LE-NEXT: bl callee ; P9LE-NEXT: bl callee
; P9LE-NEXT: nop ; P9LE-NEXT: nop
; P9LE-NEXT: li r3, 0 ; P9LE-NEXT: li r3, 0
; P9LE-NEXT: addi r1, r1, 64 ; P9LE-NEXT: addi r1, r1, 64
Show All 15 Lines
; P10LE-NEXT: addi r1, r1, 64 ; P10LE-NEXT: addi r1, r1, 64
; P10LE-NEXT: ld r0, 16(r1) ; P10LE-NEXT: ld r0, 16(r1)
; P10LE-NEXT: mtlr r0 ; P10LE-NEXT: mtlr r0
; P10LE-NEXT: blr ; P10LE-NEXT: blr
; ;
; P8BE-LABEL: caller_4: ; P8BE-LABEL: caller_4:
; P8BE: # %bb.0: # %entry ; P8BE: # %bb.0: # %entry
; P8BE-NEXT: mflr r0 ; P8BE-NEXT: mflr r0
; P8BE-NEXT: std r0, 16(r1)
; P8BE-NEXT: stdu r1, -128(r1) ; P8BE-NEXT: stdu r1, -128(r1)
; P8BE-NEXT: std r0, 144(r1)
; P8BE-NEXT: stw r3, 180(r1) ; P8BE-NEXT: stw r3, 180(r1)
; P8BE-NEXT: lwz r3, 180(r1) ; P8BE-NEXT: lwz r3, 180(r1)
; P8BE-NEXT: stw r3, 124(r1) ; P8BE-NEXT: stw r3, 124(r1)
; P8BE-NEXT: addi r3, r1, 124 ; P8BE-NEXT: addi r3, r1, 124
; P8BE-NEXT: bl callee ; P8BE-NEXT: bl callee
; P8BE-NEXT: nop ; P8BE-NEXT: nop
; P8BE-NEXT: li r3, 0 ; P8BE-NEXT: li r3, 0
; P8BE-NEXT: addi r1, r1, 128 ; P8BE-NEXT: addi r1, r1, 128
; P8BE-NEXT: ld r0, 16(r1) ; P8BE-NEXT: ld r0, 16(r1)
; P8BE-NEXT: mtlr r0 ; P8BE-NEXT: mtlr r0
; P8BE-NEXT: blr ; P8BE-NEXT: blr
; ;
; P9BE-LABEL: caller_4: ; P9BE-LABEL: caller_4:
; P9BE: # %bb.0: # %entry ; P9BE: # %bb.0: # %entry
; P9BE-NEXT: mflr r0 ; P9BE-NEXT: mflr r0
; P9BE-NEXT: std r0, 16(r1)
; P9BE-NEXT: stdu r1, -128(r1) ; P9BE-NEXT: stdu r1, -128(r1)
; P9BE-NEXT: std r0, 144(r1)
; P9BE-NEXT: stw r3, 180(r1) ; P9BE-NEXT: stw r3, 180(r1)
; P9BE-NEXT: lwz r3, 180(r1) ; P9BE-NEXT: lwz r3, 180(r1)
; P9BE-NEXT: stw r3, 124(r1) ; P9BE-NEXT: stw r3, 124(r1)
; P9BE-NEXT: addi r3, r1, 124 ; P9BE-NEXT: addi r3, r1, 124
; P9BE-NEXT: bl callee ; P9BE-NEXT: bl callee
; P9BE-NEXT: nop ; P9BE-NEXT: nop
; P9BE-NEXT: li r3, 0 ; P9BE-NEXT: li r3, 0
; P9BE-NEXT: addi r1, r1, 128 ; P9BE-NEXT: addi r1, r1, 128
Show All 36 Linesentry:
call void @callee(ptr nonnull %_param_data) call void @callee(ptr nonnull %_param_data)
ret i8 0 ret i8 0
} }
define signext i8 @caller_5(ptr nocapture readonly byval([5 x i8]) %data) #0 { define signext i8 @caller_5(ptr nocapture readonly byval([5 x i8]) %data) #0 {
; P8LE-LABEL: caller_5: ; P8LE-LABEL: caller_5:
; P8LE: # %bb.0: # %entry ; P8LE: # %bb.0: # %entry
; P8LE-NEXT: mflr r0 ; P8LE-NEXT: mflr r0
; P8LE-NEXT: std r0, 16(r1)
; P8LE-NEXT: stdu r1, -64(r1) ; P8LE-NEXT: stdu r1, -64(r1)
; P8LE-NEXT: rldicl r4, r3, 32, 32 ; P8LE-NEXT: rldicl r4, r3, 32, 32
; P8LE-NEXT: std r0, 80(r1)
; P8LE-NEXT: stw r3, 48(r1) ; P8LE-NEXT: stw r3, 48(r1)
; P8LE-NEXT: stw r3, 59(r1)
; P8LE-NEXT: addi r3, r1, 59
; P8LE-NEXT: stb r4, 52(r1) ; P8LE-NEXT: stb r4, 52(r1)
; P8LE-NEXT: lbz r4, 52(r1) ; P8LE-NEXT: lbz r4, 52(r1)
; P8LE-NEXT: stw r3, 59(r1)
; P8LE-NEXT: addi r3, r1, 59
; P8LE-NEXT: stb r4, 63(r1) ; P8LE-NEXT: stb r4, 63(r1)
; P8LE-NEXT: bl callee ; P8LE-NEXT: bl callee
; P8LE-NEXT: nop ; P8LE-NEXT: nop
; P8LE-NEXT: li r3, 0 ; P8LE-NEXT: li r3, 0
; P8LE-NEXT: addi r1, r1, 64 ; P8LE-NEXT: addi r1, r1, 64
; P8LE-NEXT: ld r0, 16(r1) ; P8LE-NEXT: ld r0, 16(r1)
; P8LE-NEXT: mtlr r0 ; P8LE-NEXT: mtlr r0
; P8LE-NEXT: blr ; P8LE-NEXT: blr
; ;
; P9LE-LABEL: caller_5: ; P9LE-LABEL: caller_5:
; P9LE: # %bb.0: # %entry ; P9LE: # %bb.0: # %entry
; P9LE-NEXT: mflr r0 ; P9LE-NEXT: mflr r0
; P9LE-NEXT: std r0, 16(r1)
; P9LE-NEXT: stdu r1, -64(r1) ; P9LE-NEXT: stdu r1, -64(r1)
; P9LE-NEXT: rldicl r4, r3, 32, 32 ; P9LE-NEXT: rldicl r4, r3, 32, 32
; P9LE-NEXT: std r0, 80(r1)
; P9LE-NEXT: stw r3, 48(r1) ; P9LE-NEXT: stw r3, 48(r1)
; P9LE-NEXT: stw r3, 59(r1) ; P9LE-NEXT: stw r3, 59(r1)
; P9LE-NEXT: addi r3, r1, 59 ; P9LE-NEXT: addi r3, r1, 59
; P9LE-NEXT: stb r4, 52(r1) ; P9LE-NEXT: stb r4, 52(r1)
; P9LE-NEXT: lbz r4, 52(r1) ; P9LE-NEXT: lbz r4, 52(r1)
; P9LE-NEXT: stb r4, 63(r1) ; P9LE-NEXT: stb r4, 63(r1)
; P9LE-NEXT: bl callee ; P9LE-NEXT: bl callee
; P9LE-NEXT: nop ; P9LE-NEXT: nop
Show All 20 Lines
; P10LE-NEXT: addi r1, r1, 64 ; P10LE-NEXT: addi r1, r1, 64
; P10LE-NEXT: ld r0, 16(r1) ; P10LE-NEXT: ld r0, 16(r1)
; P10LE-NEXT: mtlr r0 ; P10LE-NEXT: mtlr r0
; P10LE-NEXT: blr ; P10LE-NEXT: blr
; ;
; P8BE-LABEL: caller_5: ; P8BE-LABEL: caller_5:
; P8BE: # %bb.0: # %entry ; P8BE: # %bb.0: # %entry
; P8BE-NEXT: mflr r0 ; P8BE-NEXT: mflr r0
; P8BE-NEXT: std r0, 16(r1)
; P8BE-NEXT: stdu r1, -128(r1) ; P8BE-NEXT: stdu r1, -128(r1)
; P8BE-NEXT: std r0, 144(r1)
; P8BE-NEXT: stb r3, 183(r1) ; P8BE-NEXT: stb r3, 183(r1)
; P8BE-NEXT: rldicl r3, r3, 56, 8 ; P8BE-NEXT: rldicl r3, r3, 56, 8
; P8BE-NEXT: lbz r4, 183(r1) ; P8BE-NEXT: lbz r4, 183(r1)
; P8BE-NEXT: stw r3, 179(r1) ; P8BE-NEXT: stw r3, 179(r1)
; P8BE-NEXT: stw r3, 123(r1) ; P8BE-NEXT: stw r3, 123(r1)
; P8BE-NEXT: addi r3, r1, 123 ; P8BE-NEXT: addi r3, r1, 123
; P8BE-NEXT: stb r4, 127(r1) ; P8BE-NEXT: stb r4, 127(r1)
; P8BE-NEXT: bl callee ; P8BE-NEXT: bl callee
; P8BE-NEXT: nop ; P8BE-NEXT: nop
; P8BE-NEXT: li r3, 0 ; P8BE-NEXT: li r3, 0
; P8BE-NEXT: addi r1, r1, 128 ; P8BE-NEXT: addi r1, r1, 128
; P8BE-NEXT: ld r0, 16(r1) ; P8BE-NEXT: ld r0, 16(r1)
; P8BE-NEXT: mtlr r0 ; P8BE-NEXT: mtlr r0
; P8BE-NEXT: blr ; P8BE-NEXT: blr
; ;
; P9BE-LABEL: caller_5: ; P9BE-LABEL: caller_5:
; P9BE: # %bb.0: # %entry ; P9BE: # %bb.0: # %entry
; P9BE-NEXT: mflr r0 ; P9BE-NEXT: mflr r0
; P9BE-NEXT: std r0, 16(r1)
; P9BE-NEXT: stdu r1, -128(r1) ; P9BE-NEXT: stdu r1, -128(r1)
; P9BE-NEXT: std r0, 144(r1)
; P9BE-NEXT: stb r3, 183(r1) ; P9BE-NEXT: stb r3, 183(r1)
; P9BE-NEXT: rldicl r3, r3, 56, 8
; P9BE-NEXT: lbz r4, 183(r1) ; P9BE-NEXT: lbz r4, 183(r1)
; P9BE-NEXT: rldicl r3, r3, 56, 8
; P9BE-NEXT: stw r3, 179(r1) ; P9BE-NEXT: stw r3, 179(r1)
; P9BE-NEXT: stw r3, 123(r1) ; P9BE-NEXT: stw r3, 123(r1)
; P9BE-NEXT: addi r3, r1, 123 ; P9BE-NEXT: addi r3, r1, 123
; P9BE-NEXT: stb r4, 127(r1) ; P9BE-NEXT: stb r4, 127(r1)
; P9BE-NEXT: bl callee ; P9BE-NEXT: bl callee
; P9BE-NEXT: nop ; P9BE-NEXT: nop
; P9BE-NEXT: li r3, 0 ; P9BE-NEXT: li r3, 0
; P9BE-NEXT: addi r1, r1, 128 ; P9BE-NEXT: addi r1, r1, 128
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Linesentry:
call void @callee(ptr nonnull %_param_data) call void @callee(ptr nonnull %_param_data)
ret i8 0 ret i8 0
} }
define signext i8 @caller_6(ptr nocapture readonly byval([6 x i8]) %data) #0 { define signext i8 @caller_6(ptr nocapture readonly byval([6 x i8]) %data) #0 {
; P8LE-LABEL: caller_6: ; P8LE-LABEL: caller_6:
; P8LE: # %bb.0: # %entry ; P8LE: # %bb.0: # %entry
; P8LE-NEXT: mflr r0 ; P8LE-NEXT: mflr r0
; P8LE-NEXT: std r0, 16(r1)
; P8LE-NEXT: stdu r1, -64(r1) ; P8LE-NEXT: stdu r1, -64(r1)
; P8LE-NEXT: std r0, 80(r1)
; P8LE-NEXT: rldicl r4, r3, 32, 32 ; P8LE-NEXT: rldicl r4, r3, 32, 32
; P8LE-NEXT: stw r3, 48(r1) ; P8LE-NEXT: stw r3, 48(r1)
; P8LE-NEXT: sth r4, 52(r1) ; P8LE-NEXT: sth r4, 52(r1)
; P8LE-NEXT: lwz r3, 48(r1) ; P8LE-NEXT: lwz r3, 48(r1)
; P8LE-NEXT: lhz r4, 52(r1) ; P8LE-NEXT: lhz r4, 52(r1)
; P8LE-NEXT: stw r3, 58(r1) ; P8LE-NEXT: stw r3, 58(r1)
; P8LE-NEXT: addi r3, r1, 58 ; P8LE-NEXT: addi r3, r1, 58
; P8LE-NEXT: sth r4, 62(r1) ; P8LE-NEXT: sth r4, 62(r1)
; P8LE-NEXT: bl callee ; P8LE-NEXT: bl callee
; P8LE-NEXT: nop ; P8LE-NEXT: nop
; P8LE-NEXT: li r3, 0 ; P8LE-NEXT: li r3, 0
; P8LE-NEXT: addi r1, r1, 64 ; P8LE-NEXT: addi r1, r1, 64
; P8LE-NEXT: ld r0, 16(r1) ; P8LE-NEXT: ld r0, 16(r1)
; P8LE-NEXT: mtlr r0 ; P8LE-NEXT: mtlr r0
; P8LE-NEXT: blr ; P8LE-NEXT: blr
; ;
; P9LE-LABEL: caller_6: ; P9LE-LABEL: caller_6:
; P9LE: # %bb.0: # %entry ; P9LE: # %bb.0: # %entry
; P9LE-NEXT: mflr r0 ; P9LE-NEXT: mflr r0
; P9LE-NEXT: std r0, 16(r1)
; P9LE-NEXT: stdu r1, -64(r1) ; P9LE-NEXT: stdu r1, -64(r1)
; P9LE-NEXT: std r0, 80(r1)
; P9LE-NEXT: stw r3, 48(r1) ; P9LE-NEXT: stw r3, 48(r1)
; P9LE-NEXT: rldicl r3, r3, 32, 32 ; P9LE-NEXT: rldicl r3, r3, 32, 32
; P9LE-NEXT: sth r3, 52(r1) ; P9LE-NEXT: sth r3, 52(r1)
; P9LE-NEXT: lwz r3, 48(r1) ; P9LE-NEXT: lwz r3, 48(r1)
; P9LE-NEXT: lhz r4, 52(r1) ; P9LE-NEXT: lhz r4, 52(r1)
; P9LE-NEXT: stw r3, 58(r1) ; P9LE-NEXT: stw r3, 58(r1)
; P9LE-NEXT: addi r3, r1, 58 ; P9LE-NEXT: addi r3, r1, 58
; P9LE-NEXT: sth r4, 62(r1) ; P9LE-NEXT: sth r4, 62(r1)
Show All 23 Lines
; P10LE-NEXT: addi r1, r1, 64 ; P10LE-NEXT: addi r1, r1, 64
; P10LE-NEXT: ld r0, 16(r1) ; P10LE-NEXT: ld r0, 16(r1)
; P10LE-NEXT: mtlr r0 ; P10LE-NEXT: mtlr r0
; P10LE-NEXT: blr ; P10LE-NEXT: blr
; ;
; P8BE-LABEL: caller_6: ; P8BE-LABEL: caller_6:
; P8BE: # %bb.0: # %entry ; P8BE: # %bb.0: # %entry
; P8BE-NEXT: mflr r0 ; P8BE-NEXT: mflr r0
; P8BE-NEXT: std r0, 16(r1)
; P8BE-NEXT: stdu r1, -128(r1) ; P8BE-NEXT: stdu r1, -128(r1)
; P8BE-NEXT: rldicl r4, r3, 48, 16 ; P8BE-NEXT: rldicl r4, r3, 48, 16
; P8BE-NEXT: std r0, 144(r1)
; P8BE-NEXT: sth r3, 182(r1) ; P8BE-NEXT: sth r3, 182(r1)
; P8BE-NEXT: stw r4, 178(r1) ; P8BE-NEXT: stw r4, 178(r1)
; P8BE-NEXT: lhz r4, 182(r1) ; P8BE-NEXT: lhz r4, 182(r1)
; P8BE-NEXT: lwz r3, 178(r1) ; P8BE-NEXT: lwz r3, 178(r1)
; P8BE-NEXT: sth r4, 126(r1) ; P8BE-NEXT: sth r4, 126(r1)
; P8BE-NEXT: stw r3, 122(r1) ; P8BE-NEXT: stw r3, 122(r1)
; P8BE-NEXT: addi r3, r1, 122 ; P8BE-NEXT: addi r3, r1, 122
; P8BE-NEXT: bl callee ; P8BE-NEXT: bl callee
; P8BE-NEXT: nop ; P8BE-NEXT: nop
; P8BE-NEXT: li r3, 0 ; P8BE-NEXT: li r3, 0
; P8BE-NEXT: addi r1, r1, 128 ; P8BE-NEXT: addi r1, r1, 128
; P8BE-NEXT: ld r0, 16(r1) ; P8BE-NEXT: ld r0, 16(r1)
; P8BE-NEXT: mtlr r0 ; P8BE-NEXT: mtlr r0
; P8BE-NEXT: blr ; P8BE-NEXT: blr
; ;
; P9BE-LABEL: caller_6: ; P9BE-LABEL: caller_6:
; P9BE: # %bb.0: # %entry ; P9BE: # %bb.0: # %entry
; P9BE-NEXT: mflr r0 ; P9BE-NEXT: mflr r0
; P9BE-NEXT: std r0, 16(r1)
; P9BE-NEXT: stdu r1, -128(r1) ; P9BE-NEXT: stdu r1, -128(r1)
; P9BE-NEXT: rldicl r4, r3, 48, 16 ; P9BE-NEXT: rldicl r4, r3, 48, 16
; P9BE-NEXT: std r0, 144(r1)
; P9BE-NEXT: sth r3, 182(r1) ; P9BE-NEXT: sth r3, 182(r1)
; P9BE-NEXT: stw r4, 178(r1) ; P9BE-NEXT: stw r4, 178(r1)
; P9BE-NEXT: lhz r4, 182(r1) ; P9BE-NEXT: lhz r4, 182(r1)
; P9BE-NEXT: lwz r3, 178(r1) ; P9BE-NEXT: lwz r3, 178(r1)
; P9BE-NEXT: sth r4, 126(r1) ; P9BE-NEXT: sth r4, 126(r1)
; P9BE-NEXT: stw r3, 122(r1) ; P9BE-NEXT: stw r3, 122(r1)
; P9BE-NEXT: addi r3, r1, 122 ; P9BE-NEXT: addi r3, r1, 122
; P9BE-NEXT: bl callee ; P9BE-NEXT: bl callee
▲ Show 20 Lines • Show All 51 Lines • ▼ Show 20 Linesentry:
call void @callee(ptr nonnull %_param_data) call void @callee(ptr nonnull %_param_data)
ret i8 0 ret i8 0
} }
define signext i8 @caller_7(ptr nocapture readonly byval([7 x i8]) %data) #0 { define signext i8 @caller_7(ptr nocapture readonly byval([7 x i8]) %data) #0 {
; P8LE-LABEL: caller_7: ; P8LE-LABEL: caller_7:
; P8LE: # %bb.0: # %entry ; P8LE: # %bb.0: # %entry
; P8LE-NEXT: mflr r0 ; P8LE-NEXT: mflr r0
; P8LE-NEXT: std r0, 16(r1)
; P8LE-NEXT: stdu r1, -64(r1) ; P8LE-NEXT: stdu r1, -64(r1)
; P8LE-NEXT: rldicl r4, r3, 32, 32 ; P8LE-NEXT: rldicl r4, r3, 32, 32
; P8LE-NEXT: rldicl r5, r3, 16, 48 ; P8LE-NEXT: rldicl r5, r3, 16, 48
; P8LE-NEXT: std r0, 80(r1)
; P8LE-NEXT: stw r3, 48(r1) ; P8LE-NEXT: stw r3, 48(r1)
; P8LE-NEXT: stw r3, 57(r1)
; P8LE-NEXT: addi r3, r1, 57
; P8LE-NEXT: sth r4, 52(r1) ; P8LE-NEXT: sth r4, 52(r1)
; P8LE-NEXT: stb r5, 54(r1) ; P8LE-NEXT: stb r5, 54(r1)
; P8LE-NEXT: lhz r4, 52(r1) ; P8LE-NEXT: lhz r4, 52(r1)
; P8LE-NEXT: lbz r5, 54(r1) ; P8LE-NEXT: lbz r5, 54(r1)
; P8LE-NEXT: stw r3, 57(r1)
; P8LE-NEXT: addi r3, r1, 57
; P8LE-NEXT: sth r4, 61(r1) ; P8LE-NEXT: sth r4, 61(r1)
; P8LE-NEXT: stb r5, 63(r1) ; P8LE-NEXT: stb r5, 63(r1)
; P8LE-NEXT: bl callee ; P8LE-NEXT: bl callee
; P8LE-NEXT: nop ; P8LE-NEXT: nop
; P8LE-NEXT: li r3, 0 ; P8LE-NEXT: li r3, 0
; P8LE-NEXT: addi r1, r1, 64 ; P8LE-NEXT: addi r1, r1, 64
; P8LE-NEXT: ld r0, 16(r1) ; P8LE-NEXT: ld r0, 16(r1)
; P8LE-NEXT: mtlr r0 ; P8LE-NEXT: mtlr r0
; P8LE-NEXT: blr ; P8LE-NEXT: blr
; ;
; P9LE-LABEL: caller_7: ; P9LE-LABEL: caller_7:
; P9LE: # %bb.0: # %entry ; P9LE: # %bb.0: # %entry
; P9LE-NEXT: mflr r0 ; P9LE-NEXT: mflr r0
; P9LE-NEXT: std r0, 16(r1)
; P9LE-NEXT: stdu r1, -64(r1) ; P9LE-NEXT: stdu r1, -64(r1)
; P9LE-NEXT: rldicl r4, r3, 32, 32 ; P9LE-NEXT: rldicl r4, r3, 32, 32
; P9LE-NEXT: std r0, 80(r1)
; P9LE-NEXT: stw r3, 48(r1) ; P9LE-NEXT: stw r3, 48(r1)
; P9LE-NEXT: stw r3, 57(r1) ; P9LE-NEXT: stw r3, 57(r1)
; P9LE-NEXT: sth r4, 52(r1) ; P9LE-NEXT: sth r4, 52(r1)
; P9LE-NEXT: rldicl r4, r3, 16, 48 ; P9LE-NEXT: rldicl r4, r3, 16, 48
; P9LE-NEXT: addi r3, r1, 57 ; P9LE-NEXT: addi r3, r1, 57
; P9LE-NEXT: stb r4, 54(r1) ; P9LE-NEXT: stb r4, 54(r1)
; P9LE-NEXT: lhz r4, 52(r1) ; P9LE-NEXT: lhz r4, 52(r1)
; P9LE-NEXT: lbz r5, 54(r1) ; P9LE-NEXT: lbz r5, 54(r1)
Show All 28 Lines
; P10LE-NEXT: addi r1, r1, 64 ; P10LE-NEXT: addi r1, r1, 64
; P10LE-NEXT: ld r0, 16(r1) ; P10LE-NEXT: ld r0, 16(r1)
; P10LE-NEXT: mtlr r0 ; P10LE-NEXT: mtlr r0
; P10LE-NEXT: blr ; P10LE-NEXT: blr
; ;
; P8BE-LABEL: caller_7: ; P8BE-LABEL: caller_7:
; P8BE: # %bb.0: # %entry ; P8BE: # %bb.0: # %entry
; P8BE-NEXT: mflr r0 ; P8BE-NEXT: mflr r0
; P8BE-NEXT: std r0, 16(r1)
; P8BE-NEXT: stdu r1, -128(r1) ; P8BE-NEXT: stdu r1, -128(r1)
; P8BE-NEXT: rldicl r4, r3, 56, 8 ; P8BE-NEXT: rldicl r4, r3, 56, 8
; P8BE-NEXT: std r0, 144(r1)
; P8BE-NEXT: stb r3, 183(r1) ; P8BE-NEXT: stb r3, 183(r1)
; P8BE-NEXT: rldicl r3, r3, 40, 24 ; P8BE-NEXT: rldicl r3, r3, 40, 24
; P8BE-NEXT: sth r4, 181(r1) ; P8BE-NEXT: sth r4, 181(r1)
; P8BE-NEXT: lbz r5, 183(r1) ; P8BE-NEXT: lbz r5, 183(r1)
; P8BE-NEXT: lhz r4, 181(r1) ; P8BE-NEXT: lhz r4, 181(r1)
; P8BE-NEXT: stw r3, 177(r1) ; P8BE-NEXT: stw r3, 177(r1)
; P8BE-NEXT: stw r3, 121(r1) ; P8BE-NEXT: stw r3, 121(r1)
; P8BE-NEXT: addi r3, r1, 121 ; P8BE-NEXT: addi r3, r1, 121
; P8BE-NEXT: stb r5, 127(r1)
; P8BE-NEXT: sth r4, 125(r1) ; P8BE-NEXT: sth r4, 125(r1)
; P8BE-NEXT: stb r5, 127(r1)
; P8BE-NEXT: bl callee ; P8BE-NEXT: bl callee
; P8BE-NEXT: nop ; P8BE-NEXT: nop
; P8BE-NEXT: li r3, 0 ; P8BE-NEXT: li r3, 0
; P8BE-NEXT: addi r1, r1, 128 ; P8BE-NEXT: addi r1, r1, 128
; P8BE-NEXT: ld r0, 16(r1) ; P8BE-NEXT: ld r0, 16(r1)
; P8BE-NEXT: mtlr r0 ; P8BE-NEXT: mtlr r0
; P8BE-NEXT: blr ; P8BE-NEXT: blr
; ;
; P9BE-LABEL: caller_7: ; P9BE-LABEL: caller_7:
; P9BE: # %bb.0: # %entry ; P9BE: # %bb.0: # %entry
; P9BE-NEXT: mflr r0 ; P9BE-NEXT: mflr r0
; P9BE-NEXT: std r0, 16(r1)
; P9BE-NEXT: stdu r1, -128(r1) ; P9BE-NEXT: stdu r1, -128(r1)
; P9BE-NEXT: rldicl r4, r3, 56, 8 ; P9BE-NEXT: rldicl r4, r3, 56, 8
; P9BE-NEXT: std r0, 144(r1)
; P9BE-NEXT: stb r3, 183(r1) ; P9BE-NEXT: stb r3, 183(r1)
; P9BE-NEXT: lbz r5, 183(r1) ; P9BE-NEXT: lbz r5, 183(r1)
; P9BE-NEXT: rldicl r3, r3, 40, 24 ; P9BE-NEXT: rldicl r3, r3, 40, 24
; P9BE-NEXT: sth r4, 181(r1) ; P9BE-NEXT: sth r4, 181(r1)
; P9BE-NEXT: stw r3, 177(r1) ; P9BE-NEXT: stw r3, 177(r1)
; P9BE-NEXT: lhz r4, 181(r1)
; P9BE-NEXT: stw r3, 121(r1) ; P9BE-NEXT: stw r3, 121(r1)
; P9BE-NEXT: addi r3, r1, 121 ; P9BE-NEXT: addi r3, r1, 121
; P9BE-NEXT: lhz r4, 181(r1)
; P9BE-NEXT: stb r5, 127(r1) ; P9BE-NEXT: stb r5, 127(r1)
; P9BE-NEXT: sth r4, 125(r1) ; P9BE-NEXT: sth r4, 125(r1)
; P9BE-NEXT: bl callee ; P9BE-NEXT: bl callee
; P9BE-NEXT: nop ; P9BE-NEXT: nop
; P9BE-NEXT: li r3, 0 ; P9BE-NEXT: li r3, 0
; P9BE-NEXT: addi r1, r1, 128 ; P9BE-NEXT: addi r1, r1, 128
; P9BE-NEXT: ld r0, 16(r1) ; P9BE-NEXT: ld r0, 16(r1)
; P9BE-NEXT: mtlr r0 ; P9BE-NEXT: mtlr r0
▲ Show 20 Lines • Show All 60 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/ppc64-inlineasm-clobber.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=powerpc64le-unknown-linux-unknown -verify-machineinstrs %s \ ; RUN: llc -mtriple=powerpc64le-unknown-linux-unknown -verify-machineinstrs %s \
; RUN: -ppc-asm-full-reg-names -o - | FileCheck %s --check-prefix=PPC64LE ; RUN: -ppc-asm-full-reg-names -o - | FileCheck %s --check-prefix=PPC64LE
; RUN: llc -mtriple=powerpc64-unknown-linux-unknown -verify-machineinstrs %s \ ; RUN: llc -mtriple=powerpc64-unknown-linux-unknown -verify-machineinstrs %s \
; RUN: -ppc-asm-full-reg-names -o - | FileCheck %s --check-prefix=PPC64BE ; RUN: -ppc-asm-full-reg-names -o - | FileCheck %s --check-prefix=PPC64BE
define dso_local void @ClobberLR() local_unnamed_addr #0 { define dso_local void @ClobberLR() local_unnamed_addr #0 {
; PPC64LE-LABEL: ClobberLR: ; PPC64LE-LABEL: ClobberLR:
; PPC64LE: # %bb.0: # %entry ; PPC64LE: # %bb.0: # %entry
; PPC64LE-NEXT: mflr r0 ; PPC64LE-NEXT: mflr r0
; PPC64LE-NEXT: std r0, 16(r1)
; PPC64LE-NEXT: stdu r1, -32(r1) ; PPC64LE-NEXT: stdu r1, -32(r1)
; PPC64LE-NEXT: std r0, 48(r1)
; PPC64LE-NEXT: #APP ; PPC64LE-NEXT: #APP
; PPC64LE-NEXT: #NO_APP ; PPC64LE-NEXT: #NO_APP
; PPC64LE-NEXT: addi r1, r1, 32 ; PPC64LE-NEXT: addi r1, r1, 32
; PPC64LE-NEXT: ld r0, 16(r1) ; PPC64LE-NEXT: ld r0, 16(r1)
; PPC64LE-NEXT: mtlr r0 ; PPC64LE-NEXT: mtlr r0
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
; ;
; PPC64BE-LABEL: ClobberLR: ; PPC64BE-LABEL: ClobberLR:
; PPC64BE: # %bb.0: # %entry ; PPC64BE: # %bb.0: # %entry
; PPC64BE-NEXT: mflr r0 ; PPC64BE-NEXT: mflr r0
; PPC64BE-NEXT: std r0, 16(r1)
; PPC64BE-NEXT: stdu r1, -48(r1) ; PPC64BE-NEXT: stdu r1, -48(r1)
; PPC64BE-NEXT: std r0, 64(r1)
; PPC64BE-NEXT: #APP ; PPC64BE-NEXT: #APP
; PPC64BE-NEXT: #NO_APP ; PPC64BE-NEXT: #NO_APP
; PPC64BE-NEXT: addi r1, r1, 48 ; PPC64BE-NEXT: addi r1, r1, 48
; PPC64BE-NEXT: ld r0, 16(r1) ; PPC64BE-NEXT: ld r0, 16(r1)
; PPC64BE-NEXT: mtlr r0 ; PPC64BE-NEXT: mtlr r0
; PPC64BE-NEXT: blr ; PPC64BE-NEXT: blr
entry: entry:
tail call void asm sideeffect "", "~{lr}"() tail call void asm sideeffect "", "~{lr}"()
Show All 38 Linesentry:
ret void ret void
} }
;; Test for INLINEASM_BR ;; Test for INLINEASM_BR
define dso_local signext i32 @ClobberLR_BR(i32 signext %in) #0 { define dso_local signext i32 @ClobberLR_BR(i32 signext %in) #0 {
; PPC64LE-LABEL: ClobberLR_BR: ; PPC64LE-LABEL: ClobberLR_BR:
; PPC64LE: # %bb.0: # %entry ; PPC64LE: # %bb.0: # %entry
; PPC64LE-NEXT: mflr r0 ; PPC64LE-NEXT: mflr r0
; PPC64LE-NEXT: std r0, 16(r1)
; PPC64LE-NEXT: stdu r1, -32(r1) ; PPC64LE-NEXT: stdu r1, -32(r1)
; PPC64LE-NEXT: std r0, 48(r1)
; PPC64LE-NEXT: #APP ; PPC64LE-NEXT: #APP
; PPC64LE-NEXT: nop ; PPC64LE-NEXT: nop
; PPC64LE-NEXT: #NO_APP ; PPC64LE-NEXT: #NO_APP
; PPC64LE-NEXT: .LBB3_1: # %return ; PPC64LE-NEXT: .LBB3_1: # %return
; PPC64LE-NEXT: addi r1, r1, 32 ; PPC64LE-NEXT: addi r1, r1, 32
; PPC64LE-NEXT: ld r0, 16(r1) ; PPC64LE-NEXT: ld r0, 16(r1)
; PPC64LE-NEXT: mtlr r0 ; PPC64LE-NEXT: mtlr r0
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB3_2: # Block address taken ; PPC64LE-NEXT: .LBB3_2: # Block address taken
; PPC64LE-NEXT: # %return_early ; PPC64LE-NEXT: # %return_early
; PPC64LE-NEXT: # Label of block must be emitted ; PPC64LE-NEXT: # Label of block must be emitted
; PPC64LE-NEXT: li r3, 0 ; PPC64LE-NEXT: li r3, 0
; PPC64LE-NEXT: b .LBB3_1 ; PPC64LE-NEXT: b .LBB3_1
; ;
; PPC64BE-LABEL: ClobberLR_BR: ; PPC64BE-LABEL: ClobberLR_BR:
; PPC64BE: # %bb.0: # %entry ; PPC64BE: # %bb.0: # %entry
; PPC64BE-NEXT: mflr r0 ; PPC64BE-NEXT: mflr r0
; PPC64BE-NEXT: std r0, 16(r1)
; PPC64BE-NEXT: stdu r1, -48(r1) ; PPC64BE-NEXT: stdu r1, -48(r1)
; PPC64BE-NEXT: std r0, 64(r1)
; PPC64BE-NEXT: #APP ; PPC64BE-NEXT: #APP
; PPC64BE-NEXT: nop ; PPC64BE-NEXT: nop
; PPC64BE-NEXT: #NO_APP ; PPC64BE-NEXT: #NO_APP
; PPC64BE-NEXT: .LBB3_1: # %return ; PPC64BE-NEXT: .LBB3_1: # %return
; PPC64BE-NEXT: addi r1, r1, 48 ; PPC64BE-NEXT: addi r1, r1, 48
; PPC64BE-NEXT: ld r0, 16(r1) ; PPC64BE-NEXT: ld r0, 16(r1)
; PPC64BE-NEXT: mtlr r0 ; PPC64BE-NEXT: mtlr r0
; PPC64BE-NEXT: blr ; PPC64BE-NEXT: blr
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Lines
} }
define dso_local void @DefLR() local_unnamed_addr #0 { define dso_local void @DefLR() local_unnamed_addr #0 {
; PPC64LE-LABEL: DefLR: ; PPC64LE-LABEL: DefLR:
; PPC64LE: # %bb.0: # %entry ; PPC64LE: # %bb.0: # %entry
; PPC64LE-NEXT: mflr r0 ; PPC64LE-NEXT: mflr r0
; PPC64LE-NEXT: std r0, 16(r1)
; PPC64LE-NEXT: stdu r1, -32(r1) ; PPC64LE-NEXT: stdu r1, -32(r1)
; PPC64LE-NEXT: std r0, 48(r1)
; PPC64LE-NEXT: #APP ; PPC64LE-NEXT: #APP
; PPC64LE-NEXT: #NO_APP ; PPC64LE-NEXT: #NO_APP
; PPC64LE-NEXT: addi r1, r1, 32 ; PPC64LE-NEXT: addi r1, r1, 32
; PPC64LE-NEXT: ld r0, 16(r1) ; PPC64LE-NEXT: ld r0, 16(r1)
; PPC64LE-NEXT: mtlr r0 ; PPC64LE-NEXT: mtlr r0
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
; ;
; PPC64BE-LABEL: DefLR: ; PPC64BE-LABEL: DefLR:
; PPC64BE: # %bb.0: # %entry ; PPC64BE: # %bb.0: # %entry
; PPC64BE-NEXT: mflr r0 ; PPC64BE-NEXT: mflr r0
; PPC64BE-NEXT: std r0, 16(r1)
; PPC64BE-NEXT: stdu r1, -48(r1) ; PPC64BE-NEXT: stdu r1, -48(r1)
; PPC64BE-NEXT: std r0, 64(r1)
; PPC64BE-NEXT: #APP ; PPC64BE-NEXT: #APP
; PPC64BE-NEXT: #NO_APP ; PPC64BE-NEXT: #NO_APP
; PPC64BE-NEXT: addi r1, r1, 48 ; PPC64BE-NEXT: addi r1, r1, 48
; PPC64BE-NEXT: ld r0, 16(r1) ; PPC64BE-NEXT: ld r0, 16(r1)
; PPC64BE-NEXT: mtlr r0 ; PPC64BE-NEXT: mtlr r0
; PPC64BE-NEXT: blr ; PPC64BE-NEXT: blr
entry: entry:
tail call i64 asm sideeffect "", "={lr}"() tail call i64 asm sideeffect "", "={lr}"()
ret void ret void
} }
define dso_local void @EarlyClobberLR() local_unnamed_addr #0 { define dso_local void @EarlyClobberLR() local_unnamed_addr #0 {
; PPC64LE-LABEL: EarlyClobberLR: ; PPC64LE-LABEL: EarlyClobberLR:
; PPC64LE: # %bb.0: # %entry ; PPC64LE: # %bb.0: # %entry
; PPC64LE-NEXT: mflr r0 ; PPC64LE-NEXT: mflr r0
; PPC64LE-NEXT: std r0, 16(r1)
; PPC64LE-NEXT: stdu r1, -32(r1) ; PPC64LE-NEXT: stdu r1, -32(r1)
; PPC64LE-NEXT: std r0, 48(r1)
; PPC64LE-NEXT: #APP ; PPC64LE-NEXT: #APP
; PPC64LE-NEXT: #NO_APP ; PPC64LE-NEXT: #NO_APP
; PPC64LE-NEXT: addi r1, r1, 32 ; PPC64LE-NEXT: addi r1, r1, 32
; PPC64LE-NEXT: ld r0, 16(r1) ; PPC64LE-NEXT: ld r0, 16(r1)
; PPC64LE-NEXT: mtlr r0 ; PPC64LE-NEXT: mtlr r0
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
; ;
; PPC64BE-LABEL: EarlyClobberLR: ; PPC64BE-LABEL: EarlyClobberLR:
; PPC64BE: # %bb.0: # %entry ; PPC64BE: # %bb.0: # %entry
; PPC64BE-NEXT: mflr r0 ; PPC64BE-NEXT: mflr r0
; PPC64BE-NEXT: std r0, 16(r1)
; PPC64BE-NEXT: stdu r1, -48(r1) ; PPC64BE-NEXT: stdu r1, -48(r1)
; PPC64BE-NEXT: std r0, 64(r1)
; PPC64BE-NEXT: #APP ; PPC64BE-NEXT: #APP
; PPC64BE-NEXT: #NO_APP ; PPC64BE-NEXT: #NO_APP
; PPC64BE-NEXT: addi r1, r1, 48 ; PPC64BE-NEXT: addi r1, r1, 48
; PPC64BE-NEXT: ld r0, 16(r1) ; PPC64BE-NEXT: ld r0, 16(r1)
; PPC64BE-NEXT: mtlr r0 ; PPC64BE-NEXT: mtlr r0
; PPC64BE-NEXT: blr ; PPC64BE-NEXT: blr
entry: entry:
tail call i64 asm sideeffect "", "=&{lr}"() tail call i64 asm sideeffect "", "=&{lr}"()
ret void ret void
} }
define dso_local void @ClobberMulti() local_unnamed_addr #0 { define dso_local void @ClobberMulti() local_unnamed_addr #0 {
; PPC64LE-LABEL: ClobberMulti: ; PPC64LE-LABEL: ClobberMulti:
; PPC64LE: # %bb.0: # %entry ; PPC64LE: # %bb.0: # %entry
; PPC64LE-NEXT: mflr r0 ; PPC64LE-NEXT: mflr r0
; PPC64LE-NEXT: std r15, -136(r1) # 8-byte Folded Spill ; PPC64LE-NEXT: std r15, -136(r1) # 8-byte Folded Spill
; PPC64LE-NEXT: std r16, -128(r1) # 8-byte Folded Spill ; PPC64LE-NEXT: std r16, -128(r1) # 8-byte Folded Spill
; PPC64LE-NEXT: std r0, 16(r1)
; PPC64LE-NEXT: stdu r1, -176(r1) ; PPC64LE-NEXT: stdu r1, -176(r1)
; PPC64LE-NEXT: std r0, 192(r1)
; PPC64LE-NEXT: #APP ; PPC64LE-NEXT: #APP
; PPC64LE-NEXT: #NO_APP ; PPC64LE-NEXT: #NO_APP
; PPC64LE-NEXT: addi r1, r1, 176 ; PPC64LE-NEXT: addi r1, r1, 176
; PPC64LE-NEXT: ld r0, 16(r1) ; PPC64LE-NEXT: ld r0, 16(r1)
; PPC64LE-NEXT: ld r16, -128(r1) # 8-byte Folded Reload ; PPC64LE-NEXT: ld r16, -128(r1) # 8-byte Folded Reload
; PPC64LE-NEXT: ld r15, -136(r1) # 8-byte Folded Reload ; PPC64LE-NEXT: ld r15, -136(r1) # 8-byte Folded Reload
; PPC64LE-NEXT: mtlr r0 ; PPC64LE-NEXT: mtlr r0
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
; ;
; PPC64BE-LABEL: ClobberMulti: ; PPC64BE-LABEL: ClobberMulti:
; PPC64BE: # %bb.0: # %entry ; PPC64BE: # %bb.0: # %entry
; PPC64BE-NEXT: mflr r0 ; PPC64BE-NEXT: mflr r0
; PPC64BE-NEXT: std r0, 16(r1)
; PPC64BE-NEXT: stdu r1, -192(r1) ; PPC64BE-NEXT: stdu r1, -192(r1)
; PPC64BE-NEXT: std r0, 208(r1)
; PPC64BE-NEXT: std r15, 56(r1) # 8-byte Folded Spill ; PPC64BE-NEXT: std r15, 56(r1) # 8-byte Folded Spill
; PPC64BE-NEXT: std r16, 64(r1) # 8-byte Folded Spill ; PPC64BE-NEXT: std r16, 64(r1) # 8-byte Folded Spill
; PPC64BE-NEXT: #APP ; PPC64BE-NEXT: #APP
; PPC64BE-NEXT: #NO_APP ; PPC64BE-NEXT: #NO_APP
; PPC64BE-NEXT: ld r16, 64(r1) # 8-byte Folded Reload ; PPC64BE-NEXT: ld r16, 64(r1) # 8-byte Folded Reload
; PPC64BE-NEXT: ld r15, 56(r1) # 8-byte Folded Reload ; PPC64BE-NEXT: ld r15, 56(r1) # 8-byte Folded Reload
; PPC64BE-NEXT: addi r1, r1, 192 ; PPC64BE-NEXT: addi r1, r1, 192
; PPC64BE-NEXT: ld r0, 16(r1) ; PPC64BE-NEXT: ld r0, 16(r1)
; PPC64BE-NEXT: mtlr r0 ; PPC64BE-NEXT: mtlr r0
; PPC64BE-NEXT: blr ; PPC64BE-NEXT: blr
entry: entry:
tail call void asm sideeffect "", "~{lr},~{r15},~{r16}"() tail call void asm sideeffect "", "~{lr},~{r15},~{r16}"()
ret void ret void
} }
attributes #0 = { nounwind } attributes #0 = { nounwind }

llvm/test/CodeGen/PowerPC/ppc64-nest.ll

Show All 11 Lines
; CHECK-NEXT: blr ; CHECK-NEXT: blr
ret ptr %arg ret ptr %arg
} }
define ptr @nest_caller(ptr %arg) nounwind { define ptr @nest_caller(ptr %arg) nounwind {
; CHECK-LABEL: nest_caller: ; CHECK-LABEL: nest_caller:
; CHECK: mr 11, 3 ; CHECK: mr 11, 3
; CHECK: std 0, 128(1)
; CHECK-NEXT: bl nest_receiver ; CHECK-NEXT: bl nest_receiver
; CHECK: blr ; CHECK: blr
%result = call ptr @nest_receiver(ptr nest %arg) %result = call ptr @nest_receiver(ptr nest %arg)
ret ptr %result ret ptr %result
} }
define void @test_indirect(ptr nocapture %f, ptr %p) { define void @test_indirect(ptr nocapture %f, ptr %p) {
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llvm/test/CodeGen/PowerPC/ppc64-notoc-rm-relocation.ll

Show All 36 Lines
; BE-P10-NEXT: addi r1, r1, 112 ; BE-P10-NEXT: addi r1, r1, 112
; BE-P10-NEXT: ld r0, 16(r1) ; BE-P10-NEXT: ld r0, 16(r1)
; BE-P10-NEXT: mtlr r0 ; BE-P10-NEXT: mtlr r0
; BE-P10-NEXT: blr ; BE-P10-NEXT: blr
; ;
; LE-P9-LABEL: main: ; LE-P9-LABEL: main:
; LE-P9: # %bb.0: # %_main_entry ; LE-P9: # %bb.0: # %_main_entry
; LE-P9-NEXT: mflr r0 ; LE-P9-NEXT: mflr r0
; LE-P9-NEXT: std r0, 16(r1)
; LE-P9-NEXT: stdu r1, -32(r1) ; LE-P9-NEXT: stdu r1, -32(r1)
; LE-P9-NEXT: std r0, 48(r1)
; LE-P9-NEXT: bl callee ; LE-P9-NEXT: bl callee
; LE-P9-NEXT: nop ; LE-P9-NEXT: nop
; LE-P9-NEXT: li r3, 0 ; LE-P9-NEXT: li r3, 0
; LE-P9-NEXT: addi r1, r1, 32 ; LE-P9-NEXT: addi r1, r1, 32
; LE-P9-NEXT: ld r0, 16(r1) ; LE-P9-NEXT: ld r0, 16(r1)
; LE-P9-NEXT: mtlr r0 ; LE-P9-NEXT: mtlr r0
; LE-P9-NEXT: blr ; LE-P9-NEXT: blr
; ;
; BE-P9-LABEL: main: ; BE-P9-LABEL: main:
; BE-P9: # %bb.0: # %_main_entry ; BE-P9: # %bb.0: # %_main_entry
; BE-P9-NEXT: mflr r0 ; BE-P9-NEXT: mflr r0
; BE-P9-NEXT: std r0, 16(r1)
; BE-P9-NEXT: stdu r1, -112(r1) ; BE-P9-NEXT: stdu r1, -112(r1)
; BE-P9-NEXT: std r0, 128(r1)
; BE-P9-NEXT: bl callee ; BE-P9-NEXT: bl callee
; BE-P9-NEXT: nop ; BE-P9-NEXT: nop
; BE-P9-NEXT: li r3, 0 ; BE-P9-NEXT: li r3, 0
; BE-P9-NEXT: addi r1, r1, 112 ; BE-P9-NEXT: addi r1, r1, 112
; BE-P9-NEXT: ld r0, 16(r1) ; BE-P9-NEXT: ld r0, 16(r1)
; BE-P9-NEXT: mtlr r0 ; BE-P9-NEXT: mtlr r0
; BE-P9-NEXT: blr ; BE-P9-NEXT: blr
_main_entry: _main_entry:
Show All 9 Lines

llvm/test/CodeGen/PowerPC/ppc64-rop-protection-aix.ll

Show First 20 Lines • Show All 60 Lines • ▼ Show 20 Lines
; BE-P10-NEXT: ld r0, 16(r1) ; BE-P10-NEXT: ld r0, 16(r1)
; BE-P10-NEXT: hashchk r0, -16(r1) ; BE-P10-NEXT: hashchk r0, -16(r1)
; BE-P10-NEXT: mtlr r0 ; BE-P10-NEXT: mtlr r0
; BE-P10-NEXT: blr ; BE-P10-NEXT: blr
; ;
; BE-P9-LABEL: caller: ; BE-P9-LABEL: caller:
; BE-P9: # %bb.0: # %entry ; BE-P9: # %bb.0: # %entry
; BE-P9-NEXT: mflr r0 ; BE-P9-NEXT: mflr r0
; BE-P9-NEXT: std r0, 16(r1)
; BE-P9-NEXT: hashst r0, -16(r1)
; BE-P9-NEXT: stdu r1, -128(r1) ; BE-P9-NEXT: stdu r1, -128(r1)
; BE-P9-NEXT: std r0, 144(r1)
; BE-P9-NEXT: hashst r0, -16(r1)
; BE-P9-NEXT: std r31, 120(r1) # 8-byte Folded Spill ; BE-P9-NEXT: std r31, 120(r1) # 8-byte Folded Spill
; BE-P9-NEXT: mr r31, r4 ; BE-P9-NEXT: mr r31, r4
; BE-P9-NEXT: bl .callee[PR] ; BE-P9-NEXT: bl .callee[PR]
; BE-P9-NEXT: nop ; BE-P9-NEXT: nop
; BE-P9-NEXT: add r3, r3, r31 ; BE-P9-NEXT: add r3, r3, r31
; BE-P9-NEXT: ld r31, 120(r1) # 8-byte Folded Reload ; BE-P9-NEXT: ld r31, 120(r1) # 8-byte Folded Reload
; BE-P9-NEXT: clrldi r3, r3, 32 ; BE-P9-NEXT: clrldi r3, r3, 32
; BE-P9-NEXT: addi r1, r1, 128 ; BE-P9-NEXT: addi r1, r1, 128
; BE-P9-NEXT: ld r0, 16(r1) ; BE-P9-NEXT: ld r0, 16(r1)
; BE-P9-NEXT: mtlr r0 ; BE-P9-NEXT: mtlr r0
; BE-P9-NEXT: hashchk r0, -16(r1) ; BE-P9-NEXT: hashchk r0, -16(r1)
; BE-P9-NEXT: blr ; BE-P9-NEXT: blr
; ;
; BE-P8-LABEL: caller: ; BE-P8-LABEL: caller:
; BE-P8: # %bb.0: # %entry ; BE-P8: # %bb.0: # %entry
; BE-P8-NEXT: mflr r0 ; BE-P8-NEXT: mflr r0
; BE-P8-NEXT: std r0, 16(r1)
; BE-P8-NEXT: hashst r0, -16(r1)
; BE-P8-NEXT: stdu r1, -128(r1) ; BE-P8-NEXT: stdu r1, -128(r1)
; BE-P8-NEXT: std r0, 144(r1)
; BE-P8-NEXT: hashst r0, -16(r1)
; BE-P8-NEXT: std r31, 120(r1) # 8-byte Folded Spill ; BE-P8-NEXT: std r31, 120(r1) # 8-byte Folded Spill
; BE-P8-NEXT: mr r31, r4 ; BE-P8-NEXT: mr r31, r4
; BE-P8-NEXT: bl .callee[PR] ; BE-P8-NEXT: bl .callee[PR]
; BE-P8-NEXT: nop ; BE-P8-NEXT: nop
; BE-P8-NEXT: add r3, r3, r31 ; BE-P8-NEXT: add r3, r3, r31
; BE-P8-NEXT: ld r31, 120(r1) # 8-byte Folded Reload ; BE-P8-NEXT: ld r31, 120(r1) # 8-byte Folded Reload
; BE-P8-NEXT: clrldi r3, r3, 32 ; BE-P8-NEXT: clrldi r3, r3, 32
; BE-P8-NEXT: addi r1, r1, 128 ; BE-P8-NEXT: addi r1, r1, 128
Show All 18 Lines
; BE-32BIT-P10-NEXT: lwz r0, 8(r1) ; BE-32BIT-P10-NEXT: lwz r0, 8(r1)
; BE-32BIT-P10-NEXT: hashchk r0, -16(r1) ; BE-32BIT-P10-NEXT: hashchk r0, -16(r1)
; BE-32BIT-P10-NEXT: mtlr r0 ; BE-32BIT-P10-NEXT: mtlr r0
; BE-32BIT-P10-NEXT: blr ; BE-32BIT-P10-NEXT: blr
; ;
; BE-32BIT-P9-LABEL: caller: ; BE-32BIT-P9-LABEL: caller:
; BE-32BIT-P9: # %bb.0: # %entry ; BE-32BIT-P9: # %bb.0: # %entry
; BE-32BIT-P9-NEXT: mflr r0 ; BE-32BIT-P9-NEXT: mflr r0
; BE-32BIT-P9-NEXT: stw r0, 8(r1)
; BE-32BIT-P9-NEXT: hashst r0, -16(r1)
; BE-32BIT-P9-NEXT: stwu r1, -80(r1) ; BE-32BIT-P9-NEXT: stwu r1, -80(r1)
; BE-32BIT-P9-NEXT: stw r0, 88(r1)
; BE-32BIT-P9-NEXT: hashst r0, -16(r1)
; BE-32BIT-P9-NEXT: stw r31, 76(r1) # 4-byte Folded Spill ; BE-32BIT-P9-NEXT: stw r31, 76(r1) # 4-byte Folded Spill
; BE-32BIT-P9-NEXT: mr r31, r4 ; BE-32BIT-P9-NEXT: mr r31, r4
; BE-32BIT-P9-NEXT: bl .callee[PR] ; BE-32BIT-P9-NEXT: bl .callee[PR]
; BE-32BIT-P9-NEXT: nop ; BE-32BIT-P9-NEXT: nop
; BE-32BIT-P9-NEXT: add r3, r3, r31 ; BE-32BIT-P9-NEXT: add r3, r3, r31
; BE-32BIT-P9-NEXT: lwz r31, 76(r1) # 4-byte Folded Reload ; BE-32BIT-P9-NEXT: lwz r31, 76(r1) # 4-byte Folded Reload
; BE-32BIT-P9-NEXT: addi r1, r1, 80 ; BE-32BIT-P9-NEXT: addi r1, r1, 80
; BE-32BIT-P9-NEXT: lwz r0, 8(r1) ; BE-32BIT-P9-NEXT: lwz r0, 8(r1)
; BE-32BIT-P9-NEXT: mtlr r0 ; BE-32BIT-P9-NEXT: mtlr r0
; BE-32BIT-P9-NEXT: hashchk r0, -16(r1) ; BE-32BIT-P9-NEXT: hashchk r0, -16(r1)
; BE-32BIT-P9-NEXT: blr ; BE-32BIT-P9-NEXT: blr
; ;
; BE-32BIT-P8-LABEL: caller: ; BE-32BIT-P8-LABEL: caller:
; BE-32BIT-P8: # %bb.0: # %entry ; BE-32BIT-P8: # %bb.0: # %entry
; BE-32BIT-P8-NEXT: mflr r0 ; BE-32BIT-P8-NEXT: mflr r0
; BE-32BIT-P8-NEXT: stw r0, 8(r1)
; BE-32BIT-P8-NEXT: hashst r0, -16(r1)
; BE-32BIT-P8-NEXT: stwu r1, -80(r1) ; BE-32BIT-P8-NEXT: stwu r1, -80(r1)
; BE-32BIT-P8-NEXT: stw r0, 88(r1)
; BE-32BIT-P8-NEXT: hashst r0, -16(r1)
; BE-32BIT-P8-NEXT: stw r31, 76(r1) # 4-byte Folded Spill ; BE-32BIT-P8-NEXT: stw r31, 76(r1) # 4-byte Folded Spill
; BE-32BIT-P8-NEXT: mr r31, r4 ; BE-32BIT-P8-NEXT: mr r31, r4
; BE-32BIT-P8-NEXT: bl .callee[PR] ; BE-32BIT-P8-NEXT: bl .callee[PR]
; BE-32BIT-P8-NEXT: nop ; BE-32BIT-P8-NEXT: nop
; BE-32BIT-P8-NEXT: add r3, r3, r31 ; BE-32BIT-P8-NEXT: add r3, r3, r31
; BE-32BIT-P8-NEXT: lwz r31, 76(r1) # 4-byte Folded Reload ; BE-32BIT-P8-NEXT: lwz r31, 76(r1) # 4-byte Folded Reload
; BE-32BIT-P8-NEXT: addi r1, r1, 80 ; BE-32BIT-P8-NEXT: addi r1, r1, 80
; BE-32BIT-P8-NEXT: lwz r0, 8(r1) ; BE-32BIT-P8-NEXT: lwz r0, 8(r1)
Show All 18 Lines
; BE-P10-PRIV-NEXT: ld r0, 16(r1) ; BE-P10-PRIV-NEXT: ld r0, 16(r1)
; BE-P10-PRIV-NEXT: hashchkp r0, -16(r1) ; BE-P10-PRIV-NEXT: hashchkp r0, -16(r1)
; BE-P10-PRIV-NEXT: mtlr r0 ; BE-P10-PRIV-NEXT: mtlr r0
; BE-P10-PRIV-NEXT: blr ; BE-P10-PRIV-NEXT: blr
; ;
; BE-P9-PRIV-LABEL: caller: ; BE-P9-PRIV-LABEL: caller:
; BE-P9-PRIV: # %bb.0: # %entry ; BE-P9-PRIV: # %bb.0: # %entry
; BE-P9-PRIV-NEXT: mflr r0 ; BE-P9-PRIV-NEXT: mflr r0
; BE-P9-PRIV-NEXT: std r0, 16(r1)
; BE-P9-PRIV-NEXT: hashstp r0, -16(r1)
; BE-P9-PRIV-NEXT: stdu r1, -128(r1) ; BE-P9-PRIV-NEXT: stdu r1, -128(r1)
; BE-P9-PRIV-NEXT: std r0, 144(r1)
; BE-P9-PRIV-NEXT: hashstp r0, -16(r1)
; BE-P9-PRIV-NEXT: std r31, 120(r1) # 8-byte Folded Spill ; BE-P9-PRIV-NEXT: std r31, 120(r1) # 8-byte Folded Spill
; BE-P9-PRIV-NEXT: mr r31, r4 ; BE-P9-PRIV-NEXT: mr r31, r4
; BE-P9-PRIV-NEXT: bl .callee[PR] ; BE-P9-PRIV-NEXT: bl .callee[PR]
; BE-P9-PRIV-NEXT: nop ; BE-P9-PRIV-NEXT: nop
; BE-P9-PRIV-NEXT: add r3, r3, r31 ; BE-P9-PRIV-NEXT: add r3, r3, r31
; BE-P9-PRIV-NEXT: ld r31, 120(r1) # 8-byte Folded Reload ; BE-P9-PRIV-NEXT: ld r31, 120(r1) # 8-byte Folded Reload
; BE-P9-PRIV-NEXT: clrldi r3, r3, 32 ; BE-P9-PRIV-NEXT: clrldi r3, r3, 32
; BE-P9-PRIV-NEXT: addi r1, r1, 128 ; BE-P9-PRIV-NEXT: addi r1, r1, 128
; BE-P9-PRIV-NEXT: ld r0, 16(r1) ; BE-P9-PRIV-NEXT: ld r0, 16(r1)
; BE-P9-PRIV-NEXT: mtlr r0 ; BE-P9-PRIV-NEXT: mtlr r0
; BE-P9-PRIV-NEXT: hashchkp r0, -16(r1) ; BE-P9-PRIV-NEXT: hashchkp r0, -16(r1)
; BE-P9-PRIV-NEXT: blr ; BE-P9-PRIV-NEXT: blr
; ;
; BE-P8-PRIV-LABEL: caller: ; BE-P8-PRIV-LABEL: caller:
; BE-P8-PRIV: # %bb.0: # %entry ; BE-P8-PRIV: # %bb.0: # %entry
; BE-P8-PRIV-NEXT: mflr r0 ; BE-P8-PRIV-NEXT: mflr r0
; BE-P8-PRIV-NEXT: std r0, 16(r1)
; BE-P8-PRIV-NEXT: hashstp r0, -16(r1)
; BE-P8-PRIV-NEXT: stdu r1, -128(r1) ; BE-P8-PRIV-NEXT: stdu r1, -128(r1)
; BE-P8-PRIV-NEXT: std r0, 144(r1)
; BE-P8-PRIV-NEXT: hashstp r0, -16(r1)
; BE-P8-PRIV-NEXT: std r31, 120(r1) # 8-byte Folded Spill ; BE-P8-PRIV-NEXT: std r31, 120(r1) # 8-byte Folded Spill
; BE-P8-PRIV-NEXT: mr r31, r4 ; BE-P8-PRIV-NEXT: mr r31, r4
; BE-P8-PRIV-NEXT: bl .callee[PR] ; BE-P8-PRIV-NEXT: bl .callee[PR]
; BE-P8-PRIV-NEXT: nop ; BE-P8-PRIV-NEXT: nop
; BE-P8-PRIV-NEXT: add r3, r3, r31 ; BE-P8-PRIV-NEXT: add r3, r3, r31
; BE-P8-PRIV-NEXT: ld r31, 120(r1) # 8-byte Folded Reload ; BE-P8-PRIV-NEXT: ld r31, 120(r1) # 8-byte Folded Reload
; BE-P8-PRIV-NEXT: clrldi r3, r3, 32 ; BE-P8-PRIV-NEXT: clrldi r3, r3, 32
; BE-P8-PRIV-NEXT: addi r1, r1, 128 ; BE-P8-PRIV-NEXT: addi r1, r1, 128
Show All 18 Lines
; BE-32BIT-P10-PRIV-NEXT: lwz r0, 8(r1) ; BE-32BIT-P10-PRIV-NEXT: lwz r0, 8(r1)
; BE-32BIT-P10-PRIV-NEXT: hashchkp r0, -16(r1) ; BE-32BIT-P10-PRIV-NEXT: hashchkp r0, -16(r1)
; BE-32BIT-P10-PRIV-NEXT: mtlr r0 ; BE-32BIT-P10-PRIV-NEXT: mtlr r0
; BE-32BIT-P10-PRIV-NEXT: blr ; BE-32BIT-P10-PRIV-NEXT: blr
; ;
; BE-32BIT-P9-PRIV-LABEL: caller: ; BE-32BIT-P9-PRIV-LABEL: caller:
; BE-32BIT-P9-PRIV: # %bb.0: # %entry ; BE-32BIT-P9-PRIV: # %bb.0: # %entry
; BE-32BIT-P9-PRIV-NEXT: mflr r0 ; BE-32BIT-P9-PRIV-NEXT: mflr r0
; BE-32BIT-P9-PRIV-NEXT: stw r0, 8(r1)
; BE-32BIT-P9-PRIV-NEXT: hashstp r0, -16(r1)
; BE-32BIT-P9-PRIV-NEXT: stwu r1, -80(r1) ; BE-32BIT-P9-PRIV-NEXT: stwu r1, -80(r1)
; BE-32BIT-P9-PRIV-NEXT: stw r0, 88(r1)
; BE-32BIT-P9-PRIV-NEXT: hashstp r0, -16(r1)
; BE-32BIT-P9-PRIV-NEXT: stw r31, 76(r1) # 4-byte Folded Spill ; BE-32BIT-P9-PRIV-NEXT: stw r31, 76(r1) # 4-byte Folded Spill
; BE-32BIT-P9-PRIV-NEXT: mr r31, r4 ; BE-32BIT-P9-PRIV-NEXT: mr r31, r4
; BE-32BIT-P9-PRIV-NEXT: bl .callee[PR] ; BE-32BIT-P9-PRIV-NEXT: bl .callee[PR]
; BE-32BIT-P9-PRIV-NEXT: nop ; BE-32BIT-P9-PRIV-NEXT: nop
; BE-32BIT-P9-PRIV-NEXT: add r3, r3, r31 ; BE-32BIT-P9-PRIV-NEXT: add r3, r3, r31
; BE-32BIT-P9-PRIV-NEXT: lwz r31, 76(r1) # 4-byte Folded Reload ; BE-32BIT-P9-PRIV-NEXT: lwz r31, 76(r1) # 4-byte Folded Reload
; BE-32BIT-P9-PRIV-NEXT: addi r1, r1, 80 ; BE-32BIT-P9-PRIV-NEXT: addi r1, r1, 80
; BE-32BIT-P9-PRIV-NEXT: lwz r0, 8(r1) ; BE-32BIT-P9-PRIV-NEXT: lwz r0, 8(r1)
; BE-32BIT-P9-PRIV-NEXT: mtlr r0 ; BE-32BIT-P9-PRIV-NEXT: mtlr r0
; BE-32BIT-P9-PRIV-NEXT: hashchkp r0, -16(r1) ; BE-32BIT-P9-PRIV-NEXT: hashchkp r0, -16(r1)
; BE-32BIT-P9-PRIV-NEXT: blr ; BE-32BIT-P9-PRIV-NEXT: blr
; ;
; BE-32BIT-P8-PRIV-LABEL: caller: ; BE-32BIT-P8-PRIV-LABEL: caller:
; BE-32BIT-P8-PRIV: # %bb.0: # %entry ; BE-32BIT-P8-PRIV: # %bb.0: # %entry
; BE-32BIT-P8-PRIV-NEXT: mflr r0 ; BE-32BIT-P8-PRIV-NEXT: mflr r0
; BE-32BIT-P8-PRIV-NEXT: stw r0, 8(r1)
; BE-32BIT-P8-PRIV-NEXT: hashstp r0, -16(r1)
; BE-32BIT-P8-PRIV-NEXT: stwu r1, -80(r1) ; BE-32BIT-P8-PRIV-NEXT: stwu r1, -80(r1)
; BE-32BIT-P8-PRIV-NEXT: stw r0, 88(r1)
; BE-32BIT-P8-PRIV-NEXT: hashstp r0, -16(r1)
; BE-32BIT-P8-PRIV-NEXT: stw r31, 76(r1) # 4-byte Folded Spill ; BE-32BIT-P8-PRIV-NEXT: stw r31, 76(r1) # 4-byte Folded Spill
; BE-32BIT-P8-PRIV-NEXT: mr r31, r4 ; BE-32BIT-P8-PRIV-NEXT: mr r31, r4
; BE-32BIT-P8-PRIV-NEXT: bl .callee[PR] ; BE-32BIT-P8-PRIV-NEXT: bl .callee[PR]
; BE-32BIT-P8-PRIV-NEXT: nop ; BE-32BIT-P8-PRIV-NEXT: nop
; BE-32BIT-P8-PRIV-NEXT: add r3, r3, r31 ; BE-32BIT-P8-PRIV-NEXT: add r3, r3, r31
; BE-32BIT-P8-PRIV-NEXT: lwz r31, 76(r1) # 4-byte Folded Reload ; BE-32BIT-P8-PRIV-NEXT: lwz r31, 76(r1) # 4-byte Folded Reload
; BE-32BIT-P8-PRIV-NEXT: addi r1, r1, 80 ; BE-32BIT-P8-PRIV-NEXT: addi r1, r1, 80
; BE-32BIT-P8-PRIV-NEXT: lwz r0, 8(r1) ; BE-32BIT-P8-PRIV-NEXT: lwz r0, 8(r1)
▲ Show 20 Lines • Show All 136 Lines • ▼ Show 20 Lines
; BE-P10-NEXT: hashchk r0, -488(r1) ; BE-P10-NEXT: hashchk r0, -488(r1)
; BE-P10-NEXT: mtocrf 32, r12 ; BE-P10-NEXT: mtocrf 32, r12
; BE-P10-NEXT: mtocrf 16, r12 ; BE-P10-NEXT: mtocrf 16, r12
; BE-P10-NEXT: mtocrf 8, r12 ; BE-P10-NEXT: mtocrf 8, r12
; BE-P10-NEXT: blr ; BE-P10-NEXT: blr
; ;
; BE-P9-LABEL: spill: ; BE-P9-LABEL: spill:
; BE-P9: # %bb.0: # %entry ; BE-P9: # %bb.0: # %entry
; BE-P9-NEXT: mflr r0
; BE-P9-NEXT: mfcr r12 ; BE-P9-NEXT: mfcr r12
; BE-P9-NEXT: std r0, 16(r1) ; BE-P9-NEXT: mflr r0
; BE-P9-NEXT: hashst r0, -488(r1)
; BE-P9-NEXT: stw r12, 8(r1) ; BE-P9-NEXT: stw r12, 8(r1)
; BE-P9-NEXT: stdu r1, -624(r1) ; BE-P9-NEXT: stdu r1, -624(r1)
; BE-P9-NEXT: lwz r4, 12(r3) ; BE-P9-NEXT: std r0, 640(r1)
; BE-P9-NEXT: hashst r0, -488(r1)
; BE-P9-NEXT: std r14, 336(r1) # 8-byte Folded Spill ; BE-P9-NEXT: std r14, 336(r1) # 8-byte Folded Spill
; BE-P9-NEXT: std r15, 344(r1) # 8-byte Folded Spill
; BE-P9-NEXT: stxv v20, 144(r1) # 16-byte Folded Spill ; BE-P9-NEXT: stxv v20, 144(r1) # 16-byte Folded Spill
; BE-P9-NEXT: stxv v21, 160(r1) # 16-byte Folded Spill ; BE-P9-NEXT: stxv v21, 160(r1) # 16-byte Folded Spill
; BE-P9-NEXT: lwz r4, 12(r3)
; BE-P9-NEXT: std r15, 344(r1) # 8-byte Folded Spill
; BE-P9-NEXT: stxv v22, 176(r1) # 16-byte Folded Spill ; BE-P9-NEXT: stxv v22, 176(r1) # 16-byte Folded Spill
; BE-P9-NEXT: std r16, 352(r1) # 8-byte Folded Spill ; BE-P9-NEXT: std r16, 352(r1) # 8-byte Folded Spill
; BE-P9-NEXT: std r17, 360(r1) # 8-byte Folded Spill
; BE-P9-NEXT: stxv v23, 192(r1) # 16-byte Folded Spill ; BE-P9-NEXT: stxv v23, 192(r1) # 16-byte Folded Spill
; BE-P9-NEXT: std r18, 368(r1) # 8-byte Folded Spill ; BE-P9-NEXT: std r17, 360(r1) # 8-byte Folded Spill
; BE-P9-NEXT: stxv v24, 208(r1) # 16-byte Folded Spill ; BE-P9-NEXT: stxv v24, 208(r1) # 16-byte Folded Spill
; BE-P9-NEXT: std r19, 376(r1) # 8-byte Folded Spill ; BE-P9-NEXT: std r18, 368(r1) # 8-byte Folded Spill
; BE-P9-NEXT: stxv v25, 224(r1) # 16-byte Folded Spill ; BE-P9-NEXT: stxv v25, 224(r1) # 16-byte Folded Spill
; BE-P9-NEXT: std r19, 376(r1) # 8-byte Folded Spill
; BE-P9-NEXT: std r20, 384(r1) # 8-byte Folded Spill ; BE-P9-NEXT: std r20, 384(r1) # 8-byte Folded Spill
; BE-P9-NEXT: std r21, 392(r1) # 8-byte Folded Spill
; BE-P9-NEXT: stxv v26, 240(r1) # 16-byte Folded Spill ; BE-P9-NEXT: stxv v26, 240(r1) # 16-byte Folded Spill
; BE-P9-NEXT: std r22, 400(r1) # 8-byte Folded Spill ; BE-P9-NEXT: std r21, 392(r1) # 8-byte Folded Spill
; BE-P9-NEXT: stxv v27, 256(r1) # 16-byte Folded Spill ; BE-P9-NEXT: stxv v27, 256(r1) # 16-byte Folded Spill
; BE-P9-NEXT: std r23, 408(r1) # 8-byte Folded Spill ; BE-P9-NEXT: std r22, 400(r1) # 8-byte Folded Spill
; BE-P9-NEXT: stxv v28, 272(r1) # 16-byte Folded Spill ; BE-P9-NEXT: stxv v28, 272(r1) # 16-byte Folded Spill
; BE-P9-NEXT: std r23, 408(r1) # 8-byte Folded Spill
; BE-P9-NEXT: std r24, 416(r1) # 8-byte Folded Spill ; BE-P9-NEXT: std r24, 416(r1) # 8-byte Folded Spill
; BE-P9-NEXT: std r25, 424(r1) # 8-byte Folded Spill
; BE-P9-NEXT: stxv v29, 288(r1) # 16-byte Folded Spill ; BE-P9-NEXT: stxv v29, 288(r1) # 16-byte Folded Spill
; BE-P9-NEXT: std r26, 432(r1) # 8-byte Folded Spill ; BE-P9-NEXT: std r25, 424(r1) # 8-byte Folded Spill
; BE-P9-NEXT: stxv v30, 304(r1) # 16-byte Folded Spill ; BE-P9-NEXT: stxv v30, 304(r1) # 16-byte Folded Spill
; BE-P9-NEXT: std r27, 440(r1) # 8-byte Folded Spill ; BE-P9-NEXT: std r26, 432(r1) # 8-byte Folded Spill
; BE-P9-NEXT: stxv v31, 320(r1) # 16-byte Folded Spill ; BE-P9-NEXT: stxv v31, 320(r1) # 16-byte Folded Spill
; BE-P9-NEXT: std r27, 440(r1) # 8-byte Folded Spill
; BE-P9-NEXT: std r28, 448(r1) # 8-byte Folded Spill ; BE-P9-NEXT: std r28, 448(r1) # 8-byte Folded Spill
; BE-P9-NEXT: std r29, 456(r1) # 8-byte Folded Spill ; BE-P9-NEXT: std r29, 456(r1) # 8-byte Folded Spill
; BE-P9-NEXT: std r30, 464(r1) # 8-byte Folded Spill ; BE-P9-NEXT: std r30, 464(r1) # 8-byte Folded Spill
; BE-P9-NEXT: std r31, 472(r1) # 8-byte Folded Spill ; BE-P9-NEXT: std r31, 472(r1) # 8-byte Folded Spill
; BE-P9-NEXT: stfd f14, 480(r1) # 8-byte Folded Spill ; BE-P9-NEXT: stfd f14, 480(r1) # 8-byte Folded Spill
; BE-P9-NEXT: stfd f15, 488(r1) # 8-byte Folded Spill ; BE-P9-NEXT: stfd f15, 488(r1) # 8-byte Folded Spill
; BE-P9-NEXT: stfd f16, 496(r1) # 8-byte Folded Spill ; BE-P9-NEXT: stfd f16, 496(r1) # 8-byte Folded Spill
; BE-P9-NEXT: stfd f17, 504(r1) # 8-byte Folded Spill ; BE-P9-NEXT: stfd f17, 504(r1) # 8-byte Folded Spill
▲ Show 20 Lines • Show All 80 Lines • ▼ Show 20 Lines
; BE-P9-NEXT: mtocrf 16, r12 ; BE-P9-NEXT: mtocrf 16, r12
; BE-P9-NEXT: mtocrf 8, r12 ; BE-P9-NEXT: mtocrf 8, r12
; BE-P9-NEXT: blr ; BE-P9-NEXT: blr
; ;
; BE-P8-LABEL: spill: ; BE-P8-LABEL: spill:
; BE-P8: # %bb.0: # %entry ; BE-P8: # %bb.0: # %entry
; BE-P8-NEXT: mfcr r12 ; BE-P8-NEXT: mfcr r12
; BE-P8-NEXT: mflr r0 ; BE-P8-NEXT: mflr r0
; BE-P8-NEXT: std r0, 16(r1)
; BE-P8-NEXT: hashst r0, -488(r1)
; BE-P8-NEXT: stw r12, 8(r1) ; BE-P8-NEXT: stw r12, 8(r1)
; BE-P8-NEXT: stdu r1, -624(r1) ; BE-P8-NEXT: stdu r1, -624(r1)
; BE-P8-NEXT: li r4, 144 ; BE-P8-NEXT: li r4, 144
; BE-P8-NEXT: std r0, 640(r1)
; BE-P8-NEXT: hashst r0, -488(r1)
; BE-P8-NEXT: std r14, 336(r1) # 8-byte Folded Spill ; BE-P8-NEXT: std r14, 336(r1) # 8-byte Folded Spill
; BE-P8-NEXT: std r15, 344(r1) # 8-byte Folded Spill ; BE-P8-NEXT: std r15, 344(r1) # 8-byte Folded Spill
; BE-P8-NEXT: std r16, 352(r1) # 8-byte Folded Spill ; BE-P8-NEXT: std r16, 352(r1) # 8-byte Folded Spill
; BE-P8-NEXT: std r17, 360(r1) # 8-byte Folded Spill
; BE-P8-NEXT: stxvd2x v20, r1, r4 # 16-byte Folded Spill ; BE-P8-NEXT: stxvd2x v20, r1, r4 # 16-byte Folded Spill
; BE-P8-NEXT: li r4, 160 ; BE-P8-NEXT: li r4, 160
; BE-P8-NEXT: std r17, 360(r1) # 8-byte Folded Spill
; BE-P8-NEXT: std r18, 368(r1) # 8-byte Folded Spill ; BE-P8-NEXT: std r18, 368(r1) # 8-byte Folded Spill
; BE-P8-NEXT: std r19, 376(r1) # 8-byte Folded Spill ; BE-P8-NEXT: std r19, 376(r1) # 8-byte Folded Spill
; BE-P8-NEXT: std r20, 384(r1) # 8-byte Folded Spill ; BE-P8-NEXT: std r20, 384(r1) # 8-byte Folded Spill
; BE-P8-NEXT: std r21, 392(r1) # 8-byte Folded Spill
; BE-P8-NEXT: stxvd2x v21, r1, r4 # 16-byte Folded Spill ; BE-P8-NEXT: stxvd2x v21, r1, r4 # 16-byte Folded Spill
; BE-P8-NEXT: li r4, 176 ; BE-P8-NEXT: li r4, 176
; BE-P8-NEXT: std r21, 392(r1) # 8-byte Folded Spill
; BE-P8-NEXT: std r22, 400(r1) # 8-byte Folded Spill ; BE-P8-NEXT: std r22, 400(r1) # 8-byte Folded Spill
; BE-P8-NEXT: std r23, 408(r1) # 8-byte Folded Spill ; BE-P8-NEXT: std r23, 408(r1) # 8-byte Folded Spill
; BE-P8-NEXT: std r24, 416(r1) # 8-byte Folded Spill ; BE-P8-NEXT: std r24, 416(r1) # 8-byte Folded Spill
; BE-P8-NEXT: std r25, 424(r1) # 8-byte Folded Spill ; BE-P8-NEXT: std r25, 424(r1) # 8-byte Folded Spill
; BE-P8-NEXT: std r26, 432(r1) # 8-byte Folded Spill ; BE-P8-NEXT: std r26, 432(r1) # 8-byte Folded Spill
; BE-P8-NEXT: std r27, 440(r1) # 8-byte Folded Spill ; BE-P8-NEXT: std r27, 440(r1) # 8-byte Folded Spill
; BE-P8-NEXT: std r28, 448(r1) # 8-byte Folded Spill ; BE-P8-NEXT: std r28, 448(r1) # 8-byte Folded Spill
; BE-P8-NEXT: std r29, 456(r1) # 8-byte Folded Spill ; BE-P8-NEXT: std r29, 456(r1) # 8-byte Folded Spill
; BE-P8-NEXT: std r30, 464(r1) # 8-byte Folded Spill ; BE-P8-NEXT: std r30, 464(r1) # 8-byte Folded Spill
; BE-P8-NEXT: std r31, 472(r1) # 8-byte Folded Spill ; BE-P8-NEXT: std r31, 472(r1) # 8-byte Folded Spill
; BE-P8-NEXT: std r3, 120(r1) # 8-byte Folded Spill ; BE-P8-NEXT: std r3, 120(r1) # 8-byte Folded Spill
; BE-P8-NEXT: stxvd2x v22, r1, r4 # 16-byte Folded Spill ; BE-P8-NEXT: stxvd2x v22, r1, r4 # 16-byte Folded Spill
; BE-P8-NEXT: li r4, 192 ; BE-P8-NEXT: li r4, 192
; BE-P8-NEXT: stfd f14, 480(r1) # 8-byte Folded Spill
; BE-P8-NEXT: stxvd2x v23, r1, r4 # 16-byte Folded Spill ; BE-P8-NEXT: stxvd2x v23, r1, r4 # 16-byte Folded Spill
; BE-P8-NEXT: li r4, 208 ; BE-P8-NEXT: li r4, 208
; BE-P8-NEXT: stfd f14, 480(r1) # 8-byte Folded Spill ; BE-P8-NEXT: stfd f15, 488(r1) # 8-byte Folded Spill
; BE-P8-NEXT: stxvd2x v24, r1, r4 # 16-byte Folded Spill ; BE-P8-NEXT: stxvd2x v24, r1, r4 # 16-byte Folded Spill
; BE-P8-NEXT: li r4, 224 ; BE-P8-NEXT: li r4, 224
; BE-P8-NEXT: stfd f15, 488(r1) # 8-byte Folded Spill ; BE-P8-NEXT: stfd f16, 496(r1) # 8-byte Folded Spill
; BE-P8-NEXT: stxvd2x v25, r1, r4 # 16-byte Folded Spill ; BE-P8-NEXT: stxvd2x v25, r1, r4 # 16-byte Folded Spill
; BE-P8-NEXT: li r4, 240 ; BE-P8-NEXT: li r4, 240
; BE-P8-NEXT: stfd f16, 496(r1) # 8-byte Folded Spill ; BE-P8-NEXT: stfd f17, 504(r1) # 8-byte Folded Spill
; BE-P8-NEXT: stxvd2x v26, r1, r4 # 16-byte Folded Spill ; BE-P8-NEXT: stxvd2x v26, r1, r4 # 16-byte Folded Spill
; BE-P8-NEXT: li r4, 256 ; BE-P8-NEXT: li r4, 256
; BE-P8-NEXT: stfd f17, 504(r1) # 8-byte Folded Spill ; BE-P8-NEXT: stfd f18, 512(r1) # 8-byte Folded Spill
; BE-P8-NEXT: stxvd2x v27, r1, r4 # 16-byte Folded Spill ; BE-P8-NEXT: stxvd2x v27, r1, r4 # 16-byte Folded Spill
; BE-P8-NEXT: li r4, 272 ; BE-P8-NEXT: li r4, 272
; BE-P8-NEXT: stfd f18, 512(r1) # 8-byte Folded Spill ; BE-P8-NEXT: stfd f19, 520(r1) # 8-byte Folded Spill
; BE-P8-NEXT: stxvd2x v28, r1, r4 # 16-byte Folded Spill ; BE-P8-NEXT: stxvd2x v28, r1, r4 # 16-byte Folded Spill
; BE-P8-NEXT: li r4, 288 ; BE-P8-NEXT: li r4, 288
; BE-P8-NEXT: stfd f19, 520(r1) # 8-byte Folded Spill ; BE-P8-NEXT: stfd f20, 528(r1) # 8-byte Folded Spill
; BE-P8-NEXT: stxvd2x v29, r1, r4 # 16-byte Folded Spill ; BE-P8-NEXT: stxvd2x v29, r1, r4 # 16-byte Folded Spill
; BE-P8-NEXT: li r4, 304 ; BE-P8-NEXT: li r4, 304
; BE-P8-NEXT: stfd f20, 528(r1) # 8-byte Folded Spill ; BE-P8-NEXT: stfd f21, 536(r1) # 8-byte Folded Spill
; BE-P8-NEXT: stxvd2x v30, r1, r4 # 16-byte Folded Spill ; BE-P8-NEXT: stxvd2x v30, r1, r4 # 16-byte Folded Spill
; BE-P8-NEXT: li r4, 320 ; BE-P8-NEXT: li r4, 320
; BE-P8-NEXT: stfd f21, 536(r1) # 8-byte Folded Spill ; BE-P8-NEXT: stfd f22, 544(r1) # 8-byte Folded Spill
; BE-P8-NEXT: stxvd2x v31, r1, r4 # 16-byte Folded Spill ; BE-P8-NEXT: stxvd2x v31, r1, r4 # 16-byte Folded Spill
; BE-P8-NEXT: lwz r4, 12(r3) ; BE-P8-NEXT: lwz r4, 12(r3)
; BE-P8-NEXT: stfd f22, 544(r1) # 8-byte Folded Spill
; BE-P8-NEXT: stfd f23, 552(r1) # 8-byte Folded Spill ; BE-P8-NEXT: stfd f23, 552(r1) # 8-byte Folded Spill
; BE-P8-NEXT: stfd f24, 560(r1) # 8-byte Folded Spill ; BE-P8-NEXT: stfd f24, 560(r1) # 8-byte Folded Spill
; BE-P8-NEXT: stfd f25, 568(r1) # 8-byte Folded Spill ; BE-P8-NEXT: stfd f25, 568(r1) # 8-byte Folded Spill
; BE-P8-NEXT: stfd f26, 576(r1) # 8-byte Folded Spill ; BE-P8-NEXT: stfd f26, 576(r1) # 8-byte Folded Spill
; BE-P8-NEXT: stfd f27, 584(r1) # 8-byte Folded Spill ; BE-P8-NEXT: stfd f27, 584(r1) # 8-byte Folded Spill
; BE-P8-NEXT: stfd f28, 592(r1) # 8-byte Folded Spill ; BE-P8-NEXT: stfd f28, 592(r1) # 8-byte Folded Spill
; BE-P8-NEXT: stfd f29, 600(r1) # 8-byte Folded Spill ; BE-P8-NEXT: stfd f29, 600(r1) # 8-byte Folded Spill
; BE-P8-NEXT: stfd f30, 608(r1) # 8-byte Folded Spill ; BE-P8-NEXT: stfd f30, 608(r1) # 8-byte Folded Spill
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Lines
; BE-32BIT-P10-NEXT: hashchk r0, -424(r1) ; BE-32BIT-P10-NEXT: hashchk r0, -424(r1)
; BE-32BIT-P10-NEXT: mtocrf 32, r12 ; BE-32BIT-P10-NEXT: mtocrf 32, r12
; BE-32BIT-P10-NEXT: mtocrf 16, r12 ; BE-32BIT-P10-NEXT: mtocrf 16, r12
; BE-32BIT-P10-NEXT: mtocrf 8, r12 ; BE-32BIT-P10-NEXT: mtocrf 8, r12
; BE-32BIT-P10-NEXT: blr ; BE-32BIT-P10-NEXT: blr
; ;
; BE-32BIT-P9-LABEL: spill: ; BE-32BIT-P9-LABEL: spill:
; BE-32BIT-P9: # %bb.0: # %entry ; BE-32BIT-P9: # %bb.0: # %entry
; BE-32BIT-P9-NEXT: mflr r0
; BE-32BIT-P9-NEXT: mfcr r12 ; BE-32BIT-P9-NEXT: mfcr r12
; BE-32BIT-P9-NEXT: stw r0, 8(r1) ; BE-32BIT-P9-NEXT: mflr r0
; BE-32BIT-P9-NEXT: hashst r0, -424(r1)
; BE-32BIT-P9-NEXT: stw r12, 4(r1) ; BE-32BIT-P9-NEXT: stw r12, 4(r1)
; BE-32BIT-P9-NEXT: stwu r1, -496(r1) ; BE-32BIT-P9-NEXT: stwu r1, -496(r1)
; BE-32BIT-P9-NEXT: lwz r4, 12(r3) ; BE-32BIT-P9-NEXT: stw r0, 504(r1)
; BE-32BIT-P9-NEXT: hashst r0, -424(r1)
; BE-32BIT-P9-NEXT: stw r13, 276(r1) # 4-byte Folded Spill ; BE-32BIT-P9-NEXT: stw r13, 276(r1) # 4-byte Folded Spill
; BE-32BIT-P9-NEXT: stw r14, 280(r1) # 4-byte Folded Spill
; BE-32BIT-P9-NEXT: stxv v20, 80(r1) # 16-byte Folded Spill ; BE-32BIT-P9-NEXT: stxv v20, 80(r1) # 16-byte Folded Spill
; BE-32BIT-P9-NEXT: stxv v21, 96(r1) # 16-byte Folded Spill ; BE-32BIT-P9-NEXT: stxv v21, 96(r1) # 16-byte Folded Spill
; BE-32BIT-P9-NEXT: lwz r4, 12(r3)
; BE-32BIT-P9-NEXT: stw r14, 280(r1) # 4-byte Folded Spill
; BE-32BIT-P9-NEXT: stxv v22, 112(r1) # 16-byte Folded Spill ; BE-32BIT-P9-NEXT: stxv v22, 112(r1) # 16-byte Folded Spill
; BE-32BIT-P9-NEXT: stw r15, 284(r1) # 4-byte Folded Spill ; BE-32BIT-P9-NEXT: stw r15, 284(r1) # 4-byte Folded Spill
; BE-32BIT-P9-NEXT: stw r16, 288(r1) # 4-byte Folded Spill
; BE-32BIT-P9-NEXT: stxv v23, 128(r1) # 16-byte Folded Spill ; BE-32BIT-P9-NEXT: stxv v23, 128(r1) # 16-byte Folded Spill
; BE-32BIT-P9-NEXT: stw r17, 292(r1) # 4-byte Folded Spill ; BE-32BIT-P9-NEXT: stw r16, 288(r1) # 4-byte Folded Spill
; BE-32BIT-P9-NEXT: stxv v24, 144(r1) # 16-byte Folded Spill ; BE-32BIT-P9-NEXT: stxv v24, 144(r1) # 16-byte Folded Spill
; BE-32BIT-P9-NEXT: stw r18, 296(r1) # 4-byte Folded Spill ; BE-32BIT-P9-NEXT: stw r17, 292(r1) # 4-byte Folded Spill
; BE-32BIT-P9-NEXT: stxv v25, 160(r1) # 16-byte Folded Spill ; BE-32BIT-P9-NEXT: stxv v25, 160(r1) # 16-byte Folded Spill
; BE-32BIT-P9-NEXT: stw r18, 296(r1) # 4-byte Folded Spill
; BE-32BIT-P9-NEXT: stw r19, 300(r1) # 4-byte Folded Spill ; BE-32BIT-P9-NEXT: stw r19, 300(r1) # 4-byte Folded Spill
; BE-32BIT-P9-NEXT: stw r20, 304(r1) # 4-byte Folded Spill
; BE-32BIT-P9-NEXT: stxv v26, 176(r1) # 16-byte Folded Spill ; BE-32BIT-P9-NEXT: stxv v26, 176(r1) # 16-byte Folded Spill
; BE-32BIT-P9-NEXT: stw r21, 308(r1) # 4-byte Folded Spill ; BE-32BIT-P9-NEXT: stw r20, 304(r1) # 4-byte Folded Spill
; BE-32BIT-P9-NEXT: stxv v27, 192(r1) # 16-byte Folded Spill ; BE-32BIT-P9-NEXT: stxv v27, 192(r1) # 16-byte Folded Spill
; BE-32BIT-P9-NEXT: stw r22, 312(r1) # 4-byte Folded Spill ; BE-32BIT-P9-NEXT: stw r21, 308(r1) # 4-byte Folded Spill
; BE-32BIT-P9-NEXT: stxv v28, 208(r1) # 16-byte Folded Spill ; BE-32BIT-P9-NEXT: stxv v28, 208(r1) # 16-byte Folded Spill
; BE-32BIT-P9-NEXT: stw r22, 312(r1) # 4-byte Folded Spill
; BE-32BIT-P9-NEXT: stw r23, 316(r1) # 4-byte Folded Spill ; BE-32BIT-P9-NEXT: stw r23, 316(r1) # 4-byte Folded Spill
; BE-32BIT-P9-NEXT: stw r24, 320(r1) # 4-byte Folded Spill
; BE-32BIT-P9-NEXT: stxv v29, 224(r1) # 16-byte Folded Spill ; BE-32BIT-P9-NEXT: stxv v29, 224(r1) # 16-byte Folded Spill
; BE-32BIT-P9-NEXT: stw r25, 324(r1) # 4-byte Folded Spill ; BE-32BIT-P9-NEXT: stw r24, 320(r1) # 4-byte Folded Spill
; BE-32BIT-P9-NEXT: stxv v30, 240(r1) # 16-byte Folded Spill ; BE-32BIT-P9-NEXT: stxv v30, 240(r1) # 16-byte Folded Spill
; BE-32BIT-P9-NEXT: stw r26, 328(r1) # 4-byte Folded Spill ; BE-32BIT-P9-NEXT: stw r25, 324(r1) # 4-byte Folded Spill
; BE-32BIT-P9-NEXT: stxv v31, 256(r1) # 16-byte Folded Spill ; BE-32BIT-P9-NEXT: stxv v31, 256(r1) # 16-byte Folded Spill
; BE-32BIT-P9-NEXT: stw r26, 328(r1) # 4-byte Folded Spill
; BE-32BIT-P9-NEXT: stw r27, 332(r1) # 4-byte Folded Spill ; BE-32BIT-P9-NEXT: stw r27, 332(r1) # 4-byte Folded Spill
; BE-32BIT-P9-NEXT: stw r28, 336(r1) # 4-byte Folded Spill ; BE-32BIT-P9-NEXT: stw r28, 336(r1) # 4-byte Folded Spill
; BE-32BIT-P9-NEXT: stw r29, 340(r1) # 4-byte Folded Spill ; BE-32BIT-P9-NEXT: stw r29, 340(r1) # 4-byte Folded Spill
; BE-32BIT-P9-NEXT: stw r30, 344(r1) # 4-byte Folded Spill ; BE-32BIT-P9-NEXT: stw r30, 344(r1) # 4-byte Folded Spill
; BE-32BIT-P9-NEXT: stw r31, 348(r1) # 4-byte Folded Spill ; BE-32BIT-P9-NEXT: stw r31, 348(r1) # 4-byte Folded Spill
; BE-32BIT-P9-NEXT: stfd f14, 352(r1) # 8-byte Folded Spill ; BE-32BIT-P9-NEXT: stfd f14, 352(r1) # 8-byte Folded Spill
; BE-32BIT-P9-NEXT: stfd f15, 360(r1) # 8-byte Folded Spill ; BE-32BIT-P9-NEXT: stfd f15, 360(r1) # 8-byte Folded Spill
; BE-32BIT-P9-NEXT: stfd f16, 368(r1) # 8-byte Folded Spill ; BE-32BIT-P9-NEXT: stfd f16, 368(r1) # 8-byte Folded Spill
▲ Show 20 Lines • Show All 81 Lines • ▼ Show 20 Lines
; BE-32BIT-P9-NEXT: mtocrf 16, r12 ; BE-32BIT-P9-NEXT: mtocrf 16, r12
; BE-32BIT-P9-NEXT: mtocrf 8, r12 ; BE-32BIT-P9-NEXT: mtocrf 8, r12
; BE-32BIT-P9-NEXT: blr ; BE-32BIT-P9-NEXT: blr
; ;
; BE-32BIT-P8-LABEL: spill: ; BE-32BIT-P8-LABEL: spill:
; BE-32BIT-P8: # %bb.0: # %entry ; BE-32BIT-P8: # %bb.0: # %entry
; BE-32BIT-P8-NEXT: mfcr r12 ; BE-32BIT-P8-NEXT: mfcr r12
; BE-32BIT-P8-NEXT: mflr r0 ; BE-32BIT-P8-NEXT: mflr r0
; BE-32BIT-P8-NEXT: stw r0, 8(r1)
; BE-32BIT-P8-NEXT: hashst r0, -424(r1)
; BE-32BIT-P8-NEXT: stw r12, 4(r1) ; BE-32BIT-P8-NEXT: stw r12, 4(r1)
; BE-32BIT-P8-NEXT: stwu r1, -496(r1) ; BE-32BIT-P8-NEXT: stwu r1, -496(r1)
; BE-32BIT-P8-NEXT: li r4, 80 ; BE-32BIT-P8-NEXT: li r4, 80
; BE-32BIT-P8-NEXT: stw r0, 504(r1)
; BE-32BIT-P8-NEXT: hashst r0, -424(r1)
; BE-32BIT-P8-NEXT: stw r13, 276(r1) # 4-byte Folded Spill ; BE-32BIT-P8-NEXT: stw r13, 276(r1) # 4-byte Folded Spill
; BE-32BIT-P8-NEXT: stw r14, 280(r1) # 4-byte Folded Spill
; BE-32BIT-P8-NEXT: stxvd2x v20, r1, r4 # 16-byte Folded Spill ; BE-32BIT-P8-NEXT: stxvd2x v20, r1, r4 # 16-byte Folded Spill
; BE-32BIT-P8-NEXT: li r4, 96 ; BE-32BIT-P8-NEXT: li r4, 96
; BE-32BIT-P8-NEXT: stw r15, 284(r1) # 4-byte Folded Spill ; BE-32BIT-P8-NEXT: stw r14, 280(r1) # 4-byte Folded Spill
; BE-32BIT-P8-NEXT: stxvd2x v21, r1, r4 # 16-byte Folded Spill ; BE-32BIT-P8-NEXT: stxvd2x v21, r1, r4 # 16-byte Folded Spill
; BE-32BIT-P8-NEXT: li r4, 112 ; BE-32BIT-P8-NEXT: li r4, 112
; BE-32BIT-P8-NEXT: stw r16, 288(r1) # 4-byte Folded Spill ; BE-32BIT-P8-NEXT: stw r15, 284(r1) # 4-byte Folded Spill
; BE-32BIT-P8-NEXT: stxvd2x v22, r1, r4 # 16-byte Folded Spill ; BE-32BIT-P8-NEXT: stxvd2x v22, r1, r4 # 16-byte Folded Spill
; BE-32BIT-P8-NEXT: li r4, 128 ; BE-32BIT-P8-NEXT: li r4, 128
; BE-32BIT-P8-NEXT: stw r17, 292(r1) # 4-byte Folded Spill ; BE-32BIT-P8-NEXT: stw r16, 288(r1) # 4-byte Folded Spill
; BE-32BIT-P8-NEXT: stxvd2x v23, r1, r4 # 16-byte Folded Spill ; BE-32BIT-P8-NEXT: stxvd2x v23, r1, r4 # 16-byte Folded Spill
; BE-32BIT-P8-NEXT: li r4, 144 ; BE-32BIT-P8-NEXT: li r4, 144
; BE-32BIT-P8-NEXT: stw r18, 296(r1) # 4-byte Folded Spill ; BE-32BIT-P8-NEXT: stw r17, 292(r1) # 4-byte Folded Spill
; BE-32BIT-P8-NEXT: stxvd2x v24, r1, r4 # 16-byte Folded Spill ; BE-32BIT-P8-NEXT: stxvd2x v24, r1, r4 # 16-byte Folded Spill
; BE-32BIT-P8-NEXT: li r4, 160 ; BE-32BIT-P8-NEXT: li r4, 160
; BE-32BIT-P8-NEXT: stw r19, 300(r1) # 4-byte Folded Spill ; BE-32BIT-P8-NEXT: stw r18, 296(r1) # 4-byte Folded Spill
; BE-32BIT-P8-NEXT: stxvd2x v25, r1, r4 # 16-byte Folded Spill ; BE-32BIT-P8-NEXT: stxvd2x v25, r1, r4 # 16-byte Folded Spill
; BE-32BIT-P8-NEXT: li r4, 176 ; BE-32BIT-P8-NEXT: li r4, 176
; BE-32BIT-P8-NEXT: stw r20, 304(r1) # 4-byte Folded Spill ; BE-32BIT-P8-NEXT: stw r19, 300(r1) # 4-byte Folded Spill
; BE-32BIT-P8-NEXT: stxvd2x v26, r1, r4 # 16-byte Folded Spill ; BE-32BIT-P8-NEXT: stxvd2x v26, r1, r4 # 16-byte Folded Spill
; BE-32BIT-P8-NEXT: li r4, 192 ; BE-32BIT-P8-NEXT: li r4, 192
; BE-32BIT-P8-NEXT: stw r21, 308(r1) # 4-byte Folded Spill ; BE-32BIT-P8-NEXT: stw r20, 304(r1) # 4-byte Folded Spill
; BE-32BIT-P8-NEXT: stxvd2x v27, r1, r4 # 16-byte Folded Spill ; BE-32BIT-P8-NEXT: stxvd2x v27, r1, r4 # 16-byte Folded Spill
; BE-32BIT-P8-NEXT: li r4, 208 ; BE-32BIT-P8-NEXT: li r4, 208
; BE-32BIT-P8-NEXT: stw r22, 312(r1) # 4-byte Folded Spill ; BE-32BIT-P8-NEXT: stw r21, 308(r1) # 4-byte Folded Spill
; BE-32BIT-P8-NEXT: stxvd2x v28, r1, r4 # 16-byte Folded Spill ; BE-32BIT-P8-NEXT: stxvd2x v28, r1, r4 # 16-byte Folded Spill
; BE-32BIT-P8-NEXT: li r4, 224 ; BE-32BIT-P8-NEXT: li r4, 224
; BE-32BIT-P8-NEXT: stw r23, 316(r1) # 4-byte Folded Spill ; BE-32BIT-P8-NEXT: stw r22, 312(r1) # 4-byte Folded Spill
; BE-32BIT-P8-NEXT: stxvd2x v29, r1, r4 # 16-byte Folded Spill ; BE-32BIT-P8-NEXT: stxvd2x v29, r1, r4 # 16-byte Folded Spill
; BE-32BIT-P8-NEXT: li r4, 240 ; BE-32BIT-P8-NEXT: li r4, 240
; BE-32BIT-P8-NEXT: stw r24, 320(r1) # 4-byte Folded Spill ; BE-32BIT-P8-NEXT: stw r23, 316(r1) # 4-byte Folded Spill
; BE-32BIT-P8-NEXT: stxvd2x v30, r1, r4 # 16-byte Folded Spill ; BE-32BIT-P8-NEXT: stxvd2x v30, r1, r4 # 16-byte Folded Spill
; BE-32BIT-P8-NEXT: li r4, 256 ; BE-32BIT-P8-NEXT: li r4, 256
; BE-32BIT-P8-NEXT: stw r25, 324(r1) # 4-byte Folded Spill ; BE-32BIT-P8-NEXT: stw r24, 320(r1) # 4-byte Folded Spill
; BE-32BIT-P8-NEXT: stxvd2x v31, r1, r4 # 16-byte Folded Spill ; BE-32BIT-P8-NEXT: stxvd2x v31, r1, r4 # 16-byte Folded Spill
; BE-32BIT-P8-NEXT: lwz r4, 12(r3) ; BE-32BIT-P8-NEXT: lwz r4, 12(r3)
; BE-32BIT-P8-NEXT: stw r25, 324(r1) # 4-byte Folded Spill
; BE-32BIT-P8-NEXT: stw r26, 328(r1) # 4-byte Folded Spill ; BE-32BIT-P8-NEXT: stw r26, 328(r1) # 4-byte Folded Spill
; BE-32BIT-P8-NEXT: stw r27, 332(r1) # 4-byte Folded Spill ; BE-32BIT-P8-NEXT: stw r27, 332(r1) # 4-byte Folded Spill
; BE-32BIT-P8-NEXT: stw r28, 336(r1) # 4-byte Folded Spill ; BE-32BIT-P8-NEXT: stw r28, 336(r1) # 4-byte Folded Spill
; BE-32BIT-P8-NEXT: stw r29, 340(r1) # 4-byte Folded Spill ; BE-32BIT-P8-NEXT: stw r29, 340(r1) # 4-byte Folded Spill
; BE-32BIT-P8-NEXT: stw r30, 344(r1) # 4-byte Folded Spill ; BE-32BIT-P8-NEXT: stw r30, 344(r1) # 4-byte Folded Spill
; BE-32BIT-P8-NEXT: stw r31, 348(r1) # 4-byte Folded Spill ; BE-32BIT-P8-NEXT: stw r31, 348(r1) # 4-byte Folded Spill
; BE-32BIT-P8-NEXT: stfd f14, 352(r1) # 8-byte Folded Spill ; BE-32BIT-P8-NEXT: stfd f14, 352(r1) # 8-byte Folded Spill
; BE-32BIT-P8-NEXT: stfd f15, 360(r1) # 8-byte Folded Spill ; BE-32BIT-P8-NEXT: stfd f15, 360(r1) # 8-byte Folded Spill
▲ Show 20 Lines • Show All 219 Lines • ▼ Show 20 Lines
; BE-P10-PRIV-NEXT: hashchkp r0, -488(r1) ; BE-P10-PRIV-NEXT: hashchkp r0, -488(r1)
; BE-P10-PRIV-NEXT: mtocrf 32, r12 ; BE-P10-PRIV-NEXT: mtocrf 32, r12
; BE-P10-PRIV-NEXT: mtocrf 16, r12 ; BE-P10-PRIV-NEXT: mtocrf 16, r12
; BE-P10-PRIV-NEXT: mtocrf 8, r12 ; BE-P10-PRIV-NEXT: mtocrf 8, r12
; BE-P10-PRIV-NEXT: blr ; BE-P10-PRIV-NEXT: blr
; ;
; BE-P9-PRIV-LABEL: spill: ; BE-P9-PRIV-LABEL: spill:
; BE-P9-PRIV: # %bb.0: # %entry ; BE-P9-PRIV: # %bb.0: # %entry
; BE-P9-PRIV-NEXT: mflr r0
; BE-P9-PRIV-NEXT: mfcr r12 ; BE-P9-PRIV-NEXT: mfcr r12
; BE-P9-PRIV-NEXT: std r0, 16(r1) ; BE-P9-PRIV-NEXT: mflr r0
; BE-P9-PRIV-NEXT: hashstp r0, -488(r1)
; BE-P9-PRIV-NEXT: stw r12, 8(r1) ; BE-P9-PRIV-NEXT: stw r12, 8(r1)
; BE-P9-PRIV-NEXT: stdu r1, -624(r1) ; BE-P9-PRIV-NEXT: stdu r1, -624(r1)
; BE-P9-PRIV-NEXT: lwz r4, 12(r3) ; BE-P9-PRIV-NEXT: std r0, 640(r1)
; BE-P9-PRIV-NEXT: hashstp r0, -488(r1)
; BE-P9-PRIV-NEXT: std r14, 336(r1) # 8-byte Folded Spill ; BE-P9-PRIV-NEXT: std r14, 336(r1) # 8-byte Folded Spill
; BE-P9-PRIV-NEXT: std r15, 344(r1) # 8-byte Folded Spill
; BE-P9-PRIV-NEXT: stxv v20, 144(r1) # 16-byte Folded Spill ; BE-P9-PRIV-NEXT: stxv v20, 144(r1) # 16-byte Folded Spill
; BE-P9-PRIV-NEXT: stxv v21, 160(r1) # 16-byte Folded Spill ; BE-P9-PRIV-NEXT: stxv v21, 160(r1) # 16-byte Folded Spill
; BE-P9-PRIV-NEXT: lwz r4, 12(r3)
; BE-P9-PRIV-NEXT: std r15, 344(r1) # 8-byte Folded Spill
; BE-P9-PRIV-NEXT: stxv v22, 176(r1) # 16-byte Folded Spill ; BE-P9-PRIV-NEXT: stxv v22, 176(r1) # 16-byte Folded Spill
; BE-P9-PRIV-NEXT: std r16, 352(r1) # 8-byte Folded Spill ; BE-P9-PRIV-NEXT: std r16, 352(r1) # 8-byte Folded Spill
; BE-P9-PRIV-NEXT: std r17, 360(r1) # 8-byte Folded Spill
; BE-P9-PRIV-NEXT: stxv v23, 192(r1) # 16-byte Folded Spill ; BE-P9-PRIV-NEXT: stxv v23, 192(r1) # 16-byte Folded Spill
; BE-P9-PRIV-NEXT: std r18, 368(r1) # 8-byte Folded Spill ; BE-P9-PRIV-NEXT: std r17, 360(r1) # 8-byte Folded Spill
; BE-P9-PRIV-NEXT: stxv v24, 208(r1) # 16-byte Folded Spill ; BE-P9-PRIV-NEXT: stxv v24, 208(r1) # 16-byte Folded Spill
; BE-P9-PRIV-NEXT: std r19, 376(r1) # 8-byte Folded Spill ; BE-P9-PRIV-NEXT: std r18, 368(r1) # 8-byte Folded Spill
; BE-P9-PRIV-NEXT: stxv v25, 224(r1) # 16-byte Folded Spill ; BE-P9-PRIV-NEXT: stxv v25, 224(r1) # 16-byte Folded Spill
; BE-P9-PRIV-NEXT: std r19, 376(r1) # 8-byte Folded Spill
; BE-P9-PRIV-NEXT: std r20, 384(r1) # 8-byte Folded Spill ; BE-P9-PRIV-NEXT: std r20, 384(r1) # 8-byte Folded Spill
; BE-P9-PRIV-NEXT: std r21, 392(r1) # 8-byte Folded Spill
; BE-P9-PRIV-NEXT: stxv v26, 240(r1) # 16-byte Folded Spill ; BE-P9-PRIV-NEXT: stxv v26, 240(r1) # 16-byte Folded Spill
; BE-P9-PRIV-NEXT: std r22, 400(r1) # 8-byte Folded Spill ; BE-P9-PRIV-NEXT: std r21, 392(r1) # 8-byte Folded Spill
; BE-P9-PRIV-NEXT: stxv v27, 256(r1) # 16-byte Folded Spill ; BE-P9-PRIV-NEXT: stxv v27, 256(r1) # 16-byte Folded Spill
; BE-P9-PRIV-NEXT: std r23, 408(r1) # 8-byte Folded Spill ; BE-P9-PRIV-NEXT: std r22, 400(r1) # 8-byte Folded Spill
; BE-P9-PRIV-NEXT: stxv v28, 272(r1) # 16-byte Folded Spill ; BE-P9-PRIV-NEXT: stxv v28, 272(r1) # 16-byte Folded Spill
; BE-P9-PRIV-NEXT: std r23, 408(r1) # 8-byte Folded Spill
; BE-P9-PRIV-NEXT: std r24, 416(r1) # 8-byte Folded Spill ; BE-P9-PRIV-NEXT: std r24, 416(r1) # 8-byte Folded Spill
; BE-P9-PRIV-NEXT: std r25, 424(r1) # 8-byte Folded Spill
; BE-P9-PRIV-NEXT: stxv v29, 288(r1) # 16-byte Folded Spill ; BE-P9-PRIV-NEXT: stxv v29, 288(r1) # 16-byte Folded Spill
; BE-P9-PRIV-NEXT: std r26, 432(r1) # 8-byte Folded Spill ; BE-P9-PRIV-NEXT: std r25, 424(r1) # 8-byte Folded Spill
; BE-P9-PRIV-NEXT: stxv v30, 304(r1) # 16-byte Folded Spill ; BE-P9-PRIV-NEXT: stxv v30, 304(r1) # 16-byte Folded Spill
; BE-P9-PRIV-NEXT: std r27, 440(r1) # 8-byte Folded Spill ; BE-P9-PRIV-NEXT: std r26, 432(r1) # 8-byte Folded Spill
; BE-P9-PRIV-NEXT: stxv v31, 320(r1) # 16-byte Folded Spill ; BE-P9-PRIV-NEXT: stxv v31, 320(r1) # 16-byte Folded Spill
; BE-P9-PRIV-NEXT: std r27, 440(r1) # 8-byte Folded Spill
; BE-P9-PRIV-NEXT: std r28, 448(r1) # 8-byte Folded Spill ; BE-P9-PRIV-NEXT: std r28, 448(r1) # 8-byte Folded Spill
; BE-P9-PRIV-NEXT: std r29, 456(r1) # 8-byte Folded Spill ; BE-P9-PRIV-NEXT: std r29, 456(r1) # 8-byte Folded Spill
; BE-P9-PRIV-NEXT: std r30, 464(r1) # 8-byte Folded Spill ; BE-P9-PRIV-NEXT: std r30, 464(r1) # 8-byte Folded Spill
; BE-P9-PRIV-NEXT: std r31, 472(r1) # 8-byte Folded Spill ; BE-P9-PRIV-NEXT: std r31, 472(r1) # 8-byte Folded Spill
; BE-P9-PRIV-NEXT: stfd f14, 480(r1) # 8-byte Folded Spill ; BE-P9-PRIV-NEXT: stfd f14, 480(r1) # 8-byte Folded Spill
; BE-P9-PRIV-NEXT: stfd f15, 488(r1) # 8-byte Folded Spill ; BE-P9-PRIV-NEXT: stfd f15, 488(r1) # 8-byte Folded Spill
; BE-P9-PRIV-NEXT: stfd f16, 496(r1) # 8-byte Folded Spill ; BE-P9-PRIV-NEXT: stfd f16, 496(r1) # 8-byte Folded Spill
; BE-P9-PRIV-NEXT: stfd f17, 504(r1) # 8-byte Folded Spill ; BE-P9-PRIV-NEXT: stfd f17, 504(r1) # 8-byte Folded Spill
▲ Show 20 Lines • Show All 80 Lines • ▼ Show 20 Lines
; BE-P9-PRIV-NEXT: mtocrf 16, r12 ; BE-P9-PRIV-NEXT: mtocrf 16, r12
; BE-P9-PRIV-NEXT: mtocrf 8, r12 ; BE-P9-PRIV-NEXT: mtocrf 8, r12
; BE-P9-PRIV-NEXT: blr ; BE-P9-PRIV-NEXT: blr
; ;
; BE-P8-PRIV-LABEL: spill: ; BE-P8-PRIV-LABEL: spill:
; BE-P8-PRIV: # %bb.0: # %entry ; BE-P8-PRIV: # %bb.0: # %entry
; BE-P8-PRIV-NEXT: mfcr r12 ; BE-P8-PRIV-NEXT: mfcr r12
; BE-P8-PRIV-NEXT: mflr r0 ; BE-P8-PRIV-NEXT: mflr r0
; BE-P8-PRIV-NEXT: std r0, 16(r1)
; BE-P8-PRIV-NEXT: hashstp r0, -488(r1)
; BE-P8-PRIV-NEXT: stw r12, 8(r1) ; BE-P8-PRIV-NEXT: stw r12, 8(r1)
; BE-P8-PRIV-NEXT: stdu r1, -624(r1) ; BE-P8-PRIV-NEXT: stdu r1, -624(r1)
; BE-P8-PRIV-NEXT: li r4, 144 ; BE-P8-PRIV-NEXT: li r4, 144
; BE-P8-PRIV-NEXT: std r0, 640(r1)
; BE-P8-PRIV-NEXT: hashstp r0, -488(r1)
; BE-P8-PRIV-NEXT: std r14, 336(r1) # 8-byte Folded Spill ; BE-P8-PRIV-NEXT: std r14, 336(r1) # 8-byte Folded Spill
; BE-P8-PRIV-NEXT: std r15, 344(r1) # 8-byte Folded Spill ; BE-P8-PRIV-NEXT: std r15, 344(r1) # 8-byte Folded Spill
; BE-P8-PRIV-NEXT: std r16, 352(r1) # 8-byte Folded Spill ; BE-P8-PRIV-NEXT: std r16, 352(r1) # 8-byte Folded Spill
; BE-P8-PRIV-NEXT: std r17, 360(r1) # 8-byte Folded Spill
; BE-P8-PRIV-NEXT: stxvd2x v20, r1, r4 # 16-byte Folded Spill ; BE-P8-PRIV-NEXT: stxvd2x v20, r1, r4 # 16-byte Folded Spill
; BE-P8-PRIV-NEXT: li r4, 160 ; BE-P8-PRIV-NEXT: li r4, 160
; BE-P8-PRIV-NEXT: std r17, 360(r1) # 8-byte Folded Spill
; BE-P8-PRIV-NEXT: std r18, 368(r1) # 8-byte Folded Spill ; BE-P8-PRIV-NEXT: std r18, 368(r1) # 8-byte Folded Spill
; BE-P8-PRIV-NEXT: std r19, 376(r1) # 8-byte Folded Spill ; BE-P8-PRIV-NEXT: std r19, 376(r1) # 8-byte Folded Spill
; BE-P8-PRIV-NEXT: std r20, 384(r1) # 8-byte Folded Spill ; BE-P8-PRIV-NEXT: std r20, 384(r1) # 8-byte Folded Spill
; BE-P8-PRIV-NEXT: std r21, 392(r1) # 8-byte Folded Spill
; BE-P8-PRIV-NEXT: stxvd2x v21, r1, r4 # 16-byte Folded Spill ; BE-P8-PRIV-NEXT: stxvd2x v21, r1, r4 # 16-byte Folded Spill
; BE-P8-PRIV-NEXT: li r4, 176 ; BE-P8-PRIV-NEXT: li r4, 176
; BE-P8-PRIV-NEXT: std r21, 392(r1) # 8-byte Folded Spill
; BE-P8-PRIV-NEXT: std r22, 400(r1) # 8-byte Folded Spill ; BE-P8-PRIV-NEXT: std r22, 400(r1) # 8-byte Folded Spill
; BE-P8-PRIV-NEXT: std r23, 408(r1) # 8-byte Folded Spill ; BE-P8-PRIV-NEXT: std r23, 408(r1) # 8-byte Folded Spill
; BE-P8-PRIV-NEXT: std r24, 416(r1) # 8-byte Folded Spill ; BE-P8-PRIV-NEXT: std r24, 416(r1) # 8-byte Folded Spill
; BE-P8-PRIV-NEXT: std r25, 424(r1) # 8-byte Folded Spill ; BE-P8-PRIV-NEXT: std r25, 424(r1) # 8-byte Folded Spill
; BE-P8-PRIV-NEXT: std r26, 432(r1) # 8-byte Folded Spill ; BE-P8-PRIV-NEXT: std r26, 432(r1) # 8-byte Folded Spill
; BE-P8-PRIV-NEXT: std r27, 440(r1) # 8-byte Folded Spill ; BE-P8-PRIV-NEXT: std r27, 440(r1) # 8-byte Folded Spill
; BE-P8-PRIV-NEXT: std r28, 448(r1) # 8-byte Folded Spill ; BE-P8-PRIV-NEXT: std r28, 448(r1) # 8-byte Folded Spill
; BE-P8-PRIV-NEXT: std r29, 456(r1) # 8-byte Folded Spill ; BE-P8-PRIV-NEXT: std r29, 456(r1) # 8-byte Folded Spill
; BE-P8-PRIV-NEXT: std r30, 464(r1) # 8-byte Folded Spill ; BE-P8-PRIV-NEXT: std r30, 464(r1) # 8-byte Folded Spill
; BE-P8-PRIV-NEXT: std r31, 472(r1) # 8-byte Folded Spill ; BE-P8-PRIV-NEXT: std r31, 472(r1) # 8-byte Folded Spill
; BE-P8-PRIV-NEXT: std r3, 120(r1) # 8-byte Folded Spill ; BE-P8-PRIV-NEXT: std r3, 120(r1) # 8-byte Folded Spill
; BE-P8-PRIV-NEXT: stxvd2x v22, r1, r4 # 16-byte Folded Spill ; BE-P8-PRIV-NEXT: stxvd2x v22, r1, r4 # 16-byte Folded Spill
; BE-P8-PRIV-NEXT: li r4, 192 ; BE-P8-PRIV-NEXT: li r4, 192
; BE-P8-PRIV-NEXT: stfd f14, 480(r1) # 8-byte Folded Spill
; BE-P8-PRIV-NEXT: stxvd2x v23, r1, r4 # 16-byte Folded Spill ; BE-P8-PRIV-NEXT: stxvd2x v23, r1, r4 # 16-byte Folded Spill
; BE-P8-PRIV-NEXT: li r4, 208 ; BE-P8-PRIV-NEXT: li r4, 208
; BE-P8-PRIV-NEXT: stfd f14, 480(r1) # 8-byte Folded Spill ; BE-P8-PRIV-NEXT: stfd f15, 488(r1) # 8-byte Folded Spill
; BE-P8-PRIV-NEXT: stxvd2x v24, r1, r4 # 16-byte Folded Spill ; BE-P8-PRIV-NEXT: stxvd2x v24, r1, r4 # 16-byte Folded Spill
; BE-P8-PRIV-NEXT: li r4, 224 ; BE-P8-PRIV-NEXT: li r4, 224
; BE-P8-PRIV-NEXT: stfd f15, 488(r1) # 8-byte Folded Spill ; BE-P8-PRIV-NEXT: stfd f16, 496(r1) # 8-byte Folded Spill
; BE-P8-PRIV-NEXT: stxvd2x v25, r1, r4 # 16-byte Folded Spill ; BE-P8-PRIV-NEXT: stxvd2x v25, r1, r4 # 16-byte Folded Spill
; BE-P8-PRIV-NEXT: li r4, 240 ; BE-P8-PRIV-NEXT: li r4, 240
; BE-P8-PRIV-NEXT: stfd f16, 496(r1) # 8-byte Folded Spill ; BE-P8-PRIV-NEXT: stfd f17, 504(r1) # 8-byte Folded Spill
; BE-P8-PRIV-NEXT: stxvd2x v26, r1, r4 # 16-byte Folded Spill ; BE-P8-PRIV-NEXT: stxvd2x v26, r1, r4 # 16-byte Folded Spill
; BE-P8-PRIV-NEXT: li r4, 256 ; BE-P8-PRIV-NEXT: li r4, 256
; BE-P8-PRIV-NEXT: stfd f17, 504(r1) # 8-byte Folded Spill ; BE-P8-PRIV-NEXT: stfd f18, 512(r1) # 8-byte Folded Spill
; BE-P8-PRIV-NEXT: stxvd2x v27, r1, r4 # 16-byte Folded Spill ; BE-P8-PRIV-NEXT: stxvd2x v27, r1, r4 # 16-byte Folded Spill
; BE-P8-PRIV-NEXT: li r4, 272 ; BE-P8-PRIV-NEXT: li r4, 272
; BE-P8-PRIV-NEXT: stfd f18, 512(r1) # 8-byte Folded Spill ; BE-P8-PRIV-NEXT: stfd f19, 520(r1) # 8-byte Folded Spill
; BE-P8-PRIV-NEXT: stxvd2x v28, r1, r4 # 16-byte Folded Spill ; BE-P8-PRIV-NEXT: stxvd2x v28, r1, r4 # 16-byte Folded Spill
; BE-P8-PRIV-NEXT: li r4, 288 ; BE-P8-PRIV-NEXT: li r4, 288
; BE-P8-PRIV-NEXT: stfd f19, 520(r1) # 8-byte Folded Spill ; BE-P8-PRIV-NEXT: stfd f20, 528(r1) # 8-byte Folded Spill
; BE-P8-PRIV-NEXT: stxvd2x v29, r1, r4 # 16-byte Folded Spill ; BE-P8-PRIV-NEXT: stxvd2x v29, r1, r4 # 16-byte Folded Spill
; BE-P8-PRIV-NEXT: li r4, 304 ; BE-P8-PRIV-NEXT: li r4, 304
; BE-P8-PRIV-NEXT: stfd f20, 528(r1) # 8-byte Folded Spill ; BE-P8-PRIV-NEXT: stfd f21, 536(r1) # 8-byte Folded Spill
; BE-P8-PRIV-NEXT: stxvd2x v30, r1, r4 # 16-byte Folded Spill ; BE-P8-PRIV-NEXT: stxvd2x v30, r1, r4 # 16-byte Folded Spill
; BE-P8-PRIV-NEXT: li r4, 320 ; BE-P8-PRIV-NEXT: li r4, 320
; BE-P8-PRIV-NEXT: stfd f21, 536(r1) # 8-byte Folded Spill ; BE-P8-PRIV-NEXT: stfd f22, 544(r1) # 8-byte Folded Spill
; BE-P8-PRIV-NEXT: stxvd2x v31, r1, r4 # 16-byte Folded Spill ; BE-P8-PRIV-NEXT: stxvd2x v31, r1, r4 # 16-byte Folded Spill
; BE-P8-PRIV-NEXT: lwz r4, 12(r3) ; BE-P8-PRIV-NEXT: lwz r4, 12(r3)
; BE-P8-PRIV-NEXT: stfd f22, 544(r1) # 8-byte Folded Spill
; BE-P8-PRIV-NEXT: stfd f23, 552(r1) # 8-byte Folded Spill ; BE-P8-PRIV-NEXT: stfd f23, 552(r1) # 8-byte Folded Spill
; BE-P8-PRIV-NEXT: stfd f24, 560(r1) # 8-byte Folded Spill ; BE-P8-PRIV-NEXT: stfd f24, 560(r1) # 8-byte Folded Spill
; BE-P8-PRIV-NEXT: stfd f25, 568(r1) # 8-byte Folded Spill ; BE-P8-PRIV-NEXT: stfd f25, 568(r1) # 8-byte Folded Spill
; BE-P8-PRIV-NEXT: stfd f26, 576(r1) # 8-byte Folded Spill ; BE-P8-PRIV-NEXT: stfd f26, 576(r1) # 8-byte Folded Spill
; BE-P8-PRIV-NEXT: stfd f27, 584(r1) # 8-byte Folded Spill ; BE-P8-PRIV-NEXT: stfd f27, 584(r1) # 8-byte Folded Spill
; BE-P8-PRIV-NEXT: stfd f28, 592(r1) # 8-byte Folded Spill ; BE-P8-PRIV-NEXT: stfd f28, 592(r1) # 8-byte Folded Spill
; BE-P8-PRIV-NEXT: stfd f29, 600(r1) # 8-byte Folded Spill ; BE-P8-PRIV-NEXT: stfd f29, 600(r1) # 8-byte Folded Spill
; BE-P8-PRIV-NEXT: stfd f30, 608(r1) # 8-byte Folded Spill ; BE-P8-PRIV-NEXT: stfd f30, 608(r1) # 8-byte Folded Spill
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Lines
; BE-32BIT-P10-PRIV-NEXT: hashchkp r0, -424(r1) ; BE-32BIT-P10-PRIV-NEXT: hashchkp r0, -424(r1)
; BE-32BIT-P10-PRIV-NEXT: mtocrf 32, r12 ; BE-32BIT-P10-PRIV-NEXT: mtocrf 32, r12
; BE-32BIT-P10-PRIV-NEXT: mtocrf 16, r12 ; BE-32BIT-P10-PRIV-NEXT: mtocrf 16, r12
; BE-32BIT-P10-PRIV-NEXT: mtocrf 8, r12 ; BE-32BIT-P10-PRIV-NEXT: mtocrf 8, r12
; BE-32BIT-P10-PRIV-NEXT: blr ; BE-32BIT-P10-PRIV-NEXT: blr
; ;
; BE-32BIT-P9-PRIV-LABEL: spill: ; BE-32BIT-P9-PRIV-LABEL: spill:
; BE-32BIT-P9-PRIV: # %bb.0: # %entry ; BE-32BIT-P9-PRIV: # %bb.0: # %entry
; BE-32BIT-P9-PRIV-NEXT: mflr r0
; BE-32BIT-P9-PRIV-NEXT: mfcr r12 ; BE-32BIT-P9-PRIV-NEXT: mfcr r12
; BE-32BIT-P9-PRIV-NEXT: stw r0, 8(r1) ; BE-32BIT-P9-PRIV-NEXT: mflr r0
; BE-32BIT-P9-PRIV-NEXT: hashstp r0, -424(r1)
; BE-32BIT-P9-PRIV-NEXT: stw r12, 4(r1) ; BE-32BIT-P9-PRIV-NEXT: stw r12, 4(r1)
; BE-32BIT-P9-PRIV-NEXT: stwu r1, -496(r1) ; BE-32BIT-P9-PRIV-NEXT: stwu r1, -496(r1)
; BE-32BIT-P9-PRIV-NEXT: lwz r4, 12(r3) ; BE-32BIT-P9-PRIV-NEXT: stw r0, 504(r1)
; BE-32BIT-P9-PRIV-NEXT: hashstp r0, -424(r1)
; BE-32BIT-P9-PRIV-NEXT: stw r13, 276(r1) # 4-byte Folded Spill ; BE-32BIT-P9-PRIV-NEXT: stw r13, 276(r1) # 4-byte Folded Spill
; BE-32BIT-P9-PRIV-NEXT: stw r14, 280(r1) # 4-byte Folded Spill
; BE-32BIT-P9-PRIV-NEXT: stxv v20, 80(r1) # 16-byte Folded Spill ; BE-32BIT-P9-PRIV-NEXT: stxv v20, 80(r1) # 16-byte Folded Spill
; BE-32BIT-P9-PRIV-NEXT: stxv v21, 96(r1) # 16-byte Folded Spill ; BE-32BIT-P9-PRIV-NEXT: stxv v21, 96(r1) # 16-byte Folded Spill
; BE-32BIT-P9-PRIV-NEXT: lwz r4, 12(r3)
; BE-32BIT-P9-PRIV-NEXT: stw r14, 280(r1) # 4-byte Folded Spill
; BE-32BIT-P9-PRIV-NEXT: stxv v22, 112(r1) # 16-byte Folded Spill ; BE-32BIT-P9-PRIV-NEXT: stxv v22, 112(r1) # 16-byte Folded Spill
; BE-32BIT-P9-PRIV-NEXT: stw r15, 284(r1) # 4-byte Folded Spill ; BE-32BIT-P9-PRIV-NEXT: stw r15, 284(r1) # 4-byte Folded Spill
; BE-32BIT-P9-PRIV-NEXT: stw r16, 288(r1) # 4-byte Folded Spill
; BE-32BIT-P9-PRIV-NEXT: stxv v23, 128(r1) # 16-byte Folded Spill ; BE-32BIT-P9-PRIV-NEXT: stxv v23, 128(r1) # 16-byte Folded Spill
; BE-32BIT-P9-PRIV-NEXT: stw r17, 292(r1) # 4-byte Folded Spill ; BE-32BIT-P9-PRIV-NEXT: stw r16, 288(r1) # 4-byte Folded Spill
; BE-32BIT-P9-PRIV-NEXT: stxv v24, 144(r1) # 16-byte Folded Spill ; BE-32BIT-P9-PRIV-NEXT: stxv v24, 144(r1) # 16-byte Folded Spill
; BE-32BIT-P9-PRIV-NEXT: stw r18, 296(r1) # 4-byte Folded Spill ; BE-32BIT-P9-PRIV-NEXT: stw r17, 292(r1) # 4-byte Folded Spill
; BE-32BIT-P9-PRIV-NEXT: stxv v25, 160(r1) # 16-byte Folded Spill ; BE-32BIT-P9-PRIV-NEXT: stxv v25, 160(r1) # 16-byte Folded Spill
; BE-32BIT-P9-PRIV-NEXT: stw r18, 296(r1) # 4-byte Folded Spill
; BE-32BIT-P9-PRIV-NEXT: stw r19, 300(r1) # 4-byte Folded Spill ; BE-32BIT-P9-PRIV-NEXT: stw r19, 300(r1) # 4-byte Folded Spill
; BE-32BIT-P9-PRIV-NEXT: stw r20, 304(r1) # 4-byte Folded Spill
; BE-32BIT-P9-PRIV-NEXT: stxv v26, 176(r1) # 16-byte Folded Spill ; BE-32BIT-P9-PRIV-NEXT: stxv v26, 176(r1) # 16-byte Folded Spill
; BE-32BIT-P9-PRIV-NEXT: stw r21, 308(r1) # 4-byte Folded Spill ; BE-32BIT-P9-PRIV-NEXT: stw r20, 304(r1) # 4-byte Folded Spill
; BE-32BIT-P9-PRIV-NEXT: stxv v27, 192(r1) # 16-byte Folded Spill ; BE-32BIT-P9-PRIV-NEXT: stxv v27, 192(r1) # 16-byte Folded Spill
; BE-32BIT-P9-PRIV-NEXT: stw r22, 312(r1) # 4-byte Folded Spill ; BE-32BIT-P9-PRIV-NEXT: stw r21, 308(r1) # 4-byte Folded Spill
; BE-32BIT-P9-PRIV-NEXT: stxv v28, 208(r1) # 16-byte Folded Spill ; BE-32BIT-P9-PRIV-NEXT: stxv v28, 208(r1) # 16-byte Folded Spill
; BE-32BIT-P9-PRIV-NEXT: stw r22, 312(r1) # 4-byte Folded Spill
; BE-32BIT-P9-PRIV-NEXT: stw r23, 316(r1) # 4-byte Folded Spill ; BE-32BIT-P9-PRIV-NEXT: stw r23, 316(r1) # 4-byte Folded Spill
; BE-32BIT-P9-PRIV-NEXT: stw r24, 320(r1) # 4-byte Folded Spill
; BE-32BIT-P9-PRIV-NEXT: stxv v29, 224(r1) # 16-byte Folded Spill ; BE-32BIT-P9-PRIV-NEXT: stxv v29, 224(r1) # 16-byte Folded Spill
; BE-32BIT-P9-PRIV-NEXT: stw r25, 324(r1) # 4-byte Folded Spill ; BE-32BIT-P9-PRIV-NEXT: stw r24, 320(r1) # 4-byte Folded Spill
; BE-32BIT-P9-PRIV-NEXT: stxv v30, 240(r1) # 16-byte Folded Spill ; BE-32BIT-P9-PRIV-NEXT: stxv v30, 240(r1) # 16-byte Folded Spill
; BE-32BIT-P9-PRIV-NEXT: stw r26, 328(r1) # 4-byte Folded Spill ; BE-32BIT-P9-PRIV-NEXT: stw r25, 324(r1) # 4-byte Folded Spill
; BE-32BIT-P9-PRIV-NEXT: stxv v31, 256(r1) # 16-byte Folded Spill ; BE-32BIT-P9-PRIV-NEXT: stxv v31, 256(r1) # 16-byte Folded Spill
; BE-32BIT-P9-PRIV-NEXT: stw r26, 328(r1) # 4-byte Folded Spill
; BE-32BIT-P9-PRIV-NEXT: stw r27, 332(r1) # 4-byte Folded Spill ; BE-32BIT-P9-PRIV-NEXT: stw r27, 332(r1) # 4-byte Folded Spill
; BE-32BIT-P9-PRIV-NEXT: stw r28, 336(r1) # 4-byte Folded Spill ; BE-32BIT-P9-PRIV-NEXT: stw r28, 336(r1) # 4-byte Folded Spill
; BE-32BIT-P9-PRIV-NEXT: stw r29, 340(r1) # 4-byte Folded Spill ; BE-32BIT-P9-PRIV-NEXT: stw r29, 340(r1) # 4-byte Folded Spill
; BE-32BIT-P9-PRIV-NEXT: stw r30, 344(r1) # 4-byte Folded Spill ; BE-32BIT-P9-PRIV-NEXT: stw r30, 344(r1) # 4-byte Folded Spill
; BE-32BIT-P9-PRIV-NEXT: stw r31, 348(r1) # 4-byte Folded Spill ; BE-32BIT-P9-PRIV-NEXT: stw r31, 348(r1) # 4-byte Folded Spill
; BE-32BIT-P9-PRIV-NEXT: stfd f14, 352(r1) # 8-byte Folded Spill ; BE-32BIT-P9-PRIV-NEXT: stfd f14, 352(r1) # 8-byte Folded Spill
; BE-32BIT-P9-PRIV-NEXT: stfd f15, 360(r1) # 8-byte Folded Spill ; BE-32BIT-P9-PRIV-NEXT: stfd f15, 360(r1) # 8-byte Folded Spill
; BE-32BIT-P9-PRIV-NEXT: stfd f16, 368(r1) # 8-byte Folded Spill ; BE-32BIT-P9-PRIV-NEXT: stfd f16, 368(r1) # 8-byte Folded Spill
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; BE-32BIT-P9-PRIV-NEXT: mtocrf 16, r12 ; BE-32BIT-P9-PRIV-NEXT: mtocrf 16, r12
; BE-32BIT-P9-PRIV-NEXT: mtocrf 8, r12 ; BE-32BIT-P9-PRIV-NEXT: mtocrf 8, r12
; BE-32BIT-P9-PRIV-NEXT: blr ; BE-32BIT-P9-PRIV-NEXT: blr
; ;
; BE-32BIT-P8-PRIV-LABEL: spill: ; BE-32BIT-P8-PRIV-LABEL: spill:
; BE-32BIT-P8-PRIV: # %bb.0: # %entry ; BE-32BIT-P8-PRIV: # %bb.0: # %entry
; BE-32BIT-P8-PRIV-NEXT: mfcr r12 ; BE-32BIT-P8-PRIV-NEXT: mfcr r12
; BE-32BIT-P8-PRIV-NEXT: mflr r0 ; BE-32BIT-P8-PRIV-NEXT: mflr r0
; BE-32BIT-P8-PRIV-NEXT: stw r0, 8(r1)
; BE-32BIT-P8-PRIV-NEXT: hashstp r0, -424(r1)
; BE-32BIT-P8-PRIV-NEXT: stw r12, 4(r1) ; BE-32BIT-P8-PRIV-NEXT: stw r12, 4(r1)
; BE-32BIT-P8-PRIV-NEXT: stwu r1, -496(r1) ; BE-32BIT-P8-PRIV-NEXT: stwu r1, -496(r1)
; BE-32BIT-P8-PRIV-NEXT: li r4, 80 ; BE-32BIT-P8-PRIV-NEXT: li r4, 80
; BE-32BIT-P8-PRIV-NEXT: stw r0, 504(r1)
; BE-32BIT-P8-PRIV-NEXT: hashstp r0, -424(r1)
; BE-32BIT-P8-PRIV-NEXT: stw r13, 276(r1) # 4-byte Folded Spill ; BE-32BIT-P8-PRIV-NEXT: stw r13, 276(r1) # 4-byte Folded Spill
; BE-32BIT-P8-PRIV-NEXT: stw r14, 280(r1) # 4-byte Folded Spill
; BE-32BIT-P8-PRIV-NEXT: stxvd2x v20, r1, r4 # 16-byte Folded Spill ; BE-32BIT-P8-PRIV-NEXT: stxvd2x v20, r1, r4 # 16-byte Folded Spill
; BE-32BIT-P8-PRIV-NEXT: li r4, 96 ; BE-32BIT-P8-PRIV-NEXT: li r4, 96
; BE-32BIT-P8-PRIV-NEXT: stw r15, 284(r1) # 4-byte Folded Spill ; BE-32BIT-P8-PRIV-NEXT: stw r14, 280(r1) # 4-byte Folded Spill
; BE-32BIT-P8-PRIV-NEXT: stxvd2x v21, r1, r4 # 16-byte Folded Spill ; BE-32BIT-P8-PRIV-NEXT: stxvd2x v21, r1, r4 # 16-byte Folded Spill
; BE-32BIT-P8-PRIV-NEXT: li r4, 112 ; BE-32BIT-P8-PRIV-NEXT: li r4, 112
; BE-32BIT-P8-PRIV-NEXT: stw r16, 288(r1) # 4-byte Folded Spill ; BE-32BIT-P8-PRIV-NEXT: stw r15, 284(r1) # 4-byte Folded Spill
; BE-32BIT-P8-PRIV-NEXT: stxvd2x v22, r1, r4 # 16-byte Folded Spill ; BE-32BIT-P8-PRIV-NEXT: stxvd2x v22, r1, r4 # 16-byte Folded Spill
; BE-32BIT-P8-PRIV-NEXT: li r4, 128 ; BE-32BIT-P8-PRIV-NEXT: li r4, 128
; BE-32BIT-P8-PRIV-NEXT: stw r17, 292(r1) # 4-byte Folded Spill ; BE-32BIT-P8-PRIV-NEXT: stw r16, 288(r1) # 4-byte Folded Spill
; BE-32BIT-P8-PRIV-NEXT: stxvd2x v23, r1, r4 # 16-byte Folded Spill ; BE-32BIT-P8-PRIV-NEXT: stxvd2x v23, r1, r4 # 16-byte Folded Spill
; BE-32BIT-P8-PRIV-NEXT: li r4, 144 ; BE-32BIT-P8-PRIV-NEXT: li r4, 144
; BE-32BIT-P8-PRIV-NEXT: stw r18, 296(r1) # 4-byte Folded Spill ; BE-32BIT-P8-PRIV-NEXT: stw r17, 292(r1) # 4-byte Folded Spill
; BE-32BIT-P8-PRIV-NEXT: stxvd2x v24, r1, r4 # 16-byte Folded Spill ; BE-32BIT-P8-PRIV-NEXT: stxvd2x v24, r1, r4 # 16-byte Folded Spill
; BE-32BIT-P8-PRIV-NEXT: li r4, 160 ; BE-32BIT-P8-PRIV-NEXT: li r4, 160
; BE-32BIT-P8-PRIV-NEXT: stw r19, 300(r1) # 4-byte Folded Spill ; BE-32BIT-P8-PRIV-NEXT: stw r18, 296(r1) # 4-byte Folded Spill
; BE-32BIT-P8-PRIV-NEXT: stxvd2x v25, r1, r4 # 16-byte Folded Spill ; BE-32BIT-P8-PRIV-NEXT: stxvd2x v25, r1, r4 # 16-byte Folded Spill
; BE-32BIT-P8-PRIV-NEXT: li r4, 176 ; BE-32BIT-P8-PRIV-NEXT: li r4, 176
; BE-32BIT-P8-PRIV-NEXT: stw r20, 304(r1) # 4-byte Folded Spill ; BE-32BIT-P8-PRIV-NEXT: stw r19, 300(r1) # 4-byte Folded Spill
; BE-32BIT-P8-PRIV-NEXT: stxvd2x v26, r1, r4 # 16-byte Folded Spill ; BE-32BIT-P8-PRIV-NEXT: stxvd2x v26, r1, r4 # 16-byte Folded Spill
; BE-32BIT-P8-PRIV-NEXT: li r4, 192 ; BE-32BIT-P8-PRIV-NEXT: li r4, 192
; BE-32BIT-P8-PRIV-NEXT: stw r21, 308(r1) # 4-byte Folded Spill ; BE-32BIT-P8-PRIV-NEXT: stw r20, 304(r1) # 4-byte Folded Spill
; BE-32BIT-P8-PRIV-NEXT: stxvd2x v27, r1, r4 # 16-byte Folded Spill ; BE-32BIT-P8-PRIV-NEXT: stxvd2x v27, r1, r4 # 16-byte Folded Spill
; BE-32BIT-P8-PRIV-NEXT: li r4, 208 ; BE-32BIT-P8-PRIV-NEXT: li r4, 208
; BE-32BIT-P8-PRIV-NEXT: stw r22, 312(r1) # 4-byte Folded Spill ; BE-32BIT-P8-PRIV-NEXT: stw r21, 308(r1) # 4-byte Folded Spill
; BE-32BIT-P8-PRIV-NEXT: stxvd2x v28, r1, r4 # 16-byte Folded Spill ; BE-32BIT-P8-PRIV-NEXT: stxvd2x v28, r1, r4 # 16-byte Folded Spill
; BE-32BIT-P8-PRIV-NEXT: li r4, 224 ; BE-32BIT-P8-PRIV-NEXT: li r4, 224
; BE-32BIT-P8-PRIV-NEXT: stw r23, 316(r1) # 4-byte Folded Spill ; BE-32BIT-P8-PRIV-NEXT: stw r22, 312(r1) # 4-byte Folded Spill
; BE-32BIT-P8-PRIV-NEXT: stxvd2x v29, r1, r4 # 16-byte Folded Spill ; BE-32BIT-P8-PRIV-NEXT: stxvd2x v29, r1, r4 # 16-byte Folded Spill
; BE-32BIT-P8-PRIV-NEXT: li r4, 240 ; BE-32BIT-P8-PRIV-NEXT: li r4, 240
; BE-32BIT-P8-PRIV-NEXT: stw r24, 320(r1) # 4-byte Folded Spill ; BE-32BIT-P8-PRIV-NEXT: stw r23, 316(r1) # 4-byte Folded Spill
; BE-32BIT-P8-PRIV-NEXT: stxvd2x v30, r1, r4 # 16-byte Folded Spill ; BE-32BIT-P8-PRIV-NEXT: stxvd2x v30, r1, r4 # 16-byte Folded Spill
; BE-32BIT-P8-PRIV-NEXT: li r4, 256 ; BE-32BIT-P8-PRIV-NEXT: li r4, 256
; BE-32BIT-P8-PRIV-NEXT: stw r25, 324(r1) # 4-byte Folded Spill ; BE-32BIT-P8-PRIV-NEXT: stw r24, 320(r1) # 4-byte Folded Spill
; BE-32BIT-P8-PRIV-NEXT: stxvd2x v31, r1, r4 # 16-byte Folded Spill ; BE-32BIT-P8-PRIV-NEXT: stxvd2x v31, r1, r4 # 16-byte Folded Spill
; BE-32BIT-P8-PRIV-NEXT: lwz r4, 12(r3) ; BE-32BIT-P8-PRIV-NEXT: lwz r4, 12(r3)
; BE-32BIT-P8-PRIV-NEXT: stw r25, 324(r1) # 4-byte Folded Spill
; BE-32BIT-P8-PRIV-NEXT: stw r26, 328(r1) # 4-byte Folded Spill ; BE-32BIT-P8-PRIV-NEXT: stw r26, 328(r1) # 4-byte Folded Spill
; BE-32BIT-P8-PRIV-NEXT: stw r27, 332(r1) # 4-byte Folded Spill ; BE-32BIT-P8-PRIV-NEXT: stw r27, 332(r1) # 4-byte Folded Spill
; BE-32BIT-P8-PRIV-NEXT: stw r28, 336(r1) # 4-byte Folded Spill ; BE-32BIT-P8-PRIV-NEXT: stw r28, 336(r1) # 4-byte Folded Spill
; BE-32BIT-P8-PRIV-NEXT: stw r29, 340(r1) # 4-byte Folded Spill ; BE-32BIT-P8-PRIV-NEXT: stw r29, 340(r1) # 4-byte Folded Spill
; BE-32BIT-P8-PRIV-NEXT: stw r30, 344(r1) # 4-byte Folded Spill ; BE-32BIT-P8-PRIV-NEXT: stw r30, 344(r1) # 4-byte Folded Spill
; BE-32BIT-P8-PRIV-NEXT: stw r31, 348(r1) # 4-byte Folded Spill ; BE-32BIT-P8-PRIV-NEXT: stw r31, 348(r1) # 4-byte Folded Spill
; BE-32BIT-P8-PRIV-NEXT: stfd f14, 352(r1) # 8-byte Folded Spill ; BE-32BIT-P8-PRIV-NEXT: stfd f14, 352(r1) # 8-byte Folded Spill
; BE-32BIT-P8-PRIV-NEXT: stfd f15, 360(r1) # 8-byte Folded Spill ; BE-32BIT-P8-PRIV-NEXT: stfd f15, 360(r1) # 8-byte Folded Spill
▲ Show 20 Lines • Show All 140 Lines • ▼ Show 20 Lines
; BE-P10-NEXT: blr ; BE-P10-NEXT: blr
; ;
; BE-P9-LABEL: shrinkwrap: ; BE-P9-LABEL: shrinkwrap:
; BE-P9: # %bb.0: # %entry ; BE-P9: # %bb.0: # %entry
; BE-P9-NEXT: cmpldi r3, 0 ; BE-P9-NEXT: cmpldi r3, 0
; BE-P9-NEXT: beq cr0, L..BB2_2 ; BE-P9-NEXT: beq cr0, L..BB2_2
; BE-P9-NEXT: # %bb.1: # %if.end ; BE-P9-NEXT: # %bb.1: # %if.end
; BE-P9-NEXT: mflr r0 ; BE-P9-NEXT: mflr r0
; BE-P9-NEXT: std r0, 16(r1)
; BE-P9-NEXT: hashst r0, -16(r1)
; BE-P9-NEXT: stdu r1, -144(r1) ; BE-P9-NEXT: stdu r1, -144(r1)
; BE-P9-NEXT: std r0, 160(r1)
; BE-P9-NEXT: hashst r0, -16(r1)
; BE-P9-NEXT: std r31, 136(r1) # 8-byte Folded Spill ; BE-P9-NEXT: std r31, 136(r1) # 8-byte Folded Spill
; BE-P9-NEXT: mr r31, r3 ; BE-P9-NEXT: mr r31, r3
; BE-P9-NEXT: lwz r3, 12(r3) ; BE-P9-NEXT: lwz r3, 12(r3)
; BE-P9-NEXT: stw r3, 124(r1) ; BE-P9-NEXT: stw r3, 124(r1)
; BE-P9-NEXT: addi r3, r1, 124 ; BE-P9-NEXT: addi r3, r1, 124
; BE-P9-NEXT: bl .callee2[PR] ; BE-P9-NEXT: bl .callee2[PR]
; BE-P9-NEXT: nop ; BE-P9-NEXT: nop
; BE-P9-NEXT: lwz r4, 16(r31) ; BE-P9-NEXT: lwz r4, 16(r31)
Show All 10 Lines
; BE-P9-NEXT: blr ; BE-P9-NEXT: blr
; ;
; BE-P8-LABEL: shrinkwrap: ; BE-P8-LABEL: shrinkwrap:
; BE-P8: # %bb.0: # %entry ; BE-P8: # %bb.0: # %entry
; BE-P8-NEXT: cmpldi r3, 0 ; BE-P8-NEXT: cmpldi r3, 0
; BE-P8-NEXT: beq cr0, L..BB2_2 ; BE-P8-NEXT: beq cr0, L..BB2_2
; BE-P8-NEXT: # %bb.1: # %if.end ; BE-P8-NEXT: # %bb.1: # %if.end
; BE-P8-NEXT: mflr r0 ; BE-P8-NEXT: mflr r0
; BE-P8-NEXT: std r0, 16(r1)
; BE-P8-NEXT: hashst r0, -16(r1)
; BE-P8-NEXT: stdu r1, -144(r1) ; BE-P8-NEXT: stdu r1, -144(r1)
; BE-P8-NEXT: std r0, 160(r1)
; BE-P8-NEXT: hashst r0, -16(r1)
; BE-P8-NEXT: std r31, 136(r1) # 8-byte Folded Spill ; BE-P8-NEXT: std r31, 136(r1) # 8-byte Folded Spill
; BE-P8-NEXT: mr r31, r3 ; BE-P8-NEXT: mr r31, r3
; BE-P8-NEXT: lwz r3, 12(r3) ; BE-P8-NEXT: lwz r3, 12(r3)
; BE-P8-NEXT: stw r3, 124(r1) ; BE-P8-NEXT: stw r3, 124(r1)
; BE-P8-NEXT: addi r3, r1, 124 ; BE-P8-NEXT: addi r3, r1, 124
; BE-P8-NEXT: bl .callee2[PR] ; BE-P8-NEXT: bl .callee2[PR]
; BE-P8-NEXT: nop ; BE-P8-NEXT: nop
; BE-P8-NEXT: lwz r4, 16(r31) ; BE-P8-NEXT: lwz r4, 16(r31)
Show All 38 Lines
; BE-32BIT-P10-NEXT: blr ; BE-32BIT-P10-NEXT: blr
; ;
; BE-32BIT-P9-LABEL: shrinkwrap: ; BE-32BIT-P9-LABEL: shrinkwrap:
; BE-32BIT-P9: # %bb.0: # %entry ; BE-32BIT-P9: # %bb.0: # %entry
; BE-32BIT-P9-NEXT: cmplwi r3, 0 ; BE-32BIT-P9-NEXT: cmplwi r3, 0
; BE-32BIT-P9-NEXT: beq cr0, L..BB2_2 ; BE-32BIT-P9-NEXT: beq cr0, L..BB2_2
; BE-32BIT-P9-NEXT: # %bb.1: # %if.end ; BE-32BIT-P9-NEXT: # %bb.1: # %if.end
; BE-32BIT-P9-NEXT: mflr r0 ; BE-32BIT-P9-NEXT: mflr r0
; BE-32BIT-P9-NEXT: stw r0, 8(r1)
; BE-32BIT-P9-NEXT: hashst r0, -16(r1)
; BE-32BIT-P9-NEXT: stwu r1, -80(r1) ; BE-32BIT-P9-NEXT: stwu r1, -80(r1)
; BE-32BIT-P9-NEXT: stw r0, 88(r1)
; BE-32BIT-P9-NEXT: hashst r0, -16(r1)
; BE-32BIT-P9-NEXT: stw r31, 76(r1) # 4-byte Folded Spill ; BE-32BIT-P9-NEXT: stw r31, 76(r1) # 4-byte Folded Spill
; BE-32BIT-P9-NEXT: mr r31, r3 ; BE-32BIT-P9-NEXT: mr r31, r3
; BE-32BIT-P9-NEXT: lwz r3, 12(r3) ; BE-32BIT-P9-NEXT: lwz r3, 12(r3)
; BE-32BIT-P9-NEXT: stw r3, 60(r1) ; BE-32BIT-P9-NEXT: stw r3, 60(r1)
; BE-32BIT-P9-NEXT: addi r3, r1, 60 ; BE-32BIT-P9-NEXT: addi r3, r1, 60
; BE-32BIT-P9-NEXT: bl .callee2[PR] ; BE-32BIT-P9-NEXT: bl .callee2[PR]
; BE-32BIT-P9-NEXT: nop ; BE-32BIT-P9-NEXT: nop
; BE-32BIT-P9-NEXT: lwz r4, 16(r31) ; BE-32BIT-P9-NEXT: lwz r4, 16(r31)
Show All 9 Lines
; BE-32BIT-P9-NEXT: blr ; BE-32BIT-P9-NEXT: blr
; ;
; BE-32BIT-P8-LABEL: shrinkwrap: ; BE-32BIT-P8-LABEL: shrinkwrap:
; BE-32BIT-P8: # %bb.0: # %entry ; BE-32BIT-P8: # %bb.0: # %entry
; BE-32BIT-P8-NEXT: cmplwi r3, 0 ; BE-32BIT-P8-NEXT: cmplwi r3, 0
; BE-32BIT-P8-NEXT: beq cr0, L..BB2_2 ; BE-32BIT-P8-NEXT: beq cr0, L..BB2_2
; BE-32BIT-P8-NEXT: # %bb.1: # %if.end ; BE-32BIT-P8-NEXT: # %bb.1: # %if.end
; BE-32BIT-P8-NEXT: mflr r0 ; BE-32BIT-P8-NEXT: mflr r0
; BE-32BIT-P8-NEXT: stw r0, 8(r1)
; BE-32BIT-P8-NEXT: hashst r0, -16(r1)
; BE-32BIT-P8-NEXT: stwu r1, -80(r1) ; BE-32BIT-P8-NEXT: stwu r1, -80(r1)
; BE-32BIT-P8-NEXT: stw r0, 88(r1)
; BE-32BIT-P8-NEXT: hashst r0, -16(r1)
; BE-32BIT-P8-NEXT: stw r31, 76(r1) # 4-byte Folded Spill ; BE-32BIT-P8-NEXT: stw r31, 76(r1) # 4-byte Folded Spill
; BE-32BIT-P8-NEXT: mr r31, r3 ; BE-32BIT-P8-NEXT: mr r31, r3
; BE-32BIT-P8-NEXT: lwz r3, 12(r3) ; BE-32BIT-P8-NEXT: lwz r3, 12(r3)
; BE-32BIT-P8-NEXT: stw r3, 60(r1) ; BE-32BIT-P8-NEXT: stw r3, 60(r1)
; BE-32BIT-P8-NEXT: addi r3, r1, 60 ; BE-32BIT-P8-NEXT: addi r3, r1, 60
; BE-32BIT-P8-NEXT: bl .callee2[PR] ; BE-32BIT-P8-NEXT: bl .callee2[PR]
; BE-32BIT-P8-NEXT: nop ; BE-32BIT-P8-NEXT: nop
; BE-32BIT-P8-NEXT: lwz r4, 16(r31) ; BE-32BIT-P8-NEXT: lwz r4, 16(r31)
Show All 38 Lines
; BE-P10-PRIV-NEXT: blr ; BE-P10-PRIV-NEXT: blr
; ;
; BE-P9-PRIV-LABEL: shrinkwrap: ; BE-P9-PRIV-LABEL: shrinkwrap:
; BE-P9-PRIV: # %bb.0: # %entry ; BE-P9-PRIV: # %bb.0: # %entry
; BE-P9-PRIV-NEXT: cmpldi r3, 0 ; BE-P9-PRIV-NEXT: cmpldi r3, 0
; BE-P9-PRIV-NEXT: beq cr0, L..BB2_2 ; BE-P9-PRIV-NEXT: beq cr0, L..BB2_2
; BE-P9-PRIV-NEXT: # %bb.1: # %if.end ; BE-P9-PRIV-NEXT: # %bb.1: # %if.end
; BE-P9-PRIV-NEXT: mflr r0 ; BE-P9-PRIV-NEXT: mflr r0
; BE-P9-PRIV-NEXT: std r0, 16(r1)
; BE-P9-PRIV-NEXT: hashstp r0, -16(r1)
; BE-P9-PRIV-NEXT: stdu r1, -144(r1) ; BE-P9-PRIV-NEXT: stdu r1, -144(r1)
; BE-P9-PRIV-NEXT: std r0, 160(r1)
; BE-P9-PRIV-NEXT: hashstp r0, -16(r1)
; BE-P9-PRIV-NEXT: std r31, 136(r1) # 8-byte Folded Spill ; BE-P9-PRIV-NEXT: std r31, 136(r1) # 8-byte Folded Spill
; BE-P9-PRIV-NEXT: mr r31, r3 ; BE-P9-PRIV-NEXT: mr r31, r3
; BE-P9-PRIV-NEXT: lwz r3, 12(r3) ; BE-P9-PRIV-NEXT: lwz r3, 12(r3)
; BE-P9-PRIV-NEXT: stw r3, 124(r1) ; BE-P9-PRIV-NEXT: stw r3, 124(r1)
; BE-P9-PRIV-NEXT: addi r3, r1, 124 ; BE-P9-PRIV-NEXT: addi r3, r1, 124
; BE-P9-PRIV-NEXT: bl .callee2[PR] ; BE-P9-PRIV-NEXT: bl .callee2[PR]
; BE-P9-PRIV-NEXT: nop ; BE-P9-PRIV-NEXT: nop
; BE-P9-PRIV-NEXT: lwz r4, 16(r31) ; BE-P9-PRIV-NEXT: lwz r4, 16(r31)
Show All 10 Lines
; BE-P9-PRIV-NEXT: blr ; BE-P9-PRIV-NEXT: blr
; ;
; BE-P8-PRIV-LABEL: shrinkwrap: ; BE-P8-PRIV-LABEL: shrinkwrap:
; BE-P8-PRIV: # %bb.0: # %entry ; BE-P8-PRIV: # %bb.0: # %entry
; BE-P8-PRIV-NEXT: cmpldi r3, 0 ; BE-P8-PRIV-NEXT: cmpldi r3, 0
; BE-P8-PRIV-NEXT: beq cr0, L..BB2_2 ; BE-P8-PRIV-NEXT: beq cr0, L..BB2_2
; BE-P8-PRIV-NEXT: # %bb.1: # %if.end ; BE-P8-PRIV-NEXT: # %bb.1: # %if.end
; BE-P8-PRIV-NEXT: mflr r0 ; BE-P8-PRIV-NEXT: mflr r0
; BE-P8-PRIV-NEXT: std r0, 16(r1)
; BE-P8-PRIV-NEXT: hashstp r0, -16(r1)
; BE-P8-PRIV-NEXT: stdu r1, -144(r1) ; BE-P8-PRIV-NEXT: stdu r1, -144(r1)
; BE-P8-PRIV-NEXT: std r0, 160(r1)
; BE-P8-PRIV-NEXT: hashstp r0, -16(r1)
; BE-P8-PRIV-NEXT: std r31, 136(r1) # 8-byte Folded Spill ; BE-P8-PRIV-NEXT: std r31, 136(r1) # 8-byte Folded Spill
; BE-P8-PRIV-NEXT: mr r31, r3 ; BE-P8-PRIV-NEXT: mr r31, r3
; BE-P8-PRIV-NEXT: lwz r3, 12(r3) ; BE-P8-PRIV-NEXT: lwz r3, 12(r3)
; BE-P8-PRIV-NEXT: stw r3, 124(r1) ; BE-P8-PRIV-NEXT: stw r3, 124(r1)
; BE-P8-PRIV-NEXT: addi r3, r1, 124 ; BE-P8-PRIV-NEXT: addi r3, r1, 124
; BE-P8-PRIV-NEXT: bl .callee2[PR] ; BE-P8-PRIV-NEXT: bl .callee2[PR]
; BE-P8-PRIV-NEXT: nop ; BE-P8-PRIV-NEXT: nop
; BE-P8-PRIV-NEXT: lwz r4, 16(r31) ; BE-P8-PRIV-NEXT: lwz r4, 16(r31)
Show All 38 Lines
; BE-32BIT-P10-PRIV-NEXT: blr ; BE-32BIT-P10-PRIV-NEXT: blr
; ;
; BE-32BIT-P9-PRIV-LABEL: shrinkwrap: ; BE-32BIT-P9-PRIV-LABEL: shrinkwrap:
; BE-32BIT-P9-PRIV: # %bb.0: # %entry ; BE-32BIT-P9-PRIV: # %bb.0: # %entry
; BE-32BIT-P9-PRIV-NEXT: cmplwi r3, 0 ; BE-32BIT-P9-PRIV-NEXT: cmplwi r3, 0
; BE-32BIT-P9-PRIV-NEXT: beq cr0, L..BB2_2 ; BE-32BIT-P9-PRIV-NEXT: beq cr0, L..BB2_2
; BE-32BIT-P9-PRIV-NEXT: # %bb.1: # %if.end ; BE-32BIT-P9-PRIV-NEXT: # %bb.1: # %if.end
; BE-32BIT-P9-PRIV-NEXT: mflr r0 ; BE-32BIT-P9-PRIV-NEXT: mflr r0
; BE-32BIT-P9-PRIV-NEXT: stw r0, 8(r1)
; BE-32BIT-P9-PRIV-NEXT: hashstp r0, -16(r1)
; BE-32BIT-P9-PRIV-NEXT: stwu r1, -80(r1) ; BE-32BIT-P9-PRIV-NEXT: stwu r1, -80(r1)
; BE-32BIT-P9-PRIV-NEXT: stw r0, 88(r1)
; BE-32BIT-P9-PRIV-NEXT: hashstp r0, -16(r1)
; BE-32BIT-P9-PRIV-NEXT: stw r31, 76(r1) # 4-byte Folded Spill ; BE-32BIT-P9-PRIV-NEXT: stw r31, 76(r1) # 4-byte Folded Spill
; BE-32BIT-P9-PRIV-NEXT: mr r31, r3 ; BE-32BIT-P9-PRIV-NEXT: mr r31, r3
; BE-32BIT-P9-PRIV-NEXT: lwz r3, 12(r3) ; BE-32BIT-P9-PRIV-NEXT: lwz r3, 12(r3)
; BE-32BIT-P9-PRIV-NEXT: stw r3, 60(r1) ; BE-32BIT-P9-PRIV-NEXT: stw r3, 60(r1)
; BE-32BIT-P9-PRIV-NEXT: addi r3, r1, 60 ; BE-32BIT-P9-PRIV-NEXT: addi r3, r1, 60
; BE-32BIT-P9-PRIV-NEXT: bl .callee2[PR] ; BE-32BIT-P9-PRIV-NEXT: bl .callee2[PR]
; BE-32BIT-P9-PRIV-NEXT: nop ; BE-32BIT-P9-PRIV-NEXT: nop
; BE-32BIT-P9-PRIV-NEXT: lwz r4, 16(r31) ; BE-32BIT-P9-PRIV-NEXT: lwz r4, 16(r31)
Show All 9 Lines
; BE-32BIT-P9-PRIV-NEXT: blr ; BE-32BIT-P9-PRIV-NEXT: blr
; ;
; BE-32BIT-P8-PRIV-LABEL: shrinkwrap: ; BE-32BIT-P8-PRIV-LABEL: shrinkwrap:
; BE-32BIT-P8-PRIV: # %bb.0: # %entry ; BE-32BIT-P8-PRIV: # %bb.0: # %entry
; BE-32BIT-P8-PRIV-NEXT: cmplwi r3, 0 ; BE-32BIT-P8-PRIV-NEXT: cmplwi r3, 0
; BE-32BIT-P8-PRIV-NEXT: beq cr0, L..BB2_2 ; BE-32BIT-P8-PRIV-NEXT: beq cr0, L..BB2_2
; BE-32BIT-P8-PRIV-NEXT: # %bb.1: # %if.end ; BE-32BIT-P8-PRIV-NEXT: # %bb.1: # %if.end
; BE-32BIT-P8-PRIV-NEXT: mflr r0 ; BE-32BIT-P8-PRIV-NEXT: mflr r0
; BE-32BIT-P8-PRIV-NEXT: stw r0, 8(r1)
; BE-32BIT-P8-PRIV-NEXT: hashstp r0, -16(r1)
; BE-32BIT-P8-PRIV-NEXT: stwu r1, -80(r1) ; BE-32BIT-P8-PRIV-NEXT: stwu r1, -80(r1)
; BE-32BIT-P8-PRIV-NEXT: stw r0, 88(r1)
; BE-32BIT-P8-PRIV-NEXT: hashstp r0, -16(r1)
; BE-32BIT-P8-PRIV-NEXT: stw r31, 76(r1) # 4-byte Folded Spill ; BE-32BIT-P8-PRIV-NEXT: stw r31, 76(r1) # 4-byte Folded Spill
; BE-32BIT-P8-PRIV-NEXT: mr r31, r3 ; BE-32BIT-P8-PRIV-NEXT: mr r31, r3
; BE-32BIT-P8-PRIV-NEXT: lwz r3, 12(r3) ; BE-32BIT-P8-PRIV-NEXT: lwz r3, 12(r3)
; BE-32BIT-P8-PRIV-NEXT: stw r3, 60(r1) ; BE-32BIT-P8-PRIV-NEXT: stw r3, 60(r1)
; BE-32BIT-P8-PRIV-NEXT: addi r3, r1, 60 ; BE-32BIT-P8-PRIV-NEXT: addi r3, r1, 60
; BE-32BIT-P8-PRIV-NEXT: bl .callee2[PR] ; BE-32BIT-P8-PRIV-NEXT: bl .callee2[PR]
; BE-32BIT-P8-PRIV-NEXT: nop ; BE-32BIT-P8-PRIV-NEXT: nop
; BE-32BIT-P8-PRIV-NEXT: lwz r4, 16(r31) ; BE-32BIT-P8-PRIV-NEXT: lwz r4, 16(r31)
▲ Show 20 Lines • Show All 575 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/ppc64-rop-protection.ll

Show First 20 Lines • Show All 78 Lines • ▼ Show 20 Lines
; LE-P10-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; LE-P10-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; LE-P10-NEXT: mtlr r0 ; LE-P10-NEXT: mtlr r0
; LE-P10-NEXT: blr ; LE-P10-NEXT: blr
; ;
; LE-P9-LABEL: caller: ; LE-P9-LABEL: caller:
; LE-P9: # %bb.0: # %entry ; LE-P9: # %bb.0: # %entry
; LE-P9-NEXT: mflr r0 ; LE-P9-NEXT: mflr r0
; LE-P9-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; LE-P9-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; LE-P9-NEXT: std r0, 16(r1)
; LE-P9-NEXT: hashst r0, -24(r1)
; LE-P9-NEXT: stdu r1, -64(r1) ; LE-P9-NEXT: stdu r1, -64(r1)
; LE-P9-NEXT: std r0, 80(r1)
; LE-P9-NEXT: hashst r0, -24(r1)
; LE-P9-NEXT: mr r30, r4 ; LE-P9-NEXT: mr r30, r4
; LE-P9-NEXT: bl callee ; LE-P9-NEXT: bl callee
; LE-P9-NEXT: nop ; LE-P9-NEXT: nop
; LE-P9-NEXT: add r3, r3, r30 ; LE-P9-NEXT: add r3, r3, r30
; LE-P9-NEXT: clrldi r3, r3, 32 ; LE-P9-NEXT: clrldi r3, r3, 32
; LE-P9-NEXT: addi r1, r1, 64 ; LE-P9-NEXT: addi r1, r1, 64
; LE-P9-NEXT: ld r0, 16(r1) ; LE-P9-NEXT: ld r0, 16(r1)
; LE-P9-NEXT: mtlr r0 ; LE-P9-NEXT: mtlr r0
; LE-P9-NEXT: hashchk r0, -24(r1) ; LE-P9-NEXT: hashchk r0, -24(r1)
; LE-P9-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; LE-P9-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; LE-P9-NEXT: blr ; LE-P9-NEXT: blr
; ;
; LE-P8-LABEL: caller: ; LE-P8-LABEL: caller:
; LE-P8: # %bb.0: # %entry ; LE-P8: # %bb.0: # %entry
; LE-P8-NEXT: mflr r0 ; LE-P8-NEXT: mflr r0
; LE-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; LE-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; LE-P8-NEXT: std r0, 16(r1)
; LE-P8-NEXT: hashst r0, -24(r1)
; LE-P8-NEXT: stdu r1, -64(r1) ; LE-P8-NEXT: stdu r1, -64(r1)
; LE-P8-NEXT: std r0, 80(r1)
; LE-P8-NEXT: hashst r0, -24(r1)
; LE-P8-NEXT: mr r30, r4 ; LE-P8-NEXT: mr r30, r4
; LE-P8-NEXT: bl callee ; LE-P8-NEXT: bl callee
; LE-P8-NEXT: nop ; LE-P8-NEXT: nop
; LE-P8-NEXT: add r3, r3, r30 ; LE-P8-NEXT: add r3, r3, r30
; LE-P8-NEXT: clrldi r3, r3, 32 ; LE-P8-NEXT: clrldi r3, r3, 32
; LE-P8-NEXT: addi r1, r1, 64 ; LE-P8-NEXT: addi r1, r1, 64
; LE-P8-NEXT: ld r0, 16(r1) ; LE-P8-NEXT: ld r0, 16(r1)
; LE-P8-NEXT: hashchk r0, -24(r1) ; LE-P8-NEXT: hashchk r0, -24(r1)
Show All 22 Lines
; LE-P10-O0-NEXT: ld r0, 16(r1) ; LE-P10-O0-NEXT: ld r0, 16(r1)
; LE-P10-O0-NEXT: hashchk r0, -8(r1) ; LE-P10-O0-NEXT: hashchk r0, -8(r1)
; LE-P10-O0-NEXT: mtlr r0 ; LE-P10-O0-NEXT: mtlr r0
; LE-P10-O0-NEXT: blr ; LE-P10-O0-NEXT: blr
; ;
; LE-P9-O0-LABEL: caller: ; LE-P9-O0-LABEL: caller:
; LE-P9-O0: # %bb.0: # %entry ; LE-P9-O0: # %bb.0: # %entry
; LE-P9-O0-NEXT: mflr r0 ; LE-P9-O0-NEXT: mflr r0
; LE-P9-O0-NEXT: std r0, 16(r1)
; LE-P9-O0-NEXT: hashst r0, -8(r1)
; LE-P9-O0-NEXT: stdu r1, -112(r1) ; LE-P9-O0-NEXT: stdu r1, -112(r1)
; LE-P9-O0-NEXT: std r0, 128(r1)
; LE-P9-O0-NEXT: hashst r0, -8(r1)
; LE-P9-O0-NEXT: # kill: def $r4 killed $r4 killed $x4 ; LE-P9-O0-NEXT: # kill: def $r4 killed $r4 killed $x4
; LE-P9-O0-NEXT: stw r4, 100(r1) # 4-byte Folded Spill ; LE-P9-O0-NEXT: stw r4, 100(r1) # 4-byte Folded Spill
; LE-P9-O0-NEXT: # kill: def $r3 killed $r3 killed $x3 ; LE-P9-O0-NEXT: # kill: def $r3 killed $r3 killed $x3
; LE-P9-O0-NEXT: clrldi r3, r3, 32 ; LE-P9-O0-NEXT: clrldi r3, r3, 32
; LE-P9-O0-NEXT: bl callee ; LE-P9-O0-NEXT: bl callee
; LE-P9-O0-NEXT: nop ; LE-P9-O0-NEXT: nop
; LE-P9-O0-NEXT: lwz r4, 100(r1) # 4-byte Folded Reload ; LE-P9-O0-NEXT: lwz r4, 100(r1) # 4-byte Folded Reload
; LE-P9-O0-NEXT: add r3, r3, r4 ; LE-P9-O0-NEXT: add r3, r3, r4
; LE-P9-O0-NEXT: clrldi r3, r3, 32 ; LE-P9-O0-NEXT: clrldi r3, r3, 32
; LE-P9-O0-NEXT: addi r1, r1, 112 ; LE-P9-O0-NEXT: addi r1, r1, 112
; LE-P9-O0-NEXT: ld r0, 16(r1) ; LE-P9-O0-NEXT: ld r0, 16(r1)
; LE-P9-O0-NEXT: hashchk r0, -8(r1) ; LE-P9-O0-NEXT: hashchk r0, -8(r1)
; LE-P9-O0-NEXT: mtlr r0 ; LE-P9-O0-NEXT: mtlr r0
; LE-P9-O0-NEXT: blr ; LE-P9-O0-NEXT: blr
; ;
; LE-P8-O0-LABEL: caller: ; LE-P8-O0-LABEL: caller:
; LE-P8-O0: # %bb.0: # %entry ; LE-P8-O0: # %bb.0: # %entry
; LE-P8-O0-NEXT: mflr r0 ; LE-P8-O0-NEXT: mflr r0
; LE-P8-O0-NEXT: std r0, 16(r1)
; LE-P8-O0-NEXT: hashst r0, -8(r1)
; LE-P8-O0-NEXT: stdu r1, -112(r1) ; LE-P8-O0-NEXT: stdu r1, -112(r1)
; LE-P8-O0-NEXT: std r0, 128(r1)
; LE-P8-O0-NEXT: hashst r0, -8(r1)
; LE-P8-O0-NEXT: # kill: def $r4 killed $r4 killed $x4 ; LE-P8-O0-NEXT: # kill: def $r4 killed $r4 killed $x4
; LE-P8-O0-NEXT: stw r4, 100(r1) # 4-byte Folded Spill ; LE-P8-O0-NEXT: stw r4, 100(r1) # 4-byte Folded Spill
; LE-P8-O0-NEXT: # kill: def $r3 killed $r3 killed $x3 ; LE-P8-O0-NEXT: # kill: def $r3 killed $r3 killed $x3
; LE-P8-O0-NEXT: clrldi r3, r3, 32 ; LE-P8-O0-NEXT: clrldi r3, r3, 32
; LE-P8-O0-NEXT: bl callee ; LE-P8-O0-NEXT: bl callee
; LE-P8-O0-NEXT: nop ; LE-P8-O0-NEXT: nop
; LE-P8-O0-NEXT: lwz r4, 100(r1) # 4-byte Folded Reload ; LE-P8-O0-NEXT: lwz r4, 100(r1) # 4-byte Folded Reload
; LE-P8-O0-NEXT: add r3, r3, r4 ; LE-P8-O0-NEXT: add r3, r3, r4
Show All 21 Lines
; BE-P10-NEXT: ld r0, 16(r1) ; BE-P10-NEXT: ld r0, 16(r1)
; BE-P10-NEXT: hashchk r0, -24(r1) ; BE-P10-NEXT: hashchk r0, -24(r1)
; BE-P10-NEXT: mtlr r0 ; BE-P10-NEXT: mtlr r0
; BE-P10-NEXT: blr ; BE-P10-NEXT: blr
; ;
; BE-P9-LABEL: caller: ; BE-P9-LABEL: caller:
; BE-P9: # %bb.0: # %entry ; BE-P9: # %bb.0: # %entry
; BE-P9-NEXT: mflr r0 ; BE-P9-NEXT: mflr r0
; BE-P9-NEXT: std r0, 16(r1)
; BE-P9-NEXT: hashst r0, -24(r1)
; BE-P9-NEXT: stdu r1, -144(r1) ; BE-P9-NEXT: stdu r1, -144(r1)
; BE-P9-NEXT: std r0, 160(r1)
; BE-P9-NEXT: hashst r0, -24(r1)
; BE-P9-NEXT: std r30, 128(r1) # 8-byte Folded Spill ; BE-P9-NEXT: std r30, 128(r1) # 8-byte Folded Spill
; BE-P9-NEXT: mr r30, r4 ; BE-P9-NEXT: mr r30, r4
; BE-P9-NEXT: bl callee ; BE-P9-NEXT: bl callee
; BE-P9-NEXT: nop ; BE-P9-NEXT: nop
; BE-P9-NEXT: add r3, r3, r30 ; BE-P9-NEXT: add r3, r3, r30
; BE-P9-NEXT: ld r30, 128(r1) # 8-byte Folded Reload ; BE-P9-NEXT: ld r30, 128(r1) # 8-byte Folded Reload
; BE-P9-NEXT: clrldi r3, r3, 32 ; BE-P9-NEXT: clrldi r3, r3, 32
; BE-P9-NEXT: addi r1, r1, 144 ; BE-P9-NEXT: addi r1, r1, 144
; BE-P9-NEXT: ld r0, 16(r1) ; BE-P9-NEXT: ld r0, 16(r1)
; BE-P9-NEXT: mtlr r0 ; BE-P9-NEXT: mtlr r0
; BE-P9-NEXT: hashchk r0, -24(r1) ; BE-P9-NEXT: hashchk r0, -24(r1)
; BE-P9-NEXT: blr ; BE-P9-NEXT: blr
; ;
; BE-P8-LABEL: caller: ; BE-P8-LABEL: caller:
; BE-P8: # %bb.0: # %entry ; BE-P8: # %bb.0: # %entry
; BE-P8-NEXT: mflr r0 ; BE-P8-NEXT: mflr r0
; BE-P8-NEXT: std r0, 16(r1)
; BE-P8-NEXT: hashst r0, -24(r1)
; BE-P8-NEXT: stdu r1, -144(r1) ; BE-P8-NEXT: stdu r1, -144(r1)
; BE-P8-NEXT: std r0, 160(r1)
; BE-P8-NEXT: hashst r0, -24(r1)
; BE-P8-NEXT: std r30, 128(r1) # 8-byte Folded Spill ; BE-P8-NEXT: std r30, 128(r1) # 8-byte Folded Spill
; BE-P8-NEXT: mr r30, r4 ; BE-P8-NEXT: mr r30, r4
; BE-P8-NEXT: bl callee ; BE-P8-NEXT: bl callee
; BE-P8-NEXT: nop ; BE-P8-NEXT: nop
; BE-P8-NEXT: add r3, r3, r30 ; BE-P8-NEXT: add r3, r3, r30
; BE-P8-NEXT: ld r30, 128(r1) # 8-byte Folded Reload ; BE-P8-NEXT: ld r30, 128(r1) # 8-byte Folded Reload
; BE-P8-NEXT: clrldi r3, r3, 32 ; BE-P8-NEXT: clrldi r3, r3, 32
; BE-P8-NEXT: addi r1, r1, 144 ; BE-P8-NEXT: addi r1, r1, 144
Show All 17 Lines
; BE-32BIT-P10-NEXT: addi r1, r1, 32 ; BE-32BIT-P10-NEXT: addi r1, r1, 32
; BE-32BIT-P10-NEXT: hashchk r0, -16(r1) ; BE-32BIT-P10-NEXT: hashchk r0, -16(r1)
; BE-32BIT-P10-NEXT: mtlr r0 ; BE-32BIT-P10-NEXT: mtlr r0
; BE-32BIT-P10-NEXT: blr ; BE-32BIT-P10-NEXT: blr
; ;
; BE-32BIT-P9-LABEL: caller: ; BE-32BIT-P9-LABEL: caller:
; BE-32BIT-P9: # %bb.0: # %entry ; BE-32BIT-P9: # %bb.0: # %entry
; BE-32BIT-P9-NEXT: mflr r0 ; BE-32BIT-P9-NEXT: mflr r0
; BE-32BIT-P9-NEXT: stw r0, 4(r1)
; BE-32BIT-P9-NEXT: hashst r0, -16(r1)
; BE-32BIT-P9-NEXT: stwu r1, -32(r1) ; BE-32BIT-P9-NEXT: stwu r1, -32(r1)
; BE-32BIT-P9-NEXT: stw r0, 36(r1)
; BE-32BIT-P9-NEXT: hashst r0, -16(r1)
; BE-32BIT-P9-NEXT: stw r30, 24(r1) # 4-byte Folded Spill ; BE-32BIT-P9-NEXT: stw r30, 24(r1) # 4-byte Folded Spill
; BE-32BIT-P9-NEXT: mr r30, r4 ; BE-32BIT-P9-NEXT: mr r30, r4
; BE-32BIT-P9-NEXT: bl callee ; BE-32BIT-P9-NEXT: bl callee
; BE-32BIT-P9-NEXT: add r3, r3, r30 ; BE-32BIT-P9-NEXT: add r3, r3, r30
; BE-32BIT-P9-NEXT: lwz r30, 24(r1) # 4-byte Folded Reload ; BE-32BIT-P9-NEXT: lwz r30, 24(r1) # 4-byte Folded Reload
; BE-32BIT-P9-NEXT: lwz r0, 36(r1) ; BE-32BIT-P9-NEXT: lwz r0, 36(r1)
; BE-32BIT-P9-NEXT: addi r1, r1, 32 ; BE-32BIT-P9-NEXT: addi r1, r1, 32
; BE-32BIT-P9-NEXT: mtlr r0 ; BE-32BIT-P9-NEXT: mtlr r0
; BE-32BIT-P9-NEXT: hashchk r0, -16(r1) ; BE-32BIT-P9-NEXT: hashchk r0, -16(r1)
; BE-32BIT-P9-NEXT: blr ; BE-32BIT-P9-NEXT: blr
; ;
; BE-32BIT-P8-LABEL: caller: ; BE-32BIT-P8-LABEL: caller:
; BE-32BIT-P8: # %bb.0: # %entry ; BE-32BIT-P8: # %bb.0: # %entry
; BE-32BIT-P8-NEXT: mflr r0 ; BE-32BIT-P8-NEXT: mflr r0
; BE-32BIT-P8-NEXT: stw r0, 4(r1)
; BE-32BIT-P8-NEXT: hashst r0, -16(r1)
; BE-32BIT-P8-NEXT: stwu r1, -32(r1) ; BE-32BIT-P8-NEXT: stwu r1, -32(r1)
; BE-32BIT-P8-NEXT: stw r0, 36(r1)
; BE-32BIT-P8-NEXT: hashst r0, -16(r1)
; BE-32BIT-P8-NEXT: stw r30, 24(r1) # 4-byte Folded Spill ; BE-32BIT-P8-NEXT: stw r30, 24(r1) # 4-byte Folded Spill
; BE-32BIT-P8-NEXT: mr r30, r4 ; BE-32BIT-P8-NEXT: mr r30, r4
; BE-32BIT-P8-NEXT: bl callee ; BE-32BIT-P8-NEXT: bl callee
; BE-32BIT-P8-NEXT: add r3, r3, r30 ; BE-32BIT-P8-NEXT: add r3, r3, r30
; BE-32BIT-P8-NEXT: lwz r30, 24(r1) # 4-byte Folded Reload ; BE-32BIT-P8-NEXT: lwz r30, 24(r1) # 4-byte Folded Reload
; BE-32BIT-P8-NEXT: lwz r0, 36(r1) ; BE-32BIT-P8-NEXT: lwz r0, 36(r1)
; BE-32BIT-P8-NEXT: addi r1, r1, 32 ; BE-32BIT-P8-NEXT: addi r1, r1, 32
; BE-32BIT-P8-NEXT: mtlr r0 ; BE-32BIT-P8-NEXT: mtlr r0
Show All 17 Lines
; LE-P10-PRIV-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; LE-P10-PRIV-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; LE-P10-PRIV-NEXT: mtlr r0 ; LE-P10-PRIV-NEXT: mtlr r0
; LE-P10-PRIV-NEXT: blr ; LE-P10-PRIV-NEXT: blr
; ;
; LE-P9-PRIV-LABEL: caller: ; LE-P9-PRIV-LABEL: caller:
; LE-P9-PRIV: # %bb.0: # %entry ; LE-P9-PRIV: # %bb.0: # %entry
; LE-P9-PRIV-NEXT: mflr r0 ; LE-P9-PRIV-NEXT: mflr r0
; LE-P9-PRIV-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; LE-P9-PRIV-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; LE-P9-PRIV-NEXT: std r0, 16(r1)
; LE-P9-PRIV-NEXT: hashstp r0, -24(r1)
; LE-P9-PRIV-NEXT: stdu r1, -64(r1) ; LE-P9-PRIV-NEXT: stdu r1, -64(r1)
; LE-P9-PRIV-NEXT: std r0, 80(r1)
; LE-P9-PRIV-NEXT: hashstp r0, -24(r1)
; LE-P9-PRIV-NEXT: mr r30, r4 ; LE-P9-PRIV-NEXT: mr r30, r4
; LE-P9-PRIV-NEXT: bl callee ; LE-P9-PRIV-NEXT: bl callee
; LE-P9-PRIV-NEXT: nop ; LE-P9-PRIV-NEXT: nop
; LE-P9-PRIV-NEXT: add r3, r3, r30 ; LE-P9-PRIV-NEXT: add r3, r3, r30
; LE-P9-PRIV-NEXT: clrldi r3, r3, 32 ; LE-P9-PRIV-NEXT: clrldi r3, r3, 32
; LE-P9-PRIV-NEXT: addi r1, r1, 64 ; LE-P9-PRIV-NEXT: addi r1, r1, 64
; LE-P9-PRIV-NEXT: ld r0, 16(r1) ; LE-P9-PRIV-NEXT: ld r0, 16(r1)
; LE-P9-PRIV-NEXT: mtlr r0 ; LE-P9-PRIV-NEXT: mtlr r0
; LE-P9-PRIV-NEXT: hashchkp r0, -24(r1) ; LE-P9-PRIV-NEXT: hashchkp r0, -24(r1)
; LE-P9-PRIV-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; LE-P9-PRIV-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; LE-P9-PRIV-NEXT: blr ; LE-P9-PRIV-NEXT: blr
; ;
; LE-P8-PRIV-LABEL: caller: ; LE-P8-PRIV-LABEL: caller:
; LE-P8-PRIV: # %bb.0: # %entry ; LE-P8-PRIV: # %bb.0: # %entry
; LE-P8-PRIV-NEXT: mflr r0 ; LE-P8-PRIV-NEXT: mflr r0
; LE-P8-PRIV-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; LE-P8-PRIV-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; LE-P8-PRIV-NEXT: std r0, 16(r1)
; LE-P8-PRIV-NEXT: hashstp r0, -24(r1)
; LE-P8-PRIV-NEXT: stdu r1, -64(r1) ; LE-P8-PRIV-NEXT: stdu r1, -64(r1)
; LE-P8-PRIV-NEXT: std r0, 80(r1)
; LE-P8-PRIV-NEXT: hashstp r0, -24(r1)
; LE-P8-PRIV-NEXT: mr r30, r4 ; LE-P8-PRIV-NEXT: mr r30, r4
; LE-P8-PRIV-NEXT: bl callee ; LE-P8-PRIV-NEXT: bl callee
; LE-P8-PRIV-NEXT: nop ; LE-P8-PRIV-NEXT: nop
; LE-P8-PRIV-NEXT: add r3, r3, r30 ; LE-P8-PRIV-NEXT: add r3, r3, r30
; LE-P8-PRIV-NEXT: clrldi r3, r3, 32 ; LE-P8-PRIV-NEXT: clrldi r3, r3, 32
; LE-P8-PRIV-NEXT: addi r1, r1, 64 ; LE-P8-PRIV-NEXT: addi r1, r1, 64
; LE-P8-PRIV-NEXT: ld r0, 16(r1) ; LE-P8-PRIV-NEXT: ld r0, 16(r1)
; LE-P8-PRIV-NEXT: hashchkp r0, -24(r1) ; LE-P8-PRIV-NEXT: hashchkp r0, -24(r1)
Show All 18 Lines
; BE-P10-PRIV-NEXT: ld r0, 16(r1) ; BE-P10-PRIV-NEXT: ld r0, 16(r1)
; BE-P10-PRIV-NEXT: hashchkp r0, -24(r1) ; BE-P10-PRIV-NEXT: hashchkp r0, -24(r1)
; BE-P10-PRIV-NEXT: mtlr r0 ; BE-P10-PRIV-NEXT: mtlr r0
; BE-P10-PRIV-NEXT: blr ; BE-P10-PRIV-NEXT: blr
; ;
; BE-P9-PRIV-LABEL: caller: ; BE-P9-PRIV-LABEL: caller:
; BE-P9-PRIV: # %bb.0: # %entry ; BE-P9-PRIV: # %bb.0: # %entry
; BE-P9-PRIV-NEXT: mflr r0 ; BE-P9-PRIV-NEXT: mflr r0
; BE-P9-PRIV-NEXT: std r0, 16(r1)
; BE-P9-PRIV-NEXT: hashstp r0, -24(r1)
; BE-P9-PRIV-NEXT: stdu r1, -144(r1) ; BE-P9-PRIV-NEXT: stdu r1, -144(r1)
; BE-P9-PRIV-NEXT: std r0, 160(r1)
; BE-P9-PRIV-NEXT: hashstp r0, -24(r1)
; BE-P9-PRIV-NEXT: std r30, 128(r1) # 8-byte Folded Spill ; BE-P9-PRIV-NEXT: std r30, 128(r1) # 8-byte Folded Spill
; BE-P9-PRIV-NEXT: mr r30, r4 ; BE-P9-PRIV-NEXT: mr r30, r4
; BE-P9-PRIV-NEXT: bl callee ; BE-P9-PRIV-NEXT: bl callee
; BE-P9-PRIV-NEXT: nop ; BE-P9-PRIV-NEXT: nop
; BE-P9-PRIV-NEXT: add r3, r3, r30 ; BE-P9-PRIV-NEXT: add r3, r3, r30
; BE-P9-PRIV-NEXT: ld r30, 128(r1) # 8-byte Folded Reload ; BE-P9-PRIV-NEXT: ld r30, 128(r1) # 8-byte Folded Reload
; BE-P9-PRIV-NEXT: clrldi r3, r3, 32 ; BE-P9-PRIV-NEXT: clrldi r3, r3, 32
; BE-P9-PRIV-NEXT: addi r1, r1, 144 ; BE-P9-PRIV-NEXT: addi r1, r1, 144
; BE-P9-PRIV-NEXT: ld r0, 16(r1) ; BE-P9-PRIV-NEXT: ld r0, 16(r1)
; BE-P9-PRIV-NEXT: mtlr r0 ; BE-P9-PRIV-NEXT: mtlr r0
; BE-P9-PRIV-NEXT: hashchkp r0, -24(r1) ; BE-P9-PRIV-NEXT: hashchkp r0, -24(r1)
; BE-P9-PRIV-NEXT: blr ; BE-P9-PRIV-NEXT: blr
; ;
; BE-P8-PRIV-LABEL: caller: ; BE-P8-PRIV-LABEL: caller:
; BE-P8-PRIV: # %bb.0: # %entry ; BE-P8-PRIV: # %bb.0: # %entry
; BE-P8-PRIV-NEXT: mflr r0 ; BE-P8-PRIV-NEXT: mflr r0
; BE-P8-PRIV-NEXT: std r0, 16(r1)
; BE-P8-PRIV-NEXT: hashstp r0, -24(r1)
; BE-P8-PRIV-NEXT: stdu r1, -144(r1) ; BE-P8-PRIV-NEXT: stdu r1, -144(r1)
; BE-P8-PRIV-NEXT: std r0, 160(r1)
; BE-P8-PRIV-NEXT: hashstp r0, -24(r1)
; BE-P8-PRIV-NEXT: std r30, 128(r1) # 8-byte Folded Spill ; BE-P8-PRIV-NEXT: std r30, 128(r1) # 8-byte Folded Spill
; BE-P8-PRIV-NEXT: mr r30, r4 ; BE-P8-PRIV-NEXT: mr r30, r4
; BE-P8-PRIV-NEXT: bl callee ; BE-P8-PRIV-NEXT: bl callee
; BE-P8-PRIV-NEXT: nop ; BE-P8-PRIV-NEXT: nop
; BE-P8-PRIV-NEXT: add r3, r3, r30 ; BE-P8-PRIV-NEXT: add r3, r3, r30
; BE-P8-PRIV-NEXT: ld r30, 128(r1) # 8-byte Folded Reload ; BE-P8-PRIV-NEXT: ld r30, 128(r1) # 8-byte Folded Reload
; BE-P8-PRIV-NEXT: clrldi r3, r3, 32 ; BE-P8-PRIV-NEXT: clrldi r3, r3, 32
; BE-P8-PRIV-NEXT: addi r1, r1, 144 ; BE-P8-PRIV-NEXT: addi r1, r1, 144
▲ Show 20 Lines • Show All 135 Lines • ▼ Show 20 Lines
; LE-P10-NEXT: hashchk r0, -488(r1) ; LE-P10-NEXT: hashchk r0, -488(r1)
; LE-P10-NEXT: mtocrf 32, r12 ; LE-P10-NEXT: mtocrf 32, r12
; LE-P10-NEXT: mtocrf 16, r12 ; LE-P10-NEXT: mtocrf 16, r12
; LE-P10-NEXT: mtocrf 8, r12 ; LE-P10-NEXT: mtocrf 8, r12
; LE-P10-NEXT: blr ; LE-P10-NEXT: blr
; ;
; LE-P9-LABEL: spill: ; LE-P9-LABEL: spill:
; LE-P9: # %bb.0: # %entry ; LE-P9: # %bb.0: # %entry
; LE-P9-NEXT: mflr r0
; LE-P9-NEXT: mfcr r12 ; LE-P9-NEXT: mfcr r12
; LE-P9-NEXT: std r0, 16(r1) ; LE-P9-NEXT: mflr r0
; LE-P9-NEXT: hashst r0, -488(r1)
; LE-P9-NEXT: stw r12, 8(r1) ; LE-P9-NEXT: stw r12, 8(r1)
; LE-P9-NEXT: stdu r1, -544(r1) ; LE-P9-NEXT: stdu r1, -544(r1)
; LE-P9-NEXT: lwz r4, 12(r3) ; LE-P9-NEXT: std r0, 560(r1)
; LE-P9-NEXT: hashst r0, -488(r1)
; LE-P9-NEXT: std r14, 256(r1) # 8-byte Folded Spill ; LE-P9-NEXT: std r14, 256(r1) # 8-byte Folded Spill
; LE-P9-NEXT: std r15, 264(r1) # 8-byte Folded Spill
; LE-P9-NEXT: stxv v20, 64(r1) # 16-byte Folded Spill ; LE-P9-NEXT: stxv v20, 64(r1) # 16-byte Folded Spill
; LE-P9-NEXT: stxv v21, 80(r1) # 16-byte Folded Spill ; LE-P9-NEXT: stxv v21, 80(r1) # 16-byte Folded Spill
; LE-P9-NEXT: lwz r4, 12(r3)
; LE-P9-NEXT: std r15, 264(r1) # 8-byte Folded Spill
; LE-P9-NEXT: stxv v22, 96(r1) # 16-byte Folded Spill ; LE-P9-NEXT: stxv v22, 96(r1) # 16-byte Folded Spill
; LE-P9-NEXT: std r16, 272(r1) # 8-byte Folded Spill ; LE-P9-NEXT: std r16, 272(r1) # 8-byte Folded Spill
; LE-P9-NEXT: std r17, 280(r1) # 8-byte Folded Spill
; LE-P9-NEXT: stxv v23, 112(r1) # 16-byte Folded Spill ; LE-P9-NEXT: stxv v23, 112(r1) # 16-byte Folded Spill
; LE-P9-NEXT: std r18, 288(r1) # 8-byte Folded Spill ; LE-P9-NEXT: std r17, 280(r1) # 8-byte Folded Spill
; LE-P9-NEXT: stxv v24, 128(r1) # 16-byte Folded Spill ; LE-P9-NEXT: stxv v24, 128(r1) # 16-byte Folded Spill
; LE-P9-NEXT: std r19, 296(r1) # 8-byte Folded Spill ; LE-P9-NEXT: std r18, 288(r1) # 8-byte Folded Spill
; LE-P9-NEXT: stxv v25, 144(r1) # 16-byte Folded Spill ; LE-P9-NEXT: stxv v25, 144(r1) # 16-byte Folded Spill
; LE-P9-NEXT: std r19, 296(r1) # 8-byte Folded Spill
; LE-P9-NEXT: std r20, 304(r1) # 8-byte Folded Spill ; LE-P9-NEXT: std r20, 304(r1) # 8-byte Folded Spill
; LE-P9-NEXT: std r21, 312(r1) # 8-byte Folded Spill
; LE-P9-NEXT: stxv v26, 160(r1) # 16-byte Folded Spill ; LE-P9-NEXT: stxv v26, 160(r1) # 16-byte Folded Spill
; LE-P9-NEXT: std r22, 320(r1) # 8-byte Folded Spill ; LE-P9-NEXT: std r21, 312(r1) # 8-byte Folded Spill
; LE-P9-NEXT: stxv v27, 176(r1) # 16-byte Folded Spill ; LE-P9-NEXT: stxv v27, 176(r1) # 16-byte Folded Spill
; LE-P9-NEXT: std r23, 328(r1) # 8-byte Folded Spill ; LE-P9-NEXT: std r22, 320(r1) # 8-byte Folded Spill
; LE-P9-NEXT: stxv v28, 192(r1) # 16-byte Folded Spill ; LE-P9-NEXT: stxv v28, 192(r1) # 16-byte Folded Spill
; LE-P9-NEXT: std r23, 328(r1) # 8-byte Folded Spill
; LE-P9-NEXT: std r24, 336(r1) # 8-byte Folded Spill ; LE-P9-NEXT: std r24, 336(r1) # 8-byte Folded Spill
; LE-P9-NEXT: std r25, 344(r1) # 8-byte Folded Spill
; LE-P9-NEXT: stxv v29, 208(r1) # 16-byte Folded Spill ; LE-P9-NEXT: stxv v29, 208(r1) # 16-byte Folded Spill
; LE-P9-NEXT: std r26, 352(r1) # 8-byte Folded Spill ; LE-P9-NEXT: std r25, 344(r1) # 8-byte Folded Spill
; LE-P9-NEXT: stxv v30, 224(r1) # 16-byte Folded Spill ; LE-P9-NEXT: stxv v30, 224(r1) # 16-byte Folded Spill
; LE-P9-NEXT: std r27, 360(r1) # 8-byte Folded Spill ; LE-P9-NEXT: std r26, 352(r1) # 8-byte Folded Spill
; LE-P9-NEXT: stxv v31, 240(r1) # 16-byte Folded Spill ; LE-P9-NEXT: stxv v31, 240(r1) # 16-byte Folded Spill
; LE-P9-NEXT: std r27, 360(r1) # 8-byte Folded Spill
; LE-P9-NEXT: std r28, 368(r1) # 8-byte Folded Spill ; LE-P9-NEXT: std r28, 368(r1) # 8-byte Folded Spill
; LE-P9-NEXT: std r29, 376(r1) # 8-byte Folded Spill ; LE-P9-NEXT: std r29, 376(r1) # 8-byte Folded Spill
; LE-P9-NEXT: std r30, 384(r1) # 8-byte Folded Spill ; LE-P9-NEXT: std r30, 384(r1) # 8-byte Folded Spill
; LE-P9-NEXT: std r31, 392(r1) # 8-byte Folded Spill ; LE-P9-NEXT: std r31, 392(r1) # 8-byte Folded Spill
; LE-P9-NEXT: stfd f14, 400(r1) # 8-byte Folded Spill ; LE-P9-NEXT: stfd f14, 400(r1) # 8-byte Folded Spill
; LE-P9-NEXT: stfd f15, 408(r1) # 8-byte Folded Spill ; LE-P9-NEXT: stfd f15, 408(r1) # 8-byte Folded Spill
; LE-P9-NEXT: stfd f16, 416(r1) # 8-byte Folded Spill ; LE-P9-NEXT: stfd f16, 416(r1) # 8-byte Folded Spill
; LE-P9-NEXT: stfd f17, 424(r1) # 8-byte Folded Spill ; LE-P9-NEXT: stfd f17, 424(r1) # 8-byte Folded Spill
▲ Show 20 Lines • Show All 80 Lines • ▼ Show 20 Lines
; LE-P9-NEXT: mtocrf 16, r12 ; LE-P9-NEXT: mtocrf 16, r12
; LE-P9-NEXT: mtocrf 8, r12 ; LE-P9-NEXT: mtocrf 8, r12
; LE-P9-NEXT: blr ; LE-P9-NEXT: blr
; ;
; LE-P8-LABEL: spill: ; LE-P8-LABEL: spill:
; LE-P8: # %bb.0: # %entry ; LE-P8: # %bb.0: # %entry
; LE-P8-NEXT: mfcr r12 ; LE-P8-NEXT: mfcr r12
; LE-P8-NEXT: mflr r0 ; LE-P8-NEXT: mflr r0
; LE-P8-NEXT: std r0, 16(r1)
; LE-P8-NEXT: hashst r0, -488(r1)
; LE-P8-NEXT: stw r12, 8(r1) ; LE-P8-NEXT: stw r12, 8(r1)
; LE-P8-NEXT: stdu r1, -544(r1) ; LE-P8-NEXT: stdu r1, -544(r1)
; LE-P8-NEXT: li r4, 64 ; LE-P8-NEXT: li r4, 64
; LE-P8-NEXT: std r0, 560(r1)
; LE-P8-NEXT: hashst r0, -488(r1)
; LE-P8-NEXT: std r14, 256(r1) # 8-byte Folded Spill ; LE-P8-NEXT: std r14, 256(r1) # 8-byte Folded Spill
; LE-P8-NEXT: std r15, 264(r1) # 8-byte Folded Spill ; LE-P8-NEXT: std r15, 264(r1) # 8-byte Folded Spill
; LE-P8-NEXT: std r16, 272(r1) # 8-byte Folded Spill ; LE-P8-NEXT: std r16, 272(r1) # 8-byte Folded Spill
; LE-P8-NEXT: std r17, 280(r1) # 8-byte Folded Spill
; LE-P8-NEXT: stxvd2x v20, r1, r4 # 16-byte Folded Spill ; LE-P8-NEXT: stxvd2x v20, r1, r4 # 16-byte Folded Spill
; LE-P8-NEXT: li r4, 80 ; LE-P8-NEXT: li r4, 80
; LE-P8-NEXT: std r17, 280(r1) # 8-byte Folded Spill
; LE-P8-NEXT: std r18, 288(r1) # 8-byte Folded Spill ; LE-P8-NEXT: std r18, 288(r1) # 8-byte Folded Spill
; LE-P8-NEXT: std r19, 296(r1) # 8-byte Folded Spill ; LE-P8-NEXT: std r19, 296(r1) # 8-byte Folded Spill
; LE-P8-NEXT: std r20, 304(r1) # 8-byte Folded Spill ; LE-P8-NEXT: std r20, 304(r1) # 8-byte Folded Spill
; LE-P8-NEXT: std r21, 312(r1) # 8-byte Folded Spill
; LE-P8-NEXT: stxvd2x v21, r1, r4 # 16-byte Folded Spill ; LE-P8-NEXT: stxvd2x v21, r1, r4 # 16-byte Folded Spill
; LE-P8-NEXT: li r4, 96 ; LE-P8-NEXT: li r4, 96
; LE-P8-NEXT: std r21, 312(r1) # 8-byte Folded Spill
; LE-P8-NEXT: std r22, 320(r1) # 8-byte Folded Spill ; LE-P8-NEXT: std r22, 320(r1) # 8-byte Folded Spill
; LE-P8-NEXT: std r23, 328(r1) # 8-byte Folded Spill ; LE-P8-NEXT: std r23, 328(r1) # 8-byte Folded Spill
; LE-P8-NEXT: std r24, 336(r1) # 8-byte Folded Spill ; LE-P8-NEXT: std r24, 336(r1) # 8-byte Folded Spill
; LE-P8-NEXT: std r25, 344(r1) # 8-byte Folded Spill ; LE-P8-NEXT: std r25, 344(r1) # 8-byte Folded Spill
; LE-P8-NEXT: std r26, 352(r1) # 8-byte Folded Spill ; LE-P8-NEXT: std r26, 352(r1) # 8-byte Folded Spill
; LE-P8-NEXT: std r27, 360(r1) # 8-byte Folded Spill ; LE-P8-NEXT: std r27, 360(r1) # 8-byte Folded Spill
; LE-P8-NEXT: std r28, 368(r1) # 8-byte Folded Spill ; LE-P8-NEXT: std r28, 368(r1) # 8-byte Folded Spill
; LE-P8-NEXT: std r29, 376(r1) # 8-byte Folded Spill ; LE-P8-NEXT: std r29, 376(r1) # 8-byte Folded Spill
; LE-P8-NEXT: std r30, 384(r1) # 8-byte Folded Spill ; LE-P8-NEXT: std r30, 384(r1) # 8-byte Folded Spill
; LE-P8-NEXT: std r31, 392(r1) # 8-byte Folded Spill ; LE-P8-NEXT: std r31, 392(r1) # 8-byte Folded Spill
; LE-P8-NEXT: std r3, 40(r1) # 8-byte Folded Spill ; LE-P8-NEXT: std r3, 40(r1) # 8-byte Folded Spill
; LE-P8-NEXT: stxvd2x v22, r1, r4 # 16-byte Folded Spill ; LE-P8-NEXT: stxvd2x v22, r1, r4 # 16-byte Folded Spill
; LE-P8-NEXT: li r4, 112 ; LE-P8-NEXT: li r4, 112
; LE-P8-NEXT: stfd f14, 400(r1) # 8-byte Folded Spill
; LE-P8-NEXT: stxvd2x v23, r1, r4 # 16-byte Folded Spill ; LE-P8-NEXT: stxvd2x v23, r1, r4 # 16-byte Folded Spill
; LE-P8-NEXT: li r4, 128 ; LE-P8-NEXT: li r4, 128
; LE-P8-NEXT: stfd f14, 400(r1) # 8-byte Folded Spill ; LE-P8-NEXT: stfd f15, 408(r1) # 8-byte Folded Spill
; LE-P8-NEXT: stxvd2x v24, r1, r4 # 16-byte Folded Spill ; LE-P8-NEXT: stxvd2x v24, r1, r4 # 16-byte Folded Spill
; LE-P8-NEXT: li r4, 144 ; LE-P8-NEXT: li r4, 144
; LE-P8-NEXT: stfd f15, 408(r1) # 8-byte Folded Spill ; LE-P8-NEXT: stfd f16, 416(r1) # 8-byte Folded Spill
; LE-P8-NEXT: stxvd2x v25, r1, r4 # 16-byte Folded Spill ; LE-P8-NEXT: stxvd2x v25, r1, r4 # 16-byte Folded Spill
; LE-P8-NEXT: li r4, 160 ; LE-P8-NEXT: li r4, 160
; LE-P8-NEXT: stfd f16, 416(r1) # 8-byte Folded Spill ; LE-P8-NEXT: stfd f17, 424(r1) # 8-byte Folded Spill
; LE-P8-NEXT: stxvd2x v26, r1, r4 # 16-byte Folded Spill ; LE-P8-NEXT: stxvd2x v26, r1, r4 # 16-byte Folded Spill
; LE-P8-NEXT: li r4, 176 ; LE-P8-NEXT: li r4, 176
; LE-P8-NEXT: stfd f17, 424(r1) # 8-byte Folded Spill ; LE-P8-NEXT: stfd f18, 432(r1) # 8-byte Folded Spill
; LE-P8-NEXT: stxvd2x v27, r1, r4 # 16-byte Folded Spill ; LE-P8-NEXT: stxvd2x v27, r1, r4 # 16-byte Folded Spill
; LE-P8-NEXT: li r4, 192 ; LE-P8-NEXT: li r4, 192
; LE-P8-NEXT: stfd f18, 432(r1) # 8-byte Folded Spill ; LE-P8-NEXT: stfd f19, 440(r1) # 8-byte Folded Spill
; LE-P8-NEXT: stxvd2x v28, r1, r4 # 16-byte Folded Spill ; LE-P8-NEXT: stxvd2x v28, r1, r4 # 16-byte Folded Spill
; LE-P8-NEXT: li r4, 208 ; LE-P8-NEXT: li r4, 208
; LE-P8-NEXT: stfd f19, 440(r1) # 8-byte Folded Spill ; LE-P8-NEXT: stfd f20, 448(r1) # 8-byte Folded Spill
; LE-P8-NEXT: stxvd2x v29, r1, r4 # 16-byte Folded Spill ; LE-P8-NEXT: stxvd2x v29, r1, r4 # 16-byte Folded Spill
; LE-P8-NEXT: li r4, 224 ; LE-P8-NEXT: li r4, 224
; LE-P8-NEXT: stfd f20, 448(r1) # 8-byte Folded Spill ; LE-P8-NEXT: stfd f21, 456(r1) # 8-byte Folded Spill
; LE-P8-NEXT: stxvd2x v30, r1, r4 # 16-byte Folded Spill ; LE-P8-NEXT: stxvd2x v30, r1, r4 # 16-byte Folded Spill
; LE-P8-NEXT: li r4, 240 ; LE-P8-NEXT: li r4, 240
; LE-P8-NEXT: stfd f21, 456(r1) # 8-byte Folded Spill ; LE-P8-NEXT: stfd f22, 464(r1) # 8-byte Folded Spill
; LE-P8-NEXT: stxvd2x v31, r1, r4 # 16-byte Folded Spill ; LE-P8-NEXT: stxvd2x v31, r1, r4 # 16-byte Folded Spill
; LE-P8-NEXT: lwz r4, 12(r3) ; LE-P8-NEXT: lwz r4, 12(r3)
; LE-P8-NEXT: stfd f22, 464(r1) # 8-byte Folded Spill
; LE-P8-NEXT: stfd f23, 472(r1) # 8-byte Folded Spill ; LE-P8-NEXT: stfd f23, 472(r1) # 8-byte Folded Spill
; LE-P8-NEXT: stfd f24, 480(r1) # 8-byte Folded Spill ; LE-P8-NEXT: stfd f24, 480(r1) # 8-byte Folded Spill
; LE-P8-NEXT: stfd f25, 488(r1) # 8-byte Folded Spill ; LE-P8-NEXT: stfd f25, 488(r1) # 8-byte Folded Spill
; LE-P8-NEXT: stfd f26, 496(r1) # 8-byte Folded Spill ; LE-P8-NEXT: stfd f26, 496(r1) # 8-byte Folded Spill
; LE-P8-NEXT: stfd f27, 504(r1) # 8-byte Folded Spill ; LE-P8-NEXT: stfd f27, 504(r1) # 8-byte Folded Spill
; LE-P8-NEXT: stfd f28, 512(r1) # 8-byte Folded Spill ; LE-P8-NEXT: stfd f28, 512(r1) # 8-byte Folded Spill
; LE-P8-NEXT: stfd f29, 520(r1) # 8-byte Folded Spill ; LE-P8-NEXT: stfd f29, 520(r1) # 8-byte Folded Spill
; LE-P8-NEXT: stfd f30, 528(r1) # 8-byte Folded Spill ; LE-P8-NEXT: stfd f30, 528(r1) # 8-byte Folded Spill
▲ Show 20 Lines • Show All 206 Lines • ▼ Show 20 Lines
; LE-P10-O0-NEXT: hashchk r0, -488(r1) ; LE-P10-O0-NEXT: hashchk r0, -488(r1)
; LE-P10-O0-NEXT: mtlr r0 ; LE-P10-O0-NEXT: mtlr r0
; LE-P10-O0-NEXT: blr ; LE-P10-O0-NEXT: blr
; ;
; LE-P9-O0-LABEL: spill: ; LE-P9-O0-LABEL: spill:
; LE-P9-O0: # %bb.0: # %entry ; LE-P9-O0: # %bb.0: # %entry
; LE-P9-O0-NEXT: mflr r0 ; LE-P9-O0-NEXT: mflr r0
; LE-P9-O0-NEXT: mfcr r12 ; LE-P9-O0-NEXT: mfcr r12
; LE-P9-O0-NEXT: std r0, 16(r1)
; LE-P9-O0-NEXT: hashst r0, -488(r1)
; LE-P9-O0-NEXT: stw r12, 8(r1) ; LE-P9-O0-NEXT: stw r12, 8(r1)
; LE-P9-O0-NEXT: stdu r1, -608(r1) ; LE-P9-O0-NEXT: stdu r1, -608(r1)
; LE-P9-O0-NEXT: std r0, 624(r1)
; LE-P9-O0-NEXT: hashst r0, -488(r1)
; LE-P9-O0-NEXT: std r14, 320(r1) # 8-byte Folded Spill ; LE-P9-O0-NEXT: std r14, 320(r1) # 8-byte Folded Spill
; LE-P9-O0-NEXT: std r15, 328(r1) # 8-byte Folded Spill ; LE-P9-O0-NEXT: std r15, 328(r1) # 8-byte Folded Spill
; LE-P9-O0-NEXT: std r16, 336(r1) # 8-byte Folded Spill ; LE-P9-O0-NEXT: std r16, 336(r1) # 8-byte Folded Spill
; LE-P9-O0-NEXT: std r17, 344(r1) # 8-byte Folded Spill ; LE-P9-O0-NEXT: std r17, 344(r1) # 8-byte Folded Spill
; LE-P9-O0-NEXT: std r18, 352(r1) # 8-byte Folded Spill ; LE-P9-O0-NEXT: std r18, 352(r1) # 8-byte Folded Spill
; LE-P9-O0-NEXT: std r19, 360(r1) # 8-byte Folded Spill ; LE-P9-O0-NEXT: std r19, 360(r1) # 8-byte Folded Spill
; LE-P9-O0-NEXT: std r20, 368(r1) # 8-byte Folded Spill ; LE-P9-O0-NEXT: std r20, 368(r1) # 8-byte Folded Spill
; LE-P9-O0-NEXT: std r21, 376(r1) # 8-byte Folded Spill ; LE-P9-O0-NEXT: std r21, 376(r1) # 8-byte Folded Spill
▲ Show 20 Lines • Show All 108 Lines • ▼ Show 20 Lines
; LE-P9-O0-NEXT: hashchk r0, -488(r1) ; LE-P9-O0-NEXT: hashchk r0, -488(r1)
; LE-P9-O0-NEXT: mtlr r0 ; LE-P9-O0-NEXT: mtlr r0
; LE-P9-O0-NEXT: blr ; LE-P9-O0-NEXT: blr
; ;
; LE-P8-O0-LABEL: spill: ; LE-P8-O0-LABEL: spill:
; LE-P8-O0: # %bb.0: # %entry ; LE-P8-O0: # %bb.0: # %entry
; LE-P8-O0-NEXT: mflr r0 ; LE-P8-O0-NEXT: mflr r0
; LE-P8-O0-NEXT: mfcr r12 ; LE-P8-O0-NEXT: mfcr r12
; LE-P8-O0-NEXT: std r0, 16(r1)
; LE-P8-O0-NEXT: hashst r0, -488(r1)
; LE-P8-O0-NEXT: stw r12, 8(r1) ; LE-P8-O0-NEXT: stw r12, 8(r1)
; LE-P8-O0-NEXT: stdu r1, -608(r1) ; LE-P8-O0-NEXT: stdu r1, -608(r1)
; LE-P8-O0-NEXT: std r0, 624(r1)
; LE-P8-O0-NEXT: hashst r0, -488(r1)
; LE-P8-O0-NEXT: std r14, 320(r1) # 8-byte Folded Spill ; LE-P8-O0-NEXT: std r14, 320(r1) # 8-byte Folded Spill
; LE-P8-O0-NEXT: std r15, 328(r1) # 8-byte Folded Spill ; LE-P8-O0-NEXT: std r15, 328(r1) # 8-byte Folded Spill
; LE-P8-O0-NEXT: std r16, 336(r1) # 8-byte Folded Spill ; LE-P8-O0-NEXT: std r16, 336(r1) # 8-byte Folded Spill
; LE-P8-O0-NEXT: std r17, 344(r1) # 8-byte Folded Spill ; LE-P8-O0-NEXT: std r17, 344(r1) # 8-byte Folded Spill
; LE-P8-O0-NEXT: std r18, 352(r1) # 8-byte Folded Spill ; LE-P8-O0-NEXT: std r18, 352(r1) # 8-byte Folded Spill
; LE-P8-O0-NEXT: std r19, 360(r1) # 8-byte Folded Spill ; LE-P8-O0-NEXT: std r19, 360(r1) # 8-byte Folded Spill
; LE-P8-O0-NEXT: std r20, 368(r1) # 8-byte Folded Spill ; LE-P8-O0-NEXT: std r20, 368(r1) # 8-byte Folded Spill
; LE-P8-O0-NEXT: std r21, 376(r1) # 8-byte Folded Spill ; LE-P8-O0-NEXT: std r21, 376(r1) # 8-byte Folded Spill
▲ Show 20 Lines • Show All 257 Lines • ▼ Show 20 Lines
; BE-P10-NEXT: hashchk r0, -488(r1) ; BE-P10-NEXT: hashchk r0, -488(r1)
; BE-P10-NEXT: mtocrf 32, r12 ; BE-P10-NEXT: mtocrf 32, r12
; BE-P10-NEXT: mtocrf 16, r12 ; BE-P10-NEXT: mtocrf 16, r12
; BE-P10-NEXT: mtocrf 8, r12 ; BE-P10-NEXT: mtocrf 8, r12
; BE-P10-NEXT: blr ; BE-P10-NEXT: blr
; ;
; BE-P9-LABEL: spill: ; BE-P9-LABEL: spill:
; BE-P9: # %bb.0: # %entry ; BE-P9: # %bb.0: # %entry
; BE-P9-NEXT: mflr r0
; BE-P9-NEXT: mfcr r12 ; BE-P9-NEXT: mfcr r12
; BE-P9-NEXT: std r0, 16(r1) ; BE-P9-NEXT: mflr r0
; BE-P9-NEXT: hashst r0, -488(r1)
; BE-P9-NEXT: stw r12, 8(r1) ; BE-P9-NEXT: stw r12, 8(r1)
; BE-P9-NEXT: stdu r1, -624(r1) ; BE-P9-NEXT: stdu r1, -624(r1)
; BE-P9-NEXT: lwz r4, 12(r3) ; BE-P9-NEXT: std r0, 640(r1)
; BE-P9-NEXT: hashst r0, -488(r1)
; BE-P9-NEXT: std r14, 336(r1) # 8-byte Folded Spill ; BE-P9-NEXT: std r14, 336(r1) # 8-byte Folded Spill
; BE-P9-NEXT: std r15, 344(r1) # 8-byte Folded Spill
; BE-P9-NEXT: stxv v20, 144(r1) # 16-byte Folded Spill ; BE-P9-NEXT: stxv v20, 144(r1) # 16-byte Folded Spill
; BE-P9-NEXT: stxv v21, 160(r1) # 16-byte Folded Spill ; BE-P9-NEXT: stxv v21, 160(r1) # 16-byte Folded Spill
; BE-P9-NEXT: lwz r4, 12(r3)
; BE-P9-NEXT: std r15, 344(r1) # 8-byte Folded Spill
; BE-P9-NEXT: stxv v22, 176(r1) # 16-byte Folded Spill ; BE-P9-NEXT: stxv v22, 176(r1) # 16-byte Folded Spill
; BE-P9-NEXT: std r16, 352(r1) # 8-byte Folded Spill ; BE-P9-NEXT: std r16, 352(r1) # 8-byte Folded Spill
; BE-P9-NEXT: std r17, 360(r1) # 8-byte Folded Spill
; BE-P9-NEXT: stxv v23, 192(r1) # 16-byte Folded Spill ; BE-P9-NEXT: stxv v23, 192(r1) # 16-byte Folded Spill
; BE-P9-NEXT: std r18, 368(r1) # 8-byte Folded Spill ; BE-P9-NEXT: std r17, 360(r1) # 8-byte Folded Spill
; BE-P9-NEXT: stxv v24, 208(r1) # 16-byte Folded Spill ; BE-P9-NEXT: stxv v24, 208(r1) # 16-byte Folded Spill
; BE-P9-NEXT: std r19, 376(r1) # 8-byte Folded Spill ; BE-P9-NEXT: std r18, 368(r1) # 8-byte Folded Spill
; BE-P9-NEXT: stxv v25, 224(r1) # 16-byte Folded Spill ; BE-P9-NEXT: stxv v25, 224(r1) # 16-byte Folded Spill
; BE-P9-NEXT: std r19, 376(r1) # 8-byte Folded Spill
; BE-P9-NEXT: std r20, 384(r1) # 8-byte Folded Spill ; BE-P9-NEXT: std r20, 384(r1) # 8-byte Folded Spill
; BE-P9-NEXT: std r21, 392(r1) # 8-byte Folded Spill
; BE-P9-NEXT: stxv v26, 240(r1) # 16-byte Folded Spill ; BE-P9-NEXT: stxv v26, 240(r1) # 16-byte Folded Spill
; BE-P9-NEXT: std r22, 400(r1) # 8-byte Folded Spill ; BE-P9-NEXT: std r21, 392(r1) # 8-byte Folded Spill
; BE-P9-NEXT: stxv v27, 256(r1) # 16-byte Folded Spill ; BE-P9-NEXT: stxv v27, 256(r1) # 16-byte Folded Spill
; BE-P9-NEXT: std r23, 408(r1) # 8-byte Folded Spill ; BE-P9-NEXT: std r22, 400(r1) # 8-byte Folded Spill
; BE-P9-NEXT: stxv v28, 272(r1) # 16-byte Folded Spill ; BE-P9-NEXT: stxv v28, 272(r1) # 16-byte Folded Spill
; BE-P9-NEXT: std r23, 408(r1) # 8-byte Folded Spill
; BE-P9-NEXT: std r24, 416(r1) # 8-byte Folded Spill ; BE-P9-NEXT: std r24, 416(r1) # 8-byte Folded Spill
; BE-P9-NEXT: std r25, 424(r1) # 8-byte Folded Spill
; BE-P9-NEXT: stxv v29, 288(r1) # 16-byte Folded Spill ; BE-P9-NEXT: stxv v29, 288(r1) # 16-byte Folded Spill
; BE-P9-NEXT: std r26, 432(r1) # 8-byte Folded Spill ; BE-P9-NEXT: std r25, 424(r1) # 8-byte Folded Spill
; BE-P9-NEXT: stxv v30, 304(r1) # 16-byte Folded Spill ; BE-P9-NEXT: stxv v30, 304(r1) # 16-byte Folded Spill
; BE-P9-NEXT: std r27, 440(r1) # 8-byte Folded Spill ; BE-P9-NEXT: std r26, 432(r1) # 8-byte Folded Spill
; BE-P9-NEXT: stxv v31, 320(r1) # 16-byte Folded Spill ; BE-P9-NEXT: stxv v31, 320(r1) # 16-byte Folded Spill
; BE-P9-NEXT: std r27, 440(r1) # 8-byte Folded Spill
; BE-P9-NEXT: std r28, 448(r1) # 8-byte Folded Spill ; BE-P9-NEXT: std r28, 448(r1) # 8-byte Folded Spill
; BE-P9-NEXT: std r29, 456(r1) # 8-byte Folded Spill ; BE-P9-NEXT: std r29, 456(r1) # 8-byte Folded Spill
; BE-P9-NEXT: std r30, 464(r1) # 8-byte Folded Spill ; BE-P9-NEXT: std r30, 464(r1) # 8-byte Folded Spill
; BE-P9-NEXT: std r31, 472(r1) # 8-byte Folded Spill ; BE-P9-NEXT: std r31, 472(r1) # 8-byte Folded Spill
; BE-P9-NEXT: stfd f14, 480(r1) # 8-byte Folded Spill ; BE-P9-NEXT: stfd f14, 480(r1) # 8-byte Folded Spill
; BE-P9-NEXT: stfd f15, 488(r1) # 8-byte Folded Spill ; BE-P9-NEXT: stfd f15, 488(r1) # 8-byte Folded Spill
; BE-P9-NEXT: stfd f16, 496(r1) # 8-byte Folded Spill ; BE-P9-NEXT: stfd f16, 496(r1) # 8-byte Folded Spill
; BE-P9-NEXT: stfd f17, 504(r1) # 8-byte Folded Spill ; BE-P9-NEXT: stfd f17, 504(r1) # 8-byte Folded Spill
▲ Show 20 Lines • Show All 80 Lines • ▼ Show 20 Lines
; BE-P9-NEXT: mtocrf 16, r12 ; BE-P9-NEXT: mtocrf 16, r12
; BE-P9-NEXT: mtocrf 8, r12 ; BE-P9-NEXT: mtocrf 8, r12
; BE-P9-NEXT: blr ; BE-P9-NEXT: blr
; ;
; BE-P8-LABEL: spill: ; BE-P8-LABEL: spill:
; BE-P8: # %bb.0: # %entry ; BE-P8: # %bb.0: # %entry
; BE-P8-NEXT: mfcr r12 ; BE-P8-NEXT: mfcr r12
; BE-P8-NEXT: mflr r0 ; BE-P8-NEXT: mflr r0
; BE-P8-NEXT: std r0, 16(r1)
; BE-P8-NEXT: hashst r0, -488(r1)
; BE-P8-NEXT: stw r12, 8(r1) ; BE-P8-NEXT: stw r12, 8(r1)
; BE-P8-NEXT: stdu r1, -624(r1) ; BE-P8-NEXT: stdu r1, -624(r1)
; BE-P8-NEXT: li r4, 144 ; BE-P8-NEXT: li r4, 144
; BE-P8-NEXT: std r0, 640(r1)
; BE-P8-NEXT: hashst r0, -488(r1)
; BE-P8-NEXT: std r14, 336(r1) # 8-byte Folded Spill ; BE-P8-NEXT: std r14, 336(r1) # 8-byte Folded Spill
; BE-P8-NEXT: std r15, 344(r1) # 8-byte Folded Spill ; BE-P8-NEXT: std r15, 344(r1) # 8-byte Folded Spill
; BE-P8-NEXT: std r16, 352(r1) # 8-byte Folded Spill ; BE-P8-NEXT: std r16, 352(r1) # 8-byte Folded Spill
; BE-P8-NEXT: std r17, 360(r1) # 8-byte Folded Spill
; BE-P8-NEXT: stxvd2x v20, r1, r4 # 16-byte Folded Spill ; BE-P8-NEXT: stxvd2x v20, r1, r4 # 16-byte Folded Spill
; BE-P8-NEXT: li r4, 160 ; BE-P8-NEXT: li r4, 160
; BE-P8-NEXT: std r17, 360(r1) # 8-byte Folded Spill
; BE-P8-NEXT: std r18, 368(r1) # 8-byte Folded Spill ; BE-P8-NEXT: std r18, 368(r1) # 8-byte Folded Spill
; BE-P8-NEXT: std r19, 376(r1) # 8-byte Folded Spill ; BE-P8-NEXT: std r19, 376(r1) # 8-byte Folded Spill
; BE-P8-NEXT: std r20, 384(r1) # 8-byte Folded Spill ; BE-P8-NEXT: std r20, 384(r1) # 8-byte Folded Spill
; BE-P8-NEXT: std r21, 392(r1) # 8-byte Folded Spill
; BE-P8-NEXT: stxvd2x v21, r1, r4 # 16-byte Folded Spill ; BE-P8-NEXT: stxvd2x v21, r1, r4 # 16-byte Folded Spill
; BE-P8-NEXT: li r4, 176 ; BE-P8-NEXT: li r4, 176
; BE-P8-NEXT: std r21, 392(r1) # 8-byte Folded Spill
; BE-P8-NEXT: std r22, 400(r1) # 8-byte Folded Spill ; BE-P8-NEXT: std r22, 400(r1) # 8-byte Folded Spill
; BE-P8-NEXT: std r23, 408(r1) # 8-byte Folded Spill ; BE-P8-NEXT: std r23, 408(r1) # 8-byte Folded Spill
; BE-P8-NEXT: std r24, 416(r1) # 8-byte Folded Spill ; BE-P8-NEXT: std r24, 416(r1) # 8-byte Folded Spill
; BE-P8-NEXT: std r25, 424(r1) # 8-byte Folded Spill ; BE-P8-NEXT: std r25, 424(r1) # 8-byte Folded Spill
; BE-P8-NEXT: std r26, 432(r1) # 8-byte Folded Spill ; BE-P8-NEXT: std r26, 432(r1) # 8-byte Folded Spill
; BE-P8-NEXT: std r27, 440(r1) # 8-byte Folded Spill ; BE-P8-NEXT: std r27, 440(r1) # 8-byte Folded Spill
; BE-P8-NEXT: std r28, 448(r1) # 8-byte Folded Spill ; BE-P8-NEXT: std r28, 448(r1) # 8-byte Folded Spill
; BE-P8-NEXT: std r29, 456(r1) # 8-byte Folded Spill ; BE-P8-NEXT: std r29, 456(r1) # 8-byte Folded Spill
; BE-P8-NEXT: std r30, 464(r1) # 8-byte Folded Spill ; BE-P8-NEXT: std r30, 464(r1) # 8-byte Folded Spill
; BE-P8-NEXT: std r31, 472(r1) # 8-byte Folded Spill ; BE-P8-NEXT: std r31, 472(r1) # 8-byte Folded Spill
; BE-P8-NEXT: std r3, 120(r1) # 8-byte Folded Spill ; BE-P8-NEXT: std r3, 120(r1) # 8-byte Folded Spill
; BE-P8-NEXT: stxvd2x v22, r1, r4 # 16-byte Folded Spill ; BE-P8-NEXT: stxvd2x v22, r1, r4 # 16-byte Folded Spill
; BE-P8-NEXT: li r4, 192 ; BE-P8-NEXT: li r4, 192
; BE-P8-NEXT: stfd f14, 480(r1) # 8-byte Folded Spill
; BE-P8-NEXT: stxvd2x v23, r1, r4 # 16-byte Folded Spill ; BE-P8-NEXT: stxvd2x v23, r1, r4 # 16-byte Folded Spill
; BE-P8-NEXT: li r4, 208 ; BE-P8-NEXT: li r4, 208
; BE-P8-NEXT: stfd f14, 480(r1) # 8-byte Folded Spill ; BE-P8-NEXT: stfd f15, 488(r1) # 8-byte Folded Spill
; BE-P8-NEXT: stxvd2x v24, r1, r4 # 16-byte Folded Spill ; BE-P8-NEXT: stxvd2x v24, r1, r4 # 16-byte Folded Spill
; BE-P8-NEXT: li r4, 224 ; BE-P8-NEXT: li r4, 224
; BE-P8-NEXT: stfd f15, 488(r1) # 8-byte Folded Spill ; BE-P8-NEXT: stfd f16, 496(r1) # 8-byte Folded Spill
; BE-P8-NEXT: stxvd2x v25, r1, r4 # 16-byte Folded Spill ; BE-P8-NEXT: stxvd2x v25, r1, r4 # 16-byte Folded Spill
; BE-P8-NEXT: li r4, 240 ; BE-P8-NEXT: li r4, 240
; BE-P8-NEXT: stfd f16, 496(r1) # 8-byte Folded Spill ; BE-P8-NEXT: stfd f17, 504(r1) # 8-byte Folded Spill
; BE-P8-NEXT: stxvd2x v26, r1, r4 # 16-byte Folded Spill ; BE-P8-NEXT: stxvd2x v26, r1, r4 # 16-byte Folded Spill
; BE-P8-NEXT: li r4, 256 ; BE-P8-NEXT: li r4, 256
; BE-P8-NEXT: stfd f17, 504(r1) # 8-byte Folded Spill ; BE-P8-NEXT: stfd f18, 512(r1) # 8-byte Folded Spill
; BE-P8-NEXT: stxvd2x v27, r1, r4 # 16-byte Folded Spill ; BE-P8-NEXT: stxvd2x v27, r1, r4 # 16-byte Folded Spill
; BE-P8-NEXT: li r4, 272 ; BE-P8-NEXT: li r4, 272
; BE-P8-NEXT: stfd f18, 512(r1) # 8-byte Folded Spill ; BE-P8-NEXT: stfd f19, 520(r1) # 8-byte Folded Spill
; BE-P8-NEXT: stxvd2x v28, r1, r4 # 16-byte Folded Spill ; BE-P8-NEXT: stxvd2x v28, r1, r4 # 16-byte Folded Spill
; BE-P8-NEXT: li r4, 288 ; BE-P8-NEXT: li r4, 288
; BE-P8-NEXT: stfd f19, 520(r1) # 8-byte Folded Spill ; BE-P8-NEXT: stfd f20, 528(r1) # 8-byte Folded Spill
; BE-P8-NEXT: stxvd2x v29, r1, r4 # 16-byte Folded Spill ; BE-P8-NEXT: stxvd2x v29, r1, r4 # 16-byte Folded Spill
; BE-P8-NEXT: li r4, 304 ; BE-P8-NEXT: li r4, 304
; BE-P8-NEXT: stfd f20, 528(r1) # 8-byte Folded Spill ; BE-P8-NEXT: stfd f21, 536(r1) # 8-byte Folded Spill
; BE-P8-NEXT: stxvd2x v30, r1, r4 # 16-byte Folded Spill ; BE-P8-NEXT: stxvd2x v30, r1, r4 # 16-byte Folded Spill
; BE-P8-NEXT: li r4, 320 ; BE-P8-NEXT: li r4, 320
; BE-P8-NEXT: stfd f21, 536(r1) # 8-byte Folded Spill ; BE-P8-NEXT: stfd f22, 544(r1) # 8-byte Folded Spill
; BE-P8-NEXT: stxvd2x v31, r1, r4 # 16-byte Folded Spill ; BE-P8-NEXT: stxvd2x v31, r1, r4 # 16-byte Folded Spill
; BE-P8-NEXT: lwz r4, 12(r3) ; BE-P8-NEXT: lwz r4, 12(r3)
; BE-P8-NEXT: stfd f22, 544(r1) # 8-byte Folded Spill
; BE-P8-NEXT: stfd f23, 552(r1) # 8-byte Folded Spill ; BE-P8-NEXT: stfd f23, 552(r1) # 8-byte Folded Spill
; BE-P8-NEXT: stfd f24, 560(r1) # 8-byte Folded Spill ; BE-P8-NEXT: stfd f24, 560(r1) # 8-byte Folded Spill
; BE-P8-NEXT: stfd f25, 568(r1) # 8-byte Folded Spill ; BE-P8-NEXT: stfd f25, 568(r1) # 8-byte Folded Spill
; BE-P8-NEXT: stfd f26, 576(r1) # 8-byte Folded Spill ; BE-P8-NEXT: stfd f26, 576(r1) # 8-byte Folded Spill
; BE-P8-NEXT: stfd f27, 584(r1) # 8-byte Folded Spill ; BE-P8-NEXT: stfd f27, 584(r1) # 8-byte Folded Spill
; BE-P8-NEXT: stfd f28, 592(r1) # 8-byte Folded Spill ; BE-P8-NEXT: stfd f28, 592(r1) # 8-byte Folded Spill
; BE-P8-NEXT: stfd f29, 600(r1) # 8-byte Folded Spill ; BE-P8-NEXT: stfd f29, 600(r1) # 8-byte Folded Spill
; BE-P8-NEXT: stfd f30, 608(r1) # 8-byte Folded Spill ; BE-P8-NEXT: stfd f30, 608(r1) # 8-byte Folded Spill
▲ Show 20 Lines • Show All 202 Lines • ▼ Show 20 Lines
; BE-32BIT-P10-NEXT: addi r1, r1, 448 ; BE-32BIT-P10-NEXT: addi r1, r1, 448
; BE-32BIT-P10-NEXT: hashchk r0, -424(r1) ; BE-32BIT-P10-NEXT: hashchk r0, -424(r1)
; BE-32BIT-P10-NEXT: mtlr r0 ; BE-32BIT-P10-NEXT: mtlr r0
; BE-32BIT-P10-NEXT: blr ; BE-32BIT-P10-NEXT: blr
; ;
; BE-32BIT-P9-LABEL: spill: ; BE-32BIT-P9-LABEL: spill:
; BE-32BIT-P9: # %bb.0: # %entry ; BE-32BIT-P9: # %bb.0: # %entry
; BE-32BIT-P9-NEXT: mflr r0 ; BE-32BIT-P9-NEXT: mflr r0
; BE-32BIT-P9-NEXT: stw r0, 4(r1)
; BE-32BIT-P9-NEXT: hashst r0, -424(r1)
; BE-32BIT-P9-NEXT: stwu r1, -448(r1) ; BE-32BIT-P9-NEXT: stwu r1, -448(r1)
; BE-32BIT-P9-NEXT: mfcr r12 ; BE-32BIT-P9-NEXT: mfcr r12
; BE-32BIT-P9-NEXT: stw r0, 452(r1)
; BE-32BIT-P9-NEXT: hashst r0, -424(r1)
; BE-32BIT-P9-NEXT: stw r14, 232(r1) # 4-byte Folded Spill ; BE-32BIT-P9-NEXT: stw r14, 232(r1) # 4-byte Folded Spill
; BE-32BIT-P9-NEXT: stw r15, 236(r1) # 4-byte Folded Spill ; BE-32BIT-P9-NEXT: stw r15, 236(r1) # 4-byte Folded Spill
; BE-32BIT-P9-NEXT: stw r16, 240(r1) # 4-byte Folded Spill ; BE-32BIT-P9-NEXT: stw r16, 240(r1) # 4-byte Folded Spill
; BE-32BIT-P9-NEXT: stw r17, 244(r1) # 4-byte Folded Spill ; BE-32BIT-P9-NEXT: stw r17, 244(r1) # 4-byte Folded Spill
; BE-32BIT-P9-NEXT: stw r18, 248(r1) # 4-byte Folded Spill ; BE-32BIT-P9-NEXT: stw r18, 248(r1) # 4-byte Folded Spill
; BE-32BIT-P9-NEXT: stw r19, 252(r1) # 4-byte Folded Spill ; BE-32BIT-P9-NEXT: stw r19, 252(r1) # 4-byte Folded Spill
; BE-32BIT-P9-NEXT: stw r20, 256(r1) # 4-byte Folded Spill ; BE-32BIT-P9-NEXT: stw r20, 256(r1) # 4-byte Folded Spill
; BE-32BIT-P9-NEXT: stw r21, 260(r1) # 4-byte Folded Spill ; BE-32BIT-P9-NEXT: stw r21, 260(r1) # 4-byte Folded Spill
▲ Show 20 Lines • Show All 105 Lines • ▼ Show 20 Lines
; BE-32BIT-P9-NEXT: addi r1, r1, 448 ; BE-32BIT-P9-NEXT: addi r1, r1, 448
; BE-32BIT-P9-NEXT: mtlr r0 ; BE-32BIT-P9-NEXT: mtlr r0
; BE-32BIT-P9-NEXT: hashchk r0, -424(r1) ; BE-32BIT-P9-NEXT: hashchk r0, -424(r1)
; BE-32BIT-P9-NEXT: blr ; BE-32BIT-P9-NEXT: blr
; ;
; BE-32BIT-P8-LABEL: spill: ; BE-32BIT-P8-LABEL: spill:
; BE-32BIT-P8: # %bb.0: # %entry ; BE-32BIT-P8: # %bb.0: # %entry
; BE-32BIT-P8-NEXT: mflr r0 ; BE-32BIT-P8-NEXT: mflr r0
; BE-32BIT-P8-NEXT: stw r0, 4(r1)
; BE-32BIT-P8-NEXT: hashst r0, -424(r1)
; BE-32BIT-P8-NEXT: stwu r1, -448(r1) ; BE-32BIT-P8-NEXT: stwu r1, -448(r1)
; BE-32BIT-P8-NEXT: mfcr r12 ; BE-32BIT-P8-NEXT: mfcr r12
; BE-32BIT-P8-NEXT: li r4, 32 ; BE-32BIT-P8-NEXT: li r4, 32
; BE-32BIT-P8-NEXT: stw r0, 452(r1)
; BE-32BIT-P8-NEXT: hashst r0, -424(r1)
; BE-32BIT-P8-NEXT: stw r14, 232(r1) # 4-byte Folded Spill ; BE-32BIT-P8-NEXT: stw r14, 232(r1) # 4-byte Folded Spill
; BE-32BIT-P8-NEXT: stw r15, 236(r1) # 4-byte Folded Spill ; BE-32BIT-P8-NEXT: stw r15, 236(r1) # 4-byte Folded Spill
; BE-32BIT-P8-NEXT: stw r16, 240(r1) # 4-byte Folded Spill ; BE-32BIT-P8-NEXT: stw r16, 240(r1) # 4-byte Folded Spill
; BE-32BIT-P8-NEXT: stw r17, 244(r1) # 4-byte Folded Spill ; BE-32BIT-P8-NEXT: stw r17, 244(r1) # 4-byte Folded Spill
; BE-32BIT-P8-NEXT: stw r18, 248(r1) # 4-byte Folded Spill ; BE-32BIT-P8-NEXT: stw r18, 248(r1) # 4-byte Folded Spill
; BE-32BIT-P8-NEXT: stw r19, 252(r1) # 4-byte Folded Spill ; BE-32BIT-P8-NEXT: stw r19, 252(r1) # 4-byte Folded Spill
; BE-32BIT-P8-NEXT: stw r20, 256(r1) # 4-byte Folded Spill ; BE-32BIT-P8-NEXT: stw r20, 256(r1) # 4-byte Folded Spill
; BE-32BIT-P8-NEXT: stw r21, 260(r1) # 4-byte Folded Spill ; BE-32BIT-P8-NEXT: stw r21, 260(r1) # 4-byte Folded Spill
; BE-32BIT-P8-NEXT: stw r22, 264(r1) # 4-byte Folded Spill ; BE-32BIT-P8-NEXT: stw r22, 264(r1) # 4-byte Folded Spill
; BE-32BIT-P8-NEXT: stw r23, 268(r1) # 4-byte Folded Spill ; BE-32BIT-P8-NEXT: stw r23, 268(r1) # 4-byte Folded Spill
; BE-32BIT-P8-NEXT: stw r24, 272(r1) # 4-byte Folded Spill ; BE-32BIT-P8-NEXT: stw r24, 272(r1) # 4-byte Folded Spill
; BE-32BIT-P8-NEXT: stw r25, 276(r1) # 4-byte Folded Spill ; BE-32BIT-P8-NEXT: stw r25, 276(r1) # 4-byte Folded Spill
; BE-32BIT-P8-NEXT: stw r26, 280(r1) # 4-byte Folded Spill ; BE-32BIT-P8-NEXT: stw r26, 280(r1) # 4-byte Folded Spill
; BE-32BIT-P8-NEXT: stw r27, 284(r1) # 4-byte Folded Spill ; BE-32BIT-P8-NEXT: stw r27, 284(r1) # 4-byte Folded Spill
; BE-32BIT-P8-NEXT: stw r28, 288(r1) # 4-byte Folded Spill ; BE-32BIT-P8-NEXT: stw r28, 288(r1) # 4-byte Folded Spill
; BE-32BIT-P8-NEXT: stw r29, 292(r1) # 4-byte Folded Spill ; BE-32BIT-P8-NEXT: stw r29, 292(r1) # 4-byte Folded Spill
; BE-32BIT-P8-NEXT: stw r30, 296(r1) # 4-byte Folded Spill ; BE-32BIT-P8-NEXT: stw r30, 296(r1) # 4-byte Folded Spill
; BE-32BIT-P8-NEXT: stw r31, 300(r1) # 4-byte Folded Spill ; BE-32BIT-P8-NEXT: stw r31, 300(r1) # 4-byte Folded Spill
; BE-32BIT-P8-NEXT: stw r12, 228(r1) ; BE-32BIT-P8-NEXT: stw r12, 228(r1)
; BE-32BIT-P8-NEXT: stxvd2x v20, r1, r4 # 16-byte Folded Spill ; BE-32BIT-P8-NEXT: stxvd2x v20, r1, r4 # 16-byte Folded Spill
; BE-32BIT-P8-NEXT: li r4, 48 ; BE-32BIT-P8-NEXT: li r4, 48
; BE-32BIT-P8-NEXT: stfd f14, 304(r1) # 8-byte Folded Spill
; BE-32BIT-P8-NEXT: stxvd2x v21, r1, r4 # 16-byte Folded Spill ; BE-32BIT-P8-NEXT: stxvd2x v21, r1, r4 # 16-byte Folded Spill
; BE-32BIT-P8-NEXT: li r4, 64 ; BE-32BIT-P8-NEXT: li r4, 64
; BE-32BIT-P8-NEXT: stfd f14, 304(r1) # 8-byte Folded Spill ; BE-32BIT-P8-NEXT: stfd f15, 312(r1) # 8-byte Folded Spill
; BE-32BIT-P8-NEXT: stxvd2x v22, r1, r4 # 16-byte Folded Spill ; BE-32BIT-P8-NEXT: stxvd2x v22, r1, r4 # 16-byte Folded Spill
; BE-32BIT-P8-NEXT: li r4, 80 ; BE-32BIT-P8-NEXT: li r4, 80
; BE-32BIT-P8-NEXT: stfd f15, 312(r1) # 8-byte Folded Spill ; BE-32BIT-P8-NEXT: stfd f16, 320(r1) # 8-byte Folded Spill
; BE-32BIT-P8-NEXT: stxvd2x v23, r1, r4 # 16-byte Folded Spill ; BE-32BIT-P8-NEXT: stxvd2x v23, r1, r4 # 16-byte Folded Spill
; BE-32BIT-P8-NEXT: li r4, 96 ; BE-32BIT-P8-NEXT: li r4, 96
; BE-32BIT-P8-NEXT: stfd f16, 320(r1) # 8-byte Folded Spill ; BE-32BIT-P8-NEXT: stfd f17, 328(r1) # 8-byte Folded Spill
; BE-32BIT-P8-NEXT: stxvd2x v24, r1, r4 # 16-byte Folded Spill ; BE-32BIT-P8-NEXT: stxvd2x v24, r1, r4 # 16-byte Folded Spill
; BE-32BIT-P8-NEXT: li r4, 112 ; BE-32BIT-P8-NEXT: li r4, 112
; BE-32BIT-P8-NEXT: stfd f17, 328(r1) # 8-byte Folded Spill ; BE-32BIT-P8-NEXT: stfd f18, 336(r1) # 8-byte Folded Spill
; BE-32BIT-P8-NEXT: stxvd2x v25, r1, r4 # 16-byte Folded Spill ; BE-32BIT-P8-NEXT: stxvd2x v25, r1, r4 # 16-byte Folded Spill
; BE-32BIT-P8-NEXT: li r4, 128 ; BE-32BIT-P8-NEXT: li r4, 128
; BE-32BIT-P8-NEXT: stfd f18, 336(r1) # 8-byte Folded Spill ; BE-32BIT-P8-NEXT: stfd f19, 344(r1) # 8-byte Folded Spill
; BE-32BIT-P8-NEXT: stxvd2x v26, r1, r4 # 16-byte Folded Spill ; BE-32BIT-P8-NEXT: stxvd2x v26, r1, r4 # 16-byte Folded Spill
; BE-32BIT-P8-NEXT: li r4, 144 ; BE-32BIT-P8-NEXT: li r4, 144
; BE-32BIT-P8-NEXT: stfd f19, 344(r1) # 8-byte Folded Spill ; BE-32BIT-P8-NEXT: stfd f20, 352(r1) # 8-byte Folded Spill
; BE-32BIT-P8-NEXT: stxvd2x v27, r1, r4 # 16-byte Folded Spill ; BE-32BIT-P8-NEXT: stxvd2x v27, r1, r4 # 16-byte Folded Spill
; BE-32BIT-P8-NEXT: li r4, 160 ; BE-32BIT-P8-NEXT: li r4, 160
; BE-32BIT-P8-NEXT: stfd f20, 352(r1) # 8-byte Folded Spill ; BE-32BIT-P8-NEXT: stfd f21, 360(r1) # 8-byte Folded Spill
; BE-32BIT-P8-NEXT: stxvd2x v28, r1, r4 # 16-byte Folded Spill ; BE-32BIT-P8-NEXT: stxvd2x v28, r1, r4 # 16-byte Folded Spill
; BE-32BIT-P8-NEXT: li r4, 176 ; BE-32BIT-P8-NEXT: li r4, 176
; BE-32BIT-P8-NEXT: stfd f21, 360(r1) # 8-byte Folded Spill ; BE-32BIT-P8-NEXT: stfd f22, 368(r1) # 8-byte Folded Spill
; BE-32BIT-P8-NEXT: stxvd2x v29, r1, r4 # 16-byte Folded Spill ; BE-32BIT-P8-NEXT: stxvd2x v29, r1, r4 # 16-byte Folded Spill
; BE-32BIT-P8-NEXT: li r4, 192 ; BE-32BIT-P8-NEXT: li r4, 192
; BE-32BIT-P8-NEXT: stfd f22, 368(r1) # 8-byte Folded Spill ; BE-32BIT-P8-NEXT: stfd f23, 376(r1) # 8-byte Folded Spill
; BE-32BIT-P8-NEXT: stxvd2x v30, r1, r4 # 16-byte Folded Spill ; BE-32BIT-P8-NEXT: stxvd2x v30, r1, r4 # 16-byte Folded Spill
; BE-32BIT-P8-NEXT: li r4, 208 ; BE-32BIT-P8-NEXT: li r4, 208
; BE-32BIT-P8-NEXT: stfd f23, 376(r1) # 8-byte Folded Spill ; BE-32BIT-P8-NEXT: stfd f24, 384(r1) # 8-byte Folded Spill
; BE-32BIT-P8-NEXT: stxvd2x v31, r1, r4 # 16-byte Folded Spill ; BE-32BIT-P8-NEXT: stxvd2x v31, r1, r4 # 16-byte Folded Spill
; BE-32BIT-P8-NEXT: lwz r4, 12(r3) ; BE-32BIT-P8-NEXT: lwz r4, 12(r3)
; BE-32BIT-P8-NEXT: stfd f24, 384(r1) # 8-byte Folded Spill
; BE-32BIT-P8-NEXT: stfd f25, 392(r1) # 8-byte Folded Spill ; BE-32BIT-P8-NEXT: stfd f25, 392(r1) # 8-byte Folded Spill
; BE-32BIT-P8-NEXT: stfd f26, 400(r1) # 8-byte Folded Spill ; BE-32BIT-P8-NEXT: stfd f26, 400(r1) # 8-byte Folded Spill
; BE-32BIT-P8-NEXT: stfd f27, 408(r1) # 8-byte Folded Spill ; BE-32BIT-P8-NEXT: stfd f27, 408(r1) # 8-byte Folded Spill
; BE-32BIT-P8-NEXT: stfd f28, 416(r1) # 8-byte Folded Spill ; BE-32BIT-P8-NEXT: stfd f28, 416(r1) # 8-byte Folded Spill
; BE-32BIT-P8-NEXT: stfd f29, 424(r1) # 8-byte Folded Spill ; BE-32BIT-P8-NEXT: stfd f29, 424(r1) # 8-byte Folded Spill
; BE-32BIT-P8-NEXT: stfd f30, 432(r1) # 8-byte Folded Spill ; BE-32BIT-P8-NEXT: stfd f30, 432(r1) # 8-byte Folded Spill
; BE-32BIT-P8-NEXT: stfd f31, 440(r1) # 8-byte Folded Spill ; BE-32BIT-P8-NEXT: stfd f31, 440(r1) # 8-byte Folded Spill
; BE-32BIT-P8-NEXT: stw r3, 16(r1) # 4-byte Folded Spill ; BE-32BIT-P8-NEXT: stw r3, 16(r1) # 4-byte Folded Spill
▲ Show 20 Lines • Show All 199 Lines • ▼ Show 20 Lines
; LE-P10-PRIV-NEXT: hashchkp r0, -488(r1) ; LE-P10-PRIV-NEXT: hashchkp r0, -488(r1)
; LE-P10-PRIV-NEXT: mtocrf 32, r12 ; LE-P10-PRIV-NEXT: mtocrf 32, r12
; LE-P10-PRIV-NEXT: mtocrf 16, r12 ; LE-P10-PRIV-NEXT: mtocrf 16, r12
; LE-P10-PRIV-NEXT: mtocrf 8, r12 ; LE-P10-PRIV-NEXT: mtocrf 8, r12
; LE-P10-PRIV-NEXT: blr ; LE-P10-PRIV-NEXT: blr
; ;
; LE-P9-PRIV-LABEL: spill: ; LE-P9-PRIV-LABEL: spill:
; LE-P9-PRIV: # %bb.0: # %entry ; LE-P9-PRIV: # %bb.0: # %entry
; LE-P9-PRIV-NEXT: mflr r0
; LE-P9-PRIV-NEXT: mfcr r12 ; LE-P9-PRIV-NEXT: mfcr r12
; LE-P9-PRIV-NEXT: std r0, 16(r1) ; LE-P9-PRIV-NEXT: mflr r0
; LE-P9-PRIV-NEXT: hashstp r0, -488(r1)
; LE-P9-PRIV-NEXT: stw r12, 8(r1) ; LE-P9-PRIV-NEXT: stw r12, 8(r1)
; LE-P9-PRIV-NEXT: stdu r1, -544(r1) ; LE-P9-PRIV-NEXT: stdu r1, -544(r1)
; LE-P9-PRIV-NEXT: lwz r4, 12(r3) ; LE-P9-PRIV-NEXT: std r0, 560(r1)
; LE-P9-PRIV-NEXT: hashstp r0, -488(r1)
; LE-P9-PRIV-NEXT: std r14, 256(r1) # 8-byte Folded Spill ; LE-P9-PRIV-NEXT: std r14, 256(r1) # 8-byte Folded Spill
; LE-P9-PRIV-NEXT: std r15, 264(r1) # 8-byte Folded Spill
; LE-P9-PRIV-NEXT: stxv v20, 64(r1) # 16-byte Folded Spill ; LE-P9-PRIV-NEXT: stxv v20, 64(r1) # 16-byte Folded Spill
; LE-P9-PRIV-NEXT: stxv v21, 80(r1) # 16-byte Folded Spill ; LE-P9-PRIV-NEXT: stxv v21, 80(r1) # 16-byte Folded Spill
; LE-P9-PRIV-NEXT: lwz r4, 12(r3)
; LE-P9-PRIV-NEXT: std r15, 264(r1) # 8-byte Folded Spill
; LE-P9-PRIV-NEXT: stxv v22, 96(r1) # 16-byte Folded Spill ; LE-P9-PRIV-NEXT: stxv v22, 96(r1) # 16-byte Folded Spill
; LE-P9-PRIV-NEXT: std r16, 272(r1) # 8-byte Folded Spill ; LE-P9-PRIV-NEXT: std r16, 272(r1) # 8-byte Folded Spill
; LE-P9-PRIV-NEXT: std r17, 280(r1) # 8-byte Folded Spill
; LE-P9-PRIV-NEXT: stxv v23, 112(r1) # 16-byte Folded Spill ; LE-P9-PRIV-NEXT: stxv v23, 112(r1) # 16-byte Folded Spill
; LE-P9-PRIV-NEXT: std r18, 288(r1) # 8-byte Folded Spill ; LE-P9-PRIV-NEXT: std r17, 280(r1) # 8-byte Folded Spill
; LE-P9-PRIV-NEXT: stxv v24, 128(r1) # 16-byte Folded Spill ; LE-P9-PRIV-NEXT: stxv v24, 128(r1) # 16-byte Folded Spill
; LE-P9-PRIV-NEXT: std r19, 296(r1) # 8-byte Folded Spill ; LE-P9-PRIV-NEXT: std r18, 288(r1) # 8-byte Folded Spill
; LE-P9-PRIV-NEXT: stxv v25, 144(r1) # 16-byte Folded Spill ; LE-P9-PRIV-NEXT: stxv v25, 144(r1) # 16-byte Folded Spill
; LE-P9-PRIV-NEXT: std r19, 296(r1) # 8-byte Folded Spill
; LE-P9-PRIV-NEXT: std r20, 304(r1) # 8-byte Folded Spill ; LE-P9-PRIV-NEXT: std r20, 304(r1) # 8-byte Folded Spill
; LE-P9-PRIV-NEXT: std r21, 312(r1) # 8-byte Folded Spill
; LE-P9-PRIV-NEXT: stxv v26, 160(r1) # 16-byte Folded Spill ; LE-P9-PRIV-NEXT: stxv v26, 160(r1) # 16-byte Folded Spill
; LE-P9-PRIV-NEXT: std r22, 320(r1) # 8-byte Folded Spill ; LE-P9-PRIV-NEXT: std r21, 312(r1) # 8-byte Folded Spill
; LE-P9-PRIV-NEXT: stxv v27, 176(r1) # 16-byte Folded Spill ; LE-P9-PRIV-NEXT: stxv v27, 176(r1) # 16-byte Folded Spill
; LE-P9-PRIV-NEXT: std r23, 328(r1) # 8-byte Folded Spill ; LE-P9-PRIV-NEXT: std r22, 320(r1) # 8-byte Folded Spill
; LE-P9-PRIV-NEXT: stxv v28, 192(r1) # 16-byte Folded Spill ; LE-P9-PRIV-NEXT: stxv v28, 192(r1) # 16-byte Folded Spill
; LE-P9-PRIV-NEXT: std r23, 328(r1) # 8-byte Folded Spill
; LE-P9-PRIV-NEXT: std r24, 336(r1) # 8-byte Folded Spill ; LE-P9-PRIV-NEXT: std r24, 336(r1) # 8-byte Folded Spill
; LE-P9-PRIV-NEXT: std r25, 344(r1) # 8-byte Folded Spill
; LE-P9-PRIV-NEXT: stxv v29, 208(r1) # 16-byte Folded Spill ; LE-P9-PRIV-NEXT: stxv v29, 208(r1) # 16-byte Folded Spill
; LE-P9-PRIV-NEXT: std r26, 352(r1) # 8-byte Folded Spill ; LE-P9-PRIV-NEXT: std r25, 344(r1) # 8-byte Folded Spill
; LE-P9-PRIV-NEXT: stxv v30, 224(r1) # 16-byte Folded Spill ; LE-P9-PRIV-NEXT: stxv v30, 224(r1) # 16-byte Folded Spill
; LE-P9-PRIV-NEXT: std r27, 360(r1) # 8-byte Folded Spill ; LE-P9-PRIV-NEXT: std r26, 352(r1) # 8-byte Folded Spill
; LE-P9-PRIV-NEXT: stxv v31, 240(r1) # 16-byte Folded Spill ; LE-P9-PRIV-NEXT: stxv v31, 240(r1) # 16-byte Folded Spill
; LE-P9-PRIV-NEXT: std r27, 360(r1) # 8-byte Folded Spill
; LE-P9-PRIV-NEXT: std r28, 368(r1) # 8-byte Folded Spill ; LE-P9-PRIV-NEXT: std r28, 368(r1) # 8-byte Folded Spill
; LE-P9-PRIV-NEXT: std r29, 376(r1) # 8-byte Folded Spill ; LE-P9-PRIV-NEXT: std r29, 376(r1) # 8-byte Folded Spill
; LE-P9-PRIV-NEXT: std r30, 384(r1) # 8-byte Folded Spill ; LE-P9-PRIV-NEXT: std r30, 384(r1) # 8-byte Folded Spill
; LE-P9-PRIV-NEXT: std r31, 392(r1) # 8-byte Folded Spill ; LE-P9-PRIV-NEXT: std r31, 392(r1) # 8-byte Folded Spill
; LE-P9-PRIV-NEXT: stfd f14, 400(r1) # 8-byte Folded Spill ; LE-P9-PRIV-NEXT: stfd f14, 400(r1) # 8-byte Folded Spill
; LE-P9-PRIV-NEXT: stfd f15, 408(r1) # 8-byte Folded Spill ; LE-P9-PRIV-NEXT: stfd f15, 408(r1) # 8-byte Folded Spill
; LE-P9-PRIV-NEXT: stfd f16, 416(r1) # 8-byte Folded Spill ; LE-P9-PRIV-NEXT: stfd f16, 416(r1) # 8-byte Folded Spill
; LE-P9-PRIV-NEXT: stfd f17, 424(r1) # 8-byte Folded Spill ; LE-P9-PRIV-NEXT: stfd f17, 424(r1) # 8-byte Folded Spill
▲ Show 20 Lines • Show All 80 Lines • ▼ Show 20 Lines
; LE-P9-PRIV-NEXT: mtocrf 16, r12 ; LE-P9-PRIV-NEXT: mtocrf 16, r12
; LE-P9-PRIV-NEXT: mtocrf 8, r12 ; LE-P9-PRIV-NEXT: mtocrf 8, r12
; LE-P9-PRIV-NEXT: blr ; LE-P9-PRIV-NEXT: blr
; ;
; LE-P8-PRIV-LABEL: spill: ; LE-P8-PRIV-LABEL: spill:
; LE-P8-PRIV: # %bb.0: # %entry ; LE-P8-PRIV: # %bb.0: # %entry
; LE-P8-PRIV-NEXT: mfcr r12 ; LE-P8-PRIV-NEXT: mfcr r12
; LE-P8-PRIV-NEXT: mflr r0 ; LE-P8-PRIV-NEXT: mflr r0
; LE-P8-PRIV-NEXT: std r0, 16(r1)
; LE-P8-PRIV-NEXT: hashstp r0, -488(r1)
; LE-P8-PRIV-NEXT: stw r12, 8(r1) ; LE-P8-PRIV-NEXT: stw r12, 8(r1)
; LE-P8-PRIV-NEXT: stdu r1, -544(r1) ; LE-P8-PRIV-NEXT: stdu r1, -544(r1)
; LE-P8-PRIV-NEXT: li r4, 64 ; LE-P8-PRIV-NEXT: li r4, 64
; LE-P8-PRIV-NEXT: std r0, 560(r1)
; LE-P8-PRIV-NEXT: hashstp r0, -488(r1)
; LE-P8-PRIV-NEXT: std r14, 256(r1) # 8-byte Folded Spill ; LE-P8-PRIV-NEXT: std r14, 256(r1) # 8-byte Folded Spill
; LE-P8-PRIV-NEXT: std r15, 264(r1) # 8-byte Folded Spill ; LE-P8-PRIV-NEXT: std r15, 264(r1) # 8-byte Folded Spill
; LE-P8-PRIV-NEXT: std r16, 272(r1) # 8-byte Folded Spill ; LE-P8-PRIV-NEXT: std r16, 272(r1) # 8-byte Folded Spill
; LE-P8-PRIV-NEXT: std r17, 280(r1) # 8-byte Folded Spill
; LE-P8-PRIV-NEXT: stxvd2x v20, r1, r4 # 16-byte Folded Spill ; LE-P8-PRIV-NEXT: stxvd2x v20, r1, r4 # 16-byte Folded Spill
; LE-P8-PRIV-NEXT: li r4, 80 ; LE-P8-PRIV-NEXT: li r4, 80
; LE-P8-PRIV-NEXT: std r17, 280(r1) # 8-byte Folded Spill
; LE-P8-PRIV-NEXT: std r18, 288(r1) # 8-byte Folded Spill ; LE-P8-PRIV-NEXT: std r18, 288(r1) # 8-byte Folded Spill
; LE-P8-PRIV-NEXT: std r19, 296(r1) # 8-byte Folded Spill ; LE-P8-PRIV-NEXT: std r19, 296(r1) # 8-byte Folded Spill
; LE-P8-PRIV-NEXT: std r20, 304(r1) # 8-byte Folded Spill ; LE-P8-PRIV-NEXT: std r20, 304(r1) # 8-byte Folded Spill
; LE-P8-PRIV-NEXT: std r21, 312(r1) # 8-byte Folded Spill
; LE-P8-PRIV-NEXT: stxvd2x v21, r1, r4 # 16-byte Folded Spill ; LE-P8-PRIV-NEXT: stxvd2x v21, r1, r4 # 16-byte Folded Spill
; LE-P8-PRIV-NEXT: li r4, 96 ; LE-P8-PRIV-NEXT: li r4, 96
; LE-P8-PRIV-NEXT: std r21, 312(r1) # 8-byte Folded Spill
; LE-P8-PRIV-NEXT: std r22, 320(r1) # 8-byte Folded Spill ; LE-P8-PRIV-NEXT: std r22, 320(r1) # 8-byte Folded Spill
; LE-P8-PRIV-NEXT: std r23, 328(r1) # 8-byte Folded Spill ; LE-P8-PRIV-NEXT: std r23, 328(r1) # 8-byte Folded Spill
; LE-P8-PRIV-NEXT: std r24, 336(r1) # 8-byte Folded Spill ; LE-P8-PRIV-NEXT: std r24, 336(r1) # 8-byte Folded Spill
; LE-P8-PRIV-NEXT: std r25, 344(r1) # 8-byte Folded Spill ; LE-P8-PRIV-NEXT: std r25, 344(r1) # 8-byte Folded Spill
; LE-P8-PRIV-NEXT: std r26, 352(r1) # 8-byte Folded Spill ; LE-P8-PRIV-NEXT: std r26, 352(r1) # 8-byte Folded Spill
; LE-P8-PRIV-NEXT: std r27, 360(r1) # 8-byte Folded Spill ; LE-P8-PRIV-NEXT: std r27, 360(r1) # 8-byte Folded Spill
; LE-P8-PRIV-NEXT: std r28, 368(r1) # 8-byte Folded Spill ; LE-P8-PRIV-NEXT: std r28, 368(r1) # 8-byte Folded Spill
; LE-P8-PRIV-NEXT: std r29, 376(r1) # 8-byte Folded Spill ; LE-P8-PRIV-NEXT: std r29, 376(r1) # 8-byte Folded Spill
; LE-P8-PRIV-NEXT: std r30, 384(r1) # 8-byte Folded Spill ; LE-P8-PRIV-NEXT: std r30, 384(r1) # 8-byte Folded Spill
; LE-P8-PRIV-NEXT: std r31, 392(r1) # 8-byte Folded Spill ; LE-P8-PRIV-NEXT: std r31, 392(r1) # 8-byte Folded Spill
; LE-P8-PRIV-NEXT: std r3, 40(r1) # 8-byte Folded Spill ; LE-P8-PRIV-NEXT: std r3, 40(r1) # 8-byte Folded Spill
; LE-P8-PRIV-NEXT: stxvd2x v22, r1, r4 # 16-byte Folded Spill ; LE-P8-PRIV-NEXT: stxvd2x v22, r1, r4 # 16-byte Folded Spill
; LE-P8-PRIV-NEXT: li r4, 112 ; LE-P8-PRIV-NEXT: li r4, 112
; LE-P8-PRIV-NEXT: stfd f14, 400(r1) # 8-byte Folded Spill
; LE-P8-PRIV-NEXT: stxvd2x v23, r1, r4 # 16-byte Folded Spill ; LE-P8-PRIV-NEXT: stxvd2x v23, r1, r4 # 16-byte Folded Spill
; LE-P8-PRIV-NEXT: li r4, 128 ; LE-P8-PRIV-NEXT: li r4, 128
; LE-P8-PRIV-NEXT: stfd f14, 400(r1) # 8-byte Folded Spill ; LE-P8-PRIV-NEXT: stfd f15, 408(r1) # 8-byte Folded Spill
; LE-P8-PRIV-NEXT: stxvd2x v24, r1, r4 # 16-byte Folded Spill ; LE-P8-PRIV-NEXT: stxvd2x v24, r1, r4 # 16-byte Folded Spill
; LE-P8-PRIV-NEXT: li r4, 144 ; LE-P8-PRIV-NEXT: li r4, 144
; LE-P8-PRIV-NEXT: stfd f15, 408(r1) # 8-byte Folded Spill ; LE-P8-PRIV-NEXT: stfd f16, 416(r1) # 8-byte Folded Spill
; LE-P8-PRIV-NEXT: stxvd2x v25, r1, r4 # 16-byte Folded Spill ; LE-P8-PRIV-NEXT: stxvd2x v25, r1, r4 # 16-byte Folded Spill
; LE-P8-PRIV-NEXT: li r4, 160 ; LE-P8-PRIV-NEXT: li r4, 160
; LE-P8-PRIV-NEXT: stfd f16, 416(r1) # 8-byte Folded Spill ; LE-P8-PRIV-NEXT: stfd f17, 424(r1) # 8-byte Folded Spill
; LE-P8-PRIV-NEXT: stxvd2x v26, r1, r4 # 16-byte Folded Spill ; LE-P8-PRIV-NEXT: stxvd2x v26, r1, r4 # 16-byte Folded Spill
; LE-P8-PRIV-NEXT: li r4, 176 ; LE-P8-PRIV-NEXT: li r4, 176
; LE-P8-PRIV-NEXT: stfd f17, 424(r1) # 8-byte Folded Spill ; LE-P8-PRIV-NEXT: stfd f18, 432(r1) # 8-byte Folded Spill
; LE-P8-PRIV-NEXT: stxvd2x v27, r1, r4 # 16-byte Folded Spill ; LE-P8-PRIV-NEXT: stxvd2x v27, r1, r4 # 16-byte Folded Spill
; LE-P8-PRIV-NEXT: li r4, 192 ; LE-P8-PRIV-NEXT: li r4, 192
; LE-P8-PRIV-NEXT: stfd f18, 432(r1) # 8-byte Folded Spill ; LE-P8-PRIV-NEXT: stfd f19, 440(r1) # 8-byte Folded Spill
; LE-P8-PRIV-NEXT: stxvd2x v28, r1, r4 # 16-byte Folded Spill ; LE-P8-PRIV-NEXT: stxvd2x v28, r1, r4 # 16-byte Folded Spill
; LE-P8-PRIV-NEXT: li r4, 208 ; LE-P8-PRIV-NEXT: li r4, 208
; LE-P8-PRIV-NEXT: stfd f19, 440(r1) # 8-byte Folded Spill ; LE-P8-PRIV-NEXT: stfd f20, 448(r1) # 8-byte Folded Spill
; LE-P8-PRIV-NEXT: stxvd2x v29, r1, r4 # 16-byte Folded Spill ; LE-P8-PRIV-NEXT: stxvd2x v29, r1, r4 # 16-byte Folded Spill
; LE-P8-PRIV-NEXT: li r4, 224 ; LE-P8-PRIV-NEXT: li r4, 224
; LE-P8-PRIV-NEXT: stfd f20, 448(r1) # 8-byte Folded Spill ; LE-P8-PRIV-NEXT: stfd f21, 456(r1) # 8-byte Folded Spill
; LE-P8-PRIV-NEXT: stxvd2x v30, r1, r4 # 16-byte Folded Spill ; LE-P8-PRIV-NEXT: stxvd2x v30, r1, r4 # 16-byte Folded Spill
; LE-P8-PRIV-NEXT: li r4, 240 ; LE-P8-PRIV-NEXT: li r4, 240
; LE-P8-PRIV-NEXT: stfd f21, 456(r1) # 8-byte Folded Spill ; LE-P8-PRIV-NEXT: stfd f22, 464(r1) # 8-byte Folded Spill
; LE-P8-PRIV-NEXT: stxvd2x v31, r1, r4 # 16-byte Folded Spill ; LE-P8-PRIV-NEXT: stxvd2x v31, r1, r4 # 16-byte Folded Spill
; LE-P8-PRIV-NEXT: lwz r4, 12(r3) ; LE-P8-PRIV-NEXT: lwz r4, 12(r3)
; LE-P8-PRIV-NEXT: stfd f22, 464(r1) # 8-byte Folded Spill
; LE-P8-PRIV-NEXT: stfd f23, 472(r1) # 8-byte Folded Spill ; LE-P8-PRIV-NEXT: stfd f23, 472(r1) # 8-byte Folded Spill
; LE-P8-PRIV-NEXT: stfd f24, 480(r1) # 8-byte Folded Spill ; LE-P8-PRIV-NEXT: stfd f24, 480(r1) # 8-byte Folded Spill
; LE-P8-PRIV-NEXT: stfd f25, 488(r1) # 8-byte Folded Spill ; LE-P8-PRIV-NEXT: stfd f25, 488(r1) # 8-byte Folded Spill
; LE-P8-PRIV-NEXT: stfd f26, 496(r1) # 8-byte Folded Spill ; LE-P8-PRIV-NEXT: stfd f26, 496(r1) # 8-byte Folded Spill
; LE-P8-PRIV-NEXT: stfd f27, 504(r1) # 8-byte Folded Spill ; LE-P8-PRIV-NEXT: stfd f27, 504(r1) # 8-byte Folded Spill
; LE-P8-PRIV-NEXT: stfd f28, 512(r1) # 8-byte Folded Spill ; LE-P8-PRIV-NEXT: stfd f28, 512(r1) # 8-byte Folded Spill
; LE-P8-PRIV-NEXT: stfd f29, 520(r1) # 8-byte Folded Spill ; LE-P8-PRIV-NEXT: stfd f29, 520(r1) # 8-byte Folded Spill
; LE-P8-PRIV-NEXT: stfd f30, 528(r1) # 8-byte Folded Spill ; LE-P8-PRIV-NEXT: stfd f30, 528(r1) # 8-byte Folded Spill
▲ Show 20 Lines • Show All 203 Lines • ▼ Show 20 Lines
; BE-P10-PRIV-NEXT: hashchkp r0, -488(r1) ; BE-P10-PRIV-NEXT: hashchkp r0, -488(r1)
; BE-P10-PRIV-NEXT: mtocrf 32, r12 ; BE-P10-PRIV-NEXT: mtocrf 32, r12
; BE-P10-PRIV-NEXT: mtocrf 16, r12 ; BE-P10-PRIV-NEXT: mtocrf 16, r12
; BE-P10-PRIV-NEXT: mtocrf 8, r12 ; BE-P10-PRIV-NEXT: mtocrf 8, r12
; BE-P10-PRIV-NEXT: blr ; BE-P10-PRIV-NEXT: blr
; ;
; BE-P9-PRIV-LABEL: spill: ; BE-P9-PRIV-LABEL: spill:
; BE-P9-PRIV: # %bb.0: # %entry ; BE-P9-PRIV: # %bb.0: # %entry
; BE-P9-PRIV-NEXT: mflr r0
; BE-P9-PRIV-NEXT: mfcr r12 ; BE-P9-PRIV-NEXT: mfcr r12
; BE-P9-PRIV-NEXT: std r0, 16(r1) ; BE-P9-PRIV-NEXT: mflr r0
; BE-P9-PRIV-NEXT: hashstp r0, -488(r1)
; BE-P9-PRIV-NEXT: stw r12, 8(r1) ; BE-P9-PRIV-NEXT: stw r12, 8(r1)
; BE-P9-PRIV-NEXT: stdu r1, -624(r1) ; BE-P9-PRIV-NEXT: stdu r1, -624(r1)
; BE-P9-PRIV-NEXT: lwz r4, 12(r3) ; BE-P9-PRIV-NEXT: std r0, 640(r1)
; BE-P9-PRIV-NEXT: hashstp r0, -488(r1)
; BE-P9-PRIV-NEXT: std r14, 336(r1) # 8-byte Folded Spill ; BE-P9-PRIV-NEXT: std r14, 336(r1) # 8-byte Folded Spill
; BE-P9-PRIV-NEXT: std r15, 344(r1) # 8-byte Folded Spill
; BE-P9-PRIV-NEXT: stxv v20, 144(r1) # 16-byte Folded Spill ; BE-P9-PRIV-NEXT: stxv v20, 144(r1) # 16-byte Folded Spill
; BE-P9-PRIV-NEXT: stxv v21, 160(r1) # 16-byte Folded Spill ; BE-P9-PRIV-NEXT: stxv v21, 160(r1) # 16-byte Folded Spill
; BE-P9-PRIV-NEXT: lwz r4, 12(r3)
; BE-P9-PRIV-NEXT: std r15, 344(r1) # 8-byte Folded Spill
; BE-P9-PRIV-NEXT: stxv v22, 176(r1) # 16-byte Folded Spill ; BE-P9-PRIV-NEXT: stxv v22, 176(r1) # 16-byte Folded Spill
; BE-P9-PRIV-NEXT: std r16, 352(r1) # 8-byte Folded Spill ; BE-P9-PRIV-NEXT: std r16, 352(r1) # 8-byte Folded Spill
; BE-P9-PRIV-NEXT: std r17, 360(r1) # 8-byte Folded Spill
; BE-P9-PRIV-NEXT: stxv v23, 192(r1) # 16-byte Folded Spill ; BE-P9-PRIV-NEXT: stxv v23, 192(r1) # 16-byte Folded Spill
; BE-P9-PRIV-NEXT: std r18, 368(r1) # 8-byte Folded Spill ; BE-P9-PRIV-NEXT: std r17, 360(r1) # 8-byte Folded Spill
; BE-P9-PRIV-NEXT: stxv v24, 208(r1) # 16-byte Folded Spill ; BE-P9-PRIV-NEXT: stxv v24, 208(r1) # 16-byte Folded Spill
; BE-P9-PRIV-NEXT: std r19, 376(r1) # 8-byte Folded Spill ; BE-P9-PRIV-NEXT: std r18, 368(r1) # 8-byte Folded Spill
; BE-P9-PRIV-NEXT: stxv v25, 224(r1) # 16-byte Folded Spill ; BE-P9-PRIV-NEXT: stxv v25, 224(r1) # 16-byte Folded Spill
; BE-P9-PRIV-NEXT: std r19, 376(r1) # 8-byte Folded Spill
; BE-P9-PRIV-NEXT: std r20, 384(r1) # 8-byte Folded Spill ; BE-P9-PRIV-NEXT: std r20, 384(r1) # 8-byte Folded Spill
; BE-P9-PRIV-NEXT: std r21, 392(r1) # 8-byte Folded Spill
; BE-P9-PRIV-NEXT: stxv v26, 240(r1) # 16-byte Folded Spill ; BE-P9-PRIV-NEXT: stxv v26, 240(r1) # 16-byte Folded Spill
; BE-P9-PRIV-NEXT: std r22, 400(r1) # 8-byte Folded Spill ; BE-P9-PRIV-NEXT: std r21, 392(r1) # 8-byte Folded Spill
; BE-P9-PRIV-NEXT: stxv v27, 256(r1) # 16-byte Folded Spill ; BE-P9-PRIV-NEXT: stxv v27, 256(r1) # 16-byte Folded Spill
; BE-P9-PRIV-NEXT: std r23, 408(r1) # 8-byte Folded Spill ; BE-P9-PRIV-NEXT: std r22, 400(r1) # 8-byte Folded Spill
; BE-P9-PRIV-NEXT: stxv v28, 272(r1) # 16-byte Folded Spill ; BE-P9-PRIV-NEXT: stxv v28, 272(r1) # 16-byte Folded Spill
; BE-P9-PRIV-NEXT: std r23, 408(r1) # 8-byte Folded Spill
; BE-P9-PRIV-NEXT: std r24, 416(r1) # 8-byte Folded Spill ; BE-P9-PRIV-NEXT: std r24, 416(r1) # 8-byte Folded Spill
; BE-P9-PRIV-NEXT: std r25, 424(r1) # 8-byte Folded Spill
; BE-P9-PRIV-NEXT: stxv v29, 288(r1) # 16-byte Folded Spill ; BE-P9-PRIV-NEXT: stxv v29, 288(r1) # 16-byte Folded Spill
; BE-P9-PRIV-NEXT: std r26, 432(r1) # 8-byte Folded Spill ; BE-P9-PRIV-NEXT: std r25, 424(r1) # 8-byte Folded Spill
; BE-P9-PRIV-NEXT: stxv v30, 304(r1) # 16-byte Folded Spill ; BE-P9-PRIV-NEXT: stxv v30, 304(r1) # 16-byte Folded Spill
; BE-P9-PRIV-NEXT: std r27, 440(r1) # 8-byte Folded Spill ; BE-P9-PRIV-NEXT: std r26, 432(r1) # 8-byte Folded Spill
; BE-P9-PRIV-NEXT: stxv v31, 320(r1) # 16-byte Folded Spill ; BE-P9-PRIV-NEXT: stxv v31, 320(r1) # 16-byte Folded Spill
; BE-P9-PRIV-NEXT: std r27, 440(r1) # 8-byte Folded Spill
; BE-P9-PRIV-NEXT: std r28, 448(r1) # 8-byte Folded Spill ; BE-P9-PRIV-NEXT: std r28, 448(r1) # 8-byte Folded Spill
; BE-P9-PRIV-NEXT: std r29, 456(r1) # 8-byte Folded Spill ; BE-P9-PRIV-NEXT: std r29, 456(r1) # 8-byte Folded Spill
; BE-P9-PRIV-NEXT: std r30, 464(r1) # 8-byte Folded Spill ; BE-P9-PRIV-NEXT: std r30, 464(r1) # 8-byte Folded Spill
; BE-P9-PRIV-NEXT: std r31, 472(r1) # 8-byte Folded Spill ; BE-P9-PRIV-NEXT: std r31, 472(r1) # 8-byte Folded Spill
; BE-P9-PRIV-NEXT: stfd f14, 480(r1) # 8-byte Folded Spill ; BE-P9-PRIV-NEXT: stfd f14, 480(r1) # 8-byte Folded Spill
; BE-P9-PRIV-NEXT: stfd f15, 488(r1) # 8-byte Folded Spill ; BE-P9-PRIV-NEXT: stfd f15, 488(r1) # 8-byte Folded Spill
; BE-P9-PRIV-NEXT: stfd f16, 496(r1) # 8-byte Folded Spill ; BE-P9-PRIV-NEXT: stfd f16, 496(r1) # 8-byte Folded Spill
; BE-P9-PRIV-NEXT: stfd f17, 504(r1) # 8-byte Folded Spill ; BE-P9-PRIV-NEXT: stfd f17, 504(r1) # 8-byte Folded Spill
▲ Show 20 Lines • Show All 80 Lines • ▼ Show 20 Lines
; BE-P9-PRIV-NEXT: mtocrf 16, r12 ; BE-P9-PRIV-NEXT: mtocrf 16, r12
; BE-P9-PRIV-NEXT: mtocrf 8, r12 ; BE-P9-PRIV-NEXT: mtocrf 8, r12
; BE-P9-PRIV-NEXT: blr ; BE-P9-PRIV-NEXT: blr
; ;
; BE-P8-PRIV-LABEL: spill: ; BE-P8-PRIV-LABEL: spill:
; BE-P8-PRIV: # %bb.0: # %entry ; BE-P8-PRIV: # %bb.0: # %entry
; BE-P8-PRIV-NEXT: mfcr r12 ; BE-P8-PRIV-NEXT: mfcr r12
; BE-P8-PRIV-NEXT: mflr r0 ; BE-P8-PRIV-NEXT: mflr r0
; BE-P8-PRIV-NEXT: std r0, 16(r1)
; BE-P8-PRIV-NEXT: hashstp r0, -488(r1)
; BE-P8-PRIV-NEXT: stw r12, 8(r1) ; BE-P8-PRIV-NEXT: stw r12, 8(r1)
; BE-P8-PRIV-NEXT: stdu r1, -624(r1) ; BE-P8-PRIV-NEXT: stdu r1, -624(r1)
; BE-P8-PRIV-NEXT: li r4, 144 ; BE-P8-PRIV-NEXT: li r4, 144
; BE-P8-PRIV-NEXT: std r0, 640(r1)
; BE-P8-PRIV-NEXT: hashstp r0, -488(r1)
; BE-P8-PRIV-NEXT: std r14, 336(r1) # 8-byte Folded Spill ; BE-P8-PRIV-NEXT: std r14, 336(r1) # 8-byte Folded Spill
; BE-P8-PRIV-NEXT: std r15, 344(r1) # 8-byte Folded Spill ; BE-P8-PRIV-NEXT: std r15, 344(r1) # 8-byte Folded Spill
; BE-P8-PRIV-NEXT: std r16, 352(r1) # 8-byte Folded Spill ; BE-P8-PRIV-NEXT: std r16, 352(r1) # 8-byte Folded Spill
; BE-P8-PRIV-NEXT: std r17, 360(r1) # 8-byte Folded Spill
; BE-P8-PRIV-NEXT: stxvd2x v20, r1, r4 # 16-byte Folded Spill ; BE-P8-PRIV-NEXT: stxvd2x v20, r1, r4 # 16-byte Folded Spill
; BE-P8-PRIV-NEXT: li r4, 160 ; BE-P8-PRIV-NEXT: li r4, 160
; BE-P8-PRIV-NEXT: std r17, 360(r1) # 8-byte Folded Spill
; BE-P8-PRIV-NEXT: std r18, 368(r1) # 8-byte Folded Spill ; BE-P8-PRIV-NEXT: std r18, 368(r1) # 8-byte Folded Spill
; BE-P8-PRIV-NEXT: std r19, 376(r1) # 8-byte Folded Spill ; BE-P8-PRIV-NEXT: std r19, 376(r1) # 8-byte Folded Spill
; BE-P8-PRIV-NEXT: std r20, 384(r1) # 8-byte Folded Spill ; BE-P8-PRIV-NEXT: std r20, 384(r1) # 8-byte Folded Spill
; BE-P8-PRIV-NEXT: std r21, 392(r1) # 8-byte Folded Spill
; BE-P8-PRIV-NEXT: stxvd2x v21, r1, r4 # 16-byte Folded Spill ; BE-P8-PRIV-NEXT: stxvd2x v21, r1, r4 # 16-byte Folded Spill
; BE-P8-PRIV-NEXT: li r4, 176 ; BE-P8-PRIV-NEXT: li r4, 176
; BE-P8-PRIV-NEXT: std r21, 392(r1) # 8-byte Folded Spill
; BE-P8-PRIV-NEXT: std r22, 400(r1) # 8-byte Folded Spill ; BE-P8-PRIV-NEXT: std r22, 400(r1) # 8-byte Folded Spill
; BE-P8-PRIV-NEXT: std r23, 408(r1) # 8-byte Folded Spill ; BE-P8-PRIV-NEXT: std r23, 408(r1) # 8-byte Folded Spill
; BE-P8-PRIV-NEXT: std r24, 416(r1) # 8-byte Folded Spill ; BE-P8-PRIV-NEXT: std r24, 416(r1) # 8-byte Folded Spill
; BE-P8-PRIV-NEXT: std r25, 424(r1) # 8-byte Folded Spill ; BE-P8-PRIV-NEXT: std r25, 424(r1) # 8-byte Folded Spill
; BE-P8-PRIV-NEXT: std r26, 432(r1) # 8-byte Folded Spill ; BE-P8-PRIV-NEXT: std r26, 432(r1) # 8-byte Folded Spill
; BE-P8-PRIV-NEXT: std r27, 440(r1) # 8-byte Folded Spill ; BE-P8-PRIV-NEXT: std r27, 440(r1) # 8-byte Folded Spill
; BE-P8-PRIV-NEXT: std r28, 448(r1) # 8-byte Folded Spill ; BE-P8-PRIV-NEXT: std r28, 448(r1) # 8-byte Folded Spill
; BE-P8-PRIV-NEXT: std r29, 456(r1) # 8-byte Folded Spill ; BE-P8-PRIV-NEXT: std r29, 456(r1) # 8-byte Folded Spill
; BE-P8-PRIV-NEXT: std r30, 464(r1) # 8-byte Folded Spill ; BE-P8-PRIV-NEXT: std r30, 464(r1) # 8-byte Folded Spill
; BE-P8-PRIV-NEXT: std r31, 472(r1) # 8-byte Folded Spill ; BE-P8-PRIV-NEXT: std r31, 472(r1) # 8-byte Folded Spill
; BE-P8-PRIV-NEXT: std r3, 120(r1) # 8-byte Folded Spill ; BE-P8-PRIV-NEXT: std r3, 120(r1) # 8-byte Folded Spill
; BE-P8-PRIV-NEXT: stxvd2x v22, r1, r4 # 16-byte Folded Spill ; BE-P8-PRIV-NEXT: stxvd2x v22, r1, r4 # 16-byte Folded Spill
; BE-P8-PRIV-NEXT: li r4, 192 ; BE-P8-PRIV-NEXT: li r4, 192
; BE-P8-PRIV-NEXT: stfd f14, 480(r1) # 8-byte Folded Spill
; BE-P8-PRIV-NEXT: stxvd2x v23, r1, r4 # 16-byte Folded Spill ; BE-P8-PRIV-NEXT: stxvd2x v23, r1, r4 # 16-byte Folded Spill
; BE-P8-PRIV-NEXT: li r4, 208 ; BE-P8-PRIV-NEXT: li r4, 208
; BE-P8-PRIV-NEXT: stfd f14, 480(r1) # 8-byte Folded Spill ; BE-P8-PRIV-NEXT: stfd f15, 488(r1) # 8-byte Folded Spill
; BE-P8-PRIV-NEXT: stxvd2x v24, r1, r4 # 16-byte Folded Spill ; BE-P8-PRIV-NEXT: stxvd2x v24, r1, r4 # 16-byte Folded Spill
; BE-P8-PRIV-NEXT: li r4, 224 ; BE-P8-PRIV-NEXT: li r4, 224
; BE-P8-PRIV-NEXT: stfd f15, 488(r1) # 8-byte Folded Spill ; BE-P8-PRIV-NEXT: stfd f16, 496(r1) # 8-byte Folded Spill
; BE-P8-PRIV-NEXT: stxvd2x v25, r1, r4 # 16-byte Folded Spill ; BE-P8-PRIV-NEXT: stxvd2x v25, r1, r4 # 16-byte Folded Spill
; BE-P8-PRIV-NEXT: li r4, 240 ; BE-P8-PRIV-NEXT: li r4, 240
; BE-P8-PRIV-NEXT: stfd f16, 496(r1) # 8-byte Folded Spill ; BE-P8-PRIV-NEXT: stfd f17, 504(r1) # 8-byte Folded Spill
; BE-P8-PRIV-NEXT: stxvd2x v26, r1, r4 # 16-byte Folded Spill ; BE-P8-PRIV-NEXT: stxvd2x v26, r1, r4 # 16-byte Folded Spill
; BE-P8-PRIV-NEXT: li r4, 256 ; BE-P8-PRIV-NEXT: li r4, 256
; BE-P8-PRIV-NEXT: stfd f17, 504(r1) # 8-byte Folded Spill ; BE-P8-PRIV-NEXT: stfd f18, 512(r1) # 8-byte Folded Spill
; BE-P8-PRIV-NEXT: stxvd2x v27, r1, r4 # 16-byte Folded Spill ; BE-P8-PRIV-NEXT: stxvd2x v27, r1, r4 # 16-byte Folded Spill
; BE-P8-PRIV-NEXT: li r4, 272 ; BE-P8-PRIV-NEXT: li r4, 272
; BE-P8-PRIV-NEXT: stfd f18, 512(r1) # 8-byte Folded Spill ; BE-P8-PRIV-NEXT: stfd f19, 520(r1) # 8-byte Folded Spill
; BE-P8-PRIV-NEXT: stxvd2x v28, r1, r4 # 16-byte Folded Spill ; BE-P8-PRIV-NEXT: stxvd2x v28, r1, r4 # 16-byte Folded Spill
; BE-P8-PRIV-NEXT: li r4, 288 ; BE-P8-PRIV-NEXT: li r4, 288
; BE-P8-PRIV-NEXT: stfd f19, 520(r1) # 8-byte Folded Spill ; BE-P8-PRIV-NEXT: stfd f20, 528(r1) # 8-byte Folded Spill
; BE-P8-PRIV-NEXT: stxvd2x v29, r1, r4 # 16-byte Folded Spill ; BE-P8-PRIV-NEXT: stxvd2x v29, r1, r4 # 16-byte Folded Spill
; BE-P8-PRIV-NEXT: li r4, 304 ; BE-P8-PRIV-NEXT: li r4, 304
; BE-P8-PRIV-NEXT: stfd f20, 528(r1) # 8-byte Folded Spill ; BE-P8-PRIV-NEXT: stfd f21, 536(r1) # 8-byte Folded Spill
; BE-P8-PRIV-NEXT: stxvd2x v30, r1, r4 # 16-byte Folded Spill ; BE-P8-PRIV-NEXT: stxvd2x v30, r1, r4 # 16-byte Folded Spill
; BE-P8-PRIV-NEXT: li r4, 320 ; BE-P8-PRIV-NEXT: li r4, 320
; BE-P8-PRIV-NEXT: stfd f21, 536(r1) # 8-byte Folded Spill ; BE-P8-PRIV-NEXT: stfd f22, 544(r1) # 8-byte Folded Spill
; BE-P8-PRIV-NEXT: stxvd2x v31, r1, r4 # 16-byte Folded Spill ; BE-P8-PRIV-NEXT: stxvd2x v31, r1, r4 # 16-byte Folded Spill
; BE-P8-PRIV-NEXT: lwz r4, 12(r3) ; BE-P8-PRIV-NEXT: lwz r4, 12(r3)
; BE-P8-PRIV-NEXT: stfd f22, 544(r1) # 8-byte Folded Spill
; BE-P8-PRIV-NEXT: stfd f23, 552(r1) # 8-byte Folded Spill ; BE-P8-PRIV-NEXT: stfd f23, 552(r1) # 8-byte Folded Spill
; BE-P8-PRIV-NEXT: stfd f24, 560(r1) # 8-byte Folded Spill ; BE-P8-PRIV-NEXT: stfd f24, 560(r1) # 8-byte Folded Spill
; BE-P8-PRIV-NEXT: stfd f25, 568(r1) # 8-byte Folded Spill ; BE-P8-PRIV-NEXT: stfd f25, 568(r1) # 8-byte Folded Spill
; BE-P8-PRIV-NEXT: stfd f26, 576(r1) # 8-byte Folded Spill ; BE-P8-PRIV-NEXT: stfd f26, 576(r1) # 8-byte Folded Spill
; BE-P8-PRIV-NEXT: stfd f27, 584(r1) # 8-byte Folded Spill ; BE-P8-PRIV-NEXT: stfd f27, 584(r1) # 8-byte Folded Spill
; BE-P8-PRIV-NEXT: stfd f28, 592(r1) # 8-byte Folded Spill ; BE-P8-PRIV-NEXT: stfd f28, 592(r1) # 8-byte Folded Spill
; BE-P8-PRIV-NEXT: stfd f29, 600(r1) # 8-byte Folded Spill ; BE-P8-PRIV-NEXT: stfd f29, 600(r1) # 8-byte Folded Spill
; BE-P8-PRIV-NEXT: stfd f30, 608(r1) # 8-byte Folded Spill ; BE-P8-PRIV-NEXT: stfd f30, 608(r1) # 8-byte Folded Spill
▲ Show 20 Lines • Show All 124 Lines • ▼ Show 20 Lines
; ;
; LE-P9-LABEL: shrinkwrap: ; LE-P9-LABEL: shrinkwrap:
; LE-P9: # %bb.0: # %entry ; LE-P9: # %bb.0: # %entry
; LE-P9-NEXT: cmpldi r3, 0 ; LE-P9-NEXT: cmpldi r3, 0
; LE-P9-NEXT: beq cr0, .LBB2_2 ; LE-P9-NEXT: beq cr0, .LBB2_2
; LE-P9-NEXT: # %bb.1: # %if.end ; LE-P9-NEXT: # %bb.1: # %if.end
; LE-P9-NEXT: mflr r0 ; LE-P9-NEXT: mflr r0
; LE-P9-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; LE-P9-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; LE-P9-NEXT: std r0, 16(r1)
; LE-P9-NEXT: hashst r0, -24(r1)
; LE-P9-NEXT: stdu r1, -64(r1) ; LE-P9-NEXT: stdu r1, -64(r1)
; LE-P9-NEXT: std r0, 80(r1)
; LE-P9-NEXT: hashst r0, -24(r1)
; LE-P9-NEXT: mr r30, r3 ; LE-P9-NEXT: mr r30, r3
; LE-P9-NEXT: lwz r3, 12(r3) ; LE-P9-NEXT: lwz r3, 12(r3)
; LE-P9-NEXT: stw r3, 36(r1) ; LE-P9-NEXT: stw r3, 36(r1)
; LE-P9-NEXT: addi r3, r1, 36 ; LE-P9-NEXT: addi r3, r1, 36
; LE-P9-NEXT: bl callee2 ; LE-P9-NEXT: bl callee2
; LE-P9-NEXT: nop ; LE-P9-NEXT: nop
; LE-P9-NEXT: lwz r4, 16(r30) ; LE-P9-NEXT: lwz r4, 16(r30)
; LE-P9-NEXT: add r3, r4, r3 ; LE-P9-NEXT: add r3, r4, r3
Show All 10 Lines
; ;
; LE-P8-LABEL: shrinkwrap: ; LE-P8-LABEL: shrinkwrap:
; LE-P8: # %bb.0: # %entry ; LE-P8: # %bb.0: # %entry
; LE-P8-NEXT: cmpldi r3, 0 ; LE-P8-NEXT: cmpldi r3, 0
; LE-P8-NEXT: beq cr0, .LBB2_2 ; LE-P8-NEXT: beq cr0, .LBB2_2
; LE-P8-NEXT: # %bb.1: # %if.end ; LE-P8-NEXT: # %bb.1: # %if.end
; LE-P8-NEXT: mflr r0 ; LE-P8-NEXT: mflr r0
; LE-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; LE-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; LE-P8-NEXT: std r0, 16(r1)
; LE-P8-NEXT: hashst r0, -24(r1)
; LE-P8-NEXT: stdu r1, -64(r1) ; LE-P8-NEXT: stdu r1, -64(r1)
; LE-P8-NEXT: std r0, 80(r1)
; LE-P8-NEXT: hashst r0, -24(r1)
; LE-P8-NEXT: mr r30, r3 ; LE-P8-NEXT: mr r30, r3
; LE-P8-NEXT: lwz r3, 12(r3) ; LE-P8-NEXT: lwz r3, 12(r3)
; LE-P8-NEXT: stw r3, 36(r1) ; LE-P8-NEXT: stw r3, 36(r1)
; LE-P8-NEXT: addi r3, r1, 36 ; LE-P8-NEXT: addi r3, r1, 36
; LE-P8-NEXT: bl callee2 ; LE-P8-NEXT: bl callee2
; LE-P8-NEXT: nop ; LE-P8-NEXT: nop
; LE-P8-NEXT: lwz r4, 16(r30) ; LE-P8-NEXT: lwz r4, 16(r30)
; LE-P8-NEXT: add r3, r4, r3 ; LE-P8-NEXT: add r3, r4, r3
Show All 38 Lines
; LE-P10-O0-NEXT: ld r0, 16(r1) ; LE-P10-O0-NEXT: ld r0, 16(r1)
; LE-P10-O0-NEXT: hashchk r0, -8(r1) ; LE-P10-O0-NEXT: hashchk r0, -8(r1)
; LE-P10-O0-NEXT: mtlr r0 ; LE-P10-O0-NEXT: mtlr r0
; LE-P10-O0-NEXT: blr ; LE-P10-O0-NEXT: blr
; ;
; LE-P9-O0-LABEL: shrinkwrap: ; LE-P9-O0-LABEL: shrinkwrap:
; LE-P9-O0: # %bb.0: # %entry ; LE-P9-O0: # %bb.0: # %entry
; LE-P9-O0-NEXT: mflr r0 ; LE-P9-O0-NEXT: mflr r0
; LE-P9-O0-NEXT: std r0, 16(r1)
; LE-P9-O0-NEXT: hashst r0, -8(r1)
; LE-P9-O0-NEXT: stdu r1, -128(r1) ; LE-P9-O0-NEXT: stdu r1, -128(r1)
; LE-P9-O0-NEXT: std r0, 144(r1)
; LE-P9-O0-NEXT: hashst r0, -8(r1)
; LE-P9-O0-NEXT: mr. r4, r3 ; LE-P9-O0-NEXT: mr. r4, r3
; LE-P9-O0-NEXT: std r4, 104(r1) # 8-byte Folded Spill ; LE-P9-O0-NEXT: std r4, 104(r1) # 8-byte Folded Spill
; LE-P9-O0-NEXT: li r3, 0 ; LE-P9-O0-NEXT: li r3, 0
; LE-P9-O0-NEXT: stw r3, 112(r1) # 4-byte Folded Spill ; LE-P9-O0-NEXT: stw r3, 112(r1) # 4-byte Folded Spill
; LE-P9-O0-NEXT: beq cr0, .LBB2_2 ; LE-P9-O0-NEXT: beq cr0, .LBB2_2
; LE-P9-O0-NEXT: # %bb.1: # %if.end ; LE-P9-O0-NEXT: # %bb.1: # %if.end
; LE-P9-O0-NEXT: ld r3, 104(r1) # 8-byte Folded Reload ; LE-P9-O0-NEXT: ld r3, 104(r1) # 8-byte Folded Reload
; LE-P9-O0-NEXT: lwz r3, 12(r3) ; LE-P9-O0-NEXT: lwz r3, 12(r3)
Show All 13 Lines
; LE-P9-O0-NEXT: ld r0, 16(r1) ; LE-P9-O0-NEXT: ld r0, 16(r1)
; LE-P9-O0-NEXT: hashchk r0, -8(r1) ; LE-P9-O0-NEXT: hashchk r0, -8(r1)
; LE-P9-O0-NEXT: mtlr r0 ; LE-P9-O0-NEXT: mtlr r0
; LE-P9-O0-NEXT: blr ; LE-P9-O0-NEXT: blr
; ;
; LE-P8-O0-LABEL: shrinkwrap: ; LE-P8-O0-LABEL: shrinkwrap:
; LE-P8-O0: # %bb.0: # %entry ; LE-P8-O0: # %bb.0: # %entry
; LE-P8-O0-NEXT: mflr r0 ; LE-P8-O0-NEXT: mflr r0
; LE-P8-O0-NEXT: std r0, 16(r1)
; LE-P8-O0-NEXT: hashst r0, -8(r1)
; LE-P8-O0-NEXT: stdu r1, -128(r1) ; LE-P8-O0-NEXT: stdu r1, -128(r1)
; LE-P8-O0-NEXT: std r0, 144(r1)
; LE-P8-O0-NEXT: hashst r0, -8(r1)
; LE-P8-O0-NEXT: mr. r4, r3 ; LE-P8-O0-NEXT: mr. r4, r3
; LE-P8-O0-NEXT: std r4, 104(r1) # 8-byte Folded Spill ; LE-P8-O0-NEXT: std r4, 104(r1) # 8-byte Folded Spill
; LE-P8-O0-NEXT: li r3, 0 ; LE-P8-O0-NEXT: li r3, 0
; LE-P8-O0-NEXT: stw r3, 112(r1) # 4-byte Folded Spill ; LE-P8-O0-NEXT: stw r3, 112(r1) # 4-byte Folded Spill
; LE-P8-O0-NEXT: beq cr0, .LBB2_2 ; LE-P8-O0-NEXT: beq cr0, .LBB2_2
; LE-P8-O0-NEXT: # %bb.1: # %if.end ; LE-P8-O0-NEXT: # %bb.1: # %if.end
; LE-P8-O0-NEXT: ld r3, 104(r1) # 8-byte Folded Reload ; LE-P8-O0-NEXT: ld r3, 104(r1) # 8-byte Folded Reload
; LE-P8-O0-NEXT: lwz r3, 12(r3) ; LE-P8-O0-NEXT: lwz r3, 12(r3)
▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Lines
; BE-P10-NEXT: blr ; BE-P10-NEXT: blr
; ;
; BE-P9-LABEL: shrinkwrap: ; BE-P9-LABEL: shrinkwrap:
; BE-P9: # %bb.0: # %entry ; BE-P9: # %bb.0: # %entry
; BE-P9-NEXT: cmpldi r3, 0 ; BE-P9-NEXT: cmpldi r3, 0
; BE-P9-NEXT: beq cr0, .LBB2_2 ; BE-P9-NEXT: beq cr0, .LBB2_2
; BE-P9-NEXT: # %bb.1: # %if.end ; BE-P9-NEXT: # %bb.1: # %if.end
; BE-P9-NEXT: mflr r0 ; BE-P9-NEXT: mflr r0
; BE-P9-NEXT: std r0, 16(r1)
; BE-P9-NEXT: hashst r0, -24(r1)
; BE-P9-NEXT: stdu r1, -144(r1) ; BE-P9-NEXT: stdu r1, -144(r1)
; BE-P9-NEXT: std r0, 160(r1)
; BE-P9-NEXT: hashst r0, -24(r1)
; BE-P9-NEXT: std r30, 128(r1) # 8-byte Folded Spill ; BE-P9-NEXT: std r30, 128(r1) # 8-byte Folded Spill
; BE-P9-NEXT: mr r30, r3 ; BE-P9-NEXT: mr r30, r3
; BE-P9-NEXT: lwz r3, 12(r3) ; BE-P9-NEXT: lwz r3, 12(r3)
; BE-P9-NEXT: stw r3, 116(r1) ; BE-P9-NEXT: stw r3, 116(r1)
; BE-P9-NEXT: addi r3, r1, 116 ; BE-P9-NEXT: addi r3, r1, 116
; BE-P9-NEXT: bl callee2 ; BE-P9-NEXT: bl callee2
; BE-P9-NEXT: nop ; BE-P9-NEXT: nop
; BE-P9-NEXT: lwz r4, 16(r30) ; BE-P9-NEXT: lwz r4, 16(r30)
Show All 10 Lines
; BE-P9-NEXT: blr ; BE-P9-NEXT: blr
; ;
; BE-P8-LABEL: shrinkwrap: ; BE-P8-LABEL: shrinkwrap:
; BE-P8: # %bb.0: # %entry ; BE-P8: # %bb.0: # %entry
; BE-P8-NEXT: cmpldi r3, 0 ; BE-P8-NEXT: cmpldi r3, 0
; BE-P8-NEXT: beq cr0, .LBB2_2 ; BE-P8-NEXT: beq cr0, .LBB2_2
; BE-P8-NEXT: # %bb.1: # %if.end ; BE-P8-NEXT: # %bb.1: # %if.end
; BE-P8-NEXT: mflr r0 ; BE-P8-NEXT: mflr r0
; BE-P8-NEXT: std r0, 16(r1)
; BE-P8-NEXT: hashst r0, -24(r1)
; BE-P8-NEXT: stdu r1, -144(r1) ; BE-P8-NEXT: stdu r1, -144(r1)
; BE-P8-NEXT: std r0, 160(r1)
; BE-P8-NEXT: hashst r0, -24(r1)
; BE-P8-NEXT: std r30, 128(r1) # 8-byte Folded Spill ; BE-P8-NEXT: std r30, 128(r1) # 8-byte Folded Spill
; BE-P8-NEXT: mr r30, r3 ; BE-P8-NEXT: mr r30, r3
; BE-P8-NEXT: lwz r3, 12(r3) ; BE-P8-NEXT: lwz r3, 12(r3)
; BE-P8-NEXT: stw r3, 116(r1) ; BE-P8-NEXT: stw r3, 116(r1)
; BE-P8-NEXT: addi r3, r1, 116 ; BE-P8-NEXT: addi r3, r1, 116
; BE-P8-NEXT: bl callee2 ; BE-P8-NEXT: bl callee2
; BE-P8-NEXT: nop ; BE-P8-NEXT: nop
; BE-P8-NEXT: lwz r4, 16(r30) ; BE-P8-NEXT: lwz r4, 16(r30)
Show All 35 Lines
; BE-32BIT-P10-NEXT: addi r1, r1, 32 ; BE-32BIT-P10-NEXT: addi r1, r1, 32
; BE-32BIT-P10-NEXT: hashchk r0, -16(r1) ; BE-32BIT-P10-NEXT: hashchk r0, -16(r1)
; BE-32BIT-P10-NEXT: mtlr r0 ; BE-32BIT-P10-NEXT: mtlr r0
; BE-32BIT-P10-NEXT: blr ; BE-32BIT-P10-NEXT: blr
; ;
; BE-32BIT-P9-LABEL: shrinkwrap: ; BE-32BIT-P9-LABEL: shrinkwrap:
; BE-32BIT-P9: # %bb.0: # %entry ; BE-32BIT-P9: # %bb.0: # %entry
; BE-32BIT-P9-NEXT: mflr r0 ; BE-32BIT-P9-NEXT: mflr r0
; BE-32BIT-P9-NEXT: stw r0, 4(r1)
; BE-32BIT-P9-NEXT: hashst r0, -16(r1)
; BE-32BIT-P9-NEXT: stwu r1, -32(r1) ; BE-32BIT-P9-NEXT: stwu r1, -32(r1)
; BE-32BIT-P9-NEXT: cmplwi r3, 0 ; BE-32BIT-P9-NEXT: cmplwi r3, 0
; BE-32BIT-P9-NEXT: stw r0, 36(r1)
; BE-32BIT-P9-NEXT: hashst r0, -16(r1)
; BE-32BIT-P9-NEXT: stw r30, 24(r1) # 4-byte Folded Spill ; BE-32BIT-P9-NEXT: stw r30, 24(r1) # 4-byte Folded Spill
; BE-32BIT-P9-NEXT: beq cr0, .LBB2_2 ; BE-32BIT-P9-NEXT: beq cr0, .LBB2_2
; BE-32BIT-P9-NEXT: # %bb.1: # %if.end ; BE-32BIT-P9-NEXT: # %bb.1: # %if.end
; BE-32BIT-P9-NEXT: mr r30, r3 ; BE-32BIT-P9-NEXT: mr r30, r3
; BE-32BIT-P9-NEXT: lwz r3, 12(r3) ; BE-32BIT-P9-NEXT: lwz r3, 12(r3)
; BE-32BIT-P9-NEXT: stw r3, 12(r1) ; BE-32BIT-P9-NEXT: stw r3, 12(r1)
; BE-32BIT-P9-NEXT: addi r3, r1, 12 ; BE-32BIT-P9-NEXT: addi r3, r1, 12
; BE-32BIT-P9-NEXT: bl callee2 ; BE-32BIT-P9-NEXT: bl callee2
; BE-32BIT-P9-NEXT: lwz r4, 16(r30) ; BE-32BIT-P9-NEXT: lwz r4, 16(r30)
; BE-32BIT-P9-NEXT: add r3, r4, r3 ; BE-32BIT-P9-NEXT: add r3, r4, r3
; BE-32BIT-P9-NEXT: b .LBB2_3 ; BE-32BIT-P9-NEXT: b .LBB2_3
; BE-32BIT-P9-NEXT: .LBB2_2: ; BE-32BIT-P9-NEXT: .LBB2_2:
; BE-32BIT-P9-NEXT: li r3, 0 ; BE-32BIT-P9-NEXT: li r3, 0
; BE-32BIT-P9-NEXT: .LBB2_3: # %return ; BE-32BIT-P9-NEXT: .LBB2_3: # %return
; BE-32BIT-P9-NEXT: lwz r30, 24(r1) # 4-byte Folded Reload ; BE-32BIT-P9-NEXT: lwz r30, 24(r1) # 4-byte Folded Reload
; BE-32BIT-P9-NEXT: lwz r0, 36(r1) ; BE-32BIT-P9-NEXT: lwz r0, 36(r1)
; BE-32BIT-P9-NEXT: addi r1, r1, 32 ; BE-32BIT-P9-NEXT: addi r1, r1, 32
; BE-32BIT-P9-NEXT: mtlr r0 ; BE-32BIT-P9-NEXT: mtlr r0
; BE-32BIT-P9-NEXT: hashchk r0, -16(r1) ; BE-32BIT-P9-NEXT: hashchk r0, -16(r1)
; BE-32BIT-P9-NEXT: blr ; BE-32BIT-P9-NEXT: blr
; ;
; BE-32BIT-P8-LABEL: shrinkwrap: ; BE-32BIT-P8-LABEL: shrinkwrap:
; BE-32BIT-P8: # %bb.0: # %entry ; BE-32BIT-P8: # %bb.0: # %entry
; BE-32BIT-P8-NEXT: mflr r0 ; BE-32BIT-P8-NEXT: mflr r0
; BE-32BIT-P8-NEXT: stw r0, 4(r1)
; BE-32BIT-P8-NEXT: hashst r0, -16(r1)
; BE-32BIT-P8-NEXT: stwu r1, -32(r1) ; BE-32BIT-P8-NEXT: stwu r1, -32(r1)
; BE-32BIT-P8-NEXT: cmplwi r3, 0 ; BE-32BIT-P8-NEXT: cmplwi r3, 0
; BE-32BIT-P8-NEXT: stw r0, 36(r1)
; BE-32BIT-P8-NEXT: hashst r0, -16(r1)
; BE-32BIT-P8-NEXT: stw r30, 24(r1) # 4-byte Folded Spill ; BE-32BIT-P8-NEXT: stw r30, 24(r1) # 4-byte Folded Spill
; BE-32BIT-P8-NEXT: beq cr0, .LBB2_2 ; BE-32BIT-P8-NEXT: beq cr0, .LBB2_2
; BE-32BIT-P8-NEXT: # %bb.1: # %if.end ; BE-32BIT-P8-NEXT: # %bb.1: # %if.end
; BE-32BIT-P8-NEXT: mr r30, r3 ; BE-32BIT-P8-NEXT: mr r30, r3
; BE-32BIT-P8-NEXT: lwz r3, 12(r3) ; BE-32BIT-P8-NEXT: lwz r3, 12(r3)
; BE-32BIT-P8-NEXT: stw r3, 12(r1) ; BE-32BIT-P8-NEXT: stw r3, 12(r1)
; BE-32BIT-P8-NEXT: addi r3, r1, 12 ; BE-32BIT-P8-NEXT: addi r3, r1, 12
; BE-32BIT-P8-NEXT: bl callee2 ; BE-32BIT-P8-NEXT: bl callee2
Show All 40 Lines
; ;
; LE-P9-PRIV-LABEL: shrinkwrap: ; LE-P9-PRIV-LABEL: shrinkwrap:
; LE-P9-PRIV: # %bb.0: # %entry ; LE-P9-PRIV: # %bb.0: # %entry
; LE-P9-PRIV-NEXT: cmpldi r3, 0 ; LE-P9-PRIV-NEXT: cmpldi r3, 0
; LE-P9-PRIV-NEXT: beq cr0, .LBB2_2 ; LE-P9-PRIV-NEXT: beq cr0, .LBB2_2
; LE-P9-PRIV-NEXT: # %bb.1: # %if.end ; LE-P9-PRIV-NEXT: # %bb.1: # %if.end
; LE-P9-PRIV-NEXT: mflr r0 ; LE-P9-PRIV-NEXT: mflr r0
; LE-P9-PRIV-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; LE-P9-PRIV-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; LE-P9-PRIV-NEXT: std r0, 16(r1)
; LE-P9-PRIV-NEXT: hashstp r0, -24(r1)
; LE-P9-PRIV-NEXT: stdu r1, -64(r1) ; LE-P9-PRIV-NEXT: stdu r1, -64(r1)
; LE-P9-PRIV-NEXT: std r0, 80(r1)
; LE-P9-PRIV-NEXT: hashstp r0, -24(r1)
; LE-P9-PRIV-NEXT: mr r30, r3 ; LE-P9-PRIV-NEXT: mr r30, r3
; LE-P9-PRIV-NEXT: lwz r3, 12(r3) ; LE-P9-PRIV-NEXT: lwz r3, 12(r3)
; LE-P9-PRIV-NEXT: stw r3, 36(r1) ; LE-P9-PRIV-NEXT: stw r3, 36(r1)
; LE-P9-PRIV-NEXT: addi r3, r1, 36 ; LE-P9-PRIV-NEXT: addi r3, r1, 36
; LE-P9-PRIV-NEXT: bl callee2 ; LE-P9-PRIV-NEXT: bl callee2
; LE-P9-PRIV-NEXT: nop ; LE-P9-PRIV-NEXT: nop
; LE-P9-PRIV-NEXT: lwz r4, 16(r30) ; LE-P9-PRIV-NEXT: lwz r4, 16(r30)
; LE-P9-PRIV-NEXT: add r3, r4, r3 ; LE-P9-PRIV-NEXT: add r3, r4, r3
Show All 10 Lines
; ;
; LE-P8-PRIV-LABEL: shrinkwrap: ; LE-P8-PRIV-LABEL: shrinkwrap:
; LE-P8-PRIV: # %bb.0: # %entry ; LE-P8-PRIV: # %bb.0: # %entry
; LE-P8-PRIV-NEXT: cmpldi r3, 0 ; LE-P8-PRIV-NEXT: cmpldi r3, 0
; LE-P8-PRIV-NEXT: beq cr0, .LBB2_2 ; LE-P8-PRIV-NEXT: beq cr0, .LBB2_2
; LE-P8-PRIV-NEXT: # %bb.1: # %if.end ; LE-P8-PRIV-NEXT: # %bb.1: # %if.end
; LE-P8-PRIV-NEXT: mflr r0 ; LE-P8-PRIV-NEXT: mflr r0
; LE-P8-PRIV-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; LE-P8-PRIV-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; LE-P8-PRIV-NEXT: std r0, 16(r1)
; LE-P8-PRIV-NEXT: hashstp r0, -24(r1)
; LE-P8-PRIV-NEXT: stdu r1, -64(r1) ; LE-P8-PRIV-NEXT: stdu r1, -64(r1)
; LE-P8-PRIV-NEXT: std r0, 80(r1)
; LE-P8-PRIV-NEXT: hashstp r0, -24(r1)
; LE-P8-PRIV-NEXT: mr r30, r3 ; LE-P8-PRIV-NEXT: mr r30, r3
; LE-P8-PRIV-NEXT: lwz r3, 12(r3) ; LE-P8-PRIV-NEXT: lwz r3, 12(r3)
; LE-P8-PRIV-NEXT: stw r3, 36(r1) ; LE-P8-PRIV-NEXT: stw r3, 36(r1)
; LE-P8-PRIV-NEXT: addi r3, r1, 36 ; LE-P8-PRIV-NEXT: addi r3, r1, 36
; LE-P8-PRIV-NEXT: bl callee2 ; LE-P8-PRIV-NEXT: bl callee2
; LE-P8-PRIV-NEXT: nop ; LE-P8-PRIV-NEXT: nop
; LE-P8-PRIV-NEXT: lwz r4, 16(r30) ; LE-P8-PRIV-NEXT: lwz r4, 16(r30)
; LE-P8-PRIV-NEXT: add r3, r4, r3 ; LE-P8-PRIV-NEXT: add r3, r4, r3
Show All 38 Lines
; BE-P10-PRIV-NEXT: blr ; BE-P10-PRIV-NEXT: blr
; ;
; BE-P9-PRIV-LABEL: shrinkwrap: ; BE-P9-PRIV-LABEL: shrinkwrap:
; BE-P9-PRIV: # %bb.0: # %entry ; BE-P9-PRIV: # %bb.0: # %entry
; BE-P9-PRIV-NEXT: cmpldi r3, 0 ; BE-P9-PRIV-NEXT: cmpldi r3, 0
; BE-P9-PRIV-NEXT: beq cr0, .LBB2_2 ; BE-P9-PRIV-NEXT: beq cr0, .LBB2_2
; BE-P9-PRIV-NEXT: # %bb.1: # %if.end ; BE-P9-PRIV-NEXT: # %bb.1: # %if.end
; BE-P9-PRIV-NEXT: mflr r0 ; BE-P9-PRIV-NEXT: mflr r0
; BE-P9-PRIV-NEXT: std r0, 16(r1)
; BE-P9-PRIV-NEXT: hashstp r0, -24(r1)
; BE-P9-PRIV-NEXT: stdu r1, -144(r1) ; BE-P9-PRIV-NEXT: stdu r1, -144(r1)
; BE-P9-PRIV-NEXT: std r0, 160(r1)
; BE-P9-PRIV-NEXT: hashstp r0, -24(r1)
; BE-P9-PRIV-NEXT: std r30, 128(r1) # 8-byte Folded Spill ; BE-P9-PRIV-NEXT: std r30, 128(r1) # 8-byte Folded Spill
; BE-P9-PRIV-NEXT: mr r30, r3 ; BE-P9-PRIV-NEXT: mr r30, r3
; BE-P9-PRIV-NEXT: lwz r3, 12(r3) ; BE-P9-PRIV-NEXT: lwz r3, 12(r3)
; BE-P9-PRIV-NEXT: stw r3, 116(r1) ; BE-P9-PRIV-NEXT: stw r3, 116(r1)
; BE-P9-PRIV-NEXT: addi r3, r1, 116 ; BE-P9-PRIV-NEXT: addi r3, r1, 116
; BE-P9-PRIV-NEXT: bl callee2 ; BE-P9-PRIV-NEXT: bl callee2
; BE-P9-PRIV-NEXT: nop ; BE-P9-PRIV-NEXT: nop
; BE-P9-PRIV-NEXT: lwz r4, 16(r30) ; BE-P9-PRIV-NEXT: lwz r4, 16(r30)
Show All 10 Lines
; BE-P9-PRIV-NEXT: blr ; BE-P9-PRIV-NEXT: blr
; ;
; BE-P8-PRIV-LABEL: shrinkwrap: ; BE-P8-PRIV-LABEL: shrinkwrap:
; BE-P8-PRIV: # %bb.0: # %entry ; BE-P8-PRIV: # %bb.0: # %entry
; BE-P8-PRIV-NEXT: cmpldi r3, 0 ; BE-P8-PRIV-NEXT: cmpldi r3, 0
; BE-P8-PRIV-NEXT: beq cr0, .LBB2_2 ; BE-P8-PRIV-NEXT: beq cr0, .LBB2_2
; BE-P8-PRIV-NEXT: # %bb.1: # %if.end ; BE-P8-PRIV-NEXT: # %bb.1: # %if.end
; BE-P8-PRIV-NEXT: mflr r0 ; BE-P8-PRIV-NEXT: mflr r0
; BE-P8-PRIV-NEXT: std r0, 16(r1)
; BE-P8-PRIV-NEXT: hashstp r0, -24(r1)
; BE-P8-PRIV-NEXT: stdu r1, -144(r1) ; BE-P8-PRIV-NEXT: stdu r1, -144(r1)
; BE-P8-PRIV-NEXT: std r0, 160(r1)
; BE-P8-PRIV-NEXT: hashstp r0, -24(r1)
; BE-P8-PRIV-NEXT: std r30, 128(r1) # 8-byte Folded Spill ; BE-P8-PRIV-NEXT: std r30, 128(r1) # 8-byte Folded Spill
; BE-P8-PRIV-NEXT: mr r30, r3 ; BE-P8-PRIV-NEXT: mr r30, r3
; BE-P8-PRIV-NEXT: lwz r3, 12(r3) ; BE-P8-PRIV-NEXT: lwz r3, 12(r3)
; BE-P8-PRIV-NEXT: stw r3, 116(r1) ; BE-P8-PRIV-NEXT: stw r3, 116(r1)
; BE-P8-PRIV-NEXT: addi r3, r1, 116 ; BE-P8-PRIV-NEXT: addi r3, r1, 116
; BE-P8-PRIV-NEXT: bl callee2 ; BE-P8-PRIV-NEXT: bl callee2
; BE-P8-PRIV-NEXT: nop ; BE-P8-PRIV-NEXT: nop
; BE-P8-PRIV-NEXT: lwz r4, 16(r30) ; BE-P8-PRIV-NEXT: lwz r4, 16(r30)
▲ Show 20 Lines • Show All 201 Lines • ▼ Show 20 Lines
; LE-P10-O0-NEXT: hashchk r0, -24(r1) ; LE-P10-O0-NEXT: hashchk r0, -24(r1)
; LE-P10-O0-NEXT: mtlr r0 ; LE-P10-O0-NEXT: mtlr r0
; LE-P10-O0-NEXT: blr ; LE-P10-O0-NEXT: blr
; ;
; LE-P9-O0-LABEL: aligned: ; LE-P9-O0-LABEL: aligned:
; LE-P9-O0: # %bb.0: # %entry ; LE-P9-O0: # %bb.0: # %entry
; LE-P9-O0-NEXT: mflr r0 ; LE-P9-O0-NEXT: mflr r0
; LE-P9-O0-NEXT: std r30, -16(r1) ; LE-P9-O0-NEXT: std r30, -16(r1)
; LE-P9-O0-NEXT: mr r30, r1
; LE-P9-O0-NEXT: std r0, 16(r1) ; LE-P9-O0-NEXT: std r0, 16(r1)
; LE-P9-O0-NEXT: hashst r0, -24(r1) ; LE-P9-O0-NEXT: hashst r0, -24(r1)
; LE-P9-O0-NEXT: mr r30, r1
; LE-P9-O0-NEXT: clrldi r0, r1, 49 ; LE-P9-O0-NEXT: clrldi r0, r1, 49
; LE-P9-O0-NEXT: lis r12, -1 ; LE-P9-O0-NEXT: lis r12, -1
; LE-P9-O0-NEXT: subc r0, r12, r0 ; LE-P9-O0-NEXT: subc r0, r12, r0
; LE-P9-O0-NEXT: stdux r1, r1, r0 ; LE-P9-O0-NEXT: stdux r1, r1, r0
; LE-P9-O0-NEXT: std r3, 32752(r1) # 8-byte Folded Spill ; LE-P9-O0-NEXT: std r3, 32752(r1) # 8-byte Folded Spill
; LE-P9-O0-NEXT: lwz r4, 4(r3) ; LE-P9-O0-NEXT: lwz r4, 4(r3)
; LE-P9-O0-NEXT: lis r5, 0 ; LE-P9-O0-NEXT: lis r5, 0
; LE-P9-O0-NEXT: ori r5, r5, 65508 ; LE-P9-O0-NEXT: ori r5, r5, 65508
Show All 24 Lines
; LE-P9-O0-NEXT: hashchk r0, -24(r1) ; LE-P9-O0-NEXT: hashchk r0, -24(r1)
; LE-P9-O0-NEXT: mtlr r0 ; LE-P9-O0-NEXT: mtlr r0
; LE-P9-O0-NEXT: blr ; LE-P9-O0-NEXT: blr
; ;
; LE-P8-O0-LABEL: aligned: ; LE-P8-O0-LABEL: aligned:
; LE-P8-O0: # %bb.0: # %entry ; LE-P8-O0: # %bb.0: # %entry
; LE-P8-O0-NEXT: mflr r0 ; LE-P8-O0-NEXT: mflr r0
; LE-P8-O0-NEXT: std r30, -16(r1) ; LE-P8-O0-NEXT: std r30, -16(r1)
; LE-P8-O0-NEXT: mr r30, r1
; LE-P8-O0-NEXT: std r0, 16(r1) ; LE-P8-O0-NEXT: std r0, 16(r1)
; LE-P8-O0-NEXT: hashst r0, -24(r1) ; LE-P8-O0-NEXT: hashst r0, -24(r1)
; LE-P8-O0-NEXT: mr r30, r1
; LE-P8-O0-NEXT: clrldi r0, r1, 49 ; LE-P8-O0-NEXT: clrldi r0, r1, 49
; LE-P8-O0-NEXT: lis r12, -1 ; LE-P8-O0-NEXT: lis r12, -1
; LE-P8-O0-NEXT: subc r0, r12, r0 ; LE-P8-O0-NEXT: subc r0, r12, r0
; LE-P8-O0-NEXT: stdux r1, r1, r0 ; LE-P8-O0-NEXT: stdux r1, r1, r0
; LE-P8-O0-NEXT: std r3, 32752(r1) # 8-byte Folded Spill ; LE-P8-O0-NEXT: std r3, 32752(r1) # 8-byte Folded Spill
; LE-P8-O0-NEXT: lwz r4, 4(r3) ; LE-P8-O0-NEXT: lwz r4, 4(r3)
; LE-P8-O0-NEXT: lis r5, 0 ; LE-P8-O0-NEXT: lis r5, 0
; LE-P8-O0-NEXT: ori r5, r5, 65508 ; LE-P8-O0-NEXT: ori r5, r5, 65508
▲ Show 20 Lines • Show All 584 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/ppcf128-constrained-fp-intrinsics.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -O3 -mtriple=powerpc64le-linux-gnu < %s | FileCheck --check-prefix=PC64LE %s ; RUN: llc -O3 -mtriple=powerpc64le-linux-gnu < %s | FileCheck --check-prefix=PC64LE %s
; RUN: llc -O3 -mtriple=powerpc64le-linux-gnu -mcpu=pwr9 < %s | FileCheck --check-prefix=PC64LE9 %s ; RUN: llc -O3 -mtriple=powerpc64le-linux-gnu -mcpu=pwr9 < %s | FileCheck --check-prefix=PC64LE9 %s
; RUN: llc -O3 -mtriple=powerpc64-linux-gnu < %s | FileCheck --check-prefix=PC64 %s ; RUN: llc -O3 -mtriple=powerpc64-linux-gnu < %s | FileCheck --check-prefix=PC64 %s
define ppc_fp128 @test_fadd_ppc_fp128(ppc_fp128 %first, ppc_fp128 %second) #0 { define ppc_fp128 @test_fadd_ppc_fp128(ppc_fp128 %first, ppc_fp128 %second) #0 {
; PC64LE-LABEL: test_fadd_ppc_fp128: ; PC64LE-LABEL: test_fadd_ppc_fp128:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -32(1) ; PC64LE-NEXT: stdu 1, -32(1)
; PC64LE-NEXT: std 0, 48(1)
; PC64LE-NEXT: bl __gcc_qadd ; PC64LE-NEXT: bl __gcc_qadd
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: addi 1, 1, 32 ; PC64LE-NEXT: addi 1, 1, 32
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: test_fadd_ppc_fp128: ; PC64LE9-LABEL: test_fadd_ppc_fp128:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -32(1) ; PC64LE9-NEXT: stdu 1, -32(1)
; PC64LE9-NEXT: std 0, 48(1)
; PC64LE9-NEXT: bl __gcc_qadd ; PC64LE9-NEXT: bl __gcc_qadd
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addi 1, 1, 32 ; PC64LE9-NEXT: addi 1, 1, 32
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
; ;
; PC64-LABEL: test_fadd_ppc_fp128: ; PC64-LABEL: test_fadd_ppc_fp128:
; PC64: # %bb.0: # %entry ; PC64: # %bb.0: # %entry
; PC64-NEXT: mflr 0 ; PC64-NEXT: mflr 0
; PC64-NEXT: std 0, 16(1)
; PC64-NEXT: stdu 1, -112(1) ; PC64-NEXT: stdu 1, -112(1)
; PC64-NEXT: std 0, 128(1)
; PC64-NEXT: bl __gcc_qadd ; PC64-NEXT: bl __gcc_qadd
; PC64-NEXT: nop ; PC64-NEXT: nop
; PC64-NEXT: addi 1, 1, 112 ; PC64-NEXT: addi 1, 1, 112
; PC64-NEXT: ld 0, 16(1) ; PC64-NEXT: ld 0, 16(1)
; PC64-NEXT: mtlr 0 ; PC64-NEXT: mtlr 0
; PC64-NEXT: blr ; PC64-NEXT: blr
entry: entry:
%add = call ppc_fp128 @llvm.experimental.constrained.fadd.ppcf128( %add = call ppc_fp128 @llvm.experimental.constrained.fadd.ppcf128(
ppc_fp128 %first, ppc_fp128 %first,
ppc_fp128 %second, ppc_fp128 %second,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret ppc_fp128 %add ret ppc_fp128 %add
} }
define ppc_fp128 @test_fsub_ppc_fp128(ppc_fp128 %first, ppc_fp128 %second) #0 { define ppc_fp128 @test_fsub_ppc_fp128(ppc_fp128 %first, ppc_fp128 %second) #0 {
; PC64LE-LABEL: test_fsub_ppc_fp128: ; PC64LE-LABEL: test_fsub_ppc_fp128:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -32(1) ; PC64LE-NEXT: stdu 1, -32(1)
; PC64LE-NEXT: std 0, 48(1)
; PC64LE-NEXT: bl __gcc_qsub ; PC64LE-NEXT: bl __gcc_qsub
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: addi 1, 1, 32 ; PC64LE-NEXT: addi 1, 1, 32
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: test_fsub_ppc_fp128: ; PC64LE9-LABEL: test_fsub_ppc_fp128:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -32(1) ; PC64LE9-NEXT: stdu 1, -32(1)
; PC64LE9-NEXT: std 0, 48(1)
; PC64LE9-NEXT: bl __gcc_qsub ; PC64LE9-NEXT: bl __gcc_qsub
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addi 1, 1, 32 ; PC64LE9-NEXT: addi 1, 1, 32
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
; ;
; PC64-LABEL: test_fsub_ppc_fp128: ; PC64-LABEL: test_fsub_ppc_fp128:
; PC64: # %bb.0: # %entry ; PC64: # %bb.0: # %entry
; PC64-NEXT: mflr 0 ; PC64-NEXT: mflr 0
; PC64-NEXT: std 0, 16(1)
; PC64-NEXT: stdu 1, -112(1) ; PC64-NEXT: stdu 1, -112(1)
; PC64-NEXT: std 0, 128(1)
; PC64-NEXT: bl __gcc_qsub ; PC64-NEXT: bl __gcc_qsub
; PC64-NEXT: nop ; PC64-NEXT: nop
; PC64-NEXT: addi 1, 1, 112 ; PC64-NEXT: addi 1, 1, 112
; PC64-NEXT: ld 0, 16(1) ; PC64-NEXT: ld 0, 16(1)
; PC64-NEXT: mtlr 0 ; PC64-NEXT: mtlr 0
; PC64-NEXT: blr ; PC64-NEXT: blr
entry: entry:
%sub = call ppc_fp128 @llvm.experimental.constrained.fsub.ppcf128( %sub = call ppc_fp128 @llvm.experimental.constrained.fsub.ppcf128(
ppc_fp128 %first, ppc_fp128 %first,
ppc_fp128 %second, ppc_fp128 %second,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret ppc_fp128 %sub ret ppc_fp128 %sub
} }
define ppc_fp128 @test_fmul_ppc_fp128(ppc_fp128 %first, ppc_fp128 %second) #0 { define ppc_fp128 @test_fmul_ppc_fp128(ppc_fp128 %first, ppc_fp128 %second) #0 {
; PC64LE-LABEL: test_fmul_ppc_fp128: ; PC64LE-LABEL: test_fmul_ppc_fp128:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -32(1) ; PC64LE-NEXT: stdu 1, -32(1)
; PC64LE-NEXT: std 0, 48(1)
; PC64LE-NEXT: bl __gcc_qmul ; PC64LE-NEXT: bl __gcc_qmul
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: addi 1, 1, 32 ; PC64LE-NEXT: addi 1, 1, 32
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: test_fmul_ppc_fp128: ; PC64LE9-LABEL: test_fmul_ppc_fp128:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -32(1) ; PC64LE9-NEXT: stdu 1, -32(1)
; PC64LE9-NEXT: std 0, 48(1)
; PC64LE9-NEXT: bl __gcc_qmul ; PC64LE9-NEXT: bl __gcc_qmul
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addi 1, 1, 32 ; PC64LE9-NEXT: addi 1, 1, 32
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
; ;
; PC64-LABEL: test_fmul_ppc_fp128: ; PC64-LABEL: test_fmul_ppc_fp128:
; PC64: # %bb.0: # %entry ; PC64: # %bb.0: # %entry
; PC64-NEXT: mflr 0 ; PC64-NEXT: mflr 0
; PC64-NEXT: std 0, 16(1)
; PC64-NEXT: stdu 1, -112(1) ; PC64-NEXT: stdu 1, -112(1)
; PC64-NEXT: std 0, 128(1)
; PC64-NEXT: bl __gcc_qmul ; PC64-NEXT: bl __gcc_qmul
; PC64-NEXT: nop ; PC64-NEXT: nop
; PC64-NEXT: addi 1, 1, 112 ; PC64-NEXT: addi 1, 1, 112
; PC64-NEXT: ld 0, 16(1) ; PC64-NEXT: ld 0, 16(1)
; PC64-NEXT: mtlr 0 ; PC64-NEXT: mtlr 0
; PC64-NEXT: blr ; PC64-NEXT: blr
entry: entry:
%mul = call ppc_fp128 @llvm.experimental.constrained.fmul.ppcf128( %mul = call ppc_fp128 @llvm.experimental.constrained.fmul.ppcf128(
ppc_fp128 %first, ppc_fp128 %first,
ppc_fp128 %second, ppc_fp128 %second,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret ppc_fp128 %mul ret ppc_fp128 %mul
} }
define ppc_fp128 @test_fdiv_ppc_fp128(ppc_fp128 %first, ppc_fp128 %second) #0 { define ppc_fp128 @test_fdiv_ppc_fp128(ppc_fp128 %first, ppc_fp128 %second) #0 {
; PC64LE-LABEL: test_fdiv_ppc_fp128: ; PC64LE-LABEL: test_fdiv_ppc_fp128:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -32(1) ; PC64LE-NEXT: stdu 1, -32(1)
; PC64LE-NEXT: std 0, 48(1)
; PC64LE-NEXT: bl __gcc_qdiv ; PC64LE-NEXT: bl __gcc_qdiv
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: addi 1, 1, 32 ; PC64LE-NEXT: addi 1, 1, 32
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: test_fdiv_ppc_fp128: ; PC64LE9-LABEL: test_fdiv_ppc_fp128:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -32(1) ; PC64LE9-NEXT: stdu 1, -32(1)
; PC64LE9-NEXT: std 0, 48(1)
; PC64LE9-NEXT: bl __gcc_qdiv ; PC64LE9-NEXT: bl __gcc_qdiv
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addi 1, 1, 32 ; PC64LE9-NEXT: addi 1, 1, 32
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
; ;
; PC64-LABEL: test_fdiv_ppc_fp128: ; PC64-LABEL: test_fdiv_ppc_fp128:
; PC64: # %bb.0: # %entry ; PC64: # %bb.0: # %entry
; PC64-NEXT: mflr 0 ; PC64-NEXT: mflr 0
; PC64-NEXT: std 0, 16(1)
; PC64-NEXT: stdu 1, -112(1) ; PC64-NEXT: stdu 1, -112(1)
; PC64-NEXT: std 0, 128(1)
; PC64-NEXT: bl __gcc_qdiv ; PC64-NEXT: bl __gcc_qdiv
; PC64-NEXT: nop ; PC64-NEXT: nop
; PC64-NEXT: addi 1, 1, 112 ; PC64-NEXT: addi 1, 1, 112
; PC64-NEXT: ld 0, 16(1) ; PC64-NEXT: ld 0, 16(1)
; PC64-NEXT: mtlr 0 ; PC64-NEXT: mtlr 0
; PC64-NEXT: blr ; PC64-NEXT: blr
entry: entry:
%div = call ppc_fp128 @llvm.experimental.constrained.fdiv.ppcf128( %div = call ppc_fp128 @llvm.experimental.constrained.fdiv.ppcf128(
ppc_fp128 %first, ppc_fp128 %first,
ppc_fp128 %second, ppc_fp128 %second,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret ppc_fp128 %div ret ppc_fp128 %div
} }
define ppc_fp128 @test_frem_ppc_fp128(ppc_fp128 %first, ppc_fp128 %second) #0 { define ppc_fp128 @test_frem_ppc_fp128(ppc_fp128 %first, ppc_fp128 %second) #0 {
; PC64LE-LABEL: test_frem_ppc_fp128: ; PC64LE-LABEL: test_frem_ppc_fp128:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -32(1) ; PC64LE-NEXT: stdu 1, -32(1)
; PC64LE-NEXT: std 0, 48(1)
; PC64LE-NEXT: bl fmodl ; PC64LE-NEXT: bl fmodl
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: addi 1, 1, 32 ; PC64LE-NEXT: addi 1, 1, 32
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: test_frem_ppc_fp128: ; PC64LE9-LABEL: test_frem_ppc_fp128:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -32(1) ; PC64LE9-NEXT: stdu 1, -32(1)
; PC64LE9-NEXT: std 0, 48(1)
; PC64LE9-NEXT: bl fmodl ; PC64LE9-NEXT: bl fmodl
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addi 1, 1, 32 ; PC64LE9-NEXT: addi 1, 1, 32
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
; ;
; PC64-LABEL: test_frem_ppc_fp128: ; PC64-LABEL: test_frem_ppc_fp128:
; PC64: # %bb.0: # %entry ; PC64: # %bb.0: # %entry
; PC64-NEXT: mflr 0 ; PC64-NEXT: mflr 0
; PC64-NEXT: std 0, 16(1)
; PC64-NEXT: stdu 1, -112(1) ; PC64-NEXT: stdu 1, -112(1)
; PC64-NEXT: std 0, 128(1)
; PC64-NEXT: bl fmodl ; PC64-NEXT: bl fmodl
; PC64-NEXT: nop ; PC64-NEXT: nop
; PC64-NEXT: addi 1, 1, 112 ; PC64-NEXT: addi 1, 1, 112
; PC64-NEXT: ld 0, 16(1) ; PC64-NEXT: ld 0, 16(1)
; PC64-NEXT: mtlr 0 ; PC64-NEXT: mtlr 0
; PC64-NEXT: blr ; PC64-NEXT: blr
entry: entry:
%rem = call ppc_fp128 @llvm.experimental.constrained.frem.ppcf128( %rem = call ppc_fp128 @llvm.experimental.constrained.frem.ppcf128(
ppc_fp128 %first, ppc_fp128 %first,
ppc_fp128 %second, ppc_fp128 %second,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret ppc_fp128 %rem ret ppc_fp128 %rem
} }
define ppc_fp128 @test_fma_ppc_fp128(ppc_fp128 %first, ppc_fp128 %second, ppc_fp128 %third) #0 { define ppc_fp128 @test_fma_ppc_fp128(ppc_fp128 %first, ppc_fp128 %second, ppc_fp128 %third) #0 {
; PC64LE-LABEL: test_fma_ppc_fp128: ; PC64LE-LABEL: test_fma_ppc_fp128:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -32(1) ; PC64LE-NEXT: stdu 1, -32(1)
; PC64LE-NEXT: std 0, 48(1)
; PC64LE-NEXT: bl fmal ; PC64LE-NEXT: bl fmal
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: addi 1, 1, 32 ; PC64LE-NEXT: addi 1, 1, 32
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: test_fma_ppc_fp128: ; PC64LE9-LABEL: test_fma_ppc_fp128:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -32(1) ; PC64LE9-NEXT: stdu 1, -32(1)
; PC64LE9-NEXT: std 0, 48(1)
; PC64LE9-NEXT: bl fmal ; PC64LE9-NEXT: bl fmal
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addi 1, 1, 32 ; PC64LE9-NEXT: addi 1, 1, 32
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
; ;
; PC64-LABEL: test_fma_ppc_fp128: ; PC64-LABEL: test_fma_ppc_fp128:
; PC64: # %bb.0: # %entry ; PC64: # %bb.0: # %entry
; PC64-NEXT: mflr 0 ; PC64-NEXT: mflr 0
; PC64-NEXT: std 0, 16(1)
; PC64-NEXT: stdu 1, -112(1) ; PC64-NEXT: stdu 1, -112(1)
; PC64-NEXT: std 0, 128(1)
; PC64-NEXT: bl fmal ; PC64-NEXT: bl fmal
; PC64-NEXT: nop ; PC64-NEXT: nop
; PC64-NEXT: addi 1, 1, 112 ; PC64-NEXT: addi 1, 1, 112
; PC64-NEXT: ld 0, 16(1) ; PC64-NEXT: ld 0, 16(1)
; PC64-NEXT: mtlr 0 ; PC64-NEXT: mtlr 0
; PC64-NEXT: blr ; PC64-NEXT: blr
entry: entry:
%add = call ppc_fp128 @llvm.experimental.constrained.fma.ppcf128( %add = call ppc_fp128 @llvm.experimental.constrained.fma.ppcf128(
ppc_fp128 %first, ppc_fp128 %first,
ppc_fp128 %second, ppc_fp128 %second,
ppc_fp128 %third, ppc_fp128 %third,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret ppc_fp128 %add ret ppc_fp128 %add
} }
define ppc_fp128 @test_sqrt_ppc_fp128(ppc_fp128 %first) #0 { define ppc_fp128 @test_sqrt_ppc_fp128(ppc_fp128 %first) #0 {
; PC64LE-LABEL: test_sqrt_ppc_fp128: ; PC64LE-LABEL: test_sqrt_ppc_fp128:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -32(1) ; PC64LE-NEXT: stdu 1, -32(1)
; PC64LE-NEXT: std 0, 48(1)
; PC64LE-NEXT: bl sqrtl ; PC64LE-NEXT: bl sqrtl
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: addi 1, 1, 32 ; PC64LE-NEXT: addi 1, 1, 32
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: test_sqrt_ppc_fp128: ; PC64LE9-LABEL: test_sqrt_ppc_fp128:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -32(1) ; PC64LE9-NEXT: stdu 1, -32(1)
; PC64LE9-NEXT: std 0, 48(1)
; PC64LE9-NEXT: bl sqrtl ; PC64LE9-NEXT: bl sqrtl
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addi 1, 1, 32 ; PC64LE9-NEXT: addi 1, 1, 32
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
; ;
; PC64-LABEL: test_sqrt_ppc_fp128: ; PC64-LABEL: test_sqrt_ppc_fp128:
; PC64: # %bb.0: # %entry ; PC64: # %bb.0: # %entry
; PC64-NEXT: mflr 0 ; PC64-NEXT: mflr 0
; PC64-NEXT: std 0, 16(1)
; PC64-NEXT: stdu 1, -112(1) ; PC64-NEXT: stdu 1, -112(1)
; PC64-NEXT: std 0, 128(1)
; PC64-NEXT: bl sqrtl ; PC64-NEXT: bl sqrtl
; PC64-NEXT: nop ; PC64-NEXT: nop
; PC64-NEXT: addi 1, 1, 112 ; PC64-NEXT: addi 1, 1, 112
; PC64-NEXT: ld 0, 16(1) ; PC64-NEXT: ld 0, 16(1)
; PC64-NEXT: mtlr 0 ; PC64-NEXT: mtlr 0
; PC64-NEXT: blr ; PC64-NEXT: blr
entry: entry:
%sqrt = call ppc_fp128 @llvm.experimental.constrained.sqrt.ppcf128( %sqrt = call ppc_fp128 @llvm.experimental.constrained.sqrt.ppcf128(
ppc_fp128 %first, ppc_fp128 %first,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret ppc_fp128 %sqrt ret ppc_fp128 %sqrt
} }
define ppc_fp128 @test_pow_ppc_fp128(ppc_fp128 %first, ppc_fp128 %second) #0 { define ppc_fp128 @test_pow_ppc_fp128(ppc_fp128 %first, ppc_fp128 %second) #0 {
; PC64LE-LABEL: test_pow_ppc_fp128: ; PC64LE-LABEL: test_pow_ppc_fp128:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -32(1) ; PC64LE-NEXT: stdu 1, -32(1)
; PC64LE-NEXT: std 0, 48(1)
; PC64LE-NEXT: bl powl ; PC64LE-NEXT: bl powl
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: addi 1, 1, 32 ; PC64LE-NEXT: addi 1, 1, 32
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: test_pow_ppc_fp128: ; PC64LE9-LABEL: test_pow_ppc_fp128:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -32(1) ; PC64LE9-NEXT: stdu 1, -32(1)
; PC64LE9-NEXT: std 0, 48(1)
; PC64LE9-NEXT: bl powl ; PC64LE9-NEXT: bl powl
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addi 1, 1, 32 ; PC64LE9-NEXT: addi 1, 1, 32
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
; ;
; PC64-LABEL: test_pow_ppc_fp128: ; PC64-LABEL: test_pow_ppc_fp128:
; PC64: # %bb.0: # %entry ; PC64: # %bb.0: # %entry
; PC64-NEXT: mflr 0 ; PC64-NEXT: mflr 0
; PC64-NEXT: std 0, 16(1)
; PC64-NEXT: stdu 1, -112(1) ; PC64-NEXT: stdu 1, -112(1)
; PC64-NEXT: std 0, 128(1)
; PC64-NEXT: bl powl ; PC64-NEXT: bl powl
; PC64-NEXT: nop ; PC64-NEXT: nop
; PC64-NEXT: addi 1, 1, 112 ; PC64-NEXT: addi 1, 1, 112
; PC64-NEXT: ld 0, 16(1) ; PC64-NEXT: ld 0, 16(1)
; PC64-NEXT: mtlr 0 ; PC64-NEXT: mtlr 0
; PC64-NEXT: blr ; PC64-NEXT: blr
entry: entry:
%pow = call ppc_fp128 @llvm.experimental.constrained.pow.ppcf128( %pow = call ppc_fp128 @llvm.experimental.constrained.pow.ppcf128(
ppc_fp128 %first, ppc_fp128 %first,
ppc_fp128 %second, ppc_fp128 %second,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret ppc_fp128 %pow ret ppc_fp128 %pow
} }
define ppc_fp128 @test_powi_ppc_fp128(ppc_fp128 %first, i32 %second) #0 { define ppc_fp128 @test_powi_ppc_fp128(ppc_fp128 %first, i32 %second) #0 {
; PC64LE-LABEL: test_powi_ppc_fp128: ; PC64LE-LABEL: test_powi_ppc_fp128:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -32(1) ; PC64LE-NEXT: stdu 1, -32(1)
; PC64LE-NEXT: clrldi 5, 5, 32 ; PC64LE-NEXT: clrldi 5, 5, 32
; PC64LE-NEXT: std 0, 48(1)
; PC64LE-NEXT: bl __powitf2 ; PC64LE-NEXT: bl __powitf2
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: addi 1, 1, 32 ; PC64LE-NEXT: addi 1, 1, 32
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: test_powi_ppc_fp128: ; PC64LE9-LABEL: test_powi_ppc_fp128:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -32(1) ; PC64LE9-NEXT: stdu 1, -32(1)
; PC64LE9-NEXT: clrldi 5, 5, 32 ; PC64LE9-NEXT: clrldi 5, 5, 32
; PC64LE9-NEXT: std 0, 48(1)
; PC64LE9-NEXT: bl __powitf2 ; PC64LE9-NEXT: bl __powitf2
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addi 1, 1, 32 ; PC64LE9-NEXT: addi 1, 1, 32
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
; ;
; PC64-LABEL: test_powi_ppc_fp128: ; PC64-LABEL: test_powi_ppc_fp128:
; PC64: # %bb.0: # %entry ; PC64: # %bb.0: # %entry
; PC64-NEXT: mflr 0 ; PC64-NEXT: mflr 0
; PC64-NEXT: std 0, 16(1)
; PC64-NEXT: stdu 1, -112(1) ; PC64-NEXT: stdu 1, -112(1)
; PC64-NEXT: clrldi 5, 5, 32 ; PC64-NEXT: clrldi 5, 5, 32
; PC64-NEXT: std 0, 128(1)
; PC64-NEXT: bl __powitf2 ; PC64-NEXT: bl __powitf2
; PC64-NEXT: nop ; PC64-NEXT: nop
; PC64-NEXT: addi 1, 1, 112 ; PC64-NEXT: addi 1, 1, 112
; PC64-NEXT: ld 0, 16(1) ; PC64-NEXT: ld 0, 16(1)
; PC64-NEXT: mtlr 0 ; PC64-NEXT: mtlr 0
; PC64-NEXT: blr ; PC64-NEXT: blr
entry: entry:
%powi = call ppc_fp128 @llvm.experimental.constrained.powi.ppcf128( %powi = call ppc_fp128 @llvm.experimental.constrained.powi.ppcf128(
ppc_fp128 %first, ppc_fp128 %first,
i32 %second, i32 %second,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret ppc_fp128 %powi ret ppc_fp128 %powi
} }
define ppc_fp128 @test_sin_ppc_fp128(ppc_fp128 %first) #0 { define ppc_fp128 @test_sin_ppc_fp128(ppc_fp128 %first) #0 {
; PC64LE-LABEL: test_sin_ppc_fp128: ; PC64LE-LABEL: test_sin_ppc_fp128:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -32(1) ; PC64LE-NEXT: stdu 1, -32(1)
; PC64LE-NEXT: std 0, 48(1)
; PC64LE-NEXT: bl sinl ; PC64LE-NEXT: bl sinl
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: addi 1, 1, 32 ; PC64LE-NEXT: addi 1, 1, 32
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: test_sin_ppc_fp128: ; PC64LE9-LABEL: test_sin_ppc_fp128:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -32(1) ; PC64LE9-NEXT: stdu 1, -32(1)
; PC64LE9-NEXT: std 0, 48(1)
; PC64LE9-NEXT: bl sinl ; PC64LE9-NEXT: bl sinl
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addi 1, 1, 32 ; PC64LE9-NEXT: addi 1, 1, 32
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
; ;
; PC64-LABEL: test_sin_ppc_fp128: ; PC64-LABEL: test_sin_ppc_fp128:
; PC64: # %bb.0: # %entry ; PC64: # %bb.0: # %entry
; PC64-NEXT: mflr 0 ; PC64-NEXT: mflr 0
; PC64-NEXT: std 0, 16(1)
; PC64-NEXT: stdu 1, -112(1) ; PC64-NEXT: stdu 1, -112(1)
; PC64-NEXT: std 0, 128(1)
; PC64-NEXT: bl sinl ; PC64-NEXT: bl sinl
; PC64-NEXT: nop ; PC64-NEXT: nop
; PC64-NEXT: addi 1, 1, 112 ; PC64-NEXT: addi 1, 1, 112
; PC64-NEXT: ld 0, 16(1) ; PC64-NEXT: ld 0, 16(1)
; PC64-NEXT: mtlr 0 ; PC64-NEXT: mtlr 0
; PC64-NEXT: blr ; PC64-NEXT: blr
entry: entry:
%sin = call ppc_fp128 @llvm.experimental.constrained.sin.ppcf128( %sin = call ppc_fp128 @llvm.experimental.constrained.sin.ppcf128(
ppc_fp128 %first, ppc_fp128 %first,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret ppc_fp128 %sin ret ppc_fp128 %sin
} }
define ppc_fp128 @test_cos_ppc_fp128(ppc_fp128 %first) #0 { define ppc_fp128 @test_cos_ppc_fp128(ppc_fp128 %first) #0 {
; PC64LE-LABEL: test_cos_ppc_fp128: ; PC64LE-LABEL: test_cos_ppc_fp128:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -32(1) ; PC64LE-NEXT: stdu 1, -32(1)
; PC64LE-NEXT: std 0, 48(1)
; PC64LE-NEXT: bl cosl ; PC64LE-NEXT: bl cosl
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: addi 1, 1, 32 ; PC64LE-NEXT: addi 1, 1, 32
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: test_cos_ppc_fp128: ; PC64LE9-LABEL: test_cos_ppc_fp128:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -32(1) ; PC64LE9-NEXT: stdu 1, -32(1)
; PC64LE9-NEXT: std 0, 48(1)
; PC64LE9-NEXT: bl cosl ; PC64LE9-NEXT: bl cosl
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addi 1, 1, 32 ; PC64LE9-NEXT: addi 1, 1, 32
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
; ;
; PC64-LABEL: test_cos_ppc_fp128: ; PC64-LABEL: test_cos_ppc_fp128:
; PC64: # %bb.0: # %entry ; PC64: # %bb.0: # %entry
; PC64-NEXT: mflr 0 ; PC64-NEXT: mflr 0
; PC64-NEXT: std 0, 16(1)
; PC64-NEXT: stdu 1, -112(1) ; PC64-NEXT: stdu 1, -112(1)
; PC64-NEXT: std 0, 128(1)
; PC64-NEXT: bl cosl ; PC64-NEXT: bl cosl
; PC64-NEXT: nop ; PC64-NEXT: nop
; PC64-NEXT: addi 1, 1, 112 ; PC64-NEXT: addi 1, 1, 112
; PC64-NEXT: ld 0, 16(1) ; PC64-NEXT: ld 0, 16(1)
; PC64-NEXT: mtlr 0 ; PC64-NEXT: mtlr 0
; PC64-NEXT: blr ; PC64-NEXT: blr
entry: entry:
%cos = call ppc_fp128 @llvm.experimental.constrained.cos.ppcf128( %cos = call ppc_fp128 @llvm.experimental.constrained.cos.ppcf128(
ppc_fp128 %first, ppc_fp128 %first,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret ppc_fp128 %cos ret ppc_fp128 %cos
} }
define ppc_fp128 @test_exp_ppc_fp128(ppc_fp128 %first) #0 { define ppc_fp128 @test_exp_ppc_fp128(ppc_fp128 %first) #0 {
; PC64LE-LABEL: test_exp_ppc_fp128: ; PC64LE-LABEL: test_exp_ppc_fp128:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -32(1) ; PC64LE-NEXT: stdu 1, -32(1)
; PC64LE-NEXT: std 0, 48(1)
; PC64LE-NEXT: bl expl ; PC64LE-NEXT: bl expl
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: addi 1, 1, 32 ; PC64LE-NEXT: addi 1, 1, 32
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: test_exp_ppc_fp128: ; PC64LE9-LABEL: test_exp_ppc_fp128:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -32(1) ; PC64LE9-NEXT: stdu 1, -32(1)
; PC64LE9-NEXT: std 0, 48(1)
; PC64LE9-NEXT: bl expl ; PC64LE9-NEXT: bl expl
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addi 1, 1, 32 ; PC64LE9-NEXT: addi 1, 1, 32
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
; ;
; PC64-LABEL: test_exp_ppc_fp128: ; PC64-LABEL: test_exp_ppc_fp128:
; PC64: # %bb.0: # %entry ; PC64: # %bb.0: # %entry
; PC64-NEXT: mflr 0 ; PC64-NEXT: mflr 0
; PC64-NEXT: std 0, 16(1)
; PC64-NEXT: stdu 1, -112(1) ; PC64-NEXT: stdu 1, -112(1)
; PC64-NEXT: std 0, 128(1)
; PC64-NEXT: bl expl ; PC64-NEXT: bl expl
; PC64-NEXT: nop ; PC64-NEXT: nop
; PC64-NEXT: addi 1, 1, 112 ; PC64-NEXT: addi 1, 1, 112
; PC64-NEXT: ld 0, 16(1) ; PC64-NEXT: ld 0, 16(1)
; PC64-NEXT: mtlr 0 ; PC64-NEXT: mtlr 0
; PC64-NEXT: blr ; PC64-NEXT: blr
entry: entry:
%exp = call ppc_fp128 @llvm.experimental.constrained.exp.ppcf128( %exp = call ppc_fp128 @llvm.experimental.constrained.exp.ppcf128(
ppc_fp128 %first, ppc_fp128 %first,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret ppc_fp128 %exp ret ppc_fp128 %exp
} }
define ppc_fp128 @test_exp2_ppc_fp128(ppc_fp128 %first) #0 { define ppc_fp128 @test_exp2_ppc_fp128(ppc_fp128 %first) #0 {
; PC64LE-LABEL: test_exp2_ppc_fp128: ; PC64LE-LABEL: test_exp2_ppc_fp128:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -32(1) ; PC64LE-NEXT: stdu 1, -32(1)
; PC64LE-NEXT: std 0, 48(1)
; PC64LE-NEXT: bl exp2l ; PC64LE-NEXT: bl exp2l
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: addi 1, 1, 32 ; PC64LE-NEXT: addi 1, 1, 32
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: test_exp2_ppc_fp128: ; PC64LE9-LABEL: test_exp2_ppc_fp128:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -32(1) ; PC64LE9-NEXT: stdu 1, -32(1)
; PC64LE9-NEXT: std 0, 48(1)
; PC64LE9-NEXT: bl exp2l ; PC64LE9-NEXT: bl exp2l
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addi 1, 1, 32 ; PC64LE9-NEXT: addi 1, 1, 32
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
; ;
; PC64-LABEL: test_exp2_ppc_fp128: ; PC64-LABEL: test_exp2_ppc_fp128:
; PC64: # %bb.0: # %entry ; PC64: # %bb.0: # %entry
; PC64-NEXT: mflr 0 ; PC64-NEXT: mflr 0
; PC64-NEXT: std 0, 16(1)
; PC64-NEXT: stdu 1, -112(1) ; PC64-NEXT: stdu 1, -112(1)
; PC64-NEXT: std 0, 128(1)
; PC64-NEXT: bl exp2l ; PC64-NEXT: bl exp2l
; PC64-NEXT: nop ; PC64-NEXT: nop
; PC64-NEXT: addi 1, 1, 112 ; PC64-NEXT: addi 1, 1, 112
; PC64-NEXT: ld 0, 16(1) ; PC64-NEXT: ld 0, 16(1)
; PC64-NEXT: mtlr 0 ; PC64-NEXT: mtlr 0
; PC64-NEXT: blr ; PC64-NEXT: blr
entry: entry:
%exp2 = call ppc_fp128 @llvm.experimental.constrained.exp2.ppcf128( %exp2 = call ppc_fp128 @llvm.experimental.constrained.exp2.ppcf128(
ppc_fp128 %first, ppc_fp128 %first,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret ppc_fp128 %exp2 ret ppc_fp128 %exp2
} }
define ppc_fp128 @test_log_ppc_fp128(ppc_fp128 %first) #0 { define ppc_fp128 @test_log_ppc_fp128(ppc_fp128 %first) #0 {
; PC64LE-LABEL: test_log_ppc_fp128: ; PC64LE-LABEL: test_log_ppc_fp128:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -32(1) ; PC64LE-NEXT: stdu 1, -32(1)
; PC64LE-NEXT: std 0, 48(1)
; PC64LE-NEXT: bl logl ; PC64LE-NEXT: bl logl
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: addi 1, 1, 32 ; PC64LE-NEXT: addi 1, 1, 32
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: test_log_ppc_fp128: ; PC64LE9-LABEL: test_log_ppc_fp128:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -32(1) ; PC64LE9-NEXT: stdu 1, -32(1)
; PC64LE9-NEXT: std 0, 48(1)
; PC64LE9-NEXT: bl logl ; PC64LE9-NEXT: bl logl
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addi 1, 1, 32 ; PC64LE9-NEXT: addi 1, 1, 32
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
; ;
; PC64-LABEL: test_log_ppc_fp128: ; PC64-LABEL: test_log_ppc_fp128:
; PC64: # %bb.0: # %entry ; PC64: # %bb.0: # %entry
; PC64-NEXT: mflr 0 ; PC64-NEXT: mflr 0
; PC64-NEXT: std 0, 16(1)
; PC64-NEXT: stdu 1, -112(1) ; PC64-NEXT: stdu 1, -112(1)
; PC64-NEXT: std 0, 128(1)
; PC64-NEXT: bl logl ; PC64-NEXT: bl logl
; PC64-NEXT: nop ; PC64-NEXT: nop
; PC64-NEXT: addi 1, 1, 112 ; PC64-NEXT: addi 1, 1, 112
; PC64-NEXT: ld 0, 16(1) ; PC64-NEXT: ld 0, 16(1)
; PC64-NEXT: mtlr 0 ; PC64-NEXT: mtlr 0
; PC64-NEXT: blr ; PC64-NEXT: blr
entry: entry:
%log = call ppc_fp128 @llvm.experimental.constrained.log.ppcf128( %log = call ppc_fp128 @llvm.experimental.constrained.log.ppcf128(
ppc_fp128 %first, ppc_fp128 %first,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret ppc_fp128 %log ret ppc_fp128 %log
} }
define ppc_fp128 @test_log2_ppc_fp128(ppc_fp128 %first) #0 { define ppc_fp128 @test_log2_ppc_fp128(ppc_fp128 %first) #0 {
; PC64LE-LABEL: test_log2_ppc_fp128: ; PC64LE-LABEL: test_log2_ppc_fp128:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -32(1) ; PC64LE-NEXT: stdu 1, -32(1)
; PC64LE-NEXT: std 0, 48(1)
; PC64LE-NEXT: bl log2l ; PC64LE-NEXT: bl log2l
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: addi 1, 1, 32 ; PC64LE-NEXT: addi 1, 1, 32
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: test_log2_ppc_fp128: ; PC64LE9-LABEL: test_log2_ppc_fp128:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -32(1) ; PC64LE9-NEXT: stdu 1, -32(1)
; PC64LE9-NEXT: std 0, 48(1)
; PC64LE9-NEXT: bl log2l ; PC64LE9-NEXT: bl log2l
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addi 1, 1, 32 ; PC64LE9-NEXT: addi 1, 1, 32
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
; ;
; PC64-LABEL: test_log2_ppc_fp128: ; PC64-LABEL: test_log2_ppc_fp128:
; PC64: # %bb.0: # %entry ; PC64: # %bb.0: # %entry
; PC64-NEXT: mflr 0 ; PC64-NEXT: mflr 0
; PC64-NEXT: std 0, 16(1)
; PC64-NEXT: stdu 1, -112(1) ; PC64-NEXT: stdu 1, -112(1)
; PC64-NEXT: std 0, 128(1)
; PC64-NEXT: bl log2l ; PC64-NEXT: bl log2l
; PC64-NEXT: nop ; PC64-NEXT: nop
; PC64-NEXT: addi 1, 1, 112 ; PC64-NEXT: addi 1, 1, 112
; PC64-NEXT: ld 0, 16(1) ; PC64-NEXT: ld 0, 16(1)
; PC64-NEXT: mtlr 0 ; PC64-NEXT: mtlr 0
; PC64-NEXT: blr ; PC64-NEXT: blr
entry: entry:
%log2 = call ppc_fp128 @llvm.experimental.constrained.log2.ppcf128( %log2 = call ppc_fp128 @llvm.experimental.constrained.log2.ppcf128(
ppc_fp128 %first, ppc_fp128 %first,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret ppc_fp128 %log2 ret ppc_fp128 %log2
} }
define ppc_fp128 @test_log10_ppc_fp128(ppc_fp128 %first) #0 { define ppc_fp128 @test_log10_ppc_fp128(ppc_fp128 %first) #0 {
; PC64LE-LABEL: test_log10_ppc_fp128: ; PC64LE-LABEL: test_log10_ppc_fp128:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -32(1) ; PC64LE-NEXT: stdu 1, -32(1)
; PC64LE-NEXT: std 0, 48(1)
; PC64LE-NEXT: bl log10l ; PC64LE-NEXT: bl log10l
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: addi 1, 1, 32 ; PC64LE-NEXT: addi 1, 1, 32
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: test_log10_ppc_fp128: ; PC64LE9-LABEL: test_log10_ppc_fp128:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -32(1) ; PC64LE9-NEXT: stdu 1, -32(1)
; PC64LE9-NEXT: std 0, 48(1)
; PC64LE9-NEXT: bl log10l ; PC64LE9-NEXT: bl log10l
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addi 1, 1, 32 ; PC64LE9-NEXT: addi 1, 1, 32
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
; ;
; PC64-LABEL: test_log10_ppc_fp128: ; PC64-LABEL: test_log10_ppc_fp128:
; PC64: # %bb.0: # %entry ; PC64: # %bb.0: # %entry
; PC64-NEXT: mflr 0 ; PC64-NEXT: mflr 0
; PC64-NEXT: std 0, 16(1)
; PC64-NEXT: stdu 1, -112(1) ; PC64-NEXT: stdu 1, -112(1)
; PC64-NEXT: std 0, 128(1)
; PC64-NEXT: bl log10l ; PC64-NEXT: bl log10l
; PC64-NEXT: nop ; PC64-NEXT: nop
; PC64-NEXT: addi 1, 1, 112 ; PC64-NEXT: addi 1, 1, 112
; PC64-NEXT: ld 0, 16(1) ; PC64-NEXT: ld 0, 16(1)
; PC64-NEXT: mtlr 0 ; PC64-NEXT: mtlr 0
; PC64-NEXT: blr ; PC64-NEXT: blr
entry: entry:
%log10 = call ppc_fp128 @llvm.experimental.constrained.log10.ppcf128( %log10 = call ppc_fp128 @llvm.experimental.constrained.log10.ppcf128(
ppc_fp128 %first, ppc_fp128 %first,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret ppc_fp128 %log10 ret ppc_fp128 %log10
} }
define ppc_fp128 @test_rint_ppc_fp128(ppc_fp128 %first) #0 { define ppc_fp128 @test_rint_ppc_fp128(ppc_fp128 %first) #0 {
; PC64LE-LABEL: test_rint_ppc_fp128: ; PC64LE-LABEL: test_rint_ppc_fp128:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -32(1) ; PC64LE-NEXT: stdu 1, -32(1)
; PC64LE-NEXT: std 0, 48(1)
; PC64LE-NEXT: bl rintl ; PC64LE-NEXT: bl rintl
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: addi 1, 1, 32 ; PC64LE-NEXT: addi 1, 1, 32
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: test_rint_ppc_fp128: ; PC64LE9-LABEL: test_rint_ppc_fp128:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -32(1) ; PC64LE9-NEXT: stdu 1, -32(1)
; PC64LE9-NEXT: std 0, 48(1)
; PC64LE9-NEXT: bl rintl ; PC64LE9-NEXT: bl rintl
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addi 1, 1, 32 ; PC64LE9-NEXT: addi 1, 1, 32
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
; ;
; PC64-LABEL: test_rint_ppc_fp128: ; PC64-LABEL: test_rint_ppc_fp128:
; PC64: # %bb.0: # %entry ; PC64: # %bb.0: # %entry
; PC64-NEXT: mflr 0 ; PC64-NEXT: mflr 0
; PC64-NEXT: std 0, 16(1)
; PC64-NEXT: stdu 1, -112(1) ; PC64-NEXT: stdu 1, -112(1)
; PC64-NEXT: std 0, 128(1)
; PC64-NEXT: bl rintl ; PC64-NEXT: bl rintl
; PC64-NEXT: nop ; PC64-NEXT: nop
; PC64-NEXT: addi 1, 1, 112 ; PC64-NEXT: addi 1, 1, 112
; PC64-NEXT: ld 0, 16(1) ; PC64-NEXT: ld 0, 16(1)
; PC64-NEXT: mtlr 0 ; PC64-NEXT: mtlr 0
; PC64-NEXT: blr ; PC64-NEXT: blr
entry: entry:
%rint = call ppc_fp128 @llvm.experimental.constrained.rint.ppcf128( %rint = call ppc_fp128 @llvm.experimental.constrained.rint.ppcf128(
ppc_fp128 %first, ppc_fp128 %first,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret ppc_fp128 %rint ret ppc_fp128 %rint
} }
define ppc_fp128 @test_nearbyint_ppc_fp128(ppc_fp128 %first) #0 { define ppc_fp128 @test_nearbyint_ppc_fp128(ppc_fp128 %first) #0 {
; PC64LE-LABEL: test_nearbyint_ppc_fp128: ; PC64LE-LABEL: test_nearbyint_ppc_fp128:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -32(1) ; PC64LE-NEXT: stdu 1, -32(1)
; PC64LE-NEXT: std 0, 48(1)
; PC64LE-NEXT: bl nearbyintl ; PC64LE-NEXT: bl nearbyintl
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: addi 1, 1, 32 ; PC64LE-NEXT: addi 1, 1, 32
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: test_nearbyint_ppc_fp128: ; PC64LE9-LABEL: test_nearbyint_ppc_fp128:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -32(1) ; PC64LE9-NEXT: stdu 1, -32(1)
; PC64LE9-NEXT: std 0, 48(1)
; PC64LE9-NEXT: bl nearbyintl ; PC64LE9-NEXT: bl nearbyintl
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addi 1, 1, 32 ; PC64LE9-NEXT: addi 1, 1, 32
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
; ;
; PC64-LABEL: test_nearbyint_ppc_fp128: ; PC64-LABEL: test_nearbyint_ppc_fp128:
; PC64: # %bb.0: # %entry ; PC64: # %bb.0: # %entry
; PC64-NEXT: mflr 0 ; PC64-NEXT: mflr 0
; PC64-NEXT: std 0, 16(1)
; PC64-NEXT: stdu 1, -112(1) ; PC64-NEXT: stdu 1, -112(1)
; PC64-NEXT: std 0, 128(1)
; PC64-NEXT: bl nearbyintl ; PC64-NEXT: bl nearbyintl
; PC64-NEXT: nop ; PC64-NEXT: nop
; PC64-NEXT: addi 1, 1, 112 ; PC64-NEXT: addi 1, 1, 112
; PC64-NEXT: ld 0, 16(1) ; PC64-NEXT: ld 0, 16(1)
; PC64-NEXT: mtlr 0 ; PC64-NEXT: mtlr 0
; PC64-NEXT: blr ; PC64-NEXT: blr
entry: entry:
%nearbyint = call ppc_fp128 @llvm.experimental.constrained.nearbyint.ppcf128( %nearbyint = call ppc_fp128 @llvm.experimental.constrained.nearbyint.ppcf128(
ppc_fp128 %first, ppc_fp128 %first,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret ppc_fp128 %nearbyint ret ppc_fp128 %nearbyint
} }
define ppc_fp128 @test_maxnum_ppc_fp128(ppc_fp128 %first, ppc_fp128 %second) #0 { define ppc_fp128 @test_maxnum_ppc_fp128(ppc_fp128 %first, ppc_fp128 %second) #0 {
; PC64LE-LABEL: test_maxnum_ppc_fp128: ; PC64LE-LABEL: test_maxnum_ppc_fp128:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -32(1) ; PC64LE-NEXT: stdu 1, -32(1)
; PC64LE-NEXT: std 0, 48(1)
; PC64LE-NEXT: bl fmaxl ; PC64LE-NEXT: bl fmaxl
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: addi 1, 1, 32 ; PC64LE-NEXT: addi 1, 1, 32
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: test_maxnum_ppc_fp128: ; PC64LE9-LABEL: test_maxnum_ppc_fp128:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -32(1) ; PC64LE9-NEXT: stdu 1, -32(1)
; PC64LE9-NEXT: std 0, 48(1)
; PC64LE9-NEXT: bl fmaxl ; PC64LE9-NEXT: bl fmaxl
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addi 1, 1, 32 ; PC64LE9-NEXT: addi 1, 1, 32
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
; ;
; PC64-LABEL: test_maxnum_ppc_fp128: ; PC64-LABEL: test_maxnum_ppc_fp128:
; PC64: # %bb.0: # %entry ; PC64: # %bb.0: # %entry
; PC64-NEXT: mflr 0 ; PC64-NEXT: mflr 0
; PC64-NEXT: std 0, 16(1)
; PC64-NEXT: stdu 1, -112(1) ; PC64-NEXT: stdu 1, -112(1)
; PC64-NEXT: std 0, 128(1)
; PC64-NEXT: bl fmaxl ; PC64-NEXT: bl fmaxl
; PC64-NEXT: nop ; PC64-NEXT: nop
; PC64-NEXT: addi 1, 1, 112 ; PC64-NEXT: addi 1, 1, 112
; PC64-NEXT: ld 0, 16(1) ; PC64-NEXT: ld 0, 16(1)
; PC64-NEXT: mtlr 0 ; PC64-NEXT: mtlr 0
; PC64-NEXT: blr ; PC64-NEXT: blr
entry: entry:
%maxnum = call ppc_fp128 @llvm.experimental.constrained.maxnum.ppcf128( %maxnum = call ppc_fp128 @llvm.experimental.constrained.maxnum.ppcf128(
ppc_fp128 %first, ppc_fp128 %first,
ppc_fp128 %second, ppc_fp128 %second,
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret ppc_fp128 %maxnum ret ppc_fp128 %maxnum
} }
define ppc_fp128 @test_minnum_ppc_fp128(ppc_fp128 %first, ppc_fp128 %second) #0 { define ppc_fp128 @test_minnum_ppc_fp128(ppc_fp128 %first, ppc_fp128 %second) #0 {
; PC64LE-LABEL: test_minnum_ppc_fp128: ; PC64LE-LABEL: test_minnum_ppc_fp128:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -32(1) ; PC64LE-NEXT: stdu 1, -32(1)
; PC64LE-NEXT: std 0, 48(1)
; PC64LE-NEXT: bl fminl ; PC64LE-NEXT: bl fminl
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: addi 1, 1, 32 ; PC64LE-NEXT: addi 1, 1, 32
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: test_minnum_ppc_fp128: ; PC64LE9-LABEL: test_minnum_ppc_fp128:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -32(1) ; PC64LE9-NEXT: stdu 1, -32(1)
; PC64LE9-NEXT: std 0, 48(1)
; PC64LE9-NEXT: bl fminl ; PC64LE9-NEXT: bl fminl
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addi 1, 1, 32 ; PC64LE9-NEXT: addi 1, 1, 32
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
; ;
; PC64-LABEL: test_minnum_ppc_fp128: ; PC64-LABEL: test_minnum_ppc_fp128:
; PC64: # %bb.0: # %entry ; PC64: # %bb.0: # %entry
; PC64-NEXT: mflr 0 ; PC64-NEXT: mflr 0
; PC64-NEXT: std 0, 16(1)
; PC64-NEXT: stdu 1, -112(1) ; PC64-NEXT: stdu 1, -112(1)
; PC64-NEXT: std 0, 128(1)
; PC64-NEXT: bl fminl ; PC64-NEXT: bl fminl
; PC64-NEXT: nop ; PC64-NEXT: nop
; PC64-NEXT: addi 1, 1, 112 ; PC64-NEXT: addi 1, 1, 112
; PC64-NEXT: ld 0, 16(1) ; PC64-NEXT: ld 0, 16(1)
; PC64-NEXT: mtlr 0 ; PC64-NEXT: mtlr 0
; PC64-NEXT: blr ; PC64-NEXT: blr
entry: entry:
%minnum = call ppc_fp128 @llvm.experimental.constrained.minnum.ppcf128( %minnum = call ppc_fp128 @llvm.experimental.constrained.minnum.ppcf128(
ppc_fp128 %first, ppc_fp128 %first,
ppc_fp128 %second, ppc_fp128 %second,
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret ppc_fp128 %minnum ret ppc_fp128 %minnum
} }
define ppc_fp128 @test_ceil_ppc_fp128(ppc_fp128 %first) #0 { define ppc_fp128 @test_ceil_ppc_fp128(ppc_fp128 %first) #0 {
; PC64LE-LABEL: test_ceil_ppc_fp128: ; PC64LE-LABEL: test_ceil_ppc_fp128:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -32(1) ; PC64LE-NEXT: stdu 1, -32(1)
; PC64LE-NEXT: std 0, 48(1)
; PC64LE-NEXT: bl ceill ; PC64LE-NEXT: bl ceill
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: addi 1, 1, 32 ; PC64LE-NEXT: addi 1, 1, 32
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: test_ceil_ppc_fp128: ; PC64LE9-LABEL: test_ceil_ppc_fp128:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -32(1) ; PC64LE9-NEXT: stdu 1, -32(1)
; PC64LE9-NEXT: std 0, 48(1)
; PC64LE9-NEXT: bl ceill ; PC64LE9-NEXT: bl ceill
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addi 1, 1, 32 ; PC64LE9-NEXT: addi 1, 1, 32
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
; ;
; PC64-LABEL: test_ceil_ppc_fp128: ; PC64-LABEL: test_ceil_ppc_fp128:
; PC64: # %bb.0: # %entry ; PC64: # %bb.0: # %entry
; PC64-NEXT: mflr 0 ; PC64-NEXT: mflr 0
; PC64-NEXT: std 0, 16(1)
; PC64-NEXT: stdu 1, -112(1) ; PC64-NEXT: stdu 1, -112(1)
; PC64-NEXT: std 0, 128(1)
; PC64-NEXT: bl ceill ; PC64-NEXT: bl ceill
; PC64-NEXT: nop ; PC64-NEXT: nop
; PC64-NEXT: addi 1, 1, 112 ; PC64-NEXT: addi 1, 1, 112
; PC64-NEXT: ld 0, 16(1) ; PC64-NEXT: ld 0, 16(1)
; PC64-NEXT: mtlr 0 ; PC64-NEXT: mtlr 0
; PC64-NEXT: blr ; PC64-NEXT: blr
entry: entry:
%ceil = call ppc_fp128 @llvm.experimental.constrained.ceil.ppcf128( %ceil = call ppc_fp128 @llvm.experimental.constrained.ceil.ppcf128(
ppc_fp128 %first, ppc_fp128 %first,
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret ppc_fp128 %ceil ret ppc_fp128 %ceil
} }
define ppc_fp128 @test_floor_ppc_fp128(ppc_fp128 %first) #0 { define ppc_fp128 @test_floor_ppc_fp128(ppc_fp128 %first) #0 {
; PC64LE-LABEL: test_floor_ppc_fp128: ; PC64LE-LABEL: test_floor_ppc_fp128:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -32(1) ; PC64LE-NEXT: stdu 1, -32(1)
; PC64LE-NEXT: std 0, 48(1)
; PC64LE-NEXT: bl floorl ; PC64LE-NEXT: bl floorl
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: addi 1, 1, 32 ; PC64LE-NEXT: addi 1, 1, 32
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: test_floor_ppc_fp128: ; PC64LE9-LABEL: test_floor_ppc_fp128:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -32(1) ; PC64LE9-NEXT: stdu 1, -32(1)
; PC64LE9-NEXT: std 0, 48(1)
; PC64LE9-NEXT: bl floorl ; PC64LE9-NEXT: bl floorl
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addi 1, 1, 32 ; PC64LE9-NEXT: addi 1, 1, 32
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
; ;
; PC64-LABEL: test_floor_ppc_fp128: ; PC64-LABEL: test_floor_ppc_fp128:
; PC64: # %bb.0: # %entry ; PC64: # %bb.0: # %entry
; PC64-NEXT: mflr 0 ; PC64-NEXT: mflr 0
; PC64-NEXT: std 0, 16(1)
; PC64-NEXT: stdu 1, -112(1) ; PC64-NEXT: stdu 1, -112(1)
; PC64-NEXT: std 0, 128(1)
; PC64-NEXT: bl floorl ; PC64-NEXT: bl floorl
; PC64-NEXT: nop ; PC64-NEXT: nop
; PC64-NEXT: addi 1, 1, 112 ; PC64-NEXT: addi 1, 1, 112
; PC64-NEXT: ld 0, 16(1) ; PC64-NEXT: ld 0, 16(1)
; PC64-NEXT: mtlr 0 ; PC64-NEXT: mtlr 0
; PC64-NEXT: blr ; PC64-NEXT: blr
entry: entry:
%floor = call ppc_fp128 @llvm.experimental.constrained.floor.ppcf128( %floor = call ppc_fp128 @llvm.experimental.constrained.floor.ppcf128(
ppc_fp128 %first, ppc_fp128 %first,
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret ppc_fp128 %floor ret ppc_fp128 %floor
} }
define ppc_fp128 @test_round_ppc_fp128(ppc_fp128 %first) #0 { define ppc_fp128 @test_round_ppc_fp128(ppc_fp128 %first) #0 {
; PC64LE-LABEL: test_round_ppc_fp128: ; PC64LE-LABEL: test_round_ppc_fp128:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -32(1) ; PC64LE-NEXT: stdu 1, -32(1)
; PC64LE-NEXT: std 0, 48(1)
; PC64LE-NEXT: bl roundl ; PC64LE-NEXT: bl roundl
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: addi 1, 1, 32 ; PC64LE-NEXT: addi 1, 1, 32
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: test_round_ppc_fp128: ; PC64LE9-LABEL: test_round_ppc_fp128:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -32(1) ; PC64LE9-NEXT: stdu 1, -32(1)
; PC64LE9-NEXT: std 0, 48(1)
; PC64LE9-NEXT: bl roundl ; PC64LE9-NEXT: bl roundl
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addi 1, 1, 32 ; PC64LE9-NEXT: addi 1, 1, 32
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
; ;
; PC64-LABEL: test_round_ppc_fp128: ; PC64-LABEL: test_round_ppc_fp128:
; PC64: # %bb.0: # %entry ; PC64: # %bb.0: # %entry
; PC64-NEXT: mflr 0 ; PC64-NEXT: mflr 0
; PC64-NEXT: std 0, 16(1)
; PC64-NEXT: stdu 1, -112(1) ; PC64-NEXT: stdu 1, -112(1)
; PC64-NEXT: std 0, 128(1)
; PC64-NEXT: bl roundl ; PC64-NEXT: bl roundl
; PC64-NEXT: nop ; PC64-NEXT: nop
; PC64-NEXT: addi 1, 1, 112 ; PC64-NEXT: addi 1, 1, 112
; PC64-NEXT: ld 0, 16(1) ; PC64-NEXT: ld 0, 16(1)
; PC64-NEXT: mtlr 0 ; PC64-NEXT: mtlr 0
; PC64-NEXT: blr ; PC64-NEXT: blr
entry: entry:
%round = call ppc_fp128 @llvm.experimental.constrained.round.ppcf128( %round = call ppc_fp128 @llvm.experimental.constrained.round.ppcf128(
ppc_fp128 %first, ppc_fp128 %first,
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret ppc_fp128 %round ret ppc_fp128 %round
} }
define ppc_fp128 @test_trunc_ppc_fp128(ppc_fp128 %first) #0 { define ppc_fp128 @test_trunc_ppc_fp128(ppc_fp128 %first) #0 {
; PC64LE-LABEL: test_trunc_ppc_fp128: ; PC64LE-LABEL: test_trunc_ppc_fp128:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -32(1) ; PC64LE-NEXT: stdu 1, -32(1)
; PC64LE-NEXT: std 0, 48(1)
; PC64LE-NEXT: bl truncl ; PC64LE-NEXT: bl truncl
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: addi 1, 1, 32 ; PC64LE-NEXT: addi 1, 1, 32
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: test_trunc_ppc_fp128: ; PC64LE9-LABEL: test_trunc_ppc_fp128:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -32(1) ; PC64LE9-NEXT: stdu 1, -32(1)
; PC64LE9-NEXT: std 0, 48(1)
; PC64LE9-NEXT: bl truncl ; PC64LE9-NEXT: bl truncl
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addi 1, 1, 32 ; PC64LE9-NEXT: addi 1, 1, 32
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
; ;
; PC64-LABEL: test_trunc_ppc_fp128: ; PC64-LABEL: test_trunc_ppc_fp128:
; PC64: # %bb.0: # %entry ; PC64: # %bb.0: # %entry
; PC64-NEXT: mflr 0 ; PC64-NEXT: mflr 0
; PC64-NEXT: std 0, 16(1)
; PC64-NEXT: stdu 1, -112(1) ; PC64-NEXT: stdu 1, -112(1)
; PC64-NEXT: std 0, 128(1)
; PC64-NEXT: bl truncl ; PC64-NEXT: bl truncl
; PC64-NEXT: nop ; PC64-NEXT: nop
; PC64-NEXT: addi 1, 1, 112 ; PC64-NEXT: addi 1, 1, 112
; PC64-NEXT: ld 0, 16(1) ; PC64-NEXT: ld 0, 16(1)
; PC64-NEXT: mtlr 0 ; PC64-NEXT: mtlr 0
; PC64-NEXT: blr ; PC64-NEXT: blr
entry: entry:
%trunc = call ppc_fp128 @llvm.experimental.constrained.trunc.ppcf128( %trunc = call ppc_fp128 @llvm.experimental.constrained.trunc.ppcf128(
▲ Show 20 Lines • Show All 90 Lines • ▼ Show 20 Lines %fpext = call ppc_fp128 @llvm.experimental.constrained.fpext.f64.ppcf128(
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret ppc_fp128 %fpext ret ppc_fp128 %fpext
} }
define i64 @test_fptosi_ppc_i64_ppc_fp128(ppc_fp128 %first) #0 { define i64 @test_fptosi_ppc_i64_ppc_fp128(ppc_fp128 %first) #0 {
; PC64LE-LABEL: test_fptosi_ppc_i64_ppc_fp128: ; PC64LE-LABEL: test_fptosi_ppc_i64_ppc_fp128:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -32(1) ; PC64LE-NEXT: stdu 1, -32(1)
; PC64LE-NEXT: std 0, 48(1)
; PC64LE-NEXT: bl __fixtfdi ; PC64LE-NEXT: bl __fixtfdi
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: addi 1, 1, 32 ; PC64LE-NEXT: addi 1, 1, 32
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: test_fptosi_ppc_i64_ppc_fp128: ; PC64LE9-LABEL: test_fptosi_ppc_i64_ppc_fp128:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -32(1) ; PC64LE9-NEXT: stdu 1, -32(1)
; PC64LE9-NEXT: std 0, 48(1)
; PC64LE9-NEXT: bl __fixtfdi ; PC64LE9-NEXT: bl __fixtfdi
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addi 1, 1, 32 ; PC64LE9-NEXT: addi 1, 1, 32
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
; ;
; PC64-LABEL: test_fptosi_ppc_i64_ppc_fp128: ; PC64-LABEL: test_fptosi_ppc_i64_ppc_fp128:
; PC64: # %bb.0: # %entry ; PC64: # %bb.0: # %entry
; PC64-NEXT: mflr 0 ; PC64-NEXT: mflr 0
; PC64-NEXT: std 0, 16(1)
; PC64-NEXT: stdu 1, -112(1) ; PC64-NEXT: stdu 1, -112(1)
; PC64-NEXT: std 0, 128(1)
; PC64-NEXT: bl __fixtfdi ; PC64-NEXT: bl __fixtfdi
; PC64-NEXT: nop ; PC64-NEXT: nop
; PC64-NEXT: addi 1, 1, 112 ; PC64-NEXT: addi 1, 1, 112
; PC64-NEXT: ld 0, 16(1) ; PC64-NEXT: ld 0, 16(1)
; PC64-NEXT: mtlr 0 ; PC64-NEXT: mtlr 0
; PC64-NEXT: blr ; PC64-NEXT: blr
entry: entry:
%fpext = call i64 @llvm.experimental.constrained.fptosi.i64.ppcf128( %fpext = call i64 @llvm.experimental.constrained.fptosi.i64.ppcf128(
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines %fpext = call i32 @llvm.experimental.constrained.fptosi.i32.ppcf128(
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret i32 %fpext ret i32 %fpext
} }
define i64 @test_fptoui_ppc_i64_ppc_fp128(ppc_fp128 %first) #0 { define i64 @test_fptoui_ppc_i64_ppc_fp128(ppc_fp128 %first) #0 {
; PC64LE-LABEL: test_fptoui_ppc_i64_ppc_fp128: ; PC64LE-LABEL: test_fptoui_ppc_i64_ppc_fp128:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -32(1) ; PC64LE-NEXT: stdu 1, -32(1)
; PC64LE-NEXT: std 0, 48(1)
; PC64LE-NEXT: bl __fixunstfdi ; PC64LE-NEXT: bl __fixunstfdi
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: addi 1, 1, 32 ; PC64LE-NEXT: addi 1, 1, 32
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: test_fptoui_ppc_i64_ppc_fp128: ; PC64LE9-LABEL: test_fptoui_ppc_i64_ppc_fp128:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -32(1) ; PC64LE9-NEXT: stdu 1, -32(1)
; PC64LE9-NEXT: std 0, 48(1)
; PC64LE9-NEXT: bl __fixunstfdi ; PC64LE9-NEXT: bl __fixunstfdi
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addi 1, 1, 32 ; PC64LE9-NEXT: addi 1, 1, 32
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
; ;
; PC64-LABEL: test_fptoui_ppc_i64_ppc_fp128: ; PC64-LABEL: test_fptoui_ppc_i64_ppc_fp128:
; PC64: # %bb.0: # %entry ; PC64: # %bb.0: # %entry
; PC64-NEXT: mflr 0 ; PC64-NEXT: mflr 0
; PC64-NEXT: std 0, 16(1)
; PC64-NEXT: stdu 1, -112(1) ; PC64-NEXT: stdu 1, -112(1)
; PC64-NEXT: std 0, 128(1)
; PC64-NEXT: bl __fixunstfdi ; PC64-NEXT: bl __fixunstfdi
; PC64-NEXT: nop ; PC64-NEXT: nop
; PC64-NEXT: addi 1, 1, 112 ; PC64-NEXT: addi 1, 1, 112
; PC64-NEXT: ld 0, 16(1) ; PC64-NEXT: ld 0, 16(1)
; PC64-NEXT: mtlr 0 ; PC64-NEXT: mtlr 0
; PC64-NEXT: blr ; PC64-NEXT: blr
entry: entry:
%fpext = call i64 @llvm.experimental.constrained.fptoui.i64.ppcf128( %fpext = call i64 @llvm.experimental.constrained.fptoui.i64.ppcf128(
ppc_fp128 %first, ppc_fp128 %first,
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret i64 %fpext ret i64 %fpext
} }
define i32 @test_fptoui_ppc_i32_ppc_fp128(ppc_fp128 %first) #0 { define i32 @test_fptoui_ppc_i32_ppc_fp128(ppc_fp128 %first) #0 {
; PC64LE-LABEL: test_fptoui_ppc_i32_ppc_fp128: ; PC64LE-LABEL: test_fptoui_ppc_i32_ppc_fp128:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 30, -16(1) # 8-byte Folded Spill ; PC64LE-NEXT: std 30, -16(1) # 8-byte Folded Spill
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -48(1) ; PC64LE-NEXT: stdu 1, -48(1)
; PC64LE-NEXT: addis 3, 2, .LCPI31_0@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI31_0@toc@ha
; PC64LE-NEXT: xxlxor 3, 3, 3 ; PC64LE-NEXT: xxlxor 3, 3, 3
; PC64LE-NEXT: std 0, 64(1)
; PC64LE-NEXT: lfs 0, .LCPI31_0@toc@l(3) ; PC64LE-NEXT: lfs 0, .LCPI31_0@toc@l(3)
; PC64LE-NEXT: lis 3, -32768 ; PC64LE-NEXT: lis 3, -32768
; PC64LE-NEXT: fcmpo 0, 2, 3 ; PC64LE-NEXT: fcmpo 0, 2, 3
; PC64LE-NEXT: xxlxor 3, 3, 3 ; PC64LE-NEXT: xxlxor 3, 3, 3
; PC64LE-NEXT: fcmpo 1, 1, 0 ; PC64LE-NEXT: fcmpo 1, 1, 0
; PC64LE-NEXT: crand 20, 6, 0 ; PC64LE-NEXT: crand 20, 6, 0
; PC64LE-NEXT: crandc 21, 4, 6 ; PC64LE-NEXT: crandc 21, 4, 6
; PC64LE-NEXT: cror 20, 21, 20 ; PC64LE-NEXT: cror 20, 21, 20
Show All 18 Lines
; PC64LE-NEXT: ld 30, -16(1) # 8-byte Folded Reload ; PC64LE-NEXT: ld 30, -16(1) # 8-byte Folded Reload
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: test_fptoui_ppc_i32_ppc_fp128: ; PC64LE9-LABEL: test_fptoui_ppc_i32_ppc_fp128:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 30, -16(1) # 8-byte Folded Spill ; PC64LE9-NEXT: std 30, -16(1) # 8-byte Folded Spill
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -48(1) ; PC64LE9-NEXT: stdu 1, -48(1)
; PC64LE9-NEXT: addis 3, 2, .LCPI31_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI31_0@toc@ha
; PC64LE9-NEXT: xxlxor 3, 3, 3 ; PC64LE9-NEXT: xxlxor 3, 3, 3
; PC64LE9-NEXT: std 0, 64(1)
; PC64LE9-NEXT: lfs 0, .LCPI31_0@toc@l(3) ; PC64LE9-NEXT: lfs 0, .LCPI31_0@toc@l(3)
; PC64LE9-NEXT: fcmpo 1, 2, 3 ; PC64LE9-NEXT: fcmpo 1, 2, 3
; PC64LE9-NEXT: lis 3, -32768 ; PC64LE9-NEXT: lis 3, -32768
; PC64LE9-NEXT: fcmpo 0, 1, 0
; PC64LE9-NEXT: xxlxor 3, 3, 3 ; PC64LE9-NEXT: xxlxor 3, 3, 3
; PC64LE9-NEXT: fcmpo 0, 1, 0
; PC64LE9-NEXT: crand 20, 2, 4 ; PC64LE9-NEXT: crand 20, 2, 4
; PC64LE9-NEXT: crandc 21, 0, 2 ; PC64LE9-NEXT: crandc 21, 0, 2
; PC64LE9-NEXT: cror 20, 21, 20 ; PC64LE9-NEXT: cror 20, 21, 20
; PC64LE9-NEXT: isel 30, 0, 3, 20 ; PC64LE9-NEXT: isel 30, 0, 3, 20
; PC64LE9-NEXT: bc 12, 20, .LBB31_2 ; PC64LE9-NEXT: bc 12, 20, .LBB31_2
; PC64LE9-NEXT: # %bb.1: # %entry ; PC64LE9-NEXT: # %bb.1: # %entry
; PC64LE9-NEXT: fmr 3, 0 ; PC64LE9-NEXT: fmr 3, 0
; PC64LE9-NEXT: .LBB31_2: # %entry ; PC64LE9-NEXT: .LBB31_2: # %entry
Show All 11 Lines
; PC64LE9-NEXT: addi 1, 1, 48 ; PC64LE9-NEXT: addi 1, 1, 48
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: ld 30, -16(1) # 8-byte Folded Reload ; PC64LE9-NEXT: ld 30, -16(1) # 8-byte Folded Reload
; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
; ;
; PC64-LABEL: test_fptoui_ppc_i32_ppc_fp128: ; PC64-LABEL: test_fptoui_ppc_i32_ppc_fp128:
; PC64: # %bb.0: # %entry ; PC64: # %bb.0: # %entry
; PC64-NEXT: mflr 0
; PC64-NEXT: std 0, 16(1)
; PC64-NEXT: mfcr 12 ; PC64-NEXT: mfcr 12
; PC64-NEXT: mflr 0
; PC64-NEXT: stw 12, 8(1) ; PC64-NEXT: stw 12, 8(1)
; PC64-NEXT: stdu 1, -128(1) ; PC64-NEXT: stdu 1, -128(1)
; PC64-NEXT: addis 3, 2, .LCPI31_0@toc@ha ; PC64-NEXT: addis 3, 2, .LCPI31_0@toc@ha
; PC64-NEXT: std 0, 144(1)
; PC64-NEXT: lfs 0, .LCPI31_0@toc@l(3) ; PC64-NEXT: lfs 0, .LCPI31_0@toc@l(3)
; PC64-NEXT: addis 3, 2, .LCPI31_1@toc@ha ; PC64-NEXT: addis 3, 2, .LCPI31_1@toc@ha
; PC64-NEXT: lfs 4, .LCPI31_1@toc@l(3) ; PC64-NEXT: lfs 4, .LCPI31_1@toc@l(3)
; PC64-NEXT: fcmpo 0, 1, 0 ; PC64-NEXT: fcmpo 0, 1, 0
; PC64-NEXT: crandc 21, 0, 2 ; PC64-NEXT: crandc 21, 0, 2
; PC64-NEXT: fcmpo 1, 2, 4 ; PC64-NEXT: fcmpo 1, 2, 4
; PC64-NEXT: crand 20, 2, 4 ; PC64-NEXT: crand 20, 2, 4
; PC64-NEXT: cror 8, 21, 20 ; PC64-NEXT: cror 8, 21, 20
Show All 38 Lines
; PC64LE-LABEL: test_constrained_libcall_multichain: ; PC64LE-LABEL: test_constrained_libcall_multichain:
; PC64LE: # %bb.0: ; PC64LE: # %bb.0:
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 29, -48(1) # 8-byte Folded Spill ; PC64LE-NEXT: std 29, -48(1) # 8-byte Folded Spill
; PC64LE-NEXT: std 30, -40(1) # 8-byte Folded Spill ; PC64LE-NEXT: std 30, -40(1) # 8-byte Folded Spill
; PC64LE-NEXT: stfd 29, -24(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 29, -24(1) # 8-byte Folded Spill
; PC64LE-NEXT: stfd 30, -16(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 30, -16(1) # 8-byte Folded Spill
; PC64LE-NEXT: stfd 31, -8(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 31, -8(1) # 8-byte Folded Spill
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -80(1) ; PC64LE-NEXT: stdu 1, -80(1)
; PC64LE-NEXT: std 0, 96(1)
; PC64LE-NEXT: mr 29, 3 ; PC64LE-NEXT: mr 29, 3
; PC64LE-NEXT: xxlxor 2, 2, 2 ; PC64LE-NEXT: xxlxor 2, 2, 2
; PC64LE-NEXT: li 3, 0 ; PC64LE-NEXT: li 3, 0
; PC64LE-NEXT: mr 30, 4 ; PC64LE-NEXT: mr 30, 4
; PC64LE-NEXT: lfs 31, 0(29) ; PC64LE-NEXT: lfs 31, 0(29)
; PC64LE-NEXT: xxlxor 4, 4, 4 ; PC64LE-NEXT: xxlxor 4, 4, 4
; PC64LE-NEXT: std 3, 8(4) ; PC64LE-NEXT: std 3, 8(4)
; PC64LE-NEXT: fmr 1, 31 ; PC64LE-NEXT: fmr 1, 31
Show All 33 Lines
; PC64LE9-LABEL: test_constrained_libcall_multichain: ; PC64LE9-LABEL: test_constrained_libcall_multichain:
; PC64LE9: # %bb.0: ; PC64LE9: # %bb.0:
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 29, -48(1) # 8-byte Folded Spill ; PC64LE9-NEXT: std 29, -48(1) # 8-byte Folded Spill
; PC64LE9-NEXT: std 30, -40(1) # 8-byte Folded Spill ; PC64LE9-NEXT: std 30, -40(1) # 8-byte Folded Spill
; PC64LE9-NEXT: stfd 29, -24(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 29, -24(1) # 8-byte Folded Spill
; PC64LE9-NEXT: stfd 30, -16(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 30, -16(1) # 8-byte Folded Spill
; PC64LE9-NEXT: stfd 31, -8(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 31, -8(1) # 8-byte Folded Spill
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -80(1) ; PC64LE9-NEXT: stdu 1, -80(1)
; PC64LE9-NEXT: lfs 31, 0(3) ; PC64LE9-NEXT: std 0, 96(1)
; PC64LE9-NEXT: mr 29, 3 ; PC64LE9-NEXT: mr 29, 3
; PC64LE9-NEXT: li 3, 0
; PC64LE9-NEXT: xxlxor 2, 2, 2 ; PC64LE9-NEXT: xxlxor 2, 2, 2
; PC64LE9-NEXT: xxlxor 4, 4, 4
; PC64LE9-NEXT: mr 30, 4 ; PC64LE9-NEXT: mr 30, 4
; PC64LE9-NEXT: lfs 31, 0(3)
; PC64LE9-NEXT: li 3, 0
; PC64LE9-NEXT: xxlxor 4, 4, 4
; PC64LE9-NEXT: std 3, 8(4) ; PC64LE9-NEXT: std 3, 8(4)
; PC64LE9-NEXT: fmr 1, 31 ; PC64LE9-NEXT: fmr 1, 31
; PC64LE9-NEXT: fmr 3, 31 ; PC64LE9-NEXT: fmr 3, 31
; PC64LE9-NEXT: stfd 31, 0(4) ; PC64LE9-NEXT: stfd 31, 0(4)
; PC64LE9-NEXT: bl __gcc_qadd ; PC64LE9-NEXT: bl __gcc_qadd
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: fmr 3, 1 ; PC64LE9-NEXT: fmr 3, 1
; PC64LE9-NEXT: fmr 4, 2 ; PC64LE9-NEXT: fmr 4, 2
Show All 22 Lines
; PC64LE9-NEXT: ld 29, -48(1) # 8-byte Folded Reload ; PC64LE9-NEXT: ld 29, -48(1) # 8-byte Folded Reload
; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: lfd 29, -24(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 29, -24(1) # 8-byte Folded Reload
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
; ;
; PC64-LABEL: test_constrained_libcall_multichain: ; PC64-LABEL: test_constrained_libcall_multichain:
; PC64: # %bb.0: ; PC64: # %bb.0:
; PC64-NEXT: mflr 0 ; PC64-NEXT: mflr 0
; PC64-NEXT: std 0, 16(1)
; PC64-NEXT: stdu 1, -176(1) ; PC64-NEXT: stdu 1, -176(1)
; PC64-NEXT: std 0, 192(1)
; PC64-NEXT: std 29, 120(1) # 8-byte Folded Spill ; PC64-NEXT: std 29, 120(1) # 8-byte Folded Spill
; PC64-NEXT: mr 29, 3 ; PC64-NEXT: mr 29, 3
; PC64-NEXT: li 3, 0 ; PC64-NEXT: li 3, 0
; PC64-NEXT: stfd 31, 168(1) # 8-byte Folded Spill ; PC64-NEXT: stfd 31, 168(1) # 8-byte Folded Spill
; PC64-NEXT: std 30, 128(1) # 8-byte Folded Spill ; PC64-NEXT: std 30, 128(1) # 8-byte Folded Spill
; PC64-NEXT: mr 30, 4 ; PC64-NEXT: mr 30, 4
; PC64-NEXT: lfs 31, 0(29) ; PC64-NEXT: lfs 31, 0(29)
; PC64-NEXT: std 3, 8(4) ; PC64-NEXT: std 3, 8(4)
▲ Show 20 Lines • Show All 106 Lines • ▼ Show 20 Linesentry:
%conv = tail call ppc_fp128 @llvm.experimental.constrained.sitofp.ppcf128.i32(i32 %m, metadata !"round.dynamic", metadata !"fpexcept.strict") #1 %conv = tail call ppc_fp128 @llvm.experimental.constrained.sitofp.ppcf128.i32(i32 %m, metadata !"round.dynamic", metadata !"fpexcept.strict") #1
ret ppc_fp128 %conv ret ppc_fp128 %conv
} }
define ppc_fp128 @i64_to_ppcq(i64 %m) #0 { define ppc_fp128 @i64_to_ppcq(i64 %m) #0 {
; PC64LE-LABEL: i64_to_ppcq: ; PC64LE-LABEL: i64_to_ppcq:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -32(1) ; PC64LE-NEXT: stdu 1, -32(1)
; PC64LE-NEXT: std 0, 48(1)
; PC64LE-NEXT: bl __floatditf ; PC64LE-NEXT: bl __floatditf
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: addi 1, 1, 32 ; PC64LE-NEXT: addi 1, 1, 32
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: i64_to_ppcq: ; PC64LE9-LABEL: i64_to_ppcq:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -32(1) ; PC64LE9-NEXT: stdu 1, -32(1)
; PC64LE9-NEXT: std 0, 48(1)
; PC64LE9-NEXT: bl __floatditf ; PC64LE9-NEXT: bl __floatditf
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addi 1, 1, 32 ; PC64LE9-NEXT: addi 1, 1, 32
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
; ;
; PC64-LABEL: i64_to_ppcq: ; PC64-LABEL: i64_to_ppcq:
; PC64: # %bb.0: # %entry ; PC64: # %bb.0: # %entry
; PC64-NEXT: mflr 0 ; PC64-NEXT: mflr 0
; PC64-NEXT: std 0, 16(1)
; PC64-NEXT: stdu 1, -112(1) ; PC64-NEXT: stdu 1, -112(1)
; PC64-NEXT: std 0, 128(1)
; PC64-NEXT: bl __floatditf ; PC64-NEXT: bl __floatditf
; PC64-NEXT: nop ; PC64-NEXT: nop
; PC64-NEXT: addi 1, 1, 112 ; PC64-NEXT: addi 1, 1, 112
; PC64-NEXT: ld 0, 16(1) ; PC64-NEXT: ld 0, 16(1)
; PC64-NEXT: mtlr 0 ; PC64-NEXT: mtlr 0
; PC64-NEXT: blr ; PC64-NEXT: blr
entry: entry:
%conv = tail call ppc_fp128 @llvm.experimental.constrained.sitofp.ppcf128.i64(i64 %m, metadata !"round.dynamic", metadata !"fpexcept.strict") #1 %conv = tail call ppc_fp128 @llvm.experimental.constrained.sitofp.ppcf128.i64(i64 %m, metadata !"round.dynamic", metadata !"fpexcept.strict") #1
Show All 34 Lines
define ppc_fp128 @u64_to_ppcq(i64 %m) #0 { define ppc_fp128 @u64_to_ppcq(i64 %m) #0 {
; PC64LE-LABEL: u64_to_ppcq: ; PC64LE-LABEL: u64_to_ppcq:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 30, -32(1) # 8-byte Folded Spill ; PC64LE-NEXT: std 30, -32(1) # 8-byte Folded Spill
; PC64LE-NEXT: stfd 30, -16(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 30, -16(1) # 8-byte Folded Spill
; PC64LE-NEXT: stfd 31, -8(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 31, -8(1) # 8-byte Folded Spill
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -64(1) ; PC64LE-NEXT: stdu 1, -64(1)
; PC64LE-NEXT: std 0, 80(1)
; PC64LE-NEXT: mr 30, 3 ; PC64LE-NEXT: mr 30, 3
; PC64LE-NEXT: bl __floatditf ; PC64LE-NEXT: bl __floatditf
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: addis 3, 2, .LCPI36_0@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI36_0@toc@ha
; PC64LE-NEXT: xxlxor 4, 4, 4 ; PC64LE-NEXT: xxlxor 4, 4, 4
; PC64LE-NEXT: fmr 30, 1 ; PC64LE-NEXT: fmr 30, 1
; PC64LE-NEXT: lfs 3, .LCPI36_0@toc@l(3) ; PC64LE-NEXT: lfs 3, .LCPI36_0@toc@l(3)
; PC64LE-NEXT: fmr 31, 2 ; PC64LE-NEXT: fmr 31, 2
Show All 17 Lines
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: u64_to_ppcq: ; PC64LE9-LABEL: u64_to_ppcq:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 30, -32(1) # 8-byte Folded Spill ; PC64LE9-NEXT: std 30, -32(1) # 8-byte Folded Spill
; PC64LE9-NEXT: stfd 30, -16(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 30, -16(1) # 8-byte Folded Spill
; PC64LE9-NEXT: stfd 31, -8(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 31, -8(1) # 8-byte Folded Spill
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -64(1) ; PC64LE9-NEXT: stdu 1, -64(1)
; PC64LE9-NEXT: std 0, 80(1)
; PC64LE9-NEXT: mr 30, 3 ; PC64LE9-NEXT: mr 30, 3
; PC64LE9-NEXT: bl __floatditf ; PC64LE9-NEXT: bl __floatditf
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addis 3, 2, .LCPI36_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI36_0@toc@ha
; PC64LE9-NEXT: xxlxor 4, 4, 4 ; PC64LE9-NEXT: xxlxor 4, 4, 4
; PC64LE9-NEXT: fmr 30, 1 ; PC64LE9-NEXT: fmr 30, 1
; PC64LE9-NEXT: fmr 31, 2 ; PC64LE9-NEXT: fmr 31, 2
; PC64LE9-NEXT: lfs 3, .LCPI36_0@toc@l(3) ; PC64LE9-NEXT: lfs 3, .LCPI36_0@toc@l(3)
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; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload
; PC64LE9-NEXT: ld 30, -32(1) # 8-byte Folded Reload ; PC64LE9-NEXT: ld 30, -32(1) # 8-byte Folded Reload
; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
; ;
; PC64-LABEL: u64_to_ppcq: ; PC64-LABEL: u64_to_ppcq:
; PC64: # %bb.0: # %entry ; PC64: # %bb.0: # %entry
; PC64-NEXT: mflr 0 ; PC64-NEXT: mflr 0
; PC64-NEXT: std 0, 16(1)
; PC64-NEXT: stdu 1, -144(1) ; PC64-NEXT: stdu 1, -144(1)
; PC64-NEXT: std 0, 160(1)
; PC64-NEXT: std 30, 112(1) # 8-byte Folded Spill ; PC64-NEXT: std 30, 112(1) # 8-byte Folded Spill
; PC64-NEXT: stfd 30, 128(1) # 8-byte Folded Spill ; PC64-NEXT: stfd 30, 128(1) # 8-byte Folded Spill
; PC64-NEXT: mr 30, 3 ; PC64-NEXT: mr 30, 3
; PC64-NEXT: stfd 31, 136(1) # 8-byte Folded Spill ; PC64-NEXT: stfd 31, 136(1) # 8-byte Folded Spill
; PC64-NEXT: bl __floatditf ; PC64-NEXT: bl __floatditf
; PC64-NEXT: nop ; PC64-NEXT: nop
; PC64-NEXT: addis 3, 2, .LCPI36_0@toc@ha ; PC64-NEXT: addis 3, 2, .LCPI36_0@toc@ha
; PC64-NEXT: fmr 31, 2 ; PC64-NEXT: fmr 31, 2
Show All 23 Linesentry:
%conv = tail call ppc_fp128 @llvm.experimental.constrained.uitofp.ppcf128.i64(i64 %m, metadata !"round.dynamic", metadata !"fpexcept.strict") #1 %conv = tail call ppc_fp128 @llvm.experimental.constrained.uitofp.ppcf128.i64(i64 %m, metadata !"round.dynamic", metadata !"fpexcept.strict") #1
ret ppc_fp128 %conv ret ppc_fp128 %conv
} }
define ppc_fp128 @i128_to_ppcq(i128 %m) #0 { define ppc_fp128 @i128_to_ppcq(i128 %m) #0 {
; PC64LE-LABEL: i128_to_ppcq: ; PC64LE-LABEL: i128_to_ppcq:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -32(1) ; PC64LE-NEXT: stdu 1, -32(1)
; PC64LE-NEXT: std 0, 48(1)
; PC64LE-NEXT: bl __floattitf ; PC64LE-NEXT: bl __floattitf
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: addi 1, 1, 32 ; PC64LE-NEXT: addi 1, 1, 32
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: i128_to_ppcq: ; PC64LE9-LABEL: i128_to_ppcq:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -32(1) ; PC64LE9-NEXT: stdu 1, -32(1)
; PC64LE9-NEXT: std 0, 48(1)
; PC64LE9-NEXT: bl __floattitf ; PC64LE9-NEXT: bl __floattitf
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addi 1, 1, 32 ; PC64LE9-NEXT: addi 1, 1, 32
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
; ;
; PC64-LABEL: i128_to_ppcq: ; PC64-LABEL: i128_to_ppcq:
; PC64: # %bb.0: # %entry ; PC64: # %bb.0: # %entry
; PC64-NEXT: mflr 0 ; PC64-NEXT: mflr 0
; PC64-NEXT: std 0, 16(1)
; PC64-NEXT: stdu 1, -112(1) ; PC64-NEXT: stdu 1, -112(1)
; PC64-NEXT: std 0, 128(1)
; PC64-NEXT: bl __floattitf ; PC64-NEXT: bl __floattitf
; PC64-NEXT: nop ; PC64-NEXT: nop
; PC64-NEXT: addi 1, 1, 112 ; PC64-NEXT: addi 1, 1, 112
; PC64-NEXT: ld 0, 16(1) ; PC64-NEXT: ld 0, 16(1)
; PC64-NEXT: mtlr 0 ; PC64-NEXT: mtlr 0
; PC64-NEXT: blr ; PC64-NEXT: blr
entry: entry:
%conv = tail call ppc_fp128 @llvm.experimental.constrained.sitofp.ppcf128.i128(i128 %m, metadata !"round.dynamic", metadata !"fpexcept.strict") #1 %conv = tail call ppc_fp128 @llvm.experimental.constrained.sitofp.ppcf128.i128(i128 %m, metadata !"round.dynamic", metadata !"fpexcept.strict") #1
ret ppc_fp128 %conv ret ppc_fp128 %conv
} }
define ppc_fp128 @u128_to_ppcq(i128 %m) #0 { define ppc_fp128 @u128_to_ppcq(i128 %m) #0 {
; PC64LE-LABEL: u128_to_ppcq: ; PC64LE-LABEL: u128_to_ppcq:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 30, -32(1) # 8-byte Folded Spill ; PC64LE-NEXT: std 30, -32(1) # 8-byte Folded Spill
; PC64LE-NEXT: stfd 30, -16(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 30, -16(1) # 8-byte Folded Spill
; PC64LE-NEXT: stfd 31, -8(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 31, -8(1) # 8-byte Folded Spill
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -64(1) ; PC64LE-NEXT: stdu 1, -64(1)
; PC64LE-NEXT: std 0, 80(1)
; PC64LE-NEXT: mr 30, 4 ; PC64LE-NEXT: mr 30, 4
; PC64LE-NEXT: bl __floattitf ; PC64LE-NEXT: bl __floattitf
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: addis 3, 2, .LCPI38_0@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI38_0@toc@ha
; PC64LE-NEXT: xxlxor 4, 4, 4 ; PC64LE-NEXT: xxlxor 4, 4, 4
; PC64LE-NEXT: fmr 30, 1 ; PC64LE-NEXT: fmr 30, 1
; PC64LE-NEXT: lfd 3, .LCPI38_0@toc@l(3) ; PC64LE-NEXT: lfd 3, .LCPI38_0@toc@l(3)
; PC64LE-NEXT: fmr 31, 2 ; PC64LE-NEXT: fmr 31, 2
Show All 17 Lines
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: u128_to_ppcq: ; PC64LE9-LABEL: u128_to_ppcq:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 30, -32(1) # 8-byte Folded Spill ; PC64LE9-NEXT: std 30, -32(1) # 8-byte Folded Spill
; PC64LE9-NEXT: stfd 30, -16(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 30, -16(1) # 8-byte Folded Spill
; PC64LE9-NEXT: stfd 31, -8(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 31, -8(1) # 8-byte Folded Spill
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -64(1) ; PC64LE9-NEXT: stdu 1, -64(1)
; PC64LE9-NEXT: std 0, 80(1)
; PC64LE9-NEXT: mr 30, 4 ; PC64LE9-NEXT: mr 30, 4
; PC64LE9-NEXT: bl __floattitf ; PC64LE9-NEXT: bl __floattitf
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addis 3, 2, .LCPI38_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI38_0@toc@ha
; PC64LE9-NEXT: xxlxor 4, 4, 4 ; PC64LE9-NEXT: xxlxor 4, 4, 4
; PC64LE9-NEXT: fmr 30, 1 ; PC64LE9-NEXT: fmr 30, 1
; PC64LE9-NEXT: lfd 3, .LCPI38_0@toc@l(3) ; PC64LE9-NEXT: lfd 3, .LCPI38_0@toc@l(3)
; PC64LE9-NEXT: fmr 31, 2 ; PC64LE9-NEXT: fmr 31, 2
Show All 14 Lines
; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload
; PC64LE9-NEXT: ld 30, -32(1) # 8-byte Folded Reload ; PC64LE9-NEXT: ld 30, -32(1) # 8-byte Folded Reload
; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
; ;
; PC64-LABEL: u128_to_ppcq: ; PC64-LABEL: u128_to_ppcq:
; PC64: # %bb.0: # %entry ; PC64: # %bb.0: # %entry
; PC64-NEXT: mflr 0 ; PC64-NEXT: mflr 0
; PC64-NEXT: std 0, 16(1)
; PC64-NEXT: stdu 1, -144(1) ; PC64-NEXT: stdu 1, -144(1)
; PC64-NEXT: std 0, 160(1)
; PC64-NEXT: std 30, 112(1) # 8-byte Folded Spill ; PC64-NEXT: std 30, 112(1) # 8-byte Folded Spill
; PC64-NEXT: stfd 30, 128(1) # 8-byte Folded Spill ; PC64-NEXT: stfd 30, 128(1) # 8-byte Folded Spill
; PC64-NEXT: mr 30, 3 ; PC64-NEXT: mr 30, 3
; PC64-NEXT: stfd 31, 136(1) # 8-byte Folded Spill ; PC64-NEXT: stfd 31, 136(1) # 8-byte Folded Spill
; PC64-NEXT: bl __floattitf ; PC64-NEXT: bl __floattitf
; PC64-NEXT: nop ; PC64-NEXT: nop
; PC64-NEXT: addis 3, 2, .LCPI38_0@toc@ha ; PC64-NEXT: addis 3, 2, .LCPI38_0@toc@ha
; PC64-NEXT: fmr 31, 2 ; PC64-NEXT: fmr 31, 2
Show All 23 Linesentry:
%conv = tail call ppc_fp128 @llvm.experimental.constrained.uitofp.ppcf128.i128(i128 %m, metadata !"round.dynamic", metadata !"fpexcept.strict") #1 %conv = tail call ppc_fp128 @llvm.experimental.constrained.uitofp.ppcf128.i128(i128 %m, metadata !"round.dynamic", metadata !"fpexcept.strict") #1
ret ppc_fp128 %conv ret ppc_fp128 %conv
} }
define i1 @ppcq_to_s1(ppc_fp128 %a) { define i1 @ppcq_to_s1(ppc_fp128 %a) {
; PC64LE-LABEL: ppcq_to_s1: ; PC64LE-LABEL: ppcq_to_s1:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -32(1) ; PC64LE-NEXT: stdu 1, -32(1)
; PC64LE-NEXT: std 0, 48(1)
; PC64LE-NEXT: .cfi_def_cfa_offset 32 ; PC64LE-NEXT: .cfi_def_cfa_offset 32
; PC64LE-NEXT: .cfi_offset lr, 16 ; PC64LE-NEXT: .cfi_offset lr, 16
; PC64LE-NEXT: bl __gcc_qtou ; PC64LE-NEXT: bl __gcc_qtou
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: addi 1, 1, 32 ; PC64LE-NEXT: addi 1, 1, 32
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: ppcq_to_s1: ; PC64LE9-LABEL: ppcq_to_s1:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -32(1) ; PC64LE9-NEXT: stdu 1, -32(1)
; PC64LE9-NEXT: std 0, 48(1)
; PC64LE9-NEXT: .cfi_def_cfa_offset 32 ; PC64LE9-NEXT: .cfi_def_cfa_offset 32
; PC64LE9-NEXT: .cfi_offset lr, 16 ; PC64LE9-NEXT: .cfi_offset lr, 16
; PC64LE9-NEXT: bl __gcc_qtou ; PC64LE9-NEXT: bl __gcc_qtou
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addi 1, 1, 32 ; PC64LE9-NEXT: addi 1, 1, 32
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
; ;
; PC64-LABEL: ppcq_to_s1: ; PC64-LABEL: ppcq_to_s1:
; PC64: # %bb.0: # %entry ; PC64: # %bb.0: # %entry
; PC64-NEXT: mflr 0 ; PC64-NEXT: mflr 0
; PC64-NEXT: std 0, 16(1)
; PC64-NEXT: stdu 1, -112(1) ; PC64-NEXT: stdu 1, -112(1)
; PC64-NEXT: std 0, 128(1)
; PC64-NEXT: .cfi_def_cfa_offset 112 ; PC64-NEXT: .cfi_def_cfa_offset 112
; PC64-NEXT: .cfi_offset lr, 16 ; PC64-NEXT: .cfi_offset lr, 16
; PC64-NEXT: bl __gcc_qtou ; PC64-NEXT: bl __gcc_qtou
; PC64-NEXT: nop ; PC64-NEXT: nop
; PC64-NEXT: addi 1, 1, 112 ; PC64-NEXT: addi 1, 1, 112
; PC64-NEXT: ld 0, 16(1) ; PC64-NEXT: ld 0, 16(1)
; PC64-NEXT: mtlr 0 ; PC64-NEXT: mtlr 0
; PC64-NEXT: blr ; PC64-NEXT: blr
entry: entry:
%conv = tail call i1 @llvm.experimental.constrained.fptosi.ppcf128.i1(ppc_fp128 %a, metadata !"fpexcept.strict") #1 %conv = tail call i1 @llvm.experimental.constrained.fptosi.ppcf128.i1(ppc_fp128 %a, metadata !"fpexcept.strict") #1
ret i1 %conv ret i1 %conv
} }
define i1 @ppcq_to_u1(ppc_fp128 %a) { define i1 @ppcq_to_u1(ppc_fp128 %a) {
; PC64LE-LABEL: ppcq_to_u1: ; PC64LE-LABEL: ppcq_to_u1:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -32(1) ; PC64LE-NEXT: stdu 1, -32(1)
; PC64LE-NEXT: std 0, 48(1)
; PC64LE-NEXT: .cfi_def_cfa_offset 32 ; PC64LE-NEXT: .cfi_def_cfa_offset 32
; PC64LE-NEXT: .cfi_offset lr, 16 ; PC64LE-NEXT: .cfi_offset lr, 16
; PC64LE-NEXT: bl __fixunstfsi ; PC64LE-NEXT: bl __fixunstfsi
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: addi 1, 1, 32 ; PC64LE-NEXT: addi 1, 1, 32
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: ppcq_to_u1: ; PC64LE9-LABEL: ppcq_to_u1:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -32(1) ; PC64LE9-NEXT: stdu 1, -32(1)
; PC64LE9-NEXT: std 0, 48(1)
; PC64LE9-NEXT: .cfi_def_cfa_offset 32 ; PC64LE9-NEXT: .cfi_def_cfa_offset 32
; PC64LE9-NEXT: .cfi_offset lr, 16 ; PC64LE9-NEXT: .cfi_offset lr, 16
; PC64LE9-NEXT: bl __fixunstfsi ; PC64LE9-NEXT: bl __fixunstfsi
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addi 1, 1, 32 ; PC64LE9-NEXT: addi 1, 1, 32
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
; ;
; PC64-LABEL: ppcq_to_u1: ; PC64-LABEL: ppcq_to_u1:
; PC64: # %bb.0: # %entry ; PC64: # %bb.0: # %entry
; PC64-NEXT: mflr 0 ; PC64-NEXT: mflr 0
; PC64-NEXT: std 0, 16(1)
; PC64-NEXT: stdu 1, -112(1) ; PC64-NEXT: stdu 1, -112(1)
; PC64-NEXT: std 0, 128(1)
; PC64-NEXT: .cfi_def_cfa_offset 112 ; PC64-NEXT: .cfi_def_cfa_offset 112
; PC64-NEXT: .cfi_offset lr, 16 ; PC64-NEXT: .cfi_offset lr, 16
; PC64-NEXT: bl __fixunstfsi ; PC64-NEXT: bl __fixunstfsi
; PC64-NEXT: nop ; PC64-NEXT: nop
; PC64-NEXT: addi 1, 1, 112 ; PC64-NEXT: addi 1, 1, 112
; PC64-NEXT: ld 0, 16(1) ; PC64-NEXT: ld 0, 16(1)
; PC64-NEXT: mtlr 0 ; PC64-NEXT: mtlr 0
; PC64-NEXT: blr ; PC64-NEXT: blr
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llvm/test/CodeGen/PowerPC/ppcf128-endian.ll

Show All 22 Linesentry:
store ppc_fp128 %0, ptr @g, align 16 store ppc_fp128 %0, ptr @g, align 16
ret void ret void
} }
define void @caller() { define void @caller() {
; CHECK-LABEL: caller: ; CHECK-LABEL: caller:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; CHECK-NEXT: std 0, 16(1)
; CHECK-NEXT: stdu 1, -32(1) ; CHECK-NEXT: stdu 1, -32(1)
; CHECK-NEXT: std 0, 48(1)
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: addis 3, 2, .LC0@toc@ha ; CHECK-NEXT: addis 3, 2, .LC0@toc@ha
; CHECK-NEXT: ld 3, .LC0@toc@l(3) ; CHECK-NEXT: ld 3, .LC0@toc@l(3)
; CHECK-NEXT: lfd 2, 8(3) ; CHECK-NEXT: lfd 2, 8(3)
; CHECK-NEXT: lfd 1, 0(3) ; CHECK-NEXT: lfd 1, 0(3)
; CHECK-NEXT: bl test ; CHECK-NEXT: bl test
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: addi 1, 1, 32 ; CHECK-NEXT: addi 1, 1, 32
; CHECK-NEXT: ld 0, 16(1) ; CHECK-NEXT: ld 0, 16(1)
; CHECK-NEXT: mtlr 0 ; CHECK-NEXT: mtlr 0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%0 = load ppc_fp128, ptr @g, align 16 %0 = load ppc_fp128, ptr @g, align 16
call void @test(ppc_fp128 %0) call void @test(ppc_fp128 %0)
ret void ret void
} }
declare void @test(ppc_fp128) declare void @test(ppc_fp128)
define void @caller_const() { define void @caller_const() {
; CHECK-LABEL: caller_const: ; CHECK-LABEL: caller_const:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; CHECK-NEXT: std 0, 16(1)
; CHECK-NEXT: stdu 1, -32(1) ; CHECK-NEXT: stdu 1, -32(1)
; CHECK-NEXT: std 0, 48(1)
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: addis 3, 2, .LCPI2_0@toc@ha ; CHECK-NEXT: addis 3, 2, .LCPI2_0@toc@ha
; CHECK-NEXT: addis 4, 2, .LCPI2_1@toc@ha ; CHECK-NEXT: addis 4, 2, .LCPI2_1@toc@ha
; CHECK-NEXT: lfs 1, .LCPI2_0@toc@l(3) ; CHECK-NEXT: lfs 1, .LCPI2_0@toc@l(3)
; CHECK-NEXT: lfs 2, .LCPI2_1@toc@l(4) ; CHECK-NEXT: lfs 2, .LCPI2_1@toc@l(4)
; CHECK-NEXT: bl test ; CHECK-NEXT: bl test
; CHECK-NEXT: nop ; CHECK-NEXT: nop
Show All 18 Linesentry:
%0 = load ppc_fp128, ptr @g, align 16 %0 = load ppc_fp128, ptr @g, align 16
ret ppc_fp128 %0 ret ppc_fp128 %0
} }
define void @use_result() { define void @use_result() {
; CHECK-LABEL: use_result: ; CHECK-LABEL: use_result:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; CHECK-NEXT: std 0, 16(1)
; CHECK-NEXT: stdu 1, -32(1) ; CHECK-NEXT: stdu 1, -32(1)
; CHECK-NEXT: std 0, 48(1)
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: bl test_result ; CHECK-NEXT: bl test_result
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: addis 3, 2, .LC0@toc@ha ; CHECK-NEXT: addis 3, 2, .LC0@toc@ha
; CHECK-NEXT: ld 3, .LC0@toc@l(3) ; CHECK-NEXT: ld 3, .LC0@toc@l(3)
; CHECK-NEXT: stfd 2, 8(3) ; CHECK-NEXT: stfd 2, 8(3)
; CHECK-NEXT: stfd 1, 0(3) ; CHECK-NEXT: stfd 1, 0(3)
; CHECK-NEXT: addi 1, 1, 32 ; CHECK-NEXT: addi 1, 1, 32
; CHECK-NEXT: ld 0, 16(1) ; CHECK-NEXT: ld 0, 16(1)
; CHECK-NEXT: mtlr 0 ; CHECK-NEXT: mtlr 0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%call = tail call ppc_fp128 @test_result() #3 %call = tail call ppc_fp128 @test_result() #3
store ppc_fp128 %call, ptr @g, align 16 store ppc_fp128 %call, ptr @g, align 16
ret void ret void
} }
declare ppc_fp128 @test_result() declare ppc_fp128 @test_result()
define void @caller_result() { define void @caller_result() {
; CHECK-LABEL: caller_result: ; CHECK-LABEL: caller_result:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; CHECK-NEXT: std 0, 16(1)
; CHECK-NEXT: stdu 1, -32(1) ; CHECK-NEXT: stdu 1, -32(1)
; CHECK-NEXT: std 0, 48(1)
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: bl test_result ; CHECK-NEXT: bl test_result
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: bl test ; CHECK-NEXT: bl test
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: addi 1, 1, 32 ; CHECK-NEXT: addi 1, 1, 32
; CHECK-NEXT: ld 0, 16(1) ; CHECK-NEXT: ld 0, 16(1)
▲ Show 20 Lines • Show All 93 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/pr33547.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
; RUN: -mcpu=pwr8 -code-model=large < %s | FileCheck %s ; RUN: -mcpu=pwr8 -code-model=large < %s | FileCheck %s
%struct.STATICS1 = type <{ [128 x i8] }> %struct.STATICS1 = type <{ [128 x i8] }>
@.STATICS1 = internal global %struct.STATICS1 <{ [128 x i8] c"\09\00\00\00\03\00\00\00\05\00\00\00\04\00\00\00\0A\00\00\00\0A\00\00\00\0B\00\00\00\0A\08\AF/\B8\B6\87\04 \A1\07\00\08\9D\00\00\09\00\00\00\05\00\00\00\03\00\00\00\03\00\00\00\05\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00" }>, align 16 @.STATICS1 = internal global %struct.STATICS1 <{ [128 x i8] c"\09\00\00\00\03\00\00\00\05\00\00\00\04\00\00\00\0A\00\00\00\0A\00\00\00\0B\00\00\00\0A\08\AF/\B8\B6\87\04 \A1\07\00\08\9D\00\00\09\00\00\00\05\00\00\00\03\00\00\00\03\00\00\00\05\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00" }>, align 16
@.C302_MAIN_ = internal constant i32 4 @.C302_MAIN_ = internal constant i32 4
; Function Attrs: noinline norecurse nounwind ; Function Attrs: noinline norecurse nounwind
define void @main() { define void @main() {
; CHECK-LABEL: main: ; CHECK-LABEL: main:
; CHECK: # %bb.0: # %L.entry ; CHECK: # %bb.0: # %L.entry
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; CHECK-NEXT: std 0, 16(1)
; CHECK-NEXT: stdu 1, -32(1) ; CHECK-NEXT: stdu 1, -32(1)
; CHECK-NEXT: std 0, 48(1)
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: addis 3, 2, .LC0@toc@ha ; CHECK-NEXT: addis 3, 2, .LC0@toc@ha
; CHECK-NEXT: addis 4, 2, .LC1@toc@ha ; CHECK-NEXT: addis 4, 2, .LC1@toc@ha
; CHECK-NEXT: ld 3, .LC0@toc@l(3) ; CHECK-NEXT: ld 3, .LC0@toc@l(3)
; CHECK-NEXT: ld 4, .LC1@toc@l(4) ; CHECK-NEXT: ld 4, .LC1@toc@l(4)
; CHECK-NEXT: addi 3, 3, 124 ; CHECK-NEXT: addi 3, 3, 124
; CHECK-NEXT: bl testFunc ; CHECK-NEXT: bl testFunc
Show All 18 LinesL.entry:
ret i32 %0 ret i32 %0
} }
; Function Attrs: noinline norecurse nounwind ; Function Attrs: noinline norecurse nounwind
define void @testFunc(ptr nocapture %r, ptr nocapture readonly %k) { define void @testFunc(ptr nocapture %r, ptr nocapture readonly %k) {
; CHECK-LABEL: testFunc: ; CHECK-LABEL: testFunc:
; CHECK: # %bb.0: # %L.entry ; CHECK: # %bb.0: # %L.entry
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; CHECK-NEXT: std 0, 16(1)
; CHECK-NEXT: stdu 1, -32(1) ; CHECK-NEXT: stdu 1, -32(1)
; CHECK-NEXT: std 0, 48(1)
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: bl .L2$pb ; CHECK-NEXT: bl .L2$pb
; CHECK-NEXT: .L2$pb: ; CHECK-NEXT: .L2$pb:
; CHECK-NEXT: lwz 4, 0(4) ; CHECK-NEXT: lwz 4, 0(4)
; CHECK-NEXT: mflr 5 ; CHECK-NEXT: mflr 5
; CHECK-NEXT: addi 4, 4, -1 ; CHECK-NEXT: addi 4, 4, -1
; CHECK-NEXT: cmplwi 4, 5 ; CHECK-NEXT: cmplwi 4, 5
▲ Show 20 Lines • Show All 61 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/pr36292.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown < %s | \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown < %s | \
; RUN: FileCheck %s --implicit-check-not=mtctr --implicit-check-not=bdnz ; RUN: FileCheck %s --implicit-check-not=mtctr --implicit-check-not=bdnz
$test = comdat any $test = comdat any
; No CTR loop due to frem (since it is always a call). ; No CTR loop due to frem (since it is always a call).
define void @test() nounwind comdat { define void @test() nounwind comdat {
; CHECK-LABEL: test: ; CHECK-LABEL: test:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; CHECK-NEXT: std 29, -24(1) # 8-byte Folded Spill ; CHECK-NEXT: std 29, -24(1) # 8-byte Folded Spill
; CHECK-NEXT: std 30, -16(1) # 8-byte Folded Spill ; CHECK-NEXT: std 30, -16(1) # 8-byte Folded Spill
; CHECK-NEXT: std 0, 16(1)
; CHECK-NEXT: stdu 1, -64(1) ; CHECK-NEXT: stdu 1, -64(1)
; CHECK-NEXT: std 0, 80(1)
; CHECK-NEXT: ld 29, 0(3) ; CHECK-NEXT: ld 29, 0(3)
; CHECK-NEXT: ld 30, 32(1) ; CHECK-NEXT: ld 30, 32(1)
; CHECK-NEXT: cmpld 30, 29 ; CHECK-NEXT: cmpld 30, 29
; CHECK-NEXT: bge- 0, .LBB0_2 ; CHECK-NEXT: bge- 0, .LBB0_2
; CHECK-NEXT: .p2align 5 ; CHECK-NEXT: .p2align 5
; CHECK-NEXT: .LBB0_1: # %bounds.ok ; CHECK-NEXT: .LBB0_1: # %bounds.ok
; CHECK-NEXT: # ; CHECK-NEXT: #
; CHECK-NEXT: lfs 2, 0(3) ; CHECK-NEXT: lfs 2, 0(3)
Show All 31 Lines

llvm/test/CodeGen/PowerPC/pr41088.ll

Show All 27 Lines
%22 = type { [0 x i8] } %22 = type { [0 x i8] }
@var = external dso_local unnamed_addr constant <{ ptr, [8 x i8], ptr, [16 x i8] }>, align 8 @var = external dso_local unnamed_addr constant <{ ptr, [8 x i8], ptr, [16 x i8] }>, align 8
declare dso_local fastcc { ptr, ptr } @test2(ptr) unnamed_addr declare dso_local fastcc { ptr, ptr } @test2(ptr) unnamed_addr
define void @test(ptr %arg, ptr %arg1, ptr %arg2) unnamed_addr personality ptr @personality { define void @test(ptr %arg, ptr %arg1, ptr %arg2) unnamed_addr personality ptr @personality {
; CHECK-LABEL: test: ; CHECK-LABEL: test:
; CHECK: .cfi_personality 148, DW.ref.personality ; CHECK: # %bb.0: # %bb
; CHECK-NEXT: .cfi_lsda 20, .Lexception0
; CHECK-NEXT: .Lfunc_gep0:
; CHECK-NEXT: addis r2, r12, .TOC.-.Lfunc_gep0@ha
; CHECK-NEXT: addi r2, r2, .TOC.-.Lfunc_gep0@l
; CHECK-NEXT: .Lfunc_lep0:
; CHECK-NEXT: .localentry test, .Lfunc_lep0-.Lfunc_gep0
; CHECK-NEXT: # %bb.0: # %bb
; CHECK-NEXT: mflr r0 ; CHECK-NEXT: mflr r0
; CHECK-NEXT: std r0, 16(r1)
; CHECK-NEXT: stdu r1, -32(r1) ; CHECK-NEXT: stdu r1, -32(r1)
; CHECK-NEXT: std r0, 48(r1)
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: li r4, 0 ; CHECK-NEXT: li r4, 0
; CHECK-NEXT: # %bb.1: # %bb9 ; CHECK-NEXT: # %bb.1: # %bb9
; CHECK-NEXT: bl test5 ; CHECK-NEXT: bl test5
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: rlwinm r4, r3, 8, 16, 23 ; CHECK-NEXT: rlwinm r4, r3, 8, 16, 23
; CHECK-NEXT: # %bb.2: # %bb12 ; CHECK-NEXT: # %bb.2: # %bb12
▲ Show 20 Lines • Show All 87 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/pr43527.ll

Show All 10 Lines
; CHECK-NEXT: # %bb.2: # %bb4 ; CHECK-NEXT: # %bb.2: # %bb4
; CHECK-NEXT: mflr r0 ; CHECK-NEXT: mflr r0
; CHECK-NEXT: .cfi_def_cfa_offset 64 ; CHECK-NEXT: .cfi_def_cfa_offset 64
; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: .cfi_offset r29, -24 ; CHECK-NEXT: .cfi_offset r29, -24
; CHECK-NEXT: .cfi_offset r30, -16 ; CHECK-NEXT: .cfi_offset r30, -16
; CHECK-NEXT: std r29, -24(r1) # 8-byte Folded Spill ; CHECK-NEXT: std r29, -24(r1) # 8-byte Folded Spill
; CHECK-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-NEXT: std r0, 16(r1)
; CHECK-NEXT: stdu r1, -64(r1) ; CHECK-NEXT: stdu r1, -64(r1)
; CHECK-NEXT: sub r30, r4, r3 ; CHECK-NEXT: sub r30, r4, r3
; CHECK-NEXT: li r29, -4 ; CHECK-NEXT: li r29, -4
; CHECK-NEXT: std r0, 80(r1)
; CHECK-NEXT: .p2align 5 ; CHECK-NEXT: .p2align 5
; CHECK-NEXT: .LBB0_3: # %bb5 ; CHECK-NEXT: .LBB0_3: # %bb5
; CHECK-NEXT: # ; CHECK-NEXT: #
; CHECK-NEXT: lfsu f1, 4(r29) ; CHECK-NEXT: lfsu f1, 4(r29)
; CHECK-NEXT: bl lrint ; CHECK-NEXT: bl lrint
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: addi r30, r30, -1 ; CHECK-NEXT: addi r30, r30, -1
; CHECK-NEXT: cmpldi r30, 0 ; CHECK-NEXT: cmpldi r30, 0
▲ Show 20 Lines • Show All 44 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/pr43976.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=powerpc64-unknown-unknown -verify-machineinstrs \ ; RUN: llc -mtriple=powerpc64-unknown-unknown -verify-machineinstrs \
; RUN: -ppc-asm-full-reg-names < %s | FileCheck %s ; RUN: -ppc-asm-full-reg-names < %s | FileCheck %s
@a = dso_local local_unnamed_addr global double 0.000000e+00, align 8 @a = dso_local local_unnamed_addr global double 0.000000e+00, align 8
define dso_local signext i32 @b() local_unnamed_addr #0 { define dso_local signext i32 @b() local_unnamed_addr #0 {
; CHECK-LABEL: b: ; CHECK-LABEL: b:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr r0 ; CHECK-NEXT: mflr r0
; CHECK-NEXT: std r0, 16(r1)
; CHECK-NEXT: stdu r1, -144(r1) ; CHECK-NEXT: stdu r1, -144(r1)
; CHECK-NEXT: std r0, 160(r1)
; CHECK-NEXT: addis r3, r2, a@toc@ha ; CHECK-NEXT: addis r3, r2, a@toc@ha
; CHECK-NEXT: li r4, 1 ; CHECK-NEXT: li r4, 1
; CHECK-NEXT: lfd f0, a@toc@l(r3) ; CHECK-NEXT: lfd f0, a@toc@l(r3)
; CHECK-NEXT: addis r3, r2, .LCPI0_0@toc@ha ; CHECK-NEXT: addis r3, r2, .LCPI0_0@toc@ha
; CHECK-NEXT: rldic r4, r4, 63, 0 ; CHECK-NEXT: rldic r4, r4, 63, 0
; CHECK-NEXT: lfs f1, .LCPI0_0@toc@l(r3) ; CHECK-NEXT: lfs f1, .LCPI0_0@toc@l(r3)
; CHECK-NEXT: fsub f2, f0, f1 ; CHECK-NEXT: fsub f2, f0, f1
; CHECK-NEXT: fctidz f2, f2 ; CHECK-NEXT: fctidz f2, f2
Show All 40 Lines

llvm/test/CodeGen/PowerPC/pr44183.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s
%struct.m.2.5.8.11 = type { %struct.l.0.3.6.9, [7 x i8], %struct.a.1.4.7.10 } %struct.m.2.5.8.11 = type { %struct.l.0.3.6.9, [7 x i8], %struct.a.1.4.7.10 }
%struct.l.0.3.6.9 = type { i8 } %struct.l.0.3.6.9 = type { i8 }
%struct.a.1.4.7.10 = type { [27 x i8], [0 x i32], [4 x i8] } %struct.a.1.4.7.10 = type { [27 x i8], [0 x i32], [4 x i8] }
define void @_ZN1m1nEv(ptr %this) local_unnamed_addr nounwind align 2 { define void @_ZN1m1nEv(ptr %this) local_unnamed_addr nounwind align 2 {
; CHECK-LABEL: _ZN1m1nEv: ; CHECK-LABEL: _ZN1m1nEv:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr r0 ; CHECK-NEXT: mflr r0
; CHECK-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-NEXT: std r0, 16(r1)
; CHECK-NEXT: stdu r1, -48(r1) ; CHECK-NEXT: stdu r1, -48(r1)
; CHECK-NEXT: std r0, 64(r1)
; CHECK-NEXT: mr r30, r3 ; CHECK-NEXT: mr r30, r3
; CHECK-NEXT: ld r3, 8(r3) ; CHECK-NEXT: ld r3, 8(r3)
; CHECK-NEXT: lwz r4, 36(r30) ; CHECK-NEXT: lwz r4, 36(r30)
; CHECK-NEXT: rldicl r3, r3, 60, 4 ; CHECK-NEXT: rldicl r3, r3, 60, 4
; CHECK-NEXT: slwi r3, r3, 31
; CHECK-NEXT: clrlwi r4, r4, 31 ; CHECK-NEXT: clrlwi r4, r4, 31
; CHECK-NEXT: slwi r3, r3, 31
; CHECK-NEXT: rlwimi r4, r3, 0, 0, 0 ; CHECK-NEXT: rlwimi r4, r3, 0, 0, 0
; CHECK-NEXT: bl _ZN1llsE1d ; CHECK-NEXT: bl _ZN1llsE1d
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: ld r3, 16(r30) ; CHECK-NEXT: ld r3, 16(r30)
; CHECK-NEXT: ld r4, 8(r30) ; CHECK-NEXT: ld r4, 8(r30)
; CHECK-NEXT: rldicl r4, r4, 60, 4 ; CHECK-NEXT: rldicl r4, r4, 60, 4
; CHECK-NEXT: sldi r3, r3, 60 ; CHECK-NEXT: sldi r3, r3, 60
; CHECK-NEXT: or r3, r3, r4 ; CHECK-NEXT: or r3, r3, r4
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llvm/test/CodeGen/PowerPC/pr45301.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=powerpc64-- -verify-machineinstrs \ ; RUN: llc -mtriple=powerpc64-- -verify-machineinstrs \
; RUN: -ppc-asm-full-reg-names < %s | FileCheck %s ; RUN: -ppc-asm-full-reg-names < %s | FileCheck %s
%struct.e.0.1.2.3.12.29 = type { [10 x i32] } %struct.e.0.1.2.3.12.29 = type { [10 x i32] }
define dso_local void @g(ptr %agg.result) local_unnamed_addr #0 { define dso_local void @g(ptr %agg.result) local_unnamed_addr #0 {
; CHECK-LABEL: g: ; CHECK-LABEL: g:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr r0 ; CHECK-NEXT: mflr r0
; CHECK-NEXT: std r0, 16(r1)
; CHECK-NEXT: stdu r1, -112(r1) ; CHECK-NEXT: stdu r1, -112(r1)
; CHECK-NEXT: std r0, 128(r1)
; CHECK-NEXT: bl i ; CHECK-NEXT: bl i
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: addis r4, r2, g@toc@ha ; CHECK-NEXT: addis r4, r2, g@toc@ha
; CHECK-NEXT: addi r4, r4, g@toc@l ; CHECK-NEXT: addi r4, r4, g@toc@l
; CHECK-NEXT: ld r5, 16(r4) ; CHECK-NEXT: ld r5, 16(r4)
; CHECK-NEXT: std r5, 16(r3) ; CHECK-NEXT: std r5, 16(r3)
; CHECK-NEXT: ld r6, 0(r4) ; CHECK-NEXT: ld r6, 0(r4)
; CHECK-NEXT: std r6, 0(r3) ; CHECK-NEXT: std r6, 0(r3)
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llvm/test/CodeGen/PowerPC/pr45432.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr9 < %s | FileCheck %s ; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr9 < %s | FileCheck %s
%0 = type { double, [0 x %1] } %0 = type { double, [0 x %1] }
%1 = type { i32 } %1 = type { i32 }
@f = external dso_local thread_local local_unnamed_addr global %0, align 8 @f = external dso_local thread_local local_unnamed_addr global %0, align 8
@g = external dso_local local_unnamed_addr global i32, align 4 @g = external dso_local local_unnamed_addr global i32, align 4
; Function Attrs: nounwind ; Function Attrs: nounwind
define dso_local void @h() local_unnamed_addr #0 { define dso_local void @h() local_unnamed_addr #0 {
; CHECK-LABEL: h: ; CHECK-LABEL: h:
; CHECK: # %bb.0: # %bb ; CHECK: # %bb.0: # %bb
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; CHECK-NEXT: std 0, 16(1)
; CHECK-NEXT: stdu 1, -64(1) ; CHECK-NEXT: stdu 1, -64(1)
; CHECK-NEXT: addis 3, 2, g@toc@ha ; CHECK-NEXT: addis 3, 2, g@toc@ha
; CHECK-NEXT: std 0, 80(1)
; CHECK-NEXT: std 30, 48(1) # 8-byte Folded Spill ; CHECK-NEXT: std 30, 48(1) # 8-byte Folded Spill
; CHECK-NEXT: lwz 3, g@toc@l(3) ; CHECK-NEXT: lwz 3, g@toc@l(3)
; CHECK-NEXT: extswsli 30, 3, 2 ; CHECK-NEXT: extswsli 30, 3, 2
; CHECK-NEXT: addis 3, 2, f@got@tlsld@ha ; CHECK-NEXT: addis 3, 2, f@got@tlsld@ha
; CHECK-NEXT: addi 3, 3, f@got@tlsld@l ; CHECK-NEXT: addi 3, 3, f@got@tlsld@l
; CHECK-NEXT: bl __tls_get_addr(f@tlsld) ; CHECK-NEXT: bl __tls_get_addr(f@tlsld)
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: addis 3, 3, f@dtprel@ha ; CHECK-NEXT: addis 3, 3, f@dtprel@ha
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llvm/test/CodeGen/PowerPC/pr47373.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=powerpc64-unknown-freebsd13.0 -verify-machineinstrs \ ; RUN: llc -mtriple=powerpc64-unknown-freebsd13.0 -verify-machineinstrs \
; RUN: -mcpu=ppc64 -ppc-asm-full-reg-names < %s | FileCheck %s ; RUN: -mcpu=ppc64 -ppc-asm-full-reg-names < %s | FileCheck %s
@a = local_unnamed_addr global float* null, align 8 @a = local_unnamed_addr global float* null, align 8
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @d() local_unnamed_addr #0 { define void @d() local_unnamed_addr #0 {
; CHECK-LABEL: d: ; CHECK-LABEL: d:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr r0 ; CHECK-NEXT: mflr r0
; CHECK-NEXT: std r0, 16(r1)
; CHECK-NEXT: stdu r1, -208(r1) ; CHECK-NEXT: stdu r1, -208(r1)
; CHECK-NEXT: addis r3, r2, .LC0@toc@ha ; CHECK-NEXT: addis r3, r2, .LC0@toc@ha
; CHECK-NEXT: std r29, 184(r1) # 8-byte Folded Spill ; CHECK-NEXT: std r0, 224(r1)
; CHECK-NEXT: ld r3, .LC0@toc@l(r3) ; CHECK-NEXT: ld r3, .LC0@toc@l(r3)
; CHECK-NEXT: std r29, 184(r1) # 8-byte Folded Spill
; CHECK-NEXT: std r30, 192(r1) # 8-byte Folded Spill ; CHECK-NEXT: std r30, 192(r1) # 8-byte Folded Spill
; CHECK-NEXT: ld r29, 0(r3) ; CHECK-NEXT: ld r29, 0(r3)
; CHECK-NEXT: bl c ; CHECK-NEXT: bl c
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: mr r30, r3 ; CHECK-NEXT: mr r30, r3
; CHECK-NEXT: bl b ; CHECK-NEXT: bl b
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: cmpwi r30, 0 ; CHECK-NEXT: cmpwi r30, 0
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llvm/test/CodeGen/PowerPC/pr48519.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ ; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s ; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s
; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ ; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s \ ; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s \
; RUN: -check-prefix=CHECK-P9 ; RUN: -check-prefix=CHECK-P9
define void @julia__typed_vcat_20() #0 { define void @julia__typed_vcat_20() #0 {
; CHECK-LABEL: julia__typed_vcat_20: ; CHECK-LABEL: julia__typed_vcat_20:
; CHECK: # %bb.0: # %bb ; CHECK: # %bb.0: # %bb
; CHECK-NEXT: mflr r0 ; CHECK-NEXT: mflr r0
; CHECK-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-NEXT: std r0, 16(r1)
; CHECK-NEXT: stdu r1, -48(r1) ; CHECK-NEXT: stdu r1, -48(r1)
; CHECK-NEXT: li r3, 1 ; CHECK-NEXT: li r3, 1
; CHECK-NEXT: li r30, 0 ; CHECK-NEXT: li r30, 0
; CHECK-NEXT: std r0, 64(r1)
; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: .p2align 4
; CHECK-NEXT: .LBB0_1: # %bb3 ; CHECK-NEXT: .LBB0_1: # %bb3
; CHECK-NEXT: # ; CHECK-NEXT: #
; CHECK-NEXT: addi r3, r3, -1 ; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: mtfprd f0, r3 ; CHECK-NEXT: mtfprd f0, r3
; CHECK-NEXT: xscvsxdsp f1, f0 ; CHECK-NEXT: xscvsxdsp f1, f0
; CHECK-NEXT: bl __gnu_f2h_ieee ; CHECK-NEXT: bl __gnu_f2h_ieee
; CHECK-NEXT: nop ; CHECK-NEXT: nop
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declare { i64, i1 } @llvm.ssub.with.overflow.i64(i64, i64) #0 declare { i64, i1 } @llvm.ssub.with.overflow.i64(i64, i64) #0
define void @julia__hypot_17() #0 { define void @julia__hypot_17() #0 {
; CHECK-LABEL: julia__hypot_17: ; CHECK-LABEL: julia__hypot_17:
; CHECK: # %bb.0: # %bb ; CHECK: # %bb.0: # %bb
; CHECK-NEXT: mflr r0 ; CHECK-NEXT: mflr r0
; CHECK-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-NEXT: std r0, 16(r1)
; CHECK-NEXT: stdu r1, -48(r1) ; CHECK-NEXT: stdu r1, -48(r1)
; CHECK-NEXT: li r30, 3 ; CHECK-NEXT: li r30, 3
; CHECK-NEXT: std r0, 64(r1)
; CHECK-NEXT: .p2align 5 ; CHECK-NEXT: .p2align 5
; CHECK-NEXT: .LBB1_1: # %bb1 ; CHECK-NEXT: .LBB1_1: # %bb1
; CHECK-NEXT: # ; CHECK-NEXT: #
; CHECK-NEXT: addi r30, r30, -1 ; CHECK-NEXT: addi r30, r30, -1
; CHECK-NEXT: cmpldi r30, 0 ; CHECK-NEXT: cmpldi r30, 0
; CHECK-NEXT: beq cr0, .LBB1_3 ; CHECK-NEXT: beq cr0, .LBB1_3
; CHECK-NEXT: # %bb.2: # %bb3 ; CHECK-NEXT: # %bb.2: # %bb3
; CHECK-NEXT: # ; CHECK-NEXT: #
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Linesbb9: ; preds = %bb3, %bb1
ret void ret void
} }
define void @func_48786() #0 { define void @func_48786() #0 {
; CHECK-LABEL: func_48786: ; CHECK-LABEL: func_48786:
; CHECK: # %bb.0: # %bb ; CHECK: # %bb.0: # %bb
; CHECK-NEXT: mfocrf r12, 32 ; CHECK-NEXT: mfocrf r12, 32
; CHECK-NEXT: mflr r0 ; CHECK-NEXT: mflr r0
; CHECK-NEXT: std r0, 16(r1)
; CHECK-NEXT: stw r12, 8(r1) ; CHECK-NEXT: stw r12, 8(r1)
; CHECK-NEXT: stdu r1, -48(r1) ; CHECK-NEXT: stdu r1, -48(r1)
; CHECK-NEXT: ld r3, 0(r3) ; CHECK-NEXT: std r0, 64(r1)
; CHECK-NEXT: std r30, 32(r1) # 8-byte Folded Spill ; CHECK-NEXT: std r30, 32(r1) # 8-byte Folded Spill
; CHECK-NEXT: # implicit-def: $x30 ; CHECK-NEXT: # implicit-def: $x30
; CHECK-NEXT: ld r3, 0(r3)
; CHECK-NEXT: cmpdi r3, 0 ; CHECK-NEXT: cmpdi r3, 0
; CHECK-NEXT: crnot 4*cr2+lt, eq ; CHECK-NEXT: crnot 4*cr2+lt, eq
; CHECK-NEXT: bc 12, 4*cr5+lt, .LBB2_3 ; CHECK-NEXT: bc 12, 4*cr5+lt, .LBB2_3
; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: .p2align 4
; CHECK-NEXT: .LBB2_1: # %bb4 ; CHECK-NEXT: .LBB2_1: # %bb4
; CHECK-NEXT: lhz r3, 0(r3) ; CHECK-NEXT: lhz r3, 0(r3)
; CHECK-NEXT: bl __gnu_h2f_ieee ; CHECK-NEXT: bl __gnu_h2f_ieee
; CHECK-NEXT: nop ; CHECK-NEXT: nop
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define void @func_48785(half %arg) #0 { define void @func_48785(half %arg) #0 {
; CHECK-LABEL: func_48785: ; CHECK-LABEL: func_48785:
; CHECK: # %bb.0: # %bb ; CHECK: # %bb.0: # %bb
; CHECK-NEXT: mflr r0 ; CHECK-NEXT: mflr r0
; CHECK-NEXT: std r29, -32(r1) # 8-byte Folded Spill ; CHECK-NEXT: std r29, -32(r1) # 8-byte Folded Spill
; CHECK-NEXT: std r30, -24(r1) # 8-byte Folded Spill ; CHECK-NEXT: std r30, -24(r1) # 8-byte Folded Spill
; CHECK-NEXT: stfd f31, -8(r1) # 8-byte Folded Spill ; CHECK-NEXT: stfd f31, -8(r1) # 8-byte Folded Spill
; CHECK-NEXT: std r0, 16(r1)
; CHECK-NEXT: stdu r1, -64(r1) ; CHECK-NEXT: stdu r1, -64(r1)
; CHECK-NEXT: fmr f31, f1 ; CHECK-NEXT: fmr f31, f1
; CHECK-NEXT: li r30, 0 ; CHECK-NEXT: li r30, 0
; CHECK-NEXT: li r29, 0 ; CHECK-NEXT: li r29, 0
; CHECK-NEXT: std r0, 80(r1)
; CHECK-NEXT: .p2align 5 ; CHECK-NEXT: .p2align 5
; CHECK-NEXT: .LBB3_1: # %bb1 ; CHECK-NEXT: .LBB3_1: # %bb1
; CHECK-NEXT: # ; CHECK-NEXT: #
; CHECK-NEXT: fmr f1, f31 ; CHECK-NEXT: fmr f1, f31
; CHECK-NEXT: bl __gnu_f2h_ieee ; CHECK-NEXT: bl __gnu_f2h_ieee
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: addi r29, r29, -12 ; CHECK-NEXT: addi r29, r29, -12
; CHECK-NEXT: sth r3, 0(r30) ; CHECK-NEXT: sth r3, 0(r30)
Show All 34 Lines

llvm/test/CodeGen/PowerPC/pr48527.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -relocation-model=pic -verify-machineinstrs < %s \ ; RUN: llc -relocation-model=pic -verify-machineinstrs < %s \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 | FileCheck %s ; RUN: -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 | FileCheck %s
%struct.e.0.12.28.44.104.108.112.188 = type { i32 } %struct.e.0.12.28.44.104.108.112.188 = type { i32 }
%struct.t.1.13.29.45.105.109.113.189 = type { i64, i64 } %struct.t.1.13.29.45.105.109.113.189 = type { i64, i64 }
@g = external local_unnamed_addr global %struct.e.0.12.28.44.104.108.112.188, align 4 @g = external local_unnamed_addr global %struct.e.0.12.28.44.104.108.112.188, align 4
@aj = external thread_local local_unnamed_addr global %struct.t.1.13.29.45.105.109.113.189, align 8 @aj = external thread_local local_unnamed_addr global %struct.t.1.13.29.45.105.109.113.189, align 8
define void @_ZNK1q1rEv() local_unnamed_addr #0 align 2 { define void @_ZNK1q1rEv() local_unnamed_addr #0 align 2 {
; CHECK-LABEL: _ZNK1q1rEv: ; CHECK-LABEL: _ZNK1q1rEv:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; CHECK-NEXT: std 29, -24(1) # 8-byte Folded Spill ; CHECK-NEXT: std 29, -24(1) # 8-byte Folded Spill
; CHECK-NEXT: std 30, -16(1) # 8-byte Folded Spill ; CHECK-NEXT: std 30, -16(1) # 8-byte Folded Spill
; CHECK-NEXT: std 0, 16(1)
; CHECK-NEXT: stdu 1, -64(1) ; CHECK-NEXT: stdu 1, -64(1)
; CHECK-NEXT: std 0, 80(1)
; CHECK-NEXT: lwz 30, 0(3) ; CHECK-NEXT: lwz 30, 0(3)
; CHECK-NEXT: addis 3, 2, .LC0@toc@ha ; CHECK-NEXT: addis 3, 2, .LC0@toc@ha
; CHECK-NEXT: ld 29, .LC0@toc@l(3) ; CHECK-NEXT: ld 29, .LC0@toc@l(3)
; CHECK-NEXT: addis 3, 2, aj@got@tlsgd@ha ; CHECK-NEXT: addis 3, 2, aj@got@tlsgd@ha
; CHECK-NEXT: addi 3, 3, aj@got@tlsgd@l ; CHECK-NEXT: addi 3, 3, aj@got@tlsgd@l
; CHECK-NEXT: bl __tls_get_addr(aj@tlsgd) ; CHECK-NEXT: bl __tls_get_addr(aj@tlsgd)
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: addi 4, 3, 8 ; CHECK-NEXT: addi 4, 3, 8
▲ Show 20 Lines • Show All 45 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/pr49092.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ ; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s ; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s
; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ ; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s \ ; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s \
; RUN: -check-prefix=CHECK-P9 ; RUN: -check-prefix=CHECK-P9
define dso_local half @test2(i64 %a, i64 %b) local_unnamed_addr #0 { define dso_local half @test2(i64 %a, i64 %b) local_unnamed_addr #0 {
; CHECK-LABEL: test2: ; CHECK-LABEL: test2:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr r0 ; CHECK-NEXT: mflr r0
; CHECK-NEXT: std r0, 16(r1)
; CHECK-NEXT: stdu r1, -32(r1) ; CHECK-NEXT: stdu r1, -32(r1)
; CHECK-NEXT: add r3, r4, r3 ; CHECK-NEXT: add r3, r4, r3
; CHECK-NEXT: std r0, 48(r1)
; CHECK-NEXT: addi r3, r3, 11 ; CHECK-NEXT: addi r3, r3, 11
; CHECK-NEXT: clrlwi r3, r3, 16 ; CHECK-NEXT: clrlwi r3, r3, 16
; CHECK-NEXT: bl __gnu_h2f_ieee ; CHECK-NEXT: bl __gnu_h2f_ieee
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: addi r1, r1, 32 ; CHECK-NEXT: addi r1, r1, 32
; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: ld r0, 16(r1)
; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: mtlr r0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
Show All 17 Lines

llvm/test/CodeGen/PowerPC/pr55463.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=powerpcspe -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=powerpcspe -verify-machineinstrs < %s | FileCheck %s
define void @baz() #0 { define void @baz() #0 {
; CHECK-LABEL: baz: ; CHECK-LABEL: baz:
; CHECK: # %bb.0: # %bb ; CHECK: # %bb.0: # %bb
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; CHECK-NEXT: stw 0, 4(1)
; CHECK-NEXT: stwu 1, -16(1) ; CHECK-NEXT: stwu 1, -16(1)
; CHECK-NEXT: # implicit-def: $r3 ; CHECK-NEXT: # implicit-def: $r3
; CHECK-NEXT: stw 0, 20(1)
; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: .p2align 4
; CHECK-NEXT: .LBB0_1: # %bb1 ; CHECK-NEXT: .LBB0_1: # %bb1
; CHECK-NEXT: # ; CHECK-NEXT: #
; CHECK-NEXT: addi 3, 3, 1 ; CHECK-NEXT: addi 3, 3, 1
; CHECK-NEXT: cmplwi 3, 0 ; CHECK-NEXT: cmplwi 3, 0
; CHECK-NEXT: bne 0, .LBB0_1 ; CHECK-NEXT: bne 0, .LBB0_1
; CHECK-NEXT: # %bb.2: # %bb8 ; CHECK-NEXT: # %bb.2: # %bb8
; CHECK-NEXT: bl wibble ; CHECK-NEXT: bl wibble
Show All 18 Linesbb8:
call void @wibble(i32 %tmp6) call void @wibble(i32 %tmp6)
ret void ret void
} }
define void @wombat() #0 { define void @wombat() #0 {
; CHECK-LABEL: wombat: ; CHECK-LABEL: wombat:
; CHECK: # %bb.0: # %bb ; CHECK: # %bb.0: # %bb
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; CHECK-NEXT: stw 0, 4(1)
; CHECK-NEXT: stwu 1, -48(1) ; CHECK-NEXT: stwu 1, -48(1)
; CHECK-NEXT: li 3, .LCPI1_0@l ; CHECK-NEXT: li 3, .LCPI1_0@l
; CHECK-NEXT: li 5, .LCPI1_1@l ; CHECK-NEXT: li 5, .LCPI1_1@l
; CHECK-NEXT: lis 4, .LCPI1_0@ha ; CHECK-NEXT: lis 4, .LCPI1_0@ha
; CHECK-NEXT: lis 6, .LCPI1_1@ha ; CHECK-NEXT: lis 6, .LCPI1_1@ha
; CHECK-NEXT: stw 0, 52(1)
; CHECK-NEXT: evstdd 29, 24(1) # 8-byte Folded Spill ; CHECK-NEXT: evstdd 29, 24(1) # 8-byte Folded Spill
; CHECK-NEXT: evstdd 30, 32(1) # 8-byte Folded Spill ; CHECK-NEXT: evstdd 30, 32(1) # 8-byte Folded Spill
; CHECK-NEXT: evlddx 30, 4, 3 ; CHECK-NEXT: evlddx 30, 4, 3
; CHECK-NEXT: # implicit-def: $r3 ; CHECK-NEXT: # implicit-def: $r3
; CHECK-NEXT: evlddx 29, 6, 5 ; CHECK-NEXT: evlddx 29, 6, 5
; CHECK-NEXT: evstdd 28, 16(1) # 8-byte Folded Spill ; CHECK-NEXT: evstdd 28, 16(1) # 8-byte Folded Spill
; CHECK-NEXT: # implicit-def: $r28 ; CHECK-NEXT: # implicit-def: $r28
; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: .p2align 4
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llvm/test/CodeGen/PowerPC/pr56469.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-openbsd < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-openbsd < %s | FileCheck %s
@.str = private constant [32 x i8] c"i = %g, j = %g, k = %g, l = %g\0A\00", align 1 @.str = private constant [32 x i8] c"i = %g, j = %g, k = %g, l = %g\0A\00", align 1
define void @callee(float %a, float %b, float %c, float %d, float %e, float %f, float %g, float %h, float %i, float %j, float %k, float %l) nounwind { define void @callee(float %a, float %b, float %c, float %d, float %e, float %f, float %g, float %h, float %i, float %j, float %k, float %l) nounwind {
; CHECK-LABEL: callee: ; CHECK-LABEL: callee:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; CHECK-NEXT: stw 0, 4(1)
; CHECK-NEXT: stwu 1, -16(1) ; CHECK-NEXT: stwu 1, -16(1)
; CHECK-NEXT: lfs 1, 24(1) ; CHECK-NEXT: lfs 1, 24(1)
; CHECK-NEXT: lis 3, .L.str@ha ; CHECK-NEXT: lis 3, .L.str@ha
; CHECK-NEXT: lfs 2, 28(1) ; CHECK-NEXT: lfs 2, 28(1)
; CHECK-NEXT: la 3, .L.str@l(3) ; CHECK-NEXT: la 3, .L.str@l(3)
; CHECK-NEXT: lfs 3, 32(1) ; CHECK-NEXT: lfs 3, 32(1)
; CHECK-NEXT: creqv 6, 6, 6 ; CHECK-NEXT: creqv 6, 6, 6
; CHECK-NEXT: lfs 4, 36(1) ; CHECK-NEXT: lfs 4, 36(1)
; CHECK-NEXT: stw 0, 20(1)
; CHECK-NEXT: bl printf ; CHECK-NEXT: bl printf
; CHECK-NEXT: lwz 0, 20(1) ; CHECK-NEXT: lwz 0, 20(1)
; CHECK-NEXT: addi 1, 1, 16 ; CHECK-NEXT: addi 1, 1, 16
; CHECK-NEXT: mtlr 0 ; CHECK-NEXT: mtlr 0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%conv = fpext float %i to double %conv = fpext float %i to double
%conv1 = fpext float %j to double %conv1 = fpext float %j to double
%conv2 = fpext float %k to double %conv2 = fpext float %k to double
%conv3 = fpext float %l to double %conv3 = fpext float %l to double
%call = tail call signext i32 (ptr, ...) @printf(ptr nonnull dereferenceable(1) @.str, double %conv, double %conv1, double %conv2, double %conv3) %call = tail call signext i32 (ptr, ...) @printf(ptr nonnull dereferenceable(1) @.str, double %conv, double %conv1, double %conv2, double %conv3)
ret void ret void
} }
declare signext i32 @printf(ptr nocapture readonly, ...) declare signext i32 @printf(ptr nocapture readonly, ...)

llvm/test/CodeGen/PowerPC/read-set-flm.ll

Show First 20 Lines • Show All 78 Lines • ▼ Show 20 Lines
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; CHECK-NEXT: .cfi_def_cfa_offset 64 ; CHECK-NEXT: .cfi_def_cfa_offset 64
; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: .cfi_offset r30, -24 ; CHECK-NEXT: .cfi_offset r30, -24
; CHECK-NEXT: .cfi_offset f31, -8 ; CHECK-NEXT: .cfi_offset f31, -8
; CHECK-NEXT: std 30, -24(1) # 8-byte Folded Spill ; CHECK-NEXT: std 30, -24(1) # 8-byte Folded Spill
; CHECK-NEXT: stfd 31, -8(1) # 8-byte Folded Spill ; CHECK-NEXT: stfd 31, -8(1) # 8-byte Folded Spill
; CHECK-NEXT: std 0, 16(1)
; CHECK-NEXT: stdu 1, -64(1) ; CHECK-NEXT: stdu 1, -64(1)
; CHECK-NEXT: std 0, 80(1)
; CHECK-NEXT: fmr 31, 1 ; CHECK-NEXT: fmr 31, 1
; CHECK-NEXT: mr 30, 4 ; CHECK-NEXT: mr 30, 4
; CHECK-NEXT: mffs 0 ; CHECK-NEXT: mffs 0
; CHECK-NEXT: stfd 0, 0(3) ; CHECK-NEXT: stfd 0, 0(3)
; CHECK-NEXT: bl effect_func ; CHECK-NEXT: bl effect_func
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: mffs 0 ; CHECK-NEXT: mffs 0
; CHECK-NEXT: stfd 0, 0(30) ; CHECK-NEXT: stfd 0, 0(30)
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; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; CHECK-NEXT: .cfi_def_cfa_offset 64 ; CHECK-NEXT: .cfi_def_cfa_offset 64
; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: .cfi_offset r30, -24 ; CHECK-NEXT: .cfi_offset r30, -24
; CHECK-NEXT: .cfi_offset f31, -8 ; CHECK-NEXT: .cfi_offset f31, -8
; CHECK-NEXT: std 30, -24(1) # 8-byte Folded Spill ; CHECK-NEXT: std 30, -24(1) # 8-byte Folded Spill
; CHECK-NEXT: stfd 31, -8(1) # 8-byte Folded Spill ; CHECK-NEXT: stfd 31, -8(1) # 8-byte Folded Spill
; CHECK-NEXT: std 0, 16(1)
; CHECK-NEXT: stdu 1, -64(1) ; CHECK-NEXT: stdu 1, -64(1)
; CHECK-NEXT: std 0, 80(1)
; CHECK-NEXT: fmr 31, 1 ; CHECK-NEXT: fmr 31, 1
; CHECK-NEXT: mr 30, 4 ; CHECK-NEXT: mr 30, 4
; CHECK-NEXT: mffs 0 ; CHECK-NEXT: mffs 0
; CHECK-NEXT: stfd 0, 0(3) ; CHECK-NEXT: stfd 0, 0(3)
; CHECK-NEXT: bl readonly_func ; CHECK-NEXT: bl readonly_func
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: mffs 0 ; CHECK-NEXT: mffs 0
; CHECK-NEXT: stfd 0, 0(30) ; CHECK-NEXT: stfd 0, 0(30)
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llvm/test/CodeGen/PowerPC/recipest.ll

Show First 20 Lines • Show All 1,233 Lines • ▼ Show 20 Lines; CHECK-P9-NEXT: blr
%r = call <2 x double> @llvm.sqrt.v2f64(<2 x double> %a) %r = call <2 x double> @llvm.sqrt.v2f64(<2 x double> %a)
ret <2 x double> %r ret <2 x double> %r
} }
define fp128 @hoo5_fmf(fp128 %a) #1 { define fp128 @hoo5_fmf(fp128 %a) #1 {
; CHECK-P7-LABEL: hoo5_fmf: ; CHECK-P7-LABEL: hoo5_fmf:
; CHECK-P7: # %bb.0: ; CHECK-P7: # %bb.0:
; CHECK-P7-NEXT: mflr 0 ; CHECK-P7-NEXT: mflr 0
; CHECK-P7-NEXT: std 0, 16(1)
; CHECK-P7-NEXT: stdu 1, -112(1) ; CHECK-P7-NEXT: stdu 1, -112(1)
; CHECK-P7-NEXT: std 0, 128(1)
; CHECK-P7-NEXT: bl sqrtf128 ; CHECK-P7-NEXT: bl sqrtf128
; CHECK-P7-NEXT: nop ; CHECK-P7-NEXT: nop
; CHECK-P7-NEXT: addi 1, 1, 112 ; CHECK-P7-NEXT: addi 1, 1, 112
; CHECK-P7-NEXT: ld 0, 16(1) ; CHECK-P7-NEXT: ld 0, 16(1)
; CHECK-P7-NEXT: mtlr 0 ; CHECK-P7-NEXT: mtlr 0
; CHECK-P7-NEXT: blr ; CHECK-P7-NEXT: blr
; ;
; CHECK-P8-LABEL: hoo5_fmf: ; CHECK-P8-LABEL: hoo5_fmf:
; CHECK-P8: # %bb.0: ; CHECK-P8: # %bb.0:
; CHECK-P8-NEXT: mflr 0 ; CHECK-P8-NEXT: mflr 0
; CHECK-P8-NEXT: std 0, 16(1)
; CHECK-P8-NEXT: stdu 1, -32(1) ; CHECK-P8-NEXT: stdu 1, -32(1)
; CHECK-P8-NEXT: std 0, 48(1)
; CHECK-P8-NEXT: bl sqrtf128 ; CHECK-P8-NEXT: bl sqrtf128
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addi 1, 1, 32 ; CHECK-P8-NEXT: addi 1, 1, 32
; CHECK-P8-NEXT: ld 0, 16(1) ; CHECK-P8-NEXT: ld 0, 16(1)
; CHECK-P8-NEXT: mtlr 0 ; CHECK-P8-NEXT: mtlr 0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: hoo5_fmf: ; CHECK-P9-LABEL: hoo5_fmf:
; CHECK-P9: # %bb.0: ; CHECK-P9: # %bb.0:
; CHECK-P9-NEXT: xssqrtqp 2, 2 ; CHECK-P9-NEXT: xssqrtqp 2, 2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
%r = call contract reassoc ninf afn fp128 @llvm.sqrt.f128(fp128 %a) %r = call contract reassoc ninf afn fp128 @llvm.sqrt.f128(fp128 %a)
ret fp128 %r ret fp128 %r
} }
define fp128 @hoo5_safe(fp128 %a) #1 { define fp128 @hoo5_safe(fp128 %a) #1 {
; CHECK-P7-LABEL: hoo5_safe: ; CHECK-P7-LABEL: hoo5_safe:
; CHECK-P7: # %bb.0: ; CHECK-P7: # %bb.0:
; CHECK-P7-NEXT: mflr 0 ; CHECK-P7-NEXT: mflr 0
; CHECK-P7-NEXT: std 0, 16(1)
; CHECK-P7-NEXT: stdu 1, -112(1) ; CHECK-P7-NEXT: stdu 1, -112(1)
; CHECK-P7-NEXT: std 0, 128(1)
; CHECK-P7-NEXT: bl sqrtf128 ; CHECK-P7-NEXT: bl sqrtf128
; CHECK-P7-NEXT: nop ; CHECK-P7-NEXT: nop
; CHECK-P7-NEXT: addi 1, 1, 112 ; CHECK-P7-NEXT: addi 1, 1, 112
; CHECK-P7-NEXT: ld 0, 16(1) ; CHECK-P7-NEXT: ld 0, 16(1)
; CHECK-P7-NEXT: mtlr 0 ; CHECK-P7-NEXT: mtlr 0
; CHECK-P7-NEXT: blr ; CHECK-P7-NEXT: blr
; ;
; CHECK-P8-LABEL: hoo5_safe: ; CHECK-P8-LABEL: hoo5_safe:
; CHECK-P8: # %bb.0: ; CHECK-P8: # %bb.0:
; CHECK-P8-NEXT: mflr 0 ; CHECK-P8-NEXT: mflr 0
; CHECK-P8-NEXT: std 0, 16(1)
; CHECK-P8-NEXT: stdu 1, -32(1) ; CHECK-P8-NEXT: stdu 1, -32(1)
; CHECK-P8-NEXT: std 0, 48(1)
; CHECK-P8-NEXT: bl sqrtf128 ; CHECK-P8-NEXT: bl sqrtf128
; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addi 1, 1, 32 ; CHECK-P8-NEXT: addi 1, 1, 32
; CHECK-P8-NEXT: ld 0, 16(1) ; CHECK-P8-NEXT: ld 0, 16(1)
; CHECK-P8-NEXT: mtlr 0 ; CHECK-P8-NEXT: mtlr 0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: hoo5_safe: ; CHECK-P9-LABEL: hoo5_safe:
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llvm/test/CodeGen/PowerPC/reg-scavenging.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown \ ; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown \
; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s ; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s
define dso_local signext i32 @caller(i32 signext %a, i32 signext %b) local_unnamed_addr { define dso_local signext i32 @caller(i32 signext %a, i32 signext %b) local_unnamed_addr {
; CHECK-LABEL: caller: ; CHECK-LABEL: caller:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr r0 ; CHECK-NEXT: mflr r0
; CHECK-NEXT: std r0, 16(r1)
; CHECK-NEXT: stdu r1, -240(r1) ; CHECK-NEXT: stdu r1, -240(r1)
; CHECK-NEXT: std r0, 256(r1)
; CHECK-NEXT: .cfi_def_cfa_offset 240 ; CHECK-NEXT: .cfi_def_cfa_offset 240
; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: .cfi_offset v20, -192 ; CHECK-NEXT: .cfi_offset v20, -192
; CHECK-NEXT: li r5, 48 ; CHECK-NEXT: li r5, 48
; CHECK-NEXT: stvx v20, r1, r5 # 16-byte Folded Spill ; CHECK-NEXT: stvx v20, r1, r5 # 16-byte Folded Spill
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: add r3, r3, r4 ; CHECK-NEXT: add r3, r3, r4
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
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llvm/test/CodeGen/PowerPC/remove-redundant-load-imm.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mcpu=pwr9 -O3 < %s | FileCheck %s -check-prefix=PPC64LE ; RUN: llc -mcpu=pwr9 -O3 < %s | FileCheck %s -check-prefix=PPC64LE
target datalayout = "e-m:e-i64:64-n32:64" target datalayout = "e-m:e-i64:64-n32:64"
target triple = "powerpc64le-unknown-linux-gnu" target triple = "powerpc64le-unknown-linux-gnu"
@global.6 = external global ptr @global.6 = external global ptr
declare void @barney.88(i1, ptr) declare void @barney.88(i1, ptr)
declare void @barney.94(ptr, i32) declare void @barney.94(ptr, i32)
define void @redundancy_on_ppc_only(i1 %arg7) nounwind { define void @redundancy_on_ppc_only(i1 %arg7) nounwind {
; PPC64LE-LABEL: redundancy_on_ppc_only: ; PPC64LE-LABEL: redundancy_on_ppc_only:
; PPC64LE: # %bb.0: # %bb ; PPC64LE: # %bb.0: # %bb
; PPC64LE-NEXT: mflr 0
; PPC64LE-NEXT: andi. 3, 3, 1 ; PPC64LE-NEXT: andi. 3, 3, 1
; PPC64LE-NEXT: std 0, 16(1) ; PPC64LE-NEXT: mflr 0
; PPC64LE-NEXT: stdu 1, -32(1) ; PPC64LE-NEXT: stdu 1, -32(1)
; PPC64LE-NEXT: li 3, 1 ; PPC64LE-NEXT: li 3, 1
; PPC64LE-NEXT: li 4, 0 ; PPC64LE-NEXT: li 4, 0
; PPC64LE-NEXT: std 0, 48(1)
; PPC64LE-NEXT: iselgt 3, 3, 4 ; PPC64LE-NEXT: iselgt 3, 3, 4
; PPC64LE-NEXT: bl barney.88 ; PPC64LE-NEXT: bl barney.88
; PPC64LE-NEXT: nop ; PPC64LE-NEXT: nop
; PPC64LE-NEXT: addi 1, 1, 32 ; PPC64LE-NEXT: addi 1, 1, 32
; PPC64LE-NEXT: ld 0, 16(1) ; PPC64LE-NEXT: ld 0, 16(1)
; PPC64LE-NEXT: mtlr 0 ; PPC64LE-NEXT: mtlr 0
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
bb: bb:
br label %bb10 br label %bb10
bb10: ; preds = %bb bb10: ; preds = %bb
call void @barney.88(i1 %arg7, ptr null) call void @barney.88(i1 %arg7, ptr null)
ret void ret void
} }
define void @redundancy_on_ppc_and_other_targets() nounwind { define void @redundancy_on_ppc_and_other_targets() nounwind {
; PPC64LE-LABEL: redundancy_on_ppc_and_other_targets: ; PPC64LE-LABEL: redundancy_on_ppc_and_other_targets:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: mflr 0 ; PPC64LE-NEXT: mflr 0
; PPC64LE-NEXT: std 0, 16(1)
; PPC64LE-NEXT: stdu 1, -32(1) ; PPC64LE-NEXT: stdu 1, -32(1)
; PPC64LE-NEXT: addis 3, 2, .LC0@toc@ha ; PPC64LE-NEXT: addis 3, 2, .LC0@toc@ha
; PPC64LE-NEXT: li 4, 0 ; PPC64LE-NEXT: li 4, 0
; PPC64LE-NEXT: std 0, 48(1)
; PPC64LE-NEXT: ld 3, .LC0@toc@l(3) ; PPC64LE-NEXT: ld 3, .LC0@toc@l(3)
; PPC64LE-NEXT: std 4, 0(3) ; PPC64LE-NEXT: std 4, 0(3)
; PPC64LE-NEXT: bl barney.94 ; PPC64LE-NEXT: bl barney.94
; PPC64LE-NEXT: nop ; PPC64LE-NEXT: nop
store ptr null, ptr @global.6 store ptr null, ptr @global.6
call void @barney.94(ptr undef, i32 0) call void @barney.94(ptr undef, i32 0)
unreachable unreachable
} }

llvm/test/CodeGen/PowerPC/retaddr.ll

; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu | FileCheck %s -check-prefix=PPC32 ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu | FileCheck %s -check-prefix=PPC32
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s -check-prefix=PPC64 ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s -check-prefix=PPC64
; PPC32: foo ; PPC32: foo
; PPC32: mflr 0 ; PPC32: mflr 0
; PPC32: stw 0, 4(1)
; PPC32: stwu 1, -[[STACK:[0-9]+]](1) ; PPC32: stwu 1, -[[STACK:[0-9]+]](1)
; PPC32: stw 0, 20(1)
; PPC32: lwz [[REG:[0-9]+]], [[RETADDR:[0-9]+]](1) ; PPC32: lwz [[REG:[0-9]+]], [[RETADDR:[0-9]+]](1)
; PPC32: stw [[REG]], 0(3) ; PPC32: stw [[REG]], 0(3)
; PPC32: lwz 0, [[RETADDR]](1) ; PPC32: lwz 0, [[RETADDR]](1)
; PPC32: addi 1, 1, [[STACK]] ; PPC32: addi 1, 1, [[STACK]]
; PPC32: mtlr 0 ; PPC32: mtlr 0
; PPC32: blr ; PPC32: blr
; PPC64: foo ; PPC64: foo
; PPC64: mflr 0 ; PPC64: mflr 0
; PPC64: std 0, [[RETADDR:[0-9]+]] ; PPC64: stdu 1, -[[#%d,STACK:]]
; PPC64: stdu 1, -[[STACK:[0-9]+]] ; PPC64: std 0, [[#%d,RETADDR:]]
; PPC64: ld [[REG:[0-9]+]] ; PPC64: ld [[REG:[0-9]+]]
; PPC64: std [[REG]], 0(3) ; PPC64: std [[REG]], 0(3)
; PPC64: addi 1, 1, [[STACK]] ; PPC64: addi 1, 1, [[#%d,STACK]]
; PPC64: ld 0, [[RETADDR]] ; PPC64: ld 0, [[#%d,RETADDR-STACK]]
; PPC64: mtlr 0 ; PPC64: mtlr 0
; PPC64: blr ; PPC64: blr
define void @foo(ptr %X) nounwind { define void @foo(ptr %X) nounwind {
entry: entry:
%tmp = tail call ptr @llvm.returnaddress( i32 0 ) ; <ptr> [#uses=1] %tmp = tail call ptr @llvm.returnaddress( i32 0 ) ; <ptr> [#uses=1]
store ptr %tmp, ptr %X, align 4 store ptr %tmp, ptr %X, align 4
ret void ret void
} }
declare ptr @llvm.returnaddress(i32) declare ptr @llvm.returnaddress(i32)

llvm/test/CodeGen/PowerPC/retaddr2.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s
target datalayout = "E-m:e-i64:64-n32:64" target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
define ptr @test1() #0 { define ptr @test1() #0 {
entry: entry:
%0 = tail call ptr @llvm.returnaddress(i32 0) %0 = tail call ptr @llvm.returnaddress(i32 0)
ret ptr %0 ret ptr %0
} }
; CHECK-LABEL: @test1 ; CHECK-LABEL: @test1
; CHECK: mflr {{[0-9]+}} ; CHECK: mflr {{[0-9]+}}
; CHECK: std 0, 16(1) ; CHECK: std 0, 64(1)
; CHECK-DAG: ld 3, 64(1) ; CHECK-DAG: ld 3, 64(1)
; CHECK-DAG: ld [[SR:[0-9]+]], 16(1) ; CHECK-DAG: ld [[SR:[0-9]+]], 16(1)
; CHECK: mtlr [[SR]] ; CHECK: mtlr [[SR]]
; CHECK: blr ; CHECK: blr
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
declare ptr @llvm.returnaddress(i32) #0 declare ptr @llvm.returnaddress(i32) #0
attributes #0 = { nounwind readnone } attributes #0 = { nounwind readnone }

llvm/test/CodeGen/PowerPC/retaddr_multi_levels.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux \ ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux \
; RUN: -mcpu=pwr8 | FileCheck %s -check-prefix=CHECK-64B-LE ; RUN: -mcpu=pwr8 | FileCheck %s -check-prefix=CHECK-64B-LE
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux \ ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux \
; RUN: -mcpu=pwr7 | FileCheck %s -check-prefix=CHECK-64B-BE ; RUN: -mcpu=pwr7 | FileCheck %s -check-prefix=CHECK-64B-BE
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-aix \ ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-aix \
; RUN: -mcpu=pwr7 | FileCheck %s -check-prefix=CHECK-64B-BE ; RUN: -mcpu=pwr7 | FileCheck %s -check-prefix=CHECK-64B-BE
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-aix \ ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-aix \
; RUN: -mcpu=pwr7 | FileCheck %s -check-prefix=CHECK-32B-BE ; RUN: -mcpu=pwr7 | FileCheck %s -check-prefix=CHECK-32B-BE
declare ptr @llvm.returnaddress(i32) nounwind readnone declare ptr @llvm.returnaddress(i32) nounwind readnone
define ptr @test0() nounwind readnone { define ptr @test0() nounwind readnone {
; CHECK-64B-LE-LABEL: test0: ; CHECK-64B-LE-LABEL: test0:
; CHECK-64B-LE: # %bb.0: # %entry ; CHECK-64B-LE: # %bb.0: # %entry
; CHECK-64B-LE-NEXT: mflr 0 ; CHECK-64B-LE-NEXT: mflr 0
; CHECK-64B-LE-NEXT: std 0, 16(1)
; CHECK-64B-LE-NEXT: stdu 1, -32(1) ; CHECK-64B-LE-NEXT: stdu 1, -32(1)
; CHECK-64B-LE-NEXT: std 0, 48(1)
; CHECK-64B-LE-NEXT: ld 3, 48(1) ; CHECK-64B-LE-NEXT: ld 3, 48(1)
; CHECK-64B-LE-NEXT: addi 1, 1, 32 ; CHECK-64B-LE-NEXT: addi 1, 1, 32
; CHECK-64B-LE-NEXT: ld 0, 16(1) ; CHECK-64B-LE-NEXT: ld 0, 16(1)
; CHECK-64B-LE-NEXT: mtlr 0 ; CHECK-64B-LE-NEXT: mtlr 0
; CHECK-64B-LE-NEXT: blr ; CHECK-64B-LE-NEXT: blr
; ;
; CHECK-64B-BE-LABEL: test0: ; CHECK-64B-BE-LABEL: test0:
; CHECK-64B-BE: # %bb.0: # %entry ; CHECK-64B-BE: # %bb.0: # %entry
; CHECK-64B-BE-NEXT: mflr 0 ; CHECK-64B-BE-NEXT: mflr 0
; CHECK-64B-BE-NEXT: std 0, 16(1)
; CHECK-64B-BE-NEXT: stdu 1, -48(1) ; CHECK-64B-BE-NEXT: stdu 1, -48(1)
; CHECK-64B-BE-NEXT: std 0, 64(1)
; CHECK-64B-BE-NEXT: ld 3, 64(1) ; CHECK-64B-BE-NEXT: ld 3, 64(1)
; CHECK-64B-BE-NEXT: addi 1, 1, 48 ; CHECK-64B-BE-NEXT: addi 1, 1, 48
; CHECK-64B-BE-NEXT: ld 0, 16(1) ; CHECK-64B-BE-NEXT: ld 0, 16(1)
; CHECK-64B-BE-NEXT: mtlr 0 ; CHECK-64B-BE-NEXT: mtlr 0
; CHECK-64B-BE-NEXT: blr ; CHECK-64B-BE-NEXT: blr
; ;
; CHECK-32B-BE-LABEL: test0: ; CHECK-32B-BE-LABEL: test0:
; CHECK-32B-BE: # %bb.0: # %entry ; CHECK-32B-BE: # %bb.0: # %entry
; CHECK-32B-BE-NEXT: mflr 0 ; CHECK-32B-BE-NEXT: mflr 0
; CHECK-32B-BE-NEXT: stw 0, 8(1)
; CHECK-32B-BE-NEXT: stwu 1, -32(1) ; CHECK-32B-BE-NEXT: stwu 1, -32(1)
; CHECK-32B-BE-NEXT: stw 0, 40(1)
; CHECK-32B-BE-NEXT: lwz 3, 40(1) ; CHECK-32B-BE-NEXT: lwz 3, 40(1)
; CHECK-32B-BE-NEXT: addi 1, 1, 32 ; CHECK-32B-BE-NEXT: addi 1, 1, 32
; CHECK-32B-BE-NEXT: lwz 0, 8(1) ; CHECK-32B-BE-NEXT: lwz 0, 8(1)
; CHECK-32B-BE-NEXT: mtlr 0 ; CHECK-32B-BE-NEXT: mtlr 0
; CHECK-32B-BE-NEXT: blr ; CHECK-32B-BE-NEXT: blr
entry: entry:
%0 = tail call ptr @llvm.returnaddress(i32 0); %0 = tail call ptr @llvm.returnaddress(i32 0);
ret ptr %0 ret ptr %0
} }
define ptr @test1() nounwind readnone { define ptr @test1() nounwind readnone {
; CHECK-64B-LE-LABEL: test1: ; CHECK-64B-LE-LABEL: test1:
; CHECK-64B-LE: # %bb.0: # %entry ; CHECK-64B-LE: # %bb.0: # %entry
; CHECK-64B-LE-NEXT: mflr 0 ; CHECK-64B-LE-NEXT: mflr 0
; CHECK-64B-LE-NEXT: std 0, 16(1)
; CHECK-64B-LE-NEXT: stdu 1, -32(1) ; CHECK-64B-LE-NEXT: stdu 1, -32(1)
; CHECK-64B-LE-NEXT: std 0, 48(1)
; CHECK-64B-LE-NEXT: ld 3, 0(1) ; CHECK-64B-LE-NEXT: ld 3, 0(1)
; CHECK-64B-LE-NEXT: ld 3, 0(3) ; CHECK-64B-LE-NEXT: ld 3, 0(3)
; CHECK-64B-LE-NEXT: ld 3, 16(3) ; CHECK-64B-LE-NEXT: ld 3, 16(3)
; CHECK-64B-LE-NEXT: addi 1, 1, 32 ; CHECK-64B-LE-NEXT: addi 1, 1, 32
; CHECK-64B-LE-NEXT: ld 0, 16(1) ; CHECK-64B-LE-NEXT: ld 0, 16(1)
; CHECK-64B-LE-NEXT: mtlr 0 ; CHECK-64B-LE-NEXT: mtlr 0
; CHECK-64B-LE-NEXT: blr ; CHECK-64B-LE-NEXT: blr
; ;
; CHECK-64B-BE-LABEL: test1: ; CHECK-64B-BE-LABEL: test1:
; CHECK-64B-BE: # %bb.0: # %entry ; CHECK-64B-BE: # %bb.0: # %entry
; CHECK-64B-BE-NEXT: mflr 0 ; CHECK-64B-BE-NEXT: mflr 0
; CHECK-64B-BE-NEXT: std 0, 16(1)
; CHECK-64B-BE-NEXT: stdu 1, -48(1) ; CHECK-64B-BE-NEXT: stdu 1, -48(1)
; CHECK-64B-BE-NEXT: std 0, 64(1)
; CHECK-64B-BE-NEXT: ld 3, 0(1) ; CHECK-64B-BE-NEXT: ld 3, 0(1)
; CHECK-64B-BE-NEXT: ld 3, 0(3) ; CHECK-64B-BE-NEXT: ld 3, 0(3)
; CHECK-64B-BE-NEXT: ld 3, 16(3) ; CHECK-64B-BE-NEXT: ld 3, 16(3)
; CHECK-64B-BE-NEXT: addi 1, 1, 48 ; CHECK-64B-BE-NEXT: addi 1, 1, 48
; CHECK-64B-BE-NEXT: ld 0, 16(1) ; CHECK-64B-BE-NEXT: ld 0, 16(1)
; CHECK-64B-BE-NEXT: mtlr 0 ; CHECK-64B-BE-NEXT: mtlr 0
; CHECK-64B-BE-NEXT: blr ; CHECK-64B-BE-NEXT: blr
; ;
; CHECK-32B-BE-LABEL: test1: ; CHECK-32B-BE-LABEL: test1:
; CHECK-32B-BE: # %bb.0: # %entry ; CHECK-32B-BE: # %bb.0: # %entry
; CHECK-32B-BE-NEXT: mflr 0 ; CHECK-32B-BE-NEXT: mflr 0
; CHECK-32B-BE-NEXT: stw 0, 8(1)
; CHECK-32B-BE-NEXT: stwu 1, -32(1) ; CHECK-32B-BE-NEXT: stwu 1, -32(1)
; CHECK-32B-BE-NEXT: stw 0, 40(1)
; CHECK-32B-BE-NEXT: lwz 3, 0(1) ; CHECK-32B-BE-NEXT: lwz 3, 0(1)
; CHECK-32B-BE-NEXT: lwz 3, 0(3) ; CHECK-32B-BE-NEXT: lwz 3, 0(3)
; CHECK-32B-BE-NEXT: lwz 3, 8(3) ; CHECK-32B-BE-NEXT: lwz 3, 8(3)
; CHECK-32B-BE-NEXT: addi 1, 1, 32 ; CHECK-32B-BE-NEXT: addi 1, 1, 32
; CHECK-32B-BE-NEXT: lwz 0, 8(1) ; CHECK-32B-BE-NEXT: lwz 0, 8(1)
; CHECK-32B-BE-NEXT: mtlr 0 ; CHECK-32B-BE-NEXT: mtlr 0
; CHECK-32B-BE-NEXT: blr ; CHECK-32B-BE-NEXT: blr
entry: entry:
%0 = tail call ptr @llvm.returnaddress(i32 1); %0 = tail call ptr @llvm.returnaddress(i32 1);
ret ptr %0 ret ptr %0
} }
define ptr @test2() nounwind readnone { define ptr @test2() nounwind readnone {
; CHECK-64B-LE-LABEL: test2: ; CHECK-64B-LE-LABEL: test2:
; CHECK-64B-LE: # %bb.0: # %entry ; CHECK-64B-LE: # %bb.0: # %entry
; CHECK-64B-LE-NEXT: mflr 0 ; CHECK-64B-LE-NEXT: mflr 0
; CHECK-64B-LE-NEXT: std 0, 16(1)
; CHECK-64B-LE-NEXT: stdu 1, -32(1) ; CHECK-64B-LE-NEXT: stdu 1, -32(1)
; CHECK-64B-LE-NEXT: std 0, 48(1)
; CHECK-64B-LE-NEXT: ld 3, 0(1) ; CHECK-64B-LE-NEXT: ld 3, 0(1)
; CHECK-64B-LE-NEXT: ld 3, 0(3) ; CHECK-64B-LE-NEXT: ld 3, 0(3)
; CHECK-64B-LE-NEXT: ld 3, 0(3) ; CHECK-64B-LE-NEXT: ld 3, 0(3)
; CHECK-64B-LE-NEXT: ld 3, 16(3) ; CHECK-64B-LE-NEXT: ld 3, 16(3)
; CHECK-64B-LE-NEXT: addi 1, 1, 32 ; CHECK-64B-LE-NEXT: addi 1, 1, 32
; CHECK-64B-LE-NEXT: ld 0, 16(1) ; CHECK-64B-LE-NEXT: ld 0, 16(1)
; CHECK-64B-LE-NEXT: mtlr 0 ; CHECK-64B-LE-NEXT: mtlr 0
; CHECK-64B-LE-NEXT: blr ; CHECK-64B-LE-NEXT: blr
; ;
; CHECK-64B-BE-LABEL: test2: ; CHECK-64B-BE-LABEL: test2:
; CHECK-64B-BE: # %bb.0: # %entry ; CHECK-64B-BE: # %bb.0: # %entry
; CHECK-64B-BE-NEXT: mflr 0 ; CHECK-64B-BE-NEXT: mflr 0
; CHECK-64B-BE-NEXT: std 0, 16(1)
; CHECK-64B-BE-NEXT: stdu 1, -48(1) ; CHECK-64B-BE-NEXT: stdu 1, -48(1)
; CHECK-64B-BE-NEXT: std 0, 64(1)
; CHECK-64B-BE-NEXT: ld 3, 0(1) ; CHECK-64B-BE-NEXT: ld 3, 0(1)
; CHECK-64B-BE-NEXT: ld 3, 0(3) ; CHECK-64B-BE-NEXT: ld 3, 0(3)
; CHECK-64B-BE-NEXT: ld 3, 0(3) ; CHECK-64B-BE-NEXT: ld 3, 0(3)
; CHECK-64B-BE-NEXT: ld 3, 16(3) ; CHECK-64B-BE-NEXT: ld 3, 16(3)
; CHECK-64B-BE-NEXT: addi 1, 1, 48 ; CHECK-64B-BE-NEXT: addi 1, 1, 48
; CHECK-64B-BE-NEXT: ld 0, 16(1) ; CHECK-64B-BE-NEXT: ld 0, 16(1)
; CHECK-64B-BE-NEXT: mtlr 0 ; CHECK-64B-BE-NEXT: mtlr 0
; CHECK-64B-BE-NEXT: blr ; CHECK-64B-BE-NEXT: blr
; ;
; CHECK-32B-BE-LABEL: test2: ; CHECK-32B-BE-LABEL: test2:
; CHECK-32B-BE: # %bb.0: # %entry ; CHECK-32B-BE: # %bb.0: # %entry
; CHECK-32B-BE-NEXT: mflr 0 ; CHECK-32B-BE-NEXT: mflr 0
; CHECK-32B-BE-NEXT: stw 0, 8(1)
; CHECK-32B-BE-NEXT: stwu 1, -32(1) ; CHECK-32B-BE-NEXT: stwu 1, -32(1)
; CHECK-32B-BE-NEXT: stw 0, 40(1)
; CHECK-32B-BE-NEXT: lwz 3, 0(1) ; CHECK-32B-BE-NEXT: lwz 3, 0(1)
; CHECK-32B-BE-NEXT: lwz 3, 0(3) ; CHECK-32B-BE-NEXT: lwz 3, 0(3)
; CHECK-32B-BE-NEXT: lwz 3, 0(3) ; CHECK-32B-BE-NEXT: lwz 3, 0(3)
; CHECK-32B-BE-NEXT: lwz 3, 8(3) ; CHECK-32B-BE-NEXT: lwz 3, 8(3)
; CHECK-32B-BE-NEXT: addi 1, 1, 32 ; CHECK-32B-BE-NEXT: addi 1, 1, 32
; CHECK-32B-BE-NEXT: lwz 0, 8(1) ; CHECK-32B-BE-NEXT: lwz 0, 8(1)
; CHECK-32B-BE-NEXT: mtlr 0 ; CHECK-32B-BE-NEXT: mtlr 0
; CHECK-32B-BE-NEXT: blr ; CHECK-32B-BE-NEXT: blr
entry: entry:
%0 = tail call ptr @llvm.returnaddress(i32 2); %0 = tail call ptr @llvm.returnaddress(i32 2);
ret ptr %0 ret ptr %0
} }

llvm/test/CodeGen/PowerPC/scalar-rounding-ops.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mcpu=pwr7 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ ; RUN: llc -mcpu=pwr7 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
; RUN: -mtriple=powerpc64-unknown-unknown -verify-machineinstrs < %s | \ ; RUN: -mtriple=powerpc64-unknown-unknown -verify-machineinstrs < %s | \
; RUN: FileCheck %s --check-prefix=BE ; RUN: FileCheck %s --check-prefix=BE
; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ ; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
; RUN: -mtriple=powerpc64le-unknown-unknown -verify-machineinstrs < %s | \ ; RUN: -mtriple=powerpc64le-unknown-unknown -verify-machineinstrs < %s | \
; RUN: FileCheck %s ; RUN: FileCheck %s
; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ ; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
; RUN: -mtriple=powerpc64le-unknown-unknown -verify-machineinstrs < %s \ ; RUN: -mtriple=powerpc64le-unknown-unknown -verify-machineinstrs < %s \
; RUN: --enable-unsafe-fp-math | FileCheck %s --check-prefix=FAST ; RUN: --enable-unsafe-fp-math | FileCheck %s --check-prefix=FAST
define dso_local i64 @test_lrint(double %d) local_unnamed_addr { define dso_local i64 @test_lrint(double %d) local_unnamed_addr {
; BE-LABEL: test_lrint: ; BE-LABEL: test_lrint:
; BE: # %bb.0: # %entry ; BE: # %bb.0: # %entry
; BE-NEXT: mflr r0 ; BE-NEXT: mflr r0
; BE-NEXT: std r0, 16(r1)
; BE-NEXT: stdu r1, -112(r1) ; BE-NEXT: stdu r1, -112(r1)
; BE-NEXT: std r0, 128(r1)
; BE-NEXT: .cfi_def_cfa_offset 112 ; BE-NEXT: .cfi_def_cfa_offset 112
; BE-NEXT: .cfi_offset lr, 16 ; BE-NEXT: .cfi_offset lr, 16
; BE-NEXT: bl lrint ; BE-NEXT: bl lrint
; BE-NEXT: nop ; BE-NEXT: nop
; BE-NEXT: addi r1, r1, 112 ; BE-NEXT: addi r1, r1, 112
; BE-NEXT: ld r0, 16(r1) ; BE-NEXT: ld r0, 16(r1)
; BE-NEXT: mtlr r0 ; BE-NEXT: mtlr r0
; BE-NEXT: blr ; BE-NEXT: blr
; ;
; CHECK-LABEL: test_lrint: ; CHECK-LABEL: test_lrint:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr r0 ; CHECK-NEXT: mflr r0
; CHECK-NEXT: std r0, 16(r1)
; CHECK-NEXT: stdu r1, -32(r1) ; CHECK-NEXT: stdu r1, -32(r1)
; CHECK-NEXT: std r0, 48(r1)
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: bl lrint ; CHECK-NEXT: bl lrint
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: addi r1, r1, 32 ; CHECK-NEXT: addi r1, r1, 32
; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: ld r0, 16(r1)
; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: mtlr r0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
Show All 9 Lines
} }
declare i64 @llvm.lrint.i64.f64(double) declare i64 @llvm.lrint.i64.f64(double)
define dso_local i64 @test_lrintf(float %f) local_unnamed_addr { define dso_local i64 @test_lrintf(float %f) local_unnamed_addr {
; BE-LABEL: test_lrintf: ; BE-LABEL: test_lrintf:
; BE: # %bb.0: # %entry ; BE: # %bb.0: # %entry
; BE-NEXT: mflr r0 ; BE-NEXT: mflr r0
; BE-NEXT: std r0, 16(r1)
; BE-NEXT: stdu r1, -112(r1) ; BE-NEXT: stdu r1, -112(r1)
; BE-NEXT: std r0, 128(r1)
; BE-NEXT: .cfi_def_cfa_offset 112 ; BE-NEXT: .cfi_def_cfa_offset 112
; BE-NEXT: .cfi_offset lr, 16 ; BE-NEXT: .cfi_offset lr, 16
; BE-NEXT: bl lrintf ; BE-NEXT: bl lrintf
; BE-NEXT: nop ; BE-NEXT: nop
; BE-NEXT: addi r1, r1, 112 ; BE-NEXT: addi r1, r1, 112
; BE-NEXT: ld r0, 16(r1) ; BE-NEXT: ld r0, 16(r1)
; BE-NEXT: mtlr r0 ; BE-NEXT: mtlr r0
; BE-NEXT: blr ; BE-NEXT: blr
; ;
; CHECK-LABEL: test_lrintf: ; CHECK-LABEL: test_lrintf:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr r0 ; CHECK-NEXT: mflr r0
; CHECK-NEXT: std r0, 16(r1)
; CHECK-NEXT: stdu r1, -32(r1) ; CHECK-NEXT: stdu r1, -32(r1)
; CHECK-NEXT: std r0, 48(r1)
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: bl lrintf ; CHECK-NEXT: bl lrintf
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: addi r1, r1, 32 ; CHECK-NEXT: addi r1, r1, 32
; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: ld r0, 16(r1)
; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: mtlr r0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
Show All 9 Lines
} }
declare i64 @llvm.lrint.i64.f32(float) declare i64 @llvm.lrint.i64.f32(float)
define dso_local i64 @test_llrint(double %d) local_unnamed_addr { define dso_local i64 @test_llrint(double %d) local_unnamed_addr {
; BE-LABEL: test_llrint: ; BE-LABEL: test_llrint:
; BE: # %bb.0: # %entry ; BE: # %bb.0: # %entry
; BE-NEXT: mflr r0 ; BE-NEXT: mflr r0
; BE-NEXT: std r0, 16(r1)
; BE-NEXT: stdu r1, -112(r1) ; BE-NEXT: stdu r1, -112(r1)
; BE-NEXT: std r0, 128(r1)
; BE-NEXT: .cfi_def_cfa_offset 112 ; BE-NEXT: .cfi_def_cfa_offset 112
; BE-NEXT: .cfi_offset lr, 16 ; BE-NEXT: .cfi_offset lr, 16
; BE-NEXT: bl llrint ; BE-NEXT: bl llrint
; BE-NEXT: nop ; BE-NEXT: nop
; BE-NEXT: addi r1, r1, 112 ; BE-NEXT: addi r1, r1, 112
; BE-NEXT: ld r0, 16(r1) ; BE-NEXT: ld r0, 16(r1)
; BE-NEXT: mtlr r0 ; BE-NEXT: mtlr r0
; BE-NEXT: blr ; BE-NEXT: blr
; ;
; CHECK-LABEL: test_llrint: ; CHECK-LABEL: test_llrint:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr r0 ; CHECK-NEXT: mflr r0
; CHECK-NEXT: std r0, 16(r1)
; CHECK-NEXT: stdu r1, -32(r1) ; CHECK-NEXT: stdu r1, -32(r1)
; CHECK-NEXT: std r0, 48(r1)
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: bl llrint ; CHECK-NEXT: bl llrint
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: addi r1, r1, 32 ; CHECK-NEXT: addi r1, r1, 32
; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: ld r0, 16(r1)
; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: mtlr r0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
Show All 9 Lines
} }
declare i64 @llvm.llrint.i64.f64(double) declare i64 @llvm.llrint.i64.f64(double)
define dso_local i64 @test_llrintf(float %f) local_unnamed_addr { define dso_local i64 @test_llrintf(float %f) local_unnamed_addr {
; BE-LABEL: test_llrintf: ; BE-LABEL: test_llrintf:
; BE: # %bb.0: # %entry ; BE: # %bb.0: # %entry
; BE-NEXT: mflr r0 ; BE-NEXT: mflr r0
; BE-NEXT: std r0, 16(r1)
; BE-NEXT: stdu r1, -112(r1) ; BE-NEXT: stdu r1, -112(r1)
; BE-NEXT: std r0, 128(r1)
; BE-NEXT: .cfi_def_cfa_offset 112 ; BE-NEXT: .cfi_def_cfa_offset 112
; BE-NEXT: .cfi_offset lr, 16 ; BE-NEXT: .cfi_offset lr, 16
; BE-NEXT: bl llrintf ; BE-NEXT: bl llrintf
; BE-NEXT: nop ; BE-NEXT: nop
; BE-NEXT: addi r1, r1, 112 ; BE-NEXT: addi r1, r1, 112
; BE-NEXT: ld r0, 16(r1) ; BE-NEXT: ld r0, 16(r1)
; BE-NEXT: mtlr r0 ; BE-NEXT: mtlr r0
; BE-NEXT: blr ; BE-NEXT: blr
; ;
; CHECK-LABEL: test_llrintf: ; CHECK-LABEL: test_llrintf:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr r0 ; CHECK-NEXT: mflr r0
; CHECK-NEXT: std r0, 16(r1)
; CHECK-NEXT: stdu r1, -32(r1) ; CHECK-NEXT: stdu r1, -32(r1)
; CHECK-NEXT: std r0, 48(r1)
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: bl llrintf ; CHECK-NEXT: bl llrintf
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: addi r1, r1, 32 ; CHECK-NEXT: addi r1, r1, 32
; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: ld r0, 16(r1)
; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: mtlr r0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
Show All 9 Lines
} }
declare i64 @llvm.llrint.i64.f32(float) declare i64 @llvm.llrint.i64.f32(float)
define dso_local i64 @test_lround(double %d) local_unnamed_addr { define dso_local i64 @test_lround(double %d) local_unnamed_addr {
; BE-LABEL: test_lround: ; BE-LABEL: test_lround:
; BE: # %bb.0: # %entry ; BE: # %bb.0: # %entry
; BE-NEXT: mflr r0 ; BE-NEXT: mflr r0
; BE-NEXT: std r0, 16(r1)
; BE-NEXT: stdu r1, -112(r1) ; BE-NEXT: stdu r1, -112(r1)
; BE-NEXT: std r0, 128(r1)
; BE-NEXT: .cfi_def_cfa_offset 112 ; BE-NEXT: .cfi_def_cfa_offset 112
; BE-NEXT: .cfi_offset lr, 16 ; BE-NEXT: .cfi_offset lr, 16
; BE-NEXT: bl lround ; BE-NEXT: bl lround
; BE-NEXT: nop ; BE-NEXT: nop
; BE-NEXT: addi r1, r1, 112 ; BE-NEXT: addi r1, r1, 112
; BE-NEXT: ld r0, 16(r1) ; BE-NEXT: ld r0, 16(r1)
; BE-NEXT: mtlr r0 ; BE-NEXT: mtlr r0
; BE-NEXT: blr ; BE-NEXT: blr
; ;
; CHECK-LABEL: test_lround: ; CHECK-LABEL: test_lround:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr r0 ; CHECK-NEXT: mflr r0
; CHECK-NEXT: std r0, 16(r1)
; CHECK-NEXT: stdu r1, -32(r1) ; CHECK-NEXT: stdu r1, -32(r1)
; CHECK-NEXT: std r0, 48(r1)
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: bl lround ; CHECK-NEXT: bl lround
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: addi r1, r1, 32 ; CHECK-NEXT: addi r1, r1, 32
; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: ld r0, 16(r1)
; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: mtlr r0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
Show All 10 Lines
} }
declare i64 @llvm.lround.i64.f64(double) declare i64 @llvm.lround.i64.f64(double)
define dso_local i64 @test_lroundf(float %f) local_unnamed_addr { define dso_local i64 @test_lroundf(float %f) local_unnamed_addr {
; BE-LABEL: test_lroundf: ; BE-LABEL: test_lroundf:
; BE: # %bb.0: # %entry ; BE: # %bb.0: # %entry
; BE-NEXT: mflr r0 ; BE-NEXT: mflr r0
; BE-NEXT: std r0, 16(r1)
; BE-NEXT: stdu r1, -112(r1) ; BE-NEXT: stdu r1, -112(r1)
; BE-NEXT: std r0, 128(r1)
; BE-NEXT: .cfi_def_cfa_offset 112 ; BE-NEXT: .cfi_def_cfa_offset 112
; BE-NEXT: .cfi_offset lr, 16 ; BE-NEXT: .cfi_offset lr, 16
; BE-NEXT: bl lroundf ; BE-NEXT: bl lroundf
; BE-NEXT: nop ; BE-NEXT: nop
; BE-NEXT: addi r1, r1, 112 ; BE-NEXT: addi r1, r1, 112
; BE-NEXT: ld r0, 16(r1) ; BE-NEXT: ld r0, 16(r1)
; BE-NEXT: mtlr r0 ; BE-NEXT: mtlr r0
; BE-NEXT: blr ; BE-NEXT: blr
; ;
; CHECK-LABEL: test_lroundf: ; CHECK-LABEL: test_lroundf:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr r0 ; CHECK-NEXT: mflr r0
; CHECK-NEXT: std r0, 16(r1)
; CHECK-NEXT: stdu r1, -32(r1) ; CHECK-NEXT: stdu r1, -32(r1)
; CHECK-NEXT: std r0, 48(r1)
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: bl lroundf ; CHECK-NEXT: bl lroundf
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: addi r1, r1, 32 ; CHECK-NEXT: addi r1, r1, 32
; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: ld r0, 16(r1)
; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: mtlr r0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
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} }
declare i64 @llvm.lround.i64.f32(float) declare i64 @llvm.lround.i64.f32(float)
define dso_local i64 @test_llround(double %d) local_unnamed_addr { define dso_local i64 @test_llround(double %d) local_unnamed_addr {
; BE-LABEL: test_llround: ; BE-LABEL: test_llround:
; BE: # %bb.0: # %entry ; BE: # %bb.0: # %entry
; BE-NEXT: mflr r0 ; BE-NEXT: mflr r0
; BE-NEXT: std r0, 16(r1)
; BE-NEXT: stdu r1, -112(r1) ; BE-NEXT: stdu r1, -112(r1)
; BE-NEXT: std r0, 128(r1)
; BE-NEXT: .cfi_def_cfa_offset 112 ; BE-NEXT: .cfi_def_cfa_offset 112
; BE-NEXT: .cfi_offset lr, 16 ; BE-NEXT: .cfi_offset lr, 16
; BE-NEXT: bl llround ; BE-NEXT: bl llround
; BE-NEXT: nop ; BE-NEXT: nop
; BE-NEXT: addi r1, r1, 112 ; BE-NEXT: addi r1, r1, 112
; BE-NEXT: ld r0, 16(r1) ; BE-NEXT: ld r0, 16(r1)
; BE-NEXT: mtlr r0 ; BE-NEXT: mtlr r0
; BE-NEXT: blr ; BE-NEXT: blr
; ;
; CHECK-LABEL: test_llround: ; CHECK-LABEL: test_llround:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr r0 ; CHECK-NEXT: mflr r0
; CHECK-NEXT: std r0, 16(r1)
; CHECK-NEXT: stdu r1, -32(r1) ; CHECK-NEXT: stdu r1, -32(r1)
; CHECK-NEXT: std r0, 48(r1)
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: bl llround ; CHECK-NEXT: bl llround
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: addi r1, r1, 32 ; CHECK-NEXT: addi r1, r1, 32
; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: ld r0, 16(r1)
; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: mtlr r0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
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} }
declare i64 @llvm.llround.i64.f64(double) declare i64 @llvm.llround.i64.f64(double)
define dso_local i64 @test_llroundf(float %f) local_unnamed_addr { define dso_local i64 @test_llroundf(float %f) local_unnamed_addr {
; BE-LABEL: test_llroundf: ; BE-LABEL: test_llroundf:
; BE: # %bb.0: # %entry ; BE: # %bb.0: # %entry
; BE-NEXT: mflr r0 ; BE-NEXT: mflr r0
; BE-NEXT: std r0, 16(r1)
; BE-NEXT: stdu r1, -112(r1) ; BE-NEXT: stdu r1, -112(r1)
; BE-NEXT: std r0, 128(r1)
; BE-NEXT: .cfi_def_cfa_offset 112 ; BE-NEXT: .cfi_def_cfa_offset 112
; BE-NEXT: .cfi_offset lr, 16 ; BE-NEXT: .cfi_offset lr, 16
; BE-NEXT: bl llroundf ; BE-NEXT: bl llroundf
; BE-NEXT: nop ; BE-NEXT: nop
; BE-NEXT: addi r1, r1, 112 ; BE-NEXT: addi r1, r1, 112
; BE-NEXT: ld r0, 16(r1) ; BE-NEXT: ld r0, 16(r1)
; BE-NEXT: mtlr r0 ; BE-NEXT: mtlr r0
; BE-NEXT: blr ; BE-NEXT: blr
; ;
; CHECK-LABEL: test_llroundf: ; CHECK-LABEL: test_llroundf:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr r0 ; CHECK-NEXT: mflr r0
; CHECK-NEXT: std r0, 16(r1)
; CHECK-NEXT: stdu r1, -32(r1) ; CHECK-NEXT: stdu r1, -32(r1)
; CHECK-NEXT: std r0, 48(r1)
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: bl llroundf ; CHECK-NEXT: bl llroundf
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: addi r1, r1, 32 ; CHECK-NEXT: addi r1, r1, 32
; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: ld r0, 16(r1)
; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: mtlr r0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
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} }
declare i64 @llvm.llround.i64.f32(float) declare i64 @llvm.llround.i64.f32(float)
define dso_local double @test_nearbyint(double %d) local_unnamed_addr { define dso_local double @test_nearbyint(double %d) local_unnamed_addr {
; BE-LABEL: test_nearbyint: ; BE-LABEL: test_nearbyint:
; BE: # %bb.0: # %entry ; BE: # %bb.0: # %entry
; BE-NEXT: mflr r0 ; BE-NEXT: mflr r0
; BE-NEXT: std r0, 16(r1)
; BE-NEXT: stdu r1, -112(r1) ; BE-NEXT: stdu r1, -112(r1)
; BE-NEXT: std r0, 128(r1)
; BE-NEXT: .cfi_def_cfa_offset 112 ; BE-NEXT: .cfi_def_cfa_offset 112
; BE-NEXT: .cfi_offset lr, 16 ; BE-NEXT: .cfi_offset lr, 16
; BE-NEXT: bl nearbyint ; BE-NEXT: bl nearbyint
; BE-NEXT: nop ; BE-NEXT: nop
; BE-NEXT: addi r1, r1, 112 ; BE-NEXT: addi r1, r1, 112
; BE-NEXT: ld r0, 16(r1) ; BE-NEXT: ld r0, 16(r1)
; BE-NEXT: mtlr r0 ; BE-NEXT: mtlr r0
; BE-NEXT: blr ; BE-NEXT: blr
; ;
; CHECK-LABEL: test_nearbyint: ; CHECK-LABEL: test_nearbyint:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr r0 ; CHECK-NEXT: mflr r0
; CHECK-NEXT: std r0, 16(r1)
; CHECK-NEXT: stdu r1, -32(r1) ; CHECK-NEXT: stdu r1, -32(r1)
; CHECK-NEXT: std r0, 48(r1)
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: bl nearbyint ; CHECK-NEXT: bl nearbyint
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: addi r1, r1, 32 ; CHECK-NEXT: addi r1, r1, 32
; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: ld r0, 16(r1)
; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: mtlr r0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; FAST-LABEL: test_nearbyint: ; FAST-LABEL: test_nearbyint:
; FAST: # %bb.0: # %entry ; FAST: # %bb.0: # %entry
; FAST-NEXT: xsrdpic f1, f1 ; FAST-NEXT: xsrdpic f1, f1
; FAST-NEXT: blr ; FAST-NEXT: blr
entry: entry:
%0 = tail call double @llvm.nearbyint.f64(double %d) %0 = tail call double @llvm.nearbyint.f64(double %d)
ret double %0 ret double %0
} }
declare double @llvm.nearbyint.f64(double) declare double @llvm.nearbyint.f64(double)
define dso_local float @test_nearbyintf(float %f) local_unnamed_addr { define dso_local float @test_nearbyintf(float %f) local_unnamed_addr {
; BE-LABEL: test_nearbyintf: ; BE-LABEL: test_nearbyintf:
; BE: # %bb.0: # %entry ; BE: # %bb.0: # %entry
; BE-NEXT: mflr r0 ; BE-NEXT: mflr r0
; BE-NEXT: std r0, 16(r1)
; BE-NEXT: stdu r1, -112(r1) ; BE-NEXT: stdu r1, -112(r1)
; BE-NEXT: std r0, 128(r1)
; BE-NEXT: .cfi_def_cfa_offset 112 ; BE-NEXT: .cfi_def_cfa_offset 112
; BE-NEXT: .cfi_offset lr, 16 ; BE-NEXT: .cfi_offset lr, 16
; BE-NEXT: bl nearbyintf ; BE-NEXT: bl nearbyintf
; BE-NEXT: nop ; BE-NEXT: nop
; BE-NEXT: addi r1, r1, 112 ; BE-NEXT: addi r1, r1, 112
; BE-NEXT: ld r0, 16(r1) ; BE-NEXT: ld r0, 16(r1)
; BE-NEXT: mtlr r0 ; BE-NEXT: mtlr r0
; BE-NEXT: blr ; BE-NEXT: blr
; ;
; CHECK-LABEL: test_nearbyintf: ; CHECK-LABEL: test_nearbyintf:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr r0 ; CHECK-NEXT: mflr r0
; CHECK-NEXT: std r0, 16(r1)
; CHECK-NEXT: stdu r1, -32(r1) ; CHECK-NEXT: stdu r1, -32(r1)
; CHECK-NEXT: std r0, 48(r1)
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: bl nearbyintf ; CHECK-NEXT: bl nearbyintf
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: addi r1, r1, 32 ; CHECK-NEXT: addi r1, r1, 32
; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: ld r0, 16(r1)
; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: mtlr r0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
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llvm/test/CodeGen/PowerPC/sms-cpy-1.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs\ ; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs\
; RUN: -mcpu=pwr9 --ppc-enable-pipeliner 2>&1 | FileCheck %s ; RUN: -mcpu=pwr9 --ppc-enable-pipeliner 2>&1 | FileCheck %s
@.str.28 = external unnamed_addr constant [69 x i8], align 1 @.str.28 = external unnamed_addr constant [69 x i8], align 1
define void @print_res() nounwind { define void @print_res() nounwind {
; CHECK-LABEL: print_res: ; CHECK-LABEL: print_res:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; CHECK-NEXT: std 0, 16(1)
; CHECK-NEXT: stdu 1, -128(1) ; CHECK-NEXT: stdu 1, -128(1)
; CHECK-NEXT: std 0, 144(1)
; CHECK-NEXT: lwz 3, 0(3) ; CHECK-NEXT: lwz 3, 0(3)
; CHECK-NEXT: addi 3, 3, -1 ; CHECK-NEXT: addi 3, 3, -1
; CHECK-NEXT: clrldi 4, 3, 32 ; CHECK-NEXT: clrldi 4, 3, 32
; CHECK-NEXT: cmplwi 3, 1 ; CHECK-NEXT: cmplwi 3, 1
; CHECK-NEXT: li 3, 1 ; CHECK-NEXT: li 3, 1
; CHECK-NEXT: iselgt 3, 4, 3 ; CHECK-NEXT: iselgt 3, 4, 3
; CHECK-NEXT: li 4, 2 ; CHECK-NEXT: li 4, 2
; CHECK-NEXT: addi 3, 3, -1 ; CHECK-NEXT: addi 3, 3, -1
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llvm/test/CodeGen/PowerPC/sms-phi-1.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs\ ; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs\
; RUN: -mcpu=pwr9 --ppc-enable-pipeliner --pipeliner-force-ii=4 2>&1 | FileCheck %s ; RUN: -mcpu=pwr9 --ppc-enable-pipeliner --pipeliner-force-ii=4 2>&1 | FileCheck %s
define void @main() nounwind #0 { define void @main() nounwind #0 {
; CHECK-LABEL: main: ; CHECK-LABEL: main:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; CHECK-NEXT: std 30, -16(1) # 8-byte Folded Spill ; CHECK-NEXT: std 30, -16(1) # 8-byte Folded Spill
; CHECK-NEXT: std 0, 16(1)
; CHECK-NEXT: stdu 1, -48(1) ; CHECK-NEXT: stdu 1, -48(1)
; CHECK-NEXT: std 0, 64(1)
; CHECK-NEXT: bl strtol ; CHECK-NEXT: bl strtol
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: mr 30, 3 ; CHECK-NEXT: mr 30, 3
; CHECK-NEXT: bl calloc ; CHECK-NEXT: bl calloc
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: clrldi 4, 30, 32 ; CHECK-NEXT: clrldi 4, 30, 32
; CHECK-NEXT: li 5, 0 ; CHECK-NEXT: li 5, 0
; CHECK-NEXT: addi 3, 3, -4 ; CHECK-NEXT: addi 3, 3, -4
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llvm/test/CodeGen/PowerPC/sms-phi-3.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs\ ; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs\
; RUN: -mcpu=pwr9 --ppc-enable-pipeliner 2>&1 | FileCheck %s ; RUN: -mcpu=pwr9 --ppc-enable-pipeliner 2>&1 | FileCheck %s
%0 = type { double, double, double, i32, i32 } %0 = type { double, double, double, i32, i32 }
declare i8* @malloc() local_unnamed_addr declare i8* @malloc() local_unnamed_addr
define void @phi3(i32*) nounwind { define void @phi3(i32*) nounwind {
; CHECK-LABEL: phi3: ; CHECK-LABEL: phi3:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; CHECK-NEXT: std 29, -24(1) # 8-byte Folded Spill ; CHECK-NEXT: std 29, -24(1) # 8-byte Folded Spill
; CHECK-NEXT: std 30, -16(1) # 8-byte Folded Spill ; CHECK-NEXT: std 30, -16(1) # 8-byte Folded Spill
; CHECK-NEXT: std 0, 16(1)
; CHECK-NEXT: stdu 1, -64(1) ; CHECK-NEXT: stdu 1, -64(1)
; CHECK-NEXT: std 0, 80(1)
; CHECK-NEXT: mr 30, 3 ; CHECK-NEXT: mr 30, 3
; CHECK-NEXT: bl malloc ; CHECK-NEXT: bl malloc
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: mr 29, 3 ; CHECK-NEXT: mr 29, 3
; CHECK-NEXT: bl malloc ; CHECK-NEXT: bl malloc
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: addi 7, 30, -4 ; CHECK-NEXT: addi 7, 30, -4
; CHECK-NEXT: mtctr 3 ; CHECK-NEXT: mtctr 3
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; CHECK-NEXT: # %bb.2: ; CHECK-NEXT: # %bb.2:
; CHECK-NEXT: add 6, 3, 6 ; CHECK-NEXT: add 6, 3, 6
; CHECK-NEXT: stdu 6, 8(4) ; CHECK-NEXT: stdu 6, 8(4)
; CHECK-NEXT: extswsli 6, 5, 5 ; CHECK-NEXT: extswsli 6, 5, 5
; CHECK-NEXT: add 5, 8, 5 ; CHECK-NEXT: add 5, 8, 5
; CHECK-NEXT: lwzu 8, 4(7) ; CHECK-NEXT: lwzu 8, 4(7)
; CHECK-NEXT: bdz .LBB0_4 ; CHECK-NEXT: bdz .LBB0_4
; CHECK-NEXT: .p2align 5 ; CHECK-NEXT: .p2align 5
; CHECK-NEXT: .LBB0_3: # ; CHECK-NEXT: .LBB0_3:
; CHECK-NEXT: add 9, 3, 6 ; CHECK-NEXT: add 9, 3, 6
; CHECK-NEXT: extswsli 6, 5, 5 ; CHECK-NEXT: extswsli 6, 5, 5
; CHECK-NEXT: add 5, 8, 5 ; CHECK-NEXT: add 5, 8, 5
; CHECK-NEXT: lwzu 8, 4(7) ; CHECK-NEXT: lwzu 8, 4(7)
; CHECK-NEXT: stdu 9, 8(4) ; CHECK-NEXT: stdu 9, 8(4)
; CHECK-NEXT: bdnz .LBB0_3 ; CHECK-NEXT: bdnz .LBB0_3
; CHECK-NEXT: .LBB0_4: ; CHECK-NEXT: .LBB0_4:
; CHECK-NEXT: add 6, 3, 6 ; CHECK-NEXT: add 6, 3, 6
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llvm/test/CodeGen/PowerPC/spe.ll

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; SPE: # %bb.0: # %entry ; SPE: # %bb.0: # %entry
; SPE-NEXT: evmergelo 3, 3, 4 ; SPE-NEXT: evmergelo 3, 3, 4
; SPE-NEXT: efscfd 3, 3 ; SPE-NEXT: efscfd 3, 3
; SPE-NEXT: blr ; SPE-NEXT: blr
; ;
; EFPU2-LABEL: test_dtos: ; EFPU2-LABEL: test_dtos:
; EFPU2: # %bb.0: # %entry ; EFPU2: # %bb.0: # %entry
; EFPU2-NEXT: mflr 0 ; EFPU2-NEXT: mflr 0
; EFPU2-NEXT: stw 0, 4(1)
; EFPU2-NEXT: stwu 1, -16(1) ; EFPU2-NEXT: stwu 1, -16(1)
; EFPU2-NEXT: stw 0, 20(1)
; EFPU2-NEXT: bl __truncdfsf2 ; EFPU2-NEXT: bl __truncdfsf2
; EFPU2-NEXT: lwz 0, 20(1) ; EFPU2-NEXT: lwz 0, 20(1)
; EFPU2-NEXT: addi 1, 1, 16 ; EFPU2-NEXT: addi 1, 1, 16
; EFPU2-NEXT: mtlr 0 ; EFPU2-NEXT: mtlr 0
; EFPU2-NEXT: blr ; EFPU2-NEXT: blr
entry: entry:
%v = fptrunc double %a to float %v = fptrunc double %a to float
ret float %v ret float %v
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; SPE-NEXT: evmergehi 3, 4, 4 ; SPE-NEXT: evmergehi 3, 4, 4
; SPE-NEXT: # kill: def $r4 killed $r4 killed $s4 ; SPE-NEXT: # kill: def $r4 killed $r4 killed $s4
; SPE-NEXT: # kill: def $r3 killed $r3 killed $s3 ; SPE-NEXT: # kill: def $r3 killed $r3 killed $s3
; SPE-NEXT: blr ; SPE-NEXT: blr
; ;
; EFPU2-LABEL: test_ddiv: ; EFPU2-LABEL: test_ddiv:
; EFPU2: # %bb.0: # %entry ; EFPU2: # %bb.0: # %entry
; EFPU2-NEXT: mflr 0 ; EFPU2-NEXT: mflr 0
; EFPU2-NEXT: stw 0, 4(1)
; EFPU2-NEXT: stwu 1, -16(1) ; EFPU2-NEXT: stwu 1, -16(1)
; EFPU2-NEXT: stw 0, 20(1)
; EFPU2-NEXT: bl __divdf3 ; EFPU2-NEXT: bl __divdf3
; EFPU2-NEXT: lwz 0, 20(1) ; EFPU2-NEXT: lwz 0, 20(1)
; EFPU2-NEXT: addi 1, 1, 16 ; EFPU2-NEXT: addi 1, 1, 16
; EFPU2-NEXT: mtlr 0 ; EFPU2-NEXT: mtlr 0
; EFPU2-NEXT: blr ; EFPU2-NEXT: blr
entry: entry:
%v = fdiv double %a, %b %v = fdiv double %a, %b
ret double %v ret double %v
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; SPE-NEXT: evmergehi 3, 4, 4 ; SPE-NEXT: evmergehi 3, 4, 4
; SPE-NEXT: # kill: def $r4 killed $r4 killed $s4 ; SPE-NEXT: # kill: def $r4 killed $r4 killed $s4
; SPE-NEXT: # kill: def $r3 killed $r3 killed $s3 ; SPE-NEXT: # kill: def $r3 killed $r3 killed $s3
; SPE-NEXT: blr ; SPE-NEXT: blr
; ;
; EFPU2-LABEL: test_dmul: ; EFPU2-LABEL: test_dmul:
; EFPU2: # %bb.0: # %entry ; EFPU2: # %bb.0: # %entry
; EFPU2-NEXT: mflr 0 ; EFPU2-NEXT: mflr 0
; EFPU2-NEXT: stw 0, 4(1)
; EFPU2-NEXT: stwu 1, -16(1) ; EFPU2-NEXT: stwu 1, -16(1)
; EFPU2-NEXT: stw 0, 20(1)
; EFPU2-NEXT: bl __muldf3 ; EFPU2-NEXT: bl __muldf3
; EFPU2-NEXT: lwz 0, 20(1) ; EFPU2-NEXT: lwz 0, 20(1)
; EFPU2-NEXT: addi 1, 1, 16 ; EFPU2-NEXT: addi 1, 1, 16
; EFPU2-NEXT: mtlr 0 ; EFPU2-NEXT: mtlr 0
; EFPU2-NEXT: blr ; EFPU2-NEXT: blr
entry: entry:
%v = fmul double %a, %b %v = fmul double %a, %b
ret double %v ret double %v
} }
define double @test_dadd(double %a, double %b) #0 { define double @test_dadd(double %a, double %b) #0 {
; SPE-LABEL: test_dadd: ; SPE-LABEL: test_dadd:
; SPE: # %bb.0: # %entry ; SPE: # %bb.0: # %entry
; SPE-NEXT: evmergelo 5, 5, 6 ; SPE-NEXT: evmergelo 5, 5, 6
; SPE-NEXT: evmergelo 3, 3, 4 ; SPE-NEXT: evmergelo 3, 3, 4
; SPE-NEXT: efdadd 4, 3, 5 ; SPE-NEXT: efdadd 4, 3, 5
; SPE-NEXT: evmergehi 3, 4, 4 ; SPE-NEXT: evmergehi 3, 4, 4
; SPE-NEXT: # kill: def $r4 killed $r4 killed $s4 ; SPE-NEXT: # kill: def $r4 killed $r4 killed $s4
; SPE-NEXT: # kill: def $r3 killed $r3 killed $s3 ; SPE-NEXT: # kill: def $r3 killed $r3 killed $s3
; SPE-NEXT: blr ; SPE-NEXT: blr
; ;
; EFPU2-LABEL: test_dadd: ; EFPU2-LABEL: test_dadd:
; EFPU2: # %bb.0: # %entry ; EFPU2: # %bb.0: # %entry
; EFPU2-NEXT: mflr 0 ; EFPU2-NEXT: mflr 0
; EFPU2-NEXT: stw 0, 4(1)
; EFPU2-NEXT: stwu 1, -16(1) ; EFPU2-NEXT: stwu 1, -16(1)
; EFPU2-NEXT: stw 0, 20(1)
; EFPU2-NEXT: bl __adddf3 ; EFPU2-NEXT: bl __adddf3
; EFPU2-NEXT: lwz 0, 20(1) ; EFPU2-NEXT: lwz 0, 20(1)
; EFPU2-NEXT: addi 1, 1, 16 ; EFPU2-NEXT: addi 1, 1, 16
; EFPU2-NEXT: mtlr 0 ; EFPU2-NEXT: mtlr 0
; EFPU2-NEXT: blr ; EFPU2-NEXT: blr
entry: entry:
%v = fadd double %a, %b %v = fadd double %a, %b
ret double %v ret double %v
} }
define double @test_dsub(double %a, double %b) #0 { define double @test_dsub(double %a, double %b) #0 {
; SPE-LABEL: test_dsub: ; SPE-LABEL: test_dsub:
; SPE: # %bb.0: # %entry ; SPE: # %bb.0: # %entry
; SPE-NEXT: evmergelo 5, 5, 6 ; SPE-NEXT: evmergelo 5, 5, 6
; SPE-NEXT: evmergelo 3, 3, 4 ; SPE-NEXT: evmergelo 3, 3, 4
; SPE-NEXT: efdsub 4, 3, 5 ; SPE-NEXT: efdsub 4, 3, 5
; SPE-NEXT: evmergehi 3, 4, 4 ; SPE-NEXT: evmergehi 3, 4, 4
; SPE-NEXT: # kill: def $r4 killed $r4 killed $s4 ; SPE-NEXT: # kill: def $r4 killed $r4 killed $s4
; SPE-NEXT: # kill: def $r3 killed $r3 killed $s3 ; SPE-NEXT: # kill: def $r3 killed $r3 killed $s3
; SPE-NEXT: blr ; SPE-NEXT: blr
; ;
; EFPU2-LABEL: test_dsub: ; EFPU2-LABEL: test_dsub:
; EFPU2: # %bb.0: # %entry ; EFPU2: # %bb.0: # %entry
; EFPU2-NEXT: mflr 0 ; EFPU2-NEXT: mflr 0
; EFPU2-NEXT: stw 0, 4(1)
; EFPU2-NEXT: stwu 1, -16(1) ; EFPU2-NEXT: stwu 1, -16(1)
; EFPU2-NEXT: stw 0, 20(1)
; EFPU2-NEXT: bl __subdf3 ; EFPU2-NEXT: bl __subdf3
; EFPU2-NEXT: lwz 0, 20(1) ; EFPU2-NEXT: lwz 0, 20(1)
; EFPU2-NEXT: addi 1, 1, 16 ; EFPU2-NEXT: addi 1, 1, 16
; EFPU2-NEXT: mtlr 0 ; EFPU2-NEXT: mtlr 0
; EFPU2-NEXT: blr ; EFPU2-NEXT: blr
entry: entry:
%v = fsub double %a, %b %v = fsub double %a, %b
ret double %v ret double %v
Show All 25 Lines
; SPE-NEXT: evmergehi 3, 4, 4 ; SPE-NEXT: evmergehi 3, 4, 4
; SPE-NEXT: # kill: def $r4 killed $r4 killed $s4 ; SPE-NEXT: # kill: def $r4 killed $r4 killed $s4
; SPE-NEXT: # kill: def $r3 killed $r3 killed $s3 ; SPE-NEXT: # kill: def $r3 killed $r3 killed $s3
; SPE-NEXT: blr ; SPE-NEXT: blr
; ;
; EFPU2-LABEL: test_stod: ; EFPU2-LABEL: test_stod:
; EFPU2: # %bb.0: # %entry ; EFPU2: # %bb.0: # %entry
; EFPU2-NEXT: mflr 0 ; EFPU2-NEXT: mflr 0
; EFPU2-NEXT: stw 0, 4(1)
; EFPU2-NEXT: stwu 1, -16(1) ; EFPU2-NEXT: stwu 1, -16(1)
; EFPU2-NEXT: stw 0, 20(1)
; EFPU2-NEXT: bl __extendsfdf2 ; EFPU2-NEXT: bl __extendsfdf2
; EFPU2-NEXT: lwz 0, 20(1) ; EFPU2-NEXT: lwz 0, 20(1)
; EFPU2-NEXT: addi 1, 1, 16 ; EFPU2-NEXT: addi 1, 1, 16
; EFPU2-NEXT: mtlr 0 ; EFPU2-NEXT: mtlr 0
; EFPU2-NEXT: blr ; EFPU2-NEXT: blr
entry: entry:
%v = fpext float %a to double %v = fpext float %a to double
ret double %v ret double %v
Show All 15 Lines
; SPE-NEXT: blr ; SPE-NEXT: blr
; SPE-NEXT: .LBB35_2: # %entry ; SPE-NEXT: .LBB35_2: # %entry
; SPE-NEXT: li 3, 0 ; SPE-NEXT: li 3, 0
; SPE-NEXT: blr ; SPE-NEXT: blr
; ;
; EFPU2-LABEL: test_dcmpuno: ; EFPU2-LABEL: test_dcmpuno:
; EFPU2: # %bb.0: # %entry ; EFPU2: # %bb.0: # %entry
; EFPU2-NEXT: mflr 0 ; EFPU2-NEXT: mflr 0
; EFPU2-NEXT: stw 0, 4(1)
; EFPU2-NEXT: stwu 1, -16(1) ; EFPU2-NEXT: stwu 1, -16(1)
; EFPU2-NEXT: stw 0, 20(1)
; EFPU2-NEXT: bl __unorddf2 ; EFPU2-NEXT: bl __unorddf2
; EFPU2-NEXT: cntlzw 3, 3 ; EFPU2-NEXT: cntlzw 3, 3
; EFPU2-NEXT: not 3, 3 ; EFPU2-NEXT: not 3, 3
; EFPU2-NEXT: rlwinm 3, 3, 27, 31, 31 ; EFPU2-NEXT: rlwinm 3, 3, 27, 31, 31
; EFPU2-NEXT: lwz 0, 20(1) ; EFPU2-NEXT: lwz 0, 20(1)
; EFPU2-NEXT: addi 1, 1, 16 ; EFPU2-NEXT: addi 1, 1, 16
; EFPU2-NEXT: mtlr 0 ; EFPU2-NEXT: mtlr 0
; EFPU2-NEXT: blr ; EFPU2-NEXT: blr
Show All 17 Lines
; SPE-NEXT: blr ; SPE-NEXT: blr
; SPE-NEXT: .LBB36_2: # %entry ; SPE-NEXT: .LBB36_2: # %entry
; SPE-NEXT: li 3, 0 ; SPE-NEXT: li 3, 0
; SPE-NEXT: blr ; SPE-NEXT: blr
; ;
; EFPU2-LABEL: test_dcmpord: ; EFPU2-LABEL: test_dcmpord:
; EFPU2: # %bb.0: # %entry ; EFPU2: # %bb.0: # %entry
; EFPU2-NEXT: mflr 0 ; EFPU2-NEXT: mflr 0
; EFPU2-NEXT: stw 0, 4(1)
; EFPU2-NEXT: stwu 1, -16(1) ; EFPU2-NEXT: stwu 1, -16(1)
; EFPU2-NEXT: stw 0, 20(1)
; EFPU2-NEXT: bl __unorddf2 ; EFPU2-NEXT: bl __unorddf2
; EFPU2-NEXT: cntlzw 3, 3 ; EFPU2-NEXT: cntlzw 3, 3
; EFPU2-NEXT: rlwinm 3, 3, 27, 31, 31 ; EFPU2-NEXT: rlwinm 3, 3, 27, 31, 31
; EFPU2-NEXT: lwz 0, 20(1) ; EFPU2-NEXT: lwz 0, 20(1)
; EFPU2-NEXT: addi 1, 1, 16 ; EFPU2-NEXT: addi 1, 1, 16
; EFPU2-NEXT: mtlr 0 ; EFPU2-NEXT: mtlr 0
; EFPU2-NEXT: blr ; EFPU2-NEXT: blr
entry: entry:
Show All 18 Lines
; SPE-NEXT: stw 3, 12(1) ; SPE-NEXT: stw 3, 12(1)
; SPE-NEXT: lwz 3, 12(1) ; SPE-NEXT: lwz 3, 12(1)
; SPE-NEXT: addi 1, 1, 16 ; SPE-NEXT: addi 1, 1, 16
; SPE-NEXT: blr ; SPE-NEXT: blr
; ;
; EFPU2-LABEL: test_dcmpgt: ; EFPU2-LABEL: test_dcmpgt:
; EFPU2: # %bb.0: # %entry ; EFPU2: # %bb.0: # %entry
; EFPU2-NEXT: mflr 0 ; EFPU2-NEXT: mflr 0
; EFPU2-NEXT: stw 0, 4(1)
; EFPU2-NEXT: stwu 1, -16(1) ; EFPU2-NEXT: stwu 1, -16(1)
; EFPU2-NEXT: stw 0, 20(1)
; EFPU2-NEXT: bl __gtdf2 ; EFPU2-NEXT: bl __gtdf2
; EFPU2-NEXT: cmpwi 3, 0 ; EFPU2-NEXT: cmpwi 3, 0
; EFPU2-NEXT: ble 0, .LBB37_2 ; EFPU2-NEXT: ble 0, .LBB37_2
; EFPU2-NEXT: # %bb.1: # %tr ; EFPU2-NEXT: # %bb.1: # %tr
; EFPU2-NEXT: li 3, 1 ; EFPU2-NEXT: li 3, 1
; EFPU2-NEXT: b .LBB37_3 ; EFPU2-NEXT: b .LBB37_3
; EFPU2-NEXT: .LBB37_2: # %fa ; EFPU2-NEXT: .LBB37_2: # %fa
; EFPU2-NEXT: li 3, 0 ; EFPU2-NEXT: li 3, 0
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
; SPE-NEXT: stw 3, 12(1) ; SPE-NEXT: stw 3, 12(1)
; SPE-NEXT: lwz 3, 12(1) ; SPE-NEXT: lwz 3, 12(1)
; SPE-NEXT: addi 1, 1, 16 ; SPE-NEXT: addi 1, 1, 16
; SPE-NEXT: blr ; SPE-NEXT: blr
; ;
; EFPU2-LABEL: test_dcmpugt: ; EFPU2-LABEL: test_dcmpugt:
; EFPU2: # %bb.0: # %entry ; EFPU2: # %bb.0: # %entry
; EFPU2-NEXT: mflr 0 ; EFPU2-NEXT: mflr 0
; EFPU2-NEXT: stw 0, 4(1)
; EFPU2-NEXT: stwu 1, -16(1) ; EFPU2-NEXT: stwu 1, -16(1)
; EFPU2-NEXT: stw 0, 20(1)
; EFPU2-NEXT: bl __ledf2 ; EFPU2-NEXT: bl __ledf2
; EFPU2-NEXT: cmpwi 3, 0 ; EFPU2-NEXT: cmpwi 3, 0
; EFPU2-NEXT: ble 0, .LBB38_2 ; EFPU2-NEXT: ble 0, .LBB38_2
; EFPU2-NEXT: # %bb.1: # %tr ; EFPU2-NEXT: # %bb.1: # %tr
; EFPU2-NEXT: li 3, 1 ; EFPU2-NEXT: li 3, 1
; EFPU2-NEXT: b .LBB38_3 ; EFPU2-NEXT: b .LBB38_3
; EFPU2-NEXT: .LBB38_2: # %fa ; EFPU2-NEXT: .LBB38_2: # %fa
; EFPU2-NEXT: li 3, 0 ; EFPU2-NEXT: li 3, 0
Show All 36 Lines
; SPE-NEXT: stw 3, 12(1) ; SPE-NEXT: stw 3, 12(1)
; SPE-NEXT: lwz 3, 12(1) ; SPE-NEXT: lwz 3, 12(1)
; SPE-NEXT: addi 1, 1, 16 ; SPE-NEXT: addi 1, 1, 16
; SPE-NEXT: blr ; SPE-NEXT: blr
; ;
; EFPU2-LABEL: test_dcmple: ; EFPU2-LABEL: test_dcmple:
; EFPU2: # %bb.0: # %entry ; EFPU2: # %bb.0: # %entry
; EFPU2-NEXT: mflr 0 ; EFPU2-NEXT: mflr 0
; EFPU2-NEXT: stw 0, 4(1)
; EFPU2-NEXT: stwu 1, -16(1) ; EFPU2-NEXT: stwu 1, -16(1)
; EFPU2-NEXT: stw 0, 20(1)
; EFPU2-NEXT: bl __gtdf2 ; EFPU2-NEXT: bl __gtdf2
; EFPU2-NEXT: cmpwi 3, 0 ; EFPU2-NEXT: cmpwi 3, 0
; EFPU2-NEXT: bgt 0, .LBB39_2 ; EFPU2-NEXT: bgt 0, .LBB39_2
; EFPU2-NEXT: # %bb.1: # %tr ; EFPU2-NEXT: # %bb.1: # %tr
; EFPU2-NEXT: li 3, 1 ; EFPU2-NEXT: li 3, 1
; EFPU2-NEXT: b .LBB39_3 ; EFPU2-NEXT: b .LBB39_3
; EFPU2-NEXT: .LBB39_2: # %fa ; EFPU2-NEXT: .LBB39_2: # %fa
; EFPU2-NEXT: li 3, 0 ; EFPU2-NEXT: li 3, 0
Show All 36 Lines
; SPE-NEXT: stw 3, 12(1) ; SPE-NEXT: stw 3, 12(1)
; SPE-NEXT: lwz 3, 12(1) ; SPE-NEXT: lwz 3, 12(1)
; SPE-NEXT: addi 1, 1, 16 ; SPE-NEXT: addi 1, 1, 16
; SPE-NEXT: blr ; SPE-NEXT: blr
; ;
; EFPU2-LABEL: test_dcmpule: ; EFPU2-LABEL: test_dcmpule:
; EFPU2: # %bb.0: # %entry ; EFPU2: # %bb.0: # %entry
; EFPU2-NEXT: mflr 0 ; EFPU2-NEXT: mflr 0
; EFPU2-NEXT: stw 0, 4(1)
; EFPU2-NEXT: stwu 1, -16(1) ; EFPU2-NEXT: stwu 1, -16(1)
; EFPU2-NEXT: stw 0, 20(1)
; EFPU2-NEXT: bl __gtdf2 ; EFPU2-NEXT: bl __gtdf2
; EFPU2-NEXT: cmpwi 3, 0 ; EFPU2-NEXT: cmpwi 3, 0
; EFPU2-NEXT: bgt 0, .LBB40_2 ; EFPU2-NEXT: bgt 0, .LBB40_2
; EFPU2-NEXT: # %bb.1: # %tr ; EFPU2-NEXT: # %bb.1: # %tr
; EFPU2-NEXT: li 3, 1 ; EFPU2-NEXT: li 3, 1
; EFPU2-NEXT: b .LBB40_3 ; EFPU2-NEXT: b .LBB40_3
; EFPU2-NEXT: .LBB40_2: # %fa ; EFPU2-NEXT: .LBB40_2: # %fa
; EFPU2-NEXT: li 3, 0 ; EFPU2-NEXT: li 3, 0
Show All 37 Lines
; SPE-NEXT: stw 3, 12(1) ; SPE-NEXT: stw 3, 12(1)
; SPE-NEXT: lwz 3, 12(1) ; SPE-NEXT: lwz 3, 12(1)
; SPE-NEXT: addi 1, 1, 16 ; SPE-NEXT: addi 1, 1, 16
; SPE-NEXT: blr ; SPE-NEXT: blr
; ;
; EFPU2-LABEL: test_dcmpeq: ; EFPU2-LABEL: test_dcmpeq:
; EFPU2: # %bb.0: # %entry ; EFPU2: # %bb.0: # %entry
; EFPU2-NEXT: mflr 0 ; EFPU2-NEXT: mflr 0
; EFPU2-NEXT: stw 0, 4(1)
; EFPU2-NEXT: stwu 1, -16(1) ; EFPU2-NEXT: stwu 1, -16(1)
; EFPU2-NEXT: stw 0, 20(1)
; EFPU2-NEXT: bl __nedf2 ; EFPU2-NEXT: bl __nedf2
; EFPU2-NEXT: cmplwi 3, 0 ; EFPU2-NEXT: cmplwi 3, 0
; EFPU2-NEXT: bne 0, .LBB41_2 ; EFPU2-NEXT: bne 0, .LBB41_2
; EFPU2-NEXT: # %bb.1: # %tr ; EFPU2-NEXT: # %bb.1: # %tr
; EFPU2-NEXT: li 3, 1 ; EFPU2-NEXT: li 3, 1
; EFPU2-NEXT: b .LBB41_3 ; EFPU2-NEXT: b .LBB41_3
; EFPU2-NEXT: .LBB41_2: # %fa ; EFPU2-NEXT: .LBB41_2: # %fa
; EFPU2-NEXT: li 3, 0 ; EFPU2-NEXT: li 3, 0
Show All 39 Lines
; SPE-NEXT: stw 3, 12(1) ; SPE-NEXT: stw 3, 12(1)
; SPE-NEXT: lwz 3, 12(1) ; SPE-NEXT: lwz 3, 12(1)
; SPE-NEXT: addi 1, 1, 16 ; SPE-NEXT: addi 1, 1, 16
; SPE-NEXT: blr ; SPE-NEXT: blr
; ;
; EFPU2-LABEL: test_dcmpueq: ; EFPU2-LABEL: test_dcmpueq:
; EFPU2: # %bb.0: # %entry ; EFPU2: # %bb.0: # %entry
; EFPU2-NEXT: mflr 0 ; EFPU2-NEXT: mflr 0
; EFPU2-NEXT: stw 0, 4(1)
; EFPU2-NEXT: stwu 1, -80(1) ; EFPU2-NEXT: stwu 1, -80(1)
; EFPU2-NEXT: mfcr 12 ; EFPU2-NEXT: mfcr 12
; EFPU2-NEXT: stw 0, 84(1)
; EFPU2-NEXT: stw 12, 76(1) ; EFPU2-NEXT: stw 12, 76(1)
; EFPU2-NEXT: evstdd 27, 24(1) # 8-byte Folded Spill ; EFPU2-NEXT: evstdd 27, 24(1) # 8-byte Folded Spill
; EFPU2-NEXT: mr 27, 3 ; EFPU2-NEXT: mr 27, 3
; EFPU2-NEXT: evstdd 28, 32(1) # 8-byte Folded Spill ; EFPU2-NEXT: evstdd 28, 32(1) # 8-byte Folded Spill
; EFPU2-NEXT: mr 28, 4 ; EFPU2-NEXT: mr 28, 4
; EFPU2-NEXT: evstdd 29, 40(1) # 8-byte Folded Spill ; EFPU2-NEXT: evstdd 29, 40(1) # 8-byte Folded Spill
; EFPU2-NEXT: mr 29, 5 ; EFPU2-NEXT: mr 29, 5
; EFPU2-NEXT: evstdd 30, 48(1) # 8-byte Folded Spill ; EFPU2-NEXT: evstdd 30, 48(1) # 8-byte Folded Spill
▲ Show 20 Lines • Show All 57 Lines • ▼ Show 20 Lines
; SPE-NEXT: blr ; SPE-NEXT: blr
; SPE-NEXT: .LBB43_2: # %entry ; SPE-NEXT: .LBB43_2: # %entry
; SPE-NEXT: li 3, 0 ; SPE-NEXT: li 3, 0
; SPE-NEXT: blr ; SPE-NEXT: blr
; ;
; EFPU2-LABEL: test_dcmpne: ; EFPU2-LABEL: test_dcmpne:
; EFPU2: # %bb.0: # %entry ; EFPU2: # %bb.0: # %entry
; EFPU2-NEXT: mflr 0 ; EFPU2-NEXT: mflr 0
; EFPU2-NEXT: stw 0, 4(1)
; EFPU2-NEXT: stwu 1, -80(1) ; EFPU2-NEXT: stwu 1, -80(1)
; EFPU2-NEXT: mfcr 12 ; EFPU2-NEXT: mfcr 12
; EFPU2-NEXT: stw 0, 84(1)
; EFPU2-NEXT: stw 12, 76(1) ; EFPU2-NEXT: stw 12, 76(1)
; EFPU2-NEXT: evstdd 27, 24(1) # 8-byte Folded Spill ; EFPU2-NEXT: evstdd 27, 24(1) # 8-byte Folded Spill
; EFPU2-NEXT: mr 27, 3 ; EFPU2-NEXT: mr 27, 3
; EFPU2-NEXT: evstdd 28, 32(1) # 8-byte Folded Spill ; EFPU2-NEXT: evstdd 28, 32(1) # 8-byte Folded Spill
; EFPU2-NEXT: mr 28, 4 ; EFPU2-NEXT: mr 28, 4
; EFPU2-NEXT: evstdd 29, 40(1) # 8-byte Folded Spill ; EFPU2-NEXT: evstdd 29, 40(1) # 8-byte Folded Spill
; EFPU2-NEXT: mr 29, 5 ; EFPU2-NEXT: mr 29, 5
; EFPU2-NEXT: evstdd 30, 48(1) # 8-byte Folded Spill ; EFPU2-NEXT: evstdd 30, 48(1) # 8-byte Folded Spill
▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
; SPE-NEXT: stw 3, 12(1) ; SPE-NEXT: stw 3, 12(1)
; SPE-NEXT: lwz 3, 12(1) ; SPE-NEXT: lwz 3, 12(1)
; SPE-NEXT: addi 1, 1, 16 ; SPE-NEXT: addi 1, 1, 16
; SPE-NEXT: blr ; SPE-NEXT: blr
; ;
; EFPU2-LABEL: test_dcmpune: ; EFPU2-LABEL: test_dcmpune:
; EFPU2: # %bb.0: # %entry ; EFPU2: # %bb.0: # %entry
; EFPU2-NEXT: mflr 0 ; EFPU2-NEXT: mflr 0
; EFPU2-NEXT: stw 0, 4(1)
; EFPU2-NEXT: stwu 1, -16(1) ; EFPU2-NEXT: stwu 1, -16(1)
; EFPU2-NEXT: stw 0, 20(1)
; EFPU2-NEXT: bl __eqdf2 ; EFPU2-NEXT: bl __eqdf2
; EFPU2-NEXT: cmplwi 3, 0 ; EFPU2-NEXT: cmplwi 3, 0
; EFPU2-NEXT: beq 0, .LBB44_2 ; EFPU2-NEXT: beq 0, .LBB44_2
; EFPU2-NEXT: # %bb.1: # %tr ; EFPU2-NEXT: # %bb.1: # %tr
; EFPU2-NEXT: li 3, 1 ; EFPU2-NEXT: li 3, 1
; EFPU2-NEXT: b .LBB44_3 ; EFPU2-NEXT: b .LBB44_3
; EFPU2-NEXT: .LBB44_2: # %fa ; EFPU2-NEXT: .LBB44_2: # %fa
; EFPU2-NEXT: li 3, 0 ; EFPU2-NEXT: li 3, 0
Show All 36 Lines
; SPE-NEXT: stw 3, 12(1) ; SPE-NEXT: stw 3, 12(1)
; SPE-NEXT: lwz 3, 12(1) ; SPE-NEXT: lwz 3, 12(1)
; SPE-NEXT: addi 1, 1, 16 ; SPE-NEXT: addi 1, 1, 16
; SPE-NEXT: blr ; SPE-NEXT: blr
; ;
; EFPU2-LABEL: test_dcmplt: ; EFPU2-LABEL: test_dcmplt:
; EFPU2: # %bb.0: # %entry ; EFPU2: # %bb.0: # %entry
; EFPU2-NEXT: mflr 0 ; EFPU2-NEXT: mflr 0
; EFPU2-NEXT: stw 0, 4(1)
; EFPU2-NEXT: stwu 1, -16(1) ; EFPU2-NEXT: stwu 1, -16(1)
; EFPU2-NEXT: stw 0, 20(1)
; EFPU2-NEXT: bl __ltdf2 ; EFPU2-NEXT: bl __ltdf2
; EFPU2-NEXT: cmpwi 3, 0 ; EFPU2-NEXT: cmpwi 3, 0
; EFPU2-NEXT: bge 0, .LBB45_2 ; EFPU2-NEXT: bge 0, .LBB45_2
; EFPU2-NEXT: # %bb.1: # %tr ; EFPU2-NEXT: # %bb.1: # %tr
; EFPU2-NEXT: li 3, 1 ; EFPU2-NEXT: li 3, 1
; EFPU2-NEXT: b .LBB45_3 ; EFPU2-NEXT: b .LBB45_3
; EFPU2-NEXT: .LBB45_2: # %fa ; EFPU2-NEXT: .LBB45_2: # %fa
; EFPU2-NEXT: li 3, 0 ; EFPU2-NEXT: li 3, 0
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
; SPE-NEXT: stw 3, 12(1) ; SPE-NEXT: stw 3, 12(1)
; SPE-NEXT: lwz 3, 12(1) ; SPE-NEXT: lwz 3, 12(1)
; SPE-NEXT: addi 1, 1, 16 ; SPE-NEXT: addi 1, 1, 16
; SPE-NEXT: blr ; SPE-NEXT: blr
; ;
; EFPU2-LABEL: test_dcmpult: ; EFPU2-LABEL: test_dcmpult:
; EFPU2: # %bb.0: # %entry ; EFPU2: # %bb.0: # %entry
; EFPU2-NEXT: mflr 0 ; EFPU2-NEXT: mflr 0
; EFPU2-NEXT: stw 0, 4(1)
; EFPU2-NEXT: stwu 1, -16(1) ; EFPU2-NEXT: stwu 1, -16(1)
; EFPU2-NEXT: stw 0, 20(1)
; EFPU2-NEXT: bl __gedf2 ; EFPU2-NEXT: bl __gedf2
; EFPU2-NEXT: cmpwi 3, 0 ; EFPU2-NEXT: cmpwi 3, 0
; EFPU2-NEXT: bge 0, .LBB46_2 ; EFPU2-NEXT: bge 0, .LBB46_2
; EFPU2-NEXT: # %bb.1: # %tr ; EFPU2-NEXT: # %bb.1: # %tr
; EFPU2-NEXT: li 3, 1 ; EFPU2-NEXT: li 3, 1
; EFPU2-NEXT: b .LBB46_3 ; EFPU2-NEXT: b .LBB46_3
; EFPU2-NEXT: .LBB46_2: # %fa ; EFPU2-NEXT: .LBB46_2: # %fa
; EFPU2-NEXT: li 3, 0 ; EFPU2-NEXT: li 3, 0
Show All 36 Lines
; SPE-NEXT: blr ; SPE-NEXT: blr
; SPE-NEXT: .LBB47_2: # %entry ; SPE-NEXT: .LBB47_2: # %entry
; SPE-NEXT: li 3, 0 ; SPE-NEXT: li 3, 0
; SPE-NEXT: blr ; SPE-NEXT: blr
; ;
; EFPU2-LABEL: test_dcmpge: ; EFPU2-LABEL: test_dcmpge:
; EFPU2: # %bb.0: # %entry ; EFPU2: # %bb.0: # %entry
; EFPU2-NEXT: mflr 0 ; EFPU2-NEXT: mflr 0
; EFPU2-NEXT: stw 0, 4(1)
; EFPU2-NEXT: stwu 1, -16(1) ; EFPU2-NEXT: stwu 1, -16(1)
; EFPU2-NEXT: stw 0, 20(1)
; EFPU2-NEXT: bl __gedf2 ; EFPU2-NEXT: bl __gedf2
; EFPU2-NEXT: not 3, 3 ; EFPU2-NEXT: not 3, 3
; EFPU2-NEXT: srwi 3, 3, 31 ; EFPU2-NEXT: srwi 3, 3, 31
; EFPU2-NEXT: lwz 0, 20(1) ; EFPU2-NEXT: lwz 0, 20(1)
; EFPU2-NEXT: addi 1, 1, 16 ; EFPU2-NEXT: addi 1, 1, 16
; EFPU2-NEXT: mtlr 0 ; EFPU2-NEXT: mtlr 0
; EFPU2-NEXT: blr ; EFPU2-NEXT: blr
entry: entry:
Show All 18 Lines
; SPE-NEXT: stw 3, 12(1) ; SPE-NEXT: stw 3, 12(1)
; SPE-NEXT: lwz 3, 12(1) ; SPE-NEXT: lwz 3, 12(1)
; SPE-NEXT: addi 1, 1, 16 ; SPE-NEXT: addi 1, 1, 16
; SPE-NEXT: blr ; SPE-NEXT: blr
; ;
; EFPU2-LABEL: test_dcmpuge: ; EFPU2-LABEL: test_dcmpuge:
; EFPU2: # %bb.0: # %entry ; EFPU2: # %bb.0: # %entry
; EFPU2-NEXT: mflr 0 ; EFPU2-NEXT: mflr 0
; EFPU2-NEXT: stw 0, 4(1)
; EFPU2-NEXT: stwu 1, -16(1) ; EFPU2-NEXT: stwu 1, -16(1)
; EFPU2-NEXT: stw 0, 20(1)
; EFPU2-NEXT: bl __ltdf2 ; EFPU2-NEXT: bl __ltdf2
; EFPU2-NEXT: cmpwi 3, 0 ; EFPU2-NEXT: cmpwi 3, 0
; EFPU2-NEXT: blt 0, .LBB48_2 ; EFPU2-NEXT: blt 0, .LBB48_2
; EFPU2-NEXT: # %bb.1: # %tr ; EFPU2-NEXT: # %bb.1: # %tr
; EFPU2-NEXT: li 3, 1 ; EFPU2-NEXT: li 3, 1
; EFPU2-NEXT: b .LBB48_3 ; EFPU2-NEXT: b .LBB48_3
; EFPU2-NEXT: .LBB48_2: # %fa ; EFPU2-NEXT: .LBB48_2: # %fa
; EFPU2-NEXT: li 3, 0 ; EFPU2-NEXT: li 3, 0
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Lines
; SPE: # %bb.0: # %entry ; SPE: # %bb.0: # %entry
; SPE-NEXT: evmergelo 3, 3, 4 ; SPE-NEXT: evmergelo 3, 3, 4
; SPE-NEXT: efdctuiz 3, 3 ; SPE-NEXT: efdctuiz 3, 3
; SPE-NEXT: blr ; SPE-NEXT: blr
; ;
; EFPU2-LABEL: test_dtoui: ; EFPU2-LABEL: test_dtoui:
; EFPU2: # %bb.0: # %entry ; EFPU2: # %bb.0: # %entry
; EFPU2-NEXT: mflr 0 ; EFPU2-NEXT: mflr 0
; EFPU2-NEXT: stw 0, 4(1)
; EFPU2-NEXT: stwu 1, -16(1) ; EFPU2-NEXT: stwu 1, -16(1)
; EFPU2-NEXT: stw 0, 20(1)
; EFPU2-NEXT: bl __fixunsdfsi ; EFPU2-NEXT: bl __fixunsdfsi
; EFPU2-NEXT: lwz 0, 20(1) ; EFPU2-NEXT: lwz 0, 20(1)
; EFPU2-NEXT: addi 1, 1, 16 ; EFPU2-NEXT: addi 1, 1, 16
; EFPU2-NEXT: mtlr 0 ; EFPU2-NEXT: mtlr 0
; EFPU2-NEXT: blr ; EFPU2-NEXT: blr
entry: entry:
%v = fptoui double %a to i32 %v = fptoui double %a to i32
ret i32 %v ret i32 %v
} }
define i32 @test_dtosi(double %a) #0 { define i32 @test_dtosi(double %a) #0 {
; SPE-LABEL: test_dtosi: ; SPE-LABEL: test_dtosi:
; SPE: # %bb.0: # %entry ; SPE: # %bb.0: # %entry
; SPE-NEXT: evmergelo 3, 3, 4 ; SPE-NEXT: evmergelo 3, 3, 4
; SPE-NEXT: efdctsiz 3, 3 ; SPE-NEXT: efdctsiz 3, 3
; SPE-NEXT: blr ; SPE-NEXT: blr
; ;
; EFPU2-LABEL: test_dtosi: ; EFPU2-LABEL: test_dtosi:
; EFPU2: # %bb.0: # %entry ; EFPU2: # %bb.0: # %entry
; EFPU2-NEXT: mflr 0 ; EFPU2-NEXT: mflr 0
; EFPU2-NEXT: stw 0, 4(1)
; EFPU2-NEXT: stwu 1, -16(1) ; EFPU2-NEXT: stwu 1, -16(1)
; EFPU2-NEXT: stw 0, 20(1)
; EFPU2-NEXT: bl __fixdfsi ; EFPU2-NEXT: bl __fixdfsi
; EFPU2-NEXT: lwz 0, 20(1) ; EFPU2-NEXT: lwz 0, 20(1)
; EFPU2-NEXT: addi 1, 1, 16 ; EFPU2-NEXT: addi 1, 1, 16
; EFPU2-NEXT: mtlr 0 ; EFPU2-NEXT: mtlr 0
; EFPU2-NEXT: blr ; EFPU2-NEXT: blr
entry: entry:
%v = fptosi double %a to i32 %v = fptosi double %a to i32
ret i32 %v ret i32 %v
} }
define double @test_dfromui(i32 %a) #0 { define double @test_dfromui(i32 %a) #0 {
; SPE-LABEL: test_dfromui: ; SPE-LABEL: test_dfromui:
; SPE: # %bb.0: # %entry ; SPE: # %bb.0: # %entry
; SPE-NEXT: efdcfui 4, 3 ; SPE-NEXT: efdcfui 4, 3
; SPE-NEXT: evmergehi 3, 4, 4 ; SPE-NEXT: evmergehi 3, 4, 4
; SPE-NEXT: # kill: def $r4 killed $r4 killed $s4 ; SPE-NEXT: # kill: def $r4 killed $r4 killed $s4
; SPE-NEXT: # kill: def $r3 killed $r3 killed $s3 ; SPE-NEXT: # kill: def $r3 killed $r3 killed $s3
; SPE-NEXT: blr ; SPE-NEXT: blr
; ;
; EFPU2-LABEL: test_dfromui: ; EFPU2-LABEL: test_dfromui:
; EFPU2: # %bb.0: # %entry ; EFPU2: # %bb.0: # %entry
; EFPU2-NEXT: mflr 0 ; EFPU2-NEXT: mflr 0
; EFPU2-NEXT: stw 0, 4(1)
; EFPU2-NEXT: stwu 1, -16(1) ; EFPU2-NEXT: stwu 1, -16(1)
; EFPU2-NEXT: stw 0, 20(1)
; EFPU2-NEXT: bl __floatunsidf ; EFPU2-NEXT: bl __floatunsidf
; EFPU2-NEXT: lwz 0, 20(1) ; EFPU2-NEXT: lwz 0, 20(1)
; EFPU2-NEXT: addi 1, 1, 16 ; EFPU2-NEXT: addi 1, 1, 16
; EFPU2-NEXT: mtlr 0 ; EFPU2-NEXT: mtlr 0
; EFPU2-NEXT: blr ; EFPU2-NEXT: blr
entry: entry:
%v = uitofp i32 %a to double %v = uitofp i32 %a to double
ret double %v ret double %v
} }
define double @test_dfromsi(i32 %a) #0 { define double @test_dfromsi(i32 %a) #0 {
; SPE-LABEL: test_dfromsi: ; SPE-LABEL: test_dfromsi:
; SPE: # %bb.0: # %entry ; SPE: # %bb.0: # %entry
; SPE-NEXT: efdcfsi 4, 3 ; SPE-NEXT: efdcfsi 4, 3
; SPE-NEXT: evmergehi 3, 4, 4 ; SPE-NEXT: evmergehi 3, 4, 4
; SPE-NEXT: # kill: def $r4 killed $r4 killed $s4 ; SPE-NEXT: # kill: def $r4 killed $r4 killed $s4
; SPE-NEXT: # kill: def $r3 killed $r3 killed $s3 ; SPE-NEXT: # kill: def $r3 killed $r3 killed $s3
; SPE-NEXT: blr ; SPE-NEXT: blr
; ;
; EFPU2-LABEL: test_dfromsi: ; EFPU2-LABEL: test_dfromsi:
; EFPU2: # %bb.0: # %entry ; EFPU2: # %bb.0: # %entry
; EFPU2-NEXT: mflr 0 ; EFPU2-NEXT: mflr 0
; EFPU2-NEXT: stw 0, 4(1)
; EFPU2-NEXT: stwu 1, -16(1) ; EFPU2-NEXT: stwu 1, -16(1)
; EFPU2-NEXT: stw 0, 20(1)
; EFPU2-NEXT: bl __floatsidf ; EFPU2-NEXT: bl __floatsidf
; EFPU2-NEXT: lwz 0, 20(1) ; EFPU2-NEXT: lwz 0, 20(1)
; EFPU2-NEXT: addi 1, 1, 16 ; EFPU2-NEXT: addi 1, 1, 16
; EFPU2-NEXT: mtlr 0 ; EFPU2-NEXT: mtlr 0
; EFPU2-NEXT: blr ; EFPU2-NEXT: blr
entry: entry:
%v = sitofp i32 %a to double %v = sitofp i32 %a to double
ret double %v ret double %v
Show All 9 Lines
} }
declare void @test_memset(ptr nocapture writeonly, i8, i32, i1) declare void @test_memset(ptr nocapture writeonly, i8, i32, i1)
@global_var1 = global i32 0, align 4 @global_var1 = global i32 0, align 4
define double @test_spill(double %a, i32 %a1, i64 %a2, ptr %a3, ptr %a4, ptr %a5) #0 { define double @test_spill(double %a, i32 %a1, i64 %a2, ptr %a3, ptr %a4, ptr %a5) #0 {
; SPE-LABEL: test_spill: ; SPE-LABEL: test_spill:
; SPE: # %bb.0: # %entry ; SPE: # %bb.0: # %entry
; SPE-NEXT: mflr 0 ; SPE-NEXT: mflr 0
; SPE-NEXT: stw 0, 4(1)
; SPE-NEXT: stwu 1, -288(1) ; SPE-NEXT: stwu 1, -288(1)
; SPE-NEXT: li 5, 256 ; SPE-NEXT: li 5, 256
; SPE-NEXT: evstddx 30, 1, 5 # 8-byte Folded Spill ; SPE-NEXT: stw 0, 292(1)
; SPE-NEXT: li 5, .LCPI55_0@
; SPE-NEXT: lis 6, .LCPI55_0@ha ; SPE-NEXT: lis 6, .LCPI55_0@ha
; SPE-NEXT: evstddx 30, 1, 5 # 8-byte Folded Spill
; SPE-NEXT: li 5, .LCPI55_0@l
; SPE-NEXT: evlddx 5, 6, 5 ; SPE-NEXT: evlddx 5, 6, 5
; SPE-NEXT: stw 31, 284(1) # 4-byte Folded Spill ; SPE-NEXT: stw 31, 284(1) # 4-byte Folded Spill
; SPE-NEXT: evstdd 14, 128(1) # 8-byte Folded Spill ; SPE-NEXT: evstdd 14, 128(1) # 8-byte Folded Spill
; SPE-NEXT: evstdd 15, 136(1) # 8-byte Folded Spill ; SPE-NEXT: evstdd 15, 136(1) # 8-byte Folded Spill
; SPE-NEXT: evstdd 16, 144(1) # 8-byte Folded Spill ; SPE-NEXT: evstdd 16, 144(1) # 8-byte Folded Spill
; SPE-NEXT: evstdd 17, 152(1) # 8-byte Folded Spill ; SPE-NEXT: evstdd 17, 152(1) # 8-byte Folded Spill
; SPE-NEXT: evstdd 18, 160(1) # 8-byte Folded Spill ; SPE-NEXT: evstdd 18, 160(1) # 8-byte Folded Spill
; SPE-NEXT: evstdd 19, 168(1) # 8-byte Folded Spill ; SPE-NEXT: evstdd 19, 168(1) # 8-byte Folded Spill
; SPE-NEXT: evstdd 20, 176(1) # 8-byte Folded Spill ; SPE-NEXT: evstdd 20, 176(1) # 8-byte Folded Spill
; SPE-NEXT: evstdd 21, 184(1) # 8-byte Folded Spill ; SPE-NEXT: evstdd 21, 184(1) # 8-byte Folded Spill
▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
; SPE-NEXT: evldd 21, 184(1) # 8-byte Folded Reload ; SPE-NEXT: evldd 21, 184(1) # 8-byte Folded Reload
; SPE-NEXT: evldd 20, 176(1) # 8-byte Folded Reload ; SPE-NEXT: evldd 20, 176(1) # 8-byte Folded Reload
; SPE-NEXT: evldd 19, 168(1) # 8-byte Folded Reload ; SPE-NEXT: evldd 19, 168(1) # 8-byte Folded Reload
; SPE-NEXT: evldd 18, 160(1) # 8-byte Folded Reload ; SPE-NEXT: evldd 18, 160(1) # 8-byte Folded Reload
; SPE-NEXT: evldd 17, 152(1) # 8-byte Folded Reload ; SPE-NEXT: evldd 17, 152(1) # 8-byte Folded Reload
; SPE-NEXT: evldd 16, 144(1) # 8-byte Folded Reload ; SPE-NEXT: evldd 16, 144(1) # 8-byte Folded Reload
; SPE-NEXT: evldd 15, 136(1) # 8-byte Folded Reload ; SPE-NEXT: evldd 15, 136(1) # 8-byte Folded Reload
; SPE-NEXT: evldd 14, 128(1) # 8-byte Folded Reload ; SPE-NEXT: evldd 14, 128(1) # 8-byte Folded Reload
; SPE-NEXT: lwz 31, 284(1) # 4-byte Folded Reload ; SPE-NEXT: lwz 31, 284(1) # 4-byte Folded Reload
; SPE-NEXT: lwz 0, 292(1) ; SPE-NEXT: lwz 0, 292(1)
; SPE-NEXT: addi 1, 1, 288 ; SPE-NEXT: addi 1, 1, 288
; SPE-NEXT: mtlr 0 ; SPE-NEXT: mtlr 0
; SPE-NEXT: blr ; SPE-NEXT: blr
; ;
; EFPU2-LABEL: test_spill: ; EFPU2-LABEL: test_spill:
; EFPU2: # %bb.0: # %entry ; EFPU2: # %bb.0: # %entry
; EFPU2-NEXT: mflr 0 ; EFPU2-NEXT: mflr 0
; EFPU2-NEXT: stw 0, 4(1)
; EFPU2-NEXT: stwu 1, -144(1) ; EFPU2-NEXT: stwu 1, -144(1)
; EFPU2-NEXT: mr 5, 3 ; EFPU2-NEXT: mr 5, 3
; EFPU2-NEXT: mr 6, 4 ; EFPU2-NEXT: mr 6, 4
; EFPU2-NEXT: stw 0, 148(1)
; EFPU2-NEXT: evstdd 27, 104(1) # 8-byte Folded Spill ; EFPU2-NEXT: evstdd 27, 104(1) # 8-byte Folded Spill
; EFPU2-NEXT: evstdd 28, 112(1) # 8-byte Folded Spill ; EFPU2-NEXT: evstdd 28, 112(1) # 8-byte Folded Spill
; EFPU2-NEXT: evstdd 29, 120(1) # 8-byte Folded Spill ; EFPU2-NEXT: evstdd 29, 120(1) # 8-byte Folded Spill
; EFPU2-NEXT: evstdd 30, 128(1) # 8-byte Folded Spill ; EFPU2-NEXT: evstdd 30, 128(1) # 8-byte Folded Spill
; EFPU2-NEXT: lwz 28, 152(1) ; EFPU2-NEXT: lwz 28, 152(1)
; EFPU2-NEXT: bl __adddf3 ; EFPU2-NEXT: bl __adddf3
; EFPU2-NEXT: lis 5, 16393 ; EFPU2-NEXT: lis 5, 16393
; EFPU2-NEXT: lis 6, -4069 ; EFPU2-NEXT: lis 6, -4069
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Linesreturn:
ret double %1 ret double %1
} }
define dso_local float @test_fma(i32 %d) local_unnamed_addr #0 { define dso_local float @test_fma(i32 %d) local_unnamed_addr #0 {
; CHECK-LABEL: test_fma: ; CHECK-LABEL: test_fma:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; CHECK-NEXT: stw 0, 4(1)
; CHECK-NEXT: stwu 1, -32(1) ; CHECK-NEXT: stwu 1, -32(1)
; CHECK-NEXT: cmpwi 3, 0 ; CHECK-NEXT: cmpwi 3, 0
; CHECK-NEXT: stw 0, 36(1)
; CHECK-NEXT: evstdd 29, 8(1) # 8-byte Folded Spill ; CHECK-NEXT: evstdd 29, 8(1) # 8-byte Folded Spill
; CHECK-NEXT: evstdd 30, 16(1) # 8-byte Folded Spill ; CHECK-NEXT: evstdd 30, 16(1) # 8-byte Folded Spill
; CHECK-NEXT: ble 0, .LBB56_3 ; CHECK-NEXT: ble 0, .LBB56_3
; CHECK-NEXT: # %bb.1: # %for.body.preheader ; CHECK-NEXT: # %bb.1: # %for.body.preheader
; CHECK-NEXT: mr 30, 3 ; CHECK-NEXT: mr 30, 3
; CHECK-NEXT: li 29, 0 ; CHECK-NEXT: li 29, 0
; CHECK-NEXT: # implicit-def: $r5 ; CHECK-NEXT: # implicit-def: $r5
; CHECK-NEXT: .LBB56_2: # %for.body ; CHECK-NEXT: .LBB56_2: # %for.body
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
%struct.a = type { float, float } %struct.a = type { float, float }
declare i32 @foo(double) declare i32 @foo(double)
define void @d(ptr %e, ptr %f) #0 { define void @d(ptr %e, ptr %f) #0 {
; SPE-LABEL: d: ; SPE-LABEL: d:
; SPE: # %bb.0: # %entry ; SPE: # %bb.0: # %entry
; SPE-NEXT: mflr 0 ; SPE-NEXT: mflr 0
; SPE-NEXT: stw 0, 4(1)
; SPE-NEXT: stwu 1, -48(1) ; SPE-NEXT: stwu 1, -48(1)
; SPE-NEXT: stw 0, 52(1)
; SPE-NEXT: lwz 4, 0(4) ; SPE-NEXT: lwz 4, 0(4)
; SPE-NEXT: lwz 3, 0(3) ; SPE-NEXT: lwz 3, 0(3)
; SPE-NEXT: evstdd 29, 24(1) # 8-byte Folded Spill ; SPE-NEXT: evstdd 29, 24(1) # 8-byte Folded Spill
; SPE-NEXT: efdcfs 29, 4 ; SPE-NEXT: efdcfs 29, 4
; SPE-NEXT: evstdd 28, 16(1) # 8-byte Folded Spill ; SPE-NEXT: evstdd 28, 16(1) # 8-byte Folded Spill
; SPE-NEXT: mr 4, 29 ; SPE-NEXT: mr 4, 29
; SPE-NEXT: evstdd 30, 32(1) # 8-byte Folded Spill ; SPE-NEXT: evstdd 30, 32(1) # 8-byte Folded Spill
; SPE-NEXT: efdcfs 30, 3 ; SPE-NEXT: efdcfs 30, 3
Show All 15 Lines
; SPE-NEXT: lwz 0, 52(1) ; SPE-NEXT: lwz 0, 52(1)
; SPE-NEXT: addi 1, 1, 48 ; SPE-NEXT: addi 1, 1, 48
; SPE-NEXT: mtlr 0 ; SPE-NEXT: mtlr 0
; SPE-NEXT: blr ; SPE-NEXT: blr
; ;
; EFPU2-LABEL: d: ; EFPU2-LABEL: d:
; EFPU2: # %bb.0: # %entry ; EFPU2: # %bb.0: # %entry
; EFPU2-NEXT: mflr 0 ; EFPU2-NEXT: mflr 0
; EFPU2-NEXT: stw 0, 4(1)
; EFPU2-NEXT: stwu 1, -64(1) ; EFPU2-NEXT: stwu 1, -64(1)
; EFPU2-NEXT: stw 0, 68(1)
; EFPU2-NEXT: lwz 3, 0(3) ; EFPU2-NEXT: lwz 3, 0(3)
; EFPU2-NEXT: evstdd 26, 16(1) # 8-byte Folded Spill ; EFPU2-NEXT: evstdd 26, 16(1) # 8-byte Folded Spill
; EFPU2-NEXT: evstdd 27, 24(1) # 8-byte Folded Spill ; EFPU2-NEXT: evstdd 27, 24(1) # 8-byte Folded Spill
; EFPU2-NEXT: evstdd 28, 32(1) # 8-byte Folded Spill ; EFPU2-NEXT: evstdd 28, 32(1) # 8-byte Folded Spill
; EFPU2-NEXT: evstdd 29, 40(1) # 8-byte Folded Spill ; EFPU2-NEXT: evstdd 29, 40(1) # 8-byte Folded Spill
; EFPU2-NEXT: evstdd 30, 48(1) # 8-byte Folded Spill ; EFPU2-NEXT: evstdd 30, 48(1) # 8-byte Folded Spill
; EFPU2-NEXT: mr 30, 4 ; EFPU2-NEXT: mr 30, 4
; EFPU2-NEXT: bl __extendsfdf2 ; EFPU2-NEXT: bl __extendsfdf2
▲ Show 20 Lines • Show All 43 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/srem-lkk.ll

Show First 20 Lines • Show All 127 Lines • ▼ Show 20 Lines; CHECK-NEXT: blr
ret i32 %1 ret i32 %1
} }
; Don't fold i64 srem ; Don't fold i64 srem
define i64 @dont_fold_srem_i64(i64 %x) { define i64 @dont_fold_srem_i64(i64 %x) {
; CHECK-LABEL: dont_fold_srem_i64: ; CHECK-LABEL: dont_fold_srem_i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; CHECK-NEXT: stw 0, 4(1)
; CHECK-NEXT: stwu 1, -16(1) ; CHECK-NEXT: stwu 1, -16(1)
; CHECK-NEXT: stw 0, 20(1)
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset lr, 4 ; CHECK-NEXT: .cfi_offset lr, 4
; CHECK-NEXT: li 5, 0 ; CHECK-NEXT: li 5, 0
; CHECK-NEXT: li 6, 98 ; CHECK-NEXT: li 6, 98
; CHECK-NEXT: bl __moddi3 ; CHECK-NEXT: bl __moddi3
; CHECK-NEXT: lwz 0, 20(1) ; CHECK-NEXT: lwz 0, 20(1)
; CHECK-NEXT: addi 1, 1, 16 ; CHECK-NEXT: addi 1, 1, 16
; CHECK-NEXT: mtlr 0 ; CHECK-NEXT: mtlr 0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%1 = srem i64 %x, 98 %1 = srem i64 %x, 98
ret i64 %1 ret i64 %1
} }

llvm/test/CodeGen/PowerPC/srem-seteq-illegal-types.ll

Show First 20 Lines • Show All 115 Lines • ▼ Show 20 Lines; PPC64LE-NEXT: blr
%cmp = icmp ne i6 %srem, 0 %cmp = icmp ne i6 %srem, 0
ret i1 %cmp ret i1 %cmp
} }
define <3 x i1> @test_srem_vec(<3 x i33> %X) nounwind { define <3 x i1> @test_srem_vec(<3 x i33> %X) nounwind {
; PPC-LABEL: test_srem_vec: ; PPC-LABEL: test_srem_vec:
; PPC: # %bb.0: ; PPC: # %bb.0:
; PPC-NEXT: mflr 0 ; PPC-NEXT: mflr 0
; PPC-NEXT: stw 0, 4(1)
; PPC-NEXT: stwu 1, -48(1) ; PPC-NEXT: stwu 1, -48(1)
; PPC-NEXT: stw 0, 52(1)
; PPC-NEXT: clrlwi 5, 5, 31
; PPC-NEXT: stw 29, 36(1) # 4-byte Folded Spill ; PPC-NEXT: stw 29, 36(1) # 4-byte Folded Spill
; PPC-NEXT: mr 29, 6 ; PPC-NEXT: mr 29, 6
; PPC-NEXT: clrlwi 5, 5, 31
; PPC-NEXT: clrlwi 6, 7, 31 ; PPC-NEXT: clrlwi 6, 7, 31
; PPC-NEXT: clrlwi 3, 3, 31 ; PPC-NEXT: clrlwi 3, 3, 31
; PPC-NEXT: stw 27, 28(1) # 4-byte Folded Spill ; PPC-NEXT: stw 27, 28(1) # 4-byte Folded Spill
; PPC-NEXT: neg 27, 6 ; PPC-NEXT: neg 27, 6
; PPC-NEXT: stw 28, 32(1) # 4-byte Folded Spill ; PPC-NEXT: stw 28, 32(1) # 4-byte Folded Spill
; PPC-NEXT: neg 28, 5 ; PPC-NEXT: neg 28, 5
; PPC-NEXT: neg 3, 3 ; PPC-NEXT: neg 3, 3
; PPC-NEXT: li 5, 0 ; PPC-NEXT: li 5, 0
▲ Show 20 Lines • Show All 116 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/stack-restore-with-setjmp.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=powerpc64le-- -verify-machineinstrs | FileCheck %s ; RUN: llc < %s -mtriple=powerpc64le-- -verify-machineinstrs | FileCheck %s
; RUN: llc < %s -mtriple=powerpc64-- -verify-machineinstrs | FileCheck %s \ ; RUN: llc < %s -mtriple=powerpc64-- -verify-machineinstrs | FileCheck %s \
; RUN: --check-prefix=BE ; RUN: --check-prefix=BE
%struct.__jmp_buf_tag = type { [64 x i64], i32, %struct.__sigset_t, [8 x i8] } %struct.__jmp_buf_tag = type { [64 x i64], i32, %struct.__sigset_t, [8 x i8] }
%struct.__sigset_t = type { [16 x i64] } %struct.__sigset_t = type { [16 x i64] }
@.str = private unnamed_addr constant [33 x i8] c"Successfully returned from main\0A\00", align 1 @.str = private unnamed_addr constant [33 x i8] c"Successfully returned from main\0A\00", align 1
; Function Attrs: nounwind ; Function Attrs: nounwind
define dso_local signext i32 @main(i32 signext %argc, ptr nocapture readnone %argv) local_unnamed_addr #0 { define dso_local signext i32 @main(i32 signext %argc, ptr nocapture readnone %argv) local_unnamed_addr #0 {
; CHECK-LABEL: main: ; CHECK-LABEL: main:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mfocrf 12, 32 ; CHECK-NEXT: mfocrf 12, 32
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; CHECK-NEXT: std 31, -8(1) ; CHECK-NEXT: std 31, -8(1)
; CHECK-NEXT: std 0, 16(1)
; CHECK-NEXT: stw 12, 8(1) ; CHECK-NEXT: stw 12, 8(1)
; CHECK-NEXT: stdu 1, -784(1) ; CHECK-NEXT: stdu 1, -784(1)
; CHECK-NEXT: # kill: def $r3 killed $r3 killed $x3 ; CHECK-NEXT: # kill: def $r3 killed $r3 killed $x3
; CHECK-NEXT: cmpwi 2, 3, 2 ; CHECK-NEXT: cmpwi 2, 3, 2
; CHECK-NEXT: std 0, 800(1)
; CHECK-NEXT: mr 31, 1 ; CHECK-NEXT: mr 31, 1
; CHECK-NEXT: li 3, 0 ; CHECK-NEXT: li 3, 0
; CHECK-NEXT: blt 2, .LBB0_3 ; CHECK-NEXT: blt 2, .LBB0_3
; CHECK-NEXT: # %bb.1: # %if.end ; CHECK-NEXT: # %bb.1: # %if.end
; CHECK-NEXT: addi 3, 31, 112 ; CHECK-NEXT: addi 3, 31, 112
; CHECK-NEXT: bl _setjmp ; CHECK-NEXT: bl _setjmp
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: crmove 20, 10 ; CHECK-NEXT: crmove 20, 10
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; CHECK-NEXT: li 4, -1 ; CHECK-NEXT: li 4, -1
; CHECK-NEXT: stb 4, 0(3) ; CHECK-NEXT: stb 4, 0(3)
; CHECK-NEXT: addi 4, 31, 112 ; CHECK-NEXT: addi 4, 31, 112
; CHECK-NEXT: bl test ; CHECK-NEXT: bl test
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; ;
; BE-LABEL: main: ; BE-LABEL: main:
; BE: # %bb.0: # %entry ; BE: # %bb.0: # %entry
; BE-NEXT: mfcr 12
; BE-NEXT: mflr 0 ; BE-NEXT: mflr 0
; BE-NEXT: std 31, -8(1) ; BE-NEXT: std 31, -8(1)
; BE-NEXT: std 0, 16(1)
; BE-NEXT: mfcr 12
; BE-NEXT: stw 12, 8(1) ; BE-NEXT: stw 12, 8(1)
; BE-NEXT: stdu 1, -800(1) ; BE-NEXT: stdu 1, -800(1)
; BE-NEXT: li 4, 0 ; BE-NEXT: li 4, 0
; BE-NEXT: # kill: def $r3 killed $r3 killed $x3 ; BE-NEXT: # kill: def $r3 killed $r3 killed $x3
; BE-NEXT: cmpwi 2, 3, 2 ; BE-NEXT: cmpwi 2, 3, 2
; BE-NEXT: mr 3, 4 ; BE-NEXT: mr 3, 4
; BE-NEXT: std 0, 816(1)
; BE-NEXT: mr 31, 1 ; BE-NEXT: mr 31, 1
; BE-NEXT: blt 2, .LBB0_3 ; BE-NEXT: blt 2, .LBB0_3
; BE-NEXT: # %bb.1: # %if.end ; BE-NEXT: # %bb.1: # %if.end
; BE-NEXT: addi 3, 31, 128 ; BE-NEXT: addi 3, 31, 128
; BE-NEXT: bl _setjmp ; BE-NEXT: bl _setjmp
; BE-NEXT: nop ; BE-NEXT: nop
; BE-NEXT: crmove 20, 10 ; BE-NEXT: crmove 20, 10
; BE-NEXT: # kill: def $r3 killed $r3 killed $x3 ; BE-NEXT: # kill: def $r3 killed $r3 killed $x3
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llvm/test/CodeGen/PowerPC/store_fptoi.ll

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; ;
; CHECK-PWR8-LABEL: qpConv2sdw: ; CHECK-PWR8-LABEL: qpConv2sdw:
; CHECK-PWR8: # %bb.0: # %entry ; CHECK-PWR8: # %bb.0: # %entry
; CHECK-PWR8-NEXT: mflr 0 ; CHECK-PWR8-NEXT: mflr 0
; CHECK-PWR8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-PWR8-NEXT: .cfi_def_cfa_offset 48
; CHECK-PWR8-NEXT: .cfi_offset lr, 16 ; CHECK-PWR8-NEXT: .cfi_offset lr, 16
; CHECK-PWR8-NEXT: .cfi_offset r30, -16 ; CHECK-PWR8-NEXT: .cfi_offset r30, -16
; CHECK-PWR8-NEXT: std 30, -16(1) # 8-byte Folded Spill ; CHECK-PWR8-NEXT: std 30, -16(1) # 8-byte Folded Spill
; CHECK-PWR8-NEXT: std 0, 16(1)
; CHECK-PWR8-NEXT: stdu 1, -48(1) ; CHECK-PWR8-NEXT: stdu 1, -48(1)
; CHECK-PWR8-NEXT: lxvd2x 0, 0, 3 ; CHECK-PWR8-NEXT: std 0, 64(1)
; CHECK-PWR8-NEXT: mr 30, 4 ; CHECK-PWR8-NEXT: mr 30, 4
; CHECK-PWR8-NEXT: lxvd2x 0, 0, 3
; CHECK-PWR8-NEXT: xxswapd 2, 0 ; CHECK-PWR8-NEXT: xxswapd 2, 0
; CHECK-PWR8-NEXT: bl __fixkfdi ; CHECK-PWR8-NEXT: bl __fixkfdi
; CHECK-PWR8-NEXT: nop ; CHECK-PWR8-NEXT: nop
; CHECK-PWR8-NEXT: std 3, 0(30) ; CHECK-PWR8-NEXT: std 3, 0(30)
; CHECK-PWR8-NEXT: addi 1, 1, 48 ; CHECK-PWR8-NEXT: addi 1, 1, 48
; CHECK-PWR8-NEXT: ld 0, 16(1) ; CHECK-PWR8-NEXT: ld 0, 16(1)
; CHECK-PWR8-NEXT: ld 30, -16(1) # 8-byte Folded Reload ; CHECK-PWR8-NEXT: ld 30, -16(1) # 8-byte Folded Reload
; CHECK-PWR8-NEXT: mtlr 0 ; CHECK-PWR8-NEXT: mtlr 0
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; ;
; CHECK-PWR8-LABEL: qpConv2sw: ; CHECK-PWR8-LABEL: qpConv2sw:
; CHECK-PWR8: # %bb.0: # %entry ; CHECK-PWR8: # %bb.0: # %entry
; CHECK-PWR8-NEXT: mflr 0 ; CHECK-PWR8-NEXT: mflr 0
; CHECK-PWR8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-PWR8-NEXT: .cfi_def_cfa_offset 48
; CHECK-PWR8-NEXT: .cfi_offset lr, 16 ; CHECK-PWR8-NEXT: .cfi_offset lr, 16
; CHECK-PWR8-NEXT: .cfi_offset r30, -16 ; CHECK-PWR8-NEXT: .cfi_offset r30, -16
; CHECK-PWR8-NEXT: std 30, -16(1) # 8-byte Folded Spill ; CHECK-PWR8-NEXT: std 30, -16(1) # 8-byte Folded Spill
; CHECK-PWR8-NEXT: std 0, 16(1)
; CHECK-PWR8-NEXT: stdu 1, -48(1) ; CHECK-PWR8-NEXT: stdu 1, -48(1)
; CHECK-PWR8-NEXT: lxvd2x 0, 0, 3 ; CHECK-PWR8-NEXT: std 0, 64(1)
; CHECK-PWR8-NEXT: mr 30, 4 ; CHECK-PWR8-NEXT: mr 30, 4
; CHECK-PWR8-NEXT: lxvd2x 0, 0, 3
; CHECK-PWR8-NEXT: xxswapd 2, 0 ; CHECK-PWR8-NEXT: xxswapd 2, 0
; CHECK-PWR8-NEXT: bl __fixkfsi ; CHECK-PWR8-NEXT: bl __fixkfsi
; CHECK-PWR8-NEXT: nop ; CHECK-PWR8-NEXT: nop
; CHECK-PWR8-NEXT: stw 3, 0(30) ; CHECK-PWR8-NEXT: stw 3, 0(30)
; CHECK-PWR8-NEXT: addi 1, 1, 48 ; CHECK-PWR8-NEXT: addi 1, 1, 48
; CHECK-PWR8-NEXT: ld 0, 16(1) ; CHECK-PWR8-NEXT: ld 0, 16(1)
; CHECK-PWR8-NEXT: ld 30, -16(1) # 8-byte Folded Reload ; CHECK-PWR8-NEXT: ld 30, -16(1) # 8-byte Folded Reload
; CHECK-PWR8-NEXT: mtlr 0 ; CHECK-PWR8-NEXT: mtlr 0
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; ;
; CHECK-PWR8-LABEL: qpConv2udw: ; CHECK-PWR8-LABEL: qpConv2udw:
; CHECK-PWR8: # %bb.0: # %entry ; CHECK-PWR8: # %bb.0: # %entry
; CHECK-PWR8-NEXT: mflr 0 ; CHECK-PWR8-NEXT: mflr 0
; CHECK-PWR8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-PWR8-NEXT: .cfi_def_cfa_offset 48
; CHECK-PWR8-NEXT: .cfi_offset lr, 16 ; CHECK-PWR8-NEXT: .cfi_offset lr, 16
; CHECK-PWR8-NEXT: .cfi_offset r30, -16 ; CHECK-PWR8-NEXT: .cfi_offset r30, -16
; CHECK-PWR8-NEXT: std 30, -16(1) # 8-byte Folded Spill ; CHECK-PWR8-NEXT: std 30, -16(1) # 8-byte Folded Spill
; CHECK-PWR8-NEXT: std 0, 16(1)
; CHECK-PWR8-NEXT: stdu 1, -48(1) ; CHECK-PWR8-NEXT: stdu 1, -48(1)
; CHECK-PWR8-NEXT: lxvd2x 0, 0, 3 ; CHECK-PWR8-NEXT: std 0, 64(1)
; CHECK-PWR8-NEXT: mr 30, 4 ; CHECK-PWR8-NEXT: mr 30, 4
; CHECK-PWR8-NEXT: lxvd2x 0, 0, 3
; CHECK-PWR8-NEXT: xxswapd 2, 0 ; CHECK-PWR8-NEXT: xxswapd 2, 0
; CHECK-PWR8-NEXT: bl __fixunskfdi ; CHECK-PWR8-NEXT: bl __fixunskfdi
; CHECK-PWR8-NEXT: nop ; CHECK-PWR8-NEXT: nop
; CHECK-PWR8-NEXT: std 3, 0(30) ; CHECK-PWR8-NEXT: std 3, 0(30)
; CHECK-PWR8-NEXT: addi 1, 1, 48 ; CHECK-PWR8-NEXT: addi 1, 1, 48
; CHECK-PWR8-NEXT: ld 0, 16(1) ; CHECK-PWR8-NEXT: ld 0, 16(1)
; CHECK-PWR8-NEXT: ld 30, -16(1) # 8-byte Folded Reload ; CHECK-PWR8-NEXT: ld 30, -16(1) # 8-byte Folded Reload
; CHECK-PWR8-NEXT: mtlr 0 ; CHECK-PWR8-NEXT: mtlr 0
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; ;
; CHECK-PWR8-LABEL: qpConv2uw: ; CHECK-PWR8-LABEL: qpConv2uw:
; CHECK-PWR8: # %bb.0: # %entry ; CHECK-PWR8: # %bb.0: # %entry
; CHECK-PWR8-NEXT: mflr 0 ; CHECK-PWR8-NEXT: mflr 0
; CHECK-PWR8-NEXT: .cfi_def_cfa_offset 48 ; CHECK-PWR8-NEXT: .cfi_def_cfa_offset 48
; CHECK-PWR8-NEXT: .cfi_offset lr, 16 ; CHECK-PWR8-NEXT: .cfi_offset lr, 16
; CHECK-PWR8-NEXT: .cfi_offset r30, -16 ; CHECK-PWR8-NEXT: .cfi_offset r30, -16
; CHECK-PWR8-NEXT: std 30, -16(1) # 8-byte Folded Spill ; CHECK-PWR8-NEXT: std 30, -16(1) # 8-byte Folded Spill
; CHECK-PWR8-NEXT: std 0, 16(1)
; CHECK-PWR8-NEXT: stdu 1, -48(1) ; CHECK-PWR8-NEXT: stdu 1, -48(1)
; CHECK-PWR8-NEXT: lxvd2x 0, 0, 3 ; CHECK-PWR8-NEXT: std 0, 64(1)
; CHECK-PWR8-NEXT: mr 30, 4 ; CHECK-PWR8-NEXT: mr 30, 4
; CHECK-PWR8-NEXT: lxvd2x 0, 0, 3
; CHECK-PWR8-NEXT: xxswapd 2, 0 ; CHECK-PWR8-NEXT: xxswapd 2, 0
; CHECK-PWR8-NEXT: bl __fixunskfsi ; CHECK-PWR8-NEXT: bl __fixunskfsi
; CHECK-PWR8-NEXT: nop ; CHECK-PWR8-NEXT: nop
; CHECK-PWR8-NEXT: stw 3, 0(30) ; CHECK-PWR8-NEXT: stw 3, 0(30)
; CHECK-PWR8-NEXT: addi 1, 1, 48 ; CHECK-PWR8-NEXT: addi 1, 1, 48
; CHECK-PWR8-NEXT: ld 0, 16(1) ; CHECK-PWR8-NEXT: ld 0, 16(1)
; CHECK-PWR8-NEXT: ld 30, -16(1) # 8-byte Folded Reload ; CHECK-PWR8-NEXT: ld 30, -16(1) # 8-byte Folded Reload
; CHECK-PWR8-NEXT: mtlr 0 ; CHECK-PWR8-NEXT: mtlr 0
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llvm/test/CodeGen/PowerPC/tailcall-speculatable-callee.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | FileCheck %s ; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | FileCheck %s
; The tests check the behavior of the tail call decision when the callee is speculatable. ; The tests check the behavior of the tail call decision when the callee is speculatable.
; Callee should be tail called in this function since it is at a tail call position. ; Callee should be tail called in this function since it is at a tail call position.
define dso_local double @speculatable_callee_return_use_only (ptr nocapture %res, double %a) #0 { define dso_local double @speculatable_callee_return_use_only (ptr nocapture %res, double %a) #0 {
; CHECK-LABEL: speculatable_callee_return_use_only: ; CHECK-LABEL: speculatable_callee_return_use_only:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: b callee ; CHECK-NEXT: b callee
; CHECK-NEXT: #TC_RETURNd8 callee 0
entry: entry:
%value = tail call double @callee(double %a) #2 %value = tail call double @callee(double %a) #2
ret double %value ret double %value
} }
; Callee should not be tail called since it is not at a tail call position. ; Callee should not be tail called since it is not at a tail call position.
define dso_local void @speculatable_callee_non_return_use_only (ptr nocapture %res, double %a) #0 { define dso_local void @speculatable_callee_non_return_use_only (ptr nocapture %res, double %a) #0 {
; CHECK-LABEL: speculatable_callee_non_return_use_only: ; CHECK-LABEL: speculatable_callee_non_return_use_only:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr r0 ; CHECK-NEXT: mflr r0
; CHECK-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-NEXT: std r0, 16(r1)
; CHECK-NEXT: stdu r1, -48(r1) ; CHECK-NEXT: stdu r1, -48(r1)
; CHECK-NEXT: std r0, 64(r1)
; CHECK-NEXT: mr r30, r3 ; CHECK-NEXT: mr r30, r3
; CHECK-NEXT: bl callee ; CHECK-NEXT: bl callee
; CHECK-NEXT: stfd f1, 0(r30) ; CHECK-NEXT: stfd f1, 0(r30)
; CHECK-NEXT: addi r1, r1, 48 ; CHECK-NEXT: addi r1, r1, 48
; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: ld r0, 16(r1)
; CHECK-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: mtlr r0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%call = tail call double @callee(double %a) #2 %call = tail call double @callee(double %a) #2
store double %call, ptr %res, align 8 store double %call, ptr %res, align 8
ret void ret void
} }
; Callee should not be tail called since it is not at a tail call position. ; Callee should not be tail called since it is not at a tail call position.
define dso_local double @speculatable_callee_multi_use (ptr nocapture %res, double %a) #0 { define dso_local double @speculatable_callee_multi_use (ptr nocapture %res, double %a) #0 {
; CHECK-LABEL: speculatable_callee_multi_use: ; CHECK-LABEL: speculatable_callee_multi_use:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr r0 ; CHECK-NEXT: mflr r0
; CHECK-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-NEXT: std r0, 16(r1)
; CHECK-NEXT: stdu r1, -48(r1) ; CHECK-NEXT: stdu r1, -48(r1)
; CHECK-NEXT: std r0, 64(r1)
; CHECK-NEXT: mr r30, r3 ; CHECK-NEXT: mr r30, r3
; CHECK-NEXT: bl callee ; CHECK-NEXT: bl callee
; CHECK-NEXT: stfd f1, 0(r30) ; CHECK-NEXT: stfd f1, 0(r30)
; CHECK-NEXT: addi r1, r1, 48 ; CHECK-NEXT: addi r1, r1, 48
; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: ld r0, 16(r1)
; CHECK-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: mtlr r0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%call = tail call double @callee(double %a) #2 %call = tail call double @callee(double %a) #2
store double %call, ptr %res, align 8 store double %call, ptr %res, align 8
ret double %call ret double %call
} }
; Callee should not be tail called since it is not at a tail call position. ; Callee should not be tail called since it is not at a tail call position.
; FIXME: A speculatable callee can be tail called if it is moved into a valid tail call position. ; FIXME: A speculatable callee can be tail called if it is moved into a valid tail call position.
define dso_local double @speculatable_callee_intermediate_instructions (ptr nocapture %res, double %a) #0 { define dso_local double @speculatable_callee_intermediate_instructions (ptr nocapture %res, double %a) #0 {
; CHECK-LABEL: speculatable_callee_intermediate_instructions: ; CHECK-LABEL: speculatable_callee_intermediate_instructions:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr r0 ; CHECK-NEXT: mflr r0
; CHECK-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-NEXT: std r0, 16(r1)
; CHECK-NEXT: stdu r1, -48(r1) ; CHECK-NEXT: stdu r1, -48(r1)
; CHECK-NEXT: std r0, 64(r1)
; CHECK-NEXT: mr r30, r3 ; CHECK-NEXT: mr r30, r3
; CHECK-NEXT: bl callee ; CHECK-NEXT: bl callee
; CHECK-NEXT: lis r3, 4101 ; CHECK-NEXT: lis r3, 4101
; CHECK-NEXT: ori r3, r3, 13107 ; CHECK-NEXT: ori r3, r3, 13107
; CHECK-NEXT: rldic r3, r3, 34, 1 ; CHECK-NEXT: rldic r3, r3, 34, 1
; CHECK-NEXT: oris r3, r3, 52428 ; CHECK-NEXT: oris r3, r3, 52428
; CHECK-NEXT: ori r3, r3, 52429 ; CHECK-NEXT: ori r3, r3, 52429
; CHECK-NEXT: std r3, 0(r30) ; CHECK-NEXT: std r3, 0(r30)
; CHECK-NEXT: addi r1, r1, 48 ; CHECK-NEXT: addi r1, r1, 48
; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: ld r0, 16(r1)
; CHECK-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: mtlr r0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%call = tail call double @callee(double %a) #2 %call = tail call double @callee(double %a) #2
store double 5.2, ptr %res, align 8 store double 5.2, ptr %res, align 8
ret double %call ret double %call
} }
define dso_local double @callee(double) #1 { define dso_local double @callee(double) #1 {
; CHECK-LABEL: callee:
; CHECK: # %bb.0:
; CHECK-NEXT: addis r3, r2, .LCPI4_0@toc@ha
; CHECK-NEXT: lfs f1, .LCPI4_0@toc@l(r3)
; CHECK-NEXT: blr
ret double 4.5 ret double 4.5
} }
attributes #0 = { nounwind } attributes #0 = { nounwind }
attributes #1 = { readnone speculatable } attributes #1 = { readnone speculatable }
attributes #2 = { nounwind noinline } attributes #2 = { nounwind noinline }

llvm/test/CodeGen/PowerPC/testComparesi32gtu.ll

Show All 24 Lines
%struct.tree_common = type { i8, [3 x i8] } %struct.tree_common = type { i8, [3 x i8] }
declare signext i32 @fn2(...) local_unnamed_addr #1 declare signext i32 @fn2(...) local_unnamed_addr #1
; Function Attrs: nounwind ; Function Attrs: nounwind
define dso_local i32 @testCompare1(ptr nocapture readonly %arg1) nounwind { define dso_local i32 @testCompare1(ptr nocapture readonly %arg1) nounwind {
; BE-LABEL: testCompare1: ; BE-LABEL: testCompare1:
; BE: # %bb.0: # %entry ; BE: # %bb.0: # %entry
; BE-NEXT: mflr r0 ; BE-NEXT: mflr r0
; BE-NEXT: std r0, 16(r1)
; BE-NEXT: stdu r1, -112(r1) ; BE-NEXT: stdu r1, -112(r1)
; BE-NEXT: std r0, 128(r1)
; BE-NEXT: addis r4, r2, testCompare1@toc@ha ; BE-NEXT: addis r4, r2, testCompare1@toc@ha
; BE-NEXT: lbz r3, 0(r3)
; BE-NEXT: lbz r4, testCompare1@toc@l(r4) ; BE-NEXT: lbz r4, testCompare1@toc@l(r4)
; BE-NEXT: clrlwi r3, r3, 31 ; BE-NEXT: lbz r3, 0(r3)
; BE-NEXT: clrlwi r4, r4, 31 ; BE-NEXT: clrlwi r4, r4, 31
; BE-NEXT: clrldi r3, r3, 32 ; BE-NEXT: clrlwi r3, r3, 31
; BE-NEXT: clrldi r4, r4, 32 ; BE-NEXT: clrldi r4, r4, 32
; BE-NEXT: clrldi r3, r3, 32
; BE-NEXT: sub r3, r3, r4 ; BE-NEXT: sub r3, r3, r4
; BE-NEXT: rldicl r3, r3, 1, 63 ; BE-NEXT: rldicl r3, r3, 1, 63
; BE-NEXT: bl fn2 ; BE-NEXT: bl fn2
; BE-NEXT: nop ; BE-NEXT: nop
; BE-NEXT: addi r1, r1, 112 ; BE-NEXT: addi r1, r1, 112
; BE-NEXT: ld r0, 16(r1) ; BE-NEXT: ld r0, 16(r1)
; BE-NEXT: mtlr r0 ; BE-NEXT: mtlr r0
; BE-NEXT: blr ; BE-NEXT: blr
; ;
; LE-LABEL: testCompare1: ; LE-LABEL: testCompare1:
; LE: # %bb.0: # %entry ; LE: # %bb.0: # %entry
; LE-NEXT: mflr r0 ; LE-NEXT: mflr r0
; LE-NEXT: std r0, 16(r1)
; LE-NEXT: stdu r1, -32(r1) ; LE-NEXT: stdu r1, -32(r1)
; LE-NEXT: std r0, 48(r1)
; LE-NEXT: addis r4, r2, testCompare1@toc@ha ; LE-NEXT: addis r4, r2, testCompare1@toc@ha
; LE-NEXT: lbz r3, 0(r3)
; LE-NEXT: lbz r4, testCompare1@toc@l(r4) ; LE-NEXT: lbz r4, testCompare1@toc@l(r4)
; LE-NEXT: clrlwi r3, r3, 31 ; LE-NEXT: lbz r3, 0(r3)
; LE-NEXT: clrlwi r4, r4, 31 ; LE-NEXT: clrlwi r4, r4, 31
; LE-NEXT: clrldi r3, r3, 32 ; LE-NEXT: clrlwi r3, r3, 31
; LE-NEXT: clrldi r4, r4, 32 ; LE-NEXT: clrldi r4, r4, 32
; LE-NEXT: clrldi r3, r3, 32
; LE-NEXT: sub r3, r3, r4 ; LE-NEXT: sub r3, r3, r4
; LE-NEXT: rldicl r3, r3, 1, 63 ; LE-NEXT: rldicl r3, r3, 1, 63
; LE-NEXT: bl fn2 ; LE-NEXT: bl fn2
; LE-NEXT: nop ; LE-NEXT: nop
; LE-NEXT: addi r1, r1, 32 ; LE-NEXT: addi r1, r1, 32
; LE-NEXT: ld r0, 16(r1) ; LE-NEXT: ld r0, 16(r1)
; LE-NEXT: mtlr r0 ; LE-NEXT: mtlr r0
; LE-NEXT: blr ; LE-NEXT: blr
▲ Show 20 Lines • Show All 113 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/testComparesi32ltu.ll

Show All 26 Lines
%struct.tree_common = type { i8, [3 x i8] } %struct.tree_common = type { i8, [3 x i8] }
declare signext i32 @fn2(...) local_unnamed_addr #1 declare signext i32 @fn2(...) local_unnamed_addr #1
; Function Attrs: nounwind ; Function Attrs: nounwind
define dso_local i32 @testCompare1(ptr nocapture readonly %arg1) nounwind { define dso_local i32 @testCompare1(ptr nocapture readonly %arg1) nounwind {
; BE-LABEL: testCompare1: ; BE-LABEL: testCompare1:
; BE: # %bb.0: # %entry ; BE: # %bb.0: # %entry
; BE-NEXT: mflr r0 ; BE-NEXT: mflr r0
; BE-NEXT: std r0, 16(r1)
; BE-NEXT: stdu r1, -112(r1) ; BE-NEXT: stdu r1, -112(r1)
; BE-NEXT: std r0, 128(r1)
; BE-NEXT: addis r4, r2, testCompare1@toc@ha ; BE-NEXT: addis r4, r2, testCompare1@toc@ha
; BE-NEXT: lbz r3, 0(r3)
; BE-NEXT: lbz r4, testCompare1@toc@l(r4) ; BE-NEXT: lbz r4, testCompare1@toc@l(r4)
; BE-NEXT: clrlwi r3, r3, 31 ; BE-NEXT: lbz r3, 0(r3)
; BE-NEXT: clrlwi r4, r4, 31 ; BE-NEXT: clrlwi r4, r4, 31
; BE-NEXT: clrldi r3, r3, 32 ; BE-NEXT: clrlwi r3, r3, 31
; BE-NEXT: clrldi r4, r4, 32 ; BE-NEXT: clrldi r4, r4, 32
; BE-NEXT: clrldi r3, r3, 32
; BE-NEXT: sub r3, r4, r3 ; BE-NEXT: sub r3, r4, r3
; BE-NEXT: rldicl r3, r3, 1, 63 ; BE-NEXT: rldicl r3, r3, 1, 63
; BE-NEXT: bl fn2 ; BE-NEXT: bl fn2
; BE-NEXT: nop ; BE-NEXT: nop
; BE-NEXT: addi r1, r1, 112 ; BE-NEXT: addi r1, r1, 112
; BE-NEXT: ld r0, 16(r1) ; BE-NEXT: ld r0, 16(r1)
; BE-NEXT: mtlr r0 ; BE-NEXT: mtlr r0
; BE-NEXT: blr ; BE-NEXT: blr
; ;
; LE-LABEL: testCompare1: ; LE-LABEL: testCompare1:
; LE: # %bb.0: # %entry ; LE: # %bb.0: # %entry
; LE-NEXT: mflr r0 ; LE-NEXT: mflr r0
; LE-NEXT: std r0, 16(r1)
; LE-NEXT: stdu r1, -32(r1) ; LE-NEXT: stdu r1, -32(r1)
; LE-NEXT: std r0, 48(r1)
; LE-NEXT: addis r4, r2, testCompare1@toc@ha ; LE-NEXT: addis r4, r2, testCompare1@toc@ha
; LE-NEXT: lbz r3, 0(r3)
; LE-NEXT: lbz r4, testCompare1@toc@l(r4) ; LE-NEXT: lbz r4, testCompare1@toc@l(r4)
; LE-NEXT: clrlwi r3, r3, 31 ; LE-NEXT: lbz r3, 0(r3)
; LE-NEXT: clrlwi r4, r4, 31 ; LE-NEXT: clrlwi r4, r4, 31
; LE-NEXT: clrldi r3, r3, 32 ; LE-NEXT: clrlwi r3, r3, 31
; LE-NEXT: clrldi r4, r4, 32 ; LE-NEXT: clrldi r4, r4, 32
; LE-NEXT: clrldi r3, r3, 32
; LE-NEXT: sub r3, r4, r3 ; LE-NEXT: sub r3, r4, r3
; LE-NEXT: rldicl r3, r3, 1, 63 ; LE-NEXT: rldicl r3, r3, 1, 63
; LE-NEXT: bl fn2 ; LE-NEXT: bl fn2
; LE-NEXT: nop ; LE-NEXT: nop
; LE-NEXT: addi r1, r1, 32 ; LE-NEXT: addi r1, r1, 32
; LE-NEXT: ld r0, 16(r1) ; LE-NEXT: ld r0, 16(r1)
; LE-NEXT: mtlr r0 ; LE-NEXT: mtlr r0
; LE-NEXT: blr ; LE-NEXT: blr
▲ Show 20 Lines • Show All 111 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/tocSaveInPrologue.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names \ ; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names \
; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s ; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s
define dso_local void @test(ptr nocapture %fp, i32 signext %Arg, i32 signext %Len) local_unnamed_addr #0 { define dso_local void @test(ptr nocapture %fp, i32 signext %Arg, i32 signext %Len) local_unnamed_addr #0 {
; CHECK-LABEL: test: ; CHECK-LABEL: test:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr r0 ; CHECK-NEXT: mflr r0
; CHECK-NEXT: .cfi_def_cfa_offset 64 ; CHECK-NEXT: .cfi_def_cfa_offset 64
; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: .cfi_offset r28, -32 ; CHECK-NEXT: .cfi_offset r28, -32
; CHECK-NEXT: .cfi_offset r29, -24 ; CHECK-NEXT: .cfi_offset r29, -24
; CHECK-NEXT: .cfi_offset r30, -16 ; CHECK-NEXT: .cfi_offset r30, -16
; CHECK-NEXT: std r28, -32(r1) # 8-byte Folded Spill ; CHECK-NEXT: std r28, -32(r1) # 8-byte Folded Spill
; CHECK-NEXT: std r29, -24(r1) # 8-byte Folded Spill ; CHECK-NEXT: std r29, -24(r1) # 8-byte Folded Spill
; CHECK-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-NEXT: std r0, 16(r1)
; CHECK-NEXT: stdu r1, -64(r1) ; CHECK-NEXT: stdu r1, -64(r1)
; CHECK-NEXT: mr r29, r5 ; CHECK-NEXT: mr r29, r5
; CHECK-NEXT: mr r30, r4 ; CHECK-NEXT: mr r30, r4
; CHECK-NEXT: mr r28, r3 ; CHECK-NEXT: mr r28, r3
; CHECK-NEXT: std r2, 24(r1) ; CHECK-NEXT: std r2, 24(r1)
; CHECK-NEXT: std r0, 80(r1)
; CHECK-NEXT: cmpwi r29, 1 ; CHECK-NEXT: cmpwi r29, 1
; CHECK-NEXT: bc 12, lt, .LBB0_3 ; CHECK-NEXT: bc 12, lt, .LBB0_3
; CHECK-NEXT: # %bb.1: # %entry ; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: cmpwi r30, 11 ; CHECK-NEXT: cmpwi r30, 11
; CHECK-NEXT: bc 12, lt, .LBB0_3 ; CHECK-NEXT: bc 12, lt, .LBB0_3
; CHECK-NEXT: .p2align 5 ; CHECK-NEXT: .p2align 5
; CHECK-NEXT: .LBB0_2: # %for.body.us ; CHECK-NEXT: .LBB0_2: # %for.body.us
; CHECK-NEXT: # ; CHECK-NEXT: #
Show All 38 Lines

llvm/test/CodeGen/PowerPC/urem-lkk.ll

Show First 20 Lines • Show All 84 Lines • ▼ Show 20 Lines; CHECK-NEXT: blr
ret i32 %1 ret i32 %1
} }
; Don't fold i64 urem ; Don't fold i64 urem
define i64 @dont_fold_urem_i64(i64 %x) { define i64 @dont_fold_urem_i64(i64 %x) {
; CHECK-LABEL: dont_fold_urem_i64: ; CHECK-LABEL: dont_fold_urem_i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; CHECK-NEXT: stw 0, 4(1)
; CHECK-NEXT: stwu 1, -16(1) ; CHECK-NEXT: stwu 1, -16(1)
; CHECK-NEXT: stw 0, 20(1)
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset lr, 4 ; CHECK-NEXT: .cfi_offset lr, 4
; CHECK-NEXT: li 5, 0 ; CHECK-NEXT: li 5, 0
; CHECK-NEXT: li 6, 98 ; CHECK-NEXT: li 6, 98
; CHECK-NEXT: bl __umoddi3 ; CHECK-NEXT: bl __umoddi3
; CHECK-NEXT: lwz 0, 20(1) ; CHECK-NEXT: lwz 0, 20(1)
; CHECK-NEXT: addi 1, 1, 16 ; CHECK-NEXT: addi 1, 1, 16
; CHECK-NEXT: mtlr 0 ; CHECK-NEXT: mtlr 0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%1 = urem i64 %x, 98 %1 = urem i64 %x, 98
ret i64 %1 ret i64 %1
} }

llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 162 Lines • ▼ Show 20 Lines %div = call <4 x double> @llvm.experimental.constrained.fdiv.v4f64(
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <4 x double> %div ret <4 x double> %div
} }
define <1 x float> @constrained_vector_frem_v1f32(<1 x float> %x, <1 x float> %y) #0 { define <1 x float> @constrained_vector_frem_v1f32(<1 x float> %x, <1 x float> %y) #0 {
; PC64LE-LABEL: constrained_vector_frem_v1f32: ; PC64LE-LABEL: constrained_vector_frem_v1f32:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -32(1) ; PC64LE-NEXT: stdu 1, -32(1)
; PC64LE-NEXT: std 0, 48(1)
; PC64LE-NEXT: bl fmodf ; PC64LE-NEXT: bl fmodf
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: addi 1, 1, 32 ; PC64LE-NEXT: addi 1, 1, 32
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_frem_v1f32: ; PC64LE9-LABEL: constrained_vector_frem_v1f32:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -32(1) ; PC64LE9-NEXT: stdu 1, -32(1)
; PC64LE9-NEXT: std 0, 48(1)
; PC64LE9-NEXT: bl fmodf ; PC64LE9-NEXT: bl fmodf
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addi 1, 1, 32 ; PC64LE9-NEXT: addi 1, 1, 32
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%rem = call <1 x float> @llvm.experimental.constrained.frem.v1f32( %rem = call <1 x float> @llvm.experimental.constrained.frem.v1f32(
<1 x float> %x, <1 x float> %x,
<1 x float> %y, <1 x float> %y,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <1 x float> %rem ret <1 x float> %rem
} }
define <2 x double> @constrained_vector_frem_v2f64(<2 x double> %x, <2 x double> %y) #0 { define <2 x double> @constrained_vector_frem_v2f64(<2 x double> %x, <2 x double> %y) #0 {
; PC64LE-LABEL: constrained_vector_frem_v2f64: ; PC64LE-LABEL: constrained_vector_frem_v2f64:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -96(1) ; PC64LE-NEXT: stdu 1, -96(1)
; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: li 3, 48
; PC64LE-NEXT: std 0, 112(1)
; PC64LE-NEXT: stxvd2x 61, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 61, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: li 3, 64 ; PC64LE-NEXT: li 3, 64
; PC64LE-NEXT: stxvd2x 62, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 62, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: li 3, 80 ; PC64LE-NEXT: li 3, 80
; PC64LE-NEXT: vmr 30, 2 ; PC64LE-NEXT: vmr 30, 2
; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: vmr 31, 3 ; PC64LE-NEXT: vmr 31, 3
; PC64LE-NEXT: xxlor 1, 62, 62 ; PC64LE-NEXT: xxlor 1, 62, 62
Show All 18 Lines
; PC64LE-NEXT: addi 1, 1, 96 ; PC64LE-NEXT: addi 1, 1, 96
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_frem_v2f64: ; PC64LE9-LABEL: constrained_vector_frem_v2f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -80(1) ; PC64LE9-NEXT: stdu 1, -80(1)
; PC64LE9-NEXT: std 0, 96(1)
; PC64LE9-NEXT: stxv 62, 48(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 62, 48(1) # 16-byte Folded Spill
; PC64LE9-NEXT: stxv 63, 64(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 63, 64(1) # 16-byte Folded Spill
; PC64LE9-NEXT: vmr 31, 3 ; PC64LE9-NEXT: vmr 31, 3
; PC64LE9-NEXT: xscpsgndp 2, 63, 63 ; PC64LE9-NEXT: xscpsgndp 2, 63, 63
; PC64LE9-NEXT: vmr 30, 2 ; PC64LE9-NEXT: vmr 30, 2
; PC64LE9-NEXT: xscpsgndp 1, 62, 62 ; PC64LE9-NEXT: xscpsgndp 1, 62, 62
; PC64LE9-NEXT: stxv 61, 32(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 61, 32(1) # 16-byte Folded Spill
; PC64LE9-NEXT: bl fmod ; PC64LE9-NEXT: bl fmod
Show All 22 Lines %rem = call <2 x double> @llvm.experimental.constrained.frem.v2f64(
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <2 x double> %rem ret <2 x double> %rem
} }
define <3 x float> @constrained_vector_frem_v3f32(<3 x float> %x, <3 x float> %y) #0 { define <3 x float> @constrained_vector_frem_v3f32(<3 x float> %x, <3 x float> %y) #0 {
; PC64LE-LABEL: constrained_vector_frem_v3f32: ; PC64LE-LABEL: constrained_vector_frem_v3f32:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -96(1) ; PC64LE-NEXT: stdu 1, -96(1)
; PC64LE-NEXT: xxsldwi 0, 34, 34, 1 ; PC64LE-NEXT: xxsldwi 0, 34, 34, 1
; PC64LE-NEXT: xxsldwi 2, 35, 35, 1 ; PC64LE-NEXT: xxsldwi 2, 35, 35, 1
; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: li 3, 48
; PC64LE-NEXT: std 0, 112(1)
; PC64LE-NEXT: stxvd2x 62, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 62, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: li 3, 64 ; PC64LE-NEXT: li 3, 64
; PC64LE-NEXT: vmr 30, 2
; PC64LE-NEXT: stfd 30, 80(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 30, 80(1) # 8-byte Folded Spill
; PC64LE-NEXT: stfd 31, 88(1) # 8-byte Folded Spill
; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: xscvspdpn 1, 0 ; PC64LE-NEXT: xscvspdpn 1, 0
; PC64LE-NEXT: stfd 31, 88(1) # 8-byte Folded Spill
; PC64LE-NEXT: xscvspdpn 2, 2 ; PC64LE-NEXT: xscvspdpn 2, 2
; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: vmr 31, 3 ; PC64LE-NEXT: vmr 31, 3
; PC64LE-NEXT: vmr 30, 2
; PC64LE-NEXT: bl fmodf ; PC64LE-NEXT: bl fmodf
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: xxswapd 0, 62 ; PC64LE-NEXT: xxswapd 0, 62
; PC64LE-NEXT: xxswapd 2, 63 ; PC64LE-NEXT: xxswapd 2, 63
; PC64LE-NEXT: fmr 31, 1 ; PC64LE-NEXT: fmr 31, 1
; PC64LE-NEXT: xscvspdpn 1, 0 ; PC64LE-NEXT: xscvspdpn 1, 0
; PC64LE-NEXT: xscvspdpn 2, 2 ; PC64LE-NEXT: xscvspdpn 2, 2
; PC64LE-NEXT: bl fmodf ; PC64LE-NEXT: bl fmodf
Show All 23 Lines
; PC64LE-NEXT: addi 1, 1, 96 ; PC64LE-NEXT: addi 1, 1, 96
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_frem_v3f32: ; PC64LE9-LABEL: constrained_vector_frem_v3f32:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -80(1) ; PC64LE9-NEXT: stdu 1, -80(1)
; PC64LE9-NEXT: xxsldwi 0, 34, 34, 1 ; PC64LE9-NEXT: xxsldwi 0, 34, 34, 1
; PC64LE9-NEXT: std 0, 96(1)
; PC64LE9-NEXT: stfd 30, 64(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 30, 64(1) # 8-byte Folded Spill
; PC64LE9-NEXT: stfd 31, 72(1) # 8-byte Folded Spill
; PC64LE9-NEXT: stxv 62, 32(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 62, 32(1) # 16-byte Folded Spill
; PC64LE9-NEXT: stfd 31, 72(1) # 8-byte Folded Spill
; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill
; PC64LE9-NEXT: xscvspdpn 1, 0 ; PC64LE9-NEXT: xscvspdpn 1, 0
; PC64LE9-NEXT: xxsldwi 0, 35, 35, 1 ; PC64LE9-NEXT: xxsldwi 0, 35, 35, 1
; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill
; PC64LE9-NEXT: xscvspdpn 2, 0
; PC64LE9-NEXT: vmr 31, 3 ; PC64LE9-NEXT: vmr 31, 3
; PC64LE9-NEXT: vmr 30, 2 ; PC64LE9-NEXT: vmr 30, 2
; PC64LE9-NEXT: xscvspdpn 2, 0
; PC64LE9-NEXT: bl fmodf ; PC64LE9-NEXT: bl fmodf
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: xxswapd 0, 62 ; PC64LE9-NEXT: xxswapd 0, 62
; PC64LE9-NEXT: fmr 31, 1 ; PC64LE9-NEXT: fmr 31, 1
; PC64LE9-NEXT: xscvspdpn 1, 0 ; PC64LE9-NEXT: xscvspdpn 1, 0
; PC64LE9-NEXT: xxswapd 0, 63 ; PC64LE9-NEXT: xxswapd 0, 63
; PC64LE9-NEXT: xscvspdpn 2, 0 ; PC64LE9-NEXT: xscvspdpn 2, 0
; PC64LE9-NEXT: bl fmodf ; PC64LE9-NEXT: bl fmodf
Show All 29 Lines %rem = call <3 x float> @llvm.experimental.constrained.frem.v3f32(
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <3 x float> %rem ret <3 x float> %rem
} }
define <3 x double> @constrained_vector_frem_v3f64(<3 x double> %x, <3 x double> %y) #0 { define <3 x double> @constrained_vector_frem_v3f64(<3 x double> %x, <3 x double> %y) #0 {
; PC64LE-LABEL: constrained_vector_frem_v3f64: ; PC64LE-LABEL: constrained_vector_frem_v3f64:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -96(1) ; PC64LE-NEXT: stdu 1, -96(1)
; PC64LE-NEXT: std 0, 112(1)
; PC64LE-NEXT: stfd 28, 64(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 28, 64(1) # 8-byte Folded Spill
; PC64LE-NEXT: fmr 28, 2 ; PC64LE-NEXT: fmr 28, 2
; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: li 3, 48
; PC64LE-NEXT: fmr 2, 4 ; PC64LE-NEXT: fmr 2, 4
; PC64LE-NEXT: stfd 29, 72(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 29, 72(1) # 8-byte Folded Spill
; PC64LE-NEXT: stfd 30, 80(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 30, 80(1) # 8-byte Folded Spill
; PC64LE-NEXT: fmr 30, 5
; PC64LE-NEXT: stfd 31, 88(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 31, 88(1) # 8-byte Folded Spill
; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: fmr 31, 6 ; PC64LE-NEXT: fmr 31, 6
; PC64LE-NEXT: fmr 30, 5
; PC64LE-NEXT: fmr 29, 3 ; PC64LE-NEXT: fmr 29, 3
; PC64LE-NEXT: bl fmod ; PC64LE-NEXT: bl fmod
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: xxlor 63, 1, 1 ; PC64LE-NEXT: xxlor 63, 1, 1
; PC64LE-NEXT: fmr 1, 28 ; PC64LE-NEXT: fmr 1, 28
; PC64LE-NEXT: fmr 2, 30 ; PC64LE-NEXT: fmr 2, 30
; PC64LE-NEXT: bl fmod ; PC64LE-NEXT: bl fmod
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
Show All 16 Lines
; PC64LE-NEXT: addi 1, 1, 96 ; PC64LE-NEXT: addi 1, 1, 96
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_frem_v3f64: ; PC64LE9-LABEL: constrained_vector_frem_v3f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -80(1) ; PC64LE9-NEXT: stdu 1, -80(1)
; PC64LE9-NEXT: std 0, 96(1)
; PC64LE9-NEXT: stfd 28, 48(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 28, 48(1) # 8-byte Folded Spill
; PC64LE9-NEXT: fmr 28, 2
; PC64LE9-NEXT: stxv 63, 32(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 63, 32(1) # 16-byte Folded Spill
; PC64LE9-NEXT: fmr 28, 2
; PC64LE9-NEXT: fmr 2, 4 ; PC64LE9-NEXT: fmr 2, 4
; PC64LE9-NEXT: stfd 29, 56(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 29, 56(1) # 8-byte Folded Spill
; PC64LE9-NEXT: stfd 30, 64(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 30, 64(1) # 8-byte Folded Spill
; PC64LE9-NEXT: stfd 31, 72(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 31, 72(1) # 8-byte Folded Spill
; PC64LE9-NEXT: fmr 31, 6 ; PC64LE9-NEXT: fmr 31, 6
; PC64LE9-NEXT: fmr 30, 5 ; PC64LE9-NEXT: fmr 30, 5
; PC64LE9-NEXT: fmr 29, 3 ; PC64LE9-NEXT: fmr 29, 3
; PC64LE9-NEXT: bl fmod ; PC64LE9-NEXT: bl fmod
Show All 30 Lines %rem = call <3 x double> @llvm.experimental.constrained.frem.v3f64(
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <3 x double> %rem ret <3 x double> %rem
} }
define <4 x double> @constrained_vector_frem_v4f64(<4 x double> %x, <4 x double> %y) #0 { define <4 x double> @constrained_vector_frem_v4f64(<4 x double> %x, <4 x double> %y) #0 {
; PC64LE-LABEL: constrained_vector_frem_v4f64: ; PC64LE-LABEL: constrained_vector_frem_v4f64:
; PC64LE: # %bb.0: ; PC64LE: # %bb.0:
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -128(1) ; PC64LE-NEXT: stdu 1, -128(1)
; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: li 3, 48
; PC64LE-NEXT: std 0, 144(1)
; PC64LE-NEXT: stxvd2x 59, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 59, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: li 3, 64 ; PC64LE-NEXT: li 3, 64
; PC64LE-NEXT: stxvd2x 60, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 60, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: li 3, 80 ; PC64LE-NEXT: li 3, 80
; PC64LE-NEXT: vmr 28, 2 ; PC64LE-NEXT: vmr 28, 2
; PC64LE-NEXT: stxvd2x 61, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 61, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: li 3, 96 ; PC64LE-NEXT: li 3, 96
; PC64LE-NEXT: vmr 29, 3 ; PC64LE-NEXT: vmr 29, 3
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
; PC64LE-NEXT: addi 1, 1, 128 ; PC64LE-NEXT: addi 1, 1, 128
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_frem_v4f64: ; PC64LE9-LABEL: constrained_vector_frem_v4f64:
; PC64LE9: # %bb.0: ; PC64LE9: # %bb.0:
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -112(1) ; PC64LE9-NEXT: stdu 1, -112(1)
; PC64LE9-NEXT: std 0, 128(1)
; PC64LE9-NEXT: stxv 60, 48(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 60, 48(1) # 16-byte Folded Spill
; PC64LE9-NEXT: stxv 62, 80(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 62, 80(1) # 16-byte Folded Spill
; PC64LE9-NEXT: vmr 30, 4 ; PC64LE9-NEXT: vmr 30, 4
; PC64LE9-NEXT: xscpsgndp 2, 62, 62 ; PC64LE9-NEXT: xscpsgndp 2, 62, 62
; PC64LE9-NEXT: vmr 28, 2 ; PC64LE9-NEXT: vmr 28, 2
; PC64LE9-NEXT: xscpsgndp 1, 60, 60 ; PC64LE9-NEXT: xscpsgndp 1, 60, 60
; PC64LE9-NEXT: stxv 59, 32(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 59, 32(1) # 16-byte Folded Spill
; PC64LE9-NEXT: stxv 61, 64(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 61, 64(1) # 16-byte Folded Spill
▲ Show 20 Lines • Show All 666 Lines • ▼ Show 20 Lines %sqrt = call <4 x double> @llvm.experimental.constrained.sqrt.v4f64(
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <4 x double> %sqrt ret <4 x double> %sqrt
} }
define <1 x float> @constrained_vector_pow_v1f32(<1 x float> %x, <1 x float> %y) #0 { define <1 x float> @constrained_vector_pow_v1f32(<1 x float> %x, <1 x float> %y) #0 {
; PC64LE-LABEL: constrained_vector_pow_v1f32: ; PC64LE-LABEL: constrained_vector_pow_v1f32:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -32(1) ; PC64LE-NEXT: stdu 1, -32(1)
; PC64LE-NEXT: std 0, 48(1)
; PC64LE-NEXT: bl powf ; PC64LE-NEXT: bl powf
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: addi 1, 1, 32 ; PC64LE-NEXT: addi 1, 1, 32
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_pow_v1f32: ; PC64LE9-LABEL: constrained_vector_pow_v1f32:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -32(1) ; PC64LE9-NEXT: stdu 1, -32(1)
; PC64LE9-NEXT: std 0, 48(1)
; PC64LE9-NEXT: bl powf ; PC64LE9-NEXT: bl powf
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addi 1, 1, 32 ; PC64LE9-NEXT: addi 1, 1, 32
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%pow = call <1 x float> @llvm.experimental.constrained.pow.v1f32( %pow = call <1 x float> @llvm.experimental.constrained.pow.v1f32(
<1 x float> %x, <1 x float> %x,
<1 x float> %y, <1 x float> %y,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <1 x float> %pow ret <1 x float> %pow
} }
define <2 x double> @constrained_vector_pow_v2f64(<2 x double> %x, <2 x double> %y) #0 { define <2 x double> @constrained_vector_pow_v2f64(<2 x double> %x, <2 x double> %y) #0 {
; PC64LE-LABEL: constrained_vector_pow_v2f64: ; PC64LE-LABEL: constrained_vector_pow_v2f64:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -96(1) ; PC64LE-NEXT: stdu 1, -96(1)
; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: li 3, 48
; PC64LE-NEXT: std 0, 112(1)
; PC64LE-NEXT: stxvd2x 61, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 61, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: li 3, 64 ; PC64LE-NEXT: li 3, 64
; PC64LE-NEXT: stxvd2x 62, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 62, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: li 3, 80 ; PC64LE-NEXT: li 3, 80
; PC64LE-NEXT: vmr 30, 2 ; PC64LE-NEXT: vmr 30, 2
; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: vmr 31, 3 ; PC64LE-NEXT: vmr 31, 3
; PC64LE-NEXT: xxlor 1, 62, 62 ; PC64LE-NEXT: xxlor 1, 62, 62
Show All 18 Lines
; PC64LE-NEXT: addi 1, 1, 96 ; PC64LE-NEXT: addi 1, 1, 96
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_pow_v2f64: ; PC64LE9-LABEL: constrained_vector_pow_v2f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -80(1) ; PC64LE9-NEXT: stdu 1, -80(1)
; PC64LE9-NEXT: std 0, 96(1)
; PC64LE9-NEXT: stxv 62, 48(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 62, 48(1) # 16-byte Folded Spill
; PC64LE9-NEXT: stxv 63, 64(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 63, 64(1) # 16-byte Folded Spill
; PC64LE9-NEXT: vmr 31, 3 ; PC64LE9-NEXT: vmr 31, 3
; PC64LE9-NEXT: xscpsgndp 2, 63, 63 ; PC64LE9-NEXT: xscpsgndp 2, 63, 63
; PC64LE9-NEXT: vmr 30, 2 ; PC64LE9-NEXT: vmr 30, 2
; PC64LE9-NEXT: xscpsgndp 1, 62, 62 ; PC64LE9-NEXT: xscpsgndp 1, 62, 62
; PC64LE9-NEXT: stxv 61, 32(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 61, 32(1) # 16-byte Folded Spill
; PC64LE9-NEXT: bl pow ; PC64LE9-NEXT: bl pow
Show All 22 Lines %pow = call <2 x double> @llvm.experimental.constrained.pow.v2f64(
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <2 x double> %pow ret <2 x double> %pow
} }
define <3 x float> @constrained_vector_pow_v3f32(<3 x float> %x, <3 x float> %y) #0 { define <3 x float> @constrained_vector_pow_v3f32(<3 x float> %x, <3 x float> %y) #0 {
; PC64LE-LABEL: constrained_vector_pow_v3f32: ; PC64LE-LABEL: constrained_vector_pow_v3f32:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -96(1) ; PC64LE-NEXT: stdu 1, -96(1)
; PC64LE-NEXT: xxsldwi 0, 34, 34, 1 ; PC64LE-NEXT: xxsldwi 0, 34, 34, 1
; PC64LE-NEXT: xxsldwi 2, 35, 35, 1 ; PC64LE-NEXT: xxsldwi 2, 35, 35, 1
; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: li 3, 48
; PC64LE-NEXT: std 0, 112(1)
; PC64LE-NEXT: stxvd2x 62, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 62, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: li 3, 64 ; PC64LE-NEXT: li 3, 64
; PC64LE-NEXT: vmr 30, 2
; PC64LE-NEXT: stfd 30, 80(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 30, 80(1) # 8-byte Folded Spill
; PC64LE-NEXT: stfd 31, 88(1) # 8-byte Folded Spill
; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: xscvspdpn 1, 0 ; PC64LE-NEXT: xscvspdpn 1, 0
; PC64LE-NEXT: stfd 31, 88(1) # 8-byte Folded Spill
; PC64LE-NEXT: xscvspdpn 2, 2 ; PC64LE-NEXT: xscvspdpn 2, 2
; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: vmr 31, 3 ; PC64LE-NEXT: vmr 31, 3
; PC64LE-NEXT: vmr 30, 2
; PC64LE-NEXT: bl powf ; PC64LE-NEXT: bl powf
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: xxswapd 0, 62 ; PC64LE-NEXT: xxswapd 0, 62
; PC64LE-NEXT: xxswapd 2, 63 ; PC64LE-NEXT: xxswapd 2, 63
; PC64LE-NEXT: fmr 31, 1 ; PC64LE-NEXT: fmr 31, 1
; PC64LE-NEXT: xscvspdpn 1, 0 ; PC64LE-NEXT: xscvspdpn 1, 0
; PC64LE-NEXT: xscvspdpn 2, 2 ; PC64LE-NEXT: xscvspdpn 2, 2
; PC64LE-NEXT: bl powf ; PC64LE-NEXT: bl powf
Show All 23 Lines
; PC64LE-NEXT: addi 1, 1, 96 ; PC64LE-NEXT: addi 1, 1, 96
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_pow_v3f32: ; PC64LE9-LABEL: constrained_vector_pow_v3f32:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -80(1) ; PC64LE9-NEXT: stdu 1, -80(1)
; PC64LE9-NEXT: xxsldwi 0, 34, 34, 1 ; PC64LE9-NEXT: xxsldwi 0, 34, 34, 1
; PC64LE9-NEXT: std 0, 96(1)
; PC64LE9-NEXT: stfd 30, 64(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 30, 64(1) # 8-byte Folded Spill
; PC64LE9-NEXT: stfd 31, 72(1) # 8-byte Folded Spill
; PC64LE9-NEXT: stxv 62, 32(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 62, 32(1) # 16-byte Folded Spill
; PC64LE9-NEXT: stfd 31, 72(1) # 8-byte Folded Spill
; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill
; PC64LE9-NEXT: xscvspdpn 1, 0 ; PC64LE9-NEXT: xscvspdpn 1, 0
; PC64LE9-NEXT: xxsldwi 0, 35, 35, 1 ; PC64LE9-NEXT: xxsldwi 0, 35, 35, 1
; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill
; PC64LE9-NEXT: xscvspdpn 2, 0
; PC64LE9-NEXT: vmr 31, 3 ; PC64LE9-NEXT: vmr 31, 3
; PC64LE9-NEXT: vmr 30, 2 ; PC64LE9-NEXT: vmr 30, 2
; PC64LE9-NEXT: xscvspdpn 2, 0
; PC64LE9-NEXT: bl powf ; PC64LE9-NEXT: bl powf
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: xxswapd 0, 62 ; PC64LE9-NEXT: xxswapd 0, 62
; PC64LE9-NEXT: fmr 31, 1 ; PC64LE9-NEXT: fmr 31, 1
; PC64LE9-NEXT: xscvspdpn 1, 0 ; PC64LE9-NEXT: xscvspdpn 1, 0
; PC64LE9-NEXT: xxswapd 0, 63 ; PC64LE9-NEXT: xxswapd 0, 63
; PC64LE9-NEXT: xscvspdpn 2, 0 ; PC64LE9-NEXT: xscvspdpn 2, 0
; PC64LE9-NEXT: bl powf ; PC64LE9-NEXT: bl powf
Show All 29 Lines %pow = call <3 x float> @llvm.experimental.constrained.pow.v3f32(
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <3 x float> %pow ret <3 x float> %pow
} }
define <3 x double> @constrained_vector_pow_v3f64(<3 x double> %x, <3 x double> %y) #0 { define <3 x double> @constrained_vector_pow_v3f64(<3 x double> %x, <3 x double> %y) #0 {
; PC64LE-LABEL: constrained_vector_pow_v3f64: ; PC64LE-LABEL: constrained_vector_pow_v3f64:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -96(1) ; PC64LE-NEXT: stdu 1, -96(1)
; PC64LE-NEXT: std 0, 112(1)
; PC64LE-NEXT: stfd 28, 64(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 28, 64(1) # 8-byte Folded Spill
; PC64LE-NEXT: fmr 28, 2 ; PC64LE-NEXT: fmr 28, 2
; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: li 3, 48
; PC64LE-NEXT: fmr 2, 4 ; PC64LE-NEXT: fmr 2, 4
; PC64LE-NEXT: stfd 29, 72(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 29, 72(1) # 8-byte Folded Spill
; PC64LE-NEXT: stfd 30, 80(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 30, 80(1) # 8-byte Folded Spill
; PC64LE-NEXT: fmr 30, 5
; PC64LE-NEXT: stfd 31, 88(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 31, 88(1) # 8-byte Folded Spill
; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: fmr 31, 6 ; PC64LE-NEXT: fmr 31, 6
; PC64LE-NEXT: fmr 30, 5
; PC64LE-NEXT: fmr 29, 3 ; PC64LE-NEXT: fmr 29, 3
; PC64LE-NEXT: bl pow ; PC64LE-NEXT: bl pow
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: xxlor 63, 1, 1 ; PC64LE-NEXT: xxlor 63, 1, 1
; PC64LE-NEXT: fmr 1, 28 ; PC64LE-NEXT: fmr 1, 28
; PC64LE-NEXT: fmr 2, 30 ; PC64LE-NEXT: fmr 2, 30
; PC64LE-NEXT: bl pow ; PC64LE-NEXT: bl pow
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
Show All 16 Lines
; PC64LE-NEXT: addi 1, 1, 96 ; PC64LE-NEXT: addi 1, 1, 96
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_pow_v3f64: ; PC64LE9-LABEL: constrained_vector_pow_v3f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -80(1) ; PC64LE9-NEXT: stdu 1, -80(1)
; PC64LE9-NEXT: std 0, 96(1)
; PC64LE9-NEXT: stfd 28, 48(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 28, 48(1) # 8-byte Folded Spill
; PC64LE9-NEXT: fmr 28, 2
; PC64LE9-NEXT: stxv 63, 32(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 63, 32(1) # 16-byte Folded Spill
; PC64LE9-NEXT: fmr 28, 2
; PC64LE9-NEXT: fmr 2, 4 ; PC64LE9-NEXT: fmr 2, 4
; PC64LE9-NEXT: stfd 29, 56(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 29, 56(1) # 8-byte Folded Spill
; PC64LE9-NEXT: stfd 30, 64(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 30, 64(1) # 8-byte Folded Spill
; PC64LE9-NEXT: stfd 31, 72(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 31, 72(1) # 8-byte Folded Spill
; PC64LE9-NEXT: fmr 31, 6 ; PC64LE9-NEXT: fmr 31, 6
; PC64LE9-NEXT: fmr 30, 5 ; PC64LE9-NEXT: fmr 30, 5
; PC64LE9-NEXT: fmr 29, 3 ; PC64LE9-NEXT: fmr 29, 3
; PC64LE9-NEXT: bl pow ; PC64LE9-NEXT: bl pow
Show All 30 Lines %pow = call <3 x double> @llvm.experimental.constrained.pow.v3f64(
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <3 x double> %pow ret <3 x double> %pow
} }
define <4 x double> @constrained_vector_pow_v4f64(<4 x double> %x, <4 x double> %y) #0 { define <4 x double> @constrained_vector_pow_v4f64(<4 x double> %x, <4 x double> %y) #0 {
; PC64LE-LABEL: constrained_vector_pow_v4f64: ; PC64LE-LABEL: constrained_vector_pow_v4f64:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -128(1) ; PC64LE-NEXT: stdu 1, -128(1)
; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: li 3, 48
; PC64LE-NEXT: std 0, 144(1)
; PC64LE-NEXT: stxvd2x 59, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 59, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: li 3, 64 ; PC64LE-NEXT: li 3, 64
; PC64LE-NEXT: stxvd2x 60, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 60, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: li 3, 80 ; PC64LE-NEXT: li 3, 80
; PC64LE-NEXT: vmr 28, 2 ; PC64LE-NEXT: vmr 28, 2
; PC64LE-NEXT: stxvd2x 61, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 61, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: li 3, 96 ; PC64LE-NEXT: li 3, 96
; PC64LE-NEXT: vmr 29, 3 ; PC64LE-NEXT: vmr 29, 3
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
; PC64LE-NEXT: addi 1, 1, 128 ; PC64LE-NEXT: addi 1, 1, 128
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_pow_v4f64: ; PC64LE9-LABEL: constrained_vector_pow_v4f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -112(1) ; PC64LE9-NEXT: stdu 1, -112(1)
; PC64LE9-NEXT: std 0, 128(1)
; PC64LE9-NEXT: stxv 60, 48(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 60, 48(1) # 16-byte Folded Spill
; PC64LE9-NEXT: stxv 62, 80(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 62, 80(1) # 16-byte Folded Spill
; PC64LE9-NEXT: vmr 30, 4 ; PC64LE9-NEXT: vmr 30, 4
; PC64LE9-NEXT: xscpsgndp 2, 62, 62 ; PC64LE9-NEXT: xscpsgndp 2, 62, 62
; PC64LE9-NEXT: vmr 28, 2 ; PC64LE9-NEXT: vmr 28, 2
; PC64LE9-NEXT: xscpsgndp 1, 60, 60 ; PC64LE9-NEXT: xscpsgndp 1, 60, 60
; PC64LE9-NEXT: stxv 59, 32(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 59, 32(1) # 16-byte Folded Spill
; PC64LE9-NEXT: stxv 61, 64(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 61, 64(1) # 16-byte Folded Spill
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines %pow = call <4 x double> @llvm.experimental.constrained.pow.v4f64(
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <4 x double> %pow ret <4 x double> %pow
} }
define <1 x float> @constrained_vector_powi_v1f32(<1 x float> %x, i32 %y) #0 { define <1 x float> @constrained_vector_powi_v1f32(<1 x float> %x, i32 %y) #0 {
; PC64LE-LABEL: constrained_vector_powi_v1f32: ; PC64LE-LABEL: constrained_vector_powi_v1f32:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -32(1) ; PC64LE-NEXT: stdu 1, -32(1)
; PC64LE-NEXT: clrldi 4, 4, 32 ; PC64LE-NEXT: clrldi 4, 4, 32
; PC64LE-NEXT: std 0, 48(1)
; PC64LE-NEXT: bl __powisf2 ; PC64LE-NEXT: bl __powisf2
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: addi 1, 1, 32 ; PC64LE-NEXT: addi 1, 1, 32
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_powi_v1f32: ; PC64LE9-LABEL: constrained_vector_powi_v1f32:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -32(1) ; PC64LE9-NEXT: stdu 1, -32(1)
; PC64LE9-NEXT: clrldi 4, 4, 32 ; PC64LE9-NEXT: clrldi 4, 4, 32
; PC64LE9-NEXT: std 0, 48(1)
; PC64LE9-NEXT: bl __powisf2 ; PC64LE9-NEXT: bl __powisf2
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addi 1, 1, 32 ; PC64LE9-NEXT: addi 1, 1, 32
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%powi = call <1 x float> @llvm.experimental.constrained.powi.v1f32( %powi = call <1 x float> @llvm.experimental.constrained.powi.v1f32(
<1 x float> %x, <1 x float> %x,
i32 %y, i32 %y,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <1 x float> %powi ret <1 x float> %powi
} }
define <2 x double> @constrained_vector_powi_v2f64(<2 x double> %x, i32 %y) #0 { define <2 x double> @constrained_vector_powi_v2f64(<2 x double> %x, i32 %y) #0 {
; PC64LE-LABEL: constrained_vector_powi_v2f64: ; PC64LE-LABEL: constrained_vector_powi_v2f64:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -96(1) ; PC64LE-NEXT: stdu 1, -96(1)
; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: li 3, 48
; PC64LE-NEXT: std 0, 112(1)
; PC64LE-NEXT: std 30, 80(1) # 8-byte Folded Spill ; PC64LE-NEXT: std 30, 80(1) # 8-byte Folded Spill
; PC64LE-NEXT: clrldi 30, 5, 32 ; PC64LE-NEXT: clrldi 30, 5, 32
; PC64LE-NEXT: mr 4, 30
; PC64LE-NEXT: stxvd2x 62, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 62, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: li 3, 64 ; PC64LE-NEXT: li 3, 64
; PC64LE-NEXT: mr 4, 30
; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: vmr 31, 2 ; PC64LE-NEXT: vmr 31, 2
; PC64LE-NEXT: xxlor 1, 63, 63 ; PC64LE-NEXT: xxlor 1, 63, 63
; PC64LE-NEXT: bl __powidf2 ; PC64LE-NEXT: bl __powidf2
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: xxlor 62, 1, 1 ; PC64LE-NEXT: xxlor 62, 1, 1
; PC64LE-NEXT: xxswapd 1, 63 ; PC64LE-NEXT: xxswapd 1, 63
; PC64LE-NEXT: mr 4, 30 ; PC64LE-NEXT: mr 4, 30
Show All 10 Lines
; PC64LE-NEXT: addi 1, 1, 96 ; PC64LE-NEXT: addi 1, 1, 96
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_powi_v2f64: ; PC64LE9-LABEL: constrained_vector_powi_v2f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -80(1) ; PC64LE9-NEXT: stdu 1, -80(1)
; PC64LE9-NEXT: std 0, 96(1)
; PC64LE9-NEXT: std 30, 64(1) # 8-byte Folded Spill ; PC64LE9-NEXT: std 30, 64(1) # 8-byte Folded Spill
; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill
; PC64LE9-NEXT: vmr 31, 2 ; PC64LE9-NEXT: vmr 31, 2
; PC64LE9-NEXT: clrldi 30, 5, 32 ; PC64LE9-NEXT: clrldi 30, 5, 32
; PC64LE9-NEXT: stxv 62, 32(1) # 16-byte Folded Spill
; PC64LE9-NEXT: xscpsgndp 1, 63, 63 ; PC64LE9-NEXT: xscpsgndp 1, 63, 63
; PC64LE9-NEXT: mr 4, 30 ; PC64LE9-NEXT: mr 4, 30
; PC64LE9-NEXT: stxv 62, 32(1) # 16-byte Folded Spill
; PC64LE9-NEXT: bl __powidf2 ; PC64LE9-NEXT: bl __powidf2
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: mr 4, 30 ; PC64LE9-NEXT: mr 4, 30
; PC64LE9-NEXT: xscpsgndp 62, 1, 1 ; PC64LE9-NEXT: xscpsgndp 62, 1, 1
; PC64LE9-NEXT: xxswapd 1, 63 ; PC64LE9-NEXT: xxswapd 1, 63
; PC64LE9-NEXT: # kill: def $f1 killed $f1 killed $vsl1 ; PC64LE9-NEXT: # kill: def $f1 killed $f1 killed $vsl1
; PC64LE9-NEXT: bl __powidf2 ; PC64LE9-NEXT: bl __powidf2
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
Show All 16 Lines
} }
define <3 x float> @constrained_vector_powi_v3f32(<3 x float> %x, i32 %y) #0 { define <3 x float> @constrained_vector_powi_v3f32(<3 x float> %x, i32 %y) #0 {
; ;
; ;
; PC64LE-LABEL: constrained_vector_powi_v3f32: ; PC64LE-LABEL: constrained_vector_powi_v3f32:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -96(1) ; PC64LE-NEXT: stdu 1, -96(1)
; PC64LE-NEXT: xxsldwi 0, 34, 34, 1 ; PC64LE-NEXT: xxsldwi 0, 34, 34, 1
; PC64LE-NEXT: std 0, 112(1)
; PC64LE-NEXT: std 30, 64(1) # 8-byte Folded Spill ; PC64LE-NEXT: std 30, 64(1) # 8-byte Folded Spill
; PC64LE-NEXT: clrldi 30, 5, 32 ; PC64LE-NEXT: clrldi 30, 5, 32
; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: li 3, 48
; PC64LE-NEXT: stfd 30, 80(1) # 8-byte Folded Spill
; PC64LE-NEXT: mr 4, 30 ; PC64LE-NEXT: mr 4, 30
; PC64LE-NEXT: xscvspdpn 1, 0
; PC64LE-NEXT: stfd 30, 80(1) # 8-byte Folded Spill
; PC64LE-NEXT: stfd 31, 88(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 31, 88(1) # 8-byte Folded Spill
; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: vmr 31, 2 ; PC64LE-NEXT: vmr 31, 2
; PC64LE-NEXT: xscvspdpn 1, 0
; PC64LE-NEXT: bl __powisf2 ; PC64LE-NEXT: bl __powisf2
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: xxswapd 0, 63 ; PC64LE-NEXT: xxswapd 0, 63
; PC64LE-NEXT: fmr 31, 1 ; PC64LE-NEXT: fmr 31, 1
; PC64LE-NEXT: mr 4, 30 ; PC64LE-NEXT: mr 4, 30
; PC64LE-NEXT: xscvspdpn 1, 0 ; PC64LE-NEXT: xscvspdpn 1, 0
; PC64LE-NEXT: bl __powisf2 ; PC64LE-NEXT: bl __powisf2
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
Show All 20 Lines
; PC64LE-NEXT: addi 1, 1, 96 ; PC64LE-NEXT: addi 1, 1, 96
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_powi_v3f32: ; PC64LE9-LABEL: constrained_vector_powi_v3f32:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -80(1) ; PC64LE9-NEXT: stdu 1, -80(1)
; PC64LE9-NEXT: xxsldwi 0, 34, 34, 1 ; PC64LE9-NEXT: xxsldwi 0, 34, 34, 1
; PC64LE9-NEXT: std 0, 96(1)
; PC64LE9-NEXT: std 30, 48(1) # 8-byte Folded Spill ; PC64LE9-NEXT: std 30, 48(1) # 8-byte Folded Spill
; PC64LE9-NEXT: clrldi 30, 5, 32
; PC64LE9-NEXT: stxv 63, 32(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 63, 32(1) # 16-byte Folded Spill
; PC64LE9-NEXT: stfd 30, 64(1) # 8-byte Folded Spill ; PC64LE9-NEXT: clrldi 30, 5, 32
; PC64LE9-NEXT: vmr 31, 2 ; PC64LE9-NEXT: vmr 31, 2
; PC64LE9-NEXT: stfd 31, 72(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 30, 64(1) # 8-byte Folded Spill
; PC64LE9-NEXT: mr 4, 30 ; PC64LE9-NEXT: mr 4, 30
; PC64LE9-NEXT: stfd 31, 72(1) # 8-byte Folded Spill
; PC64LE9-NEXT: xscvspdpn 1, 0 ; PC64LE9-NEXT: xscvspdpn 1, 0
; PC64LE9-NEXT: bl __powisf2 ; PC64LE9-NEXT: bl __powisf2
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: xxswapd 0, 63 ; PC64LE9-NEXT: xxswapd 0, 63
; PC64LE9-NEXT: fmr 31, 1 ; PC64LE9-NEXT: fmr 31, 1
; PC64LE9-NEXT: mr 4, 30 ; PC64LE9-NEXT: mr 4, 30
; PC64LE9-NEXT: xscvspdpn 1, 0 ; PC64LE9-NEXT: xscvspdpn 1, 0
; PC64LE9-NEXT: bl __powisf2 ; PC64LE9-NEXT: bl __powisf2
Show All 28 Lines %powi = call <3 x float> @llvm.experimental.constrained.powi.v3f32(
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <3 x float> %powi ret <3 x float> %powi
} }
define <3 x double> @constrained_vector_powi_v3f64(<3 x double> %x, i32 %y) #0 { define <3 x double> @constrained_vector_powi_v3f64(<3 x double> %x, i32 %y) #0 {
; PC64LE-LABEL: constrained_vector_powi_v3f64: ; PC64LE-LABEL: constrained_vector_powi_v3f64:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -96(1) ; PC64LE-NEXT: stdu 1, -96(1)
; PC64LE-NEXT: std 0, 112(1)
; PC64LE-NEXT: std 30, 64(1) # 8-byte Folded Spill ; PC64LE-NEXT: std 30, 64(1) # 8-byte Folded Spill
; PC64LE-NEXT: clrldi 30, 6, 32 ; PC64LE-NEXT: clrldi 30, 6, 32
; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: li 3, 48
; PC64LE-NEXT: stfd 30, 80(1) # 8-byte Folded Spill
; PC64LE-NEXT: fmr 30, 2
; PC64LE-NEXT: mr 4, 30 ; PC64LE-NEXT: mr 4, 30
; PC64LE-NEXT: stfd 30, 80(1) # 8-byte Folded Spill
; PC64LE-NEXT: stfd 31, 88(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 31, 88(1) # 8-byte Folded Spill
; PC64LE-NEXT: fmr 31, 3
; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: fmr 31, 3
; PC64LE-NEXT: fmr 30, 2
; PC64LE-NEXT: bl __powidf2 ; PC64LE-NEXT: bl __powidf2
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: xxlor 63, 1, 1 ; PC64LE-NEXT: xxlor 63, 1, 1
; PC64LE-NEXT: fmr 1, 30 ; PC64LE-NEXT: fmr 1, 30
; PC64LE-NEXT: mr 4, 30 ; PC64LE-NEXT: mr 4, 30
; PC64LE-NEXT: bl __powidf2 ; PC64LE-NEXT: bl __powidf2
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1
Show All 14 Lines
; PC64LE-NEXT: addi 1, 1, 96 ; PC64LE-NEXT: addi 1, 1, 96
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_powi_v3f64: ; PC64LE9-LABEL: constrained_vector_powi_v3f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -80(1) ; PC64LE9-NEXT: stdu 1, -80(1)
; PC64LE9-NEXT: std 0, 96(1)
; PC64LE9-NEXT: std 30, 48(1) # 8-byte Folded Spill ; PC64LE9-NEXT: std 30, 48(1) # 8-byte Folded Spill
; PC64LE9-NEXT: clrldi 30, 6, 32
; PC64LE9-NEXT: stxv 63, 32(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 63, 32(1) # 16-byte Folded Spill
; PC64LE9-NEXT: clrldi 30, 6, 32
; PC64LE9-NEXT: mr 4, 30 ; PC64LE9-NEXT: mr 4, 30
; PC64LE9-NEXT: stfd 30, 64(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 30, 64(1) # 8-byte Folded Spill
; PC64LE9-NEXT: stfd 31, 72(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 31, 72(1) # 8-byte Folded Spill
; PC64LE9-NEXT: fmr 31, 3 ; PC64LE9-NEXT: fmr 31, 3
; PC64LE9-NEXT: fmr 30, 2 ; PC64LE9-NEXT: fmr 30, 2
; PC64LE9-NEXT: bl __powidf2 ; PC64LE9-NEXT: bl __powidf2
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: xscpsgndp 63, 1, 1 ; PC64LE9-NEXT: xscpsgndp 63, 1, 1
Show All 27 Lines %powi = call <3 x double> @llvm.experimental.constrained.powi.v3f64(
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <3 x double> %powi ret <3 x double> %powi
} }
define <4 x double> @constrained_vector_powi_v4f64(<4 x double> %x, i32 %y) #0 { define <4 x double> @constrained_vector_powi_v4f64(<4 x double> %x, i32 %y) #0 {
; PC64LE-LABEL: constrained_vector_powi_v4f64: ; PC64LE-LABEL: constrained_vector_powi_v4f64:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -112(1) ; PC64LE-NEXT: stdu 1, -112(1)
; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: li 3, 48
; PC64LE-NEXT: std 0, 128(1)
; PC64LE-NEXT: std 30, 96(1) # 8-byte Folded Spill ; PC64LE-NEXT: std 30, 96(1) # 8-byte Folded Spill
; PC64LE-NEXT: clrldi 30, 7, 32 ; PC64LE-NEXT: clrldi 30, 7, 32
; PC64LE-NEXT: mr 4, 30
; PC64LE-NEXT: stxvd2x 61, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 61, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: li 3, 64 ; PC64LE-NEXT: li 3, 64
; PC64LE-NEXT: mr 4, 30
; PC64LE-NEXT: stxvd2x 62, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 62, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: vmr 30, 2 ; PC64LE-NEXT: vmr 30, 2
; PC64LE-NEXT: li 3, 80 ; PC64LE-NEXT: li 3, 80
; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: vmr 31, 3 ; PC64LE-NEXT: vmr 31, 3
; PC64LE-NEXT: xxlor 1, 62, 62 ; PC64LE-NEXT: xxlor 1, 62, 62
; PC64LE-NEXT: bl __powidf2 ; PC64LE-NEXT: bl __powidf2
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
Show All 28 Lines
; PC64LE-NEXT: addi 1, 1, 112 ; PC64LE-NEXT: addi 1, 1, 112
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_powi_v4f64: ; PC64LE9-LABEL: constrained_vector_powi_v4f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -96(1) ; PC64LE9-NEXT: stdu 1, -96(1)
; PC64LE9-NEXT: std 0, 112(1)
; PC64LE9-NEXT: std 30, 80(1) # 8-byte Folded Spill ; PC64LE9-NEXT: std 30, 80(1) # 8-byte Folded Spill
; PC64LE9-NEXT: stxv 62, 48(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 62, 48(1) # 16-byte Folded Spill
; PC64LE9-NEXT: vmr 30, 2 ; PC64LE9-NEXT: vmr 30, 2
; PC64LE9-NEXT: clrldi 30, 7, 32 ; PC64LE9-NEXT: clrldi 30, 7, 32
; PC64LE9-NEXT: stxv 61, 32(1) # 16-byte Folded Spill
; PC64LE9-NEXT: xscpsgndp 1, 62, 62 ; PC64LE9-NEXT: xscpsgndp 1, 62, 62
; PC64LE9-NEXT: mr 4, 30 ; PC64LE9-NEXT: mr 4, 30
; PC64LE9-NEXT: stxv 61, 32(1) # 16-byte Folded Spill
; PC64LE9-NEXT: stxv 63, 64(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 63, 64(1) # 16-byte Folded Spill
; PC64LE9-NEXT: vmr 31, 3 ; PC64LE9-NEXT: vmr 31, 3
; PC64LE9-NEXT: bl __powidf2 ; PC64LE9-NEXT: bl __powidf2
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: mr 4, 30 ; PC64LE9-NEXT: mr 4, 30
; PC64LE9-NEXT: xscpsgndp 61, 1, 1 ; PC64LE9-NEXT: xscpsgndp 61, 1, 1
; PC64LE9-NEXT: xxswapd 1, 62 ; PC64LE9-NEXT: xxswapd 1, 62
; PC64LE9-NEXT: # kill: def $f1 killed $f1 killed $vsl1 ; PC64LE9-NEXT: # kill: def $f1 killed $f1 killed $vsl1
Show All 30 Lines %powi = call <4 x double> @llvm.experimental.constrained.powi.v4f64(
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <4 x double> %powi ret <4 x double> %powi
} }
define <1 x float> @constrained_vector_sin_v1f32(<1 x float> %x) #0 { define <1 x float> @constrained_vector_sin_v1f32(<1 x float> %x) #0 {
; PC64LE-LABEL: constrained_vector_sin_v1f32: ; PC64LE-LABEL: constrained_vector_sin_v1f32:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -32(1) ; PC64LE-NEXT: stdu 1, -32(1)
; PC64LE-NEXT: std 0, 48(1)
; PC64LE-NEXT: bl sinf ; PC64LE-NEXT: bl sinf
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: addi 1, 1, 32 ; PC64LE-NEXT: addi 1, 1, 32
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_sin_v1f32: ; PC64LE9-LABEL: constrained_vector_sin_v1f32:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -32(1) ; PC64LE9-NEXT: stdu 1, -32(1)
; PC64LE9-NEXT: std 0, 48(1)
; PC64LE9-NEXT: bl sinf ; PC64LE9-NEXT: bl sinf
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addi 1, 1, 32 ; PC64LE9-NEXT: addi 1, 1, 32
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%sin = call <1 x float> @llvm.experimental.constrained.sin.v1f32( %sin = call <1 x float> @llvm.experimental.constrained.sin.v1f32(
<1 x float> %x, <1 x float> %x,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <1 x float> %sin ret <1 x float> %sin
} }
define <2 x double> @constrained_vector_sin_v2f64(<2 x double> %x) #0 { define <2 x double> @constrained_vector_sin_v2f64(<2 x double> %x) #0 {
; PC64LE-LABEL: constrained_vector_sin_v2f64: ; PC64LE-LABEL: constrained_vector_sin_v2f64:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -80(1) ; PC64LE-NEXT: stdu 1, -80(1)
; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: li 3, 48
; PC64LE-NEXT: std 0, 96(1)
; PC64LE-NEXT: stxvd2x 62, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 62, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: li 3, 64 ; PC64LE-NEXT: li 3, 64
; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: vmr 31, 2 ; PC64LE-NEXT: vmr 31, 2
; PC64LE-NEXT: xxlor 1, 63, 63 ; PC64LE-NEXT: xxlor 1, 63, 63
; PC64LE-NEXT: bl sin ; PC64LE-NEXT: bl sin
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: xxlor 62, 1, 1 ; PC64LE-NEXT: xxlor 62, 1, 1
Show All 10 Lines
; PC64LE-NEXT: addi 1, 1, 80 ; PC64LE-NEXT: addi 1, 1, 80
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_sin_v2f64: ; PC64LE9-LABEL: constrained_vector_sin_v2f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -64(1) ; PC64LE9-NEXT: stdu 1, -64(1)
; PC64LE9-NEXT: std 0, 80(1)
; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill
; PC64LE9-NEXT: vmr 31, 2 ; PC64LE9-NEXT: vmr 31, 2
; PC64LE9-NEXT: xscpsgndp 1, 63, 63 ; PC64LE9-NEXT: xscpsgndp 1, 63, 63
; PC64LE9-NEXT: stxv 62, 32(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 62, 32(1) # 16-byte Folded Spill
; PC64LE9-NEXT: bl sin ; PC64LE9-NEXT: bl sin
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: xscpsgndp 62, 1, 1 ; PC64LE9-NEXT: xscpsgndp 62, 1, 1
; PC64LE9-NEXT: xxswapd 1, 63 ; PC64LE9-NEXT: xxswapd 1, 63
Show All 15 Lines %sin = call <2 x double> @llvm.experimental.constrained.sin.v2f64(
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <2 x double> %sin ret <2 x double> %sin
} }
define <3 x float> @constrained_vector_sin_v3f32(<3 x float> %x) #0 { define <3 x float> @constrained_vector_sin_v3f32(<3 x float> %x) #0 {
; PC64LE-LABEL: constrained_vector_sin_v3f32: ; PC64LE-LABEL: constrained_vector_sin_v3f32:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -80(1) ; PC64LE-NEXT: stdu 1, -80(1)
; PC64LE-NEXT: xxsldwi 0, 34, 34, 1 ; PC64LE-NEXT: xxsldwi 0, 34, 34, 1
; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: li 3, 48
; PC64LE-NEXT: std 0, 96(1)
; PC64LE-NEXT: stfd 30, 64(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 30, 64(1) # 8-byte Folded Spill
; PC64LE-NEXT: stfd 31, 72(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 31, 72(1) # 8-byte Folded Spill
; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: vmr 31, 2 ; PC64LE-NEXT: vmr 31, 2
; PC64LE-NEXT: xscvspdpn 1, 0 ; PC64LE-NEXT: xscvspdpn 1, 0
; PC64LE-NEXT: bl sinf ; PC64LE-NEXT: bl sinf
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: xxswapd 0, 63 ; PC64LE-NEXT: xxswapd 0, 63
Show All 22 Lines
; PC64LE-NEXT: addi 1, 1, 80 ; PC64LE-NEXT: addi 1, 1, 80
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_sin_v3f32: ; PC64LE9-LABEL: constrained_vector_sin_v3f32:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -64(1) ; PC64LE9-NEXT: stdu 1, -64(1)
; PC64LE9-NEXT: xxsldwi 0, 34, 34, 1 ; PC64LE9-NEXT: xxsldwi 0, 34, 34, 1
; PC64LE9-NEXT: std 0, 80(1)
; PC64LE9-NEXT: stfd 30, 48(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 30, 48(1) # 8-byte Folded Spill
; PC64LE9-NEXT: stfd 31, 56(1) # 8-byte Folded Spill
; PC64LE9-NEXT: stxv 63, 32(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 63, 32(1) # 16-byte Folded Spill
; PC64LE9-NEXT: xscvspdpn 1, 0 ; PC64LE9-NEXT: stfd 31, 56(1) # 8-byte Folded Spill
; PC64LE9-NEXT: vmr 31, 2 ; PC64LE9-NEXT: vmr 31, 2
; PC64LE9-NEXT: xscvspdpn 1, 0
; PC64LE9-NEXT: bl sinf ; PC64LE9-NEXT: bl sinf
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: xxswapd 0, 63 ; PC64LE9-NEXT: xxswapd 0, 63
; PC64LE9-NEXT: fmr 31, 1 ; PC64LE9-NEXT: fmr 31, 1
; PC64LE9-NEXT: xscvspdpn 1, 0 ; PC64LE9-NEXT: xscvspdpn 1, 0
; PC64LE9-NEXT: bl sinf ; PC64LE9-NEXT: bl sinf
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: xxsldwi 0, 63, 63, 3 ; PC64LE9-NEXT: xxsldwi 0, 63, 63, 3
Show All 23 Lines %sin = call <3 x float> @llvm.experimental.constrained.sin.v3f32(
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <3 x float> %sin ret <3 x float> %sin
} }
define <3 x double> @constrained_vector_sin_v3f64(<3 x double> %x) #0 { define <3 x double> @constrained_vector_sin_v3f64(<3 x double> %x) #0 {
; PC64LE-LABEL: constrained_vector_sin_v3f64: ; PC64LE-LABEL: constrained_vector_sin_v3f64:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -80(1) ; PC64LE-NEXT: stdu 1, -80(1)
; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: li 3, 48
; PC64LE-NEXT: std 0, 96(1)
; PC64LE-NEXT: stfd 30, 64(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 30, 64(1) # 8-byte Folded Spill
; PC64LE-NEXT: fmr 30, 2
; PC64LE-NEXT: stfd 31, 72(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 31, 72(1) # 8-byte Folded Spill
; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: fmr 31, 3 ; PC64LE-NEXT: fmr 31, 3
; PC64LE-NEXT: fmr 30, 2 ; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: bl sin ; PC64LE-NEXT: bl sin
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: xxlor 63, 1, 1 ; PC64LE-NEXT: xxlor 63, 1, 1
; PC64LE-NEXT: fmr 1, 30 ; PC64LE-NEXT: fmr 1, 30
; PC64LE-NEXT: bl sin ; PC64LE-NEXT: bl sin
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1
; PC64LE-NEXT: xxmrghd 63, 1, 63 ; PC64LE-NEXT: xxmrghd 63, 1, 63
Show All 11 Lines
; PC64LE-NEXT: addi 1, 1, 80 ; PC64LE-NEXT: addi 1, 1, 80
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_sin_v3f64: ; PC64LE9-LABEL: constrained_vector_sin_v3f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -64(1) ; PC64LE9-NEXT: stdu 1, -64(1)
; PC64LE9-NEXT: std 0, 80(1)
; PC64LE9-NEXT: stfd 30, 48(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 30, 48(1) # 8-byte Folded Spill
; PC64LE9-NEXT: stfd 31, 56(1) # 8-byte Folded Spill
; PC64LE9-NEXT: stxv 63, 32(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 63, 32(1) # 16-byte Folded Spill
; PC64LE9-NEXT: stfd 31, 56(1) # 8-byte Folded Spill
; PC64LE9-NEXT: fmr 31, 3 ; PC64LE9-NEXT: fmr 31, 3
; PC64LE9-NEXT: fmr 30, 2 ; PC64LE9-NEXT: fmr 30, 2
; PC64LE9-NEXT: bl sin ; PC64LE9-NEXT: bl sin
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: xscpsgndp 63, 1, 1 ; PC64LE9-NEXT: xscpsgndp 63, 1, 1
; PC64LE9-NEXT: fmr 1, 30 ; PC64LE9-NEXT: fmr 1, 30
; PC64LE9-NEXT: bl sin ; PC64LE9-NEXT: bl sin
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
Show All 20 Lines %sin = call <3 x double> @llvm.experimental.constrained.sin.v3f64(
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <3 x double> %sin ret <3 x double> %sin
} }
define <4 x double> @constrained_vector_sin_v4f64(<4 x double> %x) #0 { define <4 x double> @constrained_vector_sin_v4f64(<4 x double> %x) #0 {
; PC64LE-LABEL: constrained_vector_sin_v4f64: ; PC64LE-LABEL: constrained_vector_sin_v4f64:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -96(1) ; PC64LE-NEXT: stdu 1, -96(1)
; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: li 3, 48
; PC64LE-NEXT: std 0, 112(1)
; PC64LE-NEXT: stxvd2x 61, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 61, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: li 3, 64 ; PC64LE-NEXT: li 3, 64
; PC64LE-NEXT: stxvd2x 62, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 62, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: vmr 30, 2 ; PC64LE-NEXT: vmr 30, 2
; PC64LE-NEXT: li 3, 80 ; PC64LE-NEXT: li 3, 80
; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: vmr 31, 3 ; PC64LE-NEXT: vmr 31, 3
; PC64LE-NEXT: xxlor 1, 62, 62 ; PC64LE-NEXT: xxlor 1, 62, 62
Show All 26 Lines
; PC64LE-NEXT: addi 1, 1, 96 ; PC64LE-NEXT: addi 1, 1, 96
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_sin_v4f64: ; PC64LE9-LABEL: constrained_vector_sin_v4f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -80(1) ; PC64LE9-NEXT: stdu 1, -80(1)
; PC64LE9-NEXT: std 0, 96(1)
; PC64LE9-NEXT: stxv 62, 48(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 62, 48(1) # 16-byte Folded Spill
; PC64LE9-NEXT: vmr 30, 2 ; PC64LE9-NEXT: vmr 30, 2
; PC64LE9-NEXT: xscpsgndp 1, 62, 62 ; PC64LE9-NEXT: xscpsgndp 1, 62, 62
; PC64LE9-NEXT: stxv 61, 32(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 61, 32(1) # 16-byte Folded Spill
; PC64LE9-NEXT: stxv 63, 64(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 63, 64(1) # 16-byte Folded Spill
; PC64LE9-NEXT: vmr 31, 3 ; PC64LE9-NEXT: vmr 31, 3
; PC64LE9-NEXT: bl sin ; PC64LE9-NEXT: bl sin
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
Show All 29 Lines %sin = call <4 x double> @llvm.experimental.constrained.sin.v4f64(
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <4 x double> %sin ret <4 x double> %sin
} }
define <1 x float> @constrained_vector_cos_v1f32(<1 x float> %x) #0 { define <1 x float> @constrained_vector_cos_v1f32(<1 x float> %x) #0 {
; PC64LE-LABEL: constrained_vector_cos_v1f32: ; PC64LE-LABEL: constrained_vector_cos_v1f32:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -32(1) ; PC64LE-NEXT: stdu 1, -32(1)
; PC64LE-NEXT: std 0, 48(1)
; PC64LE-NEXT: bl cosf ; PC64LE-NEXT: bl cosf
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: addi 1, 1, 32 ; PC64LE-NEXT: addi 1, 1, 32
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_cos_v1f32: ; PC64LE9-LABEL: constrained_vector_cos_v1f32:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -32(1) ; PC64LE9-NEXT: stdu 1, -32(1)
; PC64LE9-NEXT: std 0, 48(1)
; PC64LE9-NEXT: bl cosf ; PC64LE9-NEXT: bl cosf
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addi 1, 1, 32 ; PC64LE9-NEXT: addi 1, 1, 32
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%cos = call <1 x float> @llvm.experimental.constrained.cos.v1f32( %cos = call <1 x float> @llvm.experimental.constrained.cos.v1f32(
<1 x float> %x, <1 x float> %x,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <1 x float> %cos ret <1 x float> %cos
} }
define <2 x double> @constrained_vector_cos_v2f64(<2 x double> %x) #0 { define <2 x double> @constrained_vector_cos_v2f64(<2 x double> %x) #0 {
; PC64LE-LABEL: constrained_vector_cos_v2f64: ; PC64LE-LABEL: constrained_vector_cos_v2f64:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -80(1) ; PC64LE-NEXT: stdu 1, -80(1)
; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: li 3, 48
; PC64LE-NEXT: std 0, 96(1)
; PC64LE-NEXT: stxvd2x 62, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 62, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: li 3, 64 ; PC64LE-NEXT: li 3, 64
; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: vmr 31, 2 ; PC64LE-NEXT: vmr 31, 2
; PC64LE-NEXT: xxlor 1, 63, 63 ; PC64LE-NEXT: xxlor 1, 63, 63
; PC64LE-NEXT: bl cos ; PC64LE-NEXT: bl cos
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: xxlor 62, 1, 1 ; PC64LE-NEXT: xxlor 62, 1, 1
Show All 10 Lines
; PC64LE-NEXT: addi 1, 1, 80 ; PC64LE-NEXT: addi 1, 1, 80
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_cos_v2f64: ; PC64LE9-LABEL: constrained_vector_cos_v2f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -64(1) ; PC64LE9-NEXT: stdu 1, -64(1)
; PC64LE9-NEXT: std 0, 80(1)
; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill
; PC64LE9-NEXT: vmr 31, 2 ; PC64LE9-NEXT: vmr 31, 2
; PC64LE9-NEXT: xscpsgndp 1, 63, 63 ; PC64LE9-NEXT: xscpsgndp 1, 63, 63
; PC64LE9-NEXT: stxv 62, 32(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 62, 32(1) # 16-byte Folded Spill
; PC64LE9-NEXT: bl cos ; PC64LE9-NEXT: bl cos
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: xscpsgndp 62, 1, 1 ; PC64LE9-NEXT: xscpsgndp 62, 1, 1
; PC64LE9-NEXT: xxswapd 1, 63 ; PC64LE9-NEXT: xxswapd 1, 63
Show All 15 Lines %cos = call <2 x double> @llvm.experimental.constrained.cos.v2f64(
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <2 x double> %cos ret <2 x double> %cos
} }
define <3 x float> @constrained_vector_cos_v3f32(<3 x float> %x) #0 { define <3 x float> @constrained_vector_cos_v3f32(<3 x float> %x) #0 {
; PC64LE-LABEL: constrained_vector_cos_v3f32: ; PC64LE-LABEL: constrained_vector_cos_v3f32:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -80(1) ; PC64LE-NEXT: stdu 1, -80(1)
; PC64LE-NEXT: xxsldwi 0, 34, 34, 1 ; PC64LE-NEXT: xxsldwi 0, 34, 34, 1
; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: li 3, 48
; PC64LE-NEXT: std 0, 96(1)
; PC64LE-NEXT: stfd 30, 64(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 30, 64(1) # 8-byte Folded Spill
; PC64LE-NEXT: stfd 31, 72(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 31, 72(1) # 8-byte Folded Spill
; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: vmr 31, 2 ; PC64LE-NEXT: vmr 31, 2
; PC64LE-NEXT: xscvspdpn 1, 0 ; PC64LE-NEXT: xscvspdpn 1, 0
; PC64LE-NEXT: bl cosf ; PC64LE-NEXT: bl cosf
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: xxswapd 0, 63 ; PC64LE-NEXT: xxswapd 0, 63
Show All 22 Lines
; PC64LE-NEXT: addi 1, 1, 80 ; PC64LE-NEXT: addi 1, 1, 80
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_cos_v3f32: ; PC64LE9-LABEL: constrained_vector_cos_v3f32:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -64(1) ; PC64LE9-NEXT: stdu 1, -64(1)
; PC64LE9-NEXT: xxsldwi 0, 34, 34, 1 ; PC64LE9-NEXT: xxsldwi 0, 34, 34, 1
; PC64LE9-NEXT: std 0, 80(1)
; PC64LE9-NEXT: stfd 30, 48(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 30, 48(1) # 8-byte Folded Spill
; PC64LE9-NEXT: stfd 31, 56(1) # 8-byte Folded Spill
; PC64LE9-NEXT: stxv 63, 32(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 63, 32(1) # 16-byte Folded Spill
; PC64LE9-NEXT: xscvspdpn 1, 0 ; PC64LE9-NEXT: stfd 31, 56(1) # 8-byte Folded Spill
; PC64LE9-NEXT: vmr 31, 2 ; PC64LE9-NEXT: vmr 31, 2
; PC64LE9-NEXT: xscvspdpn 1, 0
; PC64LE9-NEXT: bl cosf ; PC64LE9-NEXT: bl cosf
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: xxswapd 0, 63 ; PC64LE9-NEXT: xxswapd 0, 63
; PC64LE9-NEXT: fmr 31, 1 ; PC64LE9-NEXT: fmr 31, 1
; PC64LE9-NEXT: xscvspdpn 1, 0 ; PC64LE9-NEXT: xscvspdpn 1, 0
; PC64LE9-NEXT: bl cosf ; PC64LE9-NEXT: bl cosf
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: xxsldwi 0, 63, 63, 3 ; PC64LE9-NEXT: xxsldwi 0, 63, 63, 3
Show All 23 Lines %cos = call <3 x float> @llvm.experimental.constrained.cos.v3f32(
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <3 x float> %cos ret <3 x float> %cos
} }
define <3 x double> @constrained_vector_cos_v3f64(<3 x double> %x) #0 { define <3 x double> @constrained_vector_cos_v3f64(<3 x double> %x) #0 {
; PC64LE-LABEL: constrained_vector_cos_v3f64: ; PC64LE-LABEL: constrained_vector_cos_v3f64:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -80(1) ; PC64LE-NEXT: stdu 1, -80(1)
; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: li 3, 48
; PC64LE-NEXT: std 0, 96(1)
; PC64LE-NEXT: stfd 30, 64(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 30, 64(1) # 8-byte Folded Spill
; PC64LE-NEXT: fmr 30, 2
; PC64LE-NEXT: stfd 31, 72(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 31, 72(1) # 8-byte Folded Spill
; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: fmr 31, 3 ; PC64LE-NEXT: fmr 31, 3
; PC64LE-NEXT: fmr 30, 2 ; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: bl cos ; PC64LE-NEXT: bl cos
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: xxlor 63, 1, 1 ; PC64LE-NEXT: xxlor 63, 1, 1
; PC64LE-NEXT: fmr 1, 30 ; PC64LE-NEXT: fmr 1, 30
; PC64LE-NEXT: bl cos ; PC64LE-NEXT: bl cos
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1
; PC64LE-NEXT: xxmrghd 63, 1, 63 ; PC64LE-NEXT: xxmrghd 63, 1, 63
Show All 11 Lines
; PC64LE-NEXT: addi 1, 1, 80 ; PC64LE-NEXT: addi 1, 1, 80
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_cos_v3f64: ; PC64LE9-LABEL: constrained_vector_cos_v3f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -64(1) ; PC64LE9-NEXT: stdu 1, -64(1)
; PC64LE9-NEXT: std 0, 80(1)
; PC64LE9-NEXT: stfd 30, 48(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 30, 48(1) # 8-byte Folded Spill
; PC64LE9-NEXT: stfd 31, 56(1) # 8-byte Folded Spill
; PC64LE9-NEXT: stxv 63, 32(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 63, 32(1) # 16-byte Folded Spill
; PC64LE9-NEXT: stfd 31, 56(1) # 8-byte Folded Spill
; PC64LE9-NEXT: fmr 31, 3 ; PC64LE9-NEXT: fmr 31, 3
; PC64LE9-NEXT: fmr 30, 2 ; PC64LE9-NEXT: fmr 30, 2
; PC64LE9-NEXT: bl cos ; PC64LE9-NEXT: bl cos
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: xscpsgndp 63, 1, 1 ; PC64LE9-NEXT: xscpsgndp 63, 1, 1
; PC64LE9-NEXT: fmr 1, 30 ; PC64LE9-NEXT: fmr 1, 30
; PC64LE9-NEXT: bl cos ; PC64LE9-NEXT: bl cos
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
Show All 20 Lines %cos = call <3 x double> @llvm.experimental.constrained.cos.v3f64(
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <3 x double> %cos ret <3 x double> %cos
} }
define <4 x double> @constrained_vector_cos_v4f64(<4 x double> %x) #0 { define <4 x double> @constrained_vector_cos_v4f64(<4 x double> %x) #0 {
; PC64LE-LABEL: constrained_vector_cos_v4f64: ; PC64LE-LABEL: constrained_vector_cos_v4f64:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -96(1) ; PC64LE-NEXT: stdu 1, -96(1)
; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: li 3, 48
; PC64LE-NEXT: std 0, 112(1)
; PC64LE-NEXT: stxvd2x 61, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 61, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: li 3, 64 ; PC64LE-NEXT: li 3, 64
; PC64LE-NEXT: stxvd2x 62, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 62, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: vmr 30, 2 ; PC64LE-NEXT: vmr 30, 2
; PC64LE-NEXT: li 3, 80 ; PC64LE-NEXT: li 3, 80
; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: vmr 31, 3 ; PC64LE-NEXT: vmr 31, 3
; PC64LE-NEXT: xxlor 1, 62, 62 ; PC64LE-NEXT: xxlor 1, 62, 62
Show All 26 Lines
; PC64LE-NEXT: addi 1, 1, 96 ; PC64LE-NEXT: addi 1, 1, 96
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_cos_v4f64: ; PC64LE9-LABEL: constrained_vector_cos_v4f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -80(1) ; PC64LE9-NEXT: stdu 1, -80(1)
; PC64LE9-NEXT: std 0, 96(1)
; PC64LE9-NEXT: stxv 62, 48(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 62, 48(1) # 16-byte Folded Spill
; PC64LE9-NEXT: vmr 30, 2 ; PC64LE9-NEXT: vmr 30, 2
; PC64LE9-NEXT: xscpsgndp 1, 62, 62 ; PC64LE9-NEXT: xscpsgndp 1, 62, 62
; PC64LE9-NEXT: stxv 61, 32(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 61, 32(1) # 16-byte Folded Spill
; PC64LE9-NEXT: stxv 63, 64(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 63, 64(1) # 16-byte Folded Spill
; PC64LE9-NEXT: vmr 31, 3 ; PC64LE9-NEXT: vmr 31, 3
; PC64LE9-NEXT: bl cos ; PC64LE9-NEXT: bl cos
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
Show All 29 Lines %cos = call <4 x double> @llvm.experimental.constrained.cos.v4f64(
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <4 x double> %cos ret <4 x double> %cos
} }
define <1 x float> @constrained_vector_exp_v1f32(<1 x float> %x) #0 { define <1 x float> @constrained_vector_exp_v1f32(<1 x float> %x) #0 {
; PC64LE-LABEL: constrained_vector_exp_v1f32: ; PC64LE-LABEL: constrained_vector_exp_v1f32:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -32(1) ; PC64LE-NEXT: stdu 1, -32(1)
; PC64LE-NEXT: std 0, 48(1)
; PC64LE-NEXT: bl expf ; PC64LE-NEXT: bl expf
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: addi 1, 1, 32 ; PC64LE-NEXT: addi 1, 1, 32
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_exp_v1f32: ; PC64LE9-LABEL: constrained_vector_exp_v1f32:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -32(1) ; PC64LE9-NEXT: stdu 1, -32(1)
; PC64LE9-NEXT: std 0, 48(1)
; PC64LE9-NEXT: bl expf ; PC64LE9-NEXT: bl expf
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addi 1, 1, 32 ; PC64LE9-NEXT: addi 1, 1, 32
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%exp = call <1 x float> @llvm.experimental.constrained.exp.v1f32( %exp = call <1 x float> @llvm.experimental.constrained.exp.v1f32(
<1 x float> %x, <1 x float> %x,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <1 x float> %exp ret <1 x float> %exp
} }
define <2 x double> @constrained_vector_exp_v2f64(<2 x double> %x) #0 { define <2 x double> @constrained_vector_exp_v2f64(<2 x double> %x) #0 {
; PC64LE-LABEL: constrained_vector_exp_v2f64: ; PC64LE-LABEL: constrained_vector_exp_v2f64:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -80(1) ; PC64LE-NEXT: stdu 1, -80(1)
; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: li 3, 48
; PC64LE-NEXT: std 0, 96(1)
; PC64LE-NEXT: stxvd2x 62, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 62, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: li 3, 64 ; PC64LE-NEXT: li 3, 64
; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: vmr 31, 2 ; PC64LE-NEXT: vmr 31, 2
; PC64LE-NEXT: xxlor 1, 63, 63 ; PC64LE-NEXT: xxlor 1, 63, 63
; PC64LE-NEXT: bl exp ; PC64LE-NEXT: bl exp
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: xxlor 62, 1, 1 ; PC64LE-NEXT: xxlor 62, 1, 1
Show All 10 Lines
; PC64LE-NEXT: addi 1, 1, 80 ; PC64LE-NEXT: addi 1, 1, 80
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_exp_v2f64: ; PC64LE9-LABEL: constrained_vector_exp_v2f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -64(1) ; PC64LE9-NEXT: stdu 1, -64(1)
; PC64LE9-NEXT: std 0, 80(1)
; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill
; PC64LE9-NEXT: vmr 31, 2 ; PC64LE9-NEXT: vmr 31, 2
; PC64LE9-NEXT: xscpsgndp 1, 63, 63 ; PC64LE9-NEXT: xscpsgndp 1, 63, 63
; PC64LE9-NEXT: stxv 62, 32(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 62, 32(1) # 16-byte Folded Spill
; PC64LE9-NEXT: bl exp ; PC64LE9-NEXT: bl exp
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: xscpsgndp 62, 1, 1 ; PC64LE9-NEXT: xscpsgndp 62, 1, 1
; PC64LE9-NEXT: xxswapd 1, 63 ; PC64LE9-NEXT: xxswapd 1, 63
Show All 15 Lines %exp = call <2 x double> @llvm.experimental.constrained.exp.v2f64(
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <2 x double> %exp ret <2 x double> %exp
} }
define <3 x float> @constrained_vector_exp_v3f32(<3 x float> %x) #0 { define <3 x float> @constrained_vector_exp_v3f32(<3 x float> %x) #0 {
; PC64LE-LABEL: constrained_vector_exp_v3f32: ; PC64LE-LABEL: constrained_vector_exp_v3f32:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -80(1) ; PC64LE-NEXT: stdu 1, -80(1)
; PC64LE-NEXT: xxsldwi 0, 34, 34, 1 ; PC64LE-NEXT: xxsldwi 0, 34, 34, 1
; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: li 3, 48
; PC64LE-NEXT: std 0, 96(1)
; PC64LE-NEXT: stfd 30, 64(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 30, 64(1) # 8-byte Folded Spill
; PC64LE-NEXT: stfd 31, 72(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 31, 72(1) # 8-byte Folded Spill
; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: vmr 31, 2 ; PC64LE-NEXT: vmr 31, 2
; PC64LE-NEXT: xscvspdpn 1, 0 ; PC64LE-NEXT: xscvspdpn 1, 0
; PC64LE-NEXT: bl expf ; PC64LE-NEXT: bl expf
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: xxswapd 0, 63 ; PC64LE-NEXT: xxswapd 0, 63
Show All 22 Lines
; PC64LE-NEXT: addi 1, 1, 80 ; PC64LE-NEXT: addi 1, 1, 80
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_exp_v3f32: ; PC64LE9-LABEL: constrained_vector_exp_v3f32:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -64(1) ; PC64LE9-NEXT: stdu 1, -64(1)
; PC64LE9-NEXT: xxsldwi 0, 34, 34, 1 ; PC64LE9-NEXT: xxsldwi 0, 34, 34, 1
; PC64LE9-NEXT: std 0, 80(1)
; PC64LE9-NEXT: stfd 30, 48(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 30, 48(1) # 8-byte Folded Spill
; PC64LE9-NEXT: stfd 31, 56(1) # 8-byte Folded Spill
; PC64LE9-NEXT: stxv 63, 32(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 63, 32(1) # 16-byte Folded Spill
; PC64LE9-NEXT: xscvspdpn 1, 0 ; PC64LE9-NEXT: stfd 31, 56(1) # 8-byte Folded Spill
; PC64LE9-NEXT: vmr 31, 2 ; PC64LE9-NEXT: vmr 31, 2
; PC64LE9-NEXT: xscvspdpn 1, 0
; PC64LE9-NEXT: bl expf ; PC64LE9-NEXT: bl expf
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: xxswapd 0, 63 ; PC64LE9-NEXT: xxswapd 0, 63
; PC64LE9-NEXT: fmr 31, 1 ; PC64LE9-NEXT: fmr 31, 1
; PC64LE9-NEXT: xscvspdpn 1, 0 ; PC64LE9-NEXT: xscvspdpn 1, 0
; PC64LE9-NEXT: bl expf ; PC64LE9-NEXT: bl expf
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: xxsldwi 0, 63, 63, 3 ; PC64LE9-NEXT: xxsldwi 0, 63, 63, 3
Show All 23 Lines %exp = call <3 x float> @llvm.experimental.constrained.exp.v3f32(
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <3 x float> %exp ret <3 x float> %exp
} }
define <3 x double> @constrained_vector_exp_v3f64(<3 x double> %x) #0 { define <3 x double> @constrained_vector_exp_v3f64(<3 x double> %x) #0 {
; PC64LE-LABEL: constrained_vector_exp_v3f64: ; PC64LE-LABEL: constrained_vector_exp_v3f64:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -80(1) ; PC64LE-NEXT: stdu 1, -80(1)
; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: li 3, 48
; PC64LE-NEXT: std 0, 96(1)
; PC64LE-NEXT: stfd 30, 64(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 30, 64(1) # 8-byte Folded Spill
; PC64LE-NEXT: fmr 30, 2
; PC64LE-NEXT: stfd 31, 72(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 31, 72(1) # 8-byte Folded Spill
; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: fmr 31, 3 ; PC64LE-NEXT: fmr 31, 3
; PC64LE-NEXT: fmr 30, 2 ; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: bl exp ; PC64LE-NEXT: bl exp
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: xxlor 63, 1, 1 ; PC64LE-NEXT: xxlor 63, 1, 1
; PC64LE-NEXT: fmr 1, 30 ; PC64LE-NEXT: fmr 1, 30
; PC64LE-NEXT: bl exp ; PC64LE-NEXT: bl exp
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1
; PC64LE-NEXT: xxmrghd 63, 1, 63 ; PC64LE-NEXT: xxmrghd 63, 1, 63
Show All 11 Lines
; PC64LE-NEXT: addi 1, 1, 80 ; PC64LE-NEXT: addi 1, 1, 80
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_exp_v3f64: ; PC64LE9-LABEL: constrained_vector_exp_v3f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -64(1) ; PC64LE9-NEXT: stdu 1, -64(1)
; PC64LE9-NEXT: std 0, 80(1)
; PC64LE9-NEXT: stfd 30, 48(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 30, 48(1) # 8-byte Folded Spill
; PC64LE9-NEXT: stfd 31, 56(1) # 8-byte Folded Spill
; PC64LE9-NEXT: stxv 63, 32(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 63, 32(1) # 16-byte Folded Spill
; PC64LE9-NEXT: stfd 31, 56(1) # 8-byte Folded Spill
; PC64LE9-NEXT: fmr 31, 3 ; PC64LE9-NEXT: fmr 31, 3
; PC64LE9-NEXT: fmr 30, 2 ; PC64LE9-NEXT: fmr 30, 2
; PC64LE9-NEXT: bl exp ; PC64LE9-NEXT: bl exp
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: xscpsgndp 63, 1, 1 ; PC64LE9-NEXT: xscpsgndp 63, 1, 1
; PC64LE9-NEXT: fmr 1, 30 ; PC64LE9-NEXT: fmr 1, 30
; PC64LE9-NEXT: bl exp ; PC64LE9-NEXT: bl exp
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
Show All 20 Lines %exp = call <3 x double> @llvm.experimental.constrained.exp.v3f64(
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <3 x double> %exp ret <3 x double> %exp
} }
define <4 x double> @constrained_vector_exp_v4f64(<4 x double> %x) #0 { define <4 x double> @constrained_vector_exp_v4f64(<4 x double> %x) #0 {
; PC64LE-LABEL: constrained_vector_exp_v4f64: ; PC64LE-LABEL: constrained_vector_exp_v4f64:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -96(1) ; PC64LE-NEXT: stdu 1, -96(1)
; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: li 3, 48
; PC64LE-NEXT: std 0, 112(1)
; PC64LE-NEXT: stxvd2x 61, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 61, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: li 3, 64 ; PC64LE-NEXT: li 3, 64
; PC64LE-NEXT: stxvd2x 62, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 62, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: vmr 30, 2 ; PC64LE-NEXT: vmr 30, 2
; PC64LE-NEXT: li 3, 80 ; PC64LE-NEXT: li 3, 80
; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: vmr 31, 3 ; PC64LE-NEXT: vmr 31, 3
; PC64LE-NEXT: xxlor 1, 62, 62 ; PC64LE-NEXT: xxlor 1, 62, 62
Show All 26 Lines
; PC64LE-NEXT: addi 1, 1, 96 ; PC64LE-NEXT: addi 1, 1, 96
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_exp_v4f64: ; PC64LE9-LABEL: constrained_vector_exp_v4f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -80(1) ; PC64LE9-NEXT: stdu 1, -80(1)
; PC64LE9-NEXT: std 0, 96(1)
; PC64LE9-NEXT: stxv 62, 48(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 62, 48(1) # 16-byte Folded Spill
; PC64LE9-NEXT: vmr 30, 2 ; PC64LE9-NEXT: vmr 30, 2
; PC64LE9-NEXT: xscpsgndp 1, 62, 62 ; PC64LE9-NEXT: xscpsgndp 1, 62, 62
; PC64LE9-NEXT: stxv 61, 32(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 61, 32(1) # 16-byte Folded Spill
; PC64LE9-NEXT: stxv 63, 64(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 63, 64(1) # 16-byte Folded Spill
; PC64LE9-NEXT: vmr 31, 3 ; PC64LE9-NEXT: vmr 31, 3
; PC64LE9-NEXT: bl exp ; PC64LE9-NEXT: bl exp
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
Show All 29 Lines %exp = call <4 x double> @llvm.experimental.constrained.exp.v4f64(
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <4 x double> %exp ret <4 x double> %exp
} }
define <1 x float> @constrained_vector_exp2_v1f32(<1 x float> %x) #0 { define <1 x float> @constrained_vector_exp2_v1f32(<1 x float> %x) #0 {
; PC64LE-LABEL: constrained_vector_exp2_v1f32: ; PC64LE-LABEL: constrained_vector_exp2_v1f32:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -32(1) ; PC64LE-NEXT: stdu 1, -32(1)
; PC64LE-NEXT: std 0, 48(1)
; PC64LE-NEXT: bl exp2f ; PC64LE-NEXT: bl exp2f
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: addi 1, 1, 32 ; PC64LE-NEXT: addi 1, 1, 32
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_exp2_v1f32: ; PC64LE9-LABEL: constrained_vector_exp2_v1f32:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -32(1) ; PC64LE9-NEXT: stdu 1, -32(1)
; PC64LE9-NEXT: std 0, 48(1)
; PC64LE9-NEXT: bl exp2f ; PC64LE9-NEXT: bl exp2f
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addi 1, 1, 32 ; PC64LE9-NEXT: addi 1, 1, 32
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%exp2 = call <1 x float> @llvm.experimental.constrained.exp2.v1f32( %exp2 = call <1 x float> @llvm.experimental.constrained.exp2.v1f32(
<1 x float> %x, <1 x float> %x,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <1 x float> %exp2 ret <1 x float> %exp2
} }
define <2 x double> @constrained_vector_exp2_v2f64(<2 x double> %x) #0 { define <2 x double> @constrained_vector_exp2_v2f64(<2 x double> %x) #0 {
; PC64LE-LABEL: constrained_vector_exp2_v2f64: ; PC64LE-LABEL: constrained_vector_exp2_v2f64:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -80(1) ; PC64LE-NEXT: stdu 1, -80(1)
; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: li 3, 48
; PC64LE-NEXT: std 0, 96(1)
; PC64LE-NEXT: stxvd2x 62, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 62, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: li 3, 64 ; PC64LE-NEXT: li 3, 64
; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: vmr 31, 2 ; PC64LE-NEXT: vmr 31, 2
; PC64LE-NEXT: xxlor 1, 63, 63 ; PC64LE-NEXT: xxlor 1, 63, 63
; PC64LE-NEXT: bl exp2 ; PC64LE-NEXT: bl exp2
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: xxlor 62, 1, 1 ; PC64LE-NEXT: xxlor 62, 1, 1
Show All 10 Lines
; PC64LE-NEXT: addi 1, 1, 80 ; PC64LE-NEXT: addi 1, 1, 80
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_exp2_v2f64: ; PC64LE9-LABEL: constrained_vector_exp2_v2f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -64(1) ; PC64LE9-NEXT: stdu 1, -64(1)
; PC64LE9-NEXT: std 0, 80(1)
; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill
; PC64LE9-NEXT: vmr 31, 2 ; PC64LE9-NEXT: vmr 31, 2
; PC64LE9-NEXT: xscpsgndp 1, 63, 63 ; PC64LE9-NEXT: xscpsgndp 1, 63, 63
; PC64LE9-NEXT: stxv 62, 32(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 62, 32(1) # 16-byte Folded Spill
; PC64LE9-NEXT: bl exp2 ; PC64LE9-NEXT: bl exp2
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: xscpsgndp 62, 1, 1 ; PC64LE9-NEXT: xscpsgndp 62, 1, 1
; PC64LE9-NEXT: xxswapd 1, 63 ; PC64LE9-NEXT: xxswapd 1, 63
Show All 15 Lines %exp2 = call <2 x double> @llvm.experimental.constrained.exp2.v2f64(
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <2 x double> %exp2 ret <2 x double> %exp2
} }
define <3 x float> @constrained_vector_exp2_v3f32(<3 x float> %x) #0 { define <3 x float> @constrained_vector_exp2_v3f32(<3 x float> %x) #0 {
; PC64LE-LABEL: constrained_vector_exp2_v3f32: ; PC64LE-LABEL: constrained_vector_exp2_v3f32:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -80(1) ; PC64LE-NEXT: stdu 1, -80(1)
; PC64LE-NEXT: xxsldwi 0, 34, 34, 1 ; PC64LE-NEXT: xxsldwi 0, 34, 34, 1
; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: li 3, 48
; PC64LE-NEXT: std 0, 96(1)
; PC64LE-NEXT: stfd 30, 64(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 30, 64(1) # 8-byte Folded Spill
; PC64LE-NEXT: stfd 31, 72(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 31, 72(1) # 8-byte Folded Spill
; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: vmr 31, 2 ; PC64LE-NEXT: vmr 31, 2
; PC64LE-NEXT: xscvspdpn 1, 0 ; PC64LE-NEXT: xscvspdpn 1, 0
; PC64LE-NEXT: bl exp2f ; PC64LE-NEXT: bl exp2f
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: xxswapd 0, 63 ; PC64LE-NEXT: xxswapd 0, 63
Show All 22 Lines
; PC64LE-NEXT: addi 1, 1, 80 ; PC64LE-NEXT: addi 1, 1, 80
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_exp2_v3f32: ; PC64LE9-LABEL: constrained_vector_exp2_v3f32:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -64(1) ; PC64LE9-NEXT: stdu 1, -64(1)
; PC64LE9-NEXT: xxsldwi 0, 34, 34, 1 ; PC64LE9-NEXT: xxsldwi 0, 34, 34, 1
; PC64LE9-NEXT: std 0, 80(1)
; PC64LE9-NEXT: stfd 30, 48(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 30, 48(1) # 8-byte Folded Spill
; PC64LE9-NEXT: stfd 31, 56(1) # 8-byte Folded Spill
; PC64LE9-NEXT: stxv 63, 32(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 63, 32(1) # 16-byte Folded Spill
; PC64LE9-NEXT: xscvspdpn 1, 0 ; PC64LE9-NEXT: stfd 31, 56(1) # 8-byte Folded Spill
; PC64LE9-NEXT: vmr 31, 2 ; PC64LE9-NEXT: vmr 31, 2
; PC64LE9-NEXT: xscvspdpn 1, 0
; PC64LE9-NEXT: bl exp2f ; PC64LE9-NEXT: bl exp2f
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: xxswapd 0, 63 ; PC64LE9-NEXT: xxswapd 0, 63
; PC64LE9-NEXT: fmr 31, 1 ; PC64LE9-NEXT: fmr 31, 1
; PC64LE9-NEXT: xscvspdpn 1, 0 ; PC64LE9-NEXT: xscvspdpn 1, 0
; PC64LE9-NEXT: bl exp2f ; PC64LE9-NEXT: bl exp2f
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: xxsldwi 0, 63, 63, 3 ; PC64LE9-NEXT: xxsldwi 0, 63, 63, 3
Show All 23 Lines %exp2 = call <3 x float> @llvm.experimental.constrained.exp2.v3f32(
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <3 x float> %exp2 ret <3 x float> %exp2
} }
define <3 x double> @constrained_vector_exp2_v3f64(<3 x double> %x) #0 { define <3 x double> @constrained_vector_exp2_v3f64(<3 x double> %x) #0 {
; PC64LE-LABEL: constrained_vector_exp2_v3f64: ; PC64LE-LABEL: constrained_vector_exp2_v3f64:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -80(1) ; PC64LE-NEXT: stdu 1, -80(1)
; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: li 3, 48
; PC64LE-NEXT: std 0, 96(1)
; PC64LE-NEXT: stfd 30, 64(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 30, 64(1) # 8-byte Folded Spill
; PC64LE-NEXT: fmr 30, 2
; PC64LE-NEXT: stfd 31, 72(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 31, 72(1) # 8-byte Folded Spill
; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: fmr 31, 3 ; PC64LE-NEXT: fmr 31, 3
; PC64LE-NEXT: fmr 30, 2 ; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: bl exp2 ; PC64LE-NEXT: bl exp2
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: xxlor 63, 1, 1 ; PC64LE-NEXT: xxlor 63, 1, 1
; PC64LE-NEXT: fmr 1, 30 ; PC64LE-NEXT: fmr 1, 30
; PC64LE-NEXT: bl exp2 ; PC64LE-NEXT: bl exp2
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1
; PC64LE-NEXT: xxmrghd 63, 1, 63 ; PC64LE-NEXT: xxmrghd 63, 1, 63
Show All 11 Lines
; PC64LE-NEXT: addi 1, 1, 80 ; PC64LE-NEXT: addi 1, 1, 80
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_exp2_v3f64: ; PC64LE9-LABEL: constrained_vector_exp2_v3f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -64(1) ; PC64LE9-NEXT: stdu 1, -64(1)
; PC64LE9-NEXT: std 0, 80(1)
; PC64LE9-NEXT: stfd 30, 48(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 30, 48(1) # 8-byte Folded Spill
; PC64LE9-NEXT: stfd 31, 56(1) # 8-byte Folded Spill
; PC64LE9-NEXT: stxv 63, 32(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 63, 32(1) # 16-byte Folded Spill
; PC64LE9-NEXT: stfd 31, 56(1) # 8-byte Folded Spill
; PC64LE9-NEXT: fmr 31, 3 ; PC64LE9-NEXT: fmr 31, 3
; PC64LE9-NEXT: fmr 30, 2 ; PC64LE9-NEXT: fmr 30, 2
; PC64LE9-NEXT: bl exp2 ; PC64LE9-NEXT: bl exp2
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: xscpsgndp 63, 1, 1 ; PC64LE9-NEXT: xscpsgndp 63, 1, 1
; PC64LE9-NEXT: fmr 1, 30 ; PC64LE9-NEXT: fmr 1, 30
; PC64LE9-NEXT: bl exp2 ; PC64LE9-NEXT: bl exp2
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
Show All 20 Lines %exp2 = call <3 x double> @llvm.experimental.constrained.exp2.v3f64(
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <3 x double> %exp2 ret <3 x double> %exp2
} }
define <4 x double> @constrained_vector_exp2_v4f64(<4 x double> %x) #0 { define <4 x double> @constrained_vector_exp2_v4f64(<4 x double> %x) #0 {
; PC64LE-LABEL: constrained_vector_exp2_v4f64: ; PC64LE-LABEL: constrained_vector_exp2_v4f64:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -96(1) ; PC64LE-NEXT: stdu 1, -96(1)
; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: li 3, 48
; PC64LE-NEXT: std 0, 112(1)
; PC64LE-NEXT: stxvd2x 61, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 61, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: li 3, 64 ; PC64LE-NEXT: li 3, 64
; PC64LE-NEXT: stxvd2x 62, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 62, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: vmr 30, 2 ; PC64LE-NEXT: vmr 30, 2
; PC64LE-NEXT: li 3, 80 ; PC64LE-NEXT: li 3, 80
; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: vmr 31, 3 ; PC64LE-NEXT: vmr 31, 3
; PC64LE-NEXT: xxlor 1, 62, 62 ; PC64LE-NEXT: xxlor 1, 62, 62
Show All 26 Lines
; PC64LE-NEXT: addi 1, 1, 96 ; PC64LE-NEXT: addi 1, 1, 96
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_exp2_v4f64: ; PC64LE9-LABEL: constrained_vector_exp2_v4f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -80(1) ; PC64LE9-NEXT: stdu 1, -80(1)
; PC64LE9-NEXT: std 0, 96(1)
; PC64LE9-NEXT: stxv 62, 48(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 62, 48(1) # 16-byte Folded Spill
; PC64LE9-NEXT: vmr 30, 2 ; PC64LE9-NEXT: vmr 30, 2
; PC64LE9-NEXT: xscpsgndp 1, 62, 62 ; PC64LE9-NEXT: xscpsgndp 1, 62, 62
; PC64LE9-NEXT: stxv 61, 32(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 61, 32(1) # 16-byte Folded Spill
; PC64LE9-NEXT: stxv 63, 64(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 63, 64(1) # 16-byte Folded Spill
; PC64LE9-NEXT: vmr 31, 3 ; PC64LE9-NEXT: vmr 31, 3
; PC64LE9-NEXT: bl exp2 ; PC64LE9-NEXT: bl exp2
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
Show All 29 Lines %exp2 = call <4 x double> @llvm.experimental.constrained.exp2.v4f64(
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <4 x double> %exp2 ret <4 x double> %exp2
} }
define <1 x float> @constrained_vector_log_v1f32(<1 x float> %x) #0 { define <1 x float> @constrained_vector_log_v1f32(<1 x float> %x) #0 {
; PC64LE-LABEL: constrained_vector_log_v1f32: ; PC64LE-LABEL: constrained_vector_log_v1f32:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -32(1) ; PC64LE-NEXT: stdu 1, -32(1)
; PC64LE-NEXT: std 0, 48(1)
; PC64LE-NEXT: bl logf ; PC64LE-NEXT: bl logf
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: addi 1, 1, 32 ; PC64LE-NEXT: addi 1, 1, 32
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_log_v1f32: ; PC64LE9-LABEL: constrained_vector_log_v1f32:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -32(1) ; PC64LE9-NEXT: stdu 1, -32(1)
; PC64LE9-NEXT: std 0, 48(1)
; PC64LE9-NEXT: bl logf ; PC64LE9-NEXT: bl logf
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addi 1, 1, 32 ; PC64LE9-NEXT: addi 1, 1, 32
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%log = call <1 x float> @llvm.experimental.constrained.log.v1f32( %log = call <1 x float> @llvm.experimental.constrained.log.v1f32(
<1 x float> %x, <1 x float> %x,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <1 x float> %log ret <1 x float> %log
} }
define <2 x double> @constrained_vector_log_v2f64(<2 x double> %x) #0 { define <2 x double> @constrained_vector_log_v2f64(<2 x double> %x) #0 {
; PC64LE-LABEL: constrained_vector_log_v2f64: ; PC64LE-LABEL: constrained_vector_log_v2f64:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -80(1) ; PC64LE-NEXT: stdu 1, -80(1)
; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: li 3, 48
; PC64LE-NEXT: std 0, 96(1)
; PC64LE-NEXT: stxvd2x 62, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 62, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: li 3, 64 ; PC64LE-NEXT: li 3, 64
; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: vmr 31, 2 ; PC64LE-NEXT: vmr 31, 2
; PC64LE-NEXT: xxlor 1, 63, 63 ; PC64LE-NEXT: xxlor 1, 63, 63
; PC64LE-NEXT: bl log ; PC64LE-NEXT: bl log
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: xxlor 62, 1, 1 ; PC64LE-NEXT: xxlor 62, 1, 1
Show All 10 Lines
; PC64LE-NEXT: addi 1, 1, 80 ; PC64LE-NEXT: addi 1, 1, 80
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_log_v2f64: ; PC64LE9-LABEL: constrained_vector_log_v2f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -64(1) ; PC64LE9-NEXT: stdu 1, -64(1)
; PC64LE9-NEXT: std 0, 80(1)
; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill
; PC64LE9-NEXT: vmr 31, 2 ; PC64LE9-NEXT: vmr 31, 2
; PC64LE9-NEXT: xscpsgndp 1, 63, 63 ; PC64LE9-NEXT: xscpsgndp 1, 63, 63
; PC64LE9-NEXT: stxv 62, 32(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 62, 32(1) # 16-byte Folded Spill
; PC64LE9-NEXT: bl log ; PC64LE9-NEXT: bl log
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: xscpsgndp 62, 1, 1 ; PC64LE9-NEXT: xscpsgndp 62, 1, 1
; PC64LE9-NEXT: xxswapd 1, 63 ; PC64LE9-NEXT: xxswapd 1, 63
Show All 15 Lines %log = call <2 x double> @llvm.experimental.constrained.log.v2f64(
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <2 x double> %log ret <2 x double> %log
} }
define <3 x float> @constrained_vector_log_v3f32(<3 x float> %x) #0 { define <3 x float> @constrained_vector_log_v3f32(<3 x float> %x) #0 {
; PC64LE-LABEL: constrained_vector_log_v3f32: ; PC64LE-LABEL: constrained_vector_log_v3f32:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -80(1) ; PC64LE-NEXT: stdu 1, -80(1)
; PC64LE-NEXT: xxsldwi 0, 34, 34, 1 ; PC64LE-NEXT: xxsldwi 0, 34, 34, 1
; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: li 3, 48
; PC64LE-NEXT: std 0, 96(1)
; PC64LE-NEXT: stfd 30, 64(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 30, 64(1) # 8-byte Folded Spill
; PC64LE-NEXT: stfd 31, 72(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 31, 72(1) # 8-byte Folded Spill
; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: vmr 31, 2 ; PC64LE-NEXT: vmr 31, 2
; PC64LE-NEXT: xscvspdpn 1, 0 ; PC64LE-NEXT: xscvspdpn 1, 0
; PC64LE-NEXT: bl logf ; PC64LE-NEXT: bl logf
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: xxswapd 0, 63 ; PC64LE-NEXT: xxswapd 0, 63
Show All 22 Lines
; PC64LE-NEXT: addi 1, 1, 80 ; PC64LE-NEXT: addi 1, 1, 80
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_log_v3f32: ; PC64LE9-LABEL: constrained_vector_log_v3f32:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -64(1) ; PC64LE9-NEXT: stdu 1, -64(1)
; PC64LE9-NEXT: xxsldwi 0, 34, 34, 1 ; PC64LE9-NEXT: xxsldwi 0, 34, 34, 1
; PC64LE9-NEXT: std 0, 80(1)
; PC64LE9-NEXT: stfd 30, 48(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 30, 48(1) # 8-byte Folded Spill
; PC64LE9-NEXT: stfd 31, 56(1) # 8-byte Folded Spill
; PC64LE9-NEXT: stxv 63, 32(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 63, 32(1) # 16-byte Folded Spill
; PC64LE9-NEXT: xscvspdpn 1, 0 ; PC64LE9-NEXT: stfd 31, 56(1) # 8-byte Folded Spill
; PC64LE9-NEXT: vmr 31, 2 ; PC64LE9-NEXT: vmr 31, 2
; PC64LE9-NEXT: xscvspdpn 1, 0
; PC64LE9-NEXT: bl logf ; PC64LE9-NEXT: bl logf
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: xxswapd 0, 63 ; PC64LE9-NEXT: xxswapd 0, 63
; PC64LE9-NEXT: fmr 31, 1 ; PC64LE9-NEXT: fmr 31, 1
; PC64LE9-NEXT: xscvspdpn 1, 0 ; PC64LE9-NEXT: xscvspdpn 1, 0
; PC64LE9-NEXT: bl logf ; PC64LE9-NEXT: bl logf
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: xxsldwi 0, 63, 63, 3 ; PC64LE9-NEXT: xxsldwi 0, 63, 63, 3
Show All 23 Lines %log = call <3 x float> @llvm.experimental.constrained.log.v3f32(
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <3 x float> %log ret <3 x float> %log
} }
define <3 x double> @constrained_vector_log_v3f64(<3 x double> %x) #0 { define <3 x double> @constrained_vector_log_v3f64(<3 x double> %x) #0 {
; PC64LE-LABEL: constrained_vector_log_v3f64: ; PC64LE-LABEL: constrained_vector_log_v3f64:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -80(1) ; PC64LE-NEXT: stdu 1, -80(1)
; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: li 3, 48
; PC64LE-NEXT: std 0, 96(1)
; PC64LE-NEXT: stfd 30, 64(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 30, 64(1) # 8-byte Folded Spill
; PC64LE-NEXT: fmr 30, 2
; PC64LE-NEXT: stfd 31, 72(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 31, 72(1) # 8-byte Folded Spill
; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: fmr 31, 3 ; PC64LE-NEXT: fmr 31, 3
; PC64LE-NEXT: fmr 30, 2 ; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: bl log ; PC64LE-NEXT: bl log
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: xxlor 63, 1, 1 ; PC64LE-NEXT: xxlor 63, 1, 1
; PC64LE-NEXT: fmr 1, 30 ; PC64LE-NEXT: fmr 1, 30
; PC64LE-NEXT: bl log ; PC64LE-NEXT: bl log
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1
; PC64LE-NEXT: xxmrghd 63, 1, 63 ; PC64LE-NEXT: xxmrghd 63, 1, 63
Show All 11 Lines
; PC64LE-NEXT: addi 1, 1, 80 ; PC64LE-NEXT: addi 1, 1, 80
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_log_v3f64: ; PC64LE9-LABEL: constrained_vector_log_v3f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -64(1) ; PC64LE9-NEXT: stdu 1, -64(1)
; PC64LE9-NEXT: std 0, 80(1)
; PC64LE9-NEXT: stfd 30, 48(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 30, 48(1) # 8-byte Folded Spill
; PC64LE9-NEXT: stfd 31, 56(1) # 8-byte Folded Spill
; PC64LE9-NEXT: stxv 63, 32(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 63, 32(1) # 16-byte Folded Spill
; PC64LE9-NEXT: stfd 31, 56(1) # 8-byte Folded Spill
; PC64LE9-NEXT: fmr 31, 3 ; PC64LE9-NEXT: fmr 31, 3
; PC64LE9-NEXT: fmr 30, 2 ; PC64LE9-NEXT: fmr 30, 2
; PC64LE9-NEXT: bl log ; PC64LE9-NEXT: bl log
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: xscpsgndp 63, 1, 1 ; PC64LE9-NEXT: xscpsgndp 63, 1, 1
; PC64LE9-NEXT: fmr 1, 30 ; PC64LE9-NEXT: fmr 1, 30
; PC64LE9-NEXT: bl log ; PC64LE9-NEXT: bl log
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
Show All 20 Lines %log = call <3 x double> @llvm.experimental.constrained.log.v3f64(
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <3 x double> %log ret <3 x double> %log
} }
define <4 x double> @constrained_vector_log_v4f64(<4 x double> %x) #0 { define <4 x double> @constrained_vector_log_v4f64(<4 x double> %x) #0 {
; PC64LE-LABEL: constrained_vector_log_v4f64: ; PC64LE-LABEL: constrained_vector_log_v4f64:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -96(1) ; PC64LE-NEXT: stdu 1, -96(1)
; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: li 3, 48
; PC64LE-NEXT: std 0, 112(1)
; PC64LE-NEXT: stxvd2x 61, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 61, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: li 3, 64 ; PC64LE-NEXT: li 3, 64
; PC64LE-NEXT: stxvd2x 62, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 62, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: vmr 30, 2 ; PC64LE-NEXT: vmr 30, 2
; PC64LE-NEXT: li 3, 80 ; PC64LE-NEXT: li 3, 80
; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: vmr 31, 3 ; PC64LE-NEXT: vmr 31, 3
; PC64LE-NEXT: xxlor 1, 62, 62 ; PC64LE-NEXT: xxlor 1, 62, 62
Show All 26 Lines
; PC64LE-NEXT: addi 1, 1, 96 ; PC64LE-NEXT: addi 1, 1, 96
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_log_v4f64: ; PC64LE9-LABEL: constrained_vector_log_v4f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -80(1) ; PC64LE9-NEXT: stdu 1, -80(1)
; PC64LE9-NEXT: std 0, 96(1)
; PC64LE9-NEXT: stxv 62, 48(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 62, 48(1) # 16-byte Folded Spill
; PC64LE9-NEXT: vmr 30, 2 ; PC64LE9-NEXT: vmr 30, 2
; PC64LE9-NEXT: xscpsgndp 1, 62, 62 ; PC64LE9-NEXT: xscpsgndp 1, 62, 62
; PC64LE9-NEXT: stxv 61, 32(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 61, 32(1) # 16-byte Folded Spill
; PC64LE9-NEXT: stxv 63, 64(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 63, 64(1) # 16-byte Folded Spill
; PC64LE9-NEXT: vmr 31, 3 ; PC64LE9-NEXT: vmr 31, 3
; PC64LE9-NEXT: bl log ; PC64LE9-NEXT: bl log
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
Show All 29 Lines %log = call <4 x double> @llvm.experimental.constrained.log.v4f64(
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <4 x double> %log ret <4 x double> %log
} }
define <1 x float> @constrained_vector_log10_v1f32(<1 x float> %x) #0 { define <1 x float> @constrained_vector_log10_v1f32(<1 x float> %x) #0 {
; PC64LE-LABEL: constrained_vector_log10_v1f32: ; PC64LE-LABEL: constrained_vector_log10_v1f32:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -32(1) ; PC64LE-NEXT: stdu 1, -32(1)
; PC64LE-NEXT: std 0, 48(1)
; PC64LE-NEXT: bl log10f ; PC64LE-NEXT: bl log10f
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: addi 1, 1, 32 ; PC64LE-NEXT: addi 1, 1, 32
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_log10_v1f32: ; PC64LE9-LABEL: constrained_vector_log10_v1f32:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -32(1) ; PC64LE9-NEXT: stdu 1, -32(1)
; PC64LE9-NEXT: std 0, 48(1)
; PC64LE9-NEXT: bl log10f ; PC64LE9-NEXT: bl log10f
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addi 1, 1, 32 ; PC64LE9-NEXT: addi 1, 1, 32
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%log10 = call <1 x float> @llvm.experimental.constrained.log10.v1f32( %log10 = call <1 x float> @llvm.experimental.constrained.log10.v1f32(
<1 x float> %x, <1 x float> %x,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <1 x float> %log10 ret <1 x float> %log10
} }
define <2 x double> @constrained_vector_log10_v2f64(<2 x double> %x) #0 { define <2 x double> @constrained_vector_log10_v2f64(<2 x double> %x) #0 {
; PC64LE-LABEL: constrained_vector_log10_v2f64: ; PC64LE-LABEL: constrained_vector_log10_v2f64:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -80(1) ; PC64LE-NEXT: stdu 1, -80(1)
; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: li 3, 48
; PC64LE-NEXT: std 0, 96(1)
; PC64LE-NEXT: stxvd2x 62, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 62, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: li 3, 64 ; PC64LE-NEXT: li 3, 64
; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: vmr 31, 2 ; PC64LE-NEXT: vmr 31, 2
; PC64LE-NEXT: xxlor 1, 63, 63 ; PC64LE-NEXT: xxlor 1, 63, 63
; PC64LE-NEXT: bl log10 ; PC64LE-NEXT: bl log10
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: xxlor 62, 1, 1 ; PC64LE-NEXT: xxlor 62, 1, 1
Show All 10 Lines
; PC64LE-NEXT: addi 1, 1, 80 ; PC64LE-NEXT: addi 1, 1, 80
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_log10_v2f64: ; PC64LE9-LABEL: constrained_vector_log10_v2f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -64(1) ; PC64LE9-NEXT: stdu 1, -64(1)
; PC64LE9-NEXT: std 0, 80(1)
; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill
; PC64LE9-NEXT: vmr 31, 2 ; PC64LE9-NEXT: vmr 31, 2
; PC64LE9-NEXT: xscpsgndp 1, 63, 63 ; PC64LE9-NEXT: xscpsgndp 1, 63, 63
; PC64LE9-NEXT: stxv 62, 32(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 62, 32(1) # 16-byte Folded Spill
; PC64LE9-NEXT: bl log10 ; PC64LE9-NEXT: bl log10
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: xscpsgndp 62, 1, 1 ; PC64LE9-NEXT: xscpsgndp 62, 1, 1
; PC64LE9-NEXT: xxswapd 1, 63 ; PC64LE9-NEXT: xxswapd 1, 63
Show All 15 Lines %log10 = call <2 x double> @llvm.experimental.constrained.log10.v2f64(
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <2 x double> %log10 ret <2 x double> %log10
} }
define <3 x float> @constrained_vector_log10_v3f32(<3 x float> %x) #0 { define <3 x float> @constrained_vector_log10_v3f32(<3 x float> %x) #0 {
; PC64LE-LABEL: constrained_vector_log10_v3f32: ; PC64LE-LABEL: constrained_vector_log10_v3f32:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -80(1) ; PC64LE-NEXT: stdu 1, -80(1)
; PC64LE-NEXT: xxsldwi 0, 34, 34, 1 ; PC64LE-NEXT: xxsldwi 0, 34, 34, 1
; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: li 3, 48
; PC64LE-NEXT: std 0, 96(1)
; PC64LE-NEXT: stfd 30, 64(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 30, 64(1) # 8-byte Folded Spill
; PC64LE-NEXT: stfd 31, 72(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 31, 72(1) # 8-byte Folded Spill
; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: vmr 31, 2 ; PC64LE-NEXT: vmr 31, 2
; PC64LE-NEXT: xscvspdpn 1, 0 ; PC64LE-NEXT: xscvspdpn 1, 0
; PC64LE-NEXT: bl log10f ; PC64LE-NEXT: bl log10f
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: xxswapd 0, 63 ; PC64LE-NEXT: xxswapd 0, 63
Show All 22 Lines
; PC64LE-NEXT: addi 1, 1, 80 ; PC64LE-NEXT: addi 1, 1, 80
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_log10_v3f32: ; PC64LE9-LABEL: constrained_vector_log10_v3f32:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -64(1) ; PC64LE9-NEXT: stdu 1, -64(1)
; PC64LE9-NEXT: xxsldwi 0, 34, 34, 1 ; PC64LE9-NEXT: xxsldwi 0, 34, 34, 1
; PC64LE9-NEXT: std 0, 80(1)
; PC64LE9-NEXT: stfd 30, 48(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 30, 48(1) # 8-byte Folded Spill
; PC64LE9-NEXT: stfd 31, 56(1) # 8-byte Folded Spill
; PC64LE9-NEXT: stxv 63, 32(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 63, 32(1) # 16-byte Folded Spill
; PC64LE9-NEXT: xscvspdpn 1, 0 ; PC64LE9-NEXT: stfd 31, 56(1) # 8-byte Folded Spill
; PC64LE9-NEXT: vmr 31, 2 ; PC64LE9-NEXT: vmr 31, 2
; PC64LE9-NEXT: xscvspdpn 1, 0
; PC64LE9-NEXT: bl log10f ; PC64LE9-NEXT: bl log10f
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: xxswapd 0, 63 ; PC64LE9-NEXT: xxswapd 0, 63
; PC64LE9-NEXT: fmr 31, 1 ; PC64LE9-NEXT: fmr 31, 1
; PC64LE9-NEXT: xscvspdpn 1, 0 ; PC64LE9-NEXT: xscvspdpn 1, 0
; PC64LE9-NEXT: bl log10f ; PC64LE9-NEXT: bl log10f
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: xxsldwi 0, 63, 63, 3 ; PC64LE9-NEXT: xxsldwi 0, 63, 63, 3
Show All 23 Lines %log10 = call <3 x float> @llvm.experimental.constrained.log10.v3f32(
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <3 x float> %log10 ret <3 x float> %log10
} }
define <3 x double> @constrained_vector_log10_v3f64(<3 x double> %x) #0 { define <3 x double> @constrained_vector_log10_v3f64(<3 x double> %x) #0 {
; PC64LE-LABEL: constrained_vector_log10_v3f64: ; PC64LE-LABEL: constrained_vector_log10_v3f64:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -80(1) ; PC64LE-NEXT: stdu 1, -80(1)
; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: li 3, 48
; PC64LE-NEXT: std 0, 96(1)
; PC64LE-NEXT: stfd 30, 64(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 30, 64(1) # 8-byte Folded Spill
; PC64LE-NEXT: fmr 30, 2
; PC64LE-NEXT: stfd 31, 72(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 31, 72(1) # 8-byte Folded Spill
; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: fmr 31, 3 ; PC64LE-NEXT: fmr 31, 3
; PC64LE-NEXT: fmr 30, 2 ; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: bl log10 ; PC64LE-NEXT: bl log10
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: xxlor 63, 1, 1 ; PC64LE-NEXT: xxlor 63, 1, 1
; PC64LE-NEXT: fmr 1, 30 ; PC64LE-NEXT: fmr 1, 30
; PC64LE-NEXT: bl log10 ; PC64LE-NEXT: bl log10
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1
; PC64LE-NEXT: xxmrghd 63, 1, 63 ; PC64LE-NEXT: xxmrghd 63, 1, 63
Show All 11 Lines
; PC64LE-NEXT: addi 1, 1, 80 ; PC64LE-NEXT: addi 1, 1, 80
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_log10_v3f64: ; PC64LE9-LABEL: constrained_vector_log10_v3f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -64(1) ; PC64LE9-NEXT: stdu 1, -64(1)
; PC64LE9-NEXT: std 0, 80(1)
; PC64LE9-NEXT: stfd 30, 48(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 30, 48(1) # 8-byte Folded Spill
; PC64LE9-NEXT: stfd 31, 56(1) # 8-byte Folded Spill
; PC64LE9-NEXT: stxv 63, 32(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 63, 32(1) # 16-byte Folded Spill
; PC64LE9-NEXT: stfd 31, 56(1) # 8-byte Folded Spill
; PC64LE9-NEXT: fmr 31, 3 ; PC64LE9-NEXT: fmr 31, 3
; PC64LE9-NEXT: fmr 30, 2 ; PC64LE9-NEXT: fmr 30, 2
; PC64LE9-NEXT: bl log10 ; PC64LE9-NEXT: bl log10
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: xscpsgndp 63, 1, 1 ; PC64LE9-NEXT: xscpsgndp 63, 1, 1
; PC64LE9-NEXT: fmr 1, 30 ; PC64LE9-NEXT: fmr 1, 30
; PC64LE9-NEXT: bl log10 ; PC64LE9-NEXT: bl log10
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
Show All 20 Lines %log10 = call <3 x double> @llvm.experimental.constrained.log10.v3f64(
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <3 x double> %log10 ret <3 x double> %log10
} }
define <4 x double> @constrained_vector_log10_v4f64(<4 x double> %x) #0 { define <4 x double> @constrained_vector_log10_v4f64(<4 x double> %x) #0 {
; PC64LE-LABEL: constrained_vector_log10_v4f64: ; PC64LE-LABEL: constrained_vector_log10_v4f64:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -96(1) ; PC64LE-NEXT: stdu 1, -96(1)
; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: li 3, 48
; PC64LE-NEXT: std 0, 112(1)
; PC64LE-NEXT: stxvd2x 61, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 61, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: li 3, 64 ; PC64LE-NEXT: li 3, 64
; PC64LE-NEXT: stxvd2x 62, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 62, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: vmr 30, 2 ; PC64LE-NEXT: vmr 30, 2
; PC64LE-NEXT: li 3, 80 ; PC64LE-NEXT: li 3, 80
; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: vmr 31, 3 ; PC64LE-NEXT: vmr 31, 3
; PC64LE-NEXT: xxlor 1, 62, 62 ; PC64LE-NEXT: xxlor 1, 62, 62
Show All 26 Lines
; PC64LE-NEXT: addi 1, 1, 96 ; PC64LE-NEXT: addi 1, 1, 96
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_log10_v4f64: ; PC64LE9-LABEL: constrained_vector_log10_v4f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -80(1) ; PC64LE9-NEXT: stdu 1, -80(1)
; PC64LE9-NEXT: std 0, 96(1)
; PC64LE9-NEXT: stxv 62, 48(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 62, 48(1) # 16-byte Folded Spill
; PC64LE9-NEXT: vmr 30, 2 ; PC64LE9-NEXT: vmr 30, 2
; PC64LE9-NEXT: xscpsgndp 1, 62, 62 ; PC64LE9-NEXT: xscpsgndp 1, 62, 62
; PC64LE9-NEXT: stxv 61, 32(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 61, 32(1) # 16-byte Folded Spill
; PC64LE9-NEXT: stxv 63, 64(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 63, 64(1) # 16-byte Folded Spill
; PC64LE9-NEXT: vmr 31, 3 ; PC64LE9-NEXT: vmr 31, 3
; PC64LE9-NEXT: bl log10 ; PC64LE9-NEXT: bl log10
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
Show All 29 Lines %log10 = call <4 x double> @llvm.experimental.constrained.log10.v4f64(
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <4 x double> %log10 ret <4 x double> %log10
} }
define <1 x float> @constrained_vector_log2_v1f32(<1 x float> %x) #0 { define <1 x float> @constrained_vector_log2_v1f32(<1 x float> %x) #0 {
; PC64LE-LABEL: constrained_vector_log2_v1f32: ; PC64LE-LABEL: constrained_vector_log2_v1f32:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -32(1) ; PC64LE-NEXT: stdu 1, -32(1)
; PC64LE-NEXT: std 0, 48(1)
; PC64LE-NEXT: bl log2f ; PC64LE-NEXT: bl log2f
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: addi 1, 1, 32 ; PC64LE-NEXT: addi 1, 1, 32
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_log2_v1f32: ; PC64LE9-LABEL: constrained_vector_log2_v1f32:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -32(1) ; PC64LE9-NEXT: stdu 1, -32(1)
; PC64LE9-NEXT: std 0, 48(1)
; PC64LE9-NEXT: bl log2f ; PC64LE9-NEXT: bl log2f
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addi 1, 1, 32 ; PC64LE9-NEXT: addi 1, 1, 32
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%log2 = call <1 x float> @llvm.experimental.constrained.log2.v1f32( %log2 = call <1 x float> @llvm.experimental.constrained.log2.v1f32(
<1 x float> %x, <1 x float> %x,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <1 x float> %log2 ret <1 x float> %log2
} }
define <2 x double> @constrained_vector_log2_v2f64(<2 x double> %x) #0 { define <2 x double> @constrained_vector_log2_v2f64(<2 x double> %x) #0 {
; PC64LE-LABEL: constrained_vector_log2_v2f64: ; PC64LE-LABEL: constrained_vector_log2_v2f64:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -80(1) ; PC64LE-NEXT: stdu 1, -80(1)
; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: li 3, 48
; PC64LE-NEXT: std 0, 96(1)
; PC64LE-NEXT: stxvd2x 62, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 62, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: li 3, 64 ; PC64LE-NEXT: li 3, 64
; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: vmr 31, 2 ; PC64LE-NEXT: vmr 31, 2
; PC64LE-NEXT: xxlor 1, 63, 63 ; PC64LE-NEXT: xxlor 1, 63, 63
; PC64LE-NEXT: bl log2 ; PC64LE-NEXT: bl log2
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: xxlor 62, 1, 1 ; PC64LE-NEXT: xxlor 62, 1, 1
Show All 10 Lines
; PC64LE-NEXT: addi 1, 1, 80 ; PC64LE-NEXT: addi 1, 1, 80
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_log2_v2f64: ; PC64LE9-LABEL: constrained_vector_log2_v2f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -64(1) ; PC64LE9-NEXT: stdu 1, -64(1)
; PC64LE9-NEXT: std 0, 80(1)
; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill
; PC64LE9-NEXT: vmr 31, 2 ; PC64LE9-NEXT: vmr 31, 2
; PC64LE9-NEXT: xscpsgndp 1, 63, 63 ; PC64LE9-NEXT: xscpsgndp 1, 63, 63
; PC64LE9-NEXT: stxv 62, 32(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 62, 32(1) # 16-byte Folded Spill
; PC64LE9-NEXT: bl log2 ; PC64LE9-NEXT: bl log2
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: xscpsgndp 62, 1, 1 ; PC64LE9-NEXT: xscpsgndp 62, 1, 1
; PC64LE9-NEXT: xxswapd 1, 63 ; PC64LE9-NEXT: xxswapd 1, 63
Show All 15 Lines %log2 = call <2 x double> @llvm.experimental.constrained.log2.v2f64(
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <2 x double> %log2 ret <2 x double> %log2
} }
define <3 x float> @constrained_vector_log2_v3f32(<3 x float> %x) #0 { define <3 x float> @constrained_vector_log2_v3f32(<3 x float> %x) #0 {
; PC64LE-LABEL: constrained_vector_log2_v3f32: ; PC64LE-LABEL: constrained_vector_log2_v3f32:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -80(1) ; PC64LE-NEXT: stdu 1, -80(1)
; PC64LE-NEXT: xxsldwi 0, 34, 34, 1 ; PC64LE-NEXT: xxsldwi 0, 34, 34, 1
; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: li 3, 48
; PC64LE-NEXT: std 0, 96(1)
; PC64LE-NEXT: stfd 30, 64(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 30, 64(1) # 8-byte Folded Spill
; PC64LE-NEXT: stfd 31, 72(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 31, 72(1) # 8-byte Folded Spill
; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: vmr 31, 2 ; PC64LE-NEXT: vmr 31, 2
; PC64LE-NEXT: xscvspdpn 1, 0 ; PC64LE-NEXT: xscvspdpn 1, 0
; PC64LE-NEXT: bl log2f ; PC64LE-NEXT: bl log2f
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: xxswapd 0, 63 ; PC64LE-NEXT: xxswapd 0, 63
Show All 22 Lines
; PC64LE-NEXT: addi 1, 1, 80 ; PC64LE-NEXT: addi 1, 1, 80
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_log2_v3f32: ; PC64LE9-LABEL: constrained_vector_log2_v3f32:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -64(1) ; PC64LE9-NEXT: stdu 1, -64(1)
; PC64LE9-NEXT: xxsldwi 0, 34, 34, 1 ; PC64LE9-NEXT: xxsldwi 0, 34, 34, 1
; PC64LE9-NEXT: std 0, 80(1)
; PC64LE9-NEXT: stfd 30, 48(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 30, 48(1) # 8-byte Folded Spill
; PC64LE9-NEXT: stfd 31, 56(1) # 8-byte Folded Spill
; PC64LE9-NEXT: stxv 63, 32(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 63, 32(1) # 16-byte Folded Spill
; PC64LE9-NEXT: xscvspdpn 1, 0 ; PC64LE9-NEXT: stfd 31, 56(1) # 8-byte Folded Spill
; PC64LE9-NEXT: vmr 31, 2 ; PC64LE9-NEXT: vmr 31, 2
; PC64LE9-NEXT: xscvspdpn 1, 0
; PC64LE9-NEXT: bl log2f ; PC64LE9-NEXT: bl log2f
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: xxswapd 0, 63 ; PC64LE9-NEXT: xxswapd 0, 63
; PC64LE9-NEXT: fmr 31, 1 ; PC64LE9-NEXT: fmr 31, 1
; PC64LE9-NEXT: xscvspdpn 1, 0 ; PC64LE9-NEXT: xscvspdpn 1, 0
; PC64LE9-NEXT: bl log2f ; PC64LE9-NEXT: bl log2f
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: xxsldwi 0, 63, 63, 3 ; PC64LE9-NEXT: xxsldwi 0, 63, 63, 3
Show All 23 Lines %log2 = call <3 x float> @llvm.experimental.constrained.log2.v3f32(
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <3 x float> %log2 ret <3 x float> %log2
} }
define <3 x double> @constrained_vector_log2_v3f64(<3 x double> %x) #0 { define <3 x double> @constrained_vector_log2_v3f64(<3 x double> %x) #0 {
; PC64LE-LABEL: constrained_vector_log2_v3f64: ; PC64LE-LABEL: constrained_vector_log2_v3f64:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -80(1) ; PC64LE-NEXT: stdu 1, -80(1)
; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: li 3, 48
; PC64LE-NEXT: std 0, 96(1)
; PC64LE-NEXT: stfd 30, 64(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 30, 64(1) # 8-byte Folded Spill
; PC64LE-NEXT: fmr 30, 2
; PC64LE-NEXT: stfd 31, 72(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 31, 72(1) # 8-byte Folded Spill
; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: fmr 31, 3 ; PC64LE-NEXT: fmr 31, 3
; PC64LE-NEXT: fmr 30, 2 ; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: bl log2 ; PC64LE-NEXT: bl log2
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: xxlor 63, 1, 1 ; PC64LE-NEXT: xxlor 63, 1, 1
; PC64LE-NEXT: fmr 1, 30 ; PC64LE-NEXT: fmr 1, 30
; PC64LE-NEXT: bl log2 ; PC64LE-NEXT: bl log2
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1
; PC64LE-NEXT: xxmrghd 63, 1, 63 ; PC64LE-NEXT: xxmrghd 63, 1, 63
Show All 11 Lines
; PC64LE-NEXT: addi 1, 1, 80 ; PC64LE-NEXT: addi 1, 1, 80
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_log2_v3f64: ; PC64LE9-LABEL: constrained_vector_log2_v3f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -64(1) ; PC64LE9-NEXT: stdu 1, -64(1)
; PC64LE9-NEXT: std 0, 80(1)
; PC64LE9-NEXT: stfd 30, 48(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 30, 48(1) # 8-byte Folded Spill
; PC64LE9-NEXT: stfd 31, 56(1) # 8-byte Folded Spill
; PC64LE9-NEXT: stxv 63, 32(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 63, 32(1) # 16-byte Folded Spill
; PC64LE9-NEXT: stfd 31, 56(1) # 8-byte Folded Spill
; PC64LE9-NEXT: fmr 31, 3 ; PC64LE9-NEXT: fmr 31, 3
; PC64LE9-NEXT: fmr 30, 2 ; PC64LE9-NEXT: fmr 30, 2
; PC64LE9-NEXT: bl log2 ; PC64LE9-NEXT: bl log2
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: xscpsgndp 63, 1, 1 ; PC64LE9-NEXT: xscpsgndp 63, 1, 1
; PC64LE9-NEXT: fmr 1, 30 ; PC64LE9-NEXT: fmr 1, 30
; PC64LE9-NEXT: bl log2 ; PC64LE9-NEXT: bl log2
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
Show All 20 Lines %log2 = call <3 x double> @llvm.experimental.constrained.log2.v3f64(
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <3 x double> %log2 ret <3 x double> %log2
} }
define <4 x double> @constrained_vector_log2_v4f64(<4 x double> %x) #0 { define <4 x double> @constrained_vector_log2_v4f64(<4 x double> %x) #0 {
; PC64LE-LABEL: constrained_vector_log2_v4f64: ; PC64LE-LABEL: constrained_vector_log2_v4f64:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -96(1) ; PC64LE-NEXT: stdu 1, -96(1)
; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: li 3, 48
; PC64LE-NEXT: std 0, 112(1)
; PC64LE-NEXT: stxvd2x 61, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 61, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: li 3, 64 ; PC64LE-NEXT: li 3, 64
; PC64LE-NEXT: stxvd2x 62, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 62, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: vmr 30, 2 ; PC64LE-NEXT: vmr 30, 2
; PC64LE-NEXT: li 3, 80 ; PC64LE-NEXT: li 3, 80
; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: vmr 31, 3 ; PC64LE-NEXT: vmr 31, 3
; PC64LE-NEXT: xxlor 1, 62, 62 ; PC64LE-NEXT: xxlor 1, 62, 62
Show All 26 Lines
; PC64LE-NEXT: addi 1, 1, 96 ; PC64LE-NEXT: addi 1, 1, 96
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_log2_v4f64: ; PC64LE9-LABEL: constrained_vector_log2_v4f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -80(1) ; PC64LE9-NEXT: stdu 1, -80(1)
; PC64LE9-NEXT: std 0, 96(1)
; PC64LE9-NEXT: stxv 62, 48(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 62, 48(1) # 16-byte Folded Spill
; PC64LE9-NEXT: vmr 30, 2 ; PC64LE9-NEXT: vmr 30, 2
; PC64LE9-NEXT: xscpsgndp 1, 62, 62 ; PC64LE9-NEXT: xscpsgndp 1, 62, 62
; PC64LE9-NEXT: stxv 61, 32(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 61, 32(1) # 16-byte Folded Spill
; PC64LE9-NEXT: stxv 63, 64(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 63, 64(1) # 16-byte Folded Spill
; PC64LE9-NEXT: vmr 31, 3 ; PC64LE9-NEXT: vmr 31, 3
; PC64LE9-NEXT: bl log2 ; PC64LE9-NEXT: bl log2
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
▲ Show 20 Lines • Show All 168 Lines • ▼ Show 20 Lines %rint = call <4 x double> @llvm.experimental.constrained.rint.v4f64(
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <4 x double> %rint ret <4 x double> %rint
} }
define <1 x float> @constrained_vector_nearbyint_v1f32(<1 x float> %x) #0 { define <1 x float> @constrained_vector_nearbyint_v1f32(<1 x float> %x) #0 {
; PC64LE-LABEL: constrained_vector_nearbyint_v1f32: ; PC64LE-LABEL: constrained_vector_nearbyint_v1f32:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -32(1) ; PC64LE-NEXT: stdu 1, -32(1)
; PC64LE-NEXT: std 0, 48(1)
; PC64LE-NEXT: bl nearbyintf ; PC64LE-NEXT: bl nearbyintf
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: addi 1, 1, 32 ; PC64LE-NEXT: addi 1, 1, 32
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_nearbyint_v1f32: ; PC64LE9-LABEL: constrained_vector_nearbyint_v1f32:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -32(1) ; PC64LE9-NEXT: stdu 1, -32(1)
; PC64LE9-NEXT: std 0, 48(1)
; PC64LE9-NEXT: bl nearbyintf ; PC64LE9-NEXT: bl nearbyintf
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addi 1, 1, 32 ; PC64LE9-NEXT: addi 1, 1, 32
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%nearby = call <1 x float> @llvm.experimental.constrained.nearbyint.v1f32( %nearby = call <1 x float> @llvm.experimental.constrained.nearbyint.v1f32(
<1 x float> %x, <1 x float> %x,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <1 x float> %nearby ret <1 x float> %nearby
} }
define <2 x double> @constrained_vector_nearbyint_v2f64(<2 x double> %x) #0 { define <2 x double> @constrained_vector_nearbyint_v2f64(<2 x double> %x) #0 {
; PC64LE-LABEL: constrained_vector_nearbyint_v2f64: ; PC64LE-LABEL: constrained_vector_nearbyint_v2f64:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -80(1) ; PC64LE-NEXT: stdu 1, -80(1)
; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: li 3, 48
; PC64LE-NEXT: std 0, 96(1)
; PC64LE-NEXT: stxvd2x 62, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 62, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: li 3, 64 ; PC64LE-NEXT: li 3, 64
; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: vmr 31, 2 ; PC64LE-NEXT: vmr 31, 2
; PC64LE-NEXT: xxlor 1, 63, 63 ; PC64LE-NEXT: xxlor 1, 63, 63
; PC64LE-NEXT: bl nearbyint ; PC64LE-NEXT: bl nearbyint
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: xxlor 62, 1, 1 ; PC64LE-NEXT: xxlor 62, 1, 1
Show All 10 Lines
; PC64LE-NEXT: addi 1, 1, 80 ; PC64LE-NEXT: addi 1, 1, 80
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_nearbyint_v2f64: ; PC64LE9-LABEL: constrained_vector_nearbyint_v2f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -64(1) ; PC64LE9-NEXT: stdu 1, -64(1)
; PC64LE9-NEXT: std 0, 80(1)
; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill
; PC64LE9-NEXT: vmr 31, 2 ; PC64LE9-NEXT: vmr 31, 2
; PC64LE9-NEXT: xscpsgndp 1, 63, 63 ; PC64LE9-NEXT: xscpsgndp 1, 63, 63
; PC64LE9-NEXT: stxv 62, 32(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 62, 32(1) # 16-byte Folded Spill
; PC64LE9-NEXT: bl nearbyint ; PC64LE9-NEXT: bl nearbyint
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: xscpsgndp 62, 1, 1 ; PC64LE9-NEXT: xscpsgndp 62, 1, 1
; PC64LE9-NEXT: xxswapd 1, 63 ; PC64LE9-NEXT: xxswapd 1, 63
Show All 15 Lines %nearby = call <2 x double> @llvm.experimental.constrained.nearbyint.v2f64(
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <2 x double> %nearby ret <2 x double> %nearby
} }
define <3 x float> @constrained_vector_nearbyint_v3f32(<3 x float> %x) #0 { define <3 x float> @constrained_vector_nearbyint_v3f32(<3 x float> %x) #0 {
; PC64LE-LABEL: constrained_vector_nearbyint_v3f32: ; PC64LE-LABEL: constrained_vector_nearbyint_v3f32:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -80(1) ; PC64LE-NEXT: stdu 1, -80(1)
; PC64LE-NEXT: xxsldwi 0, 34, 34, 1 ; PC64LE-NEXT: xxsldwi 0, 34, 34, 1
; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: li 3, 48
; PC64LE-NEXT: std 0, 96(1)
; PC64LE-NEXT: stfd 30, 64(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 30, 64(1) # 8-byte Folded Spill
; PC64LE-NEXT: stfd 31, 72(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 31, 72(1) # 8-byte Folded Spill
; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: vmr 31, 2 ; PC64LE-NEXT: vmr 31, 2
; PC64LE-NEXT: xscvspdpn 1, 0 ; PC64LE-NEXT: xscvspdpn 1, 0
; PC64LE-NEXT: bl nearbyintf ; PC64LE-NEXT: bl nearbyintf
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: xxswapd 0, 63 ; PC64LE-NEXT: xxswapd 0, 63
Show All 22 Lines
; PC64LE-NEXT: addi 1, 1, 80 ; PC64LE-NEXT: addi 1, 1, 80
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_nearbyint_v3f32: ; PC64LE9-LABEL: constrained_vector_nearbyint_v3f32:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -64(1) ; PC64LE9-NEXT: stdu 1, -64(1)
; PC64LE9-NEXT: xxsldwi 0, 34, 34, 1 ; PC64LE9-NEXT: xxsldwi 0, 34, 34, 1
; PC64LE9-NEXT: std 0, 80(1)
; PC64LE9-NEXT: stfd 30, 48(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 30, 48(1) # 8-byte Folded Spill
; PC64LE9-NEXT: stfd 31, 56(1) # 8-byte Folded Spill
; PC64LE9-NEXT: stxv 63, 32(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 63, 32(1) # 16-byte Folded Spill
; PC64LE9-NEXT: xscvspdpn 1, 0 ; PC64LE9-NEXT: stfd 31, 56(1) # 8-byte Folded Spill
; PC64LE9-NEXT: vmr 31, 2 ; PC64LE9-NEXT: vmr 31, 2
; PC64LE9-NEXT: xscvspdpn 1, 0
; PC64LE9-NEXT: bl nearbyintf ; PC64LE9-NEXT: bl nearbyintf
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: xxswapd 0, 63 ; PC64LE9-NEXT: xxswapd 0, 63
; PC64LE9-NEXT: fmr 31, 1 ; PC64LE9-NEXT: fmr 31, 1
; PC64LE9-NEXT: xscvspdpn 1, 0 ; PC64LE9-NEXT: xscvspdpn 1, 0
; PC64LE9-NEXT: bl nearbyintf ; PC64LE9-NEXT: bl nearbyintf
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: xxsldwi 0, 63, 63, 3 ; PC64LE9-NEXT: xxsldwi 0, 63, 63, 3
Show All 23 Lines %nearby = call <3 x float> @llvm.experimental.constrained.nearbyint.v3f32(
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <3 x float> %nearby ret <3 x float> %nearby
} }
define <3 x double> @constrained_vector_nearby_v3f64(<3 x double> %x) #0 { define <3 x double> @constrained_vector_nearby_v3f64(<3 x double> %x) #0 {
; PC64LE-LABEL: constrained_vector_nearby_v3f64: ; PC64LE-LABEL: constrained_vector_nearby_v3f64:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -80(1) ; PC64LE-NEXT: stdu 1, -80(1)
; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: li 3, 48
; PC64LE-NEXT: std 0, 96(1)
; PC64LE-NEXT: stfd 30, 64(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 30, 64(1) # 8-byte Folded Spill
; PC64LE-NEXT: fmr 30, 2
; PC64LE-NEXT: stfd 31, 72(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 31, 72(1) # 8-byte Folded Spill
; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: fmr 31, 3 ; PC64LE-NEXT: fmr 31, 3
; PC64LE-NEXT: fmr 30, 2 ; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: bl nearbyint ; PC64LE-NEXT: bl nearbyint
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: xxlor 63, 1, 1 ; PC64LE-NEXT: xxlor 63, 1, 1
; PC64LE-NEXT: fmr 1, 30 ; PC64LE-NEXT: fmr 1, 30
; PC64LE-NEXT: bl nearbyint ; PC64LE-NEXT: bl nearbyint
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1
; PC64LE-NEXT: xxmrghd 63, 1, 63 ; PC64LE-NEXT: xxmrghd 63, 1, 63
Show All 11 Lines
; PC64LE-NEXT: addi 1, 1, 80 ; PC64LE-NEXT: addi 1, 1, 80
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_nearby_v3f64: ; PC64LE9-LABEL: constrained_vector_nearby_v3f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -64(1) ; PC64LE9-NEXT: stdu 1, -64(1)
; PC64LE9-NEXT: std 0, 80(1)
; PC64LE9-NEXT: stfd 30, 48(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 30, 48(1) # 8-byte Folded Spill
; PC64LE9-NEXT: stfd 31, 56(1) # 8-byte Folded Spill
; PC64LE9-NEXT: stxv 63, 32(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 63, 32(1) # 16-byte Folded Spill
; PC64LE9-NEXT: stfd 31, 56(1) # 8-byte Folded Spill
; PC64LE9-NEXT: fmr 31, 3 ; PC64LE9-NEXT: fmr 31, 3
; PC64LE9-NEXT: fmr 30, 2 ; PC64LE9-NEXT: fmr 30, 2
; PC64LE9-NEXT: bl nearbyint ; PC64LE9-NEXT: bl nearbyint
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: xscpsgndp 63, 1, 1 ; PC64LE9-NEXT: xscpsgndp 63, 1, 1
; PC64LE9-NEXT: fmr 1, 30 ; PC64LE9-NEXT: fmr 1, 30
; PC64LE9-NEXT: bl nearbyint ; PC64LE9-NEXT: bl nearbyint
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
Show All 20 Lines %nearby = call <3 x double> @llvm.experimental.constrained.nearbyint.v3f64(
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <3 x double> %nearby ret <3 x double> %nearby
} }
define <4 x double> @constrained_vector_nearbyint_v4f64(<4 x double> %x) #0 { define <4 x double> @constrained_vector_nearbyint_v4f64(<4 x double> %x) #0 {
; PC64LE-LABEL: constrained_vector_nearbyint_v4f64: ; PC64LE-LABEL: constrained_vector_nearbyint_v4f64:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -96(1) ; PC64LE-NEXT: stdu 1, -96(1)
; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: li 3, 48
; PC64LE-NEXT: std 0, 112(1)
; PC64LE-NEXT: stxvd2x 61, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 61, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: li 3, 64 ; PC64LE-NEXT: li 3, 64
; PC64LE-NEXT: stxvd2x 62, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 62, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: vmr 30, 2 ; PC64LE-NEXT: vmr 30, 2
; PC64LE-NEXT: li 3, 80 ; PC64LE-NEXT: li 3, 80
; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: vmr 31, 3 ; PC64LE-NEXT: vmr 31, 3
; PC64LE-NEXT: xxlor 1, 62, 62 ; PC64LE-NEXT: xxlor 1, 62, 62
Show All 26 Lines
; PC64LE-NEXT: addi 1, 1, 96 ; PC64LE-NEXT: addi 1, 1, 96
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_nearbyint_v4f64: ; PC64LE9-LABEL: constrained_vector_nearbyint_v4f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -80(1) ; PC64LE9-NEXT: stdu 1, -80(1)
; PC64LE9-NEXT: std 0, 96(1)
; PC64LE9-NEXT: stxv 62, 48(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 62, 48(1) # 16-byte Folded Spill
; PC64LE9-NEXT: vmr 30, 2 ; PC64LE9-NEXT: vmr 30, 2
; PC64LE9-NEXT: xscpsgndp 1, 62, 62 ; PC64LE9-NEXT: xscpsgndp 1, 62, 62
; PC64LE9-NEXT: stxv 61, 32(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 61, 32(1) # 16-byte Folded Spill
; PC64LE9-NEXT: stxv 63, 64(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 63, 64(1) # 16-byte Folded Spill
; PC64LE9-NEXT: vmr 31, 3 ; PC64LE9-NEXT: vmr 31, 3
; PC64LE9-NEXT: bl nearbyint ; PC64LE9-NEXT: bl nearbyint
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
Show All 29 Lines %nearby = call <4 x double> @llvm.experimental.constrained.nearbyint.v4f64(
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <4 x double> %nearby ret <4 x double> %nearby
} }
define <1 x float> @constrained_vector_maxnum_v1f32(<1 x float> %x, <1 x float> %y) #0 { define <1 x float> @constrained_vector_maxnum_v1f32(<1 x float> %x, <1 x float> %y) #0 {
; PC64LE-LABEL: constrained_vector_maxnum_v1f32: ; PC64LE-LABEL: constrained_vector_maxnum_v1f32:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -32(1) ; PC64LE-NEXT: stdu 1, -32(1)
; PC64LE-NEXT: std 0, 48(1)
; PC64LE-NEXT: bl fmaxf ; PC64LE-NEXT: bl fmaxf
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: addi 1, 1, 32 ; PC64LE-NEXT: addi 1, 1, 32
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_maxnum_v1f32: ; PC64LE9-LABEL: constrained_vector_maxnum_v1f32:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -32(1) ; PC64LE9-NEXT: stdu 1, -32(1)
; PC64LE9-NEXT: std 0, 48(1)
; PC64LE9-NEXT: bl fmaxf ; PC64LE9-NEXT: bl fmaxf
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addi 1, 1, 32 ; PC64LE9-NEXT: addi 1, 1, 32
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%max = call <1 x float> @llvm.experimental.constrained.maxnum.v1f32( %max = call <1 x float> @llvm.experimental.constrained.maxnum.v1f32(
Show All 19 Lines %max = call <2 x double> @llvm.experimental.constrained.maxnum.v2f64(
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <2 x double> %max ret <2 x double> %max
} }
define <3 x float> @constrained_vector_maxnum_v3f32(<3 x float> %x, <3 x float> %y) #0 { define <3 x float> @constrained_vector_maxnum_v3f32(<3 x float> %x, <3 x float> %y) #0 {
; PC64LE-LABEL: constrained_vector_maxnum_v3f32: ; PC64LE-LABEL: constrained_vector_maxnum_v3f32:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -96(1) ; PC64LE-NEXT: stdu 1, -96(1)
; PC64LE-NEXT: xxsldwi 0, 34, 34, 1 ; PC64LE-NEXT: xxsldwi 0, 34, 34, 1
; PC64LE-NEXT: xxsldwi 2, 35, 35, 1 ; PC64LE-NEXT: xxsldwi 2, 35, 35, 1
; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: li 3, 48
; PC64LE-NEXT: std 0, 112(1)
; PC64LE-NEXT: stxvd2x 62, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 62, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: li 3, 64 ; PC64LE-NEXT: li 3, 64
; PC64LE-NEXT: vmr 30, 2
; PC64LE-NEXT: stfd 30, 80(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 30, 80(1) # 8-byte Folded Spill
; PC64LE-NEXT: stfd 31, 88(1) # 8-byte Folded Spill
; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: xscvspdpn 1, 0 ; PC64LE-NEXT: xscvspdpn 1, 0
; PC64LE-NEXT: stfd 31, 88(1) # 8-byte Folded Spill
; PC64LE-NEXT: xscvspdpn 2, 2 ; PC64LE-NEXT: xscvspdpn 2, 2
; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: vmr 31, 3 ; PC64LE-NEXT: vmr 31, 3
; PC64LE-NEXT: vmr 30, 2
; PC64LE-NEXT: bl fmaxf ; PC64LE-NEXT: bl fmaxf
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: xxswapd 0, 62 ; PC64LE-NEXT: xxswapd 0, 62
; PC64LE-NEXT: xxswapd 2, 63 ; PC64LE-NEXT: xxswapd 2, 63
; PC64LE-NEXT: fmr 31, 1 ; PC64LE-NEXT: fmr 31, 1
; PC64LE-NEXT: xscvspdpn 1, 0 ; PC64LE-NEXT: xscvspdpn 1, 0
; PC64LE-NEXT: xscvspdpn 2, 2 ; PC64LE-NEXT: xscvspdpn 2, 2
; PC64LE-NEXT: bl fmaxf ; PC64LE-NEXT: bl fmaxf
Show All 23 Lines
; PC64LE-NEXT: addi 1, 1, 96 ; PC64LE-NEXT: addi 1, 1, 96
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_maxnum_v3f32: ; PC64LE9-LABEL: constrained_vector_maxnum_v3f32:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -80(1) ; PC64LE9-NEXT: stdu 1, -80(1)
; PC64LE9-NEXT: xxsldwi 0, 34, 34, 1 ; PC64LE9-NEXT: xxsldwi 0, 34, 34, 1
; PC64LE9-NEXT: std 0, 96(1)
; PC64LE9-NEXT: stfd 30, 64(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 30, 64(1) # 8-byte Folded Spill
; PC64LE9-NEXT: stfd 31, 72(1) # 8-byte Folded Spill
; PC64LE9-NEXT: stxv 62, 32(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 62, 32(1) # 16-byte Folded Spill
; PC64LE9-NEXT: stfd 31, 72(1) # 8-byte Folded Spill
; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill
; PC64LE9-NEXT: xscvspdpn 1, 0 ; PC64LE9-NEXT: xscvspdpn 1, 0
; PC64LE9-NEXT: xxsldwi 0, 35, 35, 1 ; PC64LE9-NEXT: xxsldwi 0, 35, 35, 1
; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill
; PC64LE9-NEXT: xscvspdpn 2, 0
; PC64LE9-NEXT: vmr 31, 3 ; PC64LE9-NEXT: vmr 31, 3
; PC64LE9-NEXT: vmr 30, 2 ; PC64LE9-NEXT: vmr 30, 2
; PC64LE9-NEXT: xscvspdpn 2, 0
; PC64LE9-NEXT: bl fmaxf ; PC64LE9-NEXT: bl fmaxf
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: xxswapd 0, 62 ; PC64LE9-NEXT: xxswapd 0, 62
; PC64LE9-NEXT: fmr 31, 1 ; PC64LE9-NEXT: fmr 31, 1
; PC64LE9-NEXT: xscvspdpn 1, 0 ; PC64LE9-NEXT: xscvspdpn 1, 0
; PC64LE9-NEXT: xxswapd 0, 63 ; PC64LE9-NEXT: xxswapd 0, 63
; PC64LE9-NEXT: xscvspdpn 2, 0 ; PC64LE9-NEXT: xscvspdpn 2, 0
; PC64LE9-NEXT: bl fmaxf ; PC64LE9-NEXT: bl fmaxf
Show All 28 Lines %max = call <3 x float> @llvm.experimental.constrained.maxnum.v3f32(
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <3 x float> %max ret <3 x float> %max
} }
define <3 x double> @constrained_vector_max_v3f64(<3 x double> %x, <3 x double> %y) #0 { define <3 x double> @constrained_vector_max_v3f64(<3 x double> %x, <3 x double> %y) #0 {
; PC64LE-LABEL: constrained_vector_max_v3f64: ; PC64LE-LABEL: constrained_vector_max_v3f64:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -64(1) ; PC64LE-NEXT: stdu 1, -64(1)
; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1
; PC64LE-NEXT: # kill: def $f5 killed $f5 def $vsl5 ; PC64LE-NEXT: # kill: def $f5 killed $f5 def $vsl5
; PC64LE-NEXT: # kill: def $f4 killed $f4 def $vsl4 ; PC64LE-NEXT: # kill: def $f4 killed $f4 def $vsl4
; PC64LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 ; PC64LE-NEXT: # kill: def $f2 killed $f2 def $vsl2
; PC64LE-NEXT: xxmrghd 0, 5, 4 ; PC64LE-NEXT: xxmrghd 0, 5, 4
; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: li 3, 48
; PC64LE-NEXT: std 0, 80(1)
; PC64LE-NEXT: xxmrghd 1, 2, 1 ; PC64LE-NEXT: xxmrghd 1, 2, 1
; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: fmr 2, 6 ; PC64LE-NEXT: fmr 2, 6
; PC64LE-NEXT: xvmaxdp 63, 1, 0 ; PC64LE-NEXT: xvmaxdp 63, 1, 0
; PC64LE-NEXT: fmr 1, 3 ; PC64LE-NEXT: fmr 1, 3
; PC64LE-NEXT: bl fmax ; PC64LE-NEXT: bl fmax
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: xxswapd 0, 63 ; PC64LE-NEXT: xxswapd 0, 63
; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: li 3, 48
; PC64LE-NEXT: xxlor 2, 63, 63 ; PC64LE-NEXT: xxlor 2, 63, 63
; PC64LE-NEXT: lxvd2x 63, 1, 3 # 16-byte Folded Reload ; PC64LE-NEXT: lxvd2x 63, 1, 3 # 16-byte Folded Reload
; PC64LE-NEXT: fmr 3, 1 ; PC64LE-NEXT: fmr 3, 1
; PC64LE-NEXT: fmr 1, 0 ; PC64LE-NEXT: fmr 1, 0
; PC64LE-NEXT: addi 1, 1, 64 ; PC64LE-NEXT: addi 1, 1, 64
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_max_v3f64: ; PC64LE9-LABEL: constrained_vector_max_v3f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -48(1) ; PC64LE9-NEXT: stdu 1, -48(1)
; PC64LE9-NEXT: # kill: def $f5 killed $f5 def $vsl5 ; PC64LE9-NEXT: # kill: def $f5 killed $f5 def $vsl5
; PC64LE9-NEXT: # kill: def $f4 killed $f4 def $vsl4 ; PC64LE9-NEXT: # kill: def $f4 killed $f4 def $vsl4
; PC64LE9-NEXT: # kill: def $f2 killed $f2 def $vsl2 ; PC64LE9-NEXT: # kill: def $f2 killed $f2 def $vsl2
; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1
; PC64LE9-NEXT: xxmrghd 0, 5, 4 ; PC64LE9-NEXT: xxmrghd 0, 5, 4
; PC64LE9-NEXT: xxmrghd 1, 2, 1 ; PC64LE9-NEXT: xxmrghd 1, 2, 1
; PC64LE9-NEXT: std 0, 64(1)
; PC64LE9-NEXT: fmr 2, 6 ; PC64LE9-NEXT: fmr 2, 6
; PC64LE9-NEXT: stxv 63, 32(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 63, 32(1) # 16-byte Folded Spill
; PC64LE9-NEXT: xvmaxdp 63, 1, 0 ; PC64LE9-NEXT: xvmaxdp 63, 1, 0
; PC64LE9-NEXT: fmr 1, 3 ; PC64LE9-NEXT: fmr 1, 3
; PC64LE9-NEXT: bl fmax ; PC64LE9-NEXT: bl fmax
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: fmr 3, 1 ; PC64LE9-NEXT: fmr 3, 1
; PC64LE9-NEXT: xxswapd 1, 63 ; PC64LE9-NEXT: xxswapd 1, 63
Show All 31 Lines %max = call <4 x double> @llvm.experimental.constrained.maxnum.v4f64(
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <4 x double> %max ret <4 x double> %max
} }
define <1 x float> @constrained_vector_minnum_v1f32(<1 x float> %x, <1 x float> %y) #0 { define <1 x float> @constrained_vector_minnum_v1f32(<1 x float> %x, <1 x float> %y) #0 {
; PC64LE-LABEL: constrained_vector_minnum_v1f32: ; PC64LE-LABEL: constrained_vector_minnum_v1f32:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -32(1) ; PC64LE-NEXT: stdu 1, -32(1)
; PC64LE-NEXT: std 0, 48(1)
; PC64LE-NEXT: bl fminf ; PC64LE-NEXT: bl fminf
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: addi 1, 1, 32 ; PC64LE-NEXT: addi 1, 1, 32
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_minnum_v1f32: ; PC64LE9-LABEL: constrained_vector_minnum_v1f32:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -32(1) ; PC64LE9-NEXT: stdu 1, -32(1)
; PC64LE9-NEXT: std 0, 48(1)
; PC64LE9-NEXT: bl fminf ; PC64LE9-NEXT: bl fminf
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addi 1, 1, 32 ; PC64LE9-NEXT: addi 1, 1, 32
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%min = call <1 x float> @llvm.experimental.constrained.minnum.v1f32( %min = call <1 x float> @llvm.experimental.constrained.minnum.v1f32(
Show All 19 Lines %min = call <2 x double> @llvm.experimental.constrained.minnum.v2f64(
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <2 x double> %min ret <2 x double> %min
} }
define <3 x float> @constrained_vector_minnum_v3f32(<3 x float> %x, <3 x float> %y) #0 { define <3 x float> @constrained_vector_minnum_v3f32(<3 x float> %x, <3 x float> %y) #0 {
; PC64LE-LABEL: constrained_vector_minnum_v3f32: ; PC64LE-LABEL: constrained_vector_minnum_v3f32:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -96(1) ; PC64LE-NEXT: stdu 1, -96(1)
; PC64LE-NEXT: xxsldwi 0, 34, 34, 1 ; PC64LE-NEXT: xxsldwi 0, 34, 34, 1
; PC64LE-NEXT: xxsldwi 2, 35, 35, 1 ; PC64LE-NEXT: xxsldwi 2, 35, 35, 1
; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: li 3, 48
; PC64LE-NEXT: std 0, 112(1)
; PC64LE-NEXT: stxvd2x 62, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 62, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: li 3, 64 ; PC64LE-NEXT: li 3, 64
; PC64LE-NEXT: vmr 30, 2
; PC64LE-NEXT: stfd 30, 80(1) # 8-byte Folded Spill ; PC64LE-NEXT: stfd 30, 80(1) # 8-byte Folded Spill
; PC64LE-NEXT: stfd 31, 88(1) # 8-byte Folded Spill
; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: xscvspdpn 1, 0 ; PC64LE-NEXT: xscvspdpn 1, 0
; PC64LE-NEXT: stfd 31, 88(1) # 8-byte Folded Spill
; PC64LE-NEXT: xscvspdpn 2, 2 ; PC64LE-NEXT: xscvspdpn 2, 2
; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: vmr 31, 3 ; PC64LE-NEXT: vmr 31, 3
; PC64LE-NEXT: vmr 30, 2
; PC64LE-NEXT: bl fminf ; PC64LE-NEXT: bl fminf
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: xxswapd 0, 62 ; PC64LE-NEXT: xxswapd 0, 62
; PC64LE-NEXT: xxswapd 2, 63 ; PC64LE-NEXT: xxswapd 2, 63
; PC64LE-NEXT: fmr 31, 1 ; PC64LE-NEXT: fmr 31, 1
; PC64LE-NEXT: xscvspdpn 1, 0 ; PC64LE-NEXT: xscvspdpn 1, 0
; PC64LE-NEXT: xscvspdpn 2, 2 ; PC64LE-NEXT: xscvspdpn 2, 2
; PC64LE-NEXT: bl fminf ; PC64LE-NEXT: bl fminf
Show All 23 Lines
; PC64LE-NEXT: addi 1, 1, 96 ; PC64LE-NEXT: addi 1, 1, 96
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_minnum_v3f32: ; PC64LE9-LABEL: constrained_vector_minnum_v3f32:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -80(1) ; PC64LE9-NEXT: stdu 1, -80(1)
; PC64LE9-NEXT: xxsldwi 0, 34, 34, 1 ; PC64LE9-NEXT: xxsldwi 0, 34, 34, 1
; PC64LE9-NEXT: std 0, 96(1)
; PC64LE9-NEXT: stfd 30, 64(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 30, 64(1) # 8-byte Folded Spill
; PC64LE9-NEXT: stfd 31, 72(1) # 8-byte Folded Spill
; PC64LE9-NEXT: stxv 62, 32(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 62, 32(1) # 16-byte Folded Spill
; PC64LE9-NEXT: stfd 31, 72(1) # 8-byte Folded Spill
; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill
; PC64LE9-NEXT: xscvspdpn 1, 0 ; PC64LE9-NEXT: xscvspdpn 1, 0
; PC64LE9-NEXT: xxsldwi 0, 35, 35, 1 ; PC64LE9-NEXT: xxsldwi 0, 35, 35, 1
; PC64LE9-NEXT: stxv 63, 48(1) # 16-byte Folded Spill
; PC64LE9-NEXT: xscvspdpn 2, 0
; PC64LE9-NEXT: vmr 31, 3 ; PC64LE9-NEXT: vmr 31, 3
; PC64LE9-NEXT: vmr 30, 2 ; PC64LE9-NEXT: vmr 30, 2
; PC64LE9-NEXT: xscvspdpn 2, 0
; PC64LE9-NEXT: bl fminf ; PC64LE9-NEXT: bl fminf
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: xxswapd 0, 62 ; PC64LE9-NEXT: xxswapd 0, 62
; PC64LE9-NEXT: fmr 31, 1 ; PC64LE9-NEXT: fmr 31, 1
; PC64LE9-NEXT: xscvspdpn 1, 0 ; PC64LE9-NEXT: xscvspdpn 1, 0
; PC64LE9-NEXT: xxswapd 0, 63 ; PC64LE9-NEXT: xxswapd 0, 63
; PC64LE9-NEXT: xscvspdpn 2, 0 ; PC64LE9-NEXT: xscvspdpn 2, 0
; PC64LE9-NEXT: bl fminf ; PC64LE9-NEXT: bl fminf
Show All 28 Lines %min = call <3 x float> @llvm.experimental.constrained.minnum.v3f32(
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <3 x float> %min ret <3 x float> %min
} }
define <3 x double> @constrained_vector_min_v3f64(<3 x double> %x, <3 x double> %y) #0 { define <3 x double> @constrained_vector_min_v3f64(<3 x double> %x, <3 x double> %y) #0 {
; PC64LE-LABEL: constrained_vector_min_v3f64: ; PC64LE-LABEL: constrained_vector_min_v3f64:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0 ; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: std 0, 16(1)
; PC64LE-NEXT: stdu 1, -64(1) ; PC64LE-NEXT: stdu 1, -64(1)
; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1
; PC64LE-NEXT: # kill: def $f5 killed $f5 def $vsl5 ; PC64LE-NEXT: # kill: def $f5 killed $f5 def $vsl5
; PC64LE-NEXT: # kill: def $f4 killed $f4 def $vsl4 ; PC64LE-NEXT: # kill: def $f4 killed $f4 def $vsl4
; PC64LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 ; PC64LE-NEXT: # kill: def $f2 killed $f2 def $vsl2
; PC64LE-NEXT: xxmrghd 0, 5, 4 ; PC64LE-NEXT: xxmrghd 0, 5, 4
; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: li 3, 48
; PC64LE-NEXT: std 0, 80(1)
; PC64LE-NEXT: xxmrghd 1, 2, 1 ; PC64LE-NEXT: xxmrghd 1, 2, 1
; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill ; PC64LE-NEXT: stxvd2x 63, 1, 3 # 16-byte Folded Spill
; PC64LE-NEXT: fmr 2, 6 ; PC64LE-NEXT: fmr 2, 6
; PC64LE-NEXT: xvmindp 63, 1, 0 ; PC64LE-NEXT: xvmindp 63, 1, 0
; PC64LE-NEXT: fmr 1, 3 ; PC64LE-NEXT: fmr 1, 3
; PC64LE-NEXT: bl fmin ; PC64LE-NEXT: bl fmin
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: xxswapd 0, 63 ; PC64LE-NEXT: xxswapd 0, 63
; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: li 3, 48
; PC64LE-NEXT: xxlor 2, 63, 63 ; PC64LE-NEXT: xxlor 2, 63, 63
; PC64LE-NEXT: lxvd2x 63, 1, 3 # 16-byte Folded Reload ; PC64LE-NEXT: lxvd2x 63, 1, 3 # 16-byte Folded Reload
; PC64LE-NEXT: fmr 3, 1 ; PC64LE-NEXT: fmr 3, 1
; PC64LE-NEXT: fmr 1, 0 ; PC64LE-NEXT: fmr 1, 0
; PC64LE-NEXT: addi 1, 1, 64 ; PC64LE-NEXT: addi 1, 1, 64
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_min_v3f64: ; PC64LE9-LABEL: constrained_vector_min_v3f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -48(1) ; PC64LE9-NEXT: stdu 1, -48(1)
; PC64LE9-NEXT: # kill: def $f5 killed $f5 def $vsl5 ; PC64LE9-NEXT: # kill: def $f5 killed $f5 def $vsl5
; PC64LE9-NEXT: # kill: def $f4 killed $f4 def $vsl4 ; PC64LE9-NEXT: # kill: def $f4 killed $f4 def $vsl4
; PC64LE9-NEXT: # kill: def $f2 killed $f2 def $vsl2 ; PC64LE9-NEXT: # kill: def $f2 killed $f2 def $vsl2
; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1
; PC64LE9-NEXT: xxmrghd 0, 5, 4 ; PC64LE9-NEXT: xxmrghd 0, 5, 4
; PC64LE9-NEXT: xxmrghd 1, 2, 1 ; PC64LE9-NEXT: xxmrghd 1, 2, 1
; PC64LE9-NEXT: std 0, 64(1)
; PC64LE9-NEXT: fmr 2, 6 ; PC64LE9-NEXT: fmr 2, 6
; PC64LE9-NEXT: stxv 63, 32(1) # 16-byte Folded Spill ; PC64LE9-NEXT: stxv 63, 32(1) # 16-byte Folded Spill
; PC64LE9-NEXT: xvmindp 63, 1, 0 ; PC64LE9-NEXT: xvmindp 63, 1, 0
; PC64LE9-NEXT: fmr 1, 3 ; PC64LE9-NEXT: fmr 1, 3
; PC64LE9-NEXT: bl fmin ; PC64LE9-NEXT: bl fmin
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: fmr 3, 1 ; PC64LE9-NEXT: fmr 3, 1
; PC64LE9-NEXT: xxswapd 1, 63 ; PC64LE9-NEXT: xxswapd 1, 63
▲ Show 20 Lines • Show All 3,035 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/vector-reduce-fadd.ll

Show First 20 Lines • Show All 3,487 Lines • ▼ Show 20 Lines
;; ;;
;; Vectors of ppc_fp128 ;; Vectors of ppc_fp128
;; ;;
define dso_local ppc_fp128 @v2ppcf128(<2 x ppc_fp128> %a) local_unnamed_addr #0 { define dso_local ppc_fp128 @v2ppcf128(<2 x ppc_fp128> %a) local_unnamed_addr #0 {
; PWR9LE-LABEL: v2ppcf128: ; PWR9LE-LABEL: v2ppcf128:
; PWR9LE: # %bb.0: # %entry ; PWR9LE: # %bb.0: # %entry
; PWR9LE-NEXT: mflr r0 ; PWR9LE-NEXT: mflr r0
; PWR9LE-NEXT: std r0, 16(r1)
; PWR9LE-NEXT: stdu r1, -32(r1) ; PWR9LE-NEXT: stdu r1, -32(r1)
; PWR9LE-NEXT: std r0, 48(r1)
; PWR9LE-NEXT: bl __gcc_qadd ; PWR9LE-NEXT: bl __gcc_qadd
; PWR9LE-NEXT: nop ; PWR9LE-NEXT: nop
; PWR9LE-NEXT: addi r1, r1, 32 ; PWR9LE-NEXT: addi r1, r1, 32
; PWR9LE-NEXT: ld r0, 16(r1) ; PWR9LE-NEXT: ld r0, 16(r1)
; PWR9LE-NEXT: mtlr r0 ; PWR9LE-NEXT: mtlr r0
; PWR9LE-NEXT: blr ; PWR9LE-NEXT: blr
; ;
; PWR9BE-LABEL: v2ppcf128: ; PWR9BE-LABEL: v2ppcf128:
; PWR9BE: # %bb.0: # %entry ; PWR9BE: # %bb.0: # %entry
; PWR9BE-NEXT: mflr r0 ; PWR9BE-NEXT: mflr r0
; PWR9BE-NEXT: std r0, 16(r1)
; PWR9BE-NEXT: stdu r1, -112(r1) ; PWR9BE-NEXT: stdu r1, -112(r1)
; PWR9BE-NEXT: std r0, 128(r1)
; PWR9BE-NEXT: bl __gcc_qadd ; PWR9BE-NEXT: bl __gcc_qadd
; PWR9BE-NEXT: nop ; PWR9BE-NEXT: nop
; PWR9BE-NEXT: addi r1, r1, 112 ; PWR9BE-NEXT: addi r1, r1, 112
; PWR9BE-NEXT: ld r0, 16(r1) ; PWR9BE-NEXT: ld r0, 16(r1)
; PWR9BE-NEXT: mtlr r0 ; PWR9BE-NEXT: mtlr r0
; PWR9BE-NEXT: blr ; PWR9BE-NEXT: blr
; ;
; PWR10LE-LABEL: v2ppcf128: ; PWR10LE-LABEL: v2ppcf128:
Show All 24 Lines
} }
define dso_local ppc_fp128 @v2ppcf128_b(<2 x ppc_fp128> %a, ppc_fp128 %b) local_unnamed_addr #0 { define dso_local ppc_fp128 @v2ppcf128_b(<2 x ppc_fp128> %a, ppc_fp128 %b) local_unnamed_addr #0 {
; PWR9LE-LABEL: v2ppcf128_b: ; PWR9LE-LABEL: v2ppcf128_b:
; PWR9LE: # %bb.0: # %entry ; PWR9LE: # %bb.0: # %entry
; PWR9LE-NEXT: mflr r0 ; PWR9LE-NEXT: mflr r0
; PWR9LE-NEXT: stfd f30, -16(r1) # 8-byte Folded Spill ; PWR9LE-NEXT: stfd f30, -16(r1) # 8-byte Folded Spill
; PWR9LE-NEXT: stfd f31, -8(r1) # 8-byte Folded Spill ; PWR9LE-NEXT: stfd f31, -8(r1) # 8-byte Folded Spill
; PWR9LE-NEXT: std r0, 16(r1)
; PWR9LE-NEXT: stdu r1, -48(r1) ; PWR9LE-NEXT: stdu r1, -48(r1)
; PWR9LE-NEXT: fmr f31, f4 ; PWR9LE-NEXT: fmr f31, f4
; PWR9LE-NEXT: fmr f30, f3 ; PWR9LE-NEXT: fmr f30, f3
; PWR9LE-NEXT: fmr f4, f2 ; PWR9LE-NEXT: fmr f4, f2
; PWR9LE-NEXT: fmr f3, f1 ; PWR9LE-NEXT: fmr f3, f1
; PWR9LE-NEXT: fmr f1, f5 ; PWR9LE-NEXT: fmr f1, f5
; PWR9LE-NEXT: fmr f2, f6 ; PWR9LE-NEXT: fmr f2, f6
; PWR9LE-NEXT: std r0, 64(r1)
; PWR9LE-NEXT: bl __gcc_qadd ; PWR9LE-NEXT: bl __gcc_qadd
; PWR9LE-NEXT: nop ; PWR9LE-NEXT: nop
; PWR9LE-NEXT: fmr f3, f30 ; PWR9LE-NEXT: fmr f3, f30
; PWR9LE-NEXT: fmr f4, f31 ; PWR9LE-NEXT: fmr f4, f31
; PWR9LE-NEXT: bl __gcc_qadd ; PWR9LE-NEXT: bl __gcc_qadd
; PWR9LE-NEXT: nop ; PWR9LE-NEXT: nop
; PWR9LE-NEXT: addi r1, r1, 48 ; PWR9LE-NEXT: addi r1, r1, 48
; PWR9LE-NEXT: ld r0, 16(r1) ; PWR9LE-NEXT: ld r0, 16(r1)
; PWR9LE-NEXT: lfd f31, -8(r1) # 8-byte Folded Reload ; PWR9LE-NEXT: lfd f31, -8(r1) # 8-byte Folded Reload
; PWR9LE-NEXT: lfd f30, -16(r1) # 8-byte Folded Reload ; PWR9LE-NEXT: lfd f30, -16(r1) # 8-byte Folded Reload
; PWR9LE-NEXT: mtlr r0 ; PWR9LE-NEXT: mtlr r0
; PWR9LE-NEXT: blr ; PWR9LE-NEXT: blr
; ;
; PWR9BE-LABEL: v2ppcf128_b: ; PWR9BE-LABEL: v2ppcf128_b:
; PWR9BE: # %bb.0: # %entry ; PWR9BE: # %bb.0: # %entry
; PWR9BE-NEXT: mflr r0 ; PWR9BE-NEXT: mflr r0
; PWR9BE-NEXT: std r0, 16(r1)
; PWR9BE-NEXT: stdu r1, -128(r1) ; PWR9BE-NEXT: stdu r1, -128(r1)
; PWR9BE-NEXT: std r0, 144(r1)
; PWR9BE-NEXT: stfd f30, 112(r1) # 8-byte Folded Spill ; PWR9BE-NEXT: stfd f30, 112(r1) # 8-byte Folded Spill
; PWR9BE-NEXT: stfd f31, 120(r1) # 8-byte Folded Spill ; PWR9BE-NEXT: stfd f31, 120(r1) # 8-byte Folded Spill
; PWR9BE-NEXT: fmr f31, f4 ; PWR9BE-NEXT: fmr f31, f4
; PWR9BE-NEXT: fmr f30, f3 ; PWR9BE-NEXT: fmr f30, f3
; PWR9BE-NEXT: fmr f4, f2 ; PWR9BE-NEXT: fmr f4, f2
; PWR9BE-NEXT: fmr f3, f1 ; PWR9BE-NEXT: fmr f3, f1
; PWR9BE-NEXT: fmr f1, f5 ; PWR9BE-NEXT: fmr f1, f5
; PWR9BE-NEXT: fmr f2, f6 ; PWR9BE-NEXT: fmr f2, f6
▲ Show 20 Lines • Show All 63 Lines • ▼ Show 20 Linesentry:
%0 = call ppc_fp128 @llvm.vector.reduce.fadd.v2ppcf128(ppc_fp128 %b, <2 x ppc_fp128> %a) %0 = call ppc_fp128 @llvm.vector.reduce.fadd.v2ppcf128(ppc_fp128 %b, <2 x ppc_fp128> %a)
ret ppc_fp128 %0 ret ppc_fp128 %0
} }
define dso_local ppc_fp128 @v2ppcf128_fast(<2 x ppc_fp128> %a) local_unnamed_addr #0 { define dso_local ppc_fp128 @v2ppcf128_fast(<2 x ppc_fp128> %a) local_unnamed_addr #0 {
; PWR9LE-LABEL: v2ppcf128_fast: ; PWR9LE-LABEL: v2ppcf128_fast:
; PWR9LE: # %bb.0: # %entry ; PWR9LE: # %bb.0: # %entry
; PWR9LE-NEXT: mflr r0 ; PWR9LE-NEXT: mflr r0
; PWR9LE-NEXT: std r0, 16(r1)
; PWR9LE-NEXT: stdu r1, -64(r1) ; PWR9LE-NEXT: stdu r1, -64(r1)
; PWR9LE-NEXT: std r0, 80(r1)
; PWR9LE-NEXT: bl __gcc_qadd ; PWR9LE-NEXT: bl __gcc_qadd
; PWR9LE-NEXT: nop ; PWR9LE-NEXT: nop
; PWR9LE-NEXT: stfd f2, 40(r1) ; PWR9LE-NEXT: stfd f2, 40(r1)
; PWR9LE-NEXT: stfd f1, 32(r1) ; PWR9LE-NEXT: stfd f1, 32(r1)
; PWR9LE-NEXT: lxv vs1, 32(r1) ; PWR9LE-NEXT: lxv vs1, 32(r1)
; PWR9LE-NEXT: xxswapd vs2, vs1 ; PWR9LE-NEXT: xxswapd vs2, vs1
; PWR9LE-NEXT: # kill: def $f1 killed $f1 killed $vsl1 ; PWR9LE-NEXT: # kill: def $f1 killed $f1 killed $vsl1
; PWR9LE-NEXT: # kill: def $f2 killed $f2 killed $vsl2 ; PWR9LE-NEXT: # kill: def $f2 killed $f2 killed $vsl2
; PWR9LE-NEXT: addi r1, r1, 64 ; PWR9LE-NEXT: addi r1, r1, 64
; PWR9LE-NEXT: ld r0, 16(r1) ; PWR9LE-NEXT: ld r0, 16(r1)
; PWR9LE-NEXT: mtlr r0 ; PWR9LE-NEXT: mtlr r0
; PWR9LE-NEXT: blr ; PWR9LE-NEXT: blr
; ;
; PWR9BE-LABEL: v2ppcf128_fast: ; PWR9BE-LABEL: v2ppcf128_fast:
; PWR9BE: # %bb.0: # %entry ; PWR9BE: # %bb.0: # %entry
; PWR9BE-NEXT: mflr r0 ; PWR9BE-NEXT: mflr r0
; PWR9BE-NEXT: std r0, 16(r1)
; PWR9BE-NEXT: stdu r1, -144(r1) ; PWR9BE-NEXT: stdu r1, -144(r1)
; PWR9BE-NEXT: std r0, 160(r1)
; PWR9BE-NEXT: bl __gcc_qadd ; PWR9BE-NEXT: bl __gcc_qadd
; PWR9BE-NEXT: nop ; PWR9BE-NEXT: nop
; PWR9BE-NEXT: stfd f2, 120(r1) ; PWR9BE-NEXT: stfd f2, 120(r1)
; PWR9BE-NEXT: stfd f1, 112(r1) ; PWR9BE-NEXT: stfd f1, 112(r1)
; PWR9BE-NEXT: lxv vs1, 112(r1) ; PWR9BE-NEXT: lxv vs1, 112(r1)
; PWR9BE-NEXT: xxswapd vs2, vs1 ; PWR9BE-NEXT: xxswapd vs2, vs1
; PWR9BE-NEXT: # kill: def $f1 killed $f1 killed $vsl1 ; PWR9BE-NEXT: # kill: def $f1 killed $f1 killed $vsl1
; PWR9BE-NEXT: # kill: def $f2 killed $f2 killed $vsl2 ; PWR9BE-NEXT: # kill: def $f2 killed $f2 killed $vsl2
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define dso_local ppc_fp128 @v4ppcf128(<4 x ppc_fp128> %a) local_unnamed_addr #0 { define dso_local ppc_fp128 @v4ppcf128(<4 x ppc_fp128> %a) local_unnamed_addr #0 {
; PWR9LE-LABEL: v4ppcf128: ; PWR9LE-LABEL: v4ppcf128:
; PWR9LE: # %bb.0: # %entry ; PWR9LE: # %bb.0: # %entry
; PWR9LE-NEXT: mflr r0 ; PWR9LE-NEXT: mflr r0
; PWR9LE-NEXT: stfd f28, -32(r1) # 8-byte Folded Spill ; PWR9LE-NEXT: stfd f28, -32(r1) # 8-byte Folded Spill
; PWR9LE-NEXT: stfd f29, -24(r1) # 8-byte Folded Spill ; PWR9LE-NEXT: stfd f29, -24(r1) # 8-byte Folded Spill
; PWR9LE-NEXT: stfd f30, -16(r1) # 8-byte Folded Spill ; PWR9LE-NEXT: stfd f30, -16(r1) # 8-byte Folded Spill
; PWR9LE-NEXT: stfd f31, -8(r1) # 8-byte Folded Spill ; PWR9LE-NEXT: stfd f31, -8(r1) # 8-byte Folded Spill
; PWR9LE-NEXT: std r0, 16(r1)
; PWR9LE-NEXT: stdu r1, -64(r1) ; PWR9LE-NEXT: stdu r1, -64(r1)
; PWR9LE-NEXT: std r0, 80(r1)
; PWR9LE-NEXT: fmr f31, f8 ; PWR9LE-NEXT: fmr f31, f8
; PWR9LE-NEXT: fmr f30, f7 ; PWR9LE-NEXT: fmr f30, f7
; PWR9LE-NEXT: fmr f29, f6 ; PWR9LE-NEXT: fmr f29, f6
; PWR9LE-NEXT: fmr f28, f5 ; PWR9LE-NEXT: fmr f28, f5
; PWR9LE-NEXT: bl __gcc_qadd ; PWR9LE-NEXT: bl __gcc_qadd
; PWR9LE-NEXT: nop ; PWR9LE-NEXT: nop
; PWR9LE-NEXT: fmr f3, f28 ; PWR9LE-NEXT: fmr f3, f28
; PWR9LE-NEXT: fmr f4, f29 ; PWR9LE-NEXT: fmr f4, f29
Show All 10 Lines
; PWR9LE-NEXT: mtlr r0 ; PWR9LE-NEXT: mtlr r0
; PWR9LE-NEXT: lfd f29, -24(r1) # 8-byte Folded Reload ; PWR9LE-NEXT: lfd f29, -24(r1) # 8-byte Folded Reload
; PWR9LE-NEXT: lfd f28, -32(r1) # 8-byte Folded Reload ; PWR9LE-NEXT: lfd f28, -32(r1) # 8-byte Folded Reload
; PWR9LE-NEXT: blr ; PWR9LE-NEXT: blr
; ;
; PWR9BE-LABEL: v4ppcf128: ; PWR9BE-LABEL: v4ppcf128:
; PWR9BE: # %bb.0: # %entry ; PWR9BE: # %bb.0: # %entry
; PWR9BE-NEXT: mflr r0 ; PWR9BE-NEXT: mflr r0
; PWR9BE-NEXT: std r0, 16(r1)
; PWR9BE-NEXT: stdu r1, -144(r1) ; PWR9BE-NEXT: stdu r1, -144(r1)
; PWR9BE-NEXT: std r0, 160(r1)
; PWR9BE-NEXT: stfd f28, 112(r1) # 8-byte Folded Spill ; PWR9BE-NEXT: stfd f28, 112(r1) # 8-byte Folded Spill
; PWR9BE-NEXT: stfd f29, 120(r1) # 8-byte Folded Spill ; PWR9BE-NEXT: stfd f29, 120(r1) # 8-byte Folded Spill
; PWR9BE-NEXT: stfd f30, 128(r1) # 8-byte Folded Spill ; PWR9BE-NEXT: stfd f30, 128(r1) # 8-byte Folded Spill
; PWR9BE-NEXT: stfd f31, 136(r1) # 8-byte Folded Spill ; PWR9BE-NEXT: stfd f31, 136(r1) # 8-byte Folded Spill
; PWR9BE-NEXT: fmr f31, f8 ; PWR9BE-NEXT: fmr f31, f8
; PWR9BE-NEXT: fmr f30, f7 ; PWR9BE-NEXT: fmr f30, f7
; PWR9BE-NEXT: fmr f29, f6 ; PWR9BE-NEXT: fmr f29, f6
; PWR9BE-NEXT: fmr f28, f5 ; PWR9BE-NEXT: fmr f28, f5
▲ Show 20 Lines • Show All 86 Lines • ▼ Show 20 Lines
; PWR9LE: # %bb.0: # %entry ; PWR9LE: # %bb.0: # %entry
; PWR9LE-NEXT: mflr r0 ; PWR9LE-NEXT: mflr r0
; PWR9LE-NEXT: stfd f26, -48(r1) # 8-byte Folded Spill ; PWR9LE-NEXT: stfd f26, -48(r1) # 8-byte Folded Spill
; PWR9LE-NEXT: stfd f27, -40(r1) # 8-byte Folded Spill ; PWR9LE-NEXT: stfd f27, -40(r1) # 8-byte Folded Spill
; PWR9LE-NEXT: stfd f28, -32(r1) # 8-byte Folded Spill ; PWR9LE-NEXT: stfd f28, -32(r1) # 8-byte Folded Spill
; PWR9LE-NEXT: stfd f29, -24(r1) # 8-byte Folded Spill ; PWR9LE-NEXT: stfd f29, -24(r1) # 8-byte Folded Spill
; PWR9LE-NEXT: stfd f30, -16(r1) # 8-byte Folded Spill ; PWR9LE-NEXT: stfd f30, -16(r1) # 8-byte Folded Spill
; PWR9LE-NEXT: stfd f31, -8(r1) # 8-byte Folded Spill ; PWR9LE-NEXT: stfd f31, -8(r1) # 8-byte Folded Spill
; PWR9LE-NEXT: std r0, 16(r1)
; PWR9LE-NEXT: stdu r1, -80(r1) ; PWR9LE-NEXT: stdu r1, -80(r1)
; PWR9LE-NEXT: fmr f27, f4 ; PWR9LE-NEXT: fmr f27, f4
; PWR9LE-NEXT: fmr f26, f3 ; PWR9LE-NEXT: fmr f26, f3
; PWR9LE-NEXT: fmr f4, f2 ; PWR9LE-NEXT: fmr f4, f2
; PWR9LE-NEXT: fmr f3, f1 ; PWR9LE-NEXT: fmr f3, f1
; PWR9LE-NEXT: fmr f1, f9 ; PWR9LE-NEXT: fmr f1, f9
; PWR9LE-NEXT: fmr f2, f10 ; PWR9LE-NEXT: fmr f2, f10
; PWR9LE-NEXT: std r0, 96(r1)
; PWR9LE-NEXT: fmr f31, f8 ; PWR9LE-NEXT: fmr f31, f8
; PWR9LE-NEXT: fmr f30, f7 ; PWR9LE-NEXT: fmr f30, f7
; PWR9LE-NEXT: fmr f29, f6 ; PWR9LE-NEXT: fmr f29, f6
; PWR9LE-NEXT: fmr f28, f5 ; PWR9LE-NEXT: fmr f28, f5
; PWR9LE-NEXT: bl __gcc_qadd ; PWR9LE-NEXT: bl __gcc_qadd
; PWR9LE-NEXT: nop ; PWR9LE-NEXT: nop
; PWR9LE-NEXT: fmr f3, f26 ; PWR9LE-NEXT: fmr f3, f26
; PWR9LE-NEXT: fmr f4, f27 ; PWR9LE-NEXT: fmr f4, f27
Show All 16 Lines
; PWR9LE-NEXT: lfd f28, -32(r1) # 8-byte Folded Reload ; PWR9LE-NEXT: lfd f28, -32(r1) # 8-byte Folded Reload
; PWR9LE-NEXT: lfd f27, -40(r1) # 8-byte Folded Reload ; PWR9LE-NEXT: lfd f27, -40(r1) # 8-byte Folded Reload
; PWR9LE-NEXT: lfd f26, -48(r1) # 8-byte Folded Reload ; PWR9LE-NEXT: lfd f26, -48(r1) # 8-byte Folded Reload
; PWR9LE-NEXT: blr ; PWR9LE-NEXT: blr
; ;
; PWR9BE-LABEL: v4ppcf128_b: ; PWR9BE-LABEL: v4ppcf128_b:
; PWR9BE: # %bb.0: # %entry ; PWR9BE: # %bb.0: # %entry
; PWR9BE-NEXT: mflr r0 ; PWR9BE-NEXT: mflr r0
; PWR9BE-NEXT: std r0, 16(r1)
; PWR9BE-NEXT: stdu r1, -160(r1) ; PWR9BE-NEXT: stdu r1, -160(r1)
; PWR9BE-NEXT: std r0, 176(r1)
; PWR9BE-NEXT: stfd f26, 112(r1) # 8-byte Folded Spill ; PWR9BE-NEXT: stfd f26, 112(r1) # 8-byte Folded Spill
; PWR9BE-NEXT: stfd f27, 120(r1) # 8-byte Folded Spill ; PWR9BE-NEXT: stfd f27, 120(r1) # 8-byte Folded Spill
; PWR9BE-NEXT: fmr f27, f4 ; PWR9BE-NEXT: fmr f27, f4
; PWR9BE-NEXT: fmr f26, f3 ; PWR9BE-NEXT: fmr f26, f3
; PWR9BE-NEXT: fmr f4, f2 ; PWR9BE-NEXT: fmr f4, f2
; PWR9BE-NEXT: fmr f3, f1 ; PWR9BE-NEXT: fmr f3, f1
; PWR9BE-NEXT: fmr f1, f9 ; PWR9BE-NEXT: fmr f1, f9
; PWR9BE-NEXT: fmr f2, f10 ; PWR9BE-NEXT: fmr f2, f10
▲ Show 20 Lines • Show All 127 Lines • ▼ Show 20 Lines
; PWR9LE: # %bb.0: # %entry ; PWR9LE: # %bb.0: # %entry
; PWR9LE-NEXT: mflr r0 ; PWR9LE-NEXT: mflr r0
; PWR9LE-NEXT: stfd f26, -48(r1) # 8-byte Folded Spill ; PWR9LE-NEXT: stfd f26, -48(r1) # 8-byte Folded Spill
; PWR9LE-NEXT: stfd f27, -40(r1) # 8-byte Folded Spill ; PWR9LE-NEXT: stfd f27, -40(r1) # 8-byte Folded Spill
; PWR9LE-NEXT: stfd f28, -32(r1) # 8-byte Folded Spill ; PWR9LE-NEXT: stfd f28, -32(r1) # 8-byte Folded Spill
; PWR9LE-NEXT: stfd f29, -24(r1) # 8-byte Folded Spill ; PWR9LE-NEXT: stfd f29, -24(r1) # 8-byte Folded Spill
; PWR9LE-NEXT: stfd f30, -16(r1) # 8-byte Folded Spill ; PWR9LE-NEXT: stfd f30, -16(r1) # 8-byte Folded Spill
; PWR9LE-NEXT: stfd f31, -8(r1) # 8-byte Folded Spill ; PWR9LE-NEXT: stfd f31, -8(r1) # 8-byte Folded Spill
; PWR9LE-NEXT: std r0, 16(r1)
; PWR9LE-NEXT: stdu r1, -96(r1) ; PWR9LE-NEXT: stdu r1, -96(r1)
; PWR9LE-NEXT: fmr f29, f4 ; PWR9LE-NEXT: fmr f29, f4
; PWR9LE-NEXT: fmr f28, f3 ; PWR9LE-NEXT: fmr f28, f3
; PWR9LE-NEXT: fmr f3, f5 ; PWR9LE-NEXT: fmr f3, f5
; PWR9LE-NEXT: fmr f4, f6 ; PWR9LE-NEXT: fmr f4, f6
; PWR9LE-NEXT: std r0, 112(r1)
; PWR9LE-NEXT: fmr f31, f8 ; PWR9LE-NEXT: fmr f31, f8
; PWR9LE-NEXT: fmr f30, f7 ; PWR9LE-NEXT: fmr f30, f7
; PWR9LE-NEXT: bl __gcc_qadd ; PWR9LE-NEXT: bl __gcc_qadd
; PWR9LE-NEXT: nop ; PWR9LE-NEXT: nop
; PWR9LE-NEXT: fmr f27, f1 ; PWR9LE-NEXT: fmr f27, f1
; PWR9LE-NEXT: fmr f26, f2 ; PWR9LE-NEXT: fmr f26, f2
; PWR9LE-NEXT: fmr f1, f28 ; PWR9LE-NEXT: fmr f1, f28
; PWR9LE-NEXT: fmr f2, f29 ; PWR9LE-NEXT: fmr f2, f29
Show All 22 Lines
; PWR9LE-NEXT: lfd f28, -32(r1) # 8-byte Folded Reload ; PWR9LE-NEXT: lfd f28, -32(r1) # 8-byte Folded Reload
; PWR9LE-NEXT: lfd f27, -40(r1) # 8-byte Folded Reload ; PWR9LE-NEXT: lfd f27, -40(r1) # 8-byte Folded Reload
; PWR9LE-NEXT: lfd f26, -48(r1) # 8-byte Folded Reload ; PWR9LE-NEXT: lfd f26, -48(r1) # 8-byte Folded Reload
; PWR9LE-NEXT: blr ; PWR9LE-NEXT: blr
; ;
; PWR9BE-LABEL: v4ppcf128_fast: ; PWR9BE-LABEL: v4ppcf128_fast:
; PWR9BE: # %bb.0: # %entry ; PWR9BE: # %bb.0: # %entry
; PWR9BE-NEXT: mflr r0 ; PWR9BE-NEXT: mflr r0
; PWR9BE-NEXT: std r0, 16(r1)
; PWR9BE-NEXT: stdu r1, -176(r1) ; PWR9BE-NEXT: stdu r1, -176(r1)
; PWR9BE-NEXT: std r0, 192(r1)
; PWR9BE-NEXT: stfd f28, 144(r1) # 8-byte Folded Spill ; PWR9BE-NEXT: stfd f28, 144(r1) # 8-byte Folded Spill
; PWR9BE-NEXT: stfd f29, 152(r1) # 8-byte Folded Spill ; PWR9BE-NEXT: stfd f29, 152(r1) # 8-byte Folded Spill
; PWR9BE-NEXT: fmr f29, f4 ; PWR9BE-NEXT: fmr f29, f4
; PWR9BE-NEXT: fmr f28, f3 ; PWR9BE-NEXT: fmr f28, f3
; PWR9BE-NEXT: fmr f3, f5 ; PWR9BE-NEXT: fmr f3, f5
; PWR9BE-NEXT: fmr f4, f6 ; PWR9BE-NEXT: fmr f4, f6
; PWR9BE-NEXT: stfd f26, 128(r1) # 8-byte Folded Spill ; PWR9BE-NEXT: stfd f26, 128(r1) # 8-byte Folded Spill
; PWR9BE-NEXT: stfd f27, 136(r1) # 8-byte Folded Spill ; PWR9BE-NEXT: stfd f27, 136(r1) # 8-byte Folded Spill
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llvm/test/DebugInfo/XCOFF/explicit-section.ll

Show First 20 Lines • Show All 88 Lines • ▼ Show 20 Lines
; CHECK-NEXT: .vbyte 4, TOC[TC0] ; CHECK-NEXT: .vbyte 4, TOC[TC0]
; CHECK-NEXT: .vbyte 4, 0 ; CHECK-NEXT: .vbyte 4, 0
; CHECK-NEXT: .csect explicit_main_sec[PR],5 ; CHECK-NEXT: .csect explicit_main_sec[PR],5
; CHECK-NEXT: .main: ; CHECK-NEXT: .main:
; CHECK-NEXT: L..func_begin1: ; CHECK-NEXT: L..func_begin1:
; CHECK-NEXT: # %bb.0: # %entry ; CHECK-NEXT: # %bb.0: # %entry
; CHECK-NEXT: L..tmp3: ; CHECK-NEXT: L..tmp3:
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; CHECK-NEXT: stw 0, 8(1)
; CHECK-NEXT: stwu 1, -64(1) ; CHECK-NEXT: stwu 1, -64(1)
; CHECK-NEXT: li 3, 0 ; CHECK-NEXT: li 3, 0
; CHECK-NEXT: stw 0, 72(1)
; CHECK-NEXT: stw 3, 60(1) ; CHECK-NEXT: stw 3, 60(1)
; CHECK-NEXT: L..tmp4: ; CHECK-NEXT: L..tmp4:
; CHECK-NEXT: L..tmp5: ; CHECK-NEXT: L..tmp5:
; CHECK-NEXT: bl .bar ; CHECK-NEXT: bl .bar
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: L..tmp6: ; CHECK-NEXT: L..tmp6:
; CHECK-NEXT: addi 1, 1, 64 ; CHECK-NEXT: addi 1, 1, 64
; CHECK-NEXT: lwz 0, 8(1) ; CHECK-NEXT: lwz 0, 8(1)
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