[PowerPC] add a new subtarget feature FastMFLR

[shchenz]

Summary

This is to address code review comments in https://reviews.llvm.org/D137423#3912332

Add a new subtarget feature FastMFLR, so that we don't reply on ISA version to check a processor level feature.

This caller of this new feature is in D137423 and the tests are also there.

[RolandF]

llvm/lib/Target/PowerPC/PPC.td

320

I would suggest fast-MFLR rather than cheap-MFLR, and for the description I would suggest "MFLR is a fast instruction"

llvm/lib/Target/PowerPC/PPCSubtarget.h

443

As this function has only a return, it can be a one line function and be put with the other one line functions.

[shchenz]

address comments

[RolandF]

LGTM

llvm/lib/Target/PowerPC/PPC.td

SubtargetFeature<"privileged", "HasPrivileged", "true",
                    "Add privileged instructions">;
 
 def FeaturePredictableSelectIsExpensive :
   SubtargetFeature<"predictable-select-expensive",
                    "PredictableSelectIsExpensive",
                    "true",
                    "Prefer likely predicted branches over selects">;
 
+def FeatureFastMFLR : SubtargetFeature<"fast-MFLR", "HasFastMFLR", "true",
+                                       "MFLR is a fast instruction">;
+
 // Since new processors generally contain a superset of features of those that
 // came before them, the idea is to make implementations of new processors
 // less error prone and easier to read.
 // Namely:
 //     list<SubtargetFeature> P8InheritableFeatures = ...
 //     list<SubtargetFeature> FutureProcessorAddtionalFeatures =
 //         [ features that Power8 does not support but inheritable ]
 //     list<SubtargetFeature> FutureProcessorSpecificFeatures =
def ProcessorFeatures {
   list<SubtargetFeature> FusionFeatures = [
     FeatureStoreFusion, FeatureAddLogicalFusion, FeatureLogicalAddFusion,
     FeatureLogicalFusion, FeatureArithAddFusion, FeatureSha3Fusion,
   ];
   list<SubtargetFeature> P10AdditionalFeatures =
     !listconcat(FusionFeatures, [
        DirectivePwr10, FeatureISA3_1, FeaturePrefixInstrs,
        FeaturePCRelativeMemops, FeatureP10Vector, FeatureMMA,
-       FeaturePairedVectorMemops]);
+       FeaturePairedVectorMemops, FeatureFastMFLR]);
   list<SubtargetFeature> P10SpecificFeatures = [];
   list<SubtargetFeature> P10InheritableFeatures =
     !listconcat(P9InheritableFeatures, P10AdditionalFeatures);
   list<SubtargetFeature> P10Features =
     !listconcat(P10InheritableFeatures, P10SpecificFeatures);
 
   // Future
   // For future CPU we assume that all of the existing features from Power10

llvm/lib/Target/PowerPC/PPCSubtarget.h

protected:
   bool IsISAFuture;
   bool UseLongCalls;
   bool SecurePlt;
   bool VectorsUseTwoUnits;
   bool UsePPCPreRASchedStrategy;
   bool UsePPCPostRASchedStrategy;
   bool PairedVectorMemops;
   bool PredictableSelectIsExpensive;
+  bool HasFastMFLR;
   bool HasModernAIXAs;
   bool IsAIX;
 
   POPCNTDKind HasPOPCNTD;
 
   const PPCTargetMachine &TM;
   PPCFrameLowering FrameLowering;
   PPCInstrInfo InstrInfo;
public:
   bool hasInvariantFunctionDescriptors() const {
     return HasInvariantFunctionDescriptors;
   }
   bool usePPCPreRASchedStrategy() const { return UsePPCPreRASchedStrategy; }
   bool usePPCPostRASchedStrategy() const { return UsePPCPostRASchedStrategy; }
   bool hasPartwordAtomics() const { return HasPartwordAtomics; }
   bool hasQuadwordAtomics() const { return HasQuadwordAtomics; }
   bool hasDirectMove() const { return HasDirectMove; }
+  bool hasFastMFLR() const { return HasFastMFLR; }
 
   Align getPlatformStackAlignment() const {
     return Align(16);
   }
 
   unsigned  getRedZoneSize() const {
     if (isPPC64())
       // 288 bytes = 18*8 (FPRs) + 18*8 (GPRs, GPR13 reserved)
public:
 
   bool isXRaySupported() const override { return IsPPC64 && IsLittleEndian; }
 
   bool isPredictableSelectIsExpensive() const {
     return PredictableSelectIsExpensive;
   }
 
   // Select allocation orders of GPRC and G8RC. It should be strictly consistent
   // with corresponding AltOrders in PPCRegisterInfo.td.
   unsigned getGPRAllocationOrderIdx() const {
     if (is64BitELFABI())
       return 1;
     if (isAIXABI())
       return 2;
     return 0;
   }
 

llvm/lib/Target/PowerPC/PPCSubtarget.cpp

void PPCSubtarget::initializeEnvironment() {
   IsISAFuture = false;
   UseLongCalls = false;
   SecurePlt = false;
   VectorsUseTwoUnits = false;
   UsePPCPreRASchedStrategy = false;
   UsePPCPostRASchedStrategy = false;
   PairedVectorMemops = false;
   PredictableSelectIsExpensive = false;
+  HasFastMFLR = false;
   HasModernAIXAs = false;
   IsAIX = false;
 
   HasPOPCNTD = POPCNTD_Unavailable;
 }
 
 void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
   // Determine default and user specified characteristics