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Differential D137332

[AMDGPU][MC][GFX10+] Enable literal operands with permlane16/permlanex16
ClosedPublic

Authored by dp on Nov 3 2022, 5:10 AM.

Details

Reviewers
rampitec
foad
Joe_Nash
Commits
rG6e279f5bb663: [AMDGPU][MC][GFX10+] Enable literal operands with permlane16/permlanex16
Summary

See this bug for more information.

Diff Detail

Event Timeline

dp created this revision.Nov 3 2022, 5:10 AM
Herald added a project: Restricted Project. · View Herald TranscriptNov 3 2022, 5:10 AM
Herald added subscribers: kosarev, kerbowa, hiraditya and 6 others. · View Herald Transcript
dp requested review of this revision.Nov 3 2022, 5:10 AM
Herald added a project: Restricted Project. · View Herald TranscriptNov 3 2022, 5:10 AM
Herald added subscribers: llvm-commits, wdng. · View Herald Transcript
Harbormaster completed remote builds in B195911: Diff 472902.Nov 3 2022, 6:17 AM
foad added a comment.Nov 3 2022, 7:16 AM

LGTM. Maybe add a test for using the same literal twice (is that allowed?) like v_permlane16_b32 v5, v1, 0x12345678, 0x12345678.

dp added a comment.Nov 3 2022, 7:42 AM
In D137332#3905209, @foad wrote:

LGTM. Maybe add a test for using the same literal twice (is that allowed?)

Yes, it should be allowed.

dp updated this revision to Diff 472936.Nov 3 2022, 7:43 AM

Add tests with two literals.

Joe_Nash accepted this revision.Nov 3 2022, 7:50 AM

LGTM

This revision is now accepted and ready to land.Nov 3 2022, 7:50 AM
Harbormaster completed remote builds in B195933: Diff 472936.Nov 3 2022, 8:42 AM
Closed by commit rG6e279f5bb663: [AMDGPU][MC][GFX10+] Enable literal operands with permlane16/permlanex16 (authored by dp). · Explain WhyNov 7 2022, 4:49 AM
This revision was automatically updated to reflect the committed changes.
dp added a commit: rG6e279f5bb663: [AMDGPU][MC][GFX10+] Enable literal operands with permlane16/permlanex16.
dp mentioned this in rG37e6f8402621: [AMDGPU][GFX10][DOC][NFC] Update assembler syntax description.Dec 13 2022, 3:39 AM
dp mentioned this in rGc27eded938f7: [AMDGPU][GFX1030][DOC][NFC] Update assembler syntax description.Dec 13 2022, 3:51 AM

Revision Contents

PathSize
llvm/
lib/
Target/
AMDGPU/
7 lines
test/
CodeGen/
AMDGPU/
6 lines
MC/
AMDGPU/
12 lines
12 lines
Disassembler/
AMDGPU/
12 lines

Diff 472902

llvm/lib/Target/AMDGPU/VOP3Instructions.td

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} }
let SubtargetPredicate = isGFX9GFX10 in // exclude pre-GFX9 where it was slow let SubtargetPredicate = isGFX9GFX10 in // exclude pre-GFX9 where it was slow
defm : IMAD32_Pats<V_MAD_U64_U32_e64>; defm : IMAD32_Pats<V_MAD_U64_U32_e64>;
let SubtargetPredicate = isGFX11Only in let SubtargetPredicate = isGFX11Only in
defm : IMAD32_Pats<V_MAD_U64_U32_gfx11_e64>; defm : IMAD32_Pats<V_MAD_U64_U32_gfx11_e64>;
def VOP3_PERMLANE_Profile : VOP3_Profile<VOPProfile <[i32, i32, i32, i32]>, VOP3_OPSEL> { def VOP3_PERMLANE_Profile : VOP3_Profile<VOPProfile <[i32, i32, i32, i32]>, VOP3_OPSEL> {
let Src0RC64 = VRegSrc_32;
let Src1RC64 = SCSrc_b32;
let Src2RC64 = SCSrc_b32;
let InsVOP3OpSel = (ins IntOpSelMods:$src0_modifiers, VRegSrc_32:$src0, let InsVOP3OpSel = (ins IntOpSelMods:$src0_modifiers, VRegSrc_32:$src0,
IntOpSelMods:$src1_modifiers, SCSrc_b32:$src1, IntOpSelMods:$src1_modifiers, SSrc_b32:$src1,
IntOpSelMods:$src2_modifiers, SCSrc_b32:$src2, IntOpSelMods:$src2_modifiers, SSrc_b32:$src2,
VGPR_32:$vdst_in, op_sel0:$op_sel); VGPR_32:$vdst_in, op_sel0:$op_sel);
let HasClamp = 0; let HasClamp = 0;
let HasExtVOP3DPP = 0; let HasExtVOP3DPP = 0;
let HasExtDPP = 0; let HasExtDPP = 0;
} }
class PermlanePat<SDPatternOperator permlane, class PermlanePat<SDPatternOperator permlane,
Instruction inst> : GCNPat< Instruction inst> : GCNPat<
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llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll

Show All 21 Linesdefine amdgpu_kernel void @v_permlane16_b32_vii(i32 addrspace(1)* %out, i32 %src0) #1 {
%v = call i32 @llvm.amdgcn.permlane16(i32 %src0, i32 %src0, i32 1, i32 2, i1 0, i1 0) %v = call i32 @llvm.amdgcn.permlane16(i32 %src0, i32 %src0, i32 1, i32 2, i1 0, i1 0)
store i32 %v, i32 addrspace(1)* %out store i32 %v, i32 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}v_permlane16_b32_vll: ; GCN-LABEL: {{^}}v_permlane16_b32_vll:
; FIXME-GFX10PLUS: It is allowed to have both immediates as literals ; FIXME-GFX10PLUS: It is allowed to have both immediates as literals
; GFX10PLUS-DAG: s_movk_i32 [[SRC1:s[0-9]+]], 0x1234 ; GFX10PLUS-DAG: s_movk_i32 [[SRC1:s[0-9]+]], 0x1234
; GFX10PLUS-DAG: s_mov_b32 [[SRC2:s[0-9]+]], 0xc1d1
; GFX10PLUS-NOT: v_readfirstlane_b32 ; GFX10PLUS-NOT: v_readfirstlane_b32
; GFX10PLUS: v_permlane16_b32 v{{[0-9]+}}, v{{[0-9]+}}, [[SRC1]], [[SRC2]]{{$}} ; GFX10PLUS: v_permlane16_b32 v{{[0-9]+}}, v{{[0-9]+}}, [[SRC1]], 0xc1d1{{$}}
define amdgpu_kernel void @v_permlane16_b32_vll(i32 addrspace(1)* %out, i32 %src0) #1 { define amdgpu_kernel void @v_permlane16_b32_vll(i32 addrspace(1)* %out, i32 %src0) #1 {
%v = call i32 @llvm.amdgcn.permlane16(i32 %src0, i32 %src0, i32 4660, i32 49617, i1 0, i1 0) %v = call i32 @llvm.amdgcn.permlane16(i32 %src0, i32 %src0, i32 4660, i32 49617, i1 0, i1 0)
store i32 %v, i32 addrspace(1)* %out store i32 %v, i32 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}v_permlane16_b32_vvv: ; GCN-LABEL: {{^}}v_permlane16_b32_vvv:
; GFX10-DAG: v_readfirstlane_b32 [[SRC1:s[0-9]+]], v0 ; GFX10-DAG: v_readfirstlane_b32 [[SRC1:s[0-9]+]], v0
▲ Show 20 Lines • Show All 78 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @v_permlanex16_b32_vii(i32 addrspace(1)* %out, i32 %src0) #1 {
%v = call i32 @llvm.amdgcn.permlanex16(i32 %src0, i32 %src0, i32 1, i32 2, i1 0, i1 0) %v = call i32 @llvm.amdgcn.permlanex16(i32 %src0, i32 %src0, i32 1, i32 2, i1 0, i1 0)
store i32 %v, i32 addrspace(1)* %out store i32 %v, i32 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}v_permlanex16_b32_vll: ; GCN-LABEL: {{^}}v_permlanex16_b32_vll:
; FIXME-GFX10PLUS: It is allowed to have both immediates as literals ; FIXME-GFX10PLUS: It is allowed to have both immediates as literals
; GFX10PLUS-DAG: s_movk_i32 [[SRC1:s[0-9]+]], 0x1234 ; GFX10PLUS-DAG: s_movk_i32 [[SRC1:s[0-9]+]], 0x1234
; GFX10PLUS-DAG: s_mov_b32 [[SRC2:s[0-9]+]], 0xc1d1
; GFX10PLUS-NOT: v_readfirstlane_b32 ; GFX10PLUS-NOT: v_readfirstlane_b32
; GFX10PLUS: v_permlanex16_b32 v{{[0-9]+}}, v{{[0-9]+}}, [[SRC1]], [[SRC2]]{{$}} ; GFX10PLUS: v_permlanex16_b32 v{{[0-9]+}}, v{{[0-9]+}}, [[SRC1]], 0xc1d1{{$}}
define amdgpu_kernel void @v_permlanex16_b32_vll(i32 addrspace(1)* %out, i32 %src0) #1 { define amdgpu_kernel void @v_permlanex16_b32_vll(i32 addrspace(1)* %out, i32 %src0) #1 {
%v = call i32 @llvm.amdgcn.permlanex16(i32 %src0, i32 %src0, i32 4660, i32 49617, i1 0, i1 0) %v = call i32 @llvm.amdgcn.permlanex16(i32 %src0, i32 %src0, i32 4660, i32 49617, i1 0, i1 0)
store i32 %v, i32 addrspace(1)* %out store i32 %v, i32 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}v_permlanex16_b32_vvv: ; GCN-LABEL: {{^}}v_permlanex16_b32_vvv:
; GFX10-DAG: v_readfirstlane_b32 [[SRC1:s[0-9]+]], v0 ; GFX10-DAG: v_readfirstlane_b32 [[SRC1:s[0-9]+]], v0
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llvm/test/MC/AMDGPU/gfx10_asm_vop3.s

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
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// GFX10: encoding: [0x05,0x00,0x77,0xd7,0x01,0x83,0x0d,0x00] // GFX10: encoding: [0x05,0x00,0x77,0xd7,0x01,0x83,0x0d,0x00]
v_permlane16_b32 v5, v1, 0.5, s3 v_permlane16_b32 v5, v1, 0.5, s3
// GFX10: encoding: [0x05,0x00,0x77,0xd7,0x01,0xe1,0x0d,0x00] // GFX10: encoding: [0x05,0x00,0x77,0xd7,0x01,0xe1,0x0d,0x00]
v_permlane16_b32 v5, v1, -4.0, s3 v_permlane16_b32 v5, v1, -4.0, s3
// GFX10: encoding: [0x05,0x00,0x77,0xd7,0x01,0xef,0x0d,0x00] // GFX10: encoding: [0x05,0x00,0x77,0xd7,0x01,0xef,0x0d,0x00]
v_permlane16_b32 v5, v1, 0xaf123456, s3
// GFX10: encoding: [0x05,0x00,0x77,0xd7,0x01,0xff,0x0d,0x00,0x56,0x34,0x12,0xaf]
v_permlane16_b32 v5, v1, s2, s103 v_permlane16_b32 v5, v1, s2, s103
// GFX10: encoding: [0x05,0x00,0x77,0xd7,0x01,0x05,0x9c,0x01] // GFX10: encoding: [0x05,0x00,0x77,0xd7,0x01,0x05,0x9c,0x01]
v_permlane16_b32 v5, v1, s2, vcc_lo v_permlane16_b32 v5, v1, s2, vcc_lo
// GFX10: encoding: [0x05,0x00,0x77,0xd7,0x01,0x05,0xa8,0x01] // GFX10: encoding: [0x05,0x00,0x77,0xd7,0x01,0x05,0xa8,0x01]
v_permlane16_b32 v5, v1, s2, vcc_hi v_permlane16_b32 v5, v1, s2, vcc_hi
// GFX10: encoding: [0x05,0x00,0x77,0xd7,0x01,0x05,0xac,0x01] // GFX10: encoding: [0x05,0x00,0x77,0xd7,0x01,0x05,0xac,0x01]
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// GFX10: encoding: [0x05,0x00,0x77,0xd7,0x01,0x05,0x04,0x03] // GFX10: encoding: [0x05,0x00,0x77,0xd7,0x01,0x05,0x04,0x03]
v_permlane16_b32 v5, v1, s2, 0.5 v_permlane16_b32 v5, v1, s2, 0.5
// GFX10: encoding: [0x05,0x00,0x77,0xd7,0x01,0x05,0xc0,0x03] // GFX10: encoding: [0x05,0x00,0x77,0xd7,0x01,0x05,0xc0,0x03]
v_permlane16_b32 v5, v1, s2, -4.0 v_permlane16_b32 v5, v1, s2, -4.0
// GFX10: encoding: [0x05,0x00,0x77,0xd7,0x01,0x05,0xdc,0x03] // GFX10: encoding: [0x05,0x00,0x77,0xd7,0x01,0x05,0xdc,0x03]
v_permlane16_b32 v5, v1, s2, 0xaf123456
// GFX10: encoding: [0x05,0x00,0x77,0xd7,0x01,0x05,0xfc,0x03,0x56,0x34,0x12,0xaf]
v_permlane16_b32 v5, v1, s2, s3 op_sel:[1,0] v_permlane16_b32 v5, v1, s2, s3 op_sel:[1,0]
// GFX10: encoding: [0x05,0x08,0x77,0xd7,0x01,0x05,0x0c,0x00] // GFX10: encoding: [0x05,0x08,0x77,0xd7,0x01,0x05,0x0c,0x00]
v_permlane16_b32 v5, v1, s2, s3 op_sel:[1,1] v_permlane16_b32 v5, v1, s2, s3 op_sel:[1,1]
// GFX10: encoding: [0x05,0x18,0x77,0xd7,0x01,0x05,0x0c,0x00] // GFX10: encoding: [0x05,0x18,0x77,0xd7,0x01,0x05,0x0c,0x00]
v_permlane16_b32 v5, v1, s2, s3 op_sel:[0,1] v_permlane16_b32 v5, v1, s2, s3 op_sel:[0,1]
// GFX10: encoding: [0x05,0x10,0x77,0xd7,0x01,0x05,0x0c,0x00] // GFX10: encoding: [0x05,0x10,0x77,0xd7,0x01,0x05,0x0c,0x00]
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// GFX10: encoding: [0x05,0x00,0x78,0xd7,0x01,0x83,0x0d,0x00] // GFX10: encoding: [0x05,0x00,0x78,0xd7,0x01,0x83,0x0d,0x00]
v_permlanex16_b32 v5, v1, 0.5, s3 v_permlanex16_b32 v5, v1, 0.5, s3
// GFX10: encoding: [0x05,0x00,0x78,0xd7,0x01,0xe1,0x0d,0x00] // GFX10: encoding: [0x05,0x00,0x78,0xd7,0x01,0xe1,0x0d,0x00]
v_permlanex16_b32 v5, v1, -4.0, s3 v_permlanex16_b32 v5, v1, -4.0, s3
// GFX10: encoding: [0x05,0x00,0x78,0xd7,0x01,0xef,0x0d,0x00] // GFX10: encoding: [0x05,0x00,0x78,0xd7,0x01,0xef,0x0d,0x00]
v_permlanex16_b32 v5, v1, 0xaf123456, s3
// GFX10: encoding: [0x05,0x00,0x78,0xd7,0x01,0xff,0x0d,0x00,0x56,0x34,0x12,0xaf]
v_permlanex16_b32 v5, v1, s2, s103 v_permlanex16_b32 v5, v1, s2, s103
// GFX10: encoding: [0x05,0x00,0x78,0xd7,0x01,0x05,0x9c,0x01] // GFX10: encoding: [0x05,0x00,0x78,0xd7,0x01,0x05,0x9c,0x01]
v_permlanex16_b32 v5, v1, s2, vcc_lo v_permlanex16_b32 v5, v1, s2, vcc_lo
// GFX10: encoding: [0x05,0x00,0x78,0xd7,0x01,0x05,0xa8,0x01] // GFX10: encoding: [0x05,0x00,0x78,0xd7,0x01,0x05,0xa8,0x01]
v_permlanex16_b32 v5, v1, s2, vcc_hi v_permlanex16_b32 v5, v1, s2, vcc_hi
// GFX10: encoding: [0x05,0x00,0x78,0xd7,0x01,0x05,0xac,0x01] // GFX10: encoding: [0x05,0x00,0x78,0xd7,0x01,0x05,0xac,0x01]
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// GFX10: encoding: [0x05,0x00,0x78,0xd7,0x01,0x05,0x04,0x03] // GFX10: encoding: [0x05,0x00,0x78,0xd7,0x01,0x05,0x04,0x03]
v_permlanex16_b32 v5, v1, s2, 0.5 v_permlanex16_b32 v5, v1, s2, 0.5
// GFX10: encoding: [0x05,0x00,0x78,0xd7,0x01,0x05,0xc0,0x03] // GFX10: encoding: [0x05,0x00,0x78,0xd7,0x01,0x05,0xc0,0x03]
v_permlanex16_b32 v5, v1, s2, -4.0 v_permlanex16_b32 v5, v1, s2, -4.0
// GFX10: encoding: [0x05,0x00,0x78,0xd7,0x01,0x05,0xdc,0x03] // GFX10: encoding: [0x05,0x00,0x78,0xd7,0x01,0x05,0xdc,0x03]
v_permlanex16_b32 v5, v1, s2, 0xaf123456
// GFX10: encoding: [0x05,0x00,0x78,0xd7,0x01,0x05,0xfc,0x03,0x56,0x34,0x12,0xaf]
v_permlanex16_b32 v5, v1, s2, s3 op_sel:[1,0] v_permlanex16_b32 v5, v1, s2, s3 op_sel:[1,0]
// GFX10: encoding: [0x05,0x08,0x78,0xd7,0x01,0x05,0x0c,0x00] // GFX10: encoding: [0x05,0x08,0x78,0xd7,0x01,0x05,0x0c,0x00]
v_permlanex16_b32 v5, v1, s2, s3 op_sel:[1,1] v_permlanex16_b32 v5, v1, s2, s3 op_sel:[1,1]
// GFX10: encoding: [0x05,0x18,0x78,0xd7,0x01,0x05,0x0c,0x00] // GFX10: encoding: [0x05,0x18,0x78,0xd7,0x01,0x05,0x0c,0x00]
v_permlanex16_b32 v5, v1, s2, s3 op_sel:[0,1] v_permlanex16_b32 v5, v1, s2, s3 op_sel:[0,1]
// GFX10: encoding: [0x05,0x10,0x78,0xd7,0x01,0x05,0x0c,0x00] // GFX10: encoding: [0x05,0x10,0x78,0xd7,0x01,0x05,0x0c,0x00]
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llvm/test/MC/AMDGPU/gfx11_asm_vop3.s

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// GFX11: encoding: [0x05,0x00,0x5b,0xd6,0x01,0x83,0x05,0x03] // GFX11: encoding: [0x05,0x00,0x5b,0xd6,0x01,0x83,0x05,0x03]
v_permlane16_b32 v5, v1, 0.5, null op_sel:[1,0] v_permlane16_b32 v5, v1, 0.5, null op_sel:[1,0]
// GFX11: encoding: [0x05,0x08,0x5b,0xd6,0x01,0xe1,0xf1,0x01] // GFX11: encoding: [0x05,0x08,0x5b,0xd6,0x01,0xe1,0xf1,0x01]
v_permlane16_b32 v255, v255, src_scc, exec_hi op_sel:[0,1] v_permlane16_b32 v255, v255, src_scc, exec_hi op_sel:[0,1]
// GFX11: encoding: [0xff,0x10,0x5b,0xd6,0xff,0xfb,0xfd,0x01] // GFX11: encoding: [0xff,0x10,0x5b,0xd6,0xff,0xfb,0xfd,0x01]
v_permlane16_b32 v5, v1, 0xaf123456, s3
// GFX11: encoding: [0x05,0x00,0x5b,0xd6,0x01,0xff,0x0d,0x00,0x56,0x34,0x12,0xaf]
v_permlane16_b32 v5, v1, s2, 0xaf123456
// GFX11: encoding: [0x05,0x00,0x5b,0xd6,0x01,0x05,0xfc,0x03,0x56,0x34,0x12,0xaf]
v_permlanex16_b32 v5, v1, s2, s3 v_permlanex16_b32 v5, v1, s2, s3
// GFX11: encoding: [0x05,0x00,0x5c,0xd6,0x01,0x05,0x0c,0x00] // GFX11: encoding: [0x05,0x00,0x5c,0xd6,0x01,0x05,0x0c,0x00]
v_permlanex16_b32 v5, v1, s105, s105 v_permlanex16_b32 v5, v1, s105, s105
// GFX11: encoding: [0x05,0x00,0x5c,0xd6,0x01,0xd3,0xa4,0x01] // GFX11: encoding: [0x05,0x00,0x5c,0xd6,0x01,0xd3,0xa4,0x01]
v_permlanex16_b32 v5, v1, ttmp15, ttmp15 v_permlanex16_b32 v5, v1, ttmp15, ttmp15
// GFX11: encoding: [0x05,0x00,0x5c,0xd6,0x01,0xf7,0xec,0x01] // GFX11: encoding: [0x05,0x00,0x5c,0xd6,0x01,0xf7,0xec,0x01]
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// GFX11: encoding: [0x05,0x00,0x5c,0xd6,0x01,0x83,0x05,0x03] // GFX11: encoding: [0x05,0x00,0x5c,0xd6,0x01,0x83,0x05,0x03]
v_permlanex16_b32 v5, v1, 0.5, null op_sel:[1,0] v_permlanex16_b32 v5, v1, 0.5, null op_sel:[1,0]
// GFX11: encoding: [0x05,0x08,0x5c,0xd6,0x01,0xe1,0xf1,0x01] // GFX11: encoding: [0x05,0x08,0x5c,0xd6,0x01,0xe1,0xf1,0x01]
v_permlanex16_b32 v255, v255, src_scc, exec_hi op_sel:[0,1] v_permlanex16_b32 v255, v255, src_scc, exec_hi op_sel:[0,1]
// GFX11: encoding: [0xff,0x10,0x5c,0xd6,0xff,0xfb,0xfd,0x01] // GFX11: encoding: [0xff,0x10,0x5c,0xd6,0xff,0xfb,0xfd,0x01]
v_permlanex16_b32 v5, v1, 0xaf123456, s3
// GFX11: encoding: [0x05,0x00,0x5c,0xd6,0x01,0xff,0x0d,0x00,0x56,0x34,0x12,0xaf]
v_permlanex16_b32 v5, v1, s2, 0xaf123456
// GFX11: encoding: [0x05,0x00,0x5c,0xd6,0x01,0x05,0xfc,0x03,0x56,0x34,0x12,0xaf]
v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, ttmp[14:15] v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, ttmp[14:15]
// GFX11: encoding: [0x05,0x00,0x3a,0xd6,0x01,0x05,0xea,0x01] // GFX11: encoding: [0x05,0x00,0x3a,0xd6,0x01,0x05,0xea,0x01]
v_qsad_pk_u16_u8 v[5:6], v[1:2], v255, ttmp[14:15] v_qsad_pk_u16_u8 v[5:6], v[1:2], v255, ttmp[14:15]
// GFX11: encoding: [0x05,0x00,0x3a,0xd6,0x01,0xff,0xeb,0x01] // GFX11: encoding: [0x05,0x00,0x3a,0xd6,0x01,0xff,0xeb,0x01]
v_qsad_pk_u16_u8 v[5:6], v[1:2], s2, ttmp[14:15] v_qsad_pk_u16_u8 v[5:6], v[1:2], s2, ttmp[14:15]
// GFX11: encoding: [0x05,0x00,0x3a,0xd6,0x01,0x05,0xe8,0x01] // GFX11: encoding: [0x05,0x00,0x3a,0xd6,0x01,0x05,0xe8,0x01]
▲ Show 20 Lines • Show All 821 Lines • Show Last 20 Lines

llvm/test/MC/Disassembler/AMDGPU/gfx10_vop3.txt

Show First 20 Lines • Show All 16,038 Lines • ▼ Show 20 Lines
0x05,0x00,0x77,0xd7,0x01,0xf9,0x08,0x00 0x05,0x00,0x77,0xd7,0x01,0xf9,0x08,0x00
# GFX10: v_permlane16_b32 v5, v1, m0, s3 ; encoding: [0x05,0x00,0x77,0xd7,0x01,0xf9,0x0c,0x00] # GFX10: v_permlane16_b32 v5, v1, m0, s3 ; encoding: [0x05,0x00,0x77,0xd7,0x01,0xf9,0x0c,0x00]
0x05,0x00,0x77,0xd7,0x01,0xf9,0x0c,0x00 0x05,0x00,0x77,0xd7,0x01,0xf9,0x0c,0x00
# GFX10: v_permlane16_b32 v5, v1, s103, s3 ; encoding: [0x05,0x00,0x77,0xd7,0x01,0xcf,0x0c,0x00] # GFX10: v_permlane16_b32 v5, v1, s103, s3 ; encoding: [0x05,0x00,0x77,0xd7,0x01,0xcf,0x0c,0x00]
0x05,0x00,0x77,0xd7,0x01,0xcf,0x0c,0x00 0x05,0x00,0x77,0xd7,0x01,0xcf,0x0c,0x00
# GFX10: v_permlane16_b32 v5, v1, 0xaf123456, s3 ; encoding: [0x05,0x00,0x77,0xd7,0x01,0xff,0x0d,0x00,0x56,0x34,0x12,0xaf]
0x05,0x00,0x77,0xd7,0x01,0xff,0x0d,0x00,0x56,0x34,0x12,0xaf
# GFX10: v_permlane16_b32 v5, v1, s2, -1 ; encoding: [0x05,0x00,0x77,0xd7,0x01,0x05,0x04,0x03] # GFX10: v_permlane16_b32 v5, v1, s2, -1 ; encoding: [0x05,0x00,0x77,0xd7,0x01,0x05,0x04,0x03]
0x05,0x00,0x77,0xd7,0x01,0x05,0x04,0x03 0x05,0x00,0x77,0xd7,0x01,0x05,0x04,0x03
# GFX10: v_permlane16_b32 v5, v1, s2, -4.0 ; encoding: [0x05,0x00,0x77,0xd7,0x01,0x05,0xdc,0x03] # GFX10: v_permlane16_b32 v5, v1, s2, -4.0 ; encoding: [0x05,0x00,0x77,0xd7,0x01,0x05,0xdc,0x03]
0x05,0x00,0x77,0xd7,0x01,0x05,0xdc,0x03 0x05,0x00,0x77,0xd7,0x01,0x05,0xdc,0x03
# GFX10: v_permlane16_b32 v5, v1, s2, 0 ; encoding: [0x05,0x00,0x77,0xd7,0x01,0x05,0x00,0x02] # GFX10: v_permlane16_b32 v5, v1, s2, 0 ; encoding: [0x05,0x00,0x77,0xd7,0x01,0x05,0x00,0x02]
0x05,0x00,0x77,0xd7,0x01,0x05,0x00,0x02 0x05,0x00,0x77,0xd7,0x01,0x05,0x00,0x02
Show All 11 Lines
0x05,0x00,0x77,0xd7,0x01,0x05,0xf0,0x01 0x05,0x00,0x77,0xd7,0x01,0x05,0xf0,0x01
# GFX10: v_permlane16_b32 v5, v1, s2, s103 ; encoding: [0x05,0x00,0x77,0xd7,0x01,0x05,0x9c,0x01] # GFX10: v_permlane16_b32 v5, v1, s2, s103 ; encoding: [0x05,0x00,0x77,0xd7,0x01,0x05,0x9c,0x01]
0x05,0x00,0x77,0xd7,0x01,0x05,0x9c,0x01 0x05,0x00,0x77,0xd7,0x01,0x05,0x9c,0x01
# GFX10: v_permlane16_b32 v5, v1, s2, s3 ; encoding: [0x05,0x00,0x77,0xd7,0x01,0x05,0x0c,0x00] # GFX10: v_permlane16_b32 v5, v1, s2, s3 ; encoding: [0x05,0x00,0x77,0xd7,0x01,0x05,0x0c,0x00]
0x05,0x00,0x77,0xd7,0x01,0x05,0x0c,0x00 0x05,0x00,0x77,0xd7,0x01,0x05,0x0c,0x00
# GFX10: v_permlane16_b32 v5, v1, s2, 0xaf123456 ; encoding: [0x05,0x00,0x77,0xd7,0x01,0x05,0xfc,0x03,0x56,0x34,0x12,0xaf]
0x05,0x00,0x77,0xd7,0x01,0x05,0xfc,0x03,0x56,0x34,0x12,0xaf
# GFX10: v_permlane16_b32 v5, v1, s2, s3 op_sel:[0,1] ; encoding: [0x05,0x10,0x77,0xd7,0x01,0x05,0x0c,0x00] # GFX10: v_permlane16_b32 v5, v1, s2, s3 op_sel:[0,1] ; encoding: [0x05,0x10,0x77,0xd7,0x01,0x05,0x0c,0x00]
0x05,0x10,0x77,0xd7,0x01,0x05,0x0c,0x00 0x05,0x10,0x77,0xd7,0x01,0x05,0x0c,0x00
# GFX10: v_permlane16_b32 v5, v1, s2, s3 op_sel:[1,0] ; encoding: [0x05,0x08,0x77,0xd7,0x01,0x05,0x0c,0x00] # GFX10: v_permlane16_b32 v5, v1, s2, s3 op_sel:[1,0] ; encoding: [0x05,0x08,0x77,0xd7,0x01,0x05,0x0c,0x00]
0x05,0x08,0x77,0xd7,0x01,0x05,0x0c,0x00 0x05,0x08,0x77,0xd7,0x01,0x05,0x0c,0x00
# GFX10: v_permlane16_b32 v5, v1, s2, s3 op_sel:[1,1] ; encoding: [0x05,0x18,0x77,0xd7,0x01,0x05,0x0c,0x00] # GFX10: v_permlane16_b32 v5, v1, s2, s3 op_sel:[1,1] ; encoding: [0x05,0x18,0x77,0xd7,0x01,0x05,0x0c,0x00]
0x05,0x18,0x77,0xd7,0x01,0x05,0x0c,0x00 0x05,0x18,0x77,0xd7,0x01,0x05,0x0c,0x00
▲ Show 20 Lines • Show All 62 Lines • ▼ Show 20 Lines
0x05,0x00,0x78,0xd7,0x01,0xf9,0x08,0x00 0x05,0x00,0x78,0xd7,0x01,0xf9,0x08,0x00
# GFX10: v_permlanex16_b32 v5, v1, m0, s3 ; encoding: [0x05,0x00,0x78,0xd7,0x01,0xf9,0x0c,0x00] # GFX10: v_permlanex16_b32 v5, v1, m0, s3 ; encoding: [0x05,0x00,0x78,0xd7,0x01,0xf9,0x0c,0x00]
0x05,0x00,0x78,0xd7,0x01,0xf9,0x0c,0x00 0x05,0x00,0x78,0xd7,0x01,0xf9,0x0c,0x00
# GFX10: v_permlanex16_b32 v5, v1, s103, s3 ; encoding: [0x05,0x00,0x78,0xd7,0x01,0xcf,0x0c,0x00] # GFX10: v_permlanex16_b32 v5, v1, s103, s3 ; encoding: [0x05,0x00,0x78,0xd7,0x01,0xcf,0x0c,0x00]
0x05,0x00,0x78,0xd7,0x01,0xcf,0x0c,0x00 0x05,0x00,0x78,0xd7,0x01,0xcf,0x0c,0x00
# GFX10: v_permlanex16_b32 v5, v1, 0xaf123456, s3 ; encoding: [0x05,0x00,0x78,0xd7,0x01,0xff,0x0d,0x00,0x56,0x34,0x12,0xaf]
0x05,0x00,0x78,0xd7,0x01,0xff,0x0d,0x00,0x56,0x34,0x12,0xaf
# GFX10: v_permlanex16_b32 v5, v1, s2, -1 ; encoding: [0x05,0x00,0x78,0xd7,0x01,0x05,0x04,0x03] # GFX10: v_permlanex16_b32 v5, v1, s2, -1 ; encoding: [0x05,0x00,0x78,0xd7,0x01,0x05,0x04,0x03]
0x05,0x00,0x78,0xd7,0x01,0x05,0x04,0x03 0x05,0x00,0x78,0xd7,0x01,0x05,0x04,0x03
# GFX10: v_permlanex16_b32 v5, v1, s2, -4.0 ; encoding: [0x05,0x00,0x78,0xd7,0x01,0x05,0xdc,0x03] # GFX10: v_permlanex16_b32 v5, v1, s2, -4.0 ; encoding: [0x05,0x00,0x78,0xd7,0x01,0x05,0xdc,0x03]
0x05,0x00,0x78,0xd7,0x01,0x05,0xdc,0x03 0x05,0x00,0x78,0xd7,0x01,0x05,0xdc,0x03
# GFX10: v_permlanex16_b32 v5, v1, s2, 0 ; encoding: [0x05,0x00,0x78,0xd7,0x01,0x05,0x00,0x02] # GFX10: v_permlanex16_b32 v5, v1, s2, 0 ; encoding: [0x05,0x00,0x78,0xd7,0x01,0x05,0x00,0x02]
0x05,0x00,0x78,0xd7,0x01,0x05,0x00,0x02 0x05,0x00,0x78,0xd7,0x01,0x05,0x00,0x02
Show All 11 Lines
0x05,0x00,0x78,0xd7,0x01,0x05,0xf0,0x01 0x05,0x00,0x78,0xd7,0x01,0x05,0xf0,0x01
# GFX10: v_permlanex16_b32 v5, v1, s2, s103 ; encoding: [0x05,0x00,0x78,0xd7,0x01,0x05,0x9c,0x01] # GFX10: v_permlanex16_b32 v5, v1, s2, s103 ; encoding: [0x05,0x00,0x78,0xd7,0x01,0x05,0x9c,0x01]
0x05,0x00,0x78,0xd7,0x01,0x05,0x9c,0x01 0x05,0x00,0x78,0xd7,0x01,0x05,0x9c,0x01
# GFX10: v_permlanex16_b32 v5, v1, s2, s3 ; encoding: [0x05,0x00,0x78,0xd7,0x01,0x05,0x0c,0x00] # GFX10: v_permlanex16_b32 v5, v1, s2, s3 ; encoding: [0x05,0x00,0x78,0xd7,0x01,0x05,0x0c,0x00]
0x05,0x00,0x78,0xd7,0x01,0x05,0x0c,0x00 0x05,0x00,0x78,0xd7,0x01,0x05,0x0c,0x00
# GFX10: v_permlanex16_b32 v5, v1, s2, 0xaf123456 ; encoding: [0x05,0x00,0x78,0xd7,0x01,0x05,0xfc,0x03,0x56,0x34,0x12,0xaf]
0x05,0x00,0x78,0xd7,0x01,0x05,0xfc,0x03,0x56,0x34,0x12,0xaf
# GFX10: v_permlanex16_b32 v5, v1, s2, s3 op_sel:[0,1] ; encoding: [0x05,0x10,0x78,0xd7,0x01,0x05,0x0c,0x00] # GFX10: v_permlanex16_b32 v5, v1, s2, s3 op_sel:[0,1] ; encoding: [0x05,0x10,0x78,0xd7,0x01,0x05,0x0c,0x00]
0x05,0x10,0x78,0xd7,0x01,0x05,0x0c,0x00 0x05,0x10,0x78,0xd7,0x01,0x05,0x0c,0x00
# GFX10: v_permlanex16_b32 v5, v1, s2, s3 op_sel:[1,0] ; encoding: [0x05,0x08,0x78,0xd7,0x01,0x05,0x0c,0x00] # GFX10: v_permlanex16_b32 v5, v1, s2, s3 op_sel:[1,0] ; encoding: [0x05,0x08,0x78,0xd7,0x01,0x05,0x0c,0x00]
0x05,0x08,0x78,0xd7,0x01,0x05,0x0c,0x00 0x05,0x08,0x78,0xd7,0x01,0x05,0x0c,0x00
# GFX10: v_permlanex16_b32 v5, v1, s2, s3 op_sel:[1,1] ; encoding: [0x05,0x18,0x78,0xd7,0x01,0x05,0x0c,0x00] # GFX10: v_permlanex16_b32 v5, v1, s2, s3 op_sel:[1,1] ; encoding: [0x05,0x18,0x78,0xd7,0x01,0x05,0x0c,0x00]
0x05,0x18,0x78,0xd7,0x01,0x05,0x0c,0x00 0x05,0x18,0x78,0xd7,0x01,0x05,0x0c,0x00
▲ Show 20 Lines • Show All 3,476 Lines • Show Last 20 Lines