[X86][2/2] Support PREFETCHI instructions

[pengfei]

Summary

Optimize prefetchit0/1 to prefetcht0/1 for non-rip address

For more details about these instructions, please refer to the latest ISE document: https://www.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html

[LuoYuanke]

llvm/lib/Target/X86/X86ISelLowering.cpp

36838

It seems morph code prefetch to data prefetch. Does it help performance? I'm sure about the cache hierarchy. Which cache level is shared between code cache and data cache?

[pengfei]

llvm/lib/Target/X86/X86ISelLowering.cpp

36838

I assume data prefetch is better than nop. We also use data prefetch to replace when PREFETCHI is not available.

[craig.topper]

llvm/lib/Target/X86/X86ISelLowering.cpp

36839

Can we call setDesc instead of copying the operands?

[pengfei]

Rebase and address comments.

llvm/lib/Target/X86/X86ISelLowering.cpp

36839

Yeah, setDesc is perfect, thanks!

[RKSimon]

LGTM - cheers

llvm/lib/Target/X86/X86ISelLowering.cpp

36986

A comment might be nice :)

[pengfei]

Add comment.

[goldstein.w.n]

llvm/lib/Target/X86/X86ISelLowering.cpp

36987

Is this actually an optimization? IIRC there are some micro-arch where data can't both be in icache and dcache so this might have a flushing affect.

[pengfei]

Abandon this. The problem has been solved by D142797.

llvm/lib/Target/X86/X86ISelLowering.cpp

 
     if (Opc == X86::TILESTORED)
       MIB.addReg(TMMImmToTMMReg(MI.getOperand(CurOp++).getImm()),
                  RegState::Undef);
 
     MI.eraseFromParent(); // The pseudo is gone now.
     return BB;
   }
+  case X86::PREFETCHIT0:
+  case X86::PREFETCHIT1: {
+    unsigned Opc =
+        MI.getOpcode() == X86::PREFETCHIT0 ? X86::PREFETCHT0 : X86::PREFETCHT1;
+    if (MI.getOperand(0).getReg() != X86::RIP) {
+      MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, TII->get(Opc));
+      for (unsigned Idx = 0; Idx < X86::AddrNumOperands; ++Idx)
+        MIB.add(MI.getOperand(Idx));
+      MI.eraseFromParent();
+    }
+    return BB;
+  }
   }
 }
 
 //===----------------------------------------------------------------------===//
 //                           X86 Optimization Hooks
 //===----------------------------------------------------------------------===//
 
 bool

                                             Op.getConstantOperandVal(1));
     Known = DAG.computeKnownBits(Src, DemandedElt, Depth + 1);
     Known = Known.anyextOrTrunc(BitWidth);
     Known.Zero.setBitsFrom(SrcVT.getScalarSizeInBits());
     break;
   }
   case X86ISD::VSRAI:
   case X86ISD::VSHLI:
   case X86ISD::VSRLI: {
     unsigned ShAmt = Op.getConstantOperandVal(1);
     if (ShAmt >= VT.getScalarSizeInBits()) {
       // Out of range logical bit shifts are guaranteed to be zero.
       // Out of range arithmetic bit shifts splat the sign bit.
       if (Opc != X86ISD::VSRAI) {
         Known.setAllZero();
         break;
       }
 

llvm/lib/Target/X86/X86InstrInfo.td

let Predicates = [HasUINTR, In64BitMode], SchedRW = [WriteSystem] in {
   let Defs = [EFLAGS] in
     def TESTUI : I<0x01, MRM_ED, (outs), (ins), "testui",
                    [(set EFLAGS, (X86testui))]>, XS;
 }
 
 //===----------------------------------------------------------------------===//
 // PREFETCHIT0 and PREFETCHIT1 Instructions
 // prefetch ADDR, RW, Locality, Data
-let Predicates = [HasPREFETCHI, In64BitMode], SchedRW = [WriteLoad] in {
+let Predicates = [HasPREFETCHI, In64BitMode], SchedRW = [WriteLoad],
+    usesCustomInserter = 1 in {
   def PREFETCHIT0 : I<0x18, MRM7m, (outs), (ins i8mem:$src),
     "prefetchit0\t$src", [(prefetch addr:$src, (i32 0), (i32 3), (i32 0))]>, TB;
   def PREFETCHIT1 : I<0x18, MRM6m, (outs), (ins i8mem:$src),
     "prefetchit1\t$src", [(prefetch addr:$src, (i32 0), (i32 2), (i32 0))]>, TB;
 }
 
 //===----------------------------------------------------------------------===//
 // Pattern fragments to auto generate TBM instructions.

llvm/test/CodeGen/X86/prefetch.ll

 ; PREFETCHI-NEXT:    prefetcht2 (%rdi)
 ; PREFETCHI-NEXT:    prefetcht1 (%rdi)
 ; PREFETCHI-NEXT:    prefetcht0 (%rdi)
 ; PREFETCHI-NEXT:    prefetchnta (%rdi)
 ; PREFETCHI-NEXT:    prefetcht2 (%rdi)
 ; PREFETCHI-NEXT:    prefetcht1 (%rdi)
 ; PREFETCHI-NEXT:    prefetcht0 (%rdi)
 ; PREFETCHI-NEXT:    prefetchnta (%rdi)
-; PREFETCHI-NEXT:    prefetchit1 (%rdi)
-; PREFETCHI-NEXT:    prefetchit0 (%rdi)
+; PREFETCHI-NEXT:    prefetcht1 (%rdi)
+; PREFETCHI-NEXT:    prefetcht0 (%rdi)
 ; PREFETCHI-NEXT:    prefetchit1 t(%rip)
 ; PREFETCHI-NEXT:    prefetchit0 ext(%rip)
 ; PREFETCHI-NEXT:    retq
 entry:
   tail call void @llvm.prefetch( ptr %ptr, i32 0, i32 1, i32 1 )
   tail call void @llvm.prefetch( ptr %ptr, i32 0, i32 2, i32 1 )
   tail call void @llvm.prefetch( ptr %ptr, i32 0, i32 3, i32 1 )
   tail call void @llvm.prefetch( ptr %ptr, i32 0, i32 0, i32 1 )