[AMDGPU] Make V_SAT_PK_U8_I16 a True16 Instruction

[Joe_Nash]

Summary

The return type is two u8 packed into a 16 bit VGPR, so this instruction
should be True16.

[Joe_Nash]

It's not clear to me if this instruction was ever selected. I don't see any ISel pattern or reference in tablegen or c++. In the synthesized tablgen defs, I see list<dag> Pattern = [(set i32:$vdst, (null_frag (i32 (VOP3Mods0 i32:$src0))))]; which I think doesn't get used because of the null_frag? Anyway, if it is being selected, do I need to update the pattern for the type change?

[dp]

MC changes LGTM.

[arsenm]

In D135478#3843621, @Joe_Nash wrote:

It's not clear to me if this instruction was ever selected. I don't see any ISel pattern or reference in tablegen or c++. In the synthesized tablgen defs, I see list<dag> Pattern = [(set i32:$vdst, (null_frag (i32 (VOP3Mods0 i32:$src0))))]; which I think doesn't get used because of the null_frag? Anyway, if it is being selected, do I need to update the pattern for the type change?

If it's not getting selected, it probably should be. I believe this corresponds to llvm.sadd.sat

[Joe_Nash]

In D135478#3844280, @arsenm wrote:

In D135478#3843621, @Joe_Nash wrote:

It's not clear to me if this instruction was ever selected. I don't see any ISel pattern or reference in tablegen or c++. In the synthesized tablgen defs, I see list<dag> Pattern = [(set i32:$vdst, (null_frag (i32 (VOP3Mods0 i32:$src0))))]; which I think doesn't get used because of the null_frag? Anyway, if it is being selected, do I need to update the pattern for the type change?

If it's not getting selected, it probably should be. I believe this corresponds to llvm.sadd.sat

Thanks. I made an issue for this https://github.com/llvm/llvm-project/issues/58266

llvm/lib/Target/AMDGPU/SIInstrInfo.td

 def VOP_I16_I16_I16 : VOPProfile <[i16, i16, i16, untyped]>;
 def VOP_I16_I16_I16_ARITH : VOPProfile <[i16, i16, i16, untyped], 0, /*EnableClamp=*/1>;
 
 def VOP_I16_I16_I16_I16 : VOPProfile <[i16, i16, i16, i16, untyped]>;
 def VOP_F16_F16_F16_F16 : VOPProfile <[f16, f16, f16, f16, untyped]>;
 
 def VOP_I32_I16_I16_I32 : VOPProfile <[i32, i16, i16, i32, untyped]>;
 def VOP_I32_I16 : VOPProfile <[i32, i16, untyped, untyped]>;
+def VOP_I16_I32 : VOPProfile <[i16, i32, untyped, untyped]>;
 
 def VOP_V2F16_V2F16_V2F16 : VOPProfile <[v2f16, v2f16, v2f16, untyped]>;
 def VOP_V2I16_V2I16_V2I16 : VOPProfile <[v2i16, v2i16, v2i16, untyped]>;
 def VOP_B32_F16_F16 : VOPProfile <[i32, f16, f16, untyped]>;
 
 def VOP_V2F16_V2F16_V2F16_V2F16 : VOPProfile <[v2f16, v2f16, v2f16, v2f16]>;
 def VOP_V2I16_V2I16_V2I16_V2I16 : VOPProfile <[v2i16, v2i16, v2i16, v2i16]>;
 def VOP_V2I16_F32_F32 : VOPProfile <[v2i16, f32, f32, untyped]>;

llvm/lib/Target/AMDGPU/VOP1Instructions.td

 let SubtargetPredicate = isGFX9Plus in {
   def V_SWAP_B32 : VOP1_Pseudo<"v_swap_b32", VOP_SWAP_I32, [], 1> {
     let Constraints = "$vdst = $src1, $vdst1 = $src0";
     let DisableEncoding = "$vdst1,$src1";
     let SchedRW = [Write64Bit, Write64Bit];
   }
 
   let isReMaterializable = 1 in
-  defm V_SAT_PK_U8_I16    : VOP1Inst<"v_sat_pk_u8_i16", VOP_I32_I32>;
+  defm V_SAT_PK_U8_I16    : VOP1Inst_t16<"v_sat_pk_u8_i16", VOP_I16_I32>;
 
   let mayRaiseFPException = 0 in {
     let OtherPredicates = [Has16BitInsts, NotHasTrue16BitInsts] in {
       defm V_CVT_NORM_I16_F16 : VOP1Inst<"v_cvt_norm_i16_f16", VOP_I16_F16_SPECIAL_OMOD>;
       defm V_CVT_NORM_U16_F16 : VOP1Inst<"v_cvt_norm_u16_f16", VOP_I16_F16_SPECIAL_OMOD>;
     }
     let OtherPredicates = [HasTrue16BitInsts] in {
       defm V_CVT_NORM_I16_F16_t16 : VOP1Inst<"v_cvt_norm_i16_f16_t16", VOP_I16_F16_SPECIAL_OMOD_t16>;

 defm V_FREXP_EXP_I16_F16_t16 : VOP1_Real_FULL_t16_gfx11<0x05a, "v_frexp_exp_i16_f16">;
 defm V_FLOOR_F16_t16         : VOP1_Real_FULL_t16_gfx11<0x05b, "v_floor_f16">;
 defm V_CEIL_F16_t16          : VOP1_Real_FULL_t16_gfx11<0x05c, "v_ceil_f16">;
 defm V_TRUNC_F16_t16         : VOP1_Real_FULL_t16_gfx11<0x05d, "v_trunc_f16">;
 defm V_RNDNE_F16_t16         : VOP1_Real_FULL_t16_gfx11<0x05e, "v_rndne_f16">;
 defm V_FRACT_F16_t16         : VOP1_Real_FULL_t16_gfx11<0x05f, "v_fract_f16">;
 defm V_SIN_F16_t16           : VOP1_Real_FULL_t16_gfx11<0x060, "v_sin_f16">;
 defm V_COS_F16_t16           : VOP1_Real_FULL_t16_gfx11<0x061, "v_cos_f16">;
+defm V_SAT_PK_U8_I16_t16     : VOP1_Real_FULL_t16_gfx11<0x062, "v_sat_pk_u8_i16">;
 defm V_CVT_NORM_I16_F16_t16  : VOP1_Real_FULL_t16_gfx11<0x063, "v_cvt_norm_i16_f16">;
 defm V_CVT_NORM_U16_F16_t16  : VOP1_Real_FULL_t16_gfx11<0x064, "v_cvt_norm_u16_f16">;
 
 defm V_CVT_F16_F32_t16       : VOP1_Real_FULL_t16_gfx11<0x00a, "v_cvt_f16_f32">;
 defm V_CVT_F32_F16_t16       : VOP1_Real_FULL_t16_gfx11<0x00b, "v_cvt_f32_f16">;
 
 //===----------------------------------------------------------------------===//
 // GFX10.

 defm V_FREXP_EXP_I16_F16 : VOP1_Real_gfx10<0x05a>;
 defm V_FLOOR_F16         : VOP1_Real_gfx10<0x05b>;
 defm V_CEIL_F16          : VOP1_Real_gfx10<0x05c>;
 defm V_TRUNC_F16         : VOP1_Real_gfx10<0x05d>;
 defm V_RNDNE_F16         : VOP1_Real_gfx10<0x05e>;
 defm V_FRACT_F16         : VOP1_Real_gfx10<0x05f>;
 defm V_SIN_F16           : VOP1_Real_gfx10<0x060>;
 defm V_COS_F16           : VOP1_Real_gfx10<0x061>;
-defm V_SAT_PK_U8_I16     : VOP1_Real_gfx10_FULL_gfx11<0x062>;
+defm V_SAT_PK_U8_I16     : VOP1_Real_gfx10<0x062>;
 defm V_CVT_NORM_I16_F16  : VOP1_Real_gfx10<0x063>;
 defm V_CVT_NORM_U16_F16  : VOP1_Real_gfx10<0x064>;
 
 defm V_SWAP_B32          : VOP1Only_Real_gfx10_gfx11<0x065>;
 defm V_SWAPREL_B32       : VOP1Only_Real_gfx10_gfx11<0x068>;
 
 //===----------------------------------------------------------------------===//
 // GFX7, GFX10.

llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_err.s

 // GFX11: error: operands are not valid for this GPU or mode
 
 v_rsq_f16_e32 v255, v1
 // GFX11: error: operands are not valid for this GPU or mode
 
 v_rsq_f16_e32 v5, v199
 // GFX11: error: operands are not valid for this GPU or mode
 
+v_sat_pk_u8_i16_e32 v199, v5
+// GFX11: error: operands are not valid for this GPU or mode
+
 v_sin_f16_e32 v128, 0xfe0b
 // GFX11: error: operands are not valid for this GPU or mode
 
 v_sin_f16_e32 v255, v1
 // GFX11: error: operands are not valid for this GPU or mode
 
 v_sin_f16_e32 v5, v199
 // GFX11: error: operands are not valid for this GPU or mode

 // GFX11: error: invalid operand for instruction
 
 v_rsq_f16_e32 v255, v1 quad_perm:[3,2,1,0]
 // GFX11: error: invalid operand for instruction
 
 v_rsq_f16_e32 v5, v199 quad_perm:[3,2,1,0]
 // GFX11: error: invalid operand for instruction
 
+v_sat_pk_u8_i16_e32 v199, v5 quad_perm:[3,2,1,0]
+// GFX11: error: invalid operand for instruction
+
 v_sin_f16_e32 v255, v1 quad_perm:[3,2,1,0]
 // GFX11: error: invalid operand for instruction
 
 v_sin_f16_e32 v5, v199 quad_perm:[3,2,1,0]
 // GFX11: error: invalid operand for instruction
 
 v_sqrt_f16_e32 v255, v1 quad_perm:[3,2,1,0]
 // GFX11: error: invalid operand for instruction

 // GFX11: error: invalid operand for instruction
 
 v_rsq_f16_e32 v255, v1 dpp8:[7,6,5,4,3,2,1,0]
 // GFX11: error: invalid operand for instruction
 
 v_rsq_f16_e32 v5, v199 dpp8:[7,6,5,4,3,2,1,0]
 // GFX11: error: invalid operand for instruction
 
+v_sat_pk_u8_i16_e32 v199, v5 dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: error: invalid operand for instruction
+
 v_sin_f16_e32 v255, v1 dpp8:[7,6,5,4,3,2,1,0]
 // GFX11: error: invalid operand for instruction
 
 v_sin_f16_e32 v5, v199 dpp8:[7,6,5,4,3,2,1,0]
 // GFX11: error: invalid operand for instruction
 
 v_sqrt_f16_e32 v255, v1 dpp8:[7,6,5,4,3,2,1,0]
 // GFX11: error: invalid operand for instruction

llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_promote.s

 // GFX11: v_rsq_f16_e64
 
 v_rsq_f16 v255, vcc_lo
 // GFX11: v_rsq_f16_e64
 
 v_rsq_f16 v5, v199
 // GFX11: v_rsq_f16_e64
 
+v_sat_pk_u8_i16 v199, v5
+// GFX11: v_sat_pk_u8_i16_e64
+
 v_sin_f16 v128, 0xfe0b
 // GFX11: v_sin_f16_e64
 
 v_sin_f16 v255, -1
 // GFX11: v_sin_f16_e64
 
 v_sin_f16 v255, 0.5
 // GFX11: v_sin_f16_e64

 // GFX11: v_rsq_f16_e64
 
 v_rsq_f16 v255, v127 quad_perm:[3,2,1,0]
 // GFX11: v_rsq_f16_e64
 
 v_rsq_f16 v5, v199 quad_perm:[3,2,1,0]
 // GFX11: v_rsq_f16_e64
 
+v_sat_pk_u8_i16 v199, v5 quad_perm:[3,2,1,0]
+// GFX11: v_sat_pk_u8_i16_e64
+
 v_sin_f16 v255, v1 quad_perm:[3,2,1,0]
 // GFX11: v_sin_f16_e64
 
 v_sin_f16 v255, v127 quad_perm:[3,2,1,0]
 // GFX11: v_sin_f16_e64
 
 v_sin_f16 v5, v199 quad_perm:[3,2,1,0]
 // GFX11: v_sin_f16_e64

 // GFX11: v_rsq_f16_e64
 
 v_rsq_f16 v255, v127 dpp8:[7,6,5,4,3,2,1,0]
 // GFX11: v_rsq_f16_e64
 
 v_rsq_f16 v5, v199 dpp8:[7,6,5,4,3,2,1,0]
 // GFX11: v_rsq_f16_e64
 
+v_sat_pk_u8_i16 v199, v5 dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: v_sat_pk_u8_i16_e64
+
 v_sin_f16 v255, v1 dpp8:[7,6,5,4,3,2,1,0]
 // GFX11: v_sin_f16_e64
 
 v_sin_f16 v255, v127 dpp8:[7,6,5,4,3,2,1,0]
 // GFX11: v_sin_f16_e64
 
 v_sin_f16 v5, v199 dpp8:[7,6,5,4,3,2,1,0]
 // GFX11: v_sin_f16_e64