[RISCV][CodeGen] Add Scheduling for vset{i}vl{i} instruction

[michaelmaitland]

Use 0 for read advance and fix formatting

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

4453

There's nothing to "Read" here. The sources are immediates

[michaelmaitland]

Remove read from PseduoVSETIVLI

[michaelmaitland]

Remove dead ReadVSETIVLI

[craig.topper]

LGTM

llvm/lib/Target/RISCV/RISCVInstrInfoV.td

 
 //===----------------------------------------------------------------------===//
 // Instructions
 //===----------------------------------------------------------------------===//
 
 let Predicates = [HasVInstructions] in {
 let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in {
 def VSETVLI : RVInstSetVLi<(outs GPR:$rd), (ins GPR:$rs1, VTypeIOp11:$vtypei),
-                           "vsetvli", "$rd, $rs1, $vtypei">;
-
+                           "vsetvli", "$rd, $rs1, $vtypei">,
+                           Sched<[WriteVSETVLI, ReadVSETVLI]>;
 def VSETIVLI : RVInstSetiVLi<(outs GPR:$rd), (ins uimm5:$uimm, VTypeIOp10:$vtypei),
-                             "vsetivli", "$rd, $uimm, $vtypei">;
+                             "vsetivli", "$rd, $uimm, $vtypei">,
+                             Sched<[WriteVSETIVLI]>;
 
 def VSETVL : RVInstSetVL<(outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),
-                         "vsetvl", "$rd, $rs1, $rs2">;
+                         "vsetvl", "$rd, $rs1, $rs2">,
+                          Sched<[WriteVSETVL, ReadVSETVL, ReadVSETVL]>;
 } // hasSideEffects = 1, mayLoad = 0, mayStore = 0
 foreach eew = [8, 16, 32] in {
   defvar w = !cast<RISCVWidth>("LSWidth" # eew);
 
   // Vector Unit-Stride Instructions
   def VLE#eew#_V : VUnitStrideLoad<w, "vle"#eew#".v">, VLESched<eew>;
   def VSE#eew#_V  : VUnitStrideStore<w,  "vse"#eew#".v">, VSESched<eew>;
 

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

 //===----------------------------------------------------------------------===//
 
 // Pseudos.
 let hasSideEffects = 1, mayLoad = 0, mayStore = 0, Defs = [VL, VTYPE] in {
 // Due to rs1=X0 having special meaning, we need a GPRNoX0 register class for
 // the when we aren't using one of the special X0 encodings. Otherwise it could
 // be accidentally be made X0 by MachineIR optimizations. To satisfy the
 // verifier, we also need a GPRX0 instruction for the special encodings.
-def PseudoVSETVLI : Pseudo<(outs GPR:$rd), (ins GPRNoX0:$rs1, VTypeIOp11:$vtypei), []>;
-def PseudoVSETVLIX0 : Pseudo<(outs GPR:$rd), (ins GPRX0:$rs1, VTypeIOp11:$vtypei), []>;
-def PseudoVSETIVLI : Pseudo<(outs GPR:$rd), (ins uimm5:$rs1, VTypeIOp10:$vtypei), []>;
+def PseudoVSETVLI : Pseudo<(outs GPR:$rd), (ins GPRNoX0:$rs1, VTypeIOp11:$vtypei), []>,
+                    Sched<[WriteVSETVLI, ReadVSETVLI]>;
+def PseudoVSETVLIX0 : Pseudo<(outs GPR:$rd), (ins GPRX0:$rs1, VTypeIOp11:$vtypei), []>,
+                      Sched<[WriteVSETVLI, ReadVSETVLI]>;
+def PseudoVSETIVLI : Pseudo<(outs GPR:$rd), (ins uimm5:$rs1, VTypeIOp10:$vtypei), []>,
+                     Sched<[WriteVSETIVLI]>;
 }
 
 //===----------------------------------------------------------------------===//
 // 7. Vector Loads and Stores
 //===----------------------------------------------------------------------===//
 
 //===----------------------------------------------------------------------===//
 // 7.4 Vector Unit-Stride Instructions

llvm/lib/Target/RISCV/RISCVScheduleV.td

 //===-- RISCVScheduleV.td - RISCV Scheduling Definitions V -*- tablegen -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 //===----------------------------------------------------------------------===//
 /// Define scheduler resources associated with def operands.
 
 // 3.6 Vector Byte Length vlenb
 def WriteRdVLENB      : SchedWrite;
 
+// 6. Configuration-Setting Instructions
+def WriteVSETVLI      : SchedWrite;
+def WriteVSETIVLI     : SchedWrite;
+def WriteVSETVL       : SchedWrite;
+
 // 7. Vector Loads and Stores
 // 7.4. Vector Unit-Stride Instructions
 def WriteVLDE8        : SchedWrite;
 def WriteVLDE16       : SchedWrite;
 def WriteVLDE32       : SchedWrite;
 def WriteVLDE64       : SchedWrite;
 def WriteVSTE8        : SchedWrite;
 def WriteVSTE16       : SchedWrite;

 def WriteVMov1V       : SchedWrite;
 def WriteVMov2V       : SchedWrite;
 def WriteVMov4V       : SchedWrite;
 def WriteVMov8V       : SchedWrite;
 
 //===----------------------------------------------------------------------===//
 /// Define scheduler resources associated with use operands.
 
+// 6. Configuration-Setting Instructions
+def ReadVSETVLI       : SchedRead;
+def ReadVSETIVLI      : SchedRead;
+def ReadVSETVL        : SchedRead;
+
 // 7. Vector Loads and Stores
 def ReadVLDX          : SchedRead;
 def ReadVSTX          : SchedRead;
 // 7.4. Vector Unit-Stride Instructions
 def ReadVSTE8V        : SchedRead;
 def ReadVSTE16V       : SchedRead;
 def ReadVSTE32V       : SchedRead;
 def ReadVSTE64V       : SchedRead;

 /// Define default scheduler resources for V.
 
 multiclass UnsupportedSchedV {
 let Unsupported = true in {
 
 // 3.6 Vector Byte Length vlenb
 def : WriteRes<WriteRdVLENB, []>;
 
+// 6. Configuration-Setting Instructions
+def : WriteRes<WriteVSETVLI, []>;
+def : WriteRes<WriteVSETIVLI, []>;
+def : WriteRes<WriteVSETVL, []>;
+
 // 7. Vector Loads and Stores
 def : WriteRes<WriteVLDE8, []>;
 def : WriteRes<WriteVLDE16, []>;
 def : WriteRes<WriteVLDE32, []>;
 def : WriteRes<WriteVLDE64, []>;
 def : WriteRes<WriteVSTE8, []>;
 def : WriteRes<WriteVSTE16, []>;
 def : WriteRes<WriteVSTE32, []>;

 def : WriteRes<WriteVGatherX, []>;
 def : WriteRes<WriteVGatherI, []>;
 def : WriteRes<WriteVCompressV, []>;
 def : WriteRes<WriteVMov1V, []>;
 def : WriteRes<WriteVMov2V, []>;
 def : WriteRes<WriteVMov4V, []>;
 def : WriteRes<WriteVMov8V, []>;
 
+// 6. Configuration-Setting Instructions
+def : ReadAdvance<ReadVSETVLI, 0>;
+def : ReadAdvance<ReadVSETIVLI, 0>;
+def : ReadAdvance<ReadVSETVL, 0>;
+
 // 7. Vector Loads and Stores
 def : ReadAdvance<ReadVLDX, 0>;
 def : ReadAdvance<ReadVSTX, 0>;
 def : ReadAdvance<ReadVSTE8V, 0>;
 def : ReadAdvance<ReadVSTE16V, 0>;
 def : ReadAdvance<ReadVSTE32V, 0>;
 def : ReadAdvance<ReadVSTE64V, 0>;
 def : ReadAdvance<ReadVSTM, 0>;