[AArch64] Ensure condition (SUBS) has no uses of value in performCONDCombine

[dmgreen]

Summary

performCONDCombine removes and 0xff in patterns of SUBS (and (add(,.), 0xff), C) under certain complex conditions. It doesn't come up often, but in the lowering of usub.sat where the SUBS is both uses as a condition and as a value, the and is removed where it would only be valid for the condition.

Removing performCONDCombine entirely alters none of the existing lit tests, except for the two pr58109 tests added for this (which the differences of here are shown here). It does appear to come up in some cases in larger codebases.

Fixes #58109.

[samtebbs]

LGTM

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

 SDValue performCONDCombine(SDNode *N,
                            TargetLowering::DAGCombinerInfo &DCI,
                            SelectionDAG &DAG, unsigned CCIndex,
                            unsigned CmpIndex) {
   unsigned CC = cast<ConstantSDNode>(N->getOperand(CCIndex))->getSExtValue();
   SDNode *SubsNode = N->getOperand(CmpIndex).getNode();
   unsigned CondOpcode = SubsNode->getOpcode();
 
-  if (CondOpcode != AArch64ISD::SUBS)
+  if (CondOpcode != AArch64ISD::SUBS || SubsNode->hasAnyUseOfValue(0))
     return SDValue();
 
   // There is a SUBS feeding this condition. Is it fed by a mask we can
   // use?
 
   SDNode *AndNode = SubsNode->getOperand(0).getNode();
   unsigned MaskBits = 0;
 

llvm/test/CodeGen/AArch64/and-mask-removal.ll

 ret_true:
   ret i1 true
 }
 
 define i64 @pr58109(i8 signext %0) {
 ; CHECK-SD-LABEL: pr58109:
 ; CHECK-SD:       ; %bb.0:
 ; CHECK-SD-NEXT:    add w8, w0, #1
+; CHECK-SD-NEXT:    and w8, w8, #0xff
 ; CHECK-SD-NEXT:    subs w8, w8, #1
 ; CHECK-SD-NEXT:    csel w0, wzr, w8, lo
 ; CHECK-SD-NEXT:    ret
 ;
 ; CHECK-GI-LABEL: pr58109:
 ; CHECK-GI:       ; %bb.0:
 ; CHECK-GI-NEXT:    add w8, w0, #1
 ; CHECK-GI-NEXT:    and w8, w8, #0xff