[MIPS] Fix useDeprecatedPositionallyEncodedOperands errors.

[jyknight]

Summary

This is a follow-on to https://reviews.llvm.org/D134073.

The number of MIPS16 changes here is a bit surprising -- and even more
so because my changes have not preserved existing behavior. Many of
the fields with mismatched names were NOT previously choosing the
correct argument positionally, but instead doing something completely
wrong (e.g. it would encode a register where an immediate was
expected).

So, I would guess that the machine-code generation for MIPS16 has
never actually functioned. It's also fully untested, thus, these
changes, despite changing behavior, breaks (and fixes) zero tests.

Outside MIPS16, I believe the only functional change is to the 'ginvi'
instruction: it was previously encoding garbage into a field which was
specified to be '00'. Fortunately, it was covered by tests -- and the
tests were testing the incorrect behavior. So, fixed.

[MaskRay]

@wzssyqa Do you mind doing some tests with this patch?

[BC204]

In D134220#3801909, @MaskRay wrote:

@wzssyqa Do you mind doing some tests with this patch?

We patched this patch to commit 539fa1df4634dad7d99e4485e4fc3a82ff1a5481 and tried to build it by using cmake -S llvm -B build -G Unix Makefiles` -DLLVM_ENABLE_PROJECTS=clang -DLLVM_ENABLE_RUNTIMES=libcxx;libcxxabi -DCMAKE_BUILD_TYPE=Release`. But there was an error llvm/lib/Target/Mips/Mips16InstrInfo.td:540:1: error: Illegal operand for the 'AddiuRxRyOffMemX16' instruction! def AddiuRxRyOffMemX16: when we run make V=1 VERBOSE=1 -j$(nproc).

[jyknight]

In D134220#3805376, @BC204 wrote:

We patched this patch to commit 539fa1df4634dad7d99e4485e4fc3a82ff1a5481 and tried to build it by using cmake -S llvm -B build -G Unix Makefiles` -DLLVM_ENABLE_PROJECTS=clang -DLLVM_ENABLE_RUNTIMES=libcxx;libcxxabi -DCMAKE_BUILD_TYPE=Release`. But there was an error llvm/lib/Target/Mips/Mips16InstrInfo.td:540:1: error: Illegal operand for the 'AddiuRxRyOffMemX16' instruction! def AddiuRxRyOffMemX16: when we run make V=1 VERBOSE=1 -j$(nproc).

Both https://reviews.llvm.org/D131003 and https://reviews.llvm.org/D134073 are prerequisites for this (in particular, missing the first one is the cause of the error.)

[jyknight]

Both https://reviews.llvm.org/D131003 and https://reviews.llvm.org/D134073 are prerequisites for this (in particular, missing the first one is the cause of the error.)

Those have been pushed, so this patch applies successfully by itself now.

[BC204]

{F24716735}As of commit 539fa1df4634dad7d99e4485e4fc3a82ff1a5481
with patch https://reviews.llvm.org/D131003, https://reviews.llvm.org/D134073 and https://reviews.llvm.org/D134220.

Compiling this source code

#define R1 2 // number of rows in Matrix-1{F24716679}
#define C1 2 // number of columns in Matrix-1
#define R2 2 // number of rows in Matrix-2
#define C2 2 // number of columns in Matrix-2

int rslt[R1][C2];
void mulMat(int mat1[][C1], int mat2[][C2])
{   
    //printf("Multiplication of given two matrices is:\n");
 
    for (int i = 0; i < R1; i++) {
        for (int j = 0; j < C2; j++) {                                                                                                                                                                 
            rslt[i][j] = 0;
 
            for (int k = 0; k < R2; k++) {
                rslt[i][j] += mat1[i][k] * mat2[k][j];
            }   
 
            //printf("%d\t", rslt[i][j]);
        }   
 
        //printf("\n");
    }   
}

[jyknight]

In D134220#3817710, @BC204 wrote:

bug.log6 KBDownload

Thank you for the test code -- but it also fails without my change. A simpler test is just echo "int f(int a, int b) { return a * b; }" | clang -c -target mips -mips16 -xc - -o /dev/null

The cause of this failure is that the multiply instructions are -- for some reason -- marked as pseudo-instructions (see e.g. MultRxRyRz16 in Mips16InstrInfo.td). That's certainly completely wrong, and, indeed, bolsters my point that MIPS16 object file emission can't possibly have worked before.

I don't intend this change to actually fix MIPS16 object file emission -- it just makes it marginally less broken in the ways that intersect with the cross-target cleanup I'm trying to do.

So I think this change can be approved as-is.

[sdardis]

That's certainly completely wrong, and, indeed, bolsters my point that MIPS16 object file emission can't possibly have worked before.

Sorry for the delay in responding.

Yes, MIPS16 requires the usage of the GNU assembler to work properly. When I was testing the MIPS releases for LLVM, MIPS16 required some extra handing compared to other MIPS variants because of lack of direct object emission.

llvm/lib/Target/Mips/MicroMips32r6InstrFormats.td

class POOL16C_NOT16_FM_MMR6 {
 
   let Inst{15-10} = 0x11;
   let Inst{9-7}   = rt;
   let Inst{6-4}   = rs;
   let Inst{3-0}   = 0b0000;
 }
 
 class POOL16C_MOVEP16_FM_MMR6 {
-  bits<3> dst_regs;
   bits<3> rt;
   bits<3> rs;
 
   bits<16> Inst;
 
   let Inst{15-10} = 0b010001;
-  let Inst{9-7}   = dst_regs;
+  // bits 7-9 are populated by MipsMCCodeEmitter::encodeInstruction, with a
+  // special encoding of both rd1 and rd2.
+  let Inst{9-7}   = ?;
   let Inst{6-4}   = rt;
   let Inst{3}     = rs{2};
   let Inst{2}     = 0b1;
   let Inst{1-0}   = rs{1-0};
 }
 
 class POOL16C_OR16_XOR16_FM_MMR6<bits<4> op> {
   bits<3> rt;

llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td

class GINV_MMR6_DESC_BASE<string opstr,
   list<dag> Pattern = [];
   Format f = FrmFR;
   string BaseOpcode = opstr;
   InstrItinClass Itinerary = Itin;
 }
 
 class GINVI_MMR6_DESC : GINV_MMR6_DESC_BASE<"ginvi", GPR32Opnd,
                                             II_GINVI> {
+  bits<2> type = 0b00;
   dag InOperandList = (ins GPR32Opnd:$rs);
   string AsmString = "ginvi\t$rs";
 }
 class GINVT_MMR6_DESC : GINV_MMR6_DESC_BASE<"ginvt", GPR32Opnd,
                                             II_GINVT>;
 
 class SC_MMR6_DESC_BASE<string opstr, InstrItinClass itin> {
   dag OutOperandList = (outs GPR32Opnd:$dst);

llvm/lib/Target/Mips/MicroMipsInstrFormats.td

class B16_FM {
 
   bits<16> Inst;
 
   let Inst{15-10} = 0x33;
   let Inst{9-0}   = offset;
 }
 
 class MOVEP_FM_MM16 {
-  bits<3> dst_regs;
   bits<3> rt;
   bits<3> rs;
 
   bits<16> Inst;
 
   let Inst{15-10} = 0x21;
-  let Inst{9-7}   = dst_regs;
+  // bits 7-9 are populated by MipsMCCodeEmitter::encodeInstruction, with a
+  // special encoding of both rd1 and rd2.
+  let Inst{9-7}   = ?;
   let Inst{6-4}   = rt;
   let Inst{3-1}   = rs;
   let Inst{0}     = 0;
 }
 
 //===----------------------------------------------------------------------===//
 // MicroMIPS 32-bit Instruction Formats
 //===----------------------------------------------------------------------===//

llvm/lib/Target/Mips/Mips.td

 include "MipsRegisterBanks.td"
 include "MipsCombine.td"
 
 // Avoid forward declaration issues.
 include "MipsScheduleP5600.td"
 include "MipsScheduleGeneric.td"
 
 def MipsInstrInfo : InstrInfo {
- let useDeprecatedPositionallyEncodedOperands = 1;
 }
 
 //===----------------------------------------------------------------------===//
 // Mips processors supported.
 //===----------------------------------------------------------------------===//
 
 def ImplP5600 : SubtargetFeature<"p5600", "ProcImpl",
                                  "MipsSubtarget::CPU::P5600",

llvm/lib/Target/Mips/Mips16InstrFormats.td

 //===----------------------------------------------------------------------===//
 // Format i8_MOVR32 instruction class in Mips : <|opcode|func|ry|r32>
 //===----------------------------------------------------------------------===//
 
 class FI8_MOVR3216<dag outs, dag ins, string asmstr,
                    list<dag> pattern, InstrItinClass itin>:
   MipsInst16<outs, ins, asmstr, pattern, itin>
 {
-
+  // FIXME: this seems wrong? 'ry' should be 3 bits, and 'r32' 5?
   bits<4> ry;
   bits<4> r32;
 
   let Opcode = 0b01100;
 
   let Inst{10-8} = 0b111;
   let Inst{7-4} = ry;
   let Inst{3-0} = r32;

llvm/lib/Target/Mips/Mips16InstrInfo.td

 
 //
 // I-type instruction format
 //
 // this is only used by bimm. the actual assembly value is a 12 bit signed
 // number
 //
 class FI16_ins<bits<5> op, string asmstr, InstrItinClass itin>:
-  FI16<op, (outs), (ins brtarget:$imm16),
-            !strconcat(asmstr, "\t$imm16 # 16 bit inst"), [], itin>;
+  FI16<op, (outs), (ins brtarget:$imm11),
+            !strconcat(asmstr, "\t$imm11 # 16 bit inst"), [], itin>;
 
 //
 //
 // I8 instruction format
 //
 
 class FI816_ins_base<bits<3> _func, string asmstr,
                      string asmstr2, InstrItinClass itin>:
-  FI816<_func, (outs), (ins simm16:$imm), !strconcat(asmstr, asmstr2),
+  FI816<_func, (outs), (ins simm16:$imm8), !strconcat(asmstr, asmstr2),
         [], itin>;
 
 class FI816_ins<bits<3> _func, string asmstr,
                 InstrItinClass itin>:
-  FI816_ins_base<_func, asmstr, "\t$imm  # 16 bit inst", itin>;
+  FI816_ins_base<_func, asmstr, "\t$imm8  # 16 bit inst", itin>;
 
 class FI816_SP_ins<bits<3> _func, string asmstr,
                    InstrItinClass itin>:
-  FI816_ins_base<_func, asmstr, "\t$$sp, $imm # 16 bit inst", itin>;
+  FI816_ins_base<_func, asmstr, "\t$$sp, $imm8 # 16 bit inst", itin>;
 
 //
 // RI instruction format
 //
 
 
 class FRI16_ins_base<bits<5> op, string asmstr, string asmstr2,
                      InstrItinClass itin>:
-  FRI16<op, (outs CPU16Regs:$rx), (ins simm16:$imm),
+  FRI16<op, (outs CPU16Regs:$rx), (ins simm16:$imm8),
         !strconcat(asmstr, asmstr2), [], itin>;
 
 class FRI16_ins<bits<5> op, string asmstr,
                 InstrItinClass itin>:
-  FRI16_ins_base<op, asmstr, "\t$rx, $imm \t# 16 bit inst", itin>;
+  FRI16_ins_base<op, asmstr, "\t$rx, $imm8 \t# 16 bit inst", itin>;
 
 class FRI16_TCP_ins<bits<5> _op, string asmstr,
                     InstrItinClass itin>:
-  FRI16<_op, (outs CPU16Regs:$rx), (ins pcrel16:$imm, i32imm:$size),
-            !strconcat(asmstr, "\t$rx, $imm\t# 16 bit inst"), [], itin>;
+  FRI16<_op, (outs CPU16Regs:$rx), (ins pcrel16:$imm8, i32imm:$size),
+            !strconcat(asmstr, "\t$rx, $imm8\t# 16 bit inst"), [], itin>;
 
 class FRI16R_ins_base<bits<5> op, string asmstr, string asmstr2,
                      InstrItinClass itin>:
-  FRI16<op, (outs), (ins CPU16Regs:$rx, simm16:$imm),
+  FRI16<op, (outs), (ins CPU16Regs:$rx, simm16:$imm8),
         !strconcat(asmstr, asmstr2), [], itin>;
 
 class FRI16R_ins<bits<5> op, string asmstr,
                 InstrItinClass itin>:
-  FRI16R_ins_base<op, asmstr, "\t$rx, $imm \t# 16 bit inst", itin>;
+  FRI16R_ins_base<op, asmstr, "\t$rx, $imm8 \t# 16 bit inst", itin>;
 
 class F2RI16_ins<bits<5> _op, string asmstr,
                      InstrItinClass itin>:
-  FRI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm),
-        !strconcat(asmstr, "\t$rx, $imm\t# 16 bit inst"), [], itin> {
+  FRI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm8),
+        !strconcat(asmstr, "\t$rx, $imm8\t# 16 bit inst"), [], itin> {
   let Constraints = "$rx_ = $rx";
 }
 
 class FRI16_B_ins<bits<5> _op, string asmstr,
                   InstrItinClass itin>:
-  FRI16<_op, (outs), (ins  CPU16Regs:$rx, brtarget:$imm),
-        !strconcat(asmstr, "\t$rx, $imm  # 16 bit inst"), [], itin>;
+  FRI16<_op, (outs), (ins  CPU16Regs:$rx, brtarget:$imm8),
+        !strconcat(asmstr, "\t$rx, $imm8  # 16 bit inst"), [], itin>;
 //
 // Compare a register and immediate and place result in CC
 // Implicit use of T8
 //
 // EXT-CCRR Instruction format
 //
 class FEXT_CCRXI16_ins<string asmstr>:
   MipsPseudo16<(outs CPU16Regs:$cc), (ins CPU16Regs:$rx, simm16:$imm),
                !strconcat(asmstr, "\t$rx, $imm\n\tmove\t$cc, $$t8"), []> {
   let isCodeGenOnly=1;
   let usesCustomInserter = 1;
 }
 
 // JAL and JALX instruction format
 //
 class FJAL16_ins<bits<1> _X, string asmstr,
                  InstrItinClass itin>:
-  FJAL16<_X, (outs), (ins uimm26:$imm),
-         !strconcat(asmstr, "\t$imm\n\tnop"),[],
+  FJAL16<_X, (outs), (ins uimm26:$imm26),
+         !strconcat(asmstr, "\t$imm26\n\tnop"),[],
          itin>  {
   let isCodeGenOnly=1;
   let Size=6;
 }
 
 class FJALB16_ins<bits<1> _X, string asmstr,
                  InstrItinClass itin>:
-  FJAL16<_X, (outs), (ins uimm26:$imm),
-         !strconcat(asmstr, "\t$imm\t# branch\n\tnop"),[],
+  FJAL16<_X, (outs), (ins uimm26:$imm26),
+         !strconcat(asmstr, "\t$imm26\t# branch\n\tnop"),[],
          itin>  {
   let isCodeGenOnly=1;
   let Size=6;
 }
 
 //
 // EXT-I instruction format
 //
 class FEXT_I16_ins<bits<5> eop, string asmstr, InstrItinClass itin> :
   FEXT_I16<eop, (outs), (ins brtarget:$imm16),
            !strconcat(asmstr, "\t$imm16"),[], itin>;
 
 //
 // EXT-I8 instruction format
 //
 
 class FEXT_I816_ins_base<bits<3> _func, string asmstr,
                          string asmstr2, InstrItinClass itin>:
-  FEXT_I816<_func, (outs), (ins simm16:$imm), !strconcat(asmstr, asmstr2),
+  FEXT_I816<_func, (outs), (ins simm16:$imm16), !strconcat(asmstr, asmstr2),
             [], itin>;
 
 class FEXT_I816_ins<bits<3> _func, string asmstr,
                     InstrItinClass itin>:
-  FEXT_I816_ins_base<_func, asmstr, "\t$imm", itin>;
+  FEXT_I816_ins_base<_func, asmstr, "\t$imm16", itin>;
 
 class FEXT_I816_SP_ins<bits<3> _func, string asmstr,
                        InstrItinClass itin>:
-      FEXT_I816_ins_base<_func, asmstr, "\t$$sp, $imm", itin>;
+      FEXT_I816_ins_base<_func, asmstr, "\t$$sp, $imm16", itin>;
 
 //
 // Assembler formats in alphabetical order.
 // Natural and pseudos are mixed together.
 //
 // Compare two registers and place result in CC
 // Implicit use of T8
 //
 // CC-RR Instruction format
 //
 class FCCRR16_ins<string asmstr> :
   MipsPseudo16<(outs CPU16Regs:$cc), (ins CPU16Regs:$rx, CPU16Regs:$ry),
                !strconcat(asmstr, "\t$rx, $ry\n\tmove\t$cc, $$t8"), []> {
   let isCodeGenOnly=1;
   let usesCustomInserter = 1;
 }
 
 //
 // EXT-RI instruction format
 //
 
 class FEXT_RI16_ins_base<bits<5> _op, string asmstr, string asmstr2,
                          InstrItinClass itin>:
-  FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins simm16:$imm),
+  FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins simm16:$imm16),
                   !strconcat(asmstr, asmstr2), [], itin>;
 
 class FEXT_RI16_ins<bits<5> _op, string asmstr,
                     InstrItinClass itin>:
-  FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $imm", itin>;
+  FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $imm16", itin>;
 
 class FEXT_RI16R_ins_base<bits<5> _op, string asmstr, string asmstr2,
                          InstrItinClass itin>:
-  FEXT_RI16<_op, (outs ), (ins CPU16Regs:$rx, simm16:$imm),
+  FEXT_RI16<_op, (outs ), (ins CPU16Regs:$rx, simm16:$imm16),
                   !strconcat(asmstr, asmstr2), [], itin>;
 
 class FEXT_RI16R_ins<bits<5> _op, string asmstr,
                     InstrItinClass itin>:
-  FEXT_RI16R_ins_base<_op, asmstr, "\t$rx, $imm", itin>;
+  FEXT_RI16R_ins_base<_op, asmstr, "\t$rx, $imm16", itin>;
 
 class FEXT_RI16_PC_ins<bits<5> _op, string asmstr, InstrItinClass itin>:
-  FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $$pc, $imm", itin>;
+  FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $$pc, $imm16", itin>;
 
 class FEXT_RI16_B_ins<bits<5> _op, string asmstr,
                       InstrItinClass itin>:
-  FEXT_RI16<_op, (outs), (ins  CPU16Regs:$rx, brtarget:$imm),
-            !strconcat(asmstr, "\t$rx, $imm"), [], itin>;
+  FEXT_RI16<_op, (outs), (ins  CPU16Regs:$rx, brtarget:$imm16),
+            !strconcat(asmstr, "\t$rx, $imm16"), [], itin>;
 
 class FEXT_RI16_TCP_ins<bits<5> _op, string asmstr,
                         InstrItinClass itin>:
-  FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins pcrel16:$imm, i32imm:$size),
-            !strconcat(asmstr, "\t$rx, $imm"), [], itin>;
+  FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins pcrel16:$imm16, i32imm:$size),
+            !strconcat(asmstr, "\t$rx, $imm16"), [], itin>;
 
 class FEXT_2RI16_ins<bits<5> _op, string asmstr,
                      InstrItinClass itin>:
-  FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm),
-            !strconcat(asmstr, "\t$rx, $imm"), [], itin> {
+  FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm16),
+            !strconcat(asmstr, "\t$rx, $imm16"), [], itin> {
   let Constraints = "$rx_ = $rx";
 }
 
 //
 // EXT-RRI instruction format
 //
 
 class FEXT_RRI16_mem_ins<bits<5> op, string asmstr, Operand MemOpnd,
                          InstrItinClass itin>:
-  FEXT_RRI16<op, (outs CPU16Regs:$ry), (ins  MemOpnd:$addr),
+  FEXT_RRI16<op, (outs CPU16Regs:$ry), (ins  (MemOpnd $rx, $imm16):$addr),
              !strconcat(asmstr, "\t$ry, $addr"), [], itin>;
 
 class FEXT_RRI16_mem2_ins<bits<5> op, string asmstr, Operand MemOpnd,
                           InstrItinClass itin>:
-  FEXT_RRI16<op, (outs ), (ins  CPU16Regs:$ry, MemOpnd:$addr),
+  FEXT_RRI16<op, (outs ), (ins  CPU16Regs:$ry, (MemOpnd $rx, $imm16):$addr),
              !strconcat(asmstr, "\t$ry, $addr"), [], itin>;
 
 //
 //
 // EXT-RRI-A instruction format
 //
 
 class FEXT_RRI_A16_mem_ins<bits<1> op, string asmstr, Operand MemOpnd,
                            InstrItinClass itin>:
-  FEXT_RRI_A16<op, (outs CPU16Regs:$ry), (ins  MemOpnd:$addr),
+  FEXT_RRI_A16<op, (outs CPU16Regs:$ry), (ins  (MemOpnd $rx, $imm15):$addr),
                !strconcat(asmstr, "\t$ry, $addr"), [], itin>;
 
 //
 // EXT-SHIFT instruction format
 //
 class FEXT_SHIFT16_ins<bits<2> _f, string asmstr, InstrItinClass itin>:
-  FEXT_SHIFT16<_f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, uimm5:$sa),
-               !strconcat(asmstr, "\t$rx, $ry, $sa"), [], itin>;
+  FEXT_SHIFT16<_f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, uimm5:$sa6),
+               !strconcat(asmstr, "\t$rx, $ry, $sa6"), [], itin>;
 
 //
 // EXT-T8I8
 //
 class FEXT_T8I816_ins<string asmstr, string asmstr2>:
   MipsPseudo16<(outs),
                (ins CPU16Regs:$rx, CPU16Regs:$ry, brtarget:$imm),
                !strconcat(asmstr2, !strconcat("\t$rx, $ry\n\t",

 }
 //
 
 
 //
 // I8_MOVR32 instruction format (used only by the MOVR32 instructio
 //
 class FI8_MOVR3216_ins<string asmstr, InstrItinClass itin>:
-       FI8_MOVR3216<(outs CPU16Regs:$rz), (ins GPR32:$r32),
-       !strconcat(asmstr,  "\t$rz, $r32"), [], itin>;
+       FI8_MOVR3216<(outs CPU16Regs:$ry), (ins GPR32:$r32),
+       !strconcat(asmstr,  "\t$ry, $r32"), [], itin>;
 
 //
 // I8_MOV32R instruction format (used only by MOV32R instruction)
 //
 
 class FI8_MOV32R16_ins<string asmstr, InstrItinClass itin>:
   FI8_MOV32R16<(outs GPR32:$r32), (ins CPU16Regs:$rz),
                !strconcat(asmstr,  "\t$r32, $rz"), [], itin>;

 class FRR16_JALRC_RA_only_ins<bits<1> nd_, bits<1> l_,
                               string asmstr, InstrItinClass itin>:
   FRR16_JALRC<nd_, l_, 1, (outs), (ins), !strconcat(asmstr, "\t$$ra"),
               [], itin> ;
 
 
 class FRR16_JALRC_ins<bits<1> nd, bits<1> l, bits<1> ra,
                       string asmstr, InstrItinClass itin>:
-  FRR16_JALRC<nd, l, ra, (outs), (ins CPU16Regs:$rx),
-              !strconcat(asmstr, "\t$rx"), [], itin> ;
+  FRR16_JALRC<nd, l, ra, (outs), (ins CPU16Regs:$rs),
+              !strconcat(asmstr, "\t$rs"), [], itin> ;
 
 class FRR_SF16_ins
   <bits<5> _funct, bits<3> _subfunc,
     string asmstr, InstrItinClass itin>:
   FRR_SF16<_funct, _subfunc, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_),
            !strconcat(asmstr, "\t $rx"),
            [], itin> {
   let Constraints = "$rx_ = $rx";
def JrcRa16: FRR16_JALRC_RA_only_ins<1, 1, "jrc", IIM16Alu> {
   let isBranch = 1;
   let isIndirectBranch = 1;
   let isTerminator=1;
   let isBarrier=1;
   let isReturn=1;
 }
 
 def JrcRx16: FRR16_JALRC_ins<1, 1, 0, "jrc", IIM16Alu> {
+  let rx = 0b000;
   let isBranch = 1;
   let isIndirectBranch = 1;
   let isTerminator=1;
   let isBarrier=1;
 }
 //
 // Format: LB ry, offset(rx) MIPS16e
 // Purpose: Load Byte (Extended)

 }
 
 //
 // Format: MFHI rx MIPS16e
 // Purpose: Move From HI Register
 // To copy the special purpose HI register to a GPR.
 //
 def Mfhi16: FRR16_M_ins<0b10000, "mfhi", IIM16Alu> {
+  let ry = 0b000; // no 'ry' field
   let Uses = [HI0];
   let hasSideEffects = 0;
   let isMoveReg = 1;
 }
 
 //
 // Format: MFLO rx MIPS16e
 // Purpose: Move From LO Register
 // To copy the special purpose LO register to a GPR.
 //
 def Mflo16: FRR16_M_ins<0b10010, "mflo", IIM16Alu> {
+  let ry = 0b000; // no 'ry' field
   let Uses = [LO0];
   let hasSideEffects = 0;
   let isMoveReg = 0;
 }
 
 //
 // Pseudo Instruction for mult
 //
def: Mips16Pat<(brind CPU16Regs:$rs), (JrcRx16 CPU16Regs:$rs)> {
   // Ensure that the addition of MIPS32r6/MIPS64r6 support does not change
   // MIPS16's behaviour.
   let AddedComplexity = 1;
 }
 
 // Jump and Link (Call)
 let isCall=1, hasDelaySlot=0 in
 def JumpLinkReg16:
-  FRR16_JALRC<0, 0, 0, (outs), (ins CPU16Regs:$rs),
-              "jalrc\t$rs", [(MipsJmpLink CPU16Regs:$rs)], II_JALRC> {
+  FRR16_JALRC<0, 0, 0, (outs), (ins CPU16Regs:$rx),
+              "jalrc\t$rx", [(MipsJmpLink CPU16Regs:$rx)], II_JALRC> {
   let Defs = [RA];
 }
 
 // Mips16 pseudos
 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1,
   hasExtraSrcRegAllocReq = 1 in
 def RetRA16 : MipsPseudo16<(outs), (ins), "", [(MipsRet)]>;
 

llvm/lib/Target/Mips/Mips32r6InstrInfo.td

class GINV_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
   dag InOperandList = (ins GPROpnd:$rs, uimm2:$type_);
   string AsmString = !strconcat(instr_asm, "\t$rs, $type_");
   list<dag> Pattern = [];
   InstrItinClass Itinerary = itin;
   bit hasSideEffects = 1;
 }
 
 class GINVI_DESC : GINV_DESC_BASE<"ginvi", GPR32Opnd, II_GINVI> {
+  bits<2> type_ = 0b00;
   dag InOperandList = (ins GPR32Opnd:$rs);
   string AsmString = "ginvi\t$rs";
 }
 class GINVT_DESC : GINV_DESC_BASE<"ginvt", GPR32Opnd, II_GINVT>;
 
 class SIGRIE_DESC {
   dag OutOperandList = (outs);
   dag InOperandList = (ins uimm16:$code_);

llvm/lib/Target/Mips/MipsEVAInstrFormats.td

 //===----------------------------------------------------------------------===//
 //
 // Encoding Formats
 //
 //===----------------------------------------------------------------------===//
 
 class SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6 Operation> : MipsEVAInst {
   bits<21> addr;
-  bits<5> hint;
+  bits<5> rt;
   bits<5> base = addr{20-16};
   bits<9> offset = addr{8-0};
 
   bits<32> Inst;
 
   let Inst{31-26} = OPGROUP_SPECIAL3.Value;
   let Inst{25-21} = base;
-  let Inst{20-16} = hint;
+  let Inst{20-16} = rt;
   let Inst{15-7}  = offset;
   let Inst{6}     = 0;
   let Inst{5-0}   = Operation.Value;
 }
 
 class TLB_FM<OPCODE6 Operation> : MipsEVAInst {
   bits<32> Inst;
 
   let Inst{31-26} = OPGROUP_COP0_TLB.Value;
   let Inst{25} = 1;       // CO
   let Inst{24-6} = 0;
   let Inst{5-0} = Operation.Value;
 }

llvm/lib/Target/Mips/MipsEVAInstrInfo.td

class TLB_DESC_BASE<string instr_asm, InstrItinClass itin = NoItinerary> {
   InstrItinClass Itinerary = itin;
 }
 
 class TLBINV_DESC  : TLB_DESC_BASE<"tlbinv", II_TLBINV>;
 class TLBINVF_DESC : TLB_DESC_BASE<"tlbinvf", II_TLBINVF>;
 
 class CACHEE_DESC_BASE<string instr_asm, Operand MemOpnd,
                        InstrItinClass itin = NoItinerary> {
+  // CACHEE puts the "hint" immediate where the encoding would otherwise have "rt"
+  bits<5> hint;
+  bits<5> rt = hint;
+
   dag OutOperandList = (outs);
   dag InOperandList = (ins  MemOpnd:$addr, uimm5:$hint);
   string AsmString = !strconcat(instr_asm, "\t$hint, $addr");
   list<dag> Pattern = [];
   string BaseOpcode = instr_asm;
   string DecoderMethod = "DecodeCacheeOp_CacheOpR6";
   InstrItinClass Itinerary = itin;
 }

llvm/test/MC/Disassembler/Mips/ginv/valid-el.txt

 # RUN: llvm-mc --disassemble %s -triple=mipsel-unknown-linux-gnu \
 # RUN:   -mcpu=mips32r6 -mattr=+ginv | FileCheck %s
 
-0x3d 0x02 0x40 0x7c  # CHECK: ginvi $2
+0x3d 0x00 0x40 0x7c  # CHECK: ginvi $2
 0xbd 0x02 0x40 0x7c  # CHECK: ginvt $2, 2

llvm/test/MC/Disassembler/Mips/ginv/valid-micromips-el.txt

 # RUN: llvm-mc --disassemble %s -triple=mipsel-unknown-linux-gnu \
 # RUN:   -mcpu=mips32r6 -mattr=+micromips,+ginv | FileCheck %s
 
-0x02 0x00 0x7c 0x65  # CHECK: ginvi $2
+0x02 0x00 0x7c 0x61  # CHECK: ginvi $2
 0x02 0x00 0x7c 0x75  # CHECK: ginvt $2, 2

llvm/test/MC/Disassembler/Mips/ginv/valid-micromips.txt

 # RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux-gnu \
 # RUN:   -mcpu=mips32r6 -mattr=+micromips,+ginv | FileCheck %s
 
-0x00 0x02 0x65 0x7c  # CHECK: ginvi $2
+0x00 0x02 0x61 0x7c  # CHECK: ginvi $2
 0x00 0x02 0x75 0x7c  # CHECK: ginvt $2, 2

llvm/test/MC/Disassembler/Mips/ginv/valid.txt

 # RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux-gnu \
 # RUN:   -mcpu=mips32r6 -mattr=+ginv | FileCheck %s
 
-0x7c 0x40 0x02 0x3d  # CHECK: ginvi $2
+0x7c 0x40 0x00 0x3d  # CHECK: ginvi $2
 0x7c 0x40 0x02 0xbd  # CHECK: ginvt $2, 2