[PowerPC] Fix CSR_64_AllRegs_AIX_Dflt_VSX definition

[tingwang]

Summary

According to AIX default ABI, the definition seems incorrect.

Base test case added in https://reviews.llvm.org/D133545.

[lkail]

Please set https://reviews.llvm.org/D133545 as parent revision.

[ZarkoCA]

llvm/lib/Target/PowerPC/PPCCallingConv.td

365–366

Thanks for catching this.

I don't quite understand why it's ok to set it to 31 here even though it seems to work.

[tingwang]

llvm/lib/Target/PowerPC/PPCCallingConv.td

365–366

I just suspected the original definition does not align with AIX default ABI, since CSR_64_AllRegs_Altivec contains V20:31 which are reserved according to ABI, and I thought here CSR_64_AllRegs_AIX_Dflt_VSX should be defined as (<all registers> - <AIX default ABI reserved V20:31>).

Now it seems to me this error is harmless because no functional logic will trigger CSR_64_AllRegs_AIX_Dflt_VSX. (As notified by Kai Luo, JIT on AIX is not supported yet, and @llvm.experimental.patchpoint.void is not functional on AIX.) This may be the reason that only eye ball catches the error, not a broken test case.

[tingwang]

Suspend this patch since the functionality is not supported on AIX.

llvm/lib/Target/PowerPC/PPCCallingConv.td

def CSR_64_AllRegs_Altivec : CalleeSavedRegs<(add CSR_64_AllRegs,
                                              (sequence "V%u", 0, 31))>;
 
 def CSR_64_AllRegs_AIX_Dflt_Altivec : CalleeSavedRegs<(add CSR_64_AllRegs,
                                              (sequence "V%u", 0, 19))>;
 
 def CSR_64_AllRegs_VSX : CalleeSavedRegs<(add CSR_64_AllRegs_Altivec,
                                          (sequence "VSL%u", 0, 31))>;
 
-def CSR_64_AllRegs_AIX_Dflt_VSX : CalleeSavedRegs<(add CSR_64_AllRegs_Altivec,
-                                         (sequence "VSL%u", 0, 19))>;
+def CSR_64_AllRegs_AIX_Dflt_VSX : CalleeSavedRegs<(add CSR_64_AllRegs_AIX_Dflt_Altivec,
+                                         (sequence "VSL%u", 0, 31))>;
 
 def CSR_ALL_VSRP : CalleeSavedRegs<(sequence "VSRp%u", 0, 31)>;
 
 def CSR_VSRP :
   CalleeSavedRegs<(add VSRp26, VSRp27, VSRp28, VSRp29, VSRp30, VSRp31)>;
 
 def CSR_SVR432_VSRP : CalleeSavedRegs<(add CSR_SVR432_Altivec, CSR_VSRP)>;
 

llvm/test/CodeGen/PowerPC/aix64-patchpoint-regmask.ll

 ; RUN: llc -O0 -verify-machineinstrs -mcpu=pwr9 -mtriple powerpc64-ibm-aix-xcoff -print-after=finalize-isel --print-regmask-num-regs=-1 < %s 2>&1 | \
 ; RUN: FileCheck %s
 
-; Error regmask pattern should be fixed: v20:v31 should be reserved in AIX defalut ABI
-; CHECK: PATCHPOINT{{[^<]+}}<regmask {{[^>]+}} $v20 $v21 $v22 $v23 $v24 $v25 $v26 $v27 $v28 $v29 $v30 $v31 {{[^>]+}}>
+; CHECK-NOT: PATCHPOINT{{[^<]+}}<regmask {{[^>]+}} $v20 $v21 $v22 $v23 $v24 $v25 $v26 $v27 $v28 $v29 $v30 $v31 {{[^>]+}}>
+; CHECK-NOT: PATCHPOINT{{[^<]+}}<regmask {{[^>]+}} $v20 {{[^>]+}}>
+; CHECK-NOT: PATCHPOINT{{[^<]+}}<regmask {{[^>]+}} $v21 {{[^>]+}}>
+; CHECK-NOT: PATCHPOINT{{[^<]+}}<regmask {{[^>]+}} $v22 {{[^>]+}}>
+; CHECK-NOT: PATCHPOINT{{[^<]+}}<regmask {{[^>]+}} $v23 {{[^>]+}}>
+; CHECK-NOT: PATCHPOINT{{[^<]+}}<regmask {{[^>]+}} $v24 {{[^>]+}}>
+; CHECK-NOT: PATCHPOINT{{[^<]+}}<regmask {{[^>]+}} $v25 {{[^>]+}}>
+; CHECK-NOT: PATCHPOINT{{[^<]+}}<regmask {{[^>]+}} $v26 {{[^>]+}}>
+; CHECK-NOT: PATCHPOINT{{[^<]+}}<regmask {{[^>]+}} $v27 {{[^>]+}}>
+; CHECK-NOT: PATCHPOINT{{[^<]+}}<regmask {{[^>]+}} $v28 {{[^>]+}}>
+; CHECK-NOT: PATCHPOINT{{[^<]+}}<regmask {{[^>]+}} $v29 {{[^>]+}}>
+; CHECK-NOT: PATCHPOINT{{[^<]+}}<regmask {{[^>]+}} $v30 {{[^>]+}}>
+; CHECK-NOT: PATCHPOINT{{[^<]+}}<regmask {{[^>]+}} $v31 {{[^>]+}}>
 define void @test(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
 entry:
   call anyregcc void (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.void(i64 13, i32 40, ptr inttoptr (i64 0 to ptr), i32 2, i64 %p1, i64 %p2, i64 %p3, i64 %p4)
   ret void
 }
 
 declare void @llvm.experimental.patchpoint.void(i64, i32, ptr, i32, ...)