[RISCV] Add scheduler class to PseudoReadVLENB.

[monkchiang]

LGTM

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
   def PseudoVMV1R_V : VPseudo<VMV1R_V, V_M1, (outs VR:$vd), (ins VR:$vs2)>;
   def PseudoVMV2R_V : VPseudo<VMV2R_V, V_M2, (outs VRM2:$vd), (ins VRM2:$vs2)>;
   def PseudoVMV4R_V : VPseudo<VMV4R_V, V_M4, (outs VRM4:$vd), (ins VRM4:$vs2)>;
   def PseudoVMV8R_V : VPseudo<VMV8R_V, V_M8, (outs VRM8:$vd), (ins VRM8:$vs2)>;
 }
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCodeGenOnly = 1 in {
   def PseudoReadVLENB : Pseudo<(outs GPR:$rd), (ins),
-                               [(set GPR:$rd, (riscv_read_vlenb))]>;
+                               [(set GPR:$rd, (riscv_read_vlenb))]>,
+                        Sched<[WriteRdVLENB]>;
 }
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCodeGenOnly = 1,
     Uses = [VL] in
 def PseudoReadVL : Pseudo<(outs GPR:$rd), (ins), []>;
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 1, isCodeGenOnly = 1 in {
   def PseudoVSPILL_M1 : VPseudo<VS1R_V, V_M1, (outs), (ins VR:$rs1, GPR:$rs2)>;

llvm/lib/Target/RISCV/RISCVScheduleV.td

 //===-- RISCVScheduleV.td - RISCV Scheduling Definitions V -*- tablegen -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 //===----------------------------------------------------------------------===//
 /// Define scheduler resources associated with def operands.
 
+// 3.6 Vector Byte Length vlenb
+def WriteRdVLENB      : SchedWrite;
+
 // 7. Vector Loads and Stores
 // 7.4. Vector Unit-Stride Instructions
 def WriteVLDE8        : SchedWrite;
 def WriteVLDE16       : SchedWrite;
 def WriteVLDE32       : SchedWrite;
 def WriteVLDE64       : SchedWrite;
 def WriteVSTE8        : SchedWrite;
 def WriteVSTE16       : SchedWrite;

 def ReadVMask         : SchedRead;
 
 //===----------------------------------------------------------------------===//
 /// Define default scheduler resources for V.
 
 multiclass UnsupportedSchedV {
 let Unsupported = true in {
 
+// 3.6 Vector Byte Length vlenb
+def : WriteRes<WriteRdVLENB, []>;
+
 // 7. Vector Loads and Stores
 def : WriteRes<WriteVLDE8, []>;
 def : WriteRes<WriteVLDE16, []>;
 def : WriteRes<WriteVLDE32, []>;
 def : WriteRes<WriteVLDE64, []>;
 def : WriteRes<WriteVSTE8, []>;
 def : WriteRes<WriteVSTE16, []>;
 def : WriteRes<WriteVSTE32, []>;