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Differential D129981

[RISCV] Pre-commit tests for D129980. NFC
ClosedPublic

Authored by craig.topper on Jul 17 2022, 8:23 PM.

Details

Reviewers
reames
asb
luismarques
Commits
rG464b3a9d8a1a: [RISCV] Pre-commit tests for D129980. NFC

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Event Timeline

craig.topper created this revision.Jul 17 2022, 8:23 PM
Herald added a project: Restricted Project. · View Herald TranscriptJul 17 2022, 8:23 PM
Herald added subscribers: sunshaoce, VincentWu, luke957 and 27 others. · View Herald Transcript
craig.topper requested review of this revision.Jul 17 2022, 8:23 PM
Herald added a project: Restricted Project. · View Herald TranscriptJul 17 2022, 8:23 PM
Herald added subscribers: • pcwang-thead, eopXD, MaskRay. · View Herald Transcript
craig.topper added a child revision: D129980: [RISCV] Optimize (seteq (i64 (and X, 0xffffffff)), C1).Jul 17 2022, 8:23 PM
Harbormaster completed remote builds in B175944: Diff 445381.Jul 17 2022, 9:42 PM
This revision was not accepted when it landed; it landed in state Needs Review.Jul 18 2022, 10:55 AM
This revision was landed with ongoing or failed builds.
Closed by commit rG464b3a9d8a1a: [RISCV] Pre-commit tests for D129980. NFC (authored by craig.topper). · Explain Why
This revision was automatically updated to reflect the committed changes.
craig.topper added a commit: rG464b3a9d8a1a: [RISCV] Pre-commit tests for D129980. NFC.

Revision Contents

PathSize
llvm/
test/
CodeGen/
RISCV/
62 lines

Diff 445567

llvm/test/CodeGen/RISCV/i64-icmp.ll

Show First 20 Lines • Show All 679 Lines • ▼ Show 20 Lines
; RV64I-NEXT: lui a1, 1048575 ; RV64I-NEXT: lui a1, 1048575
; RV64I-NEXT: addiw a1, a1, 2047 ; RV64I-NEXT: addiw a1, a1, 2047
; RV64I-NEXT: slt a0, a0, a1 ; RV64I-NEXT: slt a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = icmp sle i64 %a, -2050 %1 = icmp sle i64 %a, -2050
%2 = zext i1 %1 to i64 %2 = zext i1 %1 to i64
ret i64 %2 ret i64 %2
} }
define i64 @icmp_eq_zext_inreg_small_constant(i64 %a) nounwind {
; RV64I-LABEL: icmp_eq_zext_inreg_small_constant:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: addi a0, a0, -123
; RV64I-NEXT: seqz a0, a0
; RV64I-NEXT: ret
%1 = and i64 %a, 4294967295
%2 = icmp eq i64 %1, 123
%3 = zext i1 %2 to i64
ret i64 %3
}
define i64 @icmp_eq_zext_inreg_large_constant(i64 %a) nounwind {
; RV64I-LABEL: icmp_eq_zext_inreg_large_constant:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: lui a1, 138
; RV64I-NEXT: addiw a1, a1, -1347
; RV64I-NEXT: slli a1, a1, 12
; RV64I-NEXT: addi a1, a1, -529
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: seqz a0, a0
; RV64I-NEXT: ret
%1 = and i64 %a, 4294967295
%2 = icmp eq i64 %1, 2309737967
%3 = zext i1 %2 to i64
ret i64 %3
}
define i64 @icmp_ne_zext_inreg_small_constant(i64 %a) nounwind {
; RV64I-LABEL: icmp_ne_zext_inreg_small_constant:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: snez a0, a0
; RV64I-NEXT: ret
%1 = and i64 %a, 4294967295
%2 = icmp ne i64 %1, 0
%3 = zext i1 %2 to i64
ret i64 %3
}
define i64 @icmp_ne_zext_inreg_large_constant(i64 %a) nounwind {
; RV64I-LABEL: icmp_ne_zext_inreg_large_constant:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: li a1, 1
; RV64I-NEXT: slli a1, a1, 32
; RV64I-NEXT: addi a1, a1, -2
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: snez a0, a0
; RV64I-NEXT: ret
%1 = and i64 %a, 4294967295
%2 = icmp ne i64 %1, 4294967294
%3 = zext i1 %2 to i64
ret i64 %3
}