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Differential D129555

[AMDGPU] SILowerControlFlow uses LiveIntervals
ClosedPublic

Authored by foad on Jul 12 2022, 3:26 AM.

Details

Reviewers
arsenm
Group Reviewers
Restricted Project
Commits
rG5d41fe076880: [AMDGPU] SILowerControlFlow uses LiveIntervals
Summary

The availability of LiveIntervals affects kill flags in the output, so
declare the use to avoid strange effects where the output of this pass
is different depending on what other passes are scheduled after it.

Diff Detail

Unit TestsFailed

TimeTest
60,040 msx64 debian > MLIR.Examples/standalone::test.toy
60,080 msx64 debian > ThreadSanitizer-x86_64.ThreadSanitizer-x86_64::restore_stack.cpp
60,050 msx64 debian > libFuzzer.libFuzzer::fuzzer-leak.test
60,040 msx64 debian > libFuzzer.libFuzzer::minimize_crash.test

Event Timeline

foad created this revision.Jul 12 2022, 3:26 AM
Herald added a project: Restricted Project. · View Herald TranscriptJul 12 2022, 3:26 AM
Herald added subscribers: kosarev, jsilvanus, kerbowa and 9 others. · View Herald Transcript
foad requested review of this revision.Jul 12 2022, 3:26 AM
Herald added a project: Restricted Project. · View Herald TranscriptJul 12 2022, 3:26 AM
Herald added subscribers: llvm-commits, wdng. · View Herald Transcript
foad mentioned this in D129208: [MachineVerifier] Try harder to verify LiveIntervals.Jul 12 2022, 3:36 AM
foad added a child revision: D129208: [MachineVerifier] Try harder to verify LiveIntervals.Jul 12 2022, 3:37 AM
Harbormaster completed remote builds in B174845: Diff 443904.Jul 12 2022, 4:57 AM
arsenm accepted this revision.Jul 12 2022, 7:21 AM
This revision is now accepted and ready to land.Jul 12 2022, 7:21 AM
This revision was landed with ongoing or failed builds.Jul 12 2022, 8:56 AM
Closed by commit rG5d41fe076880: [AMDGPU] SILowerControlFlow uses LiveIntervals (authored by foad). · Explain Why
This revision was automatically updated to reflect the committed changes.
foad added a commit: rG5d41fe076880: [AMDGPU] SILowerControlFlow uses LiveIntervals.

Revision Contents

PathSize
llvm/
lib/
Target/
AMDGPU/
1 line
test/
CodeGen/
AMDGPU/
16 lines

Diff 443904

llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp

Show First 20 Lines • Show All 142 Lines • ▼ Show 20 Linespublic:
bool runOnMachineFunction(MachineFunction &MF) override; bool runOnMachineFunction(MachineFunction &MF) override;
StringRef getPassName() const override { StringRef getPassName() const override {
return "SI Lower control flow pseudo instructions"; return "SI Lower control flow pseudo instructions";
} }
void getAnalysisUsage(AnalysisUsage &AU) const override { void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.addUsedIfAvailable<LiveIntervals>();
// Should preserve the same set that TwoAddressInstructions does. // Should preserve the same set that TwoAddressInstructions does.
AU.addPreserved<MachineDominatorTree>(); AU.addPreserved<MachineDominatorTree>();
AU.addPreserved<SlotIndexes>(); AU.addPreserved<SlotIndexes>();
AU.addPreserved<LiveIntervals>(); AU.addPreserved<LiveIntervals>();
AU.addPreservedID(LiveVariablesID); AU.addPreservedID(LiveVariablesID);
MachineFunctionPass::getAnalysisUsage(AU); MachineFunctionPass::getAnalysisUsage(AU);
} }
}; };
▲ Show 20 Lines • Show All 789 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/si-lower-control-flow.mir

Show All 24 Lines
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
; GCN-LABEL: name: preserve_undef_flag_si_if_src ; GCN-LABEL: name: preserve_undef_flag_si_if_src
; GCN: bb.0: ; GCN: bb.0:
; GCN-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) ; GCN-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; GCN-NEXT: {{ $}} ; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
; GCN-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY]], undef %1:sreg_64, implicit-def dead $scc ; GCN-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY]], undef %1:sreg_64, implicit-def dead $scc
; GCN-NEXT: [[S_XOR_B64_:%[0-9]+]]:sreg_64 = S_XOR_B64 [[S_AND_B64_]], [[COPY]], implicit-def dead $scc ; GCN-NEXT: dead %0:sreg_64 = S_XOR_B64 [[S_AND_B64_]], [[COPY]], implicit-def dead $scc
; GCN-NEXT: $exec = S_MOV_B64_term killed [[S_AND_B64_]] ; GCN-NEXT: $exec = S_MOV_B64_term [[S_AND_B64_]]
; GCN-NEXT: S_CBRANCH_EXECZ %bb.2, implicit $exec ; GCN-NEXT: S_CBRANCH_EXECZ %bb.2, implicit $exec
; GCN-NEXT: S_BRANCH %bb.1 ; GCN-NEXT: S_BRANCH %bb.1
; GCN-NEXT: {{ $}} ; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.1: ; GCN-NEXT: bb.1:
; GCN-NEXT: successors: %bb.2(0x80000000) ; GCN-NEXT: successors: %bb.2(0x80000000)
; GCN-NEXT: {{ $}} ; GCN-NEXT: {{ $}}
; GCN-NEXT: {{ $}} ; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.2: ; GCN-NEXT: bb.2:
Show All 23 Linesbody: |
; GCN-NEXT: liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31 ; GCN-NEXT: liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31
; GCN-NEXT: {{ $}} ; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GCN-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[COPY]], [[COPY1]], implicit $exec ; GCN-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[COPY]], [[COPY1]], implicit $exec
; GCN-NEXT: [[COPY2:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec ; GCN-NEXT: [[COPY2:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
; GCN-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY2]], [[V_CMP_EQ_U32_e64_]], implicit-def dead $scc ; GCN-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY2]], [[V_CMP_EQ_U32_e64_]], implicit-def dead $scc
; GCN-NEXT: [[S_XOR_B64_:%[0-9]+]]:sreg_64_xexec = S_XOR_B64 [[S_AND_B64_]], [[COPY2]], implicit-def dead $scc ; GCN-NEXT: [[S_XOR_B64_:%[0-9]+]]:sreg_64_xexec = S_XOR_B64 [[S_AND_B64_]], [[COPY2]], implicit-def dead $scc
; GCN-NEXT: $exec = S_MOV_B64_term killed [[S_AND_B64_]] ; GCN-NEXT: $exec = S_MOV_B64_term [[S_AND_B64_]]
; GCN-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term [[S_XOR_B64_]], implicit $exec ; GCN-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term [[S_XOR_B64_]], implicit $exec
; GCN-NEXT: S_CBRANCH_EXECZ %bb.1, implicit $exec ; GCN-NEXT: S_CBRANCH_EXECZ %bb.1, implicit $exec
; GCN-NEXT: S_BRANCH %bb.2 ; GCN-NEXT: S_BRANCH %bb.2
; GCN-NEXT: {{ $}} ; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.1: ; GCN-NEXT: bb.1:
; GCN-NEXT: successors: %bb.2(0x80000000) ; GCN-NEXT: successors: %bb.2(0x80000000)
; GCN-NEXT: {{ $}} ; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY3:%[0-9]+]]:sreg_64_xexec = COPY [[S_MOV_B64_term]] ; GCN-NEXT: [[COPY3:%[0-9]+]]:sreg_64_xexec = COPY [[S_MOV_B64_term]]
Show All 32 Linesbody: |
; GCN-NEXT: liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31, $sgpr4_sgpr5 ; GCN-NEXT: liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31, $sgpr4_sgpr5
; GCN-NEXT: {{ $}} ; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GCN-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[COPY]], [[COPY1]], implicit $exec ; GCN-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[COPY]], [[COPY1]], implicit $exec
; GCN-NEXT: [[COPY2:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec ; GCN-NEXT: [[COPY2:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
; GCN-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY2]], [[V_CMP_EQ_U32_e64_]], implicit-def dead $scc ; GCN-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY2]], [[V_CMP_EQ_U32_e64_]], implicit-def dead $scc
; GCN-NEXT: [[S_XOR_B64_:%[0-9]+]]:sreg_64_xexec = S_XOR_B64 [[S_AND_B64_]], [[COPY2]], implicit-def dead $scc ; GCN-NEXT: [[S_XOR_B64_:%[0-9]+]]:sreg_64_xexec = S_XOR_B64 [[S_AND_B64_]], [[COPY2]], implicit-def dead $scc
; GCN-NEXT: $exec = S_MOV_B64_term killed [[S_AND_B64_]] ; GCN-NEXT: $exec = S_MOV_B64_term [[S_AND_B64_]]
; GCN-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term [[S_XOR_B64_]], implicit $exec ; GCN-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term [[S_XOR_B64_]], implicit $exec
; GCN-NEXT: S_CBRANCH_EXECZ %bb.1, implicit $exec ; GCN-NEXT: S_CBRANCH_EXECZ %bb.1, implicit $exec
; GCN-NEXT: S_BRANCH %bb.2 ; GCN-NEXT: S_BRANCH %bb.2
; GCN-NEXT: {{ $}} ; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.1: ; GCN-NEXT: bb.1:
; GCN-NEXT: successors: %bb.3(0x80000000) ; GCN-NEXT: successors: %bb.3(0x80000000)
; GCN-NEXT: liveins: $vgpr0, $sgpr4_sgpr5 ; GCN-NEXT: liveins: $vgpr0, $sgpr4_sgpr5
; GCN-NEXT: {{ $}} ; GCN-NEXT: {{ $}}
▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Linesbody: |
; GCN-NEXT: liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31, $sgpr4_sgpr5, $sgpr8_sgpr9_sgpr10_sgpr11:0x0000000000000003 ; GCN-NEXT: liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31, $sgpr4_sgpr5, $sgpr8_sgpr9_sgpr10_sgpr11:0x0000000000000003
; GCN-NEXT: {{ $}} ; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GCN-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[COPY]], [[COPY1]], implicit $exec ; GCN-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[COPY]], [[COPY1]], implicit $exec
; GCN-NEXT: [[COPY2:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec ; GCN-NEXT: [[COPY2:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
; GCN-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY2]], [[V_CMP_EQ_U32_e64_]], implicit-def dead $scc ; GCN-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY2]], [[V_CMP_EQ_U32_e64_]], implicit-def dead $scc
; GCN-NEXT: [[S_XOR_B64_:%[0-9]+]]:sreg_64_xexec = S_XOR_B64 [[S_AND_B64_]], [[COPY2]], implicit-def dead $scc ; GCN-NEXT: [[S_XOR_B64_:%[0-9]+]]:sreg_64_xexec = S_XOR_B64 [[S_AND_B64_]], [[COPY2]], implicit-def dead $scc
; GCN-NEXT: $exec = S_MOV_B64_term killed [[S_AND_B64_]] ; GCN-NEXT: $exec = S_MOV_B64_term [[S_AND_B64_]]
; GCN-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term [[S_XOR_B64_]], implicit $exec ; GCN-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term [[S_XOR_B64_]], implicit $exec
; GCN-NEXT: S_CBRANCH_EXECZ %bb.1, implicit $exec ; GCN-NEXT: S_CBRANCH_EXECZ %bb.1, implicit $exec
; GCN-NEXT: S_BRANCH %bb.2 ; GCN-NEXT: S_BRANCH %bb.2
; GCN-NEXT: {{ $}} ; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.1: ; GCN-NEXT: bb.1:
; GCN-NEXT: successors: %bb.3(0x80000000) ; GCN-NEXT: successors: %bb.3(0x80000000)
; GCN-NEXT: liveins: $vgpr0, $sgpr4_sgpr5, $sgpr8_sgpr9_sgpr10_sgpr11:0x0000000000000003 ; GCN-NEXT: liveins: $vgpr0, $sgpr4_sgpr5, $sgpr8_sgpr9_sgpr10_sgpr11:0x0000000000000003
; GCN-NEXT: {{ $}} ; GCN-NEXT: {{ $}}
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Linesbody: |
; GCN-NEXT: liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31 ; GCN-NEXT: liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31
; GCN-NEXT: {{ $}} ; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GCN-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[COPY]], [[COPY1]], implicit $exec ; GCN-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[COPY]], [[COPY1]], implicit $exec
; GCN-NEXT: [[COPY2:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec ; GCN-NEXT: [[COPY2:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
; GCN-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY2]], [[V_CMP_EQ_U32_e64_]], implicit-def dead $scc ; GCN-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY2]], [[V_CMP_EQ_U32_e64_]], implicit-def dead $scc
; GCN-NEXT: [[S_XOR_B64_:%[0-9]+]]:sreg_64_xexec = S_XOR_B64 [[S_AND_B64_]], [[COPY2]], implicit-def dead $scc ; GCN-NEXT: [[S_XOR_B64_:%[0-9]+]]:sreg_64_xexec = S_XOR_B64 [[S_AND_B64_]], [[COPY2]], implicit-def dead $scc
; GCN-NEXT: $exec = S_MOV_B64_term killed [[S_AND_B64_]] ; GCN-NEXT: $exec = S_MOV_B64_term [[S_AND_B64_]]
; GCN-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term [[S_XOR_B64_]], implicit $exec ; GCN-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term [[S_XOR_B64_]], implicit $exec
; GCN-NEXT: S_CBRANCH_EXECZ %bb.1, implicit $exec ; GCN-NEXT: S_CBRANCH_EXECZ %bb.1, implicit $exec
; GCN-NEXT: S_BRANCH %bb.2 ; GCN-NEXT: S_BRANCH %bb.2
; GCN-NEXT: {{ $}} ; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.1: ; GCN-NEXT: bb.1:
; GCN-NEXT: successors: %bb.3(0x80000000) ; GCN-NEXT: successors: %bb.3(0x80000000)
; GCN-NEXT: {{ $}} ; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY3:%[0-9]+]]:sreg_64_xexec = COPY [[S_MOV_B64_term]] ; GCN-NEXT: [[COPY3:%[0-9]+]]:sreg_64_xexec = COPY [[S_MOV_B64_term]]
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Linesbody: |
; GCN-NEXT: liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31, $sgpr4_sgpr5 ; GCN-NEXT: liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31, $sgpr4_sgpr5
; GCN-NEXT: {{ $}} ; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GCN-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[COPY]], [[COPY1]], implicit $exec ; GCN-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[COPY]], [[COPY1]], implicit $exec
; GCN-NEXT: [[COPY2:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec ; GCN-NEXT: [[COPY2:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
; GCN-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY2]], [[V_CMP_EQ_U32_e64_]], implicit-def dead $scc ; GCN-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY2]], [[V_CMP_EQ_U32_e64_]], implicit-def dead $scc
; GCN-NEXT: [[S_XOR_B64_:%[0-9]+]]:sreg_64_xexec = S_XOR_B64 [[S_AND_B64_]], [[COPY2]], implicit-def dead $scc ; GCN-NEXT: [[S_XOR_B64_:%[0-9]+]]:sreg_64_xexec = S_XOR_B64 [[S_AND_B64_]], [[COPY2]], implicit-def dead $scc
; GCN-NEXT: $exec = S_MOV_B64_term killed [[S_AND_B64_]] ; GCN-NEXT: $exec = S_MOV_B64_term [[S_AND_B64_]]
; GCN-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term [[S_XOR_B64_]], implicit $exec ; GCN-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term [[S_XOR_B64_]], implicit $exec
; GCN-NEXT: S_CBRANCH_EXECZ %bb.1, implicit $exec ; GCN-NEXT: S_CBRANCH_EXECZ %bb.1, implicit $exec
; GCN-NEXT: S_BRANCH %bb.2 ; GCN-NEXT: S_BRANCH %bb.2
; GCN-NEXT: {{ $}} ; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.1: ; GCN-NEXT: bb.1:
; GCN-NEXT: successors: %bb.3(0x80000000) ; GCN-NEXT: successors: %bb.3(0x80000000)
; GCN-NEXT: liveins: $vgpr0, $sgpr4_sgpr5 ; GCN-NEXT: liveins: $vgpr0, $sgpr4_sgpr5
; GCN-NEXT: {{ $}} ; GCN-NEXT: {{ $}}
▲ Show 20 Lines • Show All 61 Lines • ▼ Show 20 Linesbody: |
; GCN-NEXT: $exec = S_OR_B64_term $exec, [[COPY3]], implicit-def $scc ; GCN-NEXT: $exec = S_OR_B64_term $exec, [[COPY3]], implicit-def $scc
; GCN-NEXT: {{ $}} ; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.3: ; GCN-NEXT: bb.3:
; GCN-NEXT: successors: %bb.2(0x80000000) ; GCN-NEXT: successors: %bb.2(0x80000000)
; GCN-NEXT: {{ $}} ; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY4:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec ; GCN-NEXT: [[COPY4:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
; GCN-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY4]], [[V_CMP_EQ_U32_e64_1]], implicit-def dead $scc ; GCN-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY4]], [[V_CMP_EQ_U32_e64_1]], implicit-def dead $scc
; GCN-NEXT: [[S_XOR_B64_:%[0-9]+]]:sreg_64_xexec = S_XOR_B64 [[S_AND_B64_]], [[COPY4]], implicit-def dead $scc ; GCN-NEXT: [[S_XOR_B64_:%[0-9]+]]:sreg_64_xexec = S_XOR_B64 [[S_AND_B64_]], [[COPY4]], implicit-def dead $scc
; GCN-NEXT: $exec = S_MOV_B64_term killed [[S_AND_B64_]] ; GCN-NEXT: $exec = S_MOV_B64_term [[S_AND_B64_]]
; GCN-NEXT: dead %8:sreg_64_xexec = S_MOV_B64_term [[S_XOR_B64_]], implicit $exec ; GCN-NEXT: dead %8:sreg_64_xexec = S_MOV_B64_term [[S_XOR_B64_]], implicit $exec
; GCN-NEXT: S_CBRANCH_EXECZ %bb.2, implicit $exec ; GCN-NEXT: S_CBRANCH_EXECZ %bb.2, implicit $exec
; GCN-NEXT: {{ $}} ; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.2: ; GCN-NEXT: bb.2:
; GCN-NEXT: S_ENDPGM 0 ; GCN-NEXT: S_ENDPGM 0
bb.0: bb.0:
liveins: $vgpr0, $vgpr1, $vgpr2 liveins: $vgpr0, $vgpr1, $vgpr2
Show All 19 Lines